1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
19 #include "PPCRegisterInfo.h"
20 #include "PPCSubtarget.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/Target/TargetLowering.h"
27 // Start the numbering where the builtin ops and target ops leave off.
28 FIRST_NUMBER = ISD::BUILTIN_OP_END,
30 /// FSEL - Traditional three-operand fsel node.
34 /// FCFID - The FCFID instruction, taking an f64 operand and producing
35 /// and f64 value containing the FP representation of the integer that
36 /// was temporarily in the f64 operand.
39 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
40 /// unsigned integers and single-precision outputs.
41 FCFIDU, FCFIDS, FCFIDUS,
43 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
44 /// operand, producing an f64 value containing the integer representation
48 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
49 /// unsigned integers.
52 /// Reciprocal estimate instructions (unary FP ops).
55 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
56 // three v4f32 operands and producing a v4f32 result.
59 /// VPERM - The PPC VPERM Instruction.
63 /// Hi/Lo - These represent the high and low 16-bit parts of a global
64 /// address respectively. These nodes have two operands, the first of
65 /// which must be a TargetGlobalAddress, and the second of which must be a
66 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
67 /// though these are usually folded into other nodes.
72 /// The following three target-specific nodes are used for calls through
73 /// function pointers in the 64-bit SVR4 ABI.
75 /// Restore the TOC from the TOC save area of the current stack frame.
76 /// This is basically a hard coded load instruction which additionally
77 /// takes/produces a flag.
80 /// Like a regular LOAD but additionally taking/producing a flag.
83 /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is
84 /// a hard coded load instruction.
87 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
88 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
89 /// compute an allocation on the stack.
92 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
93 /// at function entry, used for PIC code.
96 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
97 /// shift amounts. These nodes are generated by the multi-precision shift
101 /// CALL - A direct function call.
102 /// CALL_NOP is a call with the special NOP which follows 64-bit
106 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
107 /// MTCTR instruction.
110 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
111 /// BCTRL instruction.
114 /// Return with a flag operand, matched by 'blr'
117 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCRpseud/MFOCRF
118 /// instructions. This copies the bits corresponding to the specified
119 /// CRREG into the resultant GPR. Bits corresponding to other CR regs
123 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
126 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
129 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
130 /// instructions. For lack of better number, we use the opcode number
131 /// encoding for the OPC field to identify the compare. For example, 838
135 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
136 /// altivec VCMP*o instructions. For lack of better number, we use the
137 /// opcode number encoding for the OPC field to identify the compare. For
138 /// example, 838 is VCMPGTSH.
141 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
142 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
143 /// condition register to branch on, OPC is the branch opcode to use (e.g.
144 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
145 /// an optional input flag argument.
148 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
149 /// towards zero. Used only as part of the long double-to-int
150 /// conversion sequence.
153 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
156 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
157 /// reserve indexed. This is used to implement atomic operations.
160 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
161 /// indexed. This is used to implement atomic operations.
164 /// TC_RETURN - A tail call return.
166 /// operand #1 callee (register or absolute)
167 /// operand #2 stack adjustment
168 /// operand #3 optional in flag
171 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
175 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
176 /// TLS model, produces an ADDIS8 instruction that adds the GOT
177 /// base to sym@got@tprel@ha.
180 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
181 /// TLS model, produces a LD instruction with base register G8RReg
182 /// and offset sym@got@tprel@l. This completes the addition that
183 /// finds the offset of "sym" relative to the thread pointer.
186 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
187 /// model, produces an ADD instruction that adds the contents of
188 /// G8RReg to the thread pointer. Symbol contains a relocation
189 /// sym@tls which is to be replaced by the thread pointer and
190 /// identifies to the linker that the instruction is part of a
194 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
195 /// model, produces an ADDIS8 instruction that adds the GOT base
196 /// register to sym@got@tlsgd@ha.
199 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
200 /// model, produces an ADDI8 instruction that adds G8RReg to
204 /// G8RC = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
205 /// model, produces a call to __tls_get_addr(sym@tlsgd).
208 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
209 /// model, produces an ADDIS8 instruction that adds the GOT base
210 /// register to sym@got@tlsld@ha.
213 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
214 /// model, produces an ADDI8 instruction that adds G8RReg to
218 /// G8RC = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
219 /// model, produces a call to __tls_get_addr(sym@tlsld).
222 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the
223 /// local-dynamic TLS model, produces an ADDIS8 instruction
224 /// that adds X3 to sym@dtprel@ha. The Chain operand is needed
225 /// to tie this in place following a copy to %X3 from the result
226 /// of a GET_TLSLD_ADDR.
229 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
230 /// model, produces an ADDI8 instruction that adds G8RReg to
231 /// sym@got@dtprel@l.
234 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
235 /// during instruction selection to optimize a BUILD_VECTOR into
236 /// operations on splats. This is necessary to avoid losing these
237 /// optimizations due to constant folding.
240 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
241 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
242 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
244 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
246 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
247 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
248 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
252 /// STFIWX - The STFIWX instruction. The first operand is an input token
253 /// chain, then an f64 value to store, then an address to store it to.
256 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
257 /// load which sign-extends from a 32-bit integer value into the
258 /// destination 64-bit register.
261 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
262 /// load which zero-extends from a 32-bit integer value into the
263 /// destination 64-bit register.
266 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model,
267 /// produces an ADDIS8 instruction that adds the TOC base register to
271 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model,
272 /// produces a LD instruction with base register G8RReg and offset
273 /// sym@toc@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
276 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
277 /// an ADDI8 instruction that adds G8RReg to sym@toc@l.
278 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
283 /// Define some predicates that are used for node matching.
285 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
286 /// VPKUHUM instruction.
287 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
289 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
290 /// VPKUWUM instruction.
291 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
293 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
294 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
295 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
298 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
299 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
300 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
303 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
304 /// amount, otherwise return -1.
305 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
307 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
308 /// specifies a splat of a single element that is suitable for input to
309 /// VSPLTB/VSPLTH/VSPLTW.
310 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
312 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
314 bool isAllNegativeZeroVector(SDNode *N);
316 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
317 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
318 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
320 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
321 /// formed by using a vspltis[bhw] instruction of the specified element
322 /// size, return the constant being splatted. The ByteSize field indicates
323 /// the number of bytes of each element [124] -> [bhw].
324 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
327 class PPCTargetLowering : public TargetLowering {
328 const PPCSubtarget &PPCSubTarget;
329 const PPCRegisterInfo *PPCRegInfo;
332 explicit PPCTargetLowering(PPCTargetMachine &TM);
334 /// getTargetNodeName() - This method returns the name of a target specific
336 virtual const char *getTargetNodeName(unsigned Opcode) const;
338 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
340 /// getSetCCResultType - Return the ISD::SETCC ValueType
341 virtual EVT getSetCCResultType(EVT VT) const;
343 /// getPreIndexedAddressParts - returns true by value, base pointer and
344 /// offset pointer and addressing mode by reference if the node's address
345 /// can be legally represented as pre-indexed load / store address.
346 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
348 ISD::MemIndexedMode &AM,
349 SelectionDAG &DAG) const;
351 /// SelectAddressRegReg - Given the specified addressed, check to see if it
352 /// can be represented as an indexed [r+r] operation. Returns false if it
353 /// can be more efficiently represented with [r+imm].
354 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
355 SelectionDAG &DAG) const;
357 /// SelectAddressRegImm - Returns true if the address N can be represented
358 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
359 /// is not better represented as reg+reg.
360 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
361 SelectionDAG &DAG) const;
363 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
364 /// represented as an indexed [r+r] operation.
365 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
366 SelectionDAG &DAG) const;
368 /// SelectAddressRegImmShift - Returns true if the address N can be
369 /// represented by a base register plus a signed 14-bit displacement
370 /// [r+imm*4]. Suitable for use by STD and friends.
371 bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
372 SelectionDAG &DAG) const;
374 Sched::Preference getSchedulingPreference(SDNode *N) const;
376 /// LowerOperation - Provide custom lowering hooks for some operations.
378 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
380 /// ReplaceNodeResults - Replace the results of node with an illegal result
381 /// type with new values built out of custom code.
383 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
384 SelectionDAG &DAG) const;
386 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
388 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
391 const SelectionDAG &DAG,
392 unsigned Depth = 0) const;
394 virtual MachineBasicBlock *
395 EmitInstrWithCustomInserter(MachineInstr *MI,
396 MachineBasicBlock *MBB) const;
397 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
398 MachineBasicBlock *MBB, bool is64Bit,
399 unsigned BinOpcode) const;
400 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
401 MachineBasicBlock *MBB,
402 bool is8bit, unsigned Opcode) const;
404 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
405 MachineBasicBlock *MBB) const;
407 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
408 MachineBasicBlock *MBB) const;
410 ConstraintType getConstraintType(const std::string &Constraint) const;
412 /// Examine constraint string and operand type and determine a weight value.
413 /// The operand object must already have been set up with the operand type.
414 ConstraintWeight getSingleConstraintMatchWeight(
415 AsmOperandInfo &info, const char *constraint) const;
417 std::pair<unsigned, const TargetRegisterClass*>
418 getRegForInlineAsmConstraint(const std::string &Constraint,
421 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
422 /// function arguments in the caller parameter area. This is the actual
423 /// alignment, not its logarithm.
424 unsigned getByValTypeAlignment(Type *Ty) const;
426 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
427 /// vector. If it is invalid, don't add anything to Ops.
428 virtual void LowerAsmOperandForConstraint(SDValue Op,
429 std::string &Constraint,
430 std::vector<SDValue> &Ops,
431 SelectionDAG &DAG) const;
433 /// isLegalAddressingMode - Return true if the addressing mode represented
434 /// by AM is legal for this target, for a load/store of the specified type.
435 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
437 /// isLegalAddressImmediate - Return true if the integer value can be used
438 /// as the offset of the target addressing mode for load / store of the
440 virtual bool isLegalAddressImmediate(int64_t V, Type *Ty) const;
442 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as
443 /// the offset of the target addressing mode.
444 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
446 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
448 /// getOptimalMemOpType - Returns the target specific optimal type for load
449 /// and store operations as a result of memset, memcpy, and memmove
450 /// lowering. If DstAlign is zero that means it's safe to destination
451 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
452 /// means there isn't a need to check it against alignment requirement,
453 /// probably because the source does not need to be loaded. If 'IsMemset' is
454 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
455 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
456 /// source is constant so it does not need to be loaded.
457 /// It returns EVT::Other if the type should be determined using generic
458 /// target-independent logic.
460 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
461 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
462 MachineFunction &MF) const;
464 /// Is unaligned memory access allowed for the given type, and is it fast
465 /// relative to software emulation.
466 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast = 0) const;
468 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
469 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
470 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
471 /// is expanded to mul + add.
472 virtual bool isFMAFasterThanMulAndAdd(EVT VT) const;
475 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
476 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
479 IsEligibleForTailCallOptimization(SDValue Callee,
480 CallingConv::ID CalleeCC,
482 const SmallVectorImpl<ISD::InputArg> &Ins,
483 SelectionDAG& DAG) const;
485 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
493 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
494 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
495 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
496 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
497 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
498 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
499 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
500 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
501 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
502 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
503 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
504 const PPCSubtarget &Subtarget) const;
505 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
506 const PPCSubtarget &Subtarget) const;
507 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
508 const PPCSubtarget &Subtarget) const;
509 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
510 const PPCSubtarget &Subtarget) const;
511 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
512 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl) const;
513 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
514 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
515 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
516 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
517 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
518 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
519 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
520 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
521 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
522 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
524 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
525 CallingConv::ID CallConv, bool isVarArg,
526 const SmallVectorImpl<ISD::InputArg> &Ins,
527 DebugLoc dl, SelectionDAG &DAG,
528 SmallVectorImpl<SDValue> &InVals) const;
529 SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall,
532 SmallVector<std::pair<unsigned, SDValue>, 8>
534 SDValue InFlag, SDValue Chain,
536 int SPDiff, unsigned NumBytes,
537 const SmallVectorImpl<ISD::InputArg> &Ins,
538 SmallVectorImpl<SDValue> &InVals) const;
541 LowerFormalArguments(SDValue Chain,
542 CallingConv::ID CallConv, bool isVarArg,
543 const SmallVectorImpl<ISD::InputArg> &Ins,
544 DebugLoc dl, SelectionDAG &DAG,
545 SmallVectorImpl<SDValue> &InVals) const;
548 LowerCall(TargetLowering::CallLoweringInfo &CLI,
549 SmallVectorImpl<SDValue> &InVals) const;
552 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
554 const SmallVectorImpl<ISD::OutputArg> &Outs,
555 LLVMContext &Context) const;
558 LowerReturn(SDValue Chain,
559 CallingConv::ID CallConv, bool isVarArg,
560 const SmallVectorImpl<ISD::OutputArg> &Outs,
561 const SmallVectorImpl<SDValue> &OutVals,
562 DebugLoc dl, SelectionDAG &DAG) const;
565 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
566 SDValue ArgVal, DebugLoc dl) const;
569 setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
570 unsigned nAltivecParamsAtEnd,
571 unsigned MinReservedArea, bool isPPC64) const;
574 LowerFormalArguments_Darwin(SDValue Chain,
575 CallingConv::ID CallConv, bool isVarArg,
576 const SmallVectorImpl<ISD::InputArg> &Ins,
577 DebugLoc dl, SelectionDAG &DAG,
578 SmallVectorImpl<SDValue> &InVals) const;
580 LowerFormalArguments_64SVR4(SDValue Chain,
581 CallingConv::ID CallConv, bool isVarArg,
582 const SmallVectorImpl<ISD::InputArg> &Ins,
583 DebugLoc dl, SelectionDAG &DAG,
584 SmallVectorImpl<SDValue> &InVals) const;
586 LowerFormalArguments_32SVR4(SDValue Chain,
587 CallingConv::ID CallConv, bool isVarArg,
588 const SmallVectorImpl<ISD::InputArg> &Ins,
589 DebugLoc dl, SelectionDAG &DAG,
590 SmallVectorImpl<SDValue> &InVals) const;
593 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
594 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
595 SelectionDAG &DAG, DebugLoc dl) const;
598 LowerCall_Darwin(SDValue Chain, SDValue Callee,
599 CallingConv::ID CallConv,
600 bool isVarArg, bool isTailCall,
601 const SmallVectorImpl<ISD::OutputArg> &Outs,
602 const SmallVectorImpl<SDValue> &OutVals,
603 const SmallVectorImpl<ISD::InputArg> &Ins,
604 DebugLoc dl, SelectionDAG &DAG,
605 SmallVectorImpl<SDValue> &InVals) const;
607 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
608 CallingConv::ID CallConv,
609 bool isVarArg, bool isTailCall,
610 const SmallVectorImpl<ISD::OutputArg> &Outs,
611 const SmallVectorImpl<SDValue> &OutVals,
612 const SmallVectorImpl<ISD::InputArg> &Ins,
613 DebugLoc dl, SelectionDAG &DAG,
614 SmallVectorImpl<SDValue> &InVals) const;
616 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
617 bool isVarArg, bool isTailCall,
618 const SmallVectorImpl<ISD::OutputArg> &Outs,
619 const SmallVectorImpl<SDValue> &OutVals,
620 const SmallVectorImpl<ISD::InputArg> &Ins,
621 DebugLoc dl, SelectionDAG &DAG,
622 SmallVectorImpl<SDValue> &InVals) const;
624 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
625 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
627 SDValue DAGCombineFastRecip(SDValue Op, DAGCombinerInfo &DCI) const;
628 SDValue DAGCombineFastRecipFSQRT(SDValue Op, DAGCombinerInfo &DCI) const;
632 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H