1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
19 #include "PPCInstrInfo.h"
20 #include "PPCRegisterInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetLowering.h"
28 // Start the numbering where the builtin ops and target ops leave off.
29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
31 /// FSEL - Traditional three-operand fsel node.
35 /// FCFID - The FCFID instruction, taking an f64 operand and producing
36 /// and f64 value containing the FP representation of the integer that
37 /// was temporarily in the f64 operand.
40 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
41 /// unsigned integers and single-precision outputs.
42 FCFIDU, FCFIDS, FCFIDUS,
44 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
45 /// operand, producing an f64 value containing the integer representation
49 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
50 /// unsigned integers.
53 /// Reciprocal estimate instructions (unary FP ops).
56 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
57 // three v4f32 operands and producing a v4f32 result.
60 /// VPERM - The PPC VPERM Instruction.
64 /// The CMPB instruction (takes two operands of i32 or i64).
67 /// Hi/Lo - These represent the high and low 16-bit parts of a global
68 /// address respectively. These nodes have two operands, the first of
69 /// which must be a TargetGlobalAddress, and the second of which must be a
70 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
71 /// though these are usually folded into other nodes.
74 /// The following two target-specific nodes are used for calls through
75 /// function pointers in the 64-bit SVR4 ABI.
77 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
78 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
79 /// compute an allocation on the stack.
82 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
83 /// at function entry, used for PIC code.
86 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
87 /// shift amounts. These nodes are generated by the multi-precision shift
91 /// The combination of sra[wd]i and addze used to implemented signed
92 /// integer division by a power of 2. The first operand is the dividend,
93 /// and the second is the constant shift amount (representing the
97 /// CALL - A direct function call.
98 /// CALL_NOP is a call with the special NOP which follows 64-bit
102 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
103 /// MTCTR instruction.
106 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
107 /// BCTRL instruction.
110 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
111 /// instruction and the TOC reload required on SVR4 PPC64.
114 /// Return with a flag operand, matched by 'blr'
117 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
118 /// This copies the bits corresponding to the specified CRREG into the
119 /// resultant GPR. Bits corresponding to other CR regs are undefined.
122 // FIXME: Remove these once the ANDI glue bug is fixed:
123 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
124 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
125 /// implement truncation of i32 or i64 to i1.
126 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
128 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
129 // target (returns (Lo, Hi)). It takes a chain operand.
132 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
135 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
138 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
139 /// instructions. For lack of better number, we use the opcode number
140 /// encoding for the OPC field to identify the compare. For example, 838
144 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
145 /// altivec VCMP*o instructions. For lack of better number, we use the
146 /// opcode number encoding for the OPC field to identify the compare. For
147 /// example, 838 is VCMPGTSH.
150 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
151 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
152 /// condition register to branch on, OPC is the branch opcode to use (e.g.
153 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
154 /// an optional input flag argument.
157 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
161 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
162 /// towards zero. Used only as part of the long double-to-int
163 /// conversion sequence.
166 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
169 /// TC_RETURN - A tail call return.
171 /// operand #1 callee (register or absolute)
172 /// operand #2 stack adjustment
173 /// operand #3 optional in flag
176 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
180 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
184 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
185 /// local dynamic TLS on PPC32.
188 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
189 /// TLS model, produces an ADDIS8 instruction that adds the GOT
190 /// base to sym\@got\@tprel\@ha.
193 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
194 /// TLS model, produces a LD instruction with base register G8RReg
195 /// and offset sym\@got\@tprel\@l. This completes the addition that
196 /// finds the offset of "sym" relative to the thread pointer.
199 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
200 /// model, produces an ADD instruction that adds the contents of
201 /// G8RReg to the thread pointer. Symbol contains a relocation
202 /// sym\@tls which is to be replaced by the thread pointer and
203 /// identifies to the linker that the instruction is part of a
207 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
208 /// model, produces an ADDIS8 instruction that adds the GOT base
209 /// register to sym\@got\@tlsgd\@ha.
212 /// %X3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
213 /// model, produces an ADDI8 instruction that adds G8RReg to
214 /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by
215 /// ADDIS_TLSGD_L_ADDR until after register assignment.
218 /// %X3 = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
219 /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by
220 /// ADDIS_TLSGD_L_ADDR until after register assignment.
223 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
224 /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following
225 /// register assignment.
228 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
229 /// model, produces an ADDIS8 instruction that adds the GOT base
230 /// register to sym\@got\@tlsld\@ha.
233 /// %X3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
234 /// model, produces an ADDI8 instruction that adds G8RReg to
235 /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by
236 /// ADDIS_TLSLD_L_ADDR until after register assignment.
239 /// %X3 = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
240 /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by
241 /// ADDIS_TLSLD_L_ADDR until after register assignment.
244 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
245 /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion
246 /// following register assignment.
249 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol - For the local-dynamic TLS
250 /// model, produces an ADDIS8 instruction that adds X3 to
254 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
255 /// model, produces an ADDI8 instruction that adds G8RReg to
256 /// sym\@got\@dtprel\@l.
259 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
260 /// during instruction selection to optimize a BUILD_VECTOR into
261 /// operations on splats. This is necessary to avoid losing these
262 /// optimizations due to constant folding.
265 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
266 /// operand identifies the operating system entry point.
269 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
270 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
271 /// or stxvd2x instruction. The chain is necessary because the
272 /// sequence replaces a load and needs to provide the same number
276 /// QVFPERM = This corresponds to the QPX qvfperm instruction.
279 /// QVGPCI = This corresponds to the QPX qvgpci instruction.
282 /// QVALIGNI = This corresponds to the QPX qvaligni instruction.
285 /// QVESPLATI = This corresponds to the QPX qvesplati instruction.
288 /// QBFLT = Access the underlying QPX floating-point boolean
292 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
293 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
294 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
296 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
298 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
299 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
300 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
304 /// STFIWX - The STFIWX instruction. The first operand is an input token
305 /// chain, then an f64 value to store, then an address to store it to.
308 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
309 /// load which sign-extends from a 32-bit integer value into the
310 /// destination 64-bit register.
313 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
314 /// load which zero-extends from a 32-bit integer value into the
315 /// destination 64-bit register.
318 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
319 /// Maps directly to an lxvd2x instruction that will be followed by
323 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
324 /// Maps directly to an stxvd2x instruction that will be preceded by
328 /// QBRC, CHAIN = QVLFSb CHAIN, Ptr
329 /// The 4xf32 load used for v4i1 constants.
332 /// GPRC = TOC_ENTRY GA, TOC
333 /// Loads the entry for GA from the TOC, where the TOC base is given by
334 /// the last operand.
339 /// Define some predicates that are used for node matching.
341 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
342 /// VPKUHUM instruction.
343 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
346 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
347 /// VPKUWUM instruction.
348 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
351 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
352 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
353 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
354 unsigned ShuffleKind, SelectionDAG &DAG);
356 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
357 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
358 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
359 unsigned ShuffleKind, SelectionDAG &DAG);
361 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
362 /// shift amount, otherwise return -1.
363 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
366 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
367 /// specifies a splat of a single element that is suitable for input to
368 /// VSPLTB/VSPLTH/VSPLTW.
369 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
371 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
372 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
373 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
375 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
376 /// formed by using a vspltis[bhw] instruction of the specified element
377 /// size, return the constant being splatted. The ByteSize field indicates
378 /// the number of bytes of each element [124] -> [bhw].
379 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
381 /// If this is a qvaligni shuffle mask, return the shift
382 /// amount, otherwise return -1.
383 int isQVALIGNIShuffleMask(SDNode *N);
386 class PPCTargetLowering : public TargetLowering {
387 const PPCSubtarget &Subtarget;
390 explicit PPCTargetLowering(const PPCTargetMachine &TM,
391 const PPCSubtarget &STI);
393 /// getTargetNodeName() - This method returns the name of a target specific
395 const char *getTargetNodeName(unsigned Opcode) const override;
397 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
399 bool isCheapToSpeculateCttz() const override {
403 bool isCheapToSpeculateCtlz() const override {
407 /// getSetCCResultType - Return the ISD::SETCC ValueType
408 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
410 /// Return true if target always beneficiates from combining into FMA for a
411 /// given value type. This must typically return false on targets where FMA
412 /// takes more cycles to execute than FADD.
413 bool enableAggressiveFMAFusion(EVT VT) const override;
415 /// getPreIndexedAddressParts - returns true by value, base pointer and
416 /// offset pointer and addressing mode by reference if the node's address
417 /// can be legally represented as pre-indexed load / store address.
418 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
420 ISD::MemIndexedMode &AM,
421 SelectionDAG &DAG) const override;
423 /// SelectAddressRegReg - Given the specified addressed, check to see if it
424 /// can be represented as an indexed [r+r] operation. Returns false if it
425 /// can be more efficiently represented with [r+imm].
426 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
427 SelectionDAG &DAG) const;
429 /// SelectAddressRegImm - Returns true if the address N can be represented
430 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
431 /// is not better represented as reg+reg. If Aligned is true, only accept
432 /// displacements suitable for STD and friends, i.e. multiples of 4.
433 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
434 SelectionDAG &DAG, bool Aligned) const;
436 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
437 /// represented as an indexed [r+r] operation.
438 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
439 SelectionDAG &DAG) const;
441 Sched::Preference getSchedulingPreference(SDNode *N) const override;
443 /// LowerOperation - Provide custom lowering hooks for some operations.
445 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
447 /// ReplaceNodeResults - Replace the results of node with an illegal result
448 /// type with new values built out of custom code.
450 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
451 SelectionDAG &DAG) const override;
453 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
454 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
456 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
458 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
459 std::vector<SDNode *> *Created) const override;
461 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
463 void computeKnownBitsForTargetNode(const SDValue Op,
466 const SelectionDAG &DAG,
467 unsigned Depth = 0) const override;
469 unsigned getPrefLoopAlignment(MachineLoop *ML) const override;
471 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
472 bool IsStore, bool IsLoad) const override;
473 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
474 bool IsStore, bool IsLoad) const override;
477 EmitInstrWithCustomInserter(MachineInstr *MI,
478 MachineBasicBlock *MBB) const override;
479 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
480 MachineBasicBlock *MBB,
482 unsigned BinOpcode) const;
483 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
484 MachineBasicBlock *MBB,
485 bool is8bit, unsigned Opcode) const;
487 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
488 MachineBasicBlock *MBB) const;
490 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
491 MachineBasicBlock *MBB) const;
494 getConstraintType(const std::string &Constraint) const override;
496 /// Examine constraint string and operand type and determine a weight value.
497 /// The operand object must already have been set up with the operand type.
498 ConstraintWeight getSingleConstraintMatchWeight(
499 AsmOperandInfo &info, const char *constraint) const override;
501 std::pair<unsigned, const TargetRegisterClass *>
502 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
503 const std::string &Constraint,
504 MVT VT) const override;
506 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
507 /// function arguments in the caller parameter area. This is the actual
508 /// alignment, not its logarithm.
509 unsigned getByValTypeAlignment(Type *Ty) const override;
511 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
512 /// vector. If it is invalid, don't add anything to Ops.
513 void LowerAsmOperandForConstraint(SDValue Op,
514 std::string &Constraint,
515 std::vector<SDValue> &Ops,
516 SelectionDAG &DAG) const override;
518 unsigned getInlineAsmMemConstraint(
519 const std::string &ConstraintCode) const override {
520 if (ConstraintCode == "es")
521 return InlineAsm::Constraint_es;
522 else if (ConstraintCode == "o")
523 return InlineAsm::Constraint_o;
524 else if (ConstraintCode == "Q")
525 return InlineAsm::Constraint_Q;
526 else if (ConstraintCode == "Z")
527 return InlineAsm::Constraint_Z;
528 else if (ConstraintCode == "Zy")
529 return InlineAsm::Constraint_Zy;
530 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
533 /// isLegalAddressingMode - Return true if the addressing mode represented
534 /// by AM is legal for this target, for a load/store of the specified type.
535 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
537 /// isLegalICmpImmediate - Return true if the specified immediate is legal
538 /// icmp immediate, that is the target has icmp instructions which can
539 /// compare a register against the immediate without having to materialize
540 /// the immediate into a register.
541 bool isLegalICmpImmediate(int64_t Imm) const override;
543 /// isLegalAddImmediate - Return true if the specified immediate is legal
544 /// add immediate, that is the target has add instructions which can
545 /// add a register and the immediate without having to materialize
546 /// the immediate into a register.
547 bool isLegalAddImmediate(int64_t Imm) const override;
549 /// isTruncateFree - Return true if it's free to truncate a value of
550 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
551 /// register X1 to i32 by referencing its sub-register R1.
552 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
553 bool isTruncateFree(EVT VT1, EVT VT2) const override;
555 bool isZExtFree(SDValue Val, EVT VT2) const override;
557 bool isFPExtFree(EVT VT) const override;
559 /// \brief Returns true if it is beneficial to convert a load of a constant
560 /// to just the constant itself.
561 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
562 Type *Ty) const override;
564 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
566 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
568 unsigned Intrinsic) const override;
570 /// getOptimalMemOpType - Returns the target specific optimal type for load
571 /// and store operations as a result of memset, memcpy, and memmove
572 /// lowering. If DstAlign is zero that means it's safe to destination
573 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
574 /// means there isn't a need to check it against alignment requirement,
575 /// probably because the source does not need to be loaded. If 'IsMemset' is
576 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
577 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
578 /// source is constant so it does not need to be loaded.
579 /// It returns EVT::Other if the type should be determined using generic
580 /// target-independent logic.
582 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
583 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
584 MachineFunction &MF) const override;
586 /// Is unaligned memory access allowed for the given type, and is it fast
587 /// relative to software emulation.
588 bool allowsMisalignedMemoryAccesses(EVT VT,
591 bool *Fast = nullptr) const override;
593 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
594 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
595 /// expanded to FMAs when this method returns true, otherwise fmuladd is
596 /// expanded to fmul + fadd.
597 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
599 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
601 // Should we expand the build vector with shuffles?
603 shouldExpandBuildVectorWithShuffles(EVT VT,
604 unsigned DefinedValues) const override;
606 /// createFastISel - This method returns a target-specific FastISel object,
607 /// or null if the target does not support "fast" instruction selection.
608 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
609 const TargetLibraryInfo *LibInfo) const override;
611 /// \brief Returns true if an argument of type Ty needs to be passed in a
612 /// contiguous block of registers in calling convention CallConv.
613 bool functionArgumentNeedsConsecutiveRegisters(
614 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
615 // We support any array type as "consecutive" block in the parameter
616 // save area. The element type defines the alignment requirement and
617 // whether the argument should go in GPRs, FPRs, or VRs if available.
619 // Note that clang uses this capability both to implement the ELFv2
620 // homogeneous float/vector aggregate ABI, and to avoid having to use
621 // "byval" when passing aggregates that might fully fit in registers.
622 return Ty->isArrayTy();
627 struct ReuseLoadInfo {
631 MachinePointerInfo MPI;
635 const MDNode *Ranges;
637 ReuseLoadInfo() : IsInvariant(false), Alignment(0), Ranges(nullptr) {}
640 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
642 ISD::LoadExtType ET = ISD::NON_EXTLOAD) const;
643 void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
644 SelectionDAG &DAG) const;
646 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
647 SelectionDAG &DAG, SDLoc dl) const;
649 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
650 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
653 IsEligibleForTailCallOptimization(SDValue Callee,
654 CallingConv::ID CalleeCC,
656 const SmallVectorImpl<ISD::InputArg> &Ins,
657 SelectionDAG& DAG) const;
659 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
667 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
668 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
669 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
670 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
671 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
672 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
673 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
674 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
675 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
676 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
677 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
678 const PPCSubtarget &Subtarget) const;
679 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
680 const PPCSubtarget &Subtarget) const;
681 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG,
682 const PPCSubtarget &Subtarget) const;
683 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
684 const PPCSubtarget &Subtarget) const;
685 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
686 const PPCSubtarget &Subtarget) const;
687 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
688 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
689 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
690 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
691 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const;
692 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
693 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
694 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
695 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
696 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
697 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
698 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
699 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
700 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
701 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
702 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
703 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
705 SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
706 SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
708 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
709 CallingConv::ID CallConv, bool isVarArg,
710 const SmallVectorImpl<ISD::InputArg> &Ins,
711 SDLoc dl, SelectionDAG &DAG,
712 SmallVectorImpl<SDValue> &InVals) const;
713 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall,
714 bool isVarArg, bool IsPatchPoint,
716 SmallVector<std::pair<unsigned, SDValue>, 8>
718 SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
720 int SPDiff, unsigned NumBytes,
721 const SmallVectorImpl<ISD::InputArg> &Ins,
722 SmallVectorImpl<SDValue> &InVals,
723 ImmutableCallSite *CS) const;
726 LowerFormalArguments(SDValue Chain,
727 CallingConv::ID CallConv, bool isVarArg,
728 const SmallVectorImpl<ISD::InputArg> &Ins,
729 SDLoc dl, SelectionDAG &DAG,
730 SmallVectorImpl<SDValue> &InVals) const override;
733 LowerCall(TargetLowering::CallLoweringInfo &CLI,
734 SmallVectorImpl<SDValue> &InVals) const override;
737 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
739 const SmallVectorImpl<ISD::OutputArg> &Outs,
740 LLVMContext &Context) const override;
743 LowerReturn(SDValue Chain,
744 CallingConv::ID CallConv, bool isVarArg,
745 const SmallVectorImpl<ISD::OutputArg> &Outs,
746 const SmallVectorImpl<SDValue> &OutVals,
747 SDLoc dl, SelectionDAG &DAG) const override;
750 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
751 SDValue ArgVal, SDLoc dl) const;
754 LowerFormalArguments_Darwin(SDValue Chain,
755 CallingConv::ID CallConv, bool isVarArg,
756 const SmallVectorImpl<ISD::InputArg> &Ins,
757 SDLoc dl, SelectionDAG &DAG,
758 SmallVectorImpl<SDValue> &InVals) const;
760 LowerFormalArguments_64SVR4(SDValue Chain,
761 CallingConv::ID CallConv, bool isVarArg,
762 const SmallVectorImpl<ISD::InputArg> &Ins,
763 SDLoc dl, SelectionDAG &DAG,
764 SmallVectorImpl<SDValue> &InVals) const;
766 LowerFormalArguments_32SVR4(SDValue Chain,
767 CallingConv::ID CallConv, bool isVarArg,
768 const SmallVectorImpl<ISD::InputArg> &Ins,
769 SDLoc dl, SelectionDAG &DAG,
770 SmallVectorImpl<SDValue> &InVals) const;
773 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
774 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
775 SelectionDAG &DAG, SDLoc dl) const;
778 LowerCall_Darwin(SDValue Chain, SDValue Callee,
779 CallingConv::ID CallConv,
780 bool isVarArg, bool isTailCall, bool IsPatchPoint,
781 const SmallVectorImpl<ISD::OutputArg> &Outs,
782 const SmallVectorImpl<SDValue> &OutVals,
783 const SmallVectorImpl<ISD::InputArg> &Ins,
784 SDLoc dl, SelectionDAG &DAG,
785 SmallVectorImpl<SDValue> &InVals,
786 ImmutableCallSite *CS) const;
788 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
789 CallingConv::ID CallConv,
790 bool isVarArg, bool isTailCall, bool IsPatchPoint,
791 const SmallVectorImpl<ISD::OutputArg> &Outs,
792 const SmallVectorImpl<SDValue> &OutVals,
793 const SmallVectorImpl<ISD::InputArg> &Ins,
794 SDLoc dl, SelectionDAG &DAG,
795 SmallVectorImpl<SDValue> &InVals,
796 ImmutableCallSite *CS) const;
798 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
799 bool isVarArg, bool isTailCall, bool IsPatchPoint,
800 const SmallVectorImpl<ISD::OutputArg> &Outs,
801 const SmallVectorImpl<SDValue> &OutVals,
802 const SmallVectorImpl<ISD::InputArg> &Ins,
803 SDLoc dl, SelectionDAG &DAG,
804 SmallVectorImpl<SDValue> &InVals,
805 ImmutableCallSite *CS) const;
807 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
808 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
810 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
811 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
812 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
814 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
815 unsigned &RefinementSteps,
816 bool &UseOneConstNR) const override;
817 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
818 unsigned &RefinementSteps) const override;
819 bool combineRepeatedFPDivisors(unsigned NumUsers) const override;
821 CCAssignFn *useFastISelCCs(unsigned Flag) const;
825 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
826 const TargetLibraryInfo *LibInfo);
829 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
830 CCValAssign::LocInfo &LocInfo,
831 ISD::ArgFlagsTy &ArgFlags,
834 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
836 CCValAssign::LocInfo &LocInfo,
837 ISD::ArgFlagsTy &ArgFlags,
840 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
842 CCValAssign::LocInfo &LocInfo,
843 ISD::ArgFlagsTy &ArgFlags,
847 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H