1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
19 #include "PPCRegisterInfo.h"
20 #include "PPCSubtarget.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/Target/TargetLowering.h"
27 // Start the numbering where the builtin ops and target ops leave off.
28 FIRST_NUMBER = ISD::BUILTIN_OP_END,
30 /// FSEL - Traditional three-operand fsel node.
34 /// FCFID - The FCFID instruction, taking an f64 operand and producing
35 /// and f64 value containing the FP representation of the integer that
36 /// was temporarily in the f64 operand.
39 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
40 /// operand, producing an f64 value containing the integer representation
44 /// STFIWX - The STFIWX instruction. The first operand is an input token
45 /// chain, then an f64 value to store, then an address to store it to.
48 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
49 // three v4f32 operands and producing a v4f32 result.
52 /// VPERM - The PPC VPERM Instruction.
56 /// Hi/Lo - These represent the high and low 16-bit parts of a global
57 /// address respectively. These nodes have two operands, the first of
58 /// which must be a TargetGlobalAddress, and the second of which must be a
59 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
60 /// though these are usually folded into other nodes.
65 /// The following three target-specific nodes are used for calls through
66 /// function pointers in the 64-bit SVR4 ABI.
68 /// Restore the TOC from the TOC save area of the current stack frame.
69 /// This is basically a hard coded load instruction which additionally
70 /// takes/produces a flag.
73 /// Like a regular LOAD but additionally taking/producing a flag.
76 /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is
77 /// a hard coded load instruction.
80 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
81 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
82 /// compute an allocation on the stack.
85 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
86 /// at function entry, used for PIC code.
89 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
90 /// shift amounts. These nodes are generated by the multi-precision shift
94 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
98 /// CALL - A direct function call.
99 /// CALL_NOP is a call with the special NOP which follows 64-bit
103 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
104 /// MTCTR instruction.
107 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
108 /// BCTRL instruction.
111 /// Return with a flag operand, matched by 'blr'
114 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCRpseud/MFOCRF
115 /// instructions. This copies the bits corresponding to the specified
116 /// CRREG into the resultant GPR. Bits corresponding to other CR regs
120 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
123 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
126 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
127 /// instructions. For lack of better number, we use the opcode number
128 /// encoding for the OPC field to identify the compare. For example, 838
132 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
133 /// altivec VCMP*o instructions. For lack of better number, we use the
134 /// opcode number encoding for the OPC field to identify the compare. For
135 /// example, 838 is VCMPGTSH.
138 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
139 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
140 /// condition register to branch on, OPC is the branch opcode to use (e.g.
141 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
142 /// an optional input flag argument.
145 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
146 /// towards zero. Used only as part of the long double-to-int
147 /// conversion sequence.
150 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
153 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
154 /// reserve indexed. This is used to implement atomic operations.
157 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
158 /// indexed. This is used to implement atomic operations.
161 /// TC_RETURN - A tail call return.
163 /// operand #1 callee (register or absolute)
164 /// operand #2 stack adjustment
165 /// operand #3 optional in flag
168 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
172 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
173 /// TLS model, produces an ADDIS8 instruction that adds the GOT
174 /// base to sym@got@tprel@ha.
177 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
178 /// TLS model, produces a LD instruction with base register G8RReg
179 /// and offset sym@got@tprel@l. This completes the addition that
180 /// finds the offset of "sym" relative to the thread pointer.
183 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
184 /// model, produces an ADD instruction that adds the contents of
185 /// G8RReg to the thread pointer. Symbol contains a relocation
186 /// sym@tls which is to be replaced by the thread pointer and
187 /// identifies to the linker that the instruction is part of a
191 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
192 /// model, produces an ADDIS8 instruction that adds the GOT base
193 /// register to sym@got@tlsgd@ha.
196 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
197 /// model, produces an ADDI8 instruction that adds G8RReg to
201 /// G8RC = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
202 /// model, produces a call to __tls_get_addr(sym@tlsgd).
205 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
206 /// model, produces an ADDIS8 instruction that adds the GOT base
207 /// register to sym@got@tlsld@ha.
210 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
211 /// model, produces an ADDI8 instruction that adds G8RReg to
215 /// G8RC = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
216 /// model, produces a call to __tls_get_addr(sym@tlsld).
219 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the
220 /// local-dynamic TLS model, produces an ADDIS8 instruction
221 /// that adds X3 to sym@dtprel@ha. The Chain operand is needed
222 /// to tie this in place following a copy to %X3 from the result
223 /// of a GET_TLSLD_ADDR.
226 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
227 /// model, produces an ADDI8 instruction that adds G8RReg to
228 /// sym@got@dtprel@l.
231 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
232 /// during instruction selection to optimize a BUILD_VECTOR into
233 /// operations on splats. This is necessary to avoid losing these
234 /// optimizations due to constant folding.
237 /// STD_32 - This is the STD instruction for use with "32-bit" registers.
238 STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE,
240 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
241 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
242 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
246 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
247 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
248 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
252 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model,
253 /// produces an ADDIS8 instruction that adds the TOC base register to
257 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model,
258 /// produces a LD instruction with base register G8RReg and offset
259 /// sym@toc@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
262 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
263 /// an ADDI8 instruction that adds G8RReg to sym@toc@l.
264 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
269 /// Define some predicates that are used for node matching.
271 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
272 /// VPKUHUM instruction.
273 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
275 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
276 /// VPKUWUM instruction.
277 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
279 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
280 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
281 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
284 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
285 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
286 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
289 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
290 /// amount, otherwise return -1.
291 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
293 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
294 /// specifies a splat of a single element that is suitable for input to
295 /// VSPLTB/VSPLTH/VSPLTW.
296 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
298 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
300 bool isAllNegativeZeroVector(SDNode *N);
302 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
303 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
304 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
306 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
307 /// formed by using a vspltis[bhw] instruction of the specified element
308 /// size, return the constant being splatted. The ByteSize field indicates
309 /// the number of bytes of each element [124] -> [bhw].
310 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
313 class PPCTargetLowering : public TargetLowering {
314 const PPCSubtarget &PPCSubTarget;
315 const PPCRegisterInfo *PPCRegInfo;
318 explicit PPCTargetLowering(PPCTargetMachine &TM);
320 /// getTargetNodeName() - This method returns the name of a target specific
322 virtual const char *getTargetNodeName(unsigned Opcode) const;
324 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
326 /// getSetCCResultType - Return the ISD::SETCC ValueType
327 virtual EVT getSetCCResultType(EVT VT) const;
329 /// getPreIndexedAddressParts - returns true by value, base pointer and
330 /// offset pointer and addressing mode by reference if the node's address
331 /// can be legally represented as pre-indexed load / store address.
332 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
334 ISD::MemIndexedMode &AM,
335 SelectionDAG &DAG) const;
337 /// SelectAddressRegReg - Given the specified addressed, check to see if it
338 /// can be represented as an indexed [r+r] operation. Returns false if it
339 /// can be more efficiently represented with [r+imm].
340 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
341 SelectionDAG &DAG) const;
343 /// SelectAddressRegImm - Returns true if the address N can be represented
344 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
345 /// is not better represented as reg+reg.
346 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
347 SelectionDAG &DAG) const;
349 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
350 /// represented as an indexed [r+r] operation.
351 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
352 SelectionDAG &DAG) const;
354 /// SelectAddressRegImmShift - Returns true if the address N can be
355 /// represented by a base register plus a signed 14-bit displacement
356 /// [r+imm*4]. Suitable for use by STD and friends.
357 bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
358 SelectionDAG &DAG) const;
360 Sched::Preference getSchedulingPreference(SDNode *N) const;
362 /// LowerOperation - Provide custom lowering hooks for some operations.
364 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
366 /// ReplaceNodeResults - Replace the results of node with an illegal result
367 /// type with new values built out of custom code.
369 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
370 SelectionDAG &DAG) const;
372 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
374 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
377 const SelectionDAG &DAG,
378 unsigned Depth = 0) const;
380 virtual MachineBasicBlock *
381 EmitInstrWithCustomInserter(MachineInstr *MI,
382 MachineBasicBlock *MBB) const;
383 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
384 MachineBasicBlock *MBB, bool is64Bit,
385 unsigned BinOpcode) const;
386 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
387 MachineBasicBlock *MBB,
388 bool is8bit, unsigned Opcode) const;
390 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
391 MachineBasicBlock *MBB) const;
393 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
394 MachineBasicBlock *MBB) const;
396 ConstraintType getConstraintType(const std::string &Constraint) const;
398 /// Examine constraint string and operand type and determine a weight value.
399 /// The operand object must already have been set up with the operand type.
400 ConstraintWeight getSingleConstraintMatchWeight(
401 AsmOperandInfo &info, const char *constraint) const;
403 std::pair<unsigned, const TargetRegisterClass*>
404 getRegForInlineAsmConstraint(const std::string &Constraint,
407 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
408 /// function arguments in the caller parameter area. This is the actual
409 /// alignment, not its logarithm.
410 unsigned getByValTypeAlignment(Type *Ty) const;
412 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
413 /// vector. If it is invalid, don't add anything to Ops.
414 virtual void LowerAsmOperandForConstraint(SDValue Op,
415 std::string &Constraint,
416 std::vector<SDValue> &Ops,
417 SelectionDAG &DAG) const;
419 /// isLegalAddressingMode - Return true if the addressing mode represented
420 /// by AM is legal for this target, for a load/store of the specified type.
421 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
423 /// isLegalAddressImmediate - Return true if the integer value can be used
424 /// as the offset of the target addressing mode for load / store of the
426 virtual bool isLegalAddressImmediate(int64_t V, Type *Ty) const;
428 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as
429 /// the offset of the target addressing mode.
430 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
432 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
434 /// getOptimalMemOpType - Returns the target specific optimal type for load
435 /// and store operations as a result of memset, memcpy, and memmove
436 /// lowering. If DstAlign is zero that means it's safe to destination
437 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
438 /// means there isn't a need to check it against alignment requirement,
439 /// probably because the source does not need to be loaded. If 'IsMemset' is
440 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
441 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
442 /// source is constant so it does not need to be loaded.
443 /// It returns EVT::Other if the type should be determined using generic
444 /// target-independent logic.
446 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
447 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
448 MachineFunction &MF) const;
450 /// Is unaligned memory access allowed for the given type, and is it fast
451 /// relative to software emulation.
452 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast = 0) const;
454 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
455 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
456 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
457 /// is expanded to mul + add.
458 virtual bool isFMAFasterThanMulAndAdd(EVT VT) const;
461 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
462 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
465 IsEligibleForTailCallOptimization(SDValue Callee,
466 CallingConv::ID CalleeCC,
468 const SmallVectorImpl<ISD::InputArg> &Ins,
469 SelectionDAG& DAG) const;
471 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
479 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
480 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
481 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
482 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
483 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
484 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
485 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
486 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
487 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
488 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
489 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
490 const PPCSubtarget &Subtarget) const;
491 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
492 const PPCSubtarget &Subtarget) const;
493 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
494 const PPCSubtarget &Subtarget) const;
495 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
496 const PPCSubtarget &Subtarget) const;
497 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
498 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl) const;
499 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
500 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
501 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
502 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
503 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
504 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
505 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
506 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
507 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
508 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
510 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
511 CallingConv::ID CallConv, bool isVarArg,
512 const SmallVectorImpl<ISD::InputArg> &Ins,
513 DebugLoc dl, SelectionDAG &DAG,
514 SmallVectorImpl<SDValue> &InVals) const;
515 SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall,
518 SmallVector<std::pair<unsigned, SDValue>, 8>
520 SDValue InFlag, SDValue Chain,
522 int SPDiff, unsigned NumBytes,
523 const SmallVectorImpl<ISD::InputArg> &Ins,
524 SmallVectorImpl<SDValue> &InVals) const;
527 LowerFormalArguments(SDValue Chain,
528 CallingConv::ID CallConv, bool isVarArg,
529 const SmallVectorImpl<ISD::InputArg> &Ins,
530 DebugLoc dl, SelectionDAG &DAG,
531 SmallVectorImpl<SDValue> &InVals) const;
534 LowerCall(TargetLowering::CallLoweringInfo &CLI,
535 SmallVectorImpl<SDValue> &InVals) const;
538 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
540 const SmallVectorImpl<ISD::OutputArg> &Outs,
541 LLVMContext &Context) const;
544 LowerReturn(SDValue Chain,
545 CallingConv::ID CallConv, bool isVarArg,
546 const SmallVectorImpl<ISD::OutputArg> &Outs,
547 const SmallVectorImpl<SDValue> &OutVals,
548 DebugLoc dl, SelectionDAG &DAG) const;
551 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
552 SDValue ArgVal, DebugLoc dl) const;
555 setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
556 unsigned nAltivecParamsAtEnd,
557 unsigned MinReservedArea, bool isPPC64) const;
560 LowerFormalArguments_Darwin(SDValue Chain,
561 CallingConv::ID CallConv, bool isVarArg,
562 const SmallVectorImpl<ISD::InputArg> &Ins,
563 DebugLoc dl, SelectionDAG &DAG,
564 SmallVectorImpl<SDValue> &InVals) const;
566 LowerFormalArguments_64SVR4(SDValue Chain,
567 CallingConv::ID CallConv, bool isVarArg,
568 const SmallVectorImpl<ISD::InputArg> &Ins,
569 DebugLoc dl, SelectionDAG &DAG,
570 SmallVectorImpl<SDValue> &InVals) const;
572 LowerFormalArguments_32SVR4(SDValue Chain,
573 CallingConv::ID CallConv, bool isVarArg,
574 const SmallVectorImpl<ISD::InputArg> &Ins,
575 DebugLoc dl, SelectionDAG &DAG,
576 SmallVectorImpl<SDValue> &InVals) const;
579 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
580 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
581 SelectionDAG &DAG, DebugLoc dl) const;
584 LowerCall_Darwin(SDValue Chain, SDValue Callee,
585 CallingConv::ID CallConv,
586 bool isVarArg, bool isTailCall,
587 const SmallVectorImpl<ISD::OutputArg> &Outs,
588 const SmallVectorImpl<SDValue> &OutVals,
589 const SmallVectorImpl<ISD::InputArg> &Ins,
590 DebugLoc dl, SelectionDAG &DAG,
591 SmallVectorImpl<SDValue> &InVals) const;
593 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
594 CallingConv::ID CallConv,
595 bool isVarArg, bool isTailCall,
596 const SmallVectorImpl<ISD::OutputArg> &Outs,
597 const SmallVectorImpl<SDValue> &OutVals,
598 const SmallVectorImpl<ISD::InputArg> &Ins,
599 DebugLoc dl, SelectionDAG &DAG,
600 SmallVectorImpl<SDValue> &InVals) const;
602 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
603 bool isVarArg, bool isTailCall,
604 const SmallVectorImpl<ISD::OutputArg> &Outs,
605 const SmallVectorImpl<SDValue> &OutVals,
606 const SmallVectorImpl<ISD::InputArg> &Ins,
607 DebugLoc dl, SelectionDAG &DAG,
608 SmallVectorImpl<SDValue> &InVals) const;
610 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
611 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
615 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H