1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
43 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
45 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
46 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
49 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
51 // FIXME: Remove this once the bug has been fixed!
52 extern cl::opt<bool> ANDIGlueBug;
54 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
55 // If it isn't a Mach-O file then it's going to be a linux ELF
58 return new TargetLoweringObjectFileMachO();
60 return new PPC64LinuxTargetObjectFile();
63 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
64 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))),
65 Subtarget(*TM.getSubtargetImpl()) {
68 // Use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(true);
72 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
73 // arguments are at least 4/8 bytes aligned.
74 bool isPPC64 = Subtarget.isPPC64();
75 setMinStackArgumentAlignment(isPPC64 ? 8:4);
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
82 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // PowerPC has pre-inc load and store's.
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
100 if (Subtarget.useCRBits()) {
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
103 if (isPPC64 || Subtarget.hasFPCVT()) {
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
108 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
109 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
115 // PowerPC does not support direct load / store of condition registers
116 setOperationAction(ISD::LOAD, MVT::i1, Custom);
117 setOperationAction(ISD::STORE, MVT::i1, Custom);
119 // FIXME: Remove this once the ANDI glue bug is fixed:
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
125 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
127 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
128 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath &&
180 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget.hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath &&
185 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget.hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget.hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget.hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget.useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget.isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget.isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget.has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget.use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget.hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
405 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
407 // add/sub are legal for all supported vector VT's.
408 setOperationAction(ISD::ADD , VT, Legal);
409 setOperationAction(ISD::SUB , VT, Legal);
411 // We promote all shuffles to v16i8.
412 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
413 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
415 // We promote all non-typed operations to v4i32.
416 setOperationAction(ISD::AND , VT, Promote);
417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
418 setOperationAction(ISD::OR , VT, Promote);
419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
420 setOperationAction(ISD::XOR , VT, Promote);
421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
422 setOperationAction(ISD::LOAD , VT, Promote);
423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
424 setOperationAction(ISD::SELECT, VT, Promote);
425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
426 setOperationAction(ISD::STORE, VT, Promote);
427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
429 // No other operations are legal.
430 setOperationAction(ISD::MUL , VT, Expand);
431 setOperationAction(ISD::SDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UDIV, VT, Expand);
434 setOperationAction(ISD::UREM, VT, Expand);
435 setOperationAction(ISD::FDIV, VT, Expand);
436 setOperationAction(ISD::FREM, VT, Expand);
437 setOperationAction(ISD::FNEG, VT, Expand);
438 setOperationAction(ISD::FSQRT, VT, Expand);
439 setOperationAction(ISD::FLOG, VT, Expand);
440 setOperationAction(ISD::FLOG10, VT, Expand);
441 setOperationAction(ISD::FLOG2, VT, Expand);
442 setOperationAction(ISD::FEXP, VT, Expand);
443 setOperationAction(ISD::FEXP2, VT, Expand);
444 setOperationAction(ISD::FSIN, VT, Expand);
445 setOperationAction(ISD::FCOS, VT, Expand);
446 setOperationAction(ISD::FABS, VT, Expand);
447 setOperationAction(ISD::FPOWI, VT, Expand);
448 setOperationAction(ISD::FFLOOR, VT, Expand);
449 setOperationAction(ISD::FCEIL, VT, Expand);
450 setOperationAction(ISD::FTRUNC, VT, Expand);
451 setOperationAction(ISD::FRINT, VT, Expand);
452 setOperationAction(ISD::FNEARBYINT, VT, Expand);
453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
455 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
456 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
457 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
458 setOperationAction(ISD::UDIVREM, VT, Expand);
459 setOperationAction(ISD::SDIVREM, VT, Expand);
460 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
461 setOperationAction(ISD::FPOW, VT, Expand);
462 setOperationAction(ISD::BSWAP, VT, Expand);
463 setOperationAction(ISD::CTPOP, VT, Expand);
464 setOperationAction(ISD::CTLZ, VT, Expand);
465 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
466 setOperationAction(ISD::CTTZ, VT, Expand);
467 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
468 setOperationAction(ISD::VSELECT, VT, Expand);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
471 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
472 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
473 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
474 setTruncStoreAction(VT, InnerVT, Expand);
476 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
477 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
478 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
481 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
482 // with merges, splats, etc.
483 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
485 setOperationAction(ISD::AND , MVT::v4i32, Legal);
486 setOperationAction(ISD::OR , MVT::v4i32, Legal);
487 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
488 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
489 setOperationAction(ISD::SELECT, MVT::v4i32,
490 Subtarget.useCRBits() ? Legal : Expand);
491 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
492 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
493 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
494 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
495 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
496 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
497 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
498 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
499 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
501 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
502 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
503 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
504 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
506 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
507 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
509 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
510 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
511 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
514 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
515 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
516 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
518 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
519 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
521 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
522 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
524 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
526 // Altivec does not contain unordered floating-point compare instructions
527 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
528 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
529 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
530 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
531 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
532 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
534 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
535 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
537 if (Subtarget.hasVSX()) {
538 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
541 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
542 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
543 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
544 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
545 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
547 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
549 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
550 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
552 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
553 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
559 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
561 // Share the Altivec comparison restrictions.
562 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
563 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
564 setCondCodeAction(ISD::SETUGT, MVT::v2f64, Expand);
565 setCondCodeAction(ISD::SETUGE, MVT::v2f64, Expand);
566 setCondCodeAction(ISD::SETULT, MVT::v2f64, Expand);
567 setCondCodeAction(ISD::SETULE, MVT::v2f64, Expand);
569 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
570 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
572 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
573 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
575 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
577 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
579 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
580 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
582 // VSX v2i64 only supports non-arithmetic operations.
583 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
584 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
586 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
587 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
588 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
590 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
592 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
593 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
594 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
595 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
597 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
599 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
600 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
601 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
602 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
604 // Vector operation legalization checks the result type of
605 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
608 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
611 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
615 if (Subtarget.has64BitSupport()) {
616 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
617 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
620 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
621 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
622 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
623 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
625 setBooleanContents(ZeroOrOneBooleanContent);
626 // Altivec instructions set fields to all zeros or all ones.
627 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
630 setStackPointerRegisterToSaveRestore(PPC::X1);
631 setExceptionPointerRegister(PPC::X3);
632 setExceptionSelectorRegister(PPC::X4);
634 setStackPointerRegisterToSaveRestore(PPC::R1);
635 setExceptionPointerRegister(PPC::R3);
636 setExceptionSelectorRegister(PPC::R4);
639 // We have target-specific dag combine patterns for the following nodes:
640 setTargetDAGCombine(ISD::SINT_TO_FP);
641 setTargetDAGCombine(ISD::LOAD);
642 setTargetDAGCombine(ISD::STORE);
643 setTargetDAGCombine(ISD::BR_CC);
644 if (Subtarget.useCRBits())
645 setTargetDAGCombine(ISD::BRCOND);
646 setTargetDAGCombine(ISD::BSWAP);
647 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
649 setTargetDAGCombine(ISD::SIGN_EXTEND);
650 setTargetDAGCombine(ISD::ZERO_EXTEND);
651 setTargetDAGCombine(ISD::ANY_EXTEND);
653 if (Subtarget.useCRBits()) {
654 setTargetDAGCombine(ISD::TRUNCATE);
655 setTargetDAGCombine(ISD::SETCC);
656 setTargetDAGCombine(ISD::SELECT_CC);
659 // Use reciprocal estimates.
660 if (TM.Options.UnsafeFPMath) {
661 setTargetDAGCombine(ISD::FDIV);
662 setTargetDAGCombine(ISD::FSQRT);
665 // Darwin long double math library functions have $LDBL128 appended.
666 if (Subtarget.isDarwin()) {
667 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
668 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
669 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
670 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
671 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
672 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
673 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
674 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
675 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
676 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
679 // With 32 condition bits, we don't need to sink (and duplicate) compares
680 // aggressively in CodeGenPrep.
681 if (Subtarget.useCRBits())
682 setHasMultipleConditionRegisters();
684 setMinFunctionAlignment(2);
685 if (Subtarget.isDarwin())
686 setPrefFunctionAlignment(4);
688 if (isPPC64 && Subtarget.isJITCodeModel())
689 // Temporary workaround for the inability of PPC64 JIT to handle jump
691 setSupportJumpTables(false);
693 setInsertFencesForAtomic(true);
695 if (Subtarget.enableMachineScheduler())
696 setSchedulingPreference(Sched::Source);
698 setSchedulingPreference(Sched::Hybrid);
700 computeRegisterProperties();
702 // The Freescale cores does better with aggressive inlining of memcpy and
703 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
704 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
705 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
706 MaxStoresPerMemset = 32;
707 MaxStoresPerMemsetOptSize = 16;
708 MaxStoresPerMemcpy = 32;
709 MaxStoresPerMemcpyOptSize = 8;
710 MaxStoresPerMemmove = 32;
711 MaxStoresPerMemmoveOptSize = 8;
713 setPrefFunctionAlignment(4);
717 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
718 /// the desired ByVal argument alignment.
719 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
720 unsigned MaxMaxAlign) {
721 if (MaxAlign == MaxMaxAlign)
723 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
724 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
726 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
728 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
729 unsigned EltAlign = 0;
730 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
731 if (EltAlign > MaxAlign)
733 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
734 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
735 unsigned EltAlign = 0;
736 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
737 if (EltAlign > MaxAlign)
739 if (MaxAlign == MaxMaxAlign)
745 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
746 /// function arguments in the caller parameter area.
747 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
748 // Darwin passes everything on 4 byte boundary.
749 if (Subtarget.isDarwin())
752 // 16byte and wider vectors are passed on 16byte boundary.
753 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
754 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
755 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
756 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
760 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
762 default: return nullptr;
763 case PPCISD::FSEL: return "PPCISD::FSEL";
764 case PPCISD::FCFID: return "PPCISD::FCFID";
765 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
766 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
767 case PPCISD::FRE: return "PPCISD::FRE";
768 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
769 case PPCISD::STFIWX: return "PPCISD::STFIWX";
770 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
771 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
772 case PPCISD::VPERM: return "PPCISD::VPERM";
773 case PPCISD::Hi: return "PPCISD::Hi";
774 case PPCISD::Lo: return "PPCISD::Lo";
775 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
776 case PPCISD::LOAD: return "PPCISD::LOAD";
777 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
778 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
779 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
780 case PPCISD::SRL: return "PPCISD::SRL";
781 case PPCISD::SRA: return "PPCISD::SRA";
782 case PPCISD::SHL: return "PPCISD::SHL";
783 case PPCISD::CALL: return "PPCISD::CALL";
784 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
785 case PPCISD::MTCTR: return "PPCISD::MTCTR";
786 case PPCISD::BCTRL: return "PPCISD::BCTRL";
787 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
788 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
789 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
790 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
791 case PPCISD::VCMP: return "PPCISD::VCMP";
792 case PPCISD::VCMPo: return "PPCISD::VCMPo";
793 case PPCISD::LBRX: return "PPCISD::LBRX";
794 case PPCISD::STBRX: return "PPCISD::STBRX";
795 case PPCISD::LARX: return "PPCISD::LARX";
796 case PPCISD::STCX: return "PPCISD::STCX";
797 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
798 case PPCISD::BDNZ: return "PPCISD::BDNZ";
799 case PPCISD::BDZ: return "PPCISD::BDZ";
800 case PPCISD::MFFS: return "PPCISD::MFFS";
801 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
802 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
803 case PPCISD::CR6SET: return "PPCISD::CR6SET";
804 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
805 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
806 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
807 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
808 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
809 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
810 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
811 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
812 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
813 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
814 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
815 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
816 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
817 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
818 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
819 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
820 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
821 case PPCISD::SC: return "PPCISD::SC";
825 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
827 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
828 return VT.changeVectorElementTypeToInteger();
831 //===----------------------------------------------------------------------===//
832 // Node matching predicates, for use by the tblgen matching code.
833 //===----------------------------------------------------------------------===//
835 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
836 static bool isFloatingPointZero(SDValue Op) {
837 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
838 return CFP->getValueAPF().isZero();
839 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
840 // Maybe this has already been legalized into the constant pool?
841 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
842 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
843 return CFP->getValueAPF().isZero();
848 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
849 /// true if Op is undef or if it matches the specified value.
850 static bool isConstantOrUndef(int Op, int Val) {
851 return Op < 0 || Op == Val;
854 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
855 /// VPKUHUM instruction.
856 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
858 unsigned j = DAG.getTarget().getDataLayout()->isLittleEndian() ? 0 : 1;
860 for (unsigned i = 0; i != 16; ++i)
861 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j))
864 for (unsigned i = 0; i != 8; ++i)
865 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
866 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
872 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
873 /// VPKUWUM instruction.
874 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
877 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
885 for (unsigned i = 0; i != 16; i += 2)
886 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
887 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k))
890 for (unsigned i = 0; i != 8; i += 2)
891 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
892 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k) ||
893 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
894 !isConstantOrUndef(N->getMaskElt(i+9), i*2+k))
900 /// isVMerge - Common function, used to match vmrg* shuffles.
902 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
903 unsigned LHSStart, unsigned RHSStart) {
904 if (N->getValueType(0) != MVT::v16i8)
906 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
907 "Unsupported merge size!");
909 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
910 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
911 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
912 LHSStart+j+i*UnitSize) ||
913 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
914 RHSStart+j+i*UnitSize))
920 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
921 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
922 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
923 bool isUnary, SelectionDAG &DAG) {
924 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
926 return isVMerge(N, UnitSize, 0, 16);
927 return isVMerge(N, UnitSize, 0, 0);
930 return isVMerge(N, UnitSize, 8, 24);
931 return isVMerge(N, UnitSize, 8, 8);
935 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
936 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
937 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
938 bool isUnary, SelectionDAG &DAG) {
939 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
941 return isVMerge(N, UnitSize, 8, 24);
942 return isVMerge(N, UnitSize, 8, 8);
945 return isVMerge(N, UnitSize, 0, 16);
946 return isVMerge(N, UnitSize, 0, 0);
951 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
952 /// amount, otherwise return -1.
953 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG) {
954 if (N->getValueType(0) != MVT::v16i8)
957 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
959 // Find the first non-undef value in the shuffle mask.
961 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
964 if (i == 16) return -1; // all undef.
966 // Otherwise, check to see if the rest of the elements are consecutively
967 // numbered from this value.
968 unsigned ShiftAmt = SVOp->getMaskElt(i);
969 if (ShiftAmt < i) return -1;
971 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
976 // Check the rest of the elements to see if they are consecutive.
977 for (++i; i != 16; ++i)
978 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt - i))
981 // Check the rest of the elements to see if they are consecutive.
982 for (++i; i != 16; ++i)
983 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt - i) & 15))
987 } else { // Big Endian
992 // Check the rest of the elements to see if they are consecutive.
993 for (++i; i != 16; ++i)
994 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
997 // Check the rest of the elements to see if they are consecutive.
998 for (++i; i != 16; ++i)
999 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1006 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1007 /// specifies a splat of a single element that is suitable for input to
1008 /// VSPLTB/VSPLTH/VSPLTW.
1009 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1010 assert(N->getValueType(0) == MVT::v16i8 &&
1011 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1013 // This is a splat operation if each element of the permute is the same, and
1014 // if the value doesn't reference the second vector.
1015 unsigned ElementBase = N->getMaskElt(0);
1017 // FIXME: Handle UNDEF elements too!
1018 if (ElementBase >= 16)
1021 // Check that the indices are consecutive, in the case of a multi-byte element
1022 // splatted with a v16i8 mask.
1023 for (unsigned i = 1; i != EltSize; ++i)
1024 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1027 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1028 if (N->getMaskElt(i) < 0) continue;
1029 for (unsigned j = 0; j != EltSize; ++j)
1030 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1036 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1038 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1039 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1041 APInt APVal, APUndef;
1045 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1046 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1047 return CFP->getValueAPF().isNegZero();
1052 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1053 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1054 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1055 SelectionDAG &DAG) {
1056 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1057 assert(isSplatShuffleMask(SVOp, EltSize));
1058 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1059 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1061 return SVOp->getMaskElt(0) / EltSize;
1064 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1065 /// by using a vspltis[bhw] instruction of the specified element size, return
1066 /// the constant being splatted. The ByteSize field indicates the number of
1067 /// bytes of each element [124] -> [bhw].
1068 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1069 SDValue OpVal(nullptr, 0);
1071 // If ByteSize of the splat is bigger than the element size of the
1072 // build_vector, then we have a case where we are checking for a splat where
1073 // multiple elements of the buildvector are folded together into a single
1074 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1075 unsigned EltSize = 16/N->getNumOperands();
1076 if (EltSize < ByteSize) {
1077 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1078 SDValue UniquedVals[4];
1079 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1081 // See if all of the elements in the buildvector agree across.
1082 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1083 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1084 // If the element isn't a constant, bail fully out.
1085 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1088 if (!UniquedVals[i&(Multiple-1)].getNode())
1089 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1090 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1091 return SDValue(); // no match.
1094 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1095 // either constant or undef values that are identical for each chunk. See
1096 // if these chunks can form into a larger vspltis*.
1098 // Check to see if all of the leading entries are either 0 or -1. If
1099 // neither, then this won't fit into the immediate field.
1100 bool LeadingZero = true;
1101 bool LeadingOnes = true;
1102 for (unsigned i = 0; i != Multiple-1; ++i) {
1103 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1105 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1106 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1108 // Finally, check the least significant entry.
1110 if (!UniquedVals[Multiple-1].getNode())
1111 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1112 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1114 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1117 if (!UniquedVals[Multiple-1].getNode())
1118 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1119 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1120 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1121 return DAG.getTargetConstant(Val, MVT::i32);
1127 // Check to see if this buildvec has a single non-undef value in its elements.
1128 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1129 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1130 if (!OpVal.getNode())
1131 OpVal = N->getOperand(i);
1132 else if (OpVal != N->getOperand(i))
1136 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1138 unsigned ValSizeInBytes = EltSize;
1140 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1141 Value = CN->getZExtValue();
1142 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1143 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1144 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1147 // If the splat value is larger than the element value, then we can never do
1148 // this splat. The only case that we could fit the replicated bits into our
1149 // immediate field for would be zero, and we prefer to use vxor for it.
1150 if (ValSizeInBytes < ByteSize) return SDValue();
1152 // If the element value is larger than the splat value, cut it in half and
1153 // check to see if the two halves are equal. Continue doing this until we
1154 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1155 while (ValSizeInBytes > ByteSize) {
1156 ValSizeInBytes >>= 1;
1158 // If the top half equals the bottom half, we're still ok.
1159 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1160 (Value & ((1 << (8*ValSizeInBytes))-1)))
1164 // Properly sign extend the value.
1165 int MaskVal = SignExtend32(Value, ByteSize * 8);
1167 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1168 if (MaskVal == 0) return SDValue();
1170 // Finally, if this value fits in a 5 bit sext field, return it
1171 if (SignExtend32<5>(MaskVal) == MaskVal)
1172 return DAG.getTargetConstant(MaskVal, MVT::i32);
1176 //===----------------------------------------------------------------------===//
1177 // Addressing Mode Selection
1178 //===----------------------------------------------------------------------===//
1180 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1181 /// or 64-bit immediate, and if the value can be accurately represented as a
1182 /// sign extension from a 16-bit value. If so, this returns true and the
1184 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1185 if (!isa<ConstantSDNode>(N))
1188 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1189 if (N->getValueType(0) == MVT::i32)
1190 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1192 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1194 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1195 return isIntS16Immediate(Op.getNode(), Imm);
1199 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1200 /// can be represented as an indexed [r+r] operation. Returns false if it
1201 /// can be more efficiently represented with [r+imm].
1202 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1204 SelectionDAG &DAG) const {
1206 if (N.getOpcode() == ISD::ADD) {
1207 if (isIntS16Immediate(N.getOperand(1), imm))
1208 return false; // r+i
1209 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1210 return false; // r+i
1212 Base = N.getOperand(0);
1213 Index = N.getOperand(1);
1215 } else if (N.getOpcode() == ISD::OR) {
1216 if (isIntS16Immediate(N.getOperand(1), imm))
1217 return false; // r+i can fold it if we can.
1219 // If this is an or of disjoint bitfields, we can codegen this as an add
1220 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1222 APInt LHSKnownZero, LHSKnownOne;
1223 APInt RHSKnownZero, RHSKnownOne;
1224 DAG.computeKnownBits(N.getOperand(0),
1225 LHSKnownZero, LHSKnownOne);
1227 if (LHSKnownZero.getBoolValue()) {
1228 DAG.computeKnownBits(N.getOperand(1),
1229 RHSKnownZero, RHSKnownOne);
1230 // If all of the bits are known zero on the LHS or RHS, the add won't
1232 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1233 Base = N.getOperand(0);
1234 Index = N.getOperand(1);
1243 // If we happen to be doing an i64 load or store into a stack slot that has
1244 // less than a 4-byte alignment, then the frame-index elimination may need to
1245 // use an indexed load or store instruction (because the offset may not be a
1246 // multiple of 4). The extra register needed to hold the offset comes from the
1247 // register scavenger, and it is possible that the scavenger will need to use
1248 // an emergency spill slot. As a result, we need to make sure that a spill slot
1249 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1251 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1252 // FIXME: This does not handle the LWA case.
1256 // NOTE: We'll exclude negative FIs here, which come from argument
1257 // lowering, because there are no known test cases triggering this problem
1258 // using packed structures (or similar). We can remove this exclusion if
1259 // we find such a test case. The reason why this is so test-case driven is
1260 // because this entire 'fixup' is only to prevent crashes (from the
1261 // register scavenger) on not-really-valid inputs. For example, if we have:
1263 // %b = bitcast i1* %a to i64*
1264 // store i64* a, i64 b
1265 // then the store should really be marked as 'align 1', but is not. If it
1266 // were marked as 'align 1' then the indexed form would have been
1267 // instruction-selected initially, and the problem this 'fixup' is preventing
1268 // won't happen regardless.
1272 MachineFunction &MF = DAG.getMachineFunction();
1273 MachineFrameInfo *MFI = MF.getFrameInfo();
1275 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1279 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1280 FuncInfo->setHasNonRISpills();
1283 /// Returns true if the address N can be represented by a base register plus
1284 /// a signed 16-bit displacement [r+imm], and if it is not better
1285 /// represented as reg+reg. If Aligned is true, only accept displacements
1286 /// suitable for STD and friends, i.e. multiples of 4.
1287 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1290 bool Aligned) const {
1291 // FIXME dl should come from parent load or store, not from address
1293 // If this can be more profitably realized as r+r, fail.
1294 if (SelectAddressRegReg(N, Disp, Base, DAG))
1297 if (N.getOpcode() == ISD::ADD) {
1299 if (isIntS16Immediate(N.getOperand(1), imm) &&
1300 (!Aligned || (imm & 3) == 0)) {
1301 Disp = DAG.getTargetConstant(imm, N.getValueType());
1302 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1303 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1304 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1306 Base = N.getOperand(0);
1308 return true; // [r+i]
1309 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1310 // Match LOAD (ADD (X, Lo(G))).
1311 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1312 && "Cannot handle constant offsets yet!");
1313 Disp = N.getOperand(1).getOperand(0); // The global address.
1314 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1315 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1316 Disp.getOpcode() == ISD::TargetConstantPool ||
1317 Disp.getOpcode() == ISD::TargetJumpTable);
1318 Base = N.getOperand(0);
1319 return true; // [&g+r]
1321 } else if (N.getOpcode() == ISD::OR) {
1323 if (isIntS16Immediate(N.getOperand(1), imm) &&
1324 (!Aligned || (imm & 3) == 0)) {
1325 // If this is an or of disjoint bitfields, we can codegen this as an add
1326 // (for better address arithmetic) if the LHS and RHS of the OR are
1327 // provably disjoint.
1328 APInt LHSKnownZero, LHSKnownOne;
1329 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1331 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1332 // If all of the bits are known zero on the LHS or RHS, the add won't
1334 Base = N.getOperand(0);
1335 Disp = DAG.getTargetConstant(imm, N.getValueType());
1339 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1340 // Loading from a constant address.
1342 // If this address fits entirely in a 16-bit sext immediate field, codegen
1345 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1346 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1347 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1348 CN->getValueType(0));
1352 // Handle 32-bit sext immediates with LIS + addr mode.
1353 if ((CN->getValueType(0) == MVT::i32 ||
1354 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1355 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1356 int Addr = (int)CN->getZExtValue();
1358 // Otherwise, break this down into an LIS + disp.
1359 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1361 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1362 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1363 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1368 Disp = DAG.getTargetConstant(0, getPointerTy());
1369 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1370 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1371 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1374 return true; // [r+0]
1377 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1378 /// represented as an indexed [r+r] operation.
1379 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1381 SelectionDAG &DAG) const {
1382 // Check to see if we can easily represent this as an [r+r] address. This
1383 // will fail if it thinks that the address is more profitably represented as
1384 // reg+imm, e.g. where imm = 0.
1385 if (SelectAddressRegReg(N, Base, Index, DAG))
1388 // If the operand is an addition, always emit this as [r+r], since this is
1389 // better (for code size, and execution, as the memop does the add for free)
1390 // than emitting an explicit add.
1391 if (N.getOpcode() == ISD::ADD) {
1392 Base = N.getOperand(0);
1393 Index = N.getOperand(1);
1397 // Otherwise, do it the hard way, using R0 as the base register.
1398 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1404 /// getPreIndexedAddressParts - returns true by value, base pointer and
1405 /// offset pointer and addressing mode by reference if the node's address
1406 /// can be legally represented as pre-indexed load / store address.
1407 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1409 ISD::MemIndexedMode &AM,
1410 SelectionDAG &DAG) const {
1411 if (DisablePPCPreinc) return false;
1417 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1418 Ptr = LD->getBasePtr();
1419 VT = LD->getMemoryVT();
1420 Alignment = LD->getAlignment();
1421 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1422 Ptr = ST->getBasePtr();
1423 VT = ST->getMemoryVT();
1424 Alignment = ST->getAlignment();
1429 // PowerPC doesn't have preinc load/store instructions for vectors.
1433 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1435 // Common code will reject creating a pre-inc form if the base pointer
1436 // is a frame index, or if N is a store and the base pointer is either
1437 // the same as or a predecessor of the value being stored. Check for
1438 // those situations here, and try with swapped Base/Offset instead.
1441 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1444 SDValue Val = cast<StoreSDNode>(N)->getValue();
1445 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1450 std::swap(Base, Offset);
1456 // LDU/STU can only handle immediates that are a multiple of 4.
1457 if (VT != MVT::i64) {
1458 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1461 // LDU/STU need an address with at least 4-byte alignment.
1465 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1469 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1470 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1471 // sext i32 to i64 when addr mode is r+i.
1472 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1473 LD->getExtensionType() == ISD::SEXTLOAD &&
1474 isa<ConstantSDNode>(Offset))
1482 //===----------------------------------------------------------------------===//
1483 // LowerOperation implementation
1484 //===----------------------------------------------------------------------===//
1486 /// GetLabelAccessInfo - Return true if we should reference labels using a
1487 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1488 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1489 unsigned &LoOpFlags,
1490 const GlobalValue *GV = nullptr) {
1491 HiOpFlags = PPCII::MO_HA;
1492 LoOpFlags = PPCII::MO_LO;
1494 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1495 // non-darwin platform. We don't support PIC on other platforms yet.
1496 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1497 TM.getSubtarget<PPCSubtarget>().isDarwin();
1499 HiOpFlags |= PPCII::MO_PIC_FLAG;
1500 LoOpFlags |= PPCII::MO_PIC_FLAG;
1503 // If this is a reference to a global value that requires a non-lazy-ptr, make
1504 // sure that instruction lowering adds it.
1505 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1506 HiOpFlags |= PPCII::MO_NLP_FLAG;
1507 LoOpFlags |= PPCII::MO_NLP_FLAG;
1509 if (GV->hasHiddenVisibility()) {
1510 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1511 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1518 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1519 SelectionDAG &DAG) {
1520 EVT PtrVT = HiPart.getValueType();
1521 SDValue Zero = DAG.getConstant(0, PtrVT);
1524 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1525 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1527 // With PIC, the first instruction is actually "GR+hi(&G)".
1529 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1530 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1532 // Generate non-pic code that has direct accesses to the constant pool.
1533 // The address of the global is just (hi(&g)+lo(&g)).
1534 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1537 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1538 SelectionDAG &DAG) const {
1539 EVT PtrVT = Op.getValueType();
1540 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1541 const Constant *C = CP->getConstVal();
1543 // 64-bit SVR4 ABI code is always position-independent.
1544 // The actual address of the GlobalValue is stored in the TOC.
1545 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1546 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1547 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1548 DAG.getRegister(PPC::X2, MVT::i64));
1551 unsigned MOHiFlag, MOLoFlag;
1552 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1554 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1556 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1557 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1560 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1561 EVT PtrVT = Op.getValueType();
1562 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1564 // 64-bit SVR4 ABI code is always position-independent.
1565 // The actual address of the GlobalValue is stored in the TOC.
1566 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1567 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1568 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1569 DAG.getRegister(PPC::X2, MVT::i64));
1572 unsigned MOHiFlag, MOLoFlag;
1573 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1574 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1575 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1576 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1579 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1580 SelectionDAG &DAG) const {
1581 EVT PtrVT = Op.getValueType();
1583 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1585 unsigned MOHiFlag, MOLoFlag;
1586 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1587 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1588 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1589 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1592 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1593 SelectionDAG &DAG) const {
1595 // FIXME: TLS addresses currently use medium model code sequences,
1596 // which is the most useful form. Eventually support for small and
1597 // large models could be added if users need it, at the cost of
1598 // additional complexity.
1599 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1601 const GlobalValue *GV = GA->getGlobal();
1602 EVT PtrVT = getPointerTy();
1603 bool is64bit = Subtarget.isPPC64();
1605 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1607 if (Model == TLSModel::LocalExec) {
1608 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1609 PPCII::MO_TPREL_HA);
1610 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1611 PPCII::MO_TPREL_LO);
1612 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1613 is64bit ? MVT::i64 : MVT::i32);
1614 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1615 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1618 if (Model == TLSModel::InitialExec) {
1619 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1620 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1624 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1625 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1626 PtrVT, GOTReg, TGA);
1628 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1629 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1630 PtrVT, TGA, GOTPtr);
1631 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1634 if (Model == TLSModel::GeneralDynamic) {
1635 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1636 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1637 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1639 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1642 // We need a chain node, and don't have one handy. The underlying
1643 // call has no side effects, so using the function entry node
1645 SDValue Chain = DAG.getEntryNode();
1646 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1647 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1648 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1649 PtrVT, ParmReg, TGA);
1650 // The return value from GET_TLS_ADDR really is in X3 already, but
1651 // some hacks are needed here to tie everything together. The extra
1652 // copies dissolve during subsequent transforms.
1653 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1654 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1657 if (Model == TLSModel::LocalDynamic) {
1658 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1659 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1660 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1662 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1665 // We need a chain node, and don't have one handy. The underlying
1666 // call has no side effects, so using the function entry node
1668 SDValue Chain = DAG.getEntryNode();
1669 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1670 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1671 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1672 PtrVT, ParmReg, TGA);
1673 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1674 // some hacks are needed here to tie everything together. The extra
1675 // copies dissolve during subsequent transforms.
1676 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1677 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1678 Chain, ParmReg, TGA);
1679 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1682 llvm_unreachable("Unknown TLS model!");
1685 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1686 SelectionDAG &DAG) const {
1687 EVT PtrVT = Op.getValueType();
1688 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1690 const GlobalValue *GV = GSDN->getGlobal();
1692 // 64-bit SVR4 ABI code is always position-independent.
1693 // The actual address of the GlobalValue is stored in the TOC.
1694 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1695 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1696 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1697 DAG.getRegister(PPC::X2, MVT::i64));
1700 unsigned MOHiFlag, MOLoFlag;
1701 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1704 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1706 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1708 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1710 // If the global reference is actually to a non-lazy-pointer, we have to do an
1711 // extra load to get the address of the global.
1712 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1713 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1714 false, false, false, 0);
1718 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1719 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1722 if (Op.getValueType() == MVT::v2i64) {
1723 // When the operands themselves are v2i64 values, we need to do something
1724 // special because VSX has no underlying comparison operations for these.
1725 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1726 // Equality can be handled by casting to the legal type for Altivec
1727 // comparisons, everything else needs to be expanded.
1728 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1729 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1730 DAG.getSetCC(dl, MVT::v4i32,
1731 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1732 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1739 // We handle most of these in the usual way.
1743 // If we're comparing for equality to zero, expose the fact that this is
1744 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1745 // fold the new nodes.
1746 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1747 if (C->isNullValue() && CC == ISD::SETEQ) {
1748 EVT VT = Op.getOperand(0).getValueType();
1749 SDValue Zext = Op.getOperand(0);
1750 if (VT.bitsLT(MVT::i32)) {
1752 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1754 unsigned Log2b = Log2_32(VT.getSizeInBits());
1755 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1756 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1757 DAG.getConstant(Log2b, MVT::i32));
1758 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1760 // Leave comparisons against 0 and -1 alone for now, since they're usually
1761 // optimized. FIXME: revisit this when we can custom lower all setcc
1763 if (C->isAllOnesValue() || C->isNullValue())
1767 // If we have an integer seteq/setne, turn it into a compare against zero
1768 // by xor'ing the rhs with the lhs, which is faster than setting a
1769 // condition register, reading it back out, and masking the correct bit. The
1770 // normal approach here uses sub to do this instead of xor. Using xor exposes
1771 // the result to other bit-twiddling opportunities.
1772 EVT LHSVT = Op.getOperand(0).getValueType();
1773 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1774 EVT VT = Op.getValueType();
1775 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1777 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1782 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1783 const PPCSubtarget &Subtarget) const {
1784 SDNode *Node = Op.getNode();
1785 EVT VT = Node->getValueType(0);
1786 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1787 SDValue InChain = Node->getOperand(0);
1788 SDValue VAListPtr = Node->getOperand(1);
1789 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1792 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1795 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1796 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1798 InChain = GprIndex.getValue(1);
1800 if (VT == MVT::i64) {
1801 // Check if GprIndex is even
1802 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1803 DAG.getConstant(1, MVT::i32));
1804 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1805 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1806 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1807 DAG.getConstant(1, MVT::i32));
1808 // Align GprIndex to be even if it isn't
1809 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1813 // fpr index is 1 byte after gpr
1814 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1815 DAG.getConstant(1, MVT::i32));
1818 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1819 FprPtr, MachinePointerInfo(SV), MVT::i8,
1821 InChain = FprIndex.getValue(1);
1823 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1824 DAG.getConstant(8, MVT::i32));
1826 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1827 DAG.getConstant(4, MVT::i32));
1830 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1831 MachinePointerInfo(), false, false,
1833 InChain = OverflowArea.getValue(1);
1835 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1836 MachinePointerInfo(), false, false,
1838 InChain = RegSaveArea.getValue(1);
1840 // select overflow_area if index > 8
1841 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1842 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1844 // adjustment constant gpr_index * 4/8
1845 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1846 VT.isInteger() ? GprIndex : FprIndex,
1847 DAG.getConstant(VT.isInteger() ? 4 : 8,
1850 // OurReg = RegSaveArea + RegConstant
1851 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1854 // Floating types are 32 bytes into RegSaveArea
1855 if (VT.isFloatingPoint())
1856 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1857 DAG.getConstant(32, MVT::i32));
1859 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1860 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1861 VT.isInteger() ? GprIndex : FprIndex,
1862 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1865 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1866 VT.isInteger() ? VAListPtr : FprPtr,
1867 MachinePointerInfo(SV),
1868 MVT::i8, false, false, 0);
1870 // determine if we should load from reg_save_area or overflow_area
1871 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1873 // increase overflow_area by 4/8 if gpr/fpr > 8
1874 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1875 DAG.getConstant(VT.isInteger() ? 4 : 8,
1878 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1881 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1883 MachinePointerInfo(),
1884 MVT::i32, false, false, 0);
1886 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1887 false, false, false, 0);
1890 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1891 const PPCSubtarget &Subtarget) const {
1892 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1894 // We have to copy the entire va_list struct:
1895 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1896 return DAG.getMemcpy(Op.getOperand(0), Op,
1897 Op.getOperand(1), Op.getOperand(2),
1898 DAG.getConstant(12, MVT::i32), 8, false, true,
1899 MachinePointerInfo(), MachinePointerInfo());
1902 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1903 SelectionDAG &DAG) const {
1904 return Op.getOperand(0);
1907 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1908 SelectionDAG &DAG) const {
1909 SDValue Chain = Op.getOperand(0);
1910 SDValue Trmp = Op.getOperand(1); // trampoline
1911 SDValue FPtr = Op.getOperand(2); // nested function
1912 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1915 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1916 bool isPPC64 = (PtrVT == MVT::i64);
1918 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1921 TargetLowering::ArgListTy Args;
1922 TargetLowering::ArgListEntry Entry;
1924 Entry.Ty = IntPtrTy;
1925 Entry.Node = Trmp; Args.push_back(Entry);
1927 // TrampSize == (isPPC64 ? 48 : 40);
1928 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1929 isPPC64 ? MVT::i64 : MVT::i32);
1930 Args.push_back(Entry);
1932 Entry.Node = FPtr; Args.push_back(Entry);
1933 Entry.Node = Nest; Args.push_back(Entry);
1935 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1936 TargetLowering::CallLoweringInfo CLI(DAG);
1937 CLI.setDebugLoc(dl).setChain(Chain)
1938 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
1939 DAG.getExternalSymbol("__trampoline_setup", PtrVT), &Args, 0);
1941 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1942 return CallResult.second;
1945 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1946 const PPCSubtarget &Subtarget) const {
1947 MachineFunction &MF = DAG.getMachineFunction();
1948 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1952 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1953 // vastart just stores the address of the VarArgsFrameIndex slot into the
1954 // memory location argument.
1955 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1956 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1957 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1958 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1959 MachinePointerInfo(SV),
1963 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1964 // We suppose the given va_list is already allocated.
1967 // char gpr; /* index into the array of 8 GPRs
1968 // * stored in the register save area
1969 // * gpr=0 corresponds to r3,
1970 // * gpr=1 to r4, etc.
1972 // char fpr; /* index into the array of 8 FPRs
1973 // * stored in the register save area
1974 // * fpr=0 corresponds to f1,
1975 // * fpr=1 to f2, etc.
1977 // char *overflow_arg_area;
1978 // /* location on stack that holds
1979 // * the next overflow argument
1981 // char *reg_save_area;
1982 // /* where r3:r10 and f1:f8 (if saved)
1988 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1989 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1992 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1994 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1996 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1999 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2000 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2002 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2003 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2005 uint64_t FPROffset = 1;
2006 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2008 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2010 // Store first byte : number of int regs
2011 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2013 MachinePointerInfo(SV),
2014 MVT::i8, false, false, 0);
2015 uint64_t nextOffset = FPROffset;
2016 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2019 // Store second byte : number of float regs
2020 SDValue secondStore =
2021 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2022 MachinePointerInfo(SV, nextOffset), MVT::i8,
2024 nextOffset += StackOffset;
2025 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2027 // Store second word : arguments given on stack
2028 SDValue thirdStore =
2029 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2030 MachinePointerInfo(SV, nextOffset),
2032 nextOffset += FrameOffset;
2033 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2035 // Store third word : arguments given in registers
2036 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2037 MachinePointerInfo(SV, nextOffset),
2042 #include "PPCGenCallingConv.inc"
2044 // Function whose sole purpose is to kill compiler warnings
2045 // stemming from unused functions included from PPCGenCallingConv.inc.
2046 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2047 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2050 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2051 CCValAssign::LocInfo &LocInfo,
2052 ISD::ArgFlagsTy &ArgFlags,
2057 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2059 CCValAssign::LocInfo &LocInfo,
2060 ISD::ArgFlagsTy &ArgFlags,
2062 static const MCPhysReg ArgRegs[] = {
2063 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2064 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2066 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2068 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2070 // Skip one register if the first unallocated register has an even register
2071 // number and there are still argument registers available which have not been
2072 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2073 // need to skip a register if RegNum is odd.
2074 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2075 State.AllocateReg(ArgRegs[RegNum]);
2078 // Always return false here, as this function only makes sure that the first
2079 // unallocated register has an odd register number and does not actually
2080 // allocate a register for the current argument.
2084 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2086 CCValAssign::LocInfo &LocInfo,
2087 ISD::ArgFlagsTy &ArgFlags,
2089 static const MCPhysReg ArgRegs[] = {
2090 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2094 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2096 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2098 // If there is only one Floating-point register left we need to put both f64
2099 // values of a split ppc_fp128 value on the stack.
2100 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2101 State.AllocateReg(ArgRegs[RegNum]);
2104 // Always return false here, as this function only makes sure that the two f64
2105 // values a ppc_fp128 value is split into are both passed in registers or both
2106 // passed on the stack and does not actually allocate a register for the
2107 // current argument.
2111 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2113 static const MCPhysReg *GetFPR() {
2114 static const MCPhysReg FPR[] = {
2115 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2116 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2122 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2124 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2125 unsigned PtrByteSize) {
2126 unsigned ArgSize = ArgVT.getStoreSize();
2127 if (Flags.isByVal())
2128 ArgSize = Flags.getByValSize();
2129 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2135 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2136 CallingConv::ID CallConv, bool isVarArg,
2137 const SmallVectorImpl<ISD::InputArg>
2139 SDLoc dl, SelectionDAG &DAG,
2140 SmallVectorImpl<SDValue> &InVals)
2142 if (Subtarget.isSVR4ABI()) {
2143 if (Subtarget.isPPC64())
2144 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2147 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2150 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2156 PPCTargetLowering::LowerFormalArguments_32SVR4(
2158 CallingConv::ID CallConv, bool isVarArg,
2159 const SmallVectorImpl<ISD::InputArg>
2161 SDLoc dl, SelectionDAG &DAG,
2162 SmallVectorImpl<SDValue> &InVals) const {
2164 // 32-bit SVR4 ABI Stack Frame Layout:
2165 // +-----------------------------------+
2166 // +--> | Back chain |
2167 // | +-----------------------------------+
2168 // | | Floating-point register save area |
2169 // | +-----------------------------------+
2170 // | | General register save area |
2171 // | +-----------------------------------+
2172 // | | CR save word |
2173 // | +-----------------------------------+
2174 // | | VRSAVE save word |
2175 // | +-----------------------------------+
2176 // | | Alignment padding |
2177 // | +-----------------------------------+
2178 // | | Vector register save area |
2179 // | +-----------------------------------+
2180 // | | Local variable space |
2181 // | +-----------------------------------+
2182 // | | Parameter list area |
2183 // | +-----------------------------------+
2184 // | | LR save word |
2185 // | +-----------------------------------+
2186 // SP--> +--- | Back chain |
2187 // +-----------------------------------+
2190 // System V Application Binary Interface PowerPC Processor Supplement
2191 // AltiVec Technology Programming Interface Manual
2193 MachineFunction &MF = DAG.getMachineFunction();
2194 MachineFrameInfo *MFI = MF.getFrameInfo();
2195 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2197 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2198 // Potential tail calls could cause overwriting of argument stack slots.
2199 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2200 (CallConv == CallingConv::Fast));
2201 unsigned PtrByteSize = 4;
2203 // Assign locations to all of the incoming arguments.
2204 SmallVector<CCValAssign, 16> ArgLocs;
2205 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2206 getTargetMachine(), ArgLocs, *DAG.getContext());
2208 // Reserve space for the linkage area on the stack.
2209 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2211 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2213 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2214 CCValAssign &VA = ArgLocs[i];
2216 // Arguments stored in registers.
2217 if (VA.isRegLoc()) {
2218 const TargetRegisterClass *RC;
2219 EVT ValVT = VA.getValVT();
2221 switch (ValVT.getSimpleVT().SimpleTy) {
2223 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2226 RC = &PPC::GPRCRegClass;
2229 RC = &PPC::F4RCRegClass;
2232 if (Subtarget.hasVSX())
2233 RC = &PPC::VSFRCRegClass;
2235 RC = &PPC::F8RCRegClass;
2241 RC = &PPC::VRRCRegClass;
2245 RC = &PPC::VSHRCRegClass;
2249 // Transform the arguments stored in physical registers into virtual ones.
2250 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2251 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2252 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2254 if (ValVT == MVT::i1)
2255 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2257 InVals.push_back(ArgValue);
2259 // Argument stored in memory.
2260 assert(VA.isMemLoc());
2262 unsigned ArgSize = VA.getLocVT().getStoreSize();
2263 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2266 // Create load nodes to retrieve arguments from the stack.
2267 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2268 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2269 MachinePointerInfo(),
2270 false, false, false, 0));
2274 // Assign locations to all of the incoming aggregate by value arguments.
2275 // Aggregates passed by value are stored in the local variable space of the
2276 // caller's stack frame, right above the parameter list area.
2277 SmallVector<CCValAssign, 16> ByValArgLocs;
2278 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2279 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2281 // Reserve stack space for the allocations in CCInfo.
2282 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2284 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2286 // Area that is at least reserved in the caller of this function.
2287 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2289 // Set the size that is at least reserved in caller of this function. Tail
2290 // call optimized function's reserved stack space needs to be aligned so that
2291 // taking the difference between two stack areas will result in an aligned
2293 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2296 std::max(MinReservedArea,
2297 PPCFrameLowering::getMinCallFrameSize(false, false));
2299 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2300 getStackAlignment();
2301 unsigned AlignMask = TargetAlign-1;
2302 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2304 FI->setMinReservedArea(MinReservedArea);
2306 SmallVector<SDValue, 8> MemOps;
2308 // If the function takes variable number of arguments, make a frame index for
2309 // the start of the first vararg value... for expansion of llvm.va_start.
2311 static const MCPhysReg GPArgRegs[] = {
2312 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2313 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2315 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2317 static const MCPhysReg FPArgRegs[] = {
2318 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2321 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2323 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2325 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2328 // Make room for NumGPArgRegs and NumFPArgRegs.
2329 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2330 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2332 FuncInfo->setVarArgsStackOffset(
2333 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2334 CCInfo.getNextStackOffset(), true));
2336 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2337 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2339 // The fixed integer arguments of a variadic function are stored to the
2340 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2341 // the result of va_next.
2342 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2343 // Get an existing live-in vreg, or add a new one.
2344 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2346 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2348 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2349 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2350 MachinePointerInfo(), false, false, 0);
2351 MemOps.push_back(Store);
2352 // Increment the address by four for the next argument to store
2353 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2354 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2357 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2359 // The double arguments are stored to the VarArgsFrameIndex
2361 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2362 // Get an existing live-in vreg, or add a new one.
2363 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2365 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2367 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2368 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2369 MachinePointerInfo(), false, false, 0);
2370 MemOps.push_back(Store);
2371 // Increment the address by eight for the next argument to store
2372 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2374 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2378 if (!MemOps.empty())
2379 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2384 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2385 // value to MVT::i64 and then truncate to the correct register size.
2387 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2388 SelectionDAG &DAG, SDValue ArgVal,
2391 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2392 DAG.getValueType(ObjectVT));
2393 else if (Flags.isZExt())
2394 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2395 DAG.getValueType(ObjectVT));
2397 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2400 // Set the size that is at least reserved in caller of this function. Tail
2401 // call optimized functions' reserved stack space needs to be aligned so that
2402 // taking the difference between two stack areas will result in an aligned
2405 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2406 unsigned nAltivecParamsAtEnd,
2407 unsigned MinReservedArea,
2408 bool isPPC64) const {
2409 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2410 // Add the Altivec parameters at the end, if needed.
2411 if (nAltivecParamsAtEnd) {
2412 MinReservedArea = ((MinReservedArea+15)/16)*16;
2413 MinReservedArea += 16*nAltivecParamsAtEnd;
2416 std::max(MinReservedArea,
2417 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2418 unsigned TargetAlign
2419 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2420 getStackAlignment();
2421 unsigned AlignMask = TargetAlign-1;
2422 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2423 FI->setMinReservedArea(MinReservedArea);
2427 PPCTargetLowering::LowerFormalArguments_64SVR4(
2429 CallingConv::ID CallConv, bool isVarArg,
2430 const SmallVectorImpl<ISD::InputArg>
2432 SDLoc dl, SelectionDAG &DAG,
2433 SmallVectorImpl<SDValue> &InVals) const {
2434 // TODO: add description of PPC stack frame format, or at least some docs.
2436 MachineFunction &MF = DAG.getMachineFunction();
2437 MachineFrameInfo *MFI = MF.getFrameInfo();
2438 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2440 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2441 // Potential tail calls could cause overwriting of argument stack slots.
2442 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2443 (CallConv == CallingConv::Fast));
2444 unsigned PtrByteSize = 8;
2446 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2447 // Area that is at least reserved in caller of this function.
2448 unsigned MinReservedArea = ArgOffset;
2450 static const MCPhysReg GPR[] = {
2451 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2452 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2455 static const MCPhysReg *FPR = GetFPR();
2457 static const MCPhysReg VR[] = {
2458 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2459 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2461 static const MCPhysReg VSRH[] = {
2462 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2463 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2466 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2467 const unsigned Num_FPR_Regs = 13;
2468 const unsigned Num_VR_Regs = array_lengthof(VR);
2470 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2472 // Add DAG nodes to load the arguments or copy them out of registers. On
2473 // entry to a function on PPC, the arguments start after the linkage area,
2474 // although the first ones are often in registers.
2476 SmallVector<SDValue, 8> MemOps;
2477 unsigned nAltivecParamsAtEnd = 0;
2478 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2479 unsigned CurArgIdx = 0;
2480 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2482 bool needsLoad = false;
2483 EVT ObjectVT = Ins[ArgNo].VT;
2484 unsigned ObjSize = ObjectVT.getStoreSize();
2485 unsigned ArgSize = ObjSize;
2486 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2487 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2488 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2490 unsigned CurArgOffset = ArgOffset;
2492 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2493 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2494 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8 ||
2495 ObjectVT==MVT::v2f64 || ObjectVT==MVT::v2i64) {
2497 MinReservedArea = ((MinReservedArea+15)/16)*16;
2498 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2502 nAltivecParamsAtEnd++;
2504 // Calculate min reserved area.
2505 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2509 // FIXME the codegen can be much improved in some cases.
2510 // We do not have to keep everything in memory.
2511 if (Flags.isByVal()) {
2512 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2513 ObjSize = Flags.getByValSize();
2514 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2515 // Empty aggregate parameters do not take up registers. Examples:
2519 // etc. However, we have to provide a place-holder in InVals, so
2520 // pretend we have an 8-byte item at the current address for that
2523 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2524 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2525 InVals.push_back(FIN);
2529 unsigned BVAlign = Flags.getByValAlign();
2531 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
2532 CurArgOffset = ArgOffset;
2535 // All aggregates smaller than 8 bytes must be passed right-justified.
2536 if (ObjSize < PtrByteSize)
2537 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2538 // The value of the object is its address.
2539 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2540 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2541 InVals.push_back(FIN);
2544 if (GPR_idx != Num_GPR_Regs) {
2545 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2546 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2549 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2550 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2551 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2552 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2553 MachinePointerInfo(FuncArg),
2554 ObjType, false, false, 0);
2556 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2557 // store the whole register as-is to the parameter save area
2558 // slot. The address of the parameter was already calculated
2559 // above (InVals.push_back(FIN)) to be the right-justified
2560 // offset within the slot. For this store, we need a new
2561 // frame index that points at the beginning of the slot.
2562 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2563 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2564 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2565 MachinePointerInfo(FuncArg),
2569 MemOps.push_back(Store);
2572 // Whether we copied from a register or not, advance the offset
2573 // into the parameter save area by a full doubleword.
2574 ArgOffset += PtrByteSize;
2578 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2579 // Store whatever pieces of the object are in registers
2580 // to memory. ArgOffset will be the address of the beginning
2582 if (GPR_idx != Num_GPR_Regs) {
2584 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2585 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2586 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2587 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2588 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2589 MachinePointerInfo(FuncArg, j),
2591 MemOps.push_back(Store);
2593 ArgOffset += PtrByteSize;
2595 ArgOffset += ArgSize - j;
2602 switch (ObjectVT.getSimpleVT().SimpleTy) {
2603 default: llvm_unreachable("Unhandled argument type!");
2607 if (GPR_idx != Num_GPR_Regs) {
2608 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2609 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2611 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2612 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2613 // value to MVT::i64 and then truncate to the correct register size.
2614 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2619 ArgSize = PtrByteSize;
2626 // Every 8 bytes of argument space consumes one of the GPRs available for
2627 // argument passing.
2628 if (GPR_idx != Num_GPR_Regs) {
2631 if (FPR_idx != Num_FPR_Regs) {
2634 if (ObjectVT == MVT::f32)
2635 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2637 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2638 &PPC::VSFRCRegClass :
2639 &PPC::F8RCRegClass);
2641 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2645 ArgSize = PtrByteSize;
2656 // Note that vector arguments in registers don't reserve stack space,
2657 // except in varargs functions.
2658 if (VR_idx != Num_VR_Regs) {
2659 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2660 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2661 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2662 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2664 while ((ArgOffset % 16) != 0) {
2665 ArgOffset += PtrByteSize;
2666 if (GPR_idx != Num_GPR_Regs)
2670 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2674 // Vectors are aligned.
2675 ArgOffset = ((ArgOffset+15)/16)*16;
2676 CurArgOffset = ArgOffset;
2683 // We need to load the argument to a virtual register if we determined
2684 // above that we ran out of physical registers of the appropriate type.
2686 int FI = MFI->CreateFixedObject(ObjSize,
2687 CurArgOffset + (ArgSize - ObjSize),
2689 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2690 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2691 false, false, false, 0);
2694 InVals.push_back(ArgVal);
2697 // Set the size that is at least reserved in caller of this function. Tail
2698 // call optimized functions' reserved stack space needs to be aligned so that
2699 // taking the difference between two stack areas will result in an aligned
2701 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2703 // If the function takes variable number of arguments, make a frame index for
2704 // the start of the first vararg value... for expansion of llvm.va_start.
2706 int Depth = ArgOffset;
2708 FuncInfo->setVarArgsFrameIndex(
2709 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2710 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2712 // If this function is vararg, store any remaining integer argument regs
2713 // to their spots on the stack so that they may be loaded by deferencing the
2714 // result of va_next.
2715 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2716 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2717 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2718 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2719 MachinePointerInfo(), false, false, 0);
2720 MemOps.push_back(Store);
2721 // Increment the address by four for the next argument to store
2722 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2723 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2727 if (!MemOps.empty())
2728 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2734 PPCTargetLowering::LowerFormalArguments_Darwin(
2736 CallingConv::ID CallConv, bool isVarArg,
2737 const SmallVectorImpl<ISD::InputArg>
2739 SDLoc dl, SelectionDAG &DAG,
2740 SmallVectorImpl<SDValue> &InVals) const {
2741 // TODO: add description of PPC stack frame format, or at least some docs.
2743 MachineFunction &MF = DAG.getMachineFunction();
2744 MachineFrameInfo *MFI = MF.getFrameInfo();
2745 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2747 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2748 bool isPPC64 = PtrVT == MVT::i64;
2749 // Potential tail calls could cause overwriting of argument stack slots.
2750 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2751 (CallConv == CallingConv::Fast));
2752 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2754 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2755 // Area that is at least reserved in caller of this function.
2756 unsigned MinReservedArea = ArgOffset;
2758 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2759 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2760 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2762 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2763 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2764 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2767 static const MCPhysReg *FPR = GetFPR();
2769 static const MCPhysReg VR[] = {
2770 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2771 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2774 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2775 const unsigned Num_FPR_Regs = 13;
2776 const unsigned Num_VR_Regs = array_lengthof( VR);
2778 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2780 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2782 // In 32-bit non-varargs functions, the stack space for vectors is after the
2783 // stack space for non-vectors. We do not use this space unless we have
2784 // too many vectors to fit in registers, something that only occurs in
2785 // constructed examples:), but we have to walk the arglist to figure
2786 // that out...for the pathological case, compute VecArgOffset as the
2787 // start of the vector parameter area. Computing VecArgOffset is the
2788 // entire point of the following loop.
2789 unsigned VecArgOffset = ArgOffset;
2790 if (!isVarArg && !isPPC64) {
2791 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2793 EVT ObjectVT = Ins[ArgNo].VT;
2794 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2796 if (Flags.isByVal()) {
2797 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2798 unsigned ObjSize = Flags.getByValSize();
2800 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2801 VecArgOffset += ArgSize;
2805 switch(ObjectVT.getSimpleVT().SimpleTy) {
2806 default: llvm_unreachable("Unhandled argument type!");
2812 case MVT::i64: // PPC64
2814 // FIXME: We are guaranteed to be !isPPC64 at this point.
2815 // Does MVT::i64 apply?
2822 // Nothing to do, we're only looking at Nonvector args here.
2827 // We've found where the vector parameter area in memory is. Skip the
2828 // first 12 parameters; these don't use that memory.
2829 VecArgOffset = ((VecArgOffset+15)/16)*16;
2830 VecArgOffset += 12*16;
2832 // Add DAG nodes to load the arguments or copy them out of registers. On
2833 // entry to a function on PPC, the arguments start after the linkage area,
2834 // although the first ones are often in registers.
2836 SmallVector<SDValue, 8> MemOps;
2837 unsigned nAltivecParamsAtEnd = 0;
2838 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2839 unsigned CurArgIdx = 0;
2840 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2842 bool needsLoad = false;
2843 EVT ObjectVT = Ins[ArgNo].VT;
2844 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2845 unsigned ArgSize = ObjSize;
2846 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2847 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2848 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2850 unsigned CurArgOffset = ArgOffset;
2852 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2853 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2854 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2855 if (isVarArg || isPPC64) {
2856 MinReservedArea = ((MinReservedArea+15)/16)*16;
2857 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2860 } else nAltivecParamsAtEnd++;
2862 // Calculate min reserved area.
2863 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2867 // FIXME the codegen can be much improved in some cases.
2868 // We do not have to keep everything in memory.
2869 if (Flags.isByVal()) {
2870 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2871 ObjSize = Flags.getByValSize();
2872 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2873 // Objects of size 1 and 2 are right justified, everything else is
2874 // left justified. This means the memory address is adjusted forwards.
2875 if (ObjSize==1 || ObjSize==2) {
2876 CurArgOffset = CurArgOffset + (4 - ObjSize);
2878 // The value of the object is its address.
2879 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2880 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2881 InVals.push_back(FIN);
2882 if (ObjSize==1 || ObjSize==2) {
2883 if (GPR_idx != Num_GPR_Regs) {
2886 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2888 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2889 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2890 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2891 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2892 MachinePointerInfo(FuncArg),
2893 ObjType, false, false, 0);
2894 MemOps.push_back(Store);
2898 ArgOffset += PtrByteSize;
2902 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2903 // Store whatever pieces of the object are in registers
2904 // to memory. ArgOffset will be the address of the beginning
2906 if (GPR_idx != Num_GPR_Regs) {
2909 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2911 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2912 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2913 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2914 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2915 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2916 MachinePointerInfo(FuncArg, j),
2918 MemOps.push_back(Store);
2920 ArgOffset += PtrByteSize;
2922 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2929 switch (ObjectVT.getSimpleVT().SimpleTy) {
2930 default: llvm_unreachable("Unhandled argument type!");
2934 if (GPR_idx != Num_GPR_Regs) {
2935 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2936 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2938 if (ObjectVT == MVT::i1)
2939 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
2944 ArgSize = PtrByteSize;
2946 // All int arguments reserve stack space in the Darwin ABI.
2947 ArgOffset += PtrByteSize;
2951 case MVT::i64: // PPC64
2952 if (GPR_idx != Num_GPR_Regs) {
2953 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2954 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2956 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2957 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2958 // value to MVT::i64 and then truncate to the correct register size.
2959 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2964 ArgSize = PtrByteSize;
2966 // All int arguments reserve stack space in the Darwin ABI.
2972 // Every 4 bytes of argument space consumes one of the GPRs available for
2973 // argument passing.
2974 if (GPR_idx != Num_GPR_Regs) {
2976 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2979 if (FPR_idx != Num_FPR_Regs) {
2982 if (ObjectVT == MVT::f32)
2983 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2985 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2987 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2993 // All FP arguments reserve stack space in the Darwin ABI.
2994 ArgOffset += isPPC64 ? 8 : ObjSize;
3000 // Note that vector arguments in registers don't reserve stack space,
3001 // except in varargs functions.
3002 if (VR_idx != Num_VR_Regs) {
3003 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3004 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3006 while ((ArgOffset % 16) != 0) {
3007 ArgOffset += PtrByteSize;
3008 if (GPR_idx != Num_GPR_Regs)
3012 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3016 if (!isVarArg && !isPPC64) {
3017 // Vectors go after all the nonvectors.
3018 CurArgOffset = VecArgOffset;
3021 // Vectors are aligned.
3022 ArgOffset = ((ArgOffset+15)/16)*16;
3023 CurArgOffset = ArgOffset;
3031 // We need to load the argument to a virtual register if we determined above
3032 // that we ran out of physical registers of the appropriate type.
3034 int FI = MFI->CreateFixedObject(ObjSize,
3035 CurArgOffset + (ArgSize - ObjSize),
3037 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3038 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3039 false, false, false, 0);
3042 InVals.push_back(ArgVal);
3045 // Set the size that is at least reserved in caller of this function. Tail
3046 // call optimized functions' reserved stack space needs to be aligned so that
3047 // taking the difference between two stack areas will result in an aligned
3049 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
3051 // If the function takes variable number of arguments, make a frame index for
3052 // the start of the first vararg value... for expansion of llvm.va_start.
3054 int Depth = ArgOffset;
3056 FuncInfo->setVarArgsFrameIndex(
3057 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3059 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3061 // If this function is vararg, store any remaining integer argument regs
3062 // to their spots on the stack so that they may be loaded by deferencing the
3063 // result of va_next.
3064 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3068 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3070 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3072 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3073 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3074 MachinePointerInfo(), false, false, 0);
3075 MemOps.push_back(Store);
3076 // Increment the address by four for the next argument to store
3077 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3078 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3082 if (!MemOps.empty())
3083 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3088 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
3089 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
3091 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
3095 const SmallVectorImpl<ISD::OutputArg>
3097 const SmallVectorImpl<SDValue> &OutVals,
3098 unsigned &nAltivecParamsAtEnd) {
3099 // Count how many bytes are to be pushed on the stack, including the linkage
3100 // area, and parameter passing area. We start with 24/48 bytes, which is
3101 // prereserved space for [SP][CR][LR][3 x unused].
3102 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
3103 unsigned NumOps = Outs.size();
3104 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3106 // Add up all the space actually used.
3107 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
3108 // they all go in registers, but we must reserve stack space for them for
3109 // possible use by the caller. In varargs or 64-bit calls, parameters are
3110 // assigned stack space in order, with padding so Altivec parameters are
3112 nAltivecParamsAtEnd = 0;
3113 for (unsigned i = 0; i != NumOps; ++i) {
3114 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3115 EVT ArgVT = Outs[i].VT;
3116 // Varargs Altivec parameters are padded to a 16 byte boundary.
3117 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
3118 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8 ||
3119 ArgVT==MVT::v2f64 || ArgVT==MVT::v2i64) {
3120 if (!isVarArg && !isPPC64) {
3121 // Non-varargs Altivec parameters go after all the non-Altivec
3122 // parameters; handle those later so we know how much padding we need.
3123 nAltivecParamsAtEnd++;
3126 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
3127 NumBytes = ((NumBytes+15)/16)*16;
3129 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3132 // Allow for Altivec parameters at the end, if needed.
3133 if (nAltivecParamsAtEnd) {
3134 NumBytes = ((NumBytes+15)/16)*16;
3135 NumBytes += 16*nAltivecParamsAtEnd;
3138 // The prolog code of the callee may store up to 8 GPR argument registers to
3139 // the stack, allowing va_start to index over them in memory if its varargs.
3140 // Because we cannot tell if this is needed on the caller side, we have to
3141 // conservatively assume that it is needed. As such, make sure we have at
3142 // least enough stack space for the caller to store the 8 GPRs.
3143 NumBytes = std::max(NumBytes,
3144 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
3146 // Tail call needs the stack to be aligned.
3147 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
3148 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
3149 getFrameLowering()->getStackAlignment();
3150 unsigned AlignMask = TargetAlign-1;
3151 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
3157 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3158 /// adjusted to accommodate the arguments for the tailcall.
3159 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3160 unsigned ParamSize) {
3162 if (!isTailCall) return 0;
3164 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3165 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3166 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3167 // Remember only if the new adjustement is bigger.
3168 if (SPDiff < FI->getTailCallSPDelta())
3169 FI->setTailCallSPDelta(SPDiff);
3174 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3175 /// for tail call optimization. Targets which want to do tail call
3176 /// optimization should implement this function.
3178 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3179 CallingConv::ID CalleeCC,
3181 const SmallVectorImpl<ISD::InputArg> &Ins,
3182 SelectionDAG& DAG) const {
3183 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3186 // Variable argument functions are not supported.
3190 MachineFunction &MF = DAG.getMachineFunction();
3191 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3192 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3193 // Functions containing by val parameters are not supported.
3194 for (unsigned i = 0; i != Ins.size(); i++) {
3195 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3196 if (Flags.isByVal()) return false;
3199 // Non-PIC/GOT tail calls are supported.
3200 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3203 // At the moment we can only do local tail calls (in same module, hidden
3204 // or protected) if we are generating PIC.
3205 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3206 return G->getGlobal()->hasHiddenVisibility()
3207 || G->getGlobal()->hasProtectedVisibility();
3213 /// isCallCompatibleAddress - Return the immediate to use if the specified
3214 /// 32-bit value is representable in the immediate field of a BxA instruction.
3215 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3216 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3217 if (!C) return nullptr;
3219 int Addr = C->getZExtValue();
3220 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3221 SignExtend32<26>(Addr) != Addr)
3222 return nullptr; // Top 6 bits have to be sext of immediate.
3224 return DAG.getConstant((int)C->getZExtValue() >> 2,
3225 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3230 struct TailCallArgumentInfo {
3235 TailCallArgumentInfo() : FrameIdx(0) {}
3240 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3242 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3244 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3245 SmallVectorImpl<SDValue> &MemOpChains,
3247 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3248 SDValue Arg = TailCallArgs[i].Arg;
3249 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3250 int FI = TailCallArgs[i].FrameIdx;
3251 // Store relative to framepointer.
3252 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3253 MachinePointerInfo::getFixedStack(FI),
3258 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3259 /// the appropriate stack slot for the tail call optimized function call.
3260 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3261 MachineFunction &MF,
3270 // Calculate the new stack slot for the return address.
3271 int SlotSize = isPPC64 ? 8 : 4;
3272 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3274 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3275 NewRetAddrLoc, true);
3276 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3277 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3278 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3279 MachinePointerInfo::getFixedStack(NewRetAddr),
3282 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3283 // slot as the FP is never overwritten.
3286 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3287 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3289 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3290 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3291 MachinePointerInfo::getFixedStack(NewFPIdx),
3298 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3299 /// the position of the argument.
3301 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3302 SDValue Arg, int SPDiff, unsigned ArgOffset,
3303 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3304 int Offset = ArgOffset + SPDiff;
3305 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3306 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3307 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3308 SDValue FIN = DAG.getFrameIndex(FI, VT);
3309 TailCallArgumentInfo Info;
3311 Info.FrameIdxOp = FIN;
3313 TailCallArguments.push_back(Info);
3316 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3317 /// stack slot. Returns the chain as result and the loaded frame pointers in
3318 /// LROpOut/FPOpout. Used when tail calling.
3319 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3327 // Load the LR and FP stack slot for later adjusting.
3328 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3329 LROpOut = getReturnAddrFrameIndex(DAG);
3330 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3331 false, false, false, 0);
3332 Chain = SDValue(LROpOut.getNode(), 1);
3334 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3335 // slot as the FP is never overwritten.
3337 FPOpOut = getFramePointerFrameIndex(DAG);
3338 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3339 false, false, false, 0);
3340 Chain = SDValue(FPOpOut.getNode(), 1);
3346 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3347 /// by "Src" to address "Dst" of size "Size". Alignment information is
3348 /// specified by the specific parameter attribute. The copy will be passed as
3349 /// a byval function parameter.
3350 /// Sometimes what we are copying is the end of a larger object, the part that
3351 /// does not fit in registers.
3353 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3354 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3356 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3357 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3358 false, false, MachinePointerInfo(),
3359 MachinePointerInfo());
3362 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3365 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3366 SDValue Arg, SDValue PtrOff, int SPDiff,
3367 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3368 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3369 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3371 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3376 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3378 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3379 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3380 DAG.getConstant(ArgOffset, PtrVT));
3382 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3383 MachinePointerInfo(), false, false, 0));
3384 // Calculate and remember argument location.
3385 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3390 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3391 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3392 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3393 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3394 MachineFunction &MF = DAG.getMachineFunction();
3396 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3397 // might overwrite each other in case of tail call optimization.
3398 SmallVector<SDValue, 8> MemOpChains2;
3399 // Do not flag preceding copytoreg stuff together with the following stuff.
3401 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3403 if (!MemOpChains2.empty())
3404 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3406 // Store the return address to the appropriate stack slot.
3407 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3408 isPPC64, isDarwinABI, dl);
3410 // Emit callseq_end just before tailcall node.
3411 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3412 DAG.getIntPtrConstant(0, true), InFlag, dl);
3413 InFlag = Chain.getValue(1);
3417 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3418 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3419 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3420 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3421 const PPCSubtarget &Subtarget) {
3423 bool isPPC64 = Subtarget.isPPC64();
3424 bool isSVR4ABI = Subtarget.isSVR4ABI();
3426 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3427 NodeTys.push_back(MVT::Other); // Returns a chain
3428 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3430 unsigned CallOpc = PPCISD::CALL;
3432 bool needIndirectCall = true;
3433 if (!isSVR4ABI || !isPPC64)
3434 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3435 // If this is an absolute destination address, use the munged value.
3436 Callee = SDValue(Dest, 0);
3437 needIndirectCall = false;
3440 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3441 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3442 // Use indirect calls for ALL functions calls in JIT mode, since the
3443 // far-call stubs may be outside relocation limits for a BL instruction.
3444 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3445 unsigned OpFlags = 0;
3446 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3447 (Subtarget.getTargetTriple().isMacOSX() &&
3448 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3449 (G->getGlobal()->isDeclaration() ||
3450 G->getGlobal()->isWeakForLinker())) {
3451 // PC-relative references to external symbols should go through $stub,
3452 // unless we're building with the leopard linker or later, which
3453 // automatically synthesizes these stubs.
3454 OpFlags = PPCII::MO_DARWIN_STUB;
3457 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3458 // every direct call is) turn it into a TargetGlobalAddress /
3459 // TargetExternalSymbol node so that legalize doesn't hack it.
3460 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3461 Callee.getValueType(),
3463 needIndirectCall = false;
3467 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3468 unsigned char OpFlags = 0;
3470 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3471 (Subtarget.getTargetTriple().isMacOSX() &&
3472 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3473 // PC-relative references to external symbols should go through $stub,
3474 // unless we're building with the leopard linker or later, which
3475 // automatically synthesizes these stubs.
3476 OpFlags = PPCII::MO_DARWIN_STUB;
3479 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3481 needIndirectCall = false;
3484 if (needIndirectCall) {
3485 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3486 // to do the call, we can't use PPCISD::CALL.
3487 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3489 if (isSVR4ABI && isPPC64) {
3490 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3491 // entry point, but to the function descriptor (the function entry point
3492 // address is part of the function descriptor though).
3493 // The function descriptor is a three doubleword structure with the
3494 // following fields: function entry point, TOC base address and
3495 // environment pointer.
3496 // Thus for a call through a function pointer, the following actions need
3498 // 1. Save the TOC of the caller in the TOC save area of its stack
3499 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3500 // 2. Load the address of the function entry point from the function
3502 // 3. Load the TOC of the callee from the function descriptor into r2.
3503 // 4. Load the environment pointer from the function descriptor into
3505 // 5. Branch to the function entry point address.
3506 // 6. On return of the callee, the TOC of the caller needs to be
3507 // restored (this is done in FinishCall()).
3509 // All those operations are flagged together to ensure that no other
3510 // operations can be scheduled in between. E.g. without flagging the
3511 // operations together, a TOC access in the caller could be scheduled
3512 // between the load of the callee TOC and the branch to the callee, which
3513 // results in the TOC access going through the TOC of the callee instead
3514 // of going through the TOC of the caller, which leads to incorrect code.
3516 // Load the address of the function entry point from the function
3518 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3519 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3520 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3521 Chain = LoadFuncPtr.getValue(1);
3522 InFlag = LoadFuncPtr.getValue(2);
3524 // Load environment pointer into r11.
3525 // Offset of the environment pointer within the function descriptor.
3526 SDValue PtrOff = DAG.getIntPtrConstant(16);
3528 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3529 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3531 Chain = LoadEnvPtr.getValue(1);
3532 InFlag = LoadEnvPtr.getValue(2);
3534 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3536 Chain = EnvVal.getValue(0);
3537 InFlag = EnvVal.getValue(1);
3539 // Load TOC of the callee into r2. We are using a target-specific load
3540 // with r2 hard coded, because the result of a target-independent load
3541 // would never go directly into r2, since r2 is a reserved register (which
3542 // prevents the register allocator from allocating it), resulting in an
3543 // additional register being allocated and an unnecessary move instruction
3545 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3546 SDValue TOCOff = DAG.getIntPtrConstant(8);
3547 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3548 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3550 Chain = LoadTOCPtr.getValue(0);
3551 InFlag = LoadTOCPtr.getValue(1);
3553 MTCTROps[0] = Chain;
3554 MTCTROps[1] = LoadFuncPtr;
3555 MTCTROps[2] = InFlag;
3558 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3559 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3560 InFlag = Chain.getValue(1);
3563 NodeTys.push_back(MVT::Other);
3564 NodeTys.push_back(MVT::Glue);
3565 Ops.push_back(Chain);
3566 CallOpc = PPCISD::BCTRL;
3567 Callee.setNode(nullptr);
3568 // Add use of X11 (holding environment pointer)
3569 if (isSVR4ABI && isPPC64)
3570 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3571 // Add CTR register as callee so a bctr can be emitted later.
3573 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3576 // If this is a direct call, pass the chain and the callee.
3577 if (Callee.getNode()) {
3578 Ops.push_back(Chain);
3579 Ops.push_back(Callee);
3581 // If this is a tail call add stack pointer delta.
3583 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3585 // Add argument registers to the end of the list so that they are known live
3587 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3588 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3589 RegsToPass[i].second.getValueType()));
3595 bool isLocalCall(const SDValue &Callee)
3597 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3598 return !G->getGlobal()->isDeclaration() &&
3599 !G->getGlobal()->isWeakForLinker();
3604 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3605 CallingConv::ID CallConv, bool isVarArg,
3606 const SmallVectorImpl<ISD::InputArg> &Ins,
3607 SDLoc dl, SelectionDAG &DAG,
3608 SmallVectorImpl<SDValue> &InVals) const {
3610 SmallVector<CCValAssign, 16> RVLocs;
3611 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3612 getTargetMachine(), RVLocs, *DAG.getContext());
3613 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3615 // Copy all of the result registers out of their specified physreg.
3616 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3617 CCValAssign &VA = RVLocs[i];
3618 assert(VA.isRegLoc() && "Can only return in registers!");
3620 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3621 VA.getLocReg(), VA.getLocVT(), InFlag);
3622 Chain = Val.getValue(1);
3623 InFlag = Val.getValue(2);
3625 switch (VA.getLocInfo()) {
3626 default: llvm_unreachable("Unknown loc info!");
3627 case CCValAssign::Full: break;
3628 case CCValAssign::AExt:
3629 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3631 case CCValAssign::ZExt:
3632 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3633 DAG.getValueType(VA.getValVT()));
3634 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3636 case CCValAssign::SExt:
3637 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3638 DAG.getValueType(VA.getValVT()));
3639 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3643 InVals.push_back(Val);
3650 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3651 bool isTailCall, bool isVarArg,
3653 SmallVector<std::pair<unsigned, SDValue>, 8>
3655 SDValue InFlag, SDValue Chain,
3657 int SPDiff, unsigned NumBytes,
3658 const SmallVectorImpl<ISD::InputArg> &Ins,
3659 SmallVectorImpl<SDValue> &InVals) const {
3660 std::vector<EVT> NodeTys;
3661 SmallVector<SDValue, 8> Ops;
3662 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3663 isTailCall, RegsToPass, Ops, NodeTys,
3666 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3667 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3668 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3670 // When performing tail call optimization the callee pops its arguments off
3671 // the stack. Account for this here so these bytes can be pushed back on in
3672 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3673 int BytesCalleePops =
3674 (CallConv == CallingConv::Fast &&
3675 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3677 // Add a register mask operand representing the call-preserved registers.
3678 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3679 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3680 assert(Mask && "Missing call preserved mask for calling convention");
3681 Ops.push_back(DAG.getRegisterMask(Mask));
3683 if (InFlag.getNode())
3684 Ops.push_back(InFlag);
3688 assert(((Callee.getOpcode() == ISD::Register &&
3689 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3690 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3691 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3692 isa<ConstantSDNode>(Callee)) &&
3693 "Expecting an global address, external symbol, absolute value or register");
3695 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3698 // Add a NOP immediately after the branch instruction when using the 64-bit
3699 // SVR4 ABI. At link time, if caller and callee are in a different module and
3700 // thus have a different TOC, the call will be replaced with a call to a stub
3701 // function which saves the current TOC, loads the TOC of the callee and
3702 // branches to the callee. The NOP will be replaced with a load instruction
3703 // which restores the TOC of the caller from the TOC save slot of the current
3704 // stack frame. If caller and callee belong to the same module (and have the
3705 // same TOC), the NOP will remain unchanged.
3707 bool needsTOCRestore = false;
3708 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3709 if (CallOpc == PPCISD::BCTRL) {
3710 // This is a call through a function pointer.
3711 // Restore the caller TOC from the save area into R2.
3712 // See PrepareCall() for more information about calls through function
3713 // pointers in the 64-bit SVR4 ABI.
3714 // We are using a target-specific load with r2 hard coded, because the
3715 // result of a target-independent load would never go directly into r2,
3716 // since r2 is a reserved register (which prevents the register allocator
3717 // from allocating it), resulting in an additional register being
3718 // allocated and an unnecessary move instruction being generated.
3719 needsTOCRestore = true;
3720 } else if ((CallOpc == PPCISD::CALL) &&
3721 (!isLocalCall(Callee) ||
3722 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3723 // Otherwise insert NOP for non-local calls.
3724 CallOpc = PPCISD::CALL_NOP;
3728 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3729 InFlag = Chain.getValue(1);
3731 if (needsTOCRestore) {
3732 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3733 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3734 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3735 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset();
3736 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3737 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3738 Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag);
3739 InFlag = Chain.getValue(1);
3742 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3743 DAG.getIntPtrConstant(BytesCalleePops, true),
3746 InFlag = Chain.getValue(1);
3748 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3749 Ins, dl, DAG, InVals);
3753 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3754 SmallVectorImpl<SDValue> &InVals) const {
3755 SelectionDAG &DAG = CLI.DAG;
3757 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3758 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3759 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3760 SDValue Chain = CLI.Chain;
3761 SDValue Callee = CLI.Callee;
3762 bool &isTailCall = CLI.IsTailCall;
3763 CallingConv::ID CallConv = CLI.CallConv;
3764 bool isVarArg = CLI.IsVarArg;
3767 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3770 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3771 report_fatal_error("failed to perform tail call elimination on a call "
3772 "site marked musttail");
3774 if (Subtarget.isSVR4ABI()) {
3775 if (Subtarget.isPPC64())
3776 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3777 isTailCall, Outs, OutVals, Ins,
3780 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3781 isTailCall, Outs, OutVals, Ins,
3785 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3786 isTailCall, Outs, OutVals, Ins,
3791 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3792 CallingConv::ID CallConv, bool isVarArg,
3794 const SmallVectorImpl<ISD::OutputArg> &Outs,
3795 const SmallVectorImpl<SDValue> &OutVals,
3796 const SmallVectorImpl<ISD::InputArg> &Ins,
3797 SDLoc dl, SelectionDAG &DAG,
3798 SmallVectorImpl<SDValue> &InVals) const {
3799 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3800 // of the 32-bit SVR4 ABI stack frame layout.
3802 assert((CallConv == CallingConv::C ||
3803 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3805 unsigned PtrByteSize = 4;
3807 MachineFunction &MF = DAG.getMachineFunction();
3809 // Mark this function as potentially containing a function that contains a
3810 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3811 // and restoring the callers stack pointer in this functions epilog. This is
3812 // done because by tail calling the called function might overwrite the value
3813 // in this function's (MF) stack pointer stack slot 0(SP).
3814 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3815 CallConv == CallingConv::Fast)
3816 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3818 // Count how many bytes are to be pushed on the stack, including the linkage
3819 // area, parameter list area and the part of the local variable space which
3820 // contains copies of aggregates which are passed by value.
3822 // Assign locations to all of the outgoing arguments.
3823 SmallVector<CCValAssign, 16> ArgLocs;
3824 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3825 getTargetMachine(), ArgLocs, *DAG.getContext());
3827 // Reserve space for the linkage area on the stack.
3828 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3831 // Handle fixed and variable vector arguments differently.
3832 // Fixed vector arguments go into registers as long as registers are
3833 // available. Variable vector arguments always go into memory.
3834 unsigned NumArgs = Outs.size();
3836 for (unsigned i = 0; i != NumArgs; ++i) {
3837 MVT ArgVT = Outs[i].VT;
3838 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3841 if (Outs[i].IsFixed) {
3842 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3845 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3851 errs() << "Call operand #" << i << " has unhandled type "
3852 << EVT(ArgVT).getEVTString() << "\n";
3854 llvm_unreachable(nullptr);
3858 // All arguments are treated the same.
3859 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3862 // Assign locations to all of the outgoing aggregate by value arguments.
3863 SmallVector<CCValAssign, 16> ByValArgLocs;
3864 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3865 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3867 // Reserve stack space for the allocations in CCInfo.
3868 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3870 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3872 // Size of the linkage area, parameter list area and the part of the local
3873 // space variable where copies of aggregates which are passed by value are
3875 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3877 // Calculate by how many bytes the stack has to be adjusted in case of tail
3878 // call optimization.
3879 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3881 // Adjust the stack pointer for the new arguments...
3882 // These operations are automatically eliminated by the prolog/epilog pass
3883 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3885 SDValue CallSeqStart = Chain;
3887 // Load the return address and frame pointer so it can be moved somewhere else
3890 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3893 // Set up a copy of the stack pointer for use loading and storing any
3894 // arguments that may not fit in the registers available for argument
3896 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3898 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3899 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3900 SmallVector<SDValue, 8> MemOpChains;
3902 bool seenFloatArg = false;
3903 // Walk the register/memloc assignments, inserting copies/loads.
3904 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3907 CCValAssign &VA = ArgLocs[i];
3908 SDValue Arg = OutVals[i];
3909 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3911 if (Flags.isByVal()) {
3912 // Argument is an aggregate which is passed by value, thus we need to
3913 // create a copy of it in the local variable space of the current stack
3914 // frame (which is the stack frame of the caller) and pass the address of
3915 // this copy to the callee.
3916 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3917 CCValAssign &ByValVA = ByValArgLocs[j++];
3918 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3920 // Memory reserved in the local variable space of the callers stack frame.
3921 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3923 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3924 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3926 // Create a copy of the argument in the local area of the current
3928 SDValue MemcpyCall =
3929 CreateCopyOfByValArgument(Arg, PtrOff,
3930 CallSeqStart.getNode()->getOperand(0),
3933 // This must go outside the CALLSEQ_START..END.
3934 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3935 CallSeqStart.getNode()->getOperand(1),
3937 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3938 NewCallSeqStart.getNode());
3939 Chain = CallSeqStart = NewCallSeqStart;
3941 // Pass the address of the aggregate copy on the stack either in a
3942 // physical register or in the parameter list area of the current stack
3943 // frame to the callee.
3947 if (VA.isRegLoc()) {
3948 if (Arg.getValueType() == MVT::i1)
3949 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
3951 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3952 // Put argument in a physical register.
3953 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3955 // Put argument in the parameter list area of the current stack frame.
3956 assert(VA.isMemLoc());
3957 unsigned LocMemOffset = VA.getLocMemOffset();
3960 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3961 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3963 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3964 MachinePointerInfo(),
3967 // Calculate and remember argument location.
3968 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3974 if (!MemOpChains.empty())
3975 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3977 // Build a sequence of copy-to-reg nodes chained together with token chain
3978 // and flag operands which copy the outgoing args into the appropriate regs.
3980 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3981 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3982 RegsToPass[i].second, InFlag);
3983 InFlag = Chain.getValue(1);
3986 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3989 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3990 SDValue Ops[] = { Chain, InFlag };
3992 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3993 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
3995 InFlag = Chain.getValue(1);
3999 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4000 false, TailCallArguments);
4002 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4003 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4007 // Copy an argument into memory, being careful to do this outside the
4008 // call sequence for the call to which the argument belongs.
4010 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4011 SDValue CallSeqStart,
4012 ISD::ArgFlagsTy Flags,
4015 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4016 CallSeqStart.getNode()->getOperand(0),
4018 // The MEMCPY must go outside the CALLSEQ_START..END.
4019 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4020 CallSeqStart.getNode()->getOperand(1),
4022 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4023 NewCallSeqStart.getNode());
4024 return NewCallSeqStart;
4028 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4029 CallingConv::ID CallConv, bool isVarArg,
4031 const SmallVectorImpl<ISD::OutputArg> &Outs,
4032 const SmallVectorImpl<SDValue> &OutVals,
4033 const SmallVectorImpl<ISD::InputArg> &Ins,
4034 SDLoc dl, SelectionDAG &DAG,
4035 SmallVectorImpl<SDValue> &InVals) const {
4037 unsigned NumOps = Outs.size();
4039 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4040 unsigned PtrByteSize = 8;
4042 MachineFunction &MF = DAG.getMachineFunction();
4044 // Mark this function as potentially containing a function that contains a
4045 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4046 // and restoring the callers stack pointer in this functions epilog. This is
4047 // done because by tail calling the called function might overwrite the value
4048 // in this function's (MF) stack pointer stack slot 0(SP).
4049 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4050 CallConv == CallingConv::Fast)
4051 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4053 unsigned nAltivecParamsAtEnd = 0;
4055 // Count how many bytes are to be pushed on the stack, including the linkage
4056 // area, and parameter passing area. We start with at least 48 bytes, which
4057 // is reserved space for [SP][CR][LR][3 x unused].
4058 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
4061 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
4062 Outs, OutVals, nAltivecParamsAtEnd);
4064 // Calculate by how many bytes the stack has to be adjusted in case of tail
4065 // call optimization.
4066 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4068 // To protect arguments on the stack from being clobbered in a tail call,
4069 // force all the loads to happen before doing any other lowering.
4071 Chain = DAG.getStackArgumentTokenFactor(Chain);
4073 // Adjust the stack pointer for the new arguments...
4074 // These operations are automatically eliminated by the prolog/epilog pass
4075 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4077 SDValue CallSeqStart = Chain;
4079 // Load the return address and frame pointer so it can be move somewhere else
4082 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4085 // Set up a copy of the stack pointer for use loading and storing any
4086 // arguments that may not fit in the registers available for argument
4088 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4090 // Figure out which arguments are going to go in registers, and which in
4091 // memory. Also, if this is a vararg function, floating point operations
4092 // must be stored to our stack, and loaded into integer regs as well, if
4093 // any integer regs are available for argument passing.
4094 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
4095 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4097 static const MCPhysReg GPR[] = {
4098 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4099 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4101 static const MCPhysReg *FPR = GetFPR();
4103 static const MCPhysReg VR[] = {
4104 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4105 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4107 static const MCPhysReg VSRH[] = {
4108 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4109 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4112 const unsigned NumGPRs = array_lengthof(GPR);
4113 const unsigned NumFPRs = 13;
4114 const unsigned NumVRs = array_lengthof(VR);
4116 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4117 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4119 SmallVector<SDValue, 8> MemOpChains;
4120 for (unsigned i = 0; i != NumOps; ++i) {
4121 SDValue Arg = OutVals[i];
4122 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4124 // PtrOff will be used to store the current argument to the stack if a
4125 // register cannot be found for it.
4128 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4130 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4132 // Promote integers to 64-bit values.
4133 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4134 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4135 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4136 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4139 // FIXME memcpy is used way more than necessary. Correctness first.
4140 // Note: "by value" is code for passing a structure by value, not
4142 if (Flags.isByVal()) {
4143 // Note: Size includes alignment padding, so
4144 // struct x { short a; char b; }
4145 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4146 // These are the proper values we need for right-justifying the
4147 // aggregate in a parameter register.
4148 unsigned Size = Flags.getByValSize();
4150 // An empty aggregate parameter takes up no storage and no
4155 unsigned BVAlign = Flags.getByValAlign();
4157 if (BVAlign % PtrByteSize != 0)
4159 "ByVal alignment is not a multiple of the pointer size");
4161 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
4164 // All aggregates smaller than 8 bytes must be passed right-justified.
4165 if (Size==1 || Size==2 || Size==4) {
4166 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4167 if (GPR_idx != NumGPRs) {
4168 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4169 MachinePointerInfo(), VT,
4171 MemOpChains.push_back(Load.getValue(1));
4172 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4174 ArgOffset += PtrByteSize;
4179 if (GPR_idx == NumGPRs && Size < 8) {
4180 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4181 PtrOff.getValueType());
4182 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4183 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4186 ArgOffset += PtrByteSize;
4189 // Copy entire object into memory. There are cases where gcc-generated
4190 // code assumes it is there, even if it could be put entirely into
4191 // registers. (This is not what the doc says.)
4193 // FIXME: The above statement is likely due to a misunderstanding of the
4194 // documents. All arguments must be copied into the parameter area BY
4195 // THE CALLEE in the event that the callee takes the address of any
4196 // formal argument. That has not yet been implemented. However, it is
4197 // reasonable to use the stack area as a staging area for the register
4200 // Skip this for small aggregates, as we will use the same slot for a
4201 // right-justified copy, below.
4203 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4207 // When a register is available, pass a small aggregate right-justified.
4208 if (Size < 8 && GPR_idx != NumGPRs) {
4209 // The easiest way to get this right-justified in a register
4210 // is to copy the structure into the rightmost portion of a
4211 // local variable slot, then load the whole slot into the
4213 // FIXME: The memcpy seems to produce pretty awful code for
4214 // small aggregates, particularly for packed ones.
4215 // FIXME: It would be preferable to use the slot in the
4216 // parameter save area instead of a new local variable.
4217 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4218 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4219 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4223 // Load the slot into the register.
4224 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4225 MachinePointerInfo(),
4226 false, false, false, 0);
4227 MemOpChains.push_back(Load.getValue(1));
4228 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4230 // Done with this argument.
4231 ArgOffset += PtrByteSize;
4235 // For aggregates larger than PtrByteSize, copy the pieces of the
4236 // object that fit into registers from the parameter save area.
4237 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4238 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4239 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4240 if (GPR_idx != NumGPRs) {
4241 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4242 MachinePointerInfo(),
4243 false, false, false, 0);
4244 MemOpChains.push_back(Load.getValue(1));
4245 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4246 ArgOffset += PtrByteSize;
4248 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4255 switch (Arg.getSimpleValueType().SimpleTy) {
4256 default: llvm_unreachable("Unexpected ValueType for argument!");
4260 if (GPR_idx != NumGPRs) {
4261 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4263 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4264 true, isTailCall, false, MemOpChains,
4265 TailCallArguments, dl);
4267 ArgOffset += PtrByteSize;
4271 if (FPR_idx != NumFPRs) {
4272 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4275 // A single float or an aggregate containing only a single float
4276 // must be passed right-justified in the stack doubleword, and
4277 // in the GPR, if one is available.
4279 if (Arg.getSimpleValueType().SimpleTy == MVT::f32) {
4280 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4281 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4285 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
4286 MachinePointerInfo(), false, false, 0);
4287 MemOpChains.push_back(Store);
4289 // Float varargs are always shadowed in available integer registers
4290 if (GPR_idx != NumGPRs) {
4291 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4292 MachinePointerInfo(), false, false,
4294 MemOpChains.push_back(Load.getValue(1));
4295 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4297 } else if (GPR_idx != NumGPRs)
4298 // If we have any FPRs remaining, we may also have GPRs remaining.
4301 // Single-precision floating-point values are mapped to the
4302 // second (rightmost) word of the stack doubleword.
4303 if (Arg.getValueType() == MVT::f32) {
4304 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4305 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4308 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4309 true, isTailCall, false, MemOpChains,
4310 TailCallArguments, dl);
4321 // These go aligned on the stack, or in the corresponding R registers
4322 // when within range. The Darwin PPC ABI doc claims they also go in
4323 // V registers; in fact gcc does this only for arguments that are
4324 // prototyped, not for those that match the ... We do it for all
4325 // arguments, seems to work.
4326 while (ArgOffset % 16 !=0) {
4327 ArgOffset += PtrByteSize;
4328 if (GPR_idx != NumGPRs)
4331 // We could elide this store in the case where the object fits
4332 // entirely in R registers. Maybe later.
4333 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4334 DAG.getConstant(ArgOffset, PtrVT));
4335 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4336 MachinePointerInfo(), false, false, 0);
4337 MemOpChains.push_back(Store);
4338 if (VR_idx != NumVRs) {
4339 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4340 MachinePointerInfo(),
4341 false, false, false, 0);
4342 MemOpChains.push_back(Load.getValue(1));
4344 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4345 Arg.getSimpleValueType() == MVT::v2i64) ?
4346 VSRH[VR_idx] : VR[VR_idx];
4349 RegsToPass.push_back(std::make_pair(VReg, Load));
4352 for (unsigned i=0; i<16; i+=PtrByteSize) {
4353 if (GPR_idx == NumGPRs)
4355 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4356 DAG.getConstant(i, PtrVT));
4357 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4358 false, false, false, 0);
4359 MemOpChains.push_back(Load.getValue(1));
4360 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4365 // Non-varargs Altivec params generally go in registers, but have
4366 // stack space allocated at the end.
4367 if (VR_idx != NumVRs) {
4368 // Doesn't have GPR space allocated.
4369 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4370 Arg.getSimpleValueType() == MVT::v2i64) ?
4371 VSRH[VR_idx] : VR[VR_idx];
4374 RegsToPass.push_back(std::make_pair(VReg, Arg));
4376 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4377 true, isTailCall, true, MemOpChains,
4378 TailCallArguments, dl);
4385 if (!MemOpChains.empty())
4386 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4388 // Check if this is an indirect call (MTCTR/BCTRL).
4389 // See PrepareCall() for more information about calls through function
4390 // pointers in the 64-bit SVR4 ABI.
4392 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4393 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4394 // Load r2 into a virtual register and store it to the TOC save area.
4395 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4396 // TOC save area offset.
4397 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset();
4398 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4399 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4400 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4404 // Build a sequence of copy-to-reg nodes chained together with token chain
4405 // and flag operands which copy the outgoing args into the appropriate regs.
4407 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4408 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4409 RegsToPass[i].second, InFlag);
4410 InFlag = Chain.getValue(1);
4414 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4415 FPOp, true, TailCallArguments);
4417 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4418 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4423 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4424 CallingConv::ID CallConv, bool isVarArg,
4426 const SmallVectorImpl<ISD::OutputArg> &Outs,
4427 const SmallVectorImpl<SDValue> &OutVals,
4428 const SmallVectorImpl<ISD::InputArg> &Ins,
4429 SDLoc dl, SelectionDAG &DAG,
4430 SmallVectorImpl<SDValue> &InVals) const {
4432 unsigned NumOps = Outs.size();
4434 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4435 bool isPPC64 = PtrVT == MVT::i64;
4436 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4438 MachineFunction &MF = DAG.getMachineFunction();
4440 // Mark this function as potentially containing a function that contains a
4441 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4442 // and restoring the callers stack pointer in this functions epilog. This is
4443 // done because by tail calling the called function might overwrite the value
4444 // in this function's (MF) stack pointer stack slot 0(SP).
4445 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4446 CallConv == CallingConv::Fast)
4447 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4449 unsigned nAltivecParamsAtEnd = 0;
4451 // Count how many bytes are to be pushed on the stack, including the linkage
4452 // area, and parameter passing area. We start with 24/48 bytes, which is
4453 // prereserved space for [SP][CR][LR][3 x unused].
4455 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4457 nAltivecParamsAtEnd);
4459 // Calculate by how many bytes the stack has to be adjusted in case of tail
4460 // call optimization.
4461 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4463 // To protect arguments on the stack from being clobbered in a tail call,
4464 // force all the loads to happen before doing any other lowering.
4466 Chain = DAG.getStackArgumentTokenFactor(Chain);
4468 // Adjust the stack pointer for the new arguments...
4469 // These operations are automatically eliminated by the prolog/epilog pass
4470 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4472 SDValue CallSeqStart = Chain;
4474 // Load the return address and frame pointer so it can be move somewhere else
4477 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4480 // Set up a copy of the stack pointer for use loading and storing any
4481 // arguments that may not fit in the registers available for argument
4485 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4487 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4489 // Figure out which arguments are going to go in registers, and which in
4490 // memory. Also, if this is a vararg function, floating point operations
4491 // must be stored to our stack, and loaded into integer regs as well, if
4492 // any integer regs are available for argument passing.
4493 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4494 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4496 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4497 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4498 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4500 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4501 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4502 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4504 static const MCPhysReg *FPR = GetFPR();
4506 static const MCPhysReg VR[] = {
4507 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4508 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4510 const unsigned NumGPRs = array_lengthof(GPR_32);
4511 const unsigned NumFPRs = 13;
4512 const unsigned NumVRs = array_lengthof(VR);
4514 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4516 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4517 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4519 SmallVector<SDValue, 8> MemOpChains;
4520 for (unsigned i = 0; i != NumOps; ++i) {
4521 SDValue Arg = OutVals[i];
4522 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4524 // PtrOff will be used to store the current argument to the stack if a
4525 // register cannot be found for it.
4528 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4530 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4532 // On PPC64, promote integers to 64-bit values.
4533 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4534 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4535 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4536 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4539 // FIXME memcpy is used way more than necessary. Correctness first.
4540 // Note: "by value" is code for passing a structure by value, not
4542 if (Flags.isByVal()) {
4543 unsigned Size = Flags.getByValSize();
4544 // Very small objects are passed right-justified. Everything else is
4545 // passed left-justified.
4546 if (Size==1 || Size==2) {
4547 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4548 if (GPR_idx != NumGPRs) {
4549 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4550 MachinePointerInfo(), VT,
4552 MemOpChains.push_back(Load.getValue(1));
4553 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4555 ArgOffset += PtrByteSize;
4557 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4558 PtrOff.getValueType());
4559 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4560 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4563 ArgOffset += PtrByteSize;
4567 // Copy entire object into memory. There are cases where gcc-generated
4568 // code assumes it is there, even if it could be put entirely into
4569 // registers. (This is not what the doc says.)
4570 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4574 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4575 // copy the pieces of the object that fit into registers from the
4576 // parameter save area.
4577 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4578 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4579 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4580 if (GPR_idx != NumGPRs) {
4581 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4582 MachinePointerInfo(),
4583 false, false, false, 0);
4584 MemOpChains.push_back(Load.getValue(1));
4585 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4586 ArgOffset += PtrByteSize;
4588 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4595 switch (Arg.getSimpleValueType().SimpleTy) {
4596 default: llvm_unreachable("Unexpected ValueType for argument!");
4600 if (GPR_idx != NumGPRs) {
4601 if (Arg.getValueType() == MVT::i1)
4602 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4604 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4606 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4607 isPPC64, isTailCall, false, MemOpChains,
4608 TailCallArguments, dl);
4610 ArgOffset += PtrByteSize;
4614 if (FPR_idx != NumFPRs) {
4615 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4618 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4619 MachinePointerInfo(), false, false, 0);
4620 MemOpChains.push_back(Store);
4622 // Float varargs are always shadowed in available integer registers
4623 if (GPR_idx != NumGPRs) {
4624 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4625 MachinePointerInfo(), false, false,
4627 MemOpChains.push_back(Load.getValue(1));
4628 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4630 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4631 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4632 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4633 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4634 MachinePointerInfo(),
4635 false, false, false, 0);
4636 MemOpChains.push_back(Load.getValue(1));
4637 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4640 // If we have any FPRs remaining, we may also have GPRs remaining.
4641 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4643 if (GPR_idx != NumGPRs)
4645 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4646 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4650 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4651 isPPC64, isTailCall, false, MemOpChains,
4652 TailCallArguments, dl);
4656 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4663 // These go aligned on the stack, or in the corresponding R registers
4664 // when within range. The Darwin PPC ABI doc claims they also go in
4665 // V registers; in fact gcc does this only for arguments that are
4666 // prototyped, not for those that match the ... We do it for all
4667 // arguments, seems to work.
4668 while (ArgOffset % 16 !=0) {
4669 ArgOffset += PtrByteSize;
4670 if (GPR_idx != NumGPRs)
4673 // We could elide this store in the case where the object fits
4674 // entirely in R registers. Maybe later.
4675 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4676 DAG.getConstant(ArgOffset, PtrVT));
4677 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4678 MachinePointerInfo(), false, false, 0);
4679 MemOpChains.push_back(Store);
4680 if (VR_idx != NumVRs) {
4681 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4682 MachinePointerInfo(),
4683 false, false, false, 0);
4684 MemOpChains.push_back(Load.getValue(1));
4685 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4688 for (unsigned i=0; i<16; i+=PtrByteSize) {
4689 if (GPR_idx == NumGPRs)
4691 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4692 DAG.getConstant(i, PtrVT));
4693 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4694 false, false, false, 0);
4695 MemOpChains.push_back(Load.getValue(1));
4696 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4701 // Non-varargs Altivec params generally go in registers, but have
4702 // stack space allocated at the end.
4703 if (VR_idx != NumVRs) {
4704 // Doesn't have GPR space allocated.
4705 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4706 } else if (nAltivecParamsAtEnd==0) {
4707 // We are emitting Altivec params in order.
4708 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4709 isPPC64, isTailCall, true, MemOpChains,
4710 TailCallArguments, dl);
4716 // If all Altivec parameters fit in registers, as they usually do,
4717 // they get stack space following the non-Altivec parameters. We
4718 // don't track this here because nobody below needs it.
4719 // If there are more Altivec parameters than fit in registers emit
4721 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4723 // Offset is aligned; skip 1st 12 params which go in V registers.
4724 ArgOffset = ((ArgOffset+15)/16)*16;
4726 for (unsigned i = 0; i != NumOps; ++i) {
4727 SDValue Arg = OutVals[i];
4728 EVT ArgType = Outs[i].VT;
4729 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4730 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4733 // We are emitting Altivec params in order.
4734 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4735 isPPC64, isTailCall, true, MemOpChains,
4736 TailCallArguments, dl);
4743 if (!MemOpChains.empty())
4744 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4746 // On Darwin, R12 must contain the address of an indirect callee. This does
4747 // not mean the MTCTR instruction must use R12; it's easier to model this as
4748 // an extra parameter, so do that.
4750 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4751 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4752 !isBLACompatibleAddress(Callee, DAG))
4753 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4754 PPC::R12), Callee));
4756 // Build a sequence of copy-to-reg nodes chained together with token chain
4757 // and flag operands which copy the outgoing args into the appropriate regs.
4759 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4760 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4761 RegsToPass[i].second, InFlag);
4762 InFlag = Chain.getValue(1);
4766 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4767 FPOp, true, TailCallArguments);
4769 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4770 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4775 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4776 MachineFunction &MF, bool isVarArg,
4777 const SmallVectorImpl<ISD::OutputArg> &Outs,
4778 LLVMContext &Context) const {
4779 SmallVector<CCValAssign, 16> RVLocs;
4780 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4782 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4786 PPCTargetLowering::LowerReturn(SDValue Chain,
4787 CallingConv::ID CallConv, bool isVarArg,
4788 const SmallVectorImpl<ISD::OutputArg> &Outs,
4789 const SmallVectorImpl<SDValue> &OutVals,
4790 SDLoc dl, SelectionDAG &DAG) const {
4792 SmallVector<CCValAssign, 16> RVLocs;
4793 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4794 getTargetMachine(), RVLocs, *DAG.getContext());
4795 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4798 SmallVector<SDValue, 4> RetOps(1, Chain);
4800 // Copy the result values into the output registers.
4801 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4802 CCValAssign &VA = RVLocs[i];
4803 assert(VA.isRegLoc() && "Can only return in registers!");
4805 SDValue Arg = OutVals[i];
4807 switch (VA.getLocInfo()) {
4808 default: llvm_unreachable("Unknown loc info!");
4809 case CCValAssign::Full: break;
4810 case CCValAssign::AExt:
4811 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4813 case CCValAssign::ZExt:
4814 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4816 case CCValAssign::SExt:
4817 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4821 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4822 Flag = Chain.getValue(1);
4823 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4826 RetOps[0] = Chain; // Update chain.
4828 // Add the flag if we have it.
4830 RetOps.push_back(Flag);
4832 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
4835 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4836 const PPCSubtarget &Subtarget) const {
4837 // When we pop the dynamic allocation we need to restore the SP link.
4840 // Get the corect type for pointers.
4841 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4843 // Construct the stack pointer operand.
4844 bool isPPC64 = Subtarget.isPPC64();
4845 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4846 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4848 // Get the operands for the STACKRESTORE.
4849 SDValue Chain = Op.getOperand(0);
4850 SDValue SaveSP = Op.getOperand(1);
4852 // Load the old link SP.
4853 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4854 MachinePointerInfo(),
4855 false, false, false, 0);
4857 // Restore the stack pointer.
4858 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4860 // Store the old link SP.
4861 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4868 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4869 MachineFunction &MF = DAG.getMachineFunction();
4870 bool isPPC64 = Subtarget.isPPC64();
4871 bool isDarwinABI = Subtarget.isDarwinABI();
4872 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4874 // Get current frame pointer save index. The users of this index will be
4875 // primarily DYNALLOC instructions.
4876 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4877 int RASI = FI->getReturnAddrSaveIndex();
4879 // If the frame pointer save index hasn't been defined yet.
4881 // Find out what the fix offset of the frame pointer save area.
4882 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4883 // Allocate the frame index for frame pointer save area.
4884 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4886 FI->setReturnAddrSaveIndex(RASI);
4888 return DAG.getFrameIndex(RASI, PtrVT);
4892 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4893 MachineFunction &MF = DAG.getMachineFunction();
4894 bool isPPC64 = Subtarget.isPPC64();
4895 bool isDarwinABI = Subtarget.isDarwinABI();
4896 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4898 // Get current frame pointer save index. The users of this index will be
4899 // primarily DYNALLOC instructions.
4900 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4901 int FPSI = FI->getFramePointerSaveIndex();
4903 // If the frame pointer save index hasn't been defined yet.
4905 // Find out what the fix offset of the frame pointer save area.
4906 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4909 // Allocate the frame index for frame pointer save area.
4910 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4912 FI->setFramePointerSaveIndex(FPSI);
4914 return DAG.getFrameIndex(FPSI, PtrVT);
4917 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4919 const PPCSubtarget &Subtarget) const {
4921 SDValue Chain = Op.getOperand(0);
4922 SDValue Size = Op.getOperand(1);
4925 // Get the corect type for pointers.
4926 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4928 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4929 DAG.getConstant(0, PtrVT), Size);
4930 // Construct a node for the frame pointer save index.
4931 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4932 // Build a DYNALLOC node.
4933 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4934 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4935 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
4938 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4939 SelectionDAG &DAG) const {
4941 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4942 DAG.getVTList(MVT::i32, MVT::Other),
4943 Op.getOperand(0), Op.getOperand(1));
4946 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4947 SelectionDAG &DAG) const {
4949 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4950 Op.getOperand(0), Op.getOperand(1));
4953 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
4954 assert(Op.getValueType() == MVT::i1 &&
4955 "Custom lowering only for i1 loads");
4957 // First, load 8 bits into 32 bits, then truncate to 1 bit.
4960 LoadSDNode *LD = cast<LoadSDNode>(Op);
4962 SDValue Chain = LD->getChain();
4963 SDValue BasePtr = LD->getBasePtr();
4964 MachineMemOperand *MMO = LD->getMemOperand();
4966 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
4967 BasePtr, MVT::i8, MMO);
4968 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
4970 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
4971 return DAG.getMergeValues(Ops, dl);
4974 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
4975 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
4976 "Custom lowering only for i1 stores");
4978 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
4981 StoreSDNode *ST = cast<StoreSDNode>(Op);
4983 SDValue Chain = ST->getChain();
4984 SDValue BasePtr = ST->getBasePtr();
4985 SDValue Value = ST->getValue();
4986 MachineMemOperand *MMO = ST->getMemOperand();
4988 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
4989 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
4992 // FIXME: Remove this once the ANDI glue bug is fixed:
4993 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
4994 assert(Op.getValueType() == MVT::i1 &&
4995 "Custom lowering only for i1 results");
4998 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5002 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5004 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5005 // Not FP? Not a fsel.
5006 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5007 !Op.getOperand(2).getValueType().isFloatingPoint())
5010 // We might be able to do better than this under some circumstances, but in
5011 // general, fsel-based lowering of select is a finite-math-only optimization.
5012 // For more information, see section F.3 of the 2.06 ISA specification.
5013 if (!DAG.getTarget().Options.NoInfsFPMath ||
5014 !DAG.getTarget().Options.NoNaNsFPMath)
5017 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5019 EVT ResVT = Op.getValueType();
5020 EVT CmpVT = Op.getOperand(0).getValueType();
5021 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5022 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5025 // If the RHS of the comparison is a 0.0, we don't need to do the
5026 // subtraction at all.
5028 if (isFloatingPointZero(RHS))
5030 default: break; // SETUO etc aren't handled by fsel.
5034 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5035 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5036 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5037 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5038 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5039 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5040 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5043 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5046 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5047 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5048 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5051 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5054 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5055 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5056 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5057 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5062 default: break; // SETUO etc aren't handled by fsel.
5066 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5067 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5068 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5069 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5070 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5071 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5072 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5073 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5076 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5077 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5078 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5079 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5082 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5083 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5084 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5085 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5088 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5089 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5090 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5091 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5094 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5095 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5096 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5097 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5102 // FIXME: Split this code up when LegalizeDAGTypes lands.
5103 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5105 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5106 SDValue Src = Op.getOperand(0);
5107 if (Src.getValueType() == MVT::f32)
5108 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5111 switch (Op.getSimpleValueType().SimpleTy) {
5112 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5114 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5115 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5120 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5121 "i64 FP_TO_UINT is supported only with FPCVT");
5122 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5128 // Convert the FP value to an int value through memory.
5129 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5130 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5131 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5132 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5133 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5135 // Emit a store to the stack slot.
5138 MachineFunction &MF = DAG.getMachineFunction();
5139 MachineMemOperand *MMO =
5140 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5141 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5142 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5143 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5145 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5146 MPI, false, false, 0);
5148 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5150 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5151 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5152 DAG.getConstant(4, FIPtr.getValueType()));
5153 MPI = MachinePointerInfo();
5156 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5157 false, false, false, 0);
5160 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5161 SelectionDAG &DAG) const {
5163 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5164 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5167 if (Op.getOperand(0).getValueType() == MVT::i1)
5168 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5169 DAG.getConstantFP(1.0, Op.getValueType()),
5170 DAG.getConstantFP(0.0, Op.getValueType()));
5172 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5173 "UINT_TO_FP is supported only with FPCVT");
5175 // If we have FCFIDS, then use it when converting to single-precision.
5176 // Otherwise, convert to double-precision and then round.
5177 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5178 (Op.getOpcode() == ISD::UINT_TO_FP ?
5179 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5180 (Op.getOpcode() == ISD::UINT_TO_FP ?
5181 PPCISD::FCFIDU : PPCISD::FCFID);
5182 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5183 MVT::f32 : MVT::f64;
5185 if (Op.getOperand(0).getValueType() == MVT::i64) {
5186 SDValue SINT = Op.getOperand(0);
5187 // When converting to single-precision, we actually need to convert
5188 // to double-precision first and then round to single-precision.
5189 // To avoid double-rounding effects during that operation, we have
5190 // to prepare the input operand. Bits that might be truncated when
5191 // converting to double-precision are replaced by a bit that won't
5192 // be lost at this stage, but is below the single-precision rounding
5195 // However, if -enable-unsafe-fp-math is in effect, accept double
5196 // rounding to avoid the extra overhead.
5197 if (Op.getValueType() == MVT::f32 &&
5198 !Subtarget.hasFPCVT() &&
5199 !DAG.getTarget().Options.UnsafeFPMath) {
5201 // Twiddle input to make sure the low 11 bits are zero. (If this
5202 // is the case, we are guaranteed the value will fit into the 53 bit
5203 // mantissa of an IEEE double-precision value without rounding.)
5204 // If any of those low 11 bits were not zero originally, make sure
5205 // bit 12 (value 2048) is set instead, so that the final rounding
5206 // to single-precision gets the correct result.
5207 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5208 SINT, DAG.getConstant(2047, MVT::i64));
5209 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5210 Round, DAG.getConstant(2047, MVT::i64));
5211 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5212 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5213 Round, DAG.getConstant(-2048, MVT::i64));
5215 // However, we cannot use that value unconditionally: if the magnitude
5216 // of the input value is small, the bit-twiddling we did above might
5217 // end up visibly changing the output. Fortunately, in that case, we
5218 // don't need to twiddle bits since the original input will convert
5219 // exactly to double-precision floating-point already. Therefore,
5220 // construct a conditional to use the original value if the top 11
5221 // bits are all sign-bit copies, and use the rounded value computed
5223 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5224 SINT, DAG.getConstant(53, MVT::i32));
5225 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5226 Cond, DAG.getConstant(1, MVT::i64));
5227 Cond = DAG.getSetCC(dl, MVT::i32,
5228 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5230 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5233 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5234 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5236 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5237 FP = DAG.getNode(ISD::FP_ROUND, dl,
5238 MVT::f32, FP, DAG.getIntPtrConstant(0));
5242 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5243 "Unhandled INT_TO_FP type in custom expander!");
5244 // Since we only generate this in 64-bit mode, we can take advantage of
5245 // 64-bit registers. In particular, sign extend the input value into the
5246 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5247 // then lfd it and fcfid it.
5248 MachineFunction &MF = DAG.getMachineFunction();
5249 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5250 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5253 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5254 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5255 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5257 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5258 MachinePointerInfo::getFixedStack(FrameIdx),
5261 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5262 "Expected an i32 store");
5263 MachineMemOperand *MMO =
5264 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5265 MachineMemOperand::MOLoad, 4, 4);
5266 SDValue Ops[] = { Store, FIdx };
5267 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5268 PPCISD::LFIWZX : PPCISD::LFIWAX,
5269 dl, DAG.getVTList(MVT::f64, MVT::Other),
5270 Ops, MVT::i32, MMO);
5272 assert(Subtarget.isPPC64() &&
5273 "i32->FP without LFIWAX supported only on PPC64");
5275 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5276 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5278 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5281 // STD the extended value into the stack slot.
5282 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5283 MachinePointerInfo::getFixedStack(FrameIdx),
5286 // Load the value as a double.
5287 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5288 MachinePointerInfo::getFixedStack(FrameIdx),
5289 false, false, false, 0);
5292 // FCFID it and return it.
5293 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5294 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5295 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5299 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5300 SelectionDAG &DAG) const {
5303 The rounding mode is in bits 30:31 of FPSR, and has the following
5310 FLT_ROUNDS, on the other hand, expects the following:
5317 To perform the conversion, we do:
5318 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5321 MachineFunction &MF = DAG.getMachineFunction();
5322 EVT VT = Op.getValueType();
5323 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5325 // Save FP Control Word to register
5327 MVT::f64, // return register
5328 MVT::Glue // unused in this context
5330 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5332 // Save FP register to stack slot
5333 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5334 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5335 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5336 StackSlot, MachinePointerInfo(), false, false,0);
5338 // Load FP Control Word from low 32 bits of stack slot.
5339 SDValue Four = DAG.getConstant(4, PtrVT);
5340 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5341 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5342 false, false, false, 0);
5344 // Transform as necessary
5346 DAG.getNode(ISD::AND, dl, MVT::i32,
5347 CWD, DAG.getConstant(3, MVT::i32));
5349 DAG.getNode(ISD::SRL, dl, MVT::i32,
5350 DAG.getNode(ISD::AND, dl, MVT::i32,
5351 DAG.getNode(ISD::XOR, dl, MVT::i32,
5352 CWD, DAG.getConstant(3, MVT::i32)),
5353 DAG.getConstant(3, MVT::i32)),
5354 DAG.getConstant(1, MVT::i32));
5357 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5359 return DAG.getNode((VT.getSizeInBits() < 16 ?
5360 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5363 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5364 EVT VT = Op.getValueType();
5365 unsigned BitWidth = VT.getSizeInBits();
5367 assert(Op.getNumOperands() == 3 &&
5368 VT == Op.getOperand(1).getValueType() &&
5371 // Expand into a bunch of logical ops. Note that these ops
5372 // depend on the PPC behavior for oversized shift amounts.
5373 SDValue Lo = Op.getOperand(0);
5374 SDValue Hi = Op.getOperand(1);
5375 SDValue Amt = Op.getOperand(2);
5376 EVT AmtVT = Amt.getValueType();
5378 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5379 DAG.getConstant(BitWidth, AmtVT), Amt);
5380 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5381 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5382 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5383 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5384 DAG.getConstant(-BitWidth, AmtVT));
5385 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5386 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5387 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5388 SDValue OutOps[] = { OutLo, OutHi };
5389 return DAG.getMergeValues(OutOps, dl);
5392 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5393 EVT VT = Op.getValueType();
5395 unsigned BitWidth = VT.getSizeInBits();
5396 assert(Op.getNumOperands() == 3 &&
5397 VT == Op.getOperand(1).getValueType() &&
5400 // Expand into a bunch of logical ops. Note that these ops
5401 // depend on the PPC behavior for oversized shift amounts.
5402 SDValue Lo = Op.getOperand(0);
5403 SDValue Hi = Op.getOperand(1);
5404 SDValue Amt = Op.getOperand(2);
5405 EVT AmtVT = Amt.getValueType();
5407 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5408 DAG.getConstant(BitWidth, AmtVT), Amt);
5409 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5410 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5411 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5412 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5413 DAG.getConstant(-BitWidth, AmtVT));
5414 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5415 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5416 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5417 SDValue OutOps[] = { OutLo, OutHi };
5418 return DAG.getMergeValues(OutOps, dl);
5421 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5423 EVT VT = Op.getValueType();
5424 unsigned BitWidth = VT.getSizeInBits();
5425 assert(Op.getNumOperands() == 3 &&
5426 VT == Op.getOperand(1).getValueType() &&
5429 // Expand into a bunch of logical ops, followed by a select_cc.
5430 SDValue Lo = Op.getOperand(0);
5431 SDValue Hi = Op.getOperand(1);
5432 SDValue Amt = Op.getOperand(2);
5433 EVT AmtVT = Amt.getValueType();
5435 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5436 DAG.getConstant(BitWidth, AmtVT), Amt);
5437 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5438 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5439 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5440 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5441 DAG.getConstant(-BitWidth, AmtVT));
5442 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5443 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5444 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5445 Tmp4, Tmp6, ISD::SETLE);
5446 SDValue OutOps[] = { OutLo, OutHi };
5447 return DAG.getMergeValues(OutOps, dl);
5450 //===----------------------------------------------------------------------===//
5451 // Vector related lowering.
5454 /// BuildSplatI - Build a canonical splati of Val with an element size of
5455 /// SplatSize. Cast the result to VT.
5456 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5457 SelectionDAG &DAG, SDLoc dl) {
5458 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5460 static const EVT VTys[] = { // canonical VT to use for each size.
5461 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5464 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5466 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5470 EVT CanonicalVT = VTys[SplatSize-1];
5472 // Build a canonical splat for this value.
5473 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5474 SmallVector<SDValue, 8> Ops;
5475 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5476 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5477 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5480 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5481 /// specified intrinsic ID.
5482 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5483 SelectionDAG &DAG, SDLoc dl,
5484 EVT DestVT = MVT::Other) {
5485 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5486 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5487 DAG.getConstant(IID, MVT::i32), Op);
5490 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5491 /// specified intrinsic ID.
5492 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5493 SelectionDAG &DAG, SDLoc dl,
5494 EVT DestVT = MVT::Other) {
5495 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5496 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5497 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5500 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5501 /// specified intrinsic ID.
5502 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5503 SDValue Op2, SelectionDAG &DAG,
5504 SDLoc dl, EVT DestVT = MVT::Other) {
5505 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5506 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5507 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5511 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5512 /// amount. The result has the specified value type.
5513 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5514 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5515 // Force LHS/RHS to be the right type.
5516 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5517 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5520 for (unsigned i = 0; i != 16; ++i)
5522 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5523 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5526 // If this is a case we can't handle, return null and let the default
5527 // expansion code take care of it. If we CAN select this case, and if it
5528 // selects to a single instruction, return Op. Otherwise, if we can codegen
5529 // this case more efficiently than a constant pool load, lower it to the
5530 // sequence of ops that should be used.
5531 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5532 SelectionDAG &DAG) const {
5534 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5535 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5537 // Check if this is a splat of a constant value.
5538 APInt APSplatBits, APSplatUndef;
5539 unsigned SplatBitSize;
5541 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5542 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5545 unsigned SplatBits = APSplatBits.getZExtValue();
5546 unsigned SplatUndef = APSplatUndef.getZExtValue();
5547 unsigned SplatSize = SplatBitSize / 8;
5549 // First, handle single instruction cases.
5552 if (SplatBits == 0) {
5553 // Canonicalize all zero vectors to be v4i32.
5554 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5555 SDValue Z = DAG.getConstant(0, MVT::i32);
5556 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5557 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5562 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5563 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5565 if (SextVal >= -16 && SextVal <= 15)
5566 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5569 // Two instruction sequences.
5571 // If this value is in the range [-32,30] and is even, use:
5572 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5573 // If this value is in the range [17,31] and is odd, use:
5574 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5575 // If this value is in the range [-31,-17] and is odd, use:
5576 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5577 // Note the last two are three-instruction sequences.
5578 if (SextVal >= -32 && SextVal <= 31) {
5579 // To avoid having these optimizations undone by constant folding,
5580 // we convert to a pseudo that will be expanded later into one of
5582 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5583 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5584 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5585 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5586 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5587 if (VT == Op.getValueType())
5590 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5593 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5594 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5596 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5597 // Make -1 and vspltisw -1:
5598 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5600 // Make the VSLW intrinsic, computing 0x8000_0000.
5601 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5604 // xor by OnesV to invert it.
5605 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5606 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5609 // The remaining cases assume either big endian element order or
5610 // a splat-size that equates to the element size of the vector
5611 // to be built. An example that doesn't work for little endian is
5612 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5613 // and a vector element size of 16 bits. The code below will
5614 // produce the vector in big endian element order, which for little
5615 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5617 // For now, just avoid these optimizations in that case.
5618 // FIXME: Develop correct optimizations for LE with mismatched
5619 // splat and element sizes.
5621 if (Subtarget.isLittleEndian() &&
5622 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5625 // Check to see if this is a wide variety of vsplti*, binop self cases.
5626 static const signed char SplatCsts[] = {
5627 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5628 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5631 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5632 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5633 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5634 int i = SplatCsts[idx];
5636 // Figure out what shift amount will be used by altivec if shifted by i in
5638 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5640 // vsplti + shl self.
5641 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5642 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5643 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5644 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5645 Intrinsic::ppc_altivec_vslw
5647 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5648 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5651 // vsplti + srl self.
5652 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5653 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5654 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5655 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5656 Intrinsic::ppc_altivec_vsrw
5658 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5659 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5662 // vsplti + sra self.
5663 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5664 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5665 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5666 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5667 Intrinsic::ppc_altivec_vsraw
5669 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5670 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5673 // vsplti + rol self.
5674 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5675 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5676 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5677 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5678 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5679 Intrinsic::ppc_altivec_vrlw
5681 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5682 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5685 // t = vsplti c, result = vsldoi t, t, 1
5686 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5687 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5688 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5690 // t = vsplti c, result = vsldoi t, t, 2
5691 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5692 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5693 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5695 // t = vsplti c, result = vsldoi t, t, 3
5696 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5697 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5698 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5705 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5706 /// the specified operations to build the shuffle.
5707 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5708 SDValue RHS, SelectionDAG &DAG,
5710 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5711 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5712 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5715 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5727 if (OpNum == OP_COPY) {
5728 if (LHSID == (1*9+2)*9+3) return LHS;
5729 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5733 SDValue OpLHS, OpRHS;
5734 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5735 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5739 default: llvm_unreachable("Unknown i32 permute!");
5741 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5742 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5743 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5744 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5747 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5748 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5749 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5750 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5753 for (unsigned i = 0; i != 16; ++i)
5754 ShufIdxs[i] = (i&3)+0;
5757 for (unsigned i = 0; i != 16; ++i)
5758 ShufIdxs[i] = (i&3)+4;
5761 for (unsigned i = 0; i != 16; ++i)
5762 ShufIdxs[i] = (i&3)+8;
5765 for (unsigned i = 0; i != 16; ++i)
5766 ShufIdxs[i] = (i&3)+12;
5769 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5771 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5773 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5775 EVT VT = OpLHS.getValueType();
5776 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5777 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5778 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5779 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5782 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5783 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5784 /// return the code it can be lowered into. Worst case, it can always be
5785 /// lowered into a vperm.
5786 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5787 SelectionDAG &DAG) const {
5789 SDValue V1 = Op.getOperand(0);
5790 SDValue V2 = Op.getOperand(1);
5791 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5792 EVT VT = Op.getValueType();
5793 bool isLittleEndian = Subtarget.isLittleEndian();
5795 // Cases that are handled by instructions that take permute immediates
5796 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5797 // selected by the instruction selector.
5798 if (V2.getOpcode() == ISD::UNDEF) {
5799 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5800 PPC::isSplatShuffleMask(SVOp, 2) ||
5801 PPC::isSplatShuffleMask(SVOp, 4) ||
5802 PPC::isVPKUWUMShuffleMask(SVOp, true, DAG) ||
5803 PPC::isVPKUHUMShuffleMask(SVOp, true, DAG) ||
5804 PPC::isVSLDOIShuffleMask(SVOp, true, DAG) != -1 ||
5805 PPC::isVMRGLShuffleMask(SVOp, 1, true, DAG) ||
5806 PPC::isVMRGLShuffleMask(SVOp, 2, true, DAG) ||
5807 PPC::isVMRGLShuffleMask(SVOp, 4, true, DAG) ||
5808 PPC::isVMRGHShuffleMask(SVOp, 1, true, DAG) ||
5809 PPC::isVMRGHShuffleMask(SVOp, 2, true, DAG) ||
5810 PPC::isVMRGHShuffleMask(SVOp, 4, true, DAG)) {
5815 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5816 // and produce a fixed permutation. If any of these match, do not lower to
5818 if (PPC::isVPKUWUMShuffleMask(SVOp, false, DAG) ||
5819 PPC::isVPKUHUMShuffleMask(SVOp, false, DAG) ||
5820 PPC::isVSLDOIShuffleMask(SVOp, false, DAG) != -1 ||
5821 PPC::isVMRGLShuffleMask(SVOp, 1, false, DAG) ||
5822 PPC::isVMRGLShuffleMask(SVOp, 2, false, DAG) ||
5823 PPC::isVMRGLShuffleMask(SVOp, 4, false, DAG) ||
5824 PPC::isVMRGHShuffleMask(SVOp, 1, false, DAG) ||
5825 PPC::isVMRGHShuffleMask(SVOp, 2, false, DAG) ||
5826 PPC::isVMRGHShuffleMask(SVOp, 4, false, DAG))
5829 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5830 // perfect shuffle table to emit an optimal matching sequence.
5831 ArrayRef<int> PermMask = SVOp->getMask();
5833 unsigned PFIndexes[4];
5834 bool isFourElementShuffle = true;
5835 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5836 unsigned EltNo = 8; // Start out undef.
5837 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5838 if (PermMask[i*4+j] < 0)
5839 continue; // Undef, ignore it.
5841 unsigned ByteSource = PermMask[i*4+j];
5842 if ((ByteSource & 3) != j) {
5843 isFourElementShuffle = false;
5848 EltNo = ByteSource/4;
5849 } else if (EltNo != ByteSource/4) {
5850 isFourElementShuffle = false;
5854 PFIndexes[i] = EltNo;
5857 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5858 // perfect shuffle vector to determine if it is cost effective to do this as
5859 // discrete instructions, or whether we should use a vperm.
5860 // For now, we skip this for little endian until such time as we have a
5861 // little-endian perfect shuffle table.
5862 if (isFourElementShuffle && !isLittleEndian) {
5863 // Compute the index in the perfect shuffle table.
5864 unsigned PFTableIndex =
5865 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5867 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5868 unsigned Cost = (PFEntry >> 30);
5870 // Determining when to avoid vperm is tricky. Many things affect the cost
5871 // of vperm, particularly how many times the perm mask needs to be computed.
5872 // For example, if the perm mask can be hoisted out of a loop or is already
5873 // used (perhaps because there are multiple permutes with the same shuffle
5874 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5875 // the loop requires an extra register.
5877 // As a compromise, we only emit discrete instructions if the shuffle can be
5878 // generated in 3 or fewer operations. When we have loop information
5879 // available, if this block is within a loop, we should avoid using vperm
5880 // for 3-operation perms and use a constant pool load instead.
5882 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5885 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5886 // vector that will get spilled to the constant pool.
5887 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5889 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5890 // that it is in input element units, not in bytes. Convert now.
5892 // For little endian, the order of the input vectors is reversed, and
5893 // the permutation mask is complemented with respect to 31. This is
5894 // necessary to produce proper semantics with the big-endian-biased vperm
5896 EVT EltVT = V1.getValueType().getVectorElementType();
5897 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5899 SmallVector<SDValue, 16> ResultMask;
5900 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5901 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5903 for (unsigned j = 0; j != BytesPerElement; ++j)
5905 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
5908 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5912 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5915 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
5918 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
5922 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5923 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5924 /// information about the intrinsic.
5925 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5927 unsigned IntrinsicID =
5928 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5931 switch (IntrinsicID) {
5932 default: return false;
5933 // Comparison predicates.
5934 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5935 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5936 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5937 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5938 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5939 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5940 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5941 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5942 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5943 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5944 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5945 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5946 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5948 // Normal Comparisons.
5949 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5950 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5951 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5952 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5953 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5954 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5955 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5956 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5957 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5958 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5959 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5960 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5961 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5966 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5967 /// lower, do it, otherwise return null.
5968 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5969 SelectionDAG &DAG) const {
5970 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5971 // opcode number of the comparison.
5975 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5976 return SDValue(); // Don't custom lower most intrinsics.
5978 // If this is a non-dot comparison, make the VCMP node and we are done.
5980 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5981 Op.getOperand(1), Op.getOperand(2),
5982 DAG.getConstant(CompareOpc, MVT::i32));
5983 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5986 // Create the PPCISD altivec 'dot' comparison node.
5988 Op.getOperand(2), // LHS
5989 Op.getOperand(3), // RHS
5990 DAG.getConstant(CompareOpc, MVT::i32)
5992 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5993 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
5995 // Now that we have the comparison, emit a copy from the CR to a GPR.
5996 // This is flagged to the above dot comparison.
5997 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5998 DAG.getRegister(PPC::CR6, MVT::i32),
5999 CompNode.getValue(1));
6001 // Unpack the result based on how the target uses it.
6002 unsigned BitNo; // Bit # of CR6.
6003 bool InvertBit; // Invert result?
6004 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6005 default: // Can't happen, don't crash on invalid number though.
6006 case 0: // Return the value of the EQ bit of CR6.
6007 BitNo = 0; InvertBit = false;
6009 case 1: // Return the inverted value of the EQ bit of CR6.
6010 BitNo = 0; InvertBit = true;
6012 case 2: // Return the value of the LT bit of CR6.
6013 BitNo = 2; InvertBit = false;
6015 case 3: // Return the inverted value of the LT bit of CR6.
6016 BitNo = 2; InvertBit = true;
6020 // Shift the bit into the low position.
6021 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6022 DAG.getConstant(8-(3-BitNo), MVT::i32));
6024 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6025 DAG.getConstant(1, MVT::i32));
6027 // If we are supposed to, toggle the bit.
6029 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6030 DAG.getConstant(1, MVT::i32));
6034 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6035 SelectionDAG &DAG) const {
6037 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6038 // instructions), but for smaller types, we need to first extend up to v2i32
6039 // before doing going farther.
6040 if (Op.getValueType() == MVT::v2i64) {
6041 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6042 if (ExtVT != MVT::v2i32) {
6043 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6044 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6045 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6046 ExtVT.getVectorElementType(), 4)));
6047 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6048 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6049 DAG.getValueType(MVT::v2i32));
6058 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6059 SelectionDAG &DAG) const {
6061 // Create a stack slot that is 16-byte aligned.
6062 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6063 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6064 EVT PtrVT = getPointerTy();
6065 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6067 // Store the input value into Value#0 of the stack slot.
6068 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6069 Op.getOperand(0), FIdx, MachinePointerInfo(),
6072 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6073 false, false, false, 0);
6076 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6078 if (Op.getValueType() == MVT::v4i32) {
6079 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6081 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6082 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6084 SDValue RHSSwap = // = vrlw RHS, 16
6085 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6087 // Shrinkify inputs to v8i16.
6088 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6089 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6090 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6092 // Low parts multiplied together, generating 32-bit results (we ignore the
6094 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6095 LHS, RHS, DAG, dl, MVT::v4i32);
6097 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6098 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6099 // Shift the high parts up 16 bits.
6100 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6102 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6103 } else if (Op.getValueType() == MVT::v8i16) {
6104 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6106 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6108 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6109 LHS, RHS, Zero, DAG, dl);
6110 } else if (Op.getValueType() == MVT::v16i8) {
6111 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6112 bool isLittleEndian = Subtarget.isLittleEndian();
6114 // Multiply the even 8-bit parts, producing 16-bit sums.
6115 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6116 LHS, RHS, DAG, dl, MVT::v8i16);
6117 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6119 // Multiply the odd 8-bit parts, producing 16-bit sums.
6120 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6121 LHS, RHS, DAG, dl, MVT::v8i16);
6122 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6124 // Merge the results together. Because vmuleub and vmuloub are
6125 // instructions with a big-endian bias, we must reverse the
6126 // element numbering and reverse the meaning of "odd" and "even"
6127 // when generating little endian code.
6129 for (unsigned i = 0; i != 8; ++i) {
6130 if (isLittleEndian) {
6132 Ops[i*2+1] = 2*i+16;
6135 Ops[i*2+1] = 2*i+1+16;
6139 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6141 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6143 llvm_unreachable("Unknown mul to lower!");
6147 /// LowerOperation - Provide custom lowering hooks for some operations.
6149 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6150 switch (Op.getOpcode()) {
6151 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6152 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6153 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6154 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6155 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6156 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6157 case ISD::SETCC: return LowerSETCC(Op, DAG);
6158 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6159 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6161 return LowerVASTART(Op, DAG, Subtarget);
6164 return LowerVAARG(Op, DAG, Subtarget);
6167 return LowerVACOPY(Op, DAG, Subtarget);
6169 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6170 case ISD::DYNAMIC_STACKALLOC:
6171 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6173 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6174 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6176 case ISD::LOAD: return LowerLOAD(Op, DAG);
6177 case ISD::STORE: return LowerSTORE(Op, DAG);
6178 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6179 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6180 case ISD::FP_TO_UINT:
6181 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6183 case ISD::UINT_TO_FP:
6184 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6185 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6187 // Lower 64-bit shifts.
6188 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6189 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6190 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6192 // Vector-related lowering.
6193 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6194 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6195 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6196 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6197 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6198 case ISD::MUL: return LowerMUL(Op, DAG);
6200 // For counter-based loop handling.
6201 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6203 // Frame & Return address.
6204 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6205 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6209 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6210 SmallVectorImpl<SDValue>&Results,
6211 SelectionDAG &DAG) const {
6212 const TargetMachine &TM = getTargetMachine();
6214 switch (N->getOpcode()) {
6216 llvm_unreachable("Do not know how to custom type legalize this operation!");
6217 case ISD::INTRINSIC_W_CHAIN: {
6218 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6219 Intrinsic::ppc_is_decremented_ctr_nonzero)
6222 assert(N->getValueType(0) == MVT::i1 &&
6223 "Unexpected result type for CTR decrement intrinsic");
6224 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6225 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6226 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6229 Results.push_back(NewInt);
6230 Results.push_back(NewInt.getValue(1));
6234 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6235 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6238 EVT VT = N->getValueType(0);
6240 if (VT == MVT::i64) {
6241 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6243 Results.push_back(NewNode);
6244 Results.push_back(NewNode.getValue(1));
6248 case ISD::FP_ROUND_INREG: {
6249 assert(N->getValueType(0) == MVT::ppcf128);
6250 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6251 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6252 MVT::f64, N->getOperand(0),
6253 DAG.getIntPtrConstant(0));
6254 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6255 MVT::f64, N->getOperand(0),
6256 DAG.getIntPtrConstant(1));
6258 // Add the two halves of the long double in round-to-zero mode.
6259 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6261 // We know the low half is about to be thrown away, so just use something
6263 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6267 case ISD::FP_TO_SINT:
6268 // LowerFP_TO_INT() can only handle f32 and f64.
6269 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6271 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6277 //===----------------------------------------------------------------------===//
6278 // Other Lowering Code
6279 //===----------------------------------------------------------------------===//
6282 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6283 bool is64bit, unsigned BinOpcode) const {
6284 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6285 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6287 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6288 MachineFunction *F = BB->getParent();
6289 MachineFunction::iterator It = BB;
6292 unsigned dest = MI->getOperand(0).getReg();
6293 unsigned ptrA = MI->getOperand(1).getReg();
6294 unsigned ptrB = MI->getOperand(2).getReg();
6295 unsigned incr = MI->getOperand(3).getReg();
6296 DebugLoc dl = MI->getDebugLoc();
6298 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6299 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6300 F->insert(It, loopMBB);
6301 F->insert(It, exitMBB);
6302 exitMBB->splice(exitMBB->begin(), BB,
6303 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6304 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6306 MachineRegisterInfo &RegInfo = F->getRegInfo();
6307 unsigned TmpReg = (!BinOpcode) ? incr :
6308 RegInfo.createVirtualRegister(
6309 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6310 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6314 // fallthrough --> loopMBB
6315 BB->addSuccessor(loopMBB);
6318 // l[wd]arx dest, ptr
6319 // add r0, dest, incr
6320 // st[wd]cx. r0, ptr
6322 // fallthrough --> exitMBB
6324 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6325 .addReg(ptrA).addReg(ptrB);
6327 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6328 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6329 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6330 BuildMI(BB, dl, TII->get(PPC::BCC))
6331 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6332 BB->addSuccessor(loopMBB);
6333 BB->addSuccessor(exitMBB);
6342 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6343 MachineBasicBlock *BB,
6344 bool is8bit, // operation
6345 unsigned BinOpcode) const {
6346 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6347 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6348 // In 64 bit mode we have to use 64 bits for addresses, even though the
6349 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6350 // registers without caring whether they're 32 or 64, but here we're
6351 // doing actual arithmetic on the addresses.
6352 bool is64bit = Subtarget.isPPC64();
6353 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6355 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6356 MachineFunction *F = BB->getParent();
6357 MachineFunction::iterator It = BB;
6360 unsigned dest = MI->getOperand(0).getReg();
6361 unsigned ptrA = MI->getOperand(1).getReg();
6362 unsigned ptrB = MI->getOperand(2).getReg();
6363 unsigned incr = MI->getOperand(3).getReg();
6364 DebugLoc dl = MI->getDebugLoc();
6366 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6367 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6368 F->insert(It, loopMBB);
6369 F->insert(It, exitMBB);
6370 exitMBB->splice(exitMBB->begin(), BB,
6371 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6372 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6374 MachineRegisterInfo &RegInfo = F->getRegInfo();
6375 const TargetRegisterClass *RC =
6376 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6377 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6378 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6379 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6380 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6381 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6382 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6383 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6384 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6385 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6386 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6387 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6388 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6390 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6394 // fallthrough --> loopMBB
6395 BB->addSuccessor(loopMBB);
6397 // The 4-byte load must be aligned, while a char or short may be
6398 // anywhere in the word. Hence all this nasty bookkeeping code.
6399 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6400 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6401 // xori shift, shift1, 24 [16]
6402 // rlwinm ptr, ptr1, 0, 0, 29
6403 // slw incr2, incr, shift
6404 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6405 // slw mask, mask2, shift
6407 // lwarx tmpDest, ptr
6408 // add tmp, tmpDest, incr2
6409 // andc tmp2, tmpDest, mask
6410 // and tmp3, tmp, mask
6411 // or tmp4, tmp3, tmp2
6414 // fallthrough --> exitMBB
6415 // srw dest, tmpDest, shift
6416 if (ptrA != ZeroReg) {
6417 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6418 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6419 .addReg(ptrA).addReg(ptrB);
6423 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6424 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6425 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6426 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6428 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6429 .addReg(Ptr1Reg).addImm(0).addImm(61);
6431 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6432 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6433 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6434 .addReg(incr).addReg(ShiftReg);
6436 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6438 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6439 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6441 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6442 .addReg(Mask2Reg).addReg(ShiftReg);
6445 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6446 .addReg(ZeroReg).addReg(PtrReg);
6448 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6449 .addReg(Incr2Reg).addReg(TmpDestReg);
6450 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6451 .addReg(TmpDestReg).addReg(MaskReg);
6452 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6453 .addReg(TmpReg).addReg(MaskReg);
6454 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6455 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6456 BuildMI(BB, dl, TII->get(PPC::STWCX))
6457 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6458 BuildMI(BB, dl, TII->get(PPC::BCC))
6459 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6460 BB->addSuccessor(loopMBB);
6461 BB->addSuccessor(exitMBB);
6466 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6471 llvm::MachineBasicBlock*
6472 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6473 MachineBasicBlock *MBB) const {
6474 DebugLoc DL = MI->getDebugLoc();
6475 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6477 MachineFunction *MF = MBB->getParent();
6478 MachineRegisterInfo &MRI = MF->getRegInfo();
6480 const BasicBlock *BB = MBB->getBasicBlock();
6481 MachineFunction::iterator I = MBB;
6485 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6486 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6488 unsigned DstReg = MI->getOperand(0).getReg();
6489 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6490 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6491 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6492 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6494 MVT PVT = getPointerTy();
6495 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6496 "Invalid Pointer Size!");
6497 // For v = setjmp(buf), we generate
6500 // SjLjSetup mainMBB
6506 // buf[LabelOffset] = LR
6510 // v = phi(main, restore)
6513 MachineBasicBlock *thisMBB = MBB;
6514 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6515 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6516 MF->insert(I, mainMBB);
6517 MF->insert(I, sinkMBB);
6519 MachineInstrBuilder MIB;
6521 // Transfer the remainder of BB and its successor edges to sinkMBB.
6522 sinkMBB->splice(sinkMBB->begin(), MBB,
6523 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6524 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6526 // Note that the structure of the jmp_buf used here is not compatible
6527 // with that used by libc, and is not designed to be. Specifically, it
6528 // stores only those 'reserved' registers that LLVM does not otherwise
6529 // understand how to spill. Also, by convention, by the time this
6530 // intrinsic is called, Clang has already stored the frame address in the
6531 // first slot of the buffer and stack address in the third. Following the
6532 // X86 target code, we'll store the jump address in the second slot. We also
6533 // need to save the TOC pointer (R2) to handle jumps between shared
6534 // libraries, and that will be stored in the fourth slot. The thread
6535 // identifier (R13) is not affected.
6538 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6539 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6540 const int64_t BPOffset = 4 * PVT.getStoreSize();
6542 // Prepare IP either in reg.
6543 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6544 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6545 unsigned BufReg = MI->getOperand(1).getReg();
6547 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6548 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6552 MIB.setMemRefs(MMOBegin, MMOEnd);
6555 // Naked functions never have a base pointer, and so we use r1. For all
6556 // other functions, this decision must be delayed until during PEI.
6558 if (MF->getFunction()->getAttributes().hasAttribute(
6559 AttributeSet::FunctionIndex, Attribute::Naked))
6560 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6562 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6564 MIB = BuildMI(*thisMBB, MI, DL,
6565 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6569 MIB.setMemRefs(MMOBegin, MMOEnd);
6572 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6573 const PPCRegisterInfo *TRI =
6574 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6575 MIB.addRegMask(TRI->getNoPreservedMask());
6577 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6579 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6581 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6583 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6584 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6588 MIB = BuildMI(mainMBB, DL,
6589 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6592 if (Subtarget.isPPC64()) {
6593 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6595 .addImm(LabelOffset)
6598 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6600 .addImm(LabelOffset)
6604 MIB.setMemRefs(MMOBegin, MMOEnd);
6606 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6607 mainMBB->addSuccessor(sinkMBB);
6610 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6611 TII->get(PPC::PHI), DstReg)
6612 .addReg(mainDstReg).addMBB(mainMBB)
6613 .addReg(restoreDstReg).addMBB(thisMBB);
6615 MI->eraseFromParent();
6620 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6621 MachineBasicBlock *MBB) const {
6622 DebugLoc DL = MI->getDebugLoc();
6623 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6625 MachineFunction *MF = MBB->getParent();
6626 MachineRegisterInfo &MRI = MF->getRegInfo();
6629 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6630 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6632 MVT PVT = getPointerTy();
6633 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6634 "Invalid Pointer Size!");
6636 const TargetRegisterClass *RC =
6637 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6638 unsigned Tmp = MRI.createVirtualRegister(RC);
6639 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6640 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6641 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6642 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6644 MachineInstrBuilder MIB;
6646 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6647 const int64_t SPOffset = 2 * PVT.getStoreSize();
6648 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6649 const int64_t BPOffset = 4 * PVT.getStoreSize();
6651 unsigned BufReg = MI->getOperand(0).getReg();
6653 // Reload FP (the jumped-to function may not have had a
6654 // frame pointer, and if so, then its r31 will be restored
6656 if (PVT == MVT::i64) {
6657 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6661 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6665 MIB.setMemRefs(MMOBegin, MMOEnd);
6668 if (PVT == MVT::i64) {
6669 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6670 .addImm(LabelOffset)
6673 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6674 .addImm(LabelOffset)
6677 MIB.setMemRefs(MMOBegin, MMOEnd);
6680 if (PVT == MVT::i64) {
6681 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6685 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6689 MIB.setMemRefs(MMOBegin, MMOEnd);
6692 if (PVT == MVT::i64) {
6693 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6697 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6701 MIB.setMemRefs(MMOBegin, MMOEnd);
6704 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
6705 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6709 MIB.setMemRefs(MMOBegin, MMOEnd);
6713 BuildMI(*MBB, MI, DL,
6714 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6715 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6717 MI->eraseFromParent();
6722 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6723 MachineBasicBlock *BB) const {
6724 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6725 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6726 return emitEHSjLjSetJmp(MI, BB);
6727 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6728 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6729 return emitEHSjLjLongJmp(MI, BB);
6732 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6734 // To "insert" these instructions we actually have to insert their
6735 // control-flow patterns.
6736 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6737 MachineFunction::iterator It = BB;
6740 MachineFunction *F = BB->getParent();
6742 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6743 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6744 MI->getOpcode() == PPC::SELECT_I4 ||
6745 MI->getOpcode() == PPC::SELECT_I8)) {
6746 SmallVector<MachineOperand, 2> Cond;
6747 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6748 MI->getOpcode() == PPC::SELECT_CC_I8)
6749 Cond.push_back(MI->getOperand(4));
6751 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
6752 Cond.push_back(MI->getOperand(1));
6754 DebugLoc dl = MI->getDebugLoc();
6755 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6756 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6757 Cond, MI->getOperand(2).getReg(),
6758 MI->getOperand(3).getReg());
6759 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6760 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6761 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6762 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6763 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
6764 MI->getOpcode() == PPC::SELECT_I4 ||
6765 MI->getOpcode() == PPC::SELECT_I8 ||
6766 MI->getOpcode() == PPC::SELECT_F4 ||
6767 MI->getOpcode() == PPC::SELECT_F8 ||
6768 MI->getOpcode() == PPC::SELECT_VRRC) {
6769 // The incoming instruction knows the destination vreg to set, the
6770 // condition code register to branch on, the true/false values to
6771 // select between, and a branch opcode to use.
6776 // cmpTY ccX, r1, r2
6778 // fallthrough --> copy0MBB
6779 MachineBasicBlock *thisMBB = BB;
6780 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6781 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6782 DebugLoc dl = MI->getDebugLoc();
6783 F->insert(It, copy0MBB);
6784 F->insert(It, sinkMBB);
6786 // Transfer the remainder of BB and its successor edges to sinkMBB.
6787 sinkMBB->splice(sinkMBB->begin(), BB,
6788 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6789 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6791 // Next, add the true and fallthrough blocks as its successors.
6792 BB->addSuccessor(copy0MBB);
6793 BB->addSuccessor(sinkMBB);
6795 if (MI->getOpcode() == PPC::SELECT_I4 ||
6796 MI->getOpcode() == PPC::SELECT_I8 ||
6797 MI->getOpcode() == PPC::SELECT_F4 ||
6798 MI->getOpcode() == PPC::SELECT_F8 ||
6799 MI->getOpcode() == PPC::SELECT_VRRC) {
6800 BuildMI(BB, dl, TII->get(PPC::BC))
6801 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6803 unsigned SelectPred = MI->getOperand(4).getImm();
6804 BuildMI(BB, dl, TII->get(PPC::BCC))
6805 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6809 // %FalseValue = ...
6810 // # fallthrough to sinkMBB
6813 // Update machine-CFG edges
6814 BB->addSuccessor(sinkMBB);
6817 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6820 BuildMI(*BB, BB->begin(), dl,
6821 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6822 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6823 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6825 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6826 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6827 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6828 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6829 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6830 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6831 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6832 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6834 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6835 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6836 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6837 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6838 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6839 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6840 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6841 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6843 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6844 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6845 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6846 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6847 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6848 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6849 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6850 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6852 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6853 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6854 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6855 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6856 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6857 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6858 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6859 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6861 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6862 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6863 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6864 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6865 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6866 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6867 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6868 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6870 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6871 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6872 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6873 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6874 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6875 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6876 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6877 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6879 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6880 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6881 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6882 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6883 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6884 BB = EmitAtomicBinary(MI, BB, false, 0);
6885 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6886 BB = EmitAtomicBinary(MI, BB, true, 0);
6888 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6889 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6890 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6892 unsigned dest = MI->getOperand(0).getReg();
6893 unsigned ptrA = MI->getOperand(1).getReg();
6894 unsigned ptrB = MI->getOperand(2).getReg();
6895 unsigned oldval = MI->getOperand(3).getReg();
6896 unsigned newval = MI->getOperand(4).getReg();
6897 DebugLoc dl = MI->getDebugLoc();
6899 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6900 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6901 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6902 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6903 F->insert(It, loop1MBB);
6904 F->insert(It, loop2MBB);
6905 F->insert(It, midMBB);
6906 F->insert(It, exitMBB);
6907 exitMBB->splice(exitMBB->begin(), BB,
6908 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6909 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6913 // fallthrough --> loopMBB
6914 BB->addSuccessor(loop1MBB);
6917 // l[wd]arx dest, ptr
6918 // cmp[wd] dest, oldval
6921 // st[wd]cx. newval, ptr
6925 // st[wd]cx. dest, ptr
6928 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6929 .addReg(ptrA).addReg(ptrB);
6930 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6931 .addReg(oldval).addReg(dest);
6932 BuildMI(BB, dl, TII->get(PPC::BCC))
6933 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6934 BB->addSuccessor(loop2MBB);
6935 BB->addSuccessor(midMBB);
6938 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6939 .addReg(newval).addReg(ptrA).addReg(ptrB);
6940 BuildMI(BB, dl, TII->get(PPC::BCC))
6941 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6942 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6943 BB->addSuccessor(loop1MBB);
6944 BB->addSuccessor(exitMBB);
6947 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6948 .addReg(dest).addReg(ptrA).addReg(ptrB);
6949 BB->addSuccessor(exitMBB);
6954 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6955 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6956 // We must use 64-bit registers for addresses when targeting 64-bit,
6957 // since we're actually doing arithmetic on them. Other registers
6959 bool is64bit = Subtarget.isPPC64();
6960 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6962 unsigned dest = MI->getOperand(0).getReg();
6963 unsigned ptrA = MI->getOperand(1).getReg();
6964 unsigned ptrB = MI->getOperand(2).getReg();
6965 unsigned oldval = MI->getOperand(3).getReg();
6966 unsigned newval = MI->getOperand(4).getReg();
6967 DebugLoc dl = MI->getDebugLoc();
6969 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6970 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6971 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6972 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6973 F->insert(It, loop1MBB);
6974 F->insert(It, loop2MBB);
6975 F->insert(It, midMBB);
6976 F->insert(It, exitMBB);
6977 exitMBB->splice(exitMBB->begin(), BB,
6978 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6979 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6981 MachineRegisterInfo &RegInfo = F->getRegInfo();
6982 const TargetRegisterClass *RC =
6983 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6984 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6985 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6986 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6987 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6988 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6989 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6990 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6991 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6992 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6993 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6994 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6995 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6996 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6997 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6999 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7000 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7003 // fallthrough --> loopMBB
7004 BB->addSuccessor(loop1MBB);
7006 // The 4-byte load must be aligned, while a char or short may be
7007 // anywhere in the word. Hence all this nasty bookkeeping code.
7008 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7009 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7010 // xori shift, shift1, 24 [16]
7011 // rlwinm ptr, ptr1, 0, 0, 29
7012 // slw newval2, newval, shift
7013 // slw oldval2, oldval,shift
7014 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7015 // slw mask, mask2, shift
7016 // and newval3, newval2, mask
7017 // and oldval3, oldval2, mask
7019 // lwarx tmpDest, ptr
7020 // and tmp, tmpDest, mask
7021 // cmpw tmp, oldval3
7024 // andc tmp2, tmpDest, mask
7025 // or tmp4, tmp2, newval3
7030 // stwcx. tmpDest, ptr
7032 // srw dest, tmpDest, shift
7033 if (ptrA != ZeroReg) {
7034 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7035 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7036 .addReg(ptrA).addReg(ptrB);
7040 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7041 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7042 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7043 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7045 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7046 .addReg(Ptr1Reg).addImm(0).addImm(61);
7048 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7049 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7050 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7051 .addReg(newval).addReg(ShiftReg);
7052 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7053 .addReg(oldval).addReg(ShiftReg);
7055 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7057 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7058 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7059 .addReg(Mask3Reg).addImm(65535);
7061 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7062 .addReg(Mask2Reg).addReg(ShiftReg);
7063 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7064 .addReg(NewVal2Reg).addReg(MaskReg);
7065 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7066 .addReg(OldVal2Reg).addReg(MaskReg);
7069 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7070 .addReg(ZeroReg).addReg(PtrReg);
7071 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7072 .addReg(TmpDestReg).addReg(MaskReg);
7073 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7074 .addReg(TmpReg).addReg(OldVal3Reg);
7075 BuildMI(BB, dl, TII->get(PPC::BCC))
7076 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7077 BB->addSuccessor(loop2MBB);
7078 BB->addSuccessor(midMBB);
7081 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7082 .addReg(TmpDestReg).addReg(MaskReg);
7083 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7084 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7085 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7086 .addReg(ZeroReg).addReg(PtrReg);
7087 BuildMI(BB, dl, TII->get(PPC::BCC))
7088 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7089 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7090 BB->addSuccessor(loop1MBB);
7091 BB->addSuccessor(exitMBB);
7094 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7095 .addReg(ZeroReg).addReg(PtrReg);
7096 BB->addSuccessor(exitMBB);
7101 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7103 } else if (MI->getOpcode() == PPC::FADDrtz) {
7104 // This pseudo performs an FADD with rounding mode temporarily forced
7105 // to round-to-zero. We emit this via custom inserter since the FPSCR
7106 // is not modeled at the SelectionDAG level.
7107 unsigned Dest = MI->getOperand(0).getReg();
7108 unsigned Src1 = MI->getOperand(1).getReg();
7109 unsigned Src2 = MI->getOperand(2).getReg();
7110 DebugLoc dl = MI->getDebugLoc();
7112 MachineRegisterInfo &RegInfo = F->getRegInfo();
7113 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7115 // Save FPSCR value.
7116 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7118 // Set rounding mode to round-to-zero.
7119 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7120 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7122 // Perform addition.
7123 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7125 // Restore FPSCR value.
7126 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7127 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7128 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7129 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7130 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7131 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7132 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7133 PPC::ANDIo8 : PPC::ANDIo;
7134 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7135 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7137 MachineRegisterInfo &RegInfo = F->getRegInfo();
7138 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7139 &PPC::GPRCRegClass :
7140 &PPC::G8RCRegClass);
7142 DebugLoc dl = MI->getDebugLoc();
7143 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7144 .addReg(MI->getOperand(1).getReg()).addImm(1);
7145 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7146 MI->getOperand(0).getReg())
7147 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7149 llvm_unreachable("Unexpected instr type to insert");
7152 MI->eraseFromParent(); // The pseudo instruction is gone now.
7156 //===----------------------------------------------------------------------===//
7157 // Target Optimization Hooks
7158 //===----------------------------------------------------------------------===//
7160 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
7161 DAGCombinerInfo &DCI) const {
7162 if (DCI.isAfterLegalizeVectorOps())
7165 EVT VT = Op.getValueType();
7167 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7168 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7169 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7170 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7172 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7173 // For the reciprocal, we need to find the zero of the function:
7174 // F(X) = A X - 1 [which has a zero at X = 1/A]
7176 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7177 // does not require additional intermediate precision]
7179 // Convergence is quadratic, so we essentially double the number of digits
7180 // correct after every iteration. The minimum architected relative
7181 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7182 // 23 digits and double has 52 digits.
7183 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7184 if (VT.getScalarType() == MVT::f64)
7187 SelectionDAG &DAG = DCI.DAG;
7191 DAG.getConstantFP(1.0, VT.getScalarType());
7192 if (VT.isVector()) {
7193 assert(VT.getVectorNumElements() == 4 &&
7194 "Unknown vector type");
7195 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7196 FPOne, FPOne, FPOne, FPOne);
7199 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
7200 DCI.AddToWorklist(Est.getNode());
7202 // Newton iterations: Est = Est + Est (1 - Arg * Est)
7203 for (int i = 0; i < Iterations; ++i) {
7204 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
7205 DCI.AddToWorklist(NewEst.getNode());
7207 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
7208 DCI.AddToWorklist(NewEst.getNode());
7210 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7211 DCI.AddToWorklist(NewEst.getNode());
7213 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
7214 DCI.AddToWorklist(Est.getNode());
7223 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
7224 DAGCombinerInfo &DCI) const {
7225 if (DCI.isAfterLegalizeVectorOps())
7228 EVT VT = Op.getValueType();
7230 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7231 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7232 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7233 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7235 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7236 // For the reciprocal sqrt, we need to find the zero of the function:
7237 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7239 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7240 // As a result, we precompute A/2 prior to the iteration loop.
7242 // Convergence is quadratic, so we essentially double the number of digits
7243 // correct after every iteration. The minimum architected relative
7244 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7245 // 23 digits and double has 52 digits.
7246 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7247 if (VT.getScalarType() == MVT::f64)
7250 SelectionDAG &DAG = DCI.DAG;
7253 SDValue FPThreeHalves =
7254 DAG.getConstantFP(1.5, VT.getScalarType());
7255 if (VT.isVector()) {
7256 assert(VT.getVectorNumElements() == 4 &&
7257 "Unknown vector type");
7258 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7259 FPThreeHalves, FPThreeHalves,
7260 FPThreeHalves, FPThreeHalves);
7263 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7264 DCI.AddToWorklist(Est.getNode());
7266 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7267 // this entire sequence requires only one FP constant.
7268 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7269 DCI.AddToWorklist(HalfArg.getNode());
7271 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7272 DCI.AddToWorklist(HalfArg.getNode());
7274 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7275 for (int i = 0; i < Iterations; ++i) {
7276 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7277 DCI.AddToWorklist(NewEst.getNode());
7279 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7280 DCI.AddToWorklist(NewEst.getNode());
7282 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7283 DCI.AddToWorklist(NewEst.getNode());
7285 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7286 DCI.AddToWorklist(Est.getNode());
7295 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7296 // not enforce equality of the chain operands.
7297 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
7298 unsigned Bytes, int Dist,
7299 SelectionDAG &DAG) {
7300 EVT VT = LS->getMemoryVT();
7301 if (VT.getSizeInBits() / 8 != Bytes)
7304 SDValue Loc = LS->getBasePtr();
7305 SDValue BaseLoc = Base->getBasePtr();
7306 if (Loc.getOpcode() == ISD::FrameIndex) {
7307 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7309 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7310 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7311 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7312 int FS = MFI->getObjectSize(FI);
7313 int BFS = MFI->getObjectSize(BFI);
7314 if (FS != BFS || FS != (int)Bytes) return false;
7315 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7319 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7320 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7323 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7324 const GlobalValue *GV1 = nullptr;
7325 const GlobalValue *GV2 = nullptr;
7326 int64_t Offset1 = 0;
7327 int64_t Offset2 = 0;
7328 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7329 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7330 if (isGA1 && isGA2 && GV1 == GV2)
7331 return Offset1 == (Offset2 + Dist*Bytes);
7335 // Return true is there is a nearyby consecutive load to the one provided
7336 // (regardless of alignment). We search up and down the chain, looking though
7337 // token factors and other loads (but nothing else). As a result, a true
7338 // results indicates that it is safe to create a new consecutive load adjacent
7339 // to the load provided.
7340 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7341 SDValue Chain = LD->getChain();
7342 EVT VT = LD->getMemoryVT();
7344 SmallSet<SDNode *, 16> LoadRoots;
7345 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7346 SmallSet<SDNode *, 16> Visited;
7348 // First, search up the chain, branching to follow all token-factor operands.
7349 // If we find a consecutive load, then we're done, otherwise, record all
7350 // nodes just above the top-level loads and token factors.
7351 while (!Queue.empty()) {
7352 SDNode *ChainNext = Queue.pop_back_val();
7353 if (!Visited.insert(ChainNext))
7356 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
7357 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7360 if (!Visited.count(ChainLD->getChain().getNode()))
7361 Queue.push_back(ChainLD->getChain().getNode());
7362 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7363 for (SDNode::op_iterator O = ChainNext->op_begin(),
7364 OE = ChainNext->op_end(); O != OE; ++O)
7365 if (!Visited.count(O->getNode()))
7366 Queue.push_back(O->getNode());
7368 LoadRoots.insert(ChainNext);
7371 // Second, search down the chain, starting from the top-level nodes recorded
7372 // in the first phase. These top-level nodes are the nodes just above all
7373 // loads and token factors. Starting with their uses, recursively look though
7374 // all loads (just the chain uses) and token factors to find a consecutive
7379 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7380 IE = LoadRoots.end(); I != IE; ++I) {
7381 Queue.push_back(*I);
7383 while (!Queue.empty()) {
7384 SDNode *LoadRoot = Queue.pop_back_val();
7385 if (!Visited.insert(LoadRoot))
7388 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
7389 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7392 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7393 UE = LoadRoot->use_end(); UI != UE; ++UI)
7394 if (((isa<LoadSDNode>(*UI) &&
7395 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7396 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7397 Queue.push_back(*UI);
7404 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7405 DAGCombinerInfo &DCI) const {
7406 SelectionDAG &DAG = DCI.DAG;
7409 assert(Subtarget.useCRBits() &&
7410 "Expecting to be tracking CR bits");
7411 // If we're tracking CR bits, we need to be careful that we don't have:
7412 // trunc(binary-ops(zext(x), zext(y)))
7414 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7415 // such that we're unnecessarily moving things into GPRs when it would be
7416 // better to keep them in CR bits.
7418 // Note that trunc here can be an actual i1 trunc, or can be the effective
7419 // truncation that comes from a setcc or select_cc.
7420 if (N->getOpcode() == ISD::TRUNCATE &&
7421 N->getValueType(0) != MVT::i1)
7424 if (N->getOperand(0).getValueType() != MVT::i32 &&
7425 N->getOperand(0).getValueType() != MVT::i64)
7428 if (N->getOpcode() == ISD::SETCC ||
7429 N->getOpcode() == ISD::SELECT_CC) {
7430 // If we're looking at a comparison, then we need to make sure that the
7431 // high bits (all except for the first) don't matter the result.
7433 cast<CondCodeSDNode>(N->getOperand(
7434 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7435 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7437 if (ISD::isSignedIntSetCC(CC)) {
7438 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7439 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7441 } else if (ISD::isUnsignedIntSetCC(CC)) {
7442 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7443 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7444 !DAG.MaskedValueIsZero(N->getOperand(1),
7445 APInt::getHighBitsSet(OpBits, OpBits-1)))
7448 // This is neither a signed nor an unsigned comparison, just make sure
7449 // that the high bits are equal.
7450 APInt Op1Zero, Op1One;
7451 APInt Op2Zero, Op2One;
7452 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7453 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7455 // We don't really care about what is known about the first bit (if
7456 // anything), so clear it in all masks prior to comparing them.
7457 Op1Zero.clearBit(0); Op1One.clearBit(0);
7458 Op2Zero.clearBit(0); Op2One.clearBit(0);
7460 if (Op1Zero != Op2Zero || Op1One != Op2One)
7465 // We now know that the higher-order bits are irrelevant, we just need to
7466 // make sure that all of the intermediate operations are bit operations, and
7467 // all inputs are extensions.
7468 if (N->getOperand(0).getOpcode() != ISD::AND &&
7469 N->getOperand(0).getOpcode() != ISD::OR &&
7470 N->getOperand(0).getOpcode() != ISD::XOR &&
7471 N->getOperand(0).getOpcode() != ISD::SELECT &&
7472 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7473 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7474 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7475 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7476 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7479 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7480 N->getOperand(1).getOpcode() != ISD::AND &&
7481 N->getOperand(1).getOpcode() != ISD::OR &&
7482 N->getOperand(1).getOpcode() != ISD::XOR &&
7483 N->getOperand(1).getOpcode() != ISD::SELECT &&
7484 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7485 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7486 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7487 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7488 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7491 SmallVector<SDValue, 4> Inputs;
7492 SmallVector<SDValue, 8> BinOps, PromOps;
7493 SmallPtrSet<SDNode *, 16> Visited;
7495 for (unsigned i = 0; i < 2; ++i) {
7496 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7497 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7498 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7499 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7500 isa<ConstantSDNode>(N->getOperand(i)))
7501 Inputs.push_back(N->getOperand(i));
7503 BinOps.push_back(N->getOperand(i));
7505 if (N->getOpcode() == ISD::TRUNCATE)
7509 // Visit all inputs, collect all binary operations (and, or, xor and
7510 // select) that are all fed by extensions.
7511 while (!BinOps.empty()) {
7512 SDValue BinOp = BinOps.back();
7515 if (!Visited.insert(BinOp.getNode()))
7518 PromOps.push_back(BinOp);
7520 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7521 // The condition of the select is not promoted.
7522 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7524 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7527 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7528 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7529 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7530 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7531 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7532 Inputs.push_back(BinOp.getOperand(i));
7533 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7534 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7535 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7536 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7537 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7538 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7539 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7540 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7541 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7542 BinOps.push_back(BinOp.getOperand(i));
7544 // We have an input that is not an extension or another binary
7545 // operation; we'll abort this transformation.
7551 // Make sure that this is a self-contained cluster of operations (which
7552 // is not quite the same thing as saying that everything has only one
7554 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7555 if (isa<ConstantSDNode>(Inputs[i]))
7558 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7559 UE = Inputs[i].getNode()->use_end();
7562 if (User != N && !Visited.count(User))
7565 // Make sure that we're not going to promote the non-output-value
7566 // operand(s) or SELECT or SELECT_CC.
7567 // FIXME: Although we could sometimes handle this, and it does occur in
7568 // practice that one of the condition inputs to the select is also one of
7569 // the outputs, we currently can't deal with this.
7570 if (User->getOpcode() == ISD::SELECT) {
7571 if (User->getOperand(0) == Inputs[i])
7573 } else if (User->getOpcode() == ISD::SELECT_CC) {
7574 if (User->getOperand(0) == Inputs[i] ||
7575 User->getOperand(1) == Inputs[i])
7581 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7582 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7583 UE = PromOps[i].getNode()->use_end();
7586 if (User != N && !Visited.count(User))
7589 // Make sure that we're not going to promote the non-output-value
7590 // operand(s) or SELECT or SELECT_CC.
7591 // FIXME: Although we could sometimes handle this, and it does occur in
7592 // practice that one of the condition inputs to the select is also one of
7593 // the outputs, we currently can't deal with this.
7594 if (User->getOpcode() == ISD::SELECT) {
7595 if (User->getOperand(0) == PromOps[i])
7597 } else if (User->getOpcode() == ISD::SELECT_CC) {
7598 if (User->getOperand(0) == PromOps[i] ||
7599 User->getOperand(1) == PromOps[i])
7605 // Replace all inputs with the extension operand.
7606 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7607 // Constants may have users outside the cluster of to-be-promoted nodes,
7608 // and so we need to replace those as we do the promotions.
7609 if (isa<ConstantSDNode>(Inputs[i]))
7612 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7615 // Replace all operations (these are all the same, but have a different
7616 // (i1) return type). DAG.getNode will validate that the types of
7617 // a binary operator match, so go through the list in reverse so that
7618 // we've likely promoted both operands first. Any intermediate truncations or
7619 // extensions disappear.
7620 while (!PromOps.empty()) {
7621 SDValue PromOp = PromOps.back();
7624 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7625 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7626 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7627 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7628 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7629 PromOp.getOperand(0).getValueType() != MVT::i1) {
7630 // The operand is not yet ready (see comment below).
7631 PromOps.insert(PromOps.begin(), PromOp);
7635 SDValue RepValue = PromOp.getOperand(0);
7636 if (isa<ConstantSDNode>(RepValue))
7637 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7639 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7644 switch (PromOp.getOpcode()) {
7645 default: C = 0; break;
7646 case ISD::SELECT: C = 1; break;
7647 case ISD::SELECT_CC: C = 2; break;
7650 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7651 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7652 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7653 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7654 // The to-be-promoted operands of this node have not yet been
7655 // promoted (this should be rare because we're going through the
7656 // list backward, but if one of the operands has several users in
7657 // this cluster of to-be-promoted nodes, it is possible).
7658 PromOps.insert(PromOps.begin(), PromOp);
7662 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7663 PromOp.getNode()->op_end());
7665 // If there are any constant inputs, make sure they're replaced now.
7666 for (unsigned i = 0; i < 2; ++i)
7667 if (isa<ConstantSDNode>(Ops[C+i]))
7668 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7670 DAG.ReplaceAllUsesOfValueWith(PromOp,
7671 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
7674 // Now we're left with the initial truncation itself.
7675 if (N->getOpcode() == ISD::TRUNCATE)
7676 return N->getOperand(0);
7678 // Otherwise, this is a comparison. The operands to be compared have just
7679 // changed type (to i1), but everything else is the same.
7680 return SDValue(N, 0);
7683 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7684 DAGCombinerInfo &DCI) const {
7685 SelectionDAG &DAG = DCI.DAG;
7688 // If we're tracking CR bits, we need to be careful that we don't have:
7689 // zext(binary-ops(trunc(x), trunc(y)))
7691 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
7692 // such that we're unnecessarily moving things into CR bits that can more
7693 // efficiently stay in GPRs. Note that if we're not certain that the high
7694 // bits are set as required by the final extension, we still may need to do
7695 // some masking to get the proper behavior.
7697 // This same functionality is important on PPC64 when dealing with
7698 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
7699 // the return values of functions. Because it is so similar, it is handled
7702 if (N->getValueType(0) != MVT::i32 &&
7703 N->getValueType(0) != MVT::i64)
7706 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
7707 Subtarget.useCRBits()) ||
7708 (N->getOperand(0).getValueType() == MVT::i32 &&
7709 Subtarget.isPPC64())))
7712 if (N->getOperand(0).getOpcode() != ISD::AND &&
7713 N->getOperand(0).getOpcode() != ISD::OR &&
7714 N->getOperand(0).getOpcode() != ISD::XOR &&
7715 N->getOperand(0).getOpcode() != ISD::SELECT &&
7716 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
7719 SmallVector<SDValue, 4> Inputs;
7720 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
7721 SmallPtrSet<SDNode *, 16> Visited;
7723 // Visit all inputs, collect all binary operations (and, or, xor and
7724 // select) that are all fed by truncations.
7725 while (!BinOps.empty()) {
7726 SDValue BinOp = BinOps.back();
7729 if (!Visited.insert(BinOp.getNode()))
7732 PromOps.push_back(BinOp);
7734 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7735 // The condition of the select is not promoted.
7736 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7738 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7741 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7742 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7743 Inputs.push_back(BinOp.getOperand(i));
7744 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7745 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7746 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7747 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7748 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
7749 BinOps.push_back(BinOp.getOperand(i));
7751 // We have an input that is not a truncation or another binary
7752 // operation; we'll abort this transformation.
7758 // Make sure that this is a self-contained cluster of operations (which
7759 // is not quite the same thing as saying that everything has only one
7761 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7762 if (isa<ConstantSDNode>(Inputs[i]))
7765 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7766 UE = Inputs[i].getNode()->use_end();
7769 if (User != N && !Visited.count(User))
7772 // Make sure that we're not going to promote the non-output-value
7773 // operand(s) or SELECT or SELECT_CC.
7774 // FIXME: Although we could sometimes handle this, and it does occur in
7775 // practice that one of the condition inputs to the select is also one of
7776 // the outputs, we currently can't deal with this.
7777 if (User->getOpcode() == ISD::SELECT) {
7778 if (User->getOperand(0) == Inputs[i])
7780 } else if (User->getOpcode() == ISD::SELECT_CC) {
7781 if (User->getOperand(0) == Inputs[i] ||
7782 User->getOperand(1) == Inputs[i])
7788 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7789 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7790 UE = PromOps[i].getNode()->use_end();
7793 if (User != N && !Visited.count(User))
7796 // Make sure that we're not going to promote the non-output-value
7797 // operand(s) or SELECT or SELECT_CC.
7798 // FIXME: Although we could sometimes handle this, and it does occur in
7799 // practice that one of the condition inputs to the select is also one of
7800 // the outputs, we currently can't deal with this.
7801 if (User->getOpcode() == ISD::SELECT) {
7802 if (User->getOperand(0) == PromOps[i])
7804 } else if (User->getOpcode() == ISD::SELECT_CC) {
7805 if (User->getOperand(0) == PromOps[i] ||
7806 User->getOperand(1) == PromOps[i])
7812 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
7813 bool ReallyNeedsExt = false;
7814 if (N->getOpcode() != ISD::ANY_EXTEND) {
7815 // If all of the inputs are not already sign/zero extended, then
7816 // we'll still need to do that at the end.
7817 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7818 if (isa<ConstantSDNode>(Inputs[i]))
7822 Inputs[i].getOperand(0).getValueSizeInBits();
7823 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
7825 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
7826 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
7827 APInt::getHighBitsSet(OpBits,
7828 OpBits-PromBits))) ||
7829 (N->getOpcode() == ISD::SIGN_EXTEND &&
7830 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
7831 (OpBits-(PromBits-1)))) {
7832 ReallyNeedsExt = true;
7838 // Replace all inputs, either with the truncation operand, or a
7839 // truncation or extension to the final output type.
7840 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7841 // Constant inputs need to be replaced with the to-be-promoted nodes that
7842 // use them because they might have users outside of the cluster of
7844 if (isa<ConstantSDNode>(Inputs[i]))
7847 SDValue InSrc = Inputs[i].getOperand(0);
7848 if (Inputs[i].getValueType() == N->getValueType(0))
7849 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
7850 else if (N->getOpcode() == ISD::SIGN_EXTEND)
7851 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7852 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
7853 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7854 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7855 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
7857 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7858 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
7861 // Replace all operations (these are all the same, but have a different
7862 // (promoted) return type). DAG.getNode will validate that the types of
7863 // a binary operator match, so go through the list in reverse so that
7864 // we've likely promoted both operands first.
7865 while (!PromOps.empty()) {
7866 SDValue PromOp = PromOps.back();
7870 switch (PromOp.getOpcode()) {
7871 default: C = 0; break;
7872 case ISD::SELECT: C = 1; break;
7873 case ISD::SELECT_CC: C = 2; break;
7876 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7877 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
7878 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7879 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
7880 // The to-be-promoted operands of this node have not yet been
7881 // promoted (this should be rare because we're going through the
7882 // list backward, but if one of the operands has several users in
7883 // this cluster of to-be-promoted nodes, it is possible).
7884 PromOps.insert(PromOps.begin(), PromOp);
7888 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7889 PromOp.getNode()->op_end());
7891 // If this node has constant inputs, then they'll need to be promoted here.
7892 for (unsigned i = 0; i < 2; ++i) {
7893 if (!isa<ConstantSDNode>(Ops[C+i]))
7895 if (Ops[C+i].getValueType() == N->getValueType(0))
7898 if (N->getOpcode() == ISD::SIGN_EXTEND)
7899 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7900 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7901 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7903 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7906 DAG.ReplaceAllUsesOfValueWith(PromOp,
7907 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
7910 // Now we're left with the initial extension itself.
7911 if (!ReallyNeedsExt)
7912 return N->getOperand(0);
7914 // To zero extend, just mask off everything except for the first bit (in the
7916 if (N->getOpcode() == ISD::ZERO_EXTEND)
7917 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
7918 DAG.getConstant(APInt::getLowBitsSet(
7919 N->getValueSizeInBits(0), PromBits),
7920 N->getValueType(0)));
7922 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
7923 "Invalid extension type");
7924 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
7926 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
7927 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
7928 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
7929 N->getOperand(0), ShiftCst), ShiftCst);
7932 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
7933 DAGCombinerInfo &DCI) const {
7934 const TargetMachine &TM = getTargetMachine();
7935 SelectionDAG &DAG = DCI.DAG;
7937 switch (N->getOpcode()) {
7940 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7941 if (C->isNullValue()) // 0 << V -> 0.
7942 return N->getOperand(0);
7946 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7947 if (C->isNullValue()) // 0 >>u V -> 0.
7948 return N->getOperand(0);
7952 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7953 if (C->isNullValue() || // 0 >>s V -> 0.
7954 C->isAllOnesValue()) // -1 >>s V -> -1.
7955 return N->getOperand(0);
7958 case ISD::SIGN_EXTEND:
7959 case ISD::ZERO_EXTEND:
7960 case ISD::ANY_EXTEND:
7961 return DAGCombineExtBoolTrunc(N, DCI);
7964 case ISD::SELECT_CC:
7965 return DAGCombineTruncBoolExt(N, DCI);
7967 assert(TM.Options.UnsafeFPMath &&
7968 "Reciprocal estimates require UnsafeFPMath");
7970 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
7972 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
7974 DCI.AddToWorklist(RV.getNode());
7975 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7976 N->getOperand(0), RV);
7978 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
7979 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7981 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7984 DCI.AddToWorklist(RV.getNode());
7985 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
7986 N->getValueType(0), RV);
7987 DCI.AddToWorklist(RV.getNode());
7988 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7989 N->getOperand(0), RV);
7991 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
7992 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7994 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7997 DCI.AddToWorklist(RV.getNode());
7998 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
7999 N->getValueType(0), RV,
8000 N->getOperand(1).getOperand(1));
8001 DCI.AddToWorklist(RV.getNode());
8002 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8003 N->getOperand(0), RV);
8007 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
8009 DCI.AddToWorklist(RV.getNode());
8010 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8011 N->getOperand(0), RV);
8017 assert(TM.Options.UnsafeFPMath &&
8018 "Reciprocal estimates require UnsafeFPMath");
8020 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
8022 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
8024 DCI.AddToWorklist(RV.getNode());
8025 RV = DAGCombineFastRecip(RV, DCI);
8027 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
8028 // this case and force the answer to 0.
8030 EVT VT = RV.getValueType();
8032 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
8033 if (VT.isVector()) {
8034 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
8035 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
8039 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
8040 N->getOperand(0), Zero, ISD::SETEQ);
8041 DCI.AddToWorklist(ZeroCmp.getNode());
8042 DCI.AddToWorklist(RV.getNode());
8044 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
8052 case ISD::SINT_TO_FP:
8053 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
8054 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8055 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8056 // We allow the src/dst to be either f32/f64, but the intermediate
8057 // type must be i64.
8058 if (N->getOperand(0).getValueType() == MVT::i64 &&
8059 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
8060 SDValue Val = N->getOperand(0).getOperand(0);
8061 if (Val.getValueType() == MVT::f32) {
8062 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8063 DCI.AddToWorklist(Val.getNode());
8066 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8067 DCI.AddToWorklist(Val.getNode());
8068 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8069 DCI.AddToWorklist(Val.getNode());
8070 if (N->getValueType(0) == MVT::f32) {
8071 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8072 DAG.getIntPtrConstant(0));
8073 DCI.AddToWorklist(Val.getNode());
8076 } else if (N->getOperand(0).getValueType() == MVT::i32) {
8077 // If the intermediate type is i32, we can avoid the load/store here
8084 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8085 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8086 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8087 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8088 N->getOperand(1).getValueType() == MVT::i32 &&
8089 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8090 SDValue Val = N->getOperand(1).getOperand(0);
8091 if (Val.getValueType() == MVT::f32) {
8092 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8093 DCI.AddToWorklist(Val.getNode());
8095 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8096 DCI.AddToWorklist(Val.getNode());
8099 N->getOperand(0), Val, N->getOperand(2),
8100 DAG.getValueType(N->getOperand(1).getValueType())
8103 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8104 DAG.getVTList(MVT::Other), Ops,
8105 cast<StoreSDNode>(N)->getMemoryVT(),
8106 cast<StoreSDNode>(N)->getMemOperand());
8107 DCI.AddToWorklist(Val.getNode());
8111 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8112 if (cast<StoreSDNode>(N)->isUnindexed() &&
8113 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8114 N->getOperand(1).getNode()->hasOneUse() &&
8115 (N->getOperand(1).getValueType() == MVT::i32 ||
8116 N->getOperand(1).getValueType() == MVT::i16 ||
8117 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8118 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8119 N->getOperand(1).getValueType() == MVT::i64))) {
8120 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8121 // Do an any-extend to 32-bits if this is a half-word input.
8122 if (BSwapOp.getValueType() == MVT::i16)
8123 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8126 N->getOperand(0), BSwapOp, N->getOperand(2),
8127 DAG.getValueType(N->getOperand(1).getValueType())
8130 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8131 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8132 cast<StoreSDNode>(N)->getMemOperand());
8136 LoadSDNode *LD = cast<LoadSDNode>(N);
8137 EVT VT = LD->getValueType(0);
8138 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8139 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8140 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8141 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8142 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8143 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8144 LD->getAlignment() < ABIAlignment) {
8145 // This is a type-legal unaligned Altivec load.
8146 SDValue Chain = LD->getChain();
8147 SDValue Ptr = LD->getBasePtr();
8148 bool isLittleEndian = Subtarget.isLittleEndian();
8150 // This implements the loading of unaligned vectors as described in
8151 // the venerable Apple Velocity Engine overview. Specifically:
8152 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8153 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8155 // The general idea is to expand a sequence of one or more unaligned
8156 // loads into an alignment-based permutation-control instruction (lvsl
8157 // or lvsr), a series of regular vector loads (which always truncate
8158 // their input address to an aligned address), and a series of
8159 // permutations. The results of these permutations are the requested
8160 // loaded values. The trick is that the last "extra" load is not taken
8161 // from the address you might suspect (sizeof(vector) bytes after the
8162 // last requested load), but rather sizeof(vector) - 1 bytes after the
8163 // last requested vector. The point of this is to avoid a page fault if
8164 // the base address happened to be aligned. This works because if the
8165 // base address is aligned, then adding less than a full vector length
8166 // will cause the last vector in the sequence to be (re)loaded.
8167 // Otherwise, the next vector will be fetched as you might suspect was
8170 // We might be able to reuse the permutation generation from
8171 // a different base address offset from this one by an aligned amount.
8172 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8173 // optimization later.
8174 Intrinsic::ID Intr = (isLittleEndian ?
8175 Intrinsic::ppc_altivec_lvsr :
8176 Intrinsic::ppc_altivec_lvsl);
8177 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8179 // Refine the alignment of the original load (a "new" load created here
8180 // which was identical to the first except for the alignment would be
8181 // merged with the existing node regardless).
8182 MachineFunction &MF = DAG.getMachineFunction();
8183 MachineMemOperand *MMO =
8184 MF.getMachineMemOperand(LD->getPointerInfo(),
8185 LD->getMemOperand()->getFlags(),
8186 LD->getMemoryVT().getStoreSize(),
8188 LD->refineAlignment(MMO);
8189 SDValue BaseLoad = SDValue(LD, 0);
8191 // Note that the value of IncOffset (which is provided to the next
8192 // load's pointer info offset value, and thus used to calculate the
8193 // alignment), and the value of IncValue (which is actually used to
8194 // increment the pointer value) are different! This is because we
8195 // require the next load to appear to be aligned, even though it
8196 // is actually offset from the base pointer by a lesser amount.
8197 int IncOffset = VT.getSizeInBits() / 8;
8198 int IncValue = IncOffset;
8200 // Walk (both up and down) the chain looking for another load at the real
8201 // (aligned) offset (the alignment of the other load does not matter in
8202 // this case). If found, then do not use the offset reduction trick, as
8203 // that will prevent the loads from being later combined (as they would
8204 // otherwise be duplicates).
8205 if (!findConsecutiveLoad(LD, DAG))
8208 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8209 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8212 DAG.getLoad(VT, dl, Chain, Ptr,
8213 LD->getPointerInfo().getWithOffset(IncOffset),
8214 LD->isVolatile(), LD->isNonTemporal(),
8215 LD->isInvariant(), ABIAlignment);
8217 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8218 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8220 if (BaseLoad.getValueType() != MVT::v4i32)
8221 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
8223 if (ExtraLoad.getValueType() != MVT::v4i32)
8224 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
8226 // Because vperm has a big-endian bias, we must reverse the order
8227 // of the input vectors and complement the permute control vector
8228 // when generating little endian code. We have already handled the
8229 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8230 // and ExtraLoad here.
8233 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8234 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8236 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8237 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8239 if (VT != MVT::v4i32)
8240 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8242 // Now we need to be really careful about how we update the users of the
8243 // original load. We cannot just call DCI.CombineTo (or
8244 // DAG.ReplaceAllUsesWith for that matter), because the load still has
8245 // uses created here (the permutation for example) that need to stay.
8246 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
8248 SDUse &Use = UI.getUse();
8250 // Note: BaseLoad is checked here because it might not be N, but a
8252 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
8253 User == TF.getNode() || Use.getResNo() > 1) {
8258 SDValue To = Use.getResNo() ? TF : Perm;
8261 SmallVector<SDValue, 8> Ops;
8262 for (SDNode::op_iterator O = User->op_begin(),
8263 OE = User->op_end(); O != OE; ++O) {
8270 DAG.UpdateNodeOperands(User, Ops);
8273 return SDValue(N, 0);
8277 case ISD::INTRINSIC_WO_CHAIN: {
8278 bool isLittleEndian = Subtarget.isLittleEndian();
8279 Intrinsic::ID Intr = (isLittleEndian ?
8280 Intrinsic::ppc_altivec_lvsr :
8281 Intrinsic::ppc_altivec_lvsl);
8282 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8283 N->getOperand(1)->getOpcode() == ISD::ADD) {
8284 SDValue Add = N->getOperand(1);
8286 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8287 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8288 Add.getValueType().getScalarType().getSizeInBits()))) {
8289 SDNode *BasePtr = Add->getOperand(0).getNode();
8290 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8291 UE = BasePtr->use_end(); UI != UE; ++UI) {
8292 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8293 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8295 // We've found another LVSL/LVSR, and this address is an aligned
8296 // multiple of that one. The results will be the same, so use the
8297 // one we've just found instead.
8299 return SDValue(*UI, 0);
8308 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8309 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8310 N->getOperand(0).hasOneUse() &&
8311 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8312 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8313 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8314 N->getValueType(0) == MVT::i64))) {
8315 SDValue Load = N->getOperand(0);
8316 LoadSDNode *LD = cast<LoadSDNode>(Load);
8317 // Create the byte-swapping load.
8319 LD->getChain(), // Chain
8320 LD->getBasePtr(), // Ptr
8321 DAG.getValueType(N->getValueType(0)) // VT
8324 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8325 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8326 MVT::i64 : MVT::i32, MVT::Other),
8327 Ops, LD->getMemoryVT(), LD->getMemOperand());
8329 // If this is an i16 load, insert the truncate.
8330 SDValue ResVal = BSLoad;
8331 if (N->getValueType(0) == MVT::i16)
8332 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8334 // First, combine the bswap away. This makes the value produced by the
8336 DCI.CombineTo(N, ResVal);
8338 // Next, combine the load away, we give it a bogus result value but a real
8339 // chain result. The result value is dead because the bswap is dead.
8340 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8342 // Return N so it doesn't get rechecked!
8343 return SDValue(N, 0);
8347 case PPCISD::VCMP: {
8348 // If a VCMPo node already exists with exactly the same operands as this
8349 // node, use its result instead of this node (VCMPo computes both a CR6 and
8350 // a normal output).
8352 if (!N->getOperand(0).hasOneUse() &&
8353 !N->getOperand(1).hasOneUse() &&
8354 !N->getOperand(2).hasOneUse()) {
8356 // Scan all of the users of the LHS, looking for VCMPo's that match.
8357 SDNode *VCMPoNode = nullptr;
8359 SDNode *LHSN = N->getOperand(0).getNode();
8360 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8362 if (UI->getOpcode() == PPCISD::VCMPo &&
8363 UI->getOperand(1) == N->getOperand(1) &&
8364 UI->getOperand(2) == N->getOperand(2) &&
8365 UI->getOperand(0) == N->getOperand(0)) {
8370 // If there is no VCMPo node, or if the flag value has a single use, don't
8372 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8375 // Look at the (necessarily single) use of the flag value. If it has a
8376 // chain, this transformation is more complex. Note that multiple things
8377 // could use the value result, which we should ignore.
8378 SDNode *FlagUser = nullptr;
8379 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8380 FlagUser == nullptr; ++UI) {
8381 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8383 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8384 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8391 // If the user is a MFOCRF instruction, we know this is safe.
8392 // Otherwise we give up for right now.
8393 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8394 return SDValue(VCMPoNode, 0);
8399 SDValue Cond = N->getOperand(1);
8400 SDValue Target = N->getOperand(2);
8402 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8403 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8404 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8406 // We now need to make the intrinsic dead (it cannot be instruction
8408 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8409 assert(Cond.getNode()->hasOneUse() &&
8410 "Counter decrement has more than one use");
8412 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8413 N->getOperand(0), Target);
8418 // If this is a branch on an altivec predicate comparison, lower this so
8419 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8420 // lowering is done pre-legalize, because the legalizer lowers the predicate
8421 // compare down to code that is difficult to reassemble.
8422 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8423 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8425 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8426 // value. If so, pass-through the AND to get to the intrinsic.
8427 if (LHS.getOpcode() == ISD::AND &&
8428 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8429 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8430 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8431 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8432 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8434 LHS = LHS.getOperand(0);
8436 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8437 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8438 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8439 isa<ConstantSDNode>(RHS)) {
8440 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8441 "Counter decrement comparison is not EQ or NE");
8443 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8444 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8445 (CC == ISD::SETNE && !Val);
8447 // We now need to make the intrinsic dead (it cannot be instruction
8449 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8450 assert(LHS.getNode()->hasOneUse() &&
8451 "Counter decrement has more than one use");
8453 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8454 N->getOperand(0), N->getOperand(4));
8460 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8461 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8462 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8463 assert(isDot && "Can't compare against a vector result!");
8465 // If this is a comparison against something other than 0/1, then we know
8466 // that the condition is never/always true.
8467 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8468 if (Val != 0 && Val != 1) {
8469 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8470 return N->getOperand(0);
8471 // Always !=, turn it into an unconditional branch.
8472 return DAG.getNode(ISD::BR, dl, MVT::Other,
8473 N->getOperand(0), N->getOperand(4));
8476 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8478 // Create the PPCISD altivec 'dot' comparison node.
8480 LHS.getOperand(2), // LHS of compare
8481 LHS.getOperand(3), // RHS of compare
8482 DAG.getConstant(CompareOpc, MVT::i32)
8484 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8485 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8487 // Unpack the result based on how the target uses it.
8488 PPC::Predicate CompOpc;
8489 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8490 default: // Can't happen, don't crash on invalid number though.
8491 case 0: // Branch on the value of the EQ bit of CR6.
8492 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8494 case 1: // Branch on the inverted value of the EQ bit of CR6.
8495 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8497 case 2: // Branch on the value of the LT bit of CR6.
8498 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8500 case 3: // Branch on the inverted value of the LT bit of CR6.
8501 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8505 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8506 DAG.getConstant(CompOpc, MVT::i32),
8507 DAG.getRegister(PPC::CR6, MVT::i32),
8508 N->getOperand(4), CompNode.getValue(1));
8517 //===----------------------------------------------------------------------===//
8518 // Inline Assembly Support
8519 //===----------------------------------------------------------------------===//
8521 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8524 const SelectionDAG &DAG,
8525 unsigned Depth) const {
8526 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8527 switch (Op.getOpcode()) {
8529 case PPCISD::LBRX: {
8530 // lhbrx is known to have the top bits cleared out.
8531 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8532 KnownZero = 0xFFFF0000;
8535 case ISD::INTRINSIC_WO_CHAIN: {
8536 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8538 case Intrinsic::ppc_altivec_vcmpbfp_p:
8539 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8540 case Intrinsic::ppc_altivec_vcmpequb_p:
8541 case Intrinsic::ppc_altivec_vcmpequh_p:
8542 case Intrinsic::ppc_altivec_vcmpequw_p:
8543 case Intrinsic::ppc_altivec_vcmpgefp_p:
8544 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8545 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8546 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8547 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8548 case Intrinsic::ppc_altivec_vcmpgtub_p:
8549 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8550 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8551 KnownZero = ~1U; // All bits but the low one are known to be zero.
8559 /// getConstraintType - Given a constraint, return the type of
8560 /// constraint it is for this target.
8561 PPCTargetLowering::ConstraintType
8562 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8563 if (Constraint.size() == 1) {
8564 switch (Constraint[0]) {
8571 return C_RegisterClass;
8573 // FIXME: While Z does indicate a memory constraint, it specifically
8574 // indicates an r+r address (used in conjunction with the 'y' modifier
8575 // in the replacement string). Currently, we're forcing the base
8576 // register to be r0 in the asm printer (which is interpreted as zero)
8577 // and forming the complete address in the second register. This is
8581 } else if (Constraint == "wc") { // individual CR bits.
8582 return C_RegisterClass;
8583 } else if (Constraint == "wa" || Constraint == "wd" ||
8584 Constraint == "wf" || Constraint == "ws") {
8585 return C_RegisterClass; // VSX registers.
8587 return TargetLowering::getConstraintType(Constraint);
8590 /// Examine constraint type and operand type and determine a weight value.
8591 /// This object must already have been set up with the operand type
8592 /// and the current alternative constraint selected.
8593 TargetLowering::ConstraintWeight
8594 PPCTargetLowering::getSingleConstraintMatchWeight(
8595 AsmOperandInfo &info, const char *constraint) const {
8596 ConstraintWeight weight = CW_Invalid;
8597 Value *CallOperandVal = info.CallOperandVal;
8598 // If we don't have a value, we can't do a match,
8599 // but allow it at the lowest weight.
8600 if (!CallOperandVal)
8602 Type *type = CallOperandVal->getType();
8604 // Look at the constraint type.
8605 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8606 return CW_Register; // an individual CR bit.
8607 else if ((StringRef(constraint) == "wa" ||
8608 StringRef(constraint) == "wd" ||
8609 StringRef(constraint) == "wf") &&
8612 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8615 switch (*constraint) {
8617 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8620 if (type->isIntegerTy())
8621 weight = CW_Register;
8624 if (type->isFloatTy())
8625 weight = CW_Register;
8628 if (type->isDoubleTy())
8629 weight = CW_Register;
8632 if (type->isVectorTy())
8633 weight = CW_Register;
8636 weight = CW_Register;
8645 std::pair<unsigned, const TargetRegisterClass*>
8646 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8648 if (Constraint.size() == 1) {
8649 // GCC RS6000 Constraint Letters
8650 switch (Constraint[0]) {
8652 if (VT == MVT::i64 && Subtarget.isPPC64())
8653 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8654 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8656 if (VT == MVT::i64 && Subtarget.isPPC64())
8657 return std::make_pair(0U, &PPC::G8RCRegClass);
8658 return std::make_pair(0U, &PPC::GPRCRegClass);
8660 if (VT == MVT::f32 || VT == MVT::i32)
8661 return std::make_pair(0U, &PPC::F4RCRegClass);
8662 if (VT == MVT::f64 || VT == MVT::i64)
8663 return std::make_pair(0U, &PPC::F8RCRegClass);
8666 return std::make_pair(0U, &PPC::VRRCRegClass);
8668 return std::make_pair(0U, &PPC::CRRCRegClass);
8670 } else if (Constraint == "wc") { // an individual CR bit.
8671 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8672 } else if (Constraint == "wa" || Constraint == "wd" ||
8673 Constraint == "wf") {
8674 return std::make_pair(0U, &PPC::VSRCRegClass);
8675 } else if (Constraint == "ws") {
8676 return std::make_pair(0U, &PPC::VSFRCRegClass);
8679 std::pair<unsigned, const TargetRegisterClass*> R =
8680 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8682 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8683 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8684 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8686 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8687 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8688 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
8689 PPC::GPRCRegClass.contains(R.first)) {
8690 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
8691 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8692 PPC::sub_32, &PPC::G8RCRegClass),
8693 &PPC::G8RCRegClass);
8700 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8701 /// vector. If it is invalid, don't add anything to Ops.
8702 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8703 std::string &Constraint,
8704 std::vector<SDValue>&Ops,
8705 SelectionDAG &DAG) const {
8708 // Only support length 1 constraints.
8709 if (Constraint.length() > 1) return;
8711 char Letter = Constraint[0];
8722 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
8723 if (!CST) return; // Must be an immediate to match.
8724 unsigned Value = CST->getZExtValue();
8726 default: llvm_unreachable("Unknown constraint letter!");
8727 case 'I': // "I" is a signed 16-bit constant.
8728 if ((short)Value == (int)Value)
8729 Result = DAG.getTargetConstant(Value, Op.getValueType());
8731 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
8732 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
8733 if ((short)Value == 0)
8734 Result = DAG.getTargetConstant(Value, Op.getValueType());
8736 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
8737 if ((Value >> 16) == 0)
8738 Result = DAG.getTargetConstant(Value, Op.getValueType());
8740 case 'M': // "M" is a constant that is greater than 31.
8742 Result = DAG.getTargetConstant(Value, Op.getValueType());
8744 case 'N': // "N" is a positive constant that is an exact power of two.
8745 if ((int)Value > 0 && isPowerOf2_32(Value))
8746 Result = DAG.getTargetConstant(Value, Op.getValueType());
8748 case 'O': // "O" is the constant zero.
8750 Result = DAG.getTargetConstant(Value, Op.getValueType());
8752 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
8753 if ((short)-Value == (int)-Value)
8754 Result = DAG.getTargetConstant(Value, Op.getValueType());
8761 if (Result.getNode()) {
8762 Ops.push_back(Result);
8766 // Handle standard constraint letters.
8767 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8770 // isLegalAddressingMode - Return true if the addressing mode represented
8771 // by AM is legal for this target, for a load/store of the specified type.
8772 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
8774 // FIXME: PPC does not allow r+i addressing modes for vectors!
8776 // PPC allows a sign-extended 16-bit immediate field.
8777 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
8780 // No global is ever allowed as a base.
8784 // PPC only support r+r,
8786 case 0: // "r+i" or just "i", depending on HasBaseReg.
8789 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
8791 // Otherwise we have r+r or r+i.
8794 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
8796 // Allow 2*r as r+r.
8799 // No other scales are supported.
8806 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
8807 SelectionDAG &DAG) const {
8808 MachineFunction &MF = DAG.getMachineFunction();
8809 MachineFrameInfo *MFI = MF.getFrameInfo();
8810 MFI->setReturnAddressIsTaken(true);
8812 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
8816 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8818 // Make sure the function does not optimize away the store of the RA to
8820 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
8821 FuncInfo->setLRStoreRequired();
8822 bool isPPC64 = Subtarget.isPPC64();
8823 bool isDarwinABI = Subtarget.isDarwinABI();
8826 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
8829 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
8830 isPPC64? MVT::i64 : MVT::i32);
8831 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8832 DAG.getNode(ISD::ADD, dl, getPointerTy(),
8834 MachinePointerInfo(), false, false, false, 0);
8837 // Just load the return address off the stack.
8838 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
8839 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8840 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
8843 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
8844 SelectionDAG &DAG) const {
8846 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8848 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
8849 bool isPPC64 = PtrVT == MVT::i64;
8851 MachineFunction &MF = DAG.getMachineFunction();
8852 MachineFrameInfo *MFI = MF.getFrameInfo();
8853 MFI->setFrameAddressIsTaken(true);
8855 // Naked functions never have a frame pointer, and so we use r1. For all
8856 // other functions, this decision must be delayed until during PEI.
8858 if (MF.getFunction()->getAttributes().hasAttribute(
8859 AttributeSet::FunctionIndex, Attribute::Naked))
8860 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
8862 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
8864 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
8867 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
8868 FrameAddr, MachinePointerInfo(), false, false,
8873 // FIXME? Maybe this could be a TableGen attribute on some registers and
8874 // this table could be generated automatically from RegInfo.
8875 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
8877 bool isPPC64 = Subtarget.isPPC64();
8878 bool isDarwinABI = Subtarget.isDarwinABI();
8880 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
8881 (!isPPC64 && VT != MVT::i32))
8882 report_fatal_error("Invalid register global variable type");
8884 bool is64Bit = isPPC64 && VT == MVT::i64;
8885 unsigned Reg = StringSwitch<unsigned>(RegName)
8886 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
8887 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
8888 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
8889 (is64Bit ? PPC::X13 : PPC::R13))
8894 report_fatal_error("Invalid register name global variable");
8898 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
8899 // The PowerPC target isn't yet aware of offsets.
8903 /// getOptimalMemOpType - Returns the target specific optimal type for load
8904 /// and store operations as a result of memset, memcpy, and memmove
8905 /// lowering. If DstAlign is zero that means it's safe to destination
8906 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
8907 /// means there isn't a need to check it against alignment requirement,
8908 /// probably because the source does not need to be loaded. If 'IsMemset' is
8909 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
8910 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
8911 /// source is constant so it does not need to be loaded.
8912 /// It returns EVT::Other if the type should be determined using generic
8913 /// target-independent logic.
8914 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
8915 unsigned DstAlign, unsigned SrcAlign,
8916 bool IsMemset, bool ZeroMemset,
8918 MachineFunction &MF) const {
8919 if (Subtarget.isPPC64()) {
8926 /// \brief Returns true if it is beneficial to convert a load of a constant
8927 /// to just the constant itself.
8928 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
8930 assert(Ty->isIntegerTy());
8932 unsigned BitSize = Ty->getPrimitiveSizeInBits();
8933 if (BitSize == 0 || BitSize > 64)
8938 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
8939 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
8941 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
8942 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
8943 return NumBits1 == 64 && NumBits2 == 32;
8946 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
8947 if (!VT1.isInteger() || !VT2.isInteger())
8949 unsigned NumBits1 = VT1.getSizeInBits();
8950 unsigned NumBits2 = VT2.getSizeInBits();
8951 return NumBits1 == 64 && NumBits2 == 32;
8954 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
8955 return isInt<16>(Imm) || isUInt<16>(Imm);
8958 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
8959 return isInt<16>(Imm) || isUInt<16>(Imm);
8962 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
8965 if (DisablePPCUnaligned)
8968 // PowerPC supports unaligned memory access for simple non-vector types.
8969 // Although accessing unaligned addresses is not as efficient as accessing
8970 // aligned addresses, it is generally more efficient than manual expansion,
8971 // and generally only traps for software emulation when crossing page
8977 if (VT.getSimpleVT().isVector()) {
8978 if (Subtarget.hasVSX()) {
8979 if (VT != MVT::v2f64 && VT != MVT::v2i64)
8986 if (VT == MVT::ppcf128)
8995 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
8996 VT = VT.getScalarType();
9001 switch (VT.getSimpleVT().SimpleTy) {
9013 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
9014 EVT VT , unsigned DefinedValues) const {
9015 if (VT == MVT::v2i64)
9018 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9021 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9022 if (DisableILPPref || Subtarget.enableMachineScheduler())
9023 return TargetLowering::getSchedulingPreference(N);
9028 // Create a fast isel object.
9030 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9031 const TargetLibraryInfo *LibInfo) const {
9032 return PPC::createFastISel(FuncInfo, LibInfo);