1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/Intrinsics.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetOptions.h"
39 static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
40 CCValAssign::LocInfo &LocInfo,
41 ISD::ArgFlagsTy &ArgFlags,
43 static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
45 CCValAssign::LocInfo &LocInfo,
46 ISD::ArgFlagsTy &ArgFlags,
48 static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
50 CCValAssign::LocInfo &LocInfo,
51 ISD::ArgFlagsTy &ArgFlags,
54 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
55 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
57 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
58 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
60 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
61 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
63 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
64 if (TM.getSubtargetImpl()->isDarwin())
65 return new TargetLoweringObjectFileMachO();
67 return new TargetLoweringObjectFileELF();
70 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
71 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
72 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
73 PPCRegInfo = TM.getRegisterInfo();
74 PPCII = TM.getInstrInfo();
78 // Use _setjmp/_longjmp instead of setjmp/longjmp.
79 setUseUnderscoreSetJmp(true);
80 setUseUnderscoreLongJmp(true);
82 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
83 // arguments are at least 4/8 bytes aligned.
84 bool isPPC64 = Subtarget->isPPC64();
85 setMinStackArgumentAlignment(isPPC64 ? 8:4);
87 // Set up the register classes.
88 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
89 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
90 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
92 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
93 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
94 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
96 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
98 // PowerPC has pre-inc load and store's.
99 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
100 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
101 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
102 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
103 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
104 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
105 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
106 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
107 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
108 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
110 // This is used in the ppcf128->int sequence. Note it has different semantics
111 // from FP_ROUND: that rounds to nearest, this rounds to zero.
112 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
114 // We do not currently implement these libm ops for PowerPC.
115 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
116 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
117 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
118 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
119 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
120 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
122 // PowerPC has no SREM/UREM instructions
123 setOperationAction(ISD::SREM, MVT::i32, Expand);
124 setOperationAction(ISD::UREM, MVT::i32, Expand);
125 setOperationAction(ISD::SREM, MVT::i64, Expand);
126 setOperationAction(ISD::UREM, MVT::i64, Expand);
128 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
129 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
130 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
131 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
132 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
133 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
134 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
135 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
136 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
138 // We don't support sin/cos/sqrt/fmod/pow
139 setOperationAction(ISD::FSIN , MVT::f64, Expand);
140 setOperationAction(ISD::FCOS , MVT::f64, Expand);
141 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
142 setOperationAction(ISD::FREM , MVT::f64, Expand);
143 setOperationAction(ISD::FPOW , MVT::f64, Expand);
144 setOperationAction(ISD::FMA , MVT::f64, Legal);
145 setOperationAction(ISD::FSIN , MVT::f32, Expand);
146 setOperationAction(ISD::FCOS , MVT::f32, Expand);
147 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
148 setOperationAction(ISD::FREM , MVT::f32, Expand);
149 setOperationAction(ISD::FPOW , MVT::f32, Expand);
150 setOperationAction(ISD::FMA , MVT::f32, Legal);
152 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
154 // If we're enabling GP optimizations, use hardware square root
155 if (!Subtarget->hasFSQRT() &&
156 !(TM.Options.UnsafeFPMath &&
157 Subtarget->hasFRSQRTE() && Subtarget->hasFRE()))
158 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
160 if (!Subtarget->hasFSQRT() &&
161 !(TM.Options.UnsafeFPMath &&
162 Subtarget->hasFRSQRTES() && Subtarget->hasFRES()))
163 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
165 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
166 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
168 if (Subtarget->hasFPRND()) {
169 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
170 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
171 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
173 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
174 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
175 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
177 // frin does not implement "ties to even." Thus, this is safe only in
179 if (TM.Options.UnsafeFPMath) {
180 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
181 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
183 // These need to set FE_INEXACT, and use a custom inserter.
184 setOperationAction(ISD::FRINT, MVT::f64, Legal);
185 setOperationAction(ISD::FRINT, MVT::f32, Legal);
189 // PowerPC does not have BSWAP, CTPOP or CTTZ
190 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
191 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
192 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
193 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
194 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
195 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
196 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
197 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
199 if (Subtarget->hasPOPCNTD()) {
200 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
201 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
203 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
204 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
207 // PowerPC does not have ROTR
208 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
209 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
211 // PowerPC does not have Select
212 setOperationAction(ISD::SELECT, MVT::i32, Expand);
213 setOperationAction(ISD::SELECT, MVT::i64, Expand);
214 setOperationAction(ISD::SELECT, MVT::f32, Expand);
215 setOperationAction(ISD::SELECT, MVT::f64, Expand);
217 // PowerPC wants to turn select_cc of FP into fsel when possible.
218 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
219 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
221 // PowerPC wants to optimize integer setcc a bit
222 setOperationAction(ISD::SETCC, MVT::i32, Custom);
224 // PowerPC does not have BRCOND which requires SetCC
225 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
227 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
229 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
230 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
232 // PowerPC does not have [U|S]INT_TO_FP
233 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
234 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
236 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
237 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
238 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
239 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
241 // We cannot sextinreg(i1). Expand to shifts.
242 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
244 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
245 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
246 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
247 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
249 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
250 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
251 // support continuation, user-level threading, and etc.. As a result, no
252 // other SjLj exception interfaces are implemented and please don't build
253 // your own exception handling based on them.
254 // LLVM/Clang supports zero-cost DWARF exception handling.
255 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
256 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
258 // We want to legalize GlobalAddress and ConstantPool nodes into the
259 // appropriate instructions to materialize the address.
260 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
261 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
262 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
263 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
264 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
265 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
266 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
267 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
268 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
269 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
272 setOperationAction(ISD::TRAP, MVT::Other, Legal);
274 // TRAMPOLINE is custom lowered.
275 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
276 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
278 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
279 setOperationAction(ISD::VASTART , MVT::Other, Custom);
281 if (Subtarget->isSVR4ABI()) {
283 // VAARG always uses double-word chunks, so promote anything smaller.
284 setOperationAction(ISD::VAARG, MVT::i1, Promote);
285 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
286 setOperationAction(ISD::VAARG, MVT::i8, Promote);
287 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
288 setOperationAction(ISD::VAARG, MVT::i16, Promote);
289 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
290 setOperationAction(ISD::VAARG, MVT::i32, Promote);
291 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
292 setOperationAction(ISD::VAARG, MVT::Other, Expand);
294 // VAARG is custom lowered with the 32-bit SVR4 ABI.
295 setOperationAction(ISD::VAARG, MVT::Other, Custom);
296 setOperationAction(ISD::VAARG, MVT::i64, Custom);
299 setOperationAction(ISD::VAARG, MVT::Other, Expand);
301 // Use the default implementation.
302 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
303 setOperationAction(ISD::VAEND , MVT::Other, Expand);
304 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
305 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
306 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
307 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
309 // We want to custom lower some of our intrinsics.
310 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
312 // Comparisons that require checking two conditions.
313 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
314 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
315 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
316 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
317 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
318 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
319 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
320 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
321 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
322 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
323 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
324 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
326 if (Subtarget->has64BitSupport()) {
327 // They also have instructions for converting between i64 and fp.
328 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
329 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
330 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
331 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
332 // This is just the low 32 bits of a (signed) fp->i64 conversion.
333 // We cannot do this with Promote because i64 is not a legal type.
334 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
336 if (PPCSubTarget.hasLFIWAX() || Subtarget->isPPC64())
337 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
339 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
340 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
343 // With the instructions enabled under FPCVT, we can do everything.
344 if (PPCSubTarget.hasFPCVT()) {
345 if (Subtarget->has64BitSupport()) {
346 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
347 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
348 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
349 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
352 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
353 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
354 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
355 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
358 if (Subtarget->use64BitRegs()) {
359 // 64-bit PowerPC implementations can support i64 types directly
360 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
361 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
362 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
363 // 64-bit PowerPC wants to expand i128 shifts itself.
364 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
365 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
366 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
368 // 32-bit PowerPC wants to expand i64 shifts itself.
369 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
370 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
371 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
374 if (Subtarget->hasAltivec()) {
375 // First set operation action for all vector types to expand. Then we
376 // will selectively turn on ones that can be effectively codegen'd.
377 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
378 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
379 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
381 // add/sub are legal for all supported vector VT's.
382 setOperationAction(ISD::ADD , VT, Legal);
383 setOperationAction(ISD::SUB , VT, Legal);
385 // We promote all shuffles to v16i8.
386 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
387 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
389 // We promote all non-typed operations to v4i32.
390 setOperationAction(ISD::AND , VT, Promote);
391 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
392 setOperationAction(ISD::OR , VT, Promote);
393 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
394 setOperationAction(ISD::XOR , VT, Promote);
395 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
396 setOperationAction(ISD::LOAD , VT, Promote);
397 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
398 setOperationAction(ISD::SELECT, VT, Promote);
399 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
400 setOperationAction(ISD::STORE, VT, Promote);
401 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
403 // No other operations are legal.
404 setOperationAction(ISD::MUL , VT, Expand);
405 setOperationAction(ISD::SDIV, VT, Expand);
406 setOperationAction(ISD::SREM, VT, Expand);
407 setOperationAction(ISD::UDIV, VT, Expand);
408 setOperationAction(ISD::UREM, VT, Expand);
409 setOperationAction(ISD::FDIV, VT, Expand);
410 setOperationAction(ISD::FNEG, VT, Expand);
411 setOperationAction(ISD::FSQRT, VT, Expand);
412 setOperationAction(ISD::FLOG, VT, Expand);
413 setOperationAction(ISD::FLOG10, VT, Expand);
414 setOperationAction(ISD::FLOG2, VT, Expand);
415 setOperationAction(ISD::FEXP, VT, Expand);
416 setOperationAction(ISD::FEXP2, VT, Expand);
417 setOperationAction(ISD::FSIN, VT, Expand);
418 setOperationAction(ISD::FCOS, VT, Expand);
419 setOperationAction(ISD::FABS, VT, Expand);
420 setOperationAction(ISD::FPOWI, VT, Expand);
421 setOperationAction(ISD::FFLOOR, VT, Expand);
422 setOperationAction(ISD::FCEIL, VT, Expand);
423 setOperationAction(ISD::FTRUNC, VT, Expand);
424 setOperationAction(ISD::FRINT, VT, Expand);
425 setOperationAction(ISD::FNEARBYINT, VT, Expand);
426 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
427 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
428 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
429 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
430 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
431 setOperationAction(ISD::UDIVREM, VT, Expand);
432 setOperationAction(ISD::SDIVREM, VT, Expand);
433 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
434 setOperationAction(ISD::FPOW, VT, Expand);
435 setOperationAction(ISD::CTPOP, VT, Expand);
436 setOperationAction(ISD::CTLZ, VT, Expand);
437 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
438 setOperationAction(ISD::CTTZ, VT, Expand);
439 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
440 setOperationAction(ISD::VSELECT, VT, Expand);
441 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
443 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
444 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
445 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
446 setTruncStoreAction(VT, InnerVT, Expand);
448 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
449 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
450 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
453 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
454 // with merges, splats, etc.
455 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
457 setOperationAction(ISD::AND , MVT::v4i32, Legal);
458 setOperationAction(ISD::OR , MVT::v4i32, Legal);
459 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
460 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
461 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
462 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
463 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
464 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
465 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
466 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
467 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
468 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
469 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
470 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
472 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
473 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
474 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
475 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
477 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
478 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
480 if (TM.Options.UnsafeFPMath) {
481 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
482 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
485 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
486 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
487 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
489 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
490 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
492 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
493 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
494 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
495 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
497 // Altivec does not contain unordered floating-point compare instructions
498 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
499 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
500 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
501 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
502 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
503 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
506 if (Subtarget->has64BitSupport()) {
507 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
508 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
511 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
512 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
513 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
514 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
516 setBooleanContents(ZeroOrOneBooleanContent);
517 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); // FIXME: Is this correct?
520 setStackPointerRegisterToSaveRestore(PPC::X1);
521 setExceptionPointerRegister(PPC::X3);
522 setExceptionSelectorRegister(PPC::X4);
524 setStackPointerRegisterToSaveRestore(PPC::R1);
525 setExceptionPointerRegister(PPC::R3);
526 setExceptionSelectorRegister(PPC::R4);
529 // We have target-specific dag combine patterns for the following nodes:
530 setTargetDAGCombine(ISD::SINT_TO_FP);
531 setTargetDAGCombine(ISD::STORE);
532 setTargetDAGCombine(ISD::BR_CC);
533 setTargetDAGCombine(ISD::BSWAP);
535 // Use reciprocal estimates.
536 if (TM.Options.UnsafeFPMath) {
537 setTargetDAGCombine(ISD::FDIV);
538 setTargetDAGCombine(ISD::FSQRT);
541 // Darwin long double math library functions have $LDBL128 appended.
542 if (Subtarget->isDarwin()) {
543 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
544 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
545 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
546 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
547 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
548 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
549 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
550 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
551 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
552 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
555 setMinFunctionAlignment(2);
556 if (PPCSubTarget.isDarwin())
557 setPrefFunctionAlignment(4);
559 if (isPPC64 && Subtarget->isJITCodeModel())
560 // Temporary workaround for the inability of PPC64 JIT to handle jump
562 setSupportJumpTables(false);
564 setInsertFencesForAtomic(true);
566 setSchedulingPreference(Sched::Hybrid);
568 computeRegisterProperties();
570 // The Freescale cores does better with aggressive inlining of memcpy and
571 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
572 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
573 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
574 MaxStoresPerMemset = 32;
575 MaxStoresPerMemsetOptSize = 16;
576 MaxStoresPerMemcpy = 32;
577 MaxStoresPerMemcpyOptSize = 8;
578 MaxStoresPerMemmove = 32;
579 MaxStoresPerMemmoveOptSize = 8;
581 setPrefFunctionAlignment(4);
585 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
586 /// function arguments in the caller parameter area.
587 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
588 const TargetMachine &TM = getTargetMachine();
589 // Darwin passes everything on 4 byte boundary.
590 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
593 // 16byte and wider vectors are passed on 16byte boundary.
594 if (VectorType *VTy = dyn_cast<VectorType>(Ty))
595 if (VTy->getBitWidth() >= 128)
598 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
599 if (PPCSubTarget.isPPC64())
605 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
608 case PPCISD::FSEL: return "PPCISD::FSEL";
609 case PPCISD::FCFID: return "PPCISD::FCFID";
610 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
611 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
612 case PPCISD::FRE: return "PPCISD::FRE";
613 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
614 case PPCISD::STFIWX: return "PPCISD::STFIWX";
615 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
616 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
617 case PPCISD::VPERM: return "PPCISD::VPERM";
618 case PPCISD::Hi: return "PPCISD::Hi";
619 case PPCISD::Lo: return "PPCISD::Lo";
620 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
621 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
622 case PPCISD::LOAD: return "PPCISD::LOAD";
623 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
624 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
625 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
626 case PPCISD::SRL: return "PPCISD::SRL";
627 case PPCISD::SRA: return "PPCISD::SRA";
628 case PPCISD::SHL: return "PPCISD::SHL";
629 case PPCISD::CALL: return "PPCISD::CALL";
630 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
631 case PPCISD::MTCTR: return "PPCISD::MTCTR";
632 case PPCISD::BCTRL: return "PPCISD::BCTRL";
633 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
634 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
635 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
636 case PPCISD::MFCR: return "PPCISD::MFCR";
637 case PPCISD::VCMP: return "PPCISD::VCMP";
638 case PPCISD::VCMPo: return "PPCISD::VCMPo";
639 case PPCISD::LBRX: return "PPCISD::LBRX";
640 case PPCISD::STBRX: return "PPCISD::STBRX";
641 case PPCISD::LARX: return "PPCISD::LARX";
642 case PPCISD::STCX: return "PPCISD::STCX";
643 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
644 case PPCISD::MFFS: return "PPCISD::MFFS";
645 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
646 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
647 case PPCISD::CR6SET: return "PPCISD::CR6SET";
648 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
649 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
650 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
651 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
652 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
653 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
654 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
655 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
656 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
657 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
658 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
659 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
660 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
661 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
662 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
663 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
667 EVT PPCTargetLowering::getSetCCResultType(EVT VT) const {
670 return VT.changeVectorElementTypeToInteger();
673 //===----------------------------------------------------------------------===//
674 // Node matching predicates, for use by the tblgen matching code.
675 //===----------------------------------------------------------------------===//
677 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
678 static bool isFloatingPointZero(SDValue Op) {
679 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
680 return CFP->getValueAPF().isZero();
681 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
682 // Maybe this has already been legalized into the constant pool?
683 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
684 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
685 return CFP->getValueAPF().isZero();
690 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
691 /// true if Op is undef or if it matches the specified value.
692 static bool isConstantOrUndef(int Op, int Val) {
693 return Op < 0 || Op == Val;
696 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
697 /// VPKUHUM instruction.
698 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
700 for (unsigned i = 0; i != 16; ++i)
701 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
704 for (unsigned i = 0; i != 8; ++i)
705 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
706 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
712 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
713 /// VPKUWUM instruction.
714 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
716 for (unsigned i = 0; i != 16; i += 2)
717 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
718 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
721 for (unsigned i = 0; i != 8; i += 2)
722 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
723 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
724 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
725 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
731 /// isVMerge - Common function, used to match vmrg* shuffles.
733 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
734 unsigned LHSStart, unsigned RHSStart) {
735 assert(N->getValueType(0) == MVT::v16i8 &&
736 "PPC only supports shuffles by bytes!");
737 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
738 "Unsupported merge size!");
740 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
741 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
742 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
743 LHSStart+j+i*UnitSize) ||
744 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
745 RHSStart+j+i*UnitSize))
751 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
752 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
753 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
756 return isVMerge(N, UnitSize, 8, 24);
757 return isVMerge(N, UnitSize, 8, 8);
760 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
761 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
762 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
765 return isVMerge(N, UnitSize, 0, 16);
766 return isVMerge(N, UnitSize, 0, 0);
770 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
771 /// amount, otherwise return -1.
772 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
773 assert(N->getValueType(0) == MVT::v16i8 &&
774 "PPC only supports shuffles by bytes!");
776 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
778 // Find the first non-undef value in the shuffle mask.
780 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
783 if (i == 16) return -1; // all undef.
785 // Otherwise, check to see if the rest of the elements are consecutively
786 // numbered from this value.
787 unsigned ShiftAmt = SVOp->getMaskElt(i);
788 if (ShiftAmt < i) return -1;
792 // Check the rest of the elements to see if they are consecutive.
793 for (++i; i != 16; ++i)
794 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
797 // Check the rest of the elements to see if they are consecutive.
798 for (++i; i != 16; ++i)
799 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
805 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
806 /// specifies a splat of a single element that is suitable for input to
807 /// VSPLTB/VSPLTH/VSPLTW.
808 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
809 assert(N->getValueType(0) == MVT::v16i8 &&
810 (EltSize == 1 || EltSize == 2 || EltSize == 4));
812 // This is a splat operation if each element of the permute is the same, and
813 // if the value doesn't reference the second vector.
814 unsigned ElementBase = N->getMaskElt(0);
816 // FIXME: Handle UNDEF elements too!
817 if (ElementBase >= 16)
820 // Check that the indices are consecutive, in the case of a multi-byte element
821 // splatted with a v16i8 mask.
822 for (unsigned i = 1; i != EltSize; ++i)
823 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
826 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
827 if (N->getMaskElt(i) < 0) continue;
828 for (unsigned j = 0; j != EltSize; ++j)
829 if (N->getMaskElt(i+j) != N->getMaskElt(j))
835 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
837 bool PPC::isAllNegativeZeroVector(SDNode *N) {
838 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
840 APInt APVal, APUndef;
844 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
845 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
846 return CFP->getValueAPF().isNegZero();
851 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
852 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
853 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
854 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
855 assert(isSplatShuffleMask(SVOp, EltSize));
856 return SVOp->getMaskElt(0) / EltSize;
859 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
860 /// by using a vspltis[bhw] instruction of the specified element size, return
861 /// the constant being splatted. The ByteSize field indicates the number of
862 /// bytes of each element [124] -> [bhw].
863 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
866 // If ByteSize of the splat is bigger than the element size of the
867 // build_vector, then we have a case where we are checking for a splat where
868 // multiple elements of the buildvector are folded together into a single
869 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
870 unsigned EltSize = 16/N->getNumOperands();
871 if (EltSize < ByteSize) {
872 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
873 SDValue UniquedVals[4];
874 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
876 // See if all of the elements in the buildvector agree across.
877 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
878 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
879 // If the element isn't a constant, bail fully out.
880 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
883 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
884 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
885 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
886 return SDValue(); // no match.
889 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
890 // either constant or undef values that are identical for each chunk. See
891 // if these chunks can form into a larger vspltis*.
893 // Check to see if all of the leading entries are either 0 or -1. If
894 // neither, then this won't fit into the immediate field.
895 bool LeadingZero = true;
896 bool LeadingOnes = true;
897 for (unsigned i = 0; i != Multiple-1; ++i) {
898 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
900 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
901 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
903 // Finally, check the least significant entry.
905 if (UniquedVals[Multiple-1].getNode() == 0)
906 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
907 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
909 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
912 if (UniquedVals[Multiple-1].getNode() == 0)
913 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
914 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
915 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
916 return DAG.getTargetConstant(Val, MVT::i32);
922 // Check to see if this buildvec has a single non-undef value in its elements.
923 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
924 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
925 if (OpVal.getNode() == 0)
926 OpVal = N->getOperand(i);
927 else if (OpVal != N->getOperand(i))
931 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
933 unsigned ValSizeInBytes = EltSize;
935 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
936 Value = CN->getZExtValue();
937 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
938 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
939 Value = FloatToBits(CN->getValueAPF().convertToFloat());
942 // If the splat value is larger than the element value, then we can never do
943 // this splat. The only case that we could fit the replicated bits into our
944 // immediate field for would be zero, and we prefer to use vxor for it.
945 if (ValSizeInBytes < ByteSize) return SDValue();
947 // If the element value is larger than the splat value, cut it in half and
948 // check to see if the two halves are equal. Continue doing this until we
949 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
950 while (ValSizeInBytes > ByteSize) {
951 ValSizeInBytes >>= 1;
953 // If the top half equals the bottom half, we're still ok.
954 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
955 (Value & ((1 << (8*ValSizeInBytes))-1)))
959 // Properly sign extend the value.
960 int MaskVal = SignExtend32(Value, ByteSize * 8);
962 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
963 if (MaskVal == 0) return SDValue();
965 // Finally, if this value fits in a 5 bit sext field, return it
966 if (SignExtend32<5>(MaskVal) == MaskVal)
967 return DAG.getTargetConstant(MaskVal, MVT::i32);
971 //===----------------------------------------------------------------------===//
972 // Addressing Mode Selection
973 //===----------------------------------------------------------------------===//
975 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
976 /// or 64-bit immediate, and if the value can be accurately represented as a
977 /// sign extension from a 16-bit value. If so, this returns true and the
979 static bool isIntS16Immediate(SDNode *N, short &Imm) {
980 if (N->getOpcode() != ISD::Constant)
983 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
984 if (N->getValueType(0) == MVT::i32)
985 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
987 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
989 static bool isIntS16Immediate(SDValue Op, short &Imm) {
990 return isIntS16Immediate(Op.getNode(), Imm);
994 /// SelectAddressRegReg - Given the specified addressed, check to see if it
995 /// can be represented as an indexed [r+r] operation. Returns false if it
996 /// can be more efficiently represented with [r+imm].
997 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
999 SelectionDAG &DAG) const {
1001 if (N.getOpcode() == ISD::ADD) {
1002 if (isIntS16Immediate(N.getOperand(1), imm))
1003 return false; // r+i
1004 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1005 return false; // r+i
1007 Base = N.getOperand(0);
1008 Index = N.getOperand(1);
1010 } else if (N.getOpcode() == ISD::OR) {
1011 if (isIntS16Immediate(N.getOperand(1), imm))
1012 return false; // r+i can fold it if we can.
1014 // If this is an or of disjoint bitfields, we can codegen this as an add
1015 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1017 APInt LHSKnownZero, LHSKnownOne;
1018 APInt RHSKnownZero, RHSKnownOne;
1019 DAG.ComputeMaskedBits(N.getOperand(0),
1020 LHSKnownZero, LHSKnownOne);
1022 if (LHSKnownZero.getBoolValue()) {
1023 DAG.ComputeMaskedBits(N.getOperand(1),
1024 RHSKnownZero, RHSKnownOne);
1025 // If all of the bits are known zero on the LHS or RHS, the add won't
1027 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1028 Base = N.getOperand(0);
1029 Index = N.getOperand(1);
1038 /// Returns true if the address N can be represented by a base register plus
1039 /// a signed 16-bit displacement [r+imm], and if it is not better
1040 /// represented as reg+reg.
1041 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1043 SelectionDAG &DAG) const {
1044 // FIXME dl should come from parent load or store, not from address
1045 DebugLoc dl = N.getDebugLoc();
1046 // If this can be more profitably realized as r+r, fail.
1047 if (SelectAddressRegReg(N, Disp, Base, DAG))
1050 if (N.getOpcode() == ISD::ADD) {
1052 if (isIntS16Immediate(N.getOperand(1), imm)) {
1053 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
1054 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1055 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1057 Base = N.getOperand(0);
1059 return true; // [r+i]
1060 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1061 // Match LOAD (ADD (X, Lo(G))).
1062 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1063 && "Cannot handle constant offsets yet!");
1064 Disp = N.getOperand(1).getOperand(0); // The global address.
1065 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1066 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1067 Disp.getOpcode() == ISD::TargetConstantPool ||
1068 Disp.getOpcode() == ISD::TargetJumpTable);
1069 Base = N.getOperand(0);
1070 return true; // [&g+r]
1072 } else if (N.getOpcode() == ISD::OR) {
1074 if (isIntS16Immediate(N.getOperand(1), imm)) {
1075 // If this is an or of disjoint bitfields, we can codegen this as an add
1076 // (for better address arithmetic) if the LHS and RHS of the OR are
1077 // provably disjoint.
1078 APInt LHSKnownZero, LHSKnownOne;
1079 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1081 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1082 // If all of the bits are known zero on the LHS or RHS, the add won't
1084 Base = N.getOperand(0);
1085 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
1089 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1090 // Loading from a constant address.
1092 // If this address fits entirely in a 16-bit sext immediate field, codegen
1095 if (isIntS16Immediate(CN, Imm)) {
1096 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1097 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1098 CN->getValueType(0));
1102 // Handle 32-bit sext immediates with LIS + addr mode.
1103 if (CN->getValueType(0) == MVT::i32 ||
1104 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1105 int Addr = (int)CN->getZExtValue();
1107 // Otherwise, break this down into an LIS + disp.
1108 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1110 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1111 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1112 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1117 Disp = DAG.getTargetConstant(0, getPointerTy());
1118 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1119 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1122 return true; // [r+0]
1125 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1126 /// represented as an indexed [r+r] operation.
1127 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1129 SelectionDAG &DAG) const {
1130 // Check to see if we can easily represent this as an [r+r] address. This
1131 // will fail if it thinks that the address is more profitably represented as
1132 // reg+imm, e.g. where imm = 0.
1133 if (SelectAddressRegReg(N, Base, Index, DAG))
1136 // If the operand is an addition, always emit this as [r+r], since this is
1137 // better (for code size, and execution, as the memop does the add for free)
1138 // than emitting an explicit add.
1139 if (N.getOpcode() == ISD::ADD) {
1140 Base = N.getOperand(0);
1141 Index = N.getOperand(1);
1145 // Otherwise, do it the hard way, using R0 as the base register.
1146 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1152 /// SelectAddressRegImmShift - Returns true if the address N can be
1153 /// represented by a base register plus a signed 14-bit displacement
1154 /// [r+imm*4]. Suitable for use by STD and friends.
1155 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
1157 SelectionDAG &DAG) const {
1158 // FIXME dl should come from the parent load or store, not the address
1159 DebugLoc dl = N.getDebugLoc();
1160 // If this can be more profitably realized as r+r, fail.
1161 if (SelectAddressRegReg(N, Disp, Base, DAG))
1164 if (N.getOpcode() == ISD::ADD) {
1166 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1167 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1168 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1169 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1171 Base = N.getOperand(0);
1173 return true; // [r+i]
1174 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1175 // Match LOAD (ADD (X, Lo(G))).
1176 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1177 && "Cannot handle constant offsets yet!");
1178 Disp = N.getOperand(1).getOperand(0); // The global address.
1179 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1180 Disp.getOpcode() == ISD::TargetConstantPool ||
1181 Disp.getOpcode() == ISD::TargetJumpTable);
1182 Base = N.getOperand(0);
1183 return true; // [&g+r]
1185 } else if (N.getOpcode() == ISD::OR) {
1187 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1188 // If this is an or of disjoint bitfields, we can codegen this as an add
1189 // (for better address arithmetic) if the LHS and RHS of the OR are
1190 // provably disjoint.
1191 APInt LHSKnownZero, LHSKnownOne;
1192 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1193 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1194 // If all of the bits are known zero on the LHS or RHS, the add won't
1196 Base = N.getOperand(0);
1197 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1201 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1202 // Loading from a constant address. Verify low two bits are clear.
1203 if ((CN->getZExtValue() & 3) == 0) {
1204 // If this address fits entirely in a 14-bit sext immediate field, codegen
1207 if (isIntS16Immediate(CN, Imm)) {
1208 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1209 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1210 CN->getValueType(0));
1214 // Fold the low-part of 32-bit absolute addresses into addr mode.
1215 if (CN->getValueType(0) == MVT::i32 ||
1216 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1217 int Addr = (int)CN->getZExtValue();
1219 // Otherwise, break this down into an LIS + disp.
1220 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1221 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1222 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1223 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1229 Disp = DAG.getTargetConstant(0, getPointerTy());
1230 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1231 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1234 return true; // [r+0]
1238 /// getPreIndexedAddressParts - returns true by value, base pointer and
1239 /// offset pointer and addressing mode by reference if the node's address
1240 /// can be legally represented as pre-indexed load / store address.
1241 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1243 ISD::MemIndexedMode &AM,
1244 SelectionDAG &DAG) const {
1245 if (DisablePPCPreinc) return false;
1251 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1252 Ptr = LD->getBasePtr();
1253 VT = LD->getMemoryVT();
1254 Alignment = LD->getAlignment();
1255 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1256 Ptr = ST->getBasePtr();
1257 VT = ST->getMemoryVT();
1258 Alignment = ST->getAlignment();
1263 // PowerPC doesn't have preinc load/store instructions for vectors.
1267 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1269 // Common code will reject creating a pre-inc form if the base pointer
1270 // is a frame index, or if N is a store and the base pointer is either
1271 // the same as or a predecessor of the value being stored. Check for
1272 // those situations here, and try with swapped Base/Offset instead.
1275 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1278 SDValue Val = cast<StoreSDNode>(N)->getValue();
1279 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1284 std::swap(Base, Offset);
1290 // LDU/STU use reg+imm*4, others use reg+imm.
1291 if (VT != MVT::i64) {
1293 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1296 // LDU/STU need an address with at least 4-byte alignment.
1301 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1305 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1306 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1307 // sext i32 to i64 when addr mode is r+i.
1308 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1309 LD->getExtensionType() == ISD::SEXTLOAD &&
1310 isa<ConstantSDNode>(Offset))
1318 //===----------------------------------------------------------------------===//
1319 // LowerOperation implementation
1320 //===----------------------------------------------------------------------===//
1322 /// GetLabelAccessInfo - Return true if we should reference labels using a
1323 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1324 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1325 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1326 HiOpFlags = PPCII::MO_HA16;
1327 LoOpFlags = PPCII::MO_LO16;
1329 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1330 // non-darwin platform. We don't support PIC on other platforms yet.
1331 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1332 TM.getSubtarget<PPCSubtarget>().isDarwin();
1334 HiOpFlags |= PPCII::MO_PIC_FLAG;
1335 LoOpFlags |= PPCII::MO_PIC_FLAG;
1338 // If this is a reference to a global value that requires a non-lazy-ptr, make
1339 // sure that instruction lowering adds it.
1340 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1341 HiOpFlags |= PPCII::MO_NLP_FLAG;
1342 LoOpFlags |= PPCII::MO_NLP_FLAG;
1344 if (GV->hasHiddenVisibility()) {
1345 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1346 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1353 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1354 SelectionDAG &DAG) {
1355 EVT PtrVT = HiPart.getValueType();
1356 SDValue Zero = DAG.getConstant(0, PtrVT);
1357 DebugLoc DL = HiPart.getDebugLoc();
1359 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1360 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1362 // With PIC, the first instruction is actually "GR+hi(&G)".
1364 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1365 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1367 // Generate non-pic code that has direct accesses to the constant pool.
1368 // The address of the global is just (hi(&g)+lo(&g)).
1369 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1372 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1373 SelectionDAG &DAG) const {
1374 EVT PtrVT = Op.getValueType();
1375 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1376 const Constant *C = CP->getConstVal();
1378 // 64-bit SVR4 ABI code is always position-independent.
1379 // The actual address of the GlobalValue is stored in the TOC.
1380 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1381 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1382 return DAG.getNode(PPCISD::TOC_ENTRY, CP->getDebugLoc(), MVT::i64, GA,
1383 DAG.getRegister(PPC::X2, MVT::i64));
1386 unsigned MOHiFlag, MOLoFlag;
1387 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1389 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1391 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1392 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1395 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1396 EVT PtrVT = Op.getValueType();
1397 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1399 // 64-bit SVR4 ABI code is always position-independent.
1400 // The actual address of the GlobalValue is stored in the TOC.
1401 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1402 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1403 return DAG.getNode(PPCISD::TOC_ENTRY, JT->getDebugLoc(), MVT::i64, GA,
1404 DAG.getRegister(PPC::X2, MVT::i64));
1407 unsigned MOHiFlag, MOLoFlag;
1408 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1409 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1410 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1411 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1414 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1415 SelectionDAG &DAG) const {
1416 EVT PtrVT = Op.getValueType();
1418 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1420 unsigned MOHiFlag, MOLoFlag;
1421 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1422 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1423 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1424 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1427 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1428 SelectionDAG &DAG) const {
1430 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1431 DebugLoc dl = GA->getDebugLoc();
1432 const GlobalValue *GV = GA->getGlobal();
1433 EVT PtrVT = getPointerTy();
1434 bool is64bit = PPCSubTarget.isPPC64();
1436 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1438 if (Model == TLSModel::LocalExec) {
1439 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1440 PPCII::MO_TPREL16_HA);
1441 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1442 PPCII::MO_TPREL16_LO);
1443 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1444 is64bit ? MVT::i64 : MVT::i32);
1445 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1446 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1450 llvm_unreachable("only local-exec is currently supported for ppc32");
1452 if (Model == TLSModel::InitialExec) {
1453 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1454 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1455 SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1456 PtrVT, GOTReg, TGA);
1457 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1458 PtrVT, TGA, TPOffsetHi);
1459 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGA);
1462 if (Model == TLSModel::GeneralDynamic) {
1463 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1464 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1465 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1467 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1470 // We need a chain node, and don't have one handy. The underlying
1471 // call has no side effects, so using the function entry node
1473 SDValue Chain = DAG.getEntryNode();
1474 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1475 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1476 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1477 PtrVT, ParmReg, TGA);
1478 // The return value from GET_TLS_ADDR really is in X3 already, but
1479 // some hacks are needed here to tie everything together. The extra
1480 // copies dissolve during subsequent transforms.
1481 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1482 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1485 if (Model == TLSModel::LocalDynamic) {
1486 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1487 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1488 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1490 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1493 // We need a chain node, and don't have one handy. The underlying
1494 // call has no side effects, so using the function entry node
1496 SDValue Chain = DAG.getEntryNode();
1497 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1498 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1499 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1500 PtrVT, ParmReg, TGA);
1501 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1502 // some hacks are needed here to tie everything together. The extra
1503 // copies dissolve during subsequent transforms.
1504 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1505 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1506 Chain, ParmReg, TGA);
1507 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1510 llvm_unreachable("Unknown TLS model!");
1513 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1514 SelectionDAG &DAG) const {
1515 EVT PtrVT = Op.getValueType();
1516 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1517 DebugLoc DL = GSDN->getDebugLoc();
1518 const GlobalValue *GV = GSDN->getGlobal();
1520 // 64-bit SVR4 ABI code is always position-independent.
1521 // The actual address of the GlobalValue is stored in the TOC.
1522 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1523 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1524 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1525 DAG.getRegister(PPC::X2, MVT::i64));
1528 unsigned MOHiFlag, MOLoFlag;
1529 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1532 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1534 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1536 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1538 // If the global reference is actually to a non-lazy-pointer, we have to do an
1539 // extra load to get the address of the global.
1540 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1541 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1542 false, false, false, 0);
1546 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1547 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1548 DebugLoc dl = Op.getDebugLoc();
1550 // If we're comparing for equality to zero, expose the fact that this is
1551 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1552 // fold the new nodes.
1553 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1554 if (C->isNullValue() && CC == ISD::SETEQ) {
1555 EVT VT = Op.getOperand(0).getValueType();
1556 SDValue Zext = Op.getOperand(0);
1557 if (VT.bitsLT(MVT::i32)) {
1559 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1561 unsigned Log2b = Log2_32(VT.getSizeInBits());
1562 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1563 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1564 DAG.getConstant(Log2b, MVT::i32));
1565 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1567 // Leave comparisons against 0 and -1 alone for now, since they're usually
1568 // optimized. FIXME: revisit this when we can custom lower all setcc
1570 if (C->isAllOnesValue() || C->isNullValue())
1574 // If we have an integer seteq/setne, turn it into a compare against zero
1575 // by xor'ing the rhs with the lhs, which is faster than setting a
1576 // condition register, reading it back out, and masking the correct bit. The
1577 // normal approach here uses sub to do this instead of xor. Using xor exposes
1578 // the result to other bit-twiddling opportunities.
1579 EVT LHSVT = Op.getOperand(0).getValueType();
1580 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1581 EVT VT = Op.getValueType();
1582 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1584 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1589 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1590 const PPCSubtarget &Subtarget) const {
1591 SDNode *Node = Op.getNode();
1592 EVT VT = Node->getValueType(0);
1593 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1594 SDValue InChain = Node->getOperand(0);
1595 SDValue VAListPtr = Node->getOperand(1);
1596 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1597 DebugLoc dl = Node->getDebugLoc();
1599 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1602 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1603 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1605 InChain = GprIndex.getValue(1);
1607 if (VT == MVT::i64) {
1608 // Check if GprIndex is even
1609 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1610 DAG.getConstant(1, MVT::i32));
1611 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1612 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1613 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1614 DAG.getConstant(1, MVT::i32));
1615 // Align GprIndex to be even if it isn't
1616 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1620 // fpr index is 1 byte after gpr
1621 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1622 DAG.getConstant(1, MVT::i32));
1625 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1626 FprPtr, MachinePointerInfo(SV), MVT::i8,
1628 InChain = FprIndex.getValue(1);
1630 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1631 DAG.getConstant(8, MVT::i32));
1633 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1634 DAG.getConstant(4, MVT::i32));
1637 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1638 MachinePointerInfo(), false, false,
1640 InChain = OverflowArea.getValue(1);
1642 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1643 MachinePointerInfo(), false, false,
1645 InChain = RegSaveArea.getValue(1);
1647 // select overflow_area if index > 8
1648 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1649 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1651 // adjustment constant gpr_index * 4/8
1652 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1653 VT.isInteger() ? GprIndex : FprIndex,
1654 DAG.getConstant(VT.isInteger() ? 4 : 8,
1657 // OurReg = RegSaveArea + RegConstant
1658 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1661 // Floating types are 32 bytes into RegSaveArea
1662 if (VT.isFloatingPoint())
1663 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1664 DAG.getConstant(32, MVT::i32));
1666 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1667 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1668 VT.isInteger() ? GprIndex : FprIndex,
1669 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1672 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1673 VT.isInteger() ? VAListPtr : FprPtr,
1674 MachinePointerInfo(SV),
1675 MVT::i8, false, false, 0);
1677 // determine if we should load from reg_save_area or overflow_area
1678 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1680 // increase overflow_area by 4/8 if gpr/fpr > 8
1681 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1682 DAG.getConstant(VT.isInteger() ? 4 : 8,
1685 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1688 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1690 MachinePointerInfo(),
1691 MVT::i32, false, false, 0);
1693 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1694 false, false, false, 0);
1697 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1698 SelectionDAG &DAG) const {
1699 return Op.getOperand(0);
1702 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1703 SelectionDAG &DAG) const {
1704 SDValue Chain = Op.getOperand(0);
1705 SDValue Trmp = Op.getOperand(1); // trampoline
1706 SDValue FPtr = Op.getOperand(2); // nested function
1707 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1708 DebugLoc dl = Op.getDebugLoc();
1710 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1711 bool isPPC64 = (PtrVT == MVT::i64);
1713 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1716 TargetLowering::ArgListTy Args;
1717 TargetLowering::ArgListEntry Entry;
1719 Entry.Ty = IntPtrTy;
1720 Entry.Node = Trmp; Args.push_back(Entry);
1722 // TrampSize == (isPPC64 ? 48 : 40);
1723 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1724 isPPC64 ? MVT::i64 : MVT::i32);
1725 Args.push_back(Entry);
1727 Entry.Node = FPtr; Args.push_back(Entry);
1728 Entry.Node = Nest; Args.push_back(Entry);
1730 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1731 TargetLowering::CallLoweringInfo CLI(Chain,
1732 Type::getVoidTy(*DAG.getContext()),
1733 false, false, false, false, 0,
1735 /*isTailCall=*/false,
1736 /*doesNotRet=*/false,
1737 /*isReturnValueUsed=*/true,
1738 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1740 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1742 return CallResult.second;
1745 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1746 const PPCSubtarget &Subtarget) const {
1747 MachineFunction &MF = DAG.getMachineFunction();
1748 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1750 DebugLoc dl = Op.getDebugLoc();
1752 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1753 // vastart just stores the address of the VarArgsFrameIndex slot into the
1754 // memory location argument.
1755 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1756 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1757 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1758 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1759 MachinePointerInfo(SV),
1763 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1764 // We suppose the given va_list is already allocated.
1767 // char gpr; /* index into the array of 8 GPRs
1768 // * stored in the register save area
1769 // * gpr=0 corresponds to r3,
1770 // * gpr=1 to r4, etc.
1772 // char fpr; /* index into the array of 8 FPRs
1773 // * stored in the register save area
1774 // * fpr=0 corresponds to f1,
1775 // * fpr=1 to f2, etc.
1777 // char *overflow_arg_area;
1778 // /* location on stack that holds
1779 // * the next overflow argument
1781 // char *reg_save_area;
1782 // /* where r3:r10 and f1:f8 (if saved)
1788 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1789 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1792 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1794 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1796 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1799 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1800 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1802 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1803 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1805 uint64_t FPROffset = 1;
1806 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1808 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1810 // Store first byte : number of int regs
1811 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1813 MachinePointerInfo(SV),
1814 MVT::i8, false, false, 0);
1815 uint64_t nextOffset = FPROffset;
1816 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1819 // Store second byte : number of float regs
1820 SDValue secondStore =
1821 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1822 MachinePointerInfo(SV, nextOffset), MVT::i8,
1824 nextOffset += StackOffset;
1825 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1827 // Store second word : arguments given on stack
1828 SDValue thirdStore =
1829 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1830 MachinePointerInfo(SV, nextOffset),
1832 nextOffset += FrameOffset;
1833 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1835 // Store third word : arguments given in registers
1836 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1837 MachinePointerInfo(SV, nextOffset),
1842 #include "PPCGenCallingConv.inc"
1844 static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1845 CCValAssign::LocInfo &LocInfo,
1846 ISD::ArgFlagsTy &ArgFlags,
1851 static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1853 CCValAssign::LocInfo &LocInfo,
1854 ISD::ArgFlagsTy &ArgFlags,
1856 static const uint16_t ArgRegs[] = {
1857 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1858 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1860 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1862 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1864 // Skip one register if the first unallocated register has an even register
1865 // number and there are still argument registers available which have not been
1866 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1867 // need to skip a register if RegNum is odd.
1868 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1869 State.AllocateReg(ArgRegs[RegNum]);
1872 // Always return false here, as this function only makes sure that the first
1873 // unallocated register has an odd register number and does not actually
1874 // allocate a register for the current argument.
1878 static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1880 CCValAssign::LocInfo &LocInfo,
1881 ISD::ArgFlagsTy &ArgFlags,
1883 static const uint16_t ArgRegs[] = {
1884 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1888 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1890 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1892 // If there is only one Floating-point register left we need to put both f64
1893 // values of a split ppc_fp128 value on the stack.
1894 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1895 State.AllocateReg(ArgRegs[RegNum]);
1898 // Always return false here, as this function only makes sure that the two f64
1899 // values a ppc_fp128 value is split into are both passed in registers or both
1900 // passed on the stack and does not actually allocate a register for the
1901 // current argument.
1905 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1907 static const uint16_t *GetFPR() {
1908 static const uint16_t FPR[] = {
1909 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1910 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1916 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1918 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1919 unsigned PtrByteSize) {
1920 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1921 if (Flags.isByVal())
1922 ArgSize = Flags.getByValSize();
1923 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1929 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1930 CallingConv::ID CallConv, bool isVarArg,
1931 const SmallVectorImpl<ISD::InputArg>
1933 DebugLoc dl, SelectionDAG &DAG,
1934 SmallVectorImpl<SDValue> &InVals)
1936 if (PPCSubTarget.isSVR4ABI()) {
1937 if (PPCSubTarget.isPPC64())
1938 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
1941 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
1944 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1950 PPCTargetLowering::LowerFormalArguments_32SVR4(
1952 CallingConv::ID CallConv, bool isVarArg,
1953 const SmallVectorImpl<ISD::InputArg>
1955 DebugLoc dl, SelectionDAG &DAG,
1956 SmallVectorImpl<SDValue> &InVals) const {
1958 // 32-bit SVR4 ABI Stack Frame Layout:
1959 // +-----------------------------------+
1960 // +--> | Back chain |
1961 // | +-----------------------------------+
1962 // | | Floating-point register save area |
1963 // | +-----------------------------------+
1964 // | | General register save area |
1965 // | +-----------------------------------+
1966 // | | CR save word |
1967 // | +-----------------------------------+
1968 // | | VRSAVE save word |
1969 // | +-----------------------------------+
1970 // | | Alignment padding |
1971 // | +-----------------------------------+
1972 // | | Vector register save area |
1973 // | +-----------------------------------+
1974 // | | Local variable space |
1975 // | +-----------------------------------+
1976 // | | Parameter list area |
1977 // | +-----------------------------------+
1978 // | | LR save word |
1979 // | +-----------------------------------+
1980 // SP--> +--- | Back chain |
1981 // +-----------------------------------+
1984 // System V Application Binary Interface PowerPC Processor Supplement
1985 // AltiVec Technology Programming Interface Manual
1987 MachineFunction &MF = DAG.getMachineFunction();
1988 MachineFrameInfo *MFI = MF.getFrameInfo();
1989 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1991 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1992 // Potential tail calls could cause overwriting of argument stack slots.
1993 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1994 (CallConv == CallingConv::Fast));
1995 unsigned PtrByteSize = 4;
1997 // Assign locations to all of the incoming arguments.
1998 SmallVector<CCValAssign, 16> ArgLocs;
1999 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2000 getTargetMachine(), ArgLocs, *DAG.getContext());
2002 // Reserve space for the linkage area on the stack.
2003 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2005 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2007 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2008 CCValAssign &VA = ArgLocs[i];
2010 // Arguments stored in registers.
2011 if (VA.isRegLoc()) {
2012 const TargetRegisterClass *RC;
2013 EVT ValVT = VA.getValVT();
2015 switch (ValVT.getSimpleVT().SimpleTy) {
2017 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2019 RC = &PPC::GPRCRegClass;
2022 RC = &PPC::F4RCRegClass;
2025 RC = &PPC::F8RCRegClass;
2031 RC = &PPC::VRRCRegClass;
2035 // Transform the arguments stored in physical registers into virtual ones.
2036 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2037 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
2039 InVals.push_back(ArgValue);
2041 // Argument stored in memory.
2042 assert(VA.isMemLoc());
2044 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
2045 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2048 // Create load nodes to retrieve arguments from the stack.
2049 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2050 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2051 MachinePointerInfo(),
2052 false, false, false, 0));
2056 // Assign locations to all of the incoming aggregate by value arguments.
2057 // Aggregates passed by value are stored in the local variable space of the
2058 // caller's stack frame, right above the parameter list area.
2059 SmallVector<CCValAssign, 16> ByValArgLocs;
2060 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2061 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2063 // Reserve stack space for the allocations in CCInfo.
2064 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2066 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2068 // Area that is at least reserved in the caller of this function.
2069 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2071 // Set the size that is at least reserved in caller of this function. Tail
2072 // call optimized function's reserved stack space needs to be aligned so that
2073 // taking the difference between two stack areas will result in an aligned
2075 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2078 std::max(MinReservedArea,
2079 PPCFrameLowering::getMinCallFrameSize(false, false));
2081 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2082 getStackAlignment();
2083 unsigned AlignMask = TargetAlign-1;
2084 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2086 FI->setMinReservedArea(MinReservedArea);
2088 SmallVector<SDValue, 8> MemOps;
2090 // If the function takes variable number of arguments, make a frame index for
2091 // the start of the first vararg value... for expansion of llvm.va_start.
2093 static const uint16_t GPArgRegs[] = {
2094 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2095 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2097 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2099 static const uint16_t FPArgRegs[] = {
2100 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2103 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2105 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2107 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2110 // Make room for NumGPArgRegs and NumFPArgRegs.
2111 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2112 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2114 FuncInfo->setVarArgsStackOffset(
2115 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2116 CCInfo.getNextStackOffset(), true));
2118 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2119 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2121 // The fixed integer arguments of a variadic function are stored to the
2122 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2123 // the result of va_next.
2124 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2125 // Get an existing live-in vreg, or add a new one.
2126 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2128 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2130 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2131 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2132 MachinePointerInfo(), false, false, 0);
2133 MemOps.push_back(Store);
2134 // Increment the address by four for the next argument to store
2135 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2136 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2139 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2141 // The double arguments are stored to the VarArgsFrameIndex
2143 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2144 // Get an existing live-in vreg, or add a new one.
2145 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2147 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2149 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2150 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2151 MachinePointerInfo(), false, false, 0);
2152 MemOps.push_back(Store);
2153 // Increment the address by eight for the next argument to store
2154 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2156 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2160 if (!MemOps.empty())
2161 Chain = DAG.getNode(ISD::TokenFactor, dl,
2162 MVT::Other, &MemOps[0], MemOps.size());
2167 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2168 // value to MVT::i64 and then truncate to the correct register size.
2170 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2171 SelectionDAG &DAG, SDValue ArgVal,
2172 DebugLoc dl) const {
2174 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2175 DAG.getValueType(ObjectVT));
2176 else if (Flags.isZExt())
2177 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2178 DAG.getValueType(ObjectVT));
2180 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2183 // Set the size that is at least reserved in caller of this function. Tail
2184 // call optimized functions' reserved stack space needs to be aligned so that
2185 // taking the difference between two stack areas will result in an aligned
2188 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2189 unsigned nAltivecParamsAtEnd,
2190 unsigned MinReservedArea,
2191 bool isPPC64) const {
2192 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2193 // Add the Altivec parameters at the end, if needed.
2194 if (nAltivecParamsAtEnd) {
2195 MinReservedArea = ((MinReservedArea+15)/16)*16;
2196 MinReservedArea += 16*nAltivecParamsAtEnd;
2199 std::max(MinReservedArea,
2200 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2201 unsigned TargetAlign
2202 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2203 getStackAlignment();
2204 unsigned AlignMask = TargetAlign-1;
2205 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2206 FI->setMinReservedArea(MinReservedArea);
2210 PPCTargetLowering::LowerFormalArguments_64SVR4(
2212 CallingConv::ID CallConv, bool isVarArg,
2213 const SmallVectorImpl<ISD::InputArg>
2215 DebugLoc dl, SelectionDAG &DAG,
2216 SmallVectorImpl<SDValue> &InVals) const {
2217 // TODO: add description of PPC stack frame format, or at least some docs.
2219 MachineFunction &MF = DAG.getMachineFunction();
2220 MachineFrameInfo *MFI = MF.getFrameInfo();
2221 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2223 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2224 // Potential tail calls could cause overwriting of argument stack slots.
2225 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2226 (CallConv == CallingConv::Fast));
2227 unsigned PtrByteSize = 8;
2229 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2230 // Area that is at least reserved in caller of this function.
2231 unsigned MinReservedArea = ArgOffset;
2233 static const uint16_t GPR[] = {
2234 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2235 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2238 static const uint16_t *FPR = GetFPR();
2240 static const uint16_t VR[] = {
2241 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2242 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2245 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2246 const unsigned Num_FPR_Regs = 13;
2247 const unsigned Num_VR_Regs = array_lengthof(VR);
2249 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2251 // Add DAG nodes to load the arguments or copy them out of registers. On
2252 // entry to a function on PPC, the arguments start after the linkage area,
2253 // although the first ones are often in registers.
2255 SmallVector<SDValue, 8> MemOps;
2256 unsigned nAltivecParamsAtEnd = 0;
2257 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2258 unsigned CurArgIdx = 0;
2259 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2261 bool needsLoad = false;
2262 EVT ObjectVT = Ins[ArgNo].VT;
2263 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2264 unsigned ArgSize = ObjSize;
2265 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2266 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2267 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2269 unsigned CurArgOffset = ArgOffset;
2271 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2272 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2273 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2275 MinReservedArea = ((MinReservedArea+15)/16)*16;
2276 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2280 nAltivecParamsAtEnd++;
2282 // Calculate min reserved area.
2283 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2287 // FIXME the codegen can be much improved in some cases.
2288 // We do not have to keep everything in memory.
2289 if (Flags.isByVal()) {
2290 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2291 ObjSize = Flags.getByValSize();
2292 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2293 // Empty aggregate parameters do not take up registers. Examples:
2297 // etc. However, we have to provide a place-holder in InVals, so
2298 // pretend we have an 8-byte item at the current address for that
2301 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2302 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2303 InVals.push_back(FIN);
2306 // All aggregates smaller than 8 bytes must be passed right-justified.
2307 if (ObjSize < PtrByteSize)
2308 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2309 // The value of the object is its address.
2310 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2311 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2312 InVals.push_back(FIN);
2315 if (GPR_idx != Num_GPR_Regs) {
2316 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2317 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2320 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2321 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2322 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2323 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2324 MachinePointerInfo(FuncArg, CurArgOffset),
2325 ObjType, false, false, 0);
2327 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2328 // store the whole register as-is to the parameter save area
2329 // slot. The address of the parameter was already calculated
2330 // above (InVals.push_back(FIN)) to be the right-justified
2331 // offset within the slot. For this store, we need a new
2332 // frame index that points at the beginning of the slot.
2333 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2334 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2335 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2336 MachinePointerInfo(FuncArg, ArgOffset),
2340 MemOps.push_back(Store);
2343 // Whether we copied from a register or not, advance the offset
2344 // into the parameter save area by a full doubleword.
2345 ArgOffset += PtrByteSize;
2349 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2350 // Store whatever pieces of the object are in registers
2351 // to memory. ArgOffset will be the address of the beginning
2353 if (GPR_idx != Num_GPR_Regs) {
2355 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2356 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2357 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2358 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2359 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2360 MachinePointerInfo(FuncArg, ArgOffset),
2362 MemOps.push_back(Store);
2364 ArgOffset += PtrByteSize;
2366 ArgOffset += ArgSize - j;
2373 switch (ObjectVT.getSimpleVT().SimpleTy) {
2374 default: llvm_unreachable("Unhandled argument type!");
2377 if (GPR_idx != Num_GPR_Regs) {
2378 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2379 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2381 if (ObjectVT == MVT::i32)
2382 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2383 // value to MVT::i64 and then truncate to the correct register size.
2384 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2389 ArgSize = PtrByteSize;
2396 // Every 8 bytes of argument space consumes one of the GPRs available for
2397 // argument passing.
2398 if (GPR_idx != Num_GPR_Regs) {
2401 if (FPR_idx != Num_FPR_Regs) {
2404 if (ObjectVT == MVT::f32)
2405 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2407 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2409 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2413 ArgSize = PtrByteSize;
2422 // Note that vector arguments in registers don't reserve stack space,
2423 // except in varargs functions.
2424 if (VR_idx != Num_VR_Regs) {
2425 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2426 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2428 while ((ArgOffset % 16) != 0) {
2429 ArgOffset += PtrByteSize;
2430 if (GPR_idx != Num_GPR_Regs)
2434 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2438 // Vectors are aligned.
2439 ArgOffset = ((ArgOffset+15)/16)*16;
2440 CurArgOffset = ArgOffset;
2447 // We need to load the argument to a virtual register if we determined
2448 // above that we ran out of physical registers of the appropriate type.
2450 int FI = MFI->CreateFixedObject(ObjSize,
2451 CurArgOffset + (ArgSize - ObjSize),
2453 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2454 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2455 false, false, false, 0);
2458 InVals.push_back(ArgVal);
2461 // Set the size that is at least reserved in caller of this function. Tail
2462 // call optimized functions' reserved stack space needs to be aligned so that
2463 // taking the difference between two stack areas will result in an aligned
2465 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2467 // If the function takes variable number of arguments, make a frame index for
2468 // the start of the first vararg value... for expansion of llvm.va_start.
2470 int Depth = ArgOffset;
2472 FuncInfo->setVarArgsFrameIndex(
2473 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2474 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2476 // If this function is vararg, store any remaining integer argument regs
2477 // to their spots on the stack so that they may be loaded by deferencing the
2478 // result of va_next.
2479 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2480 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2481 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2482 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2483 MachinePointerInfo(), false, false, 0);
2484 MemOps.push_back(Store);
2485 // Increment the address by four for the next argument to store
2486 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2487 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2491 if (!MemOps.empty())
2492 Chain = DAG.getNode(ISD::TokenFactor, dl,
2493 MVT::Other, &MemOps[0], MemOps.size());
2499 PPCTargetLowering::LowerFormalArguments_Darwin(
2501 CallingConv::ID CallConv, bool isVarArg,
2502 const SmallVectorImpl<ISD::InputArg>
2504 DebugLoc dl, SelectionDAG &DAG,
2505 SmallVectorImpl<SDValue> &InVals) const {
2506 // TODO: add description of PPC stack frame format, or at least some docs.
2508 MachineFunction &MF = DAG.getMachineFunction();
2509 MachineFrameInfo *MFI = MF.getFrameInfo();
2510 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2512 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2513 bool isPPC64 = PtrVT == MVT::i64;
2514 // Potential tail calls could cause overwriting of argument stack slots.
2515 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2516 (CallConv == CallingConv::Fast));
2517 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2519 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2520 // Area that is at least reserved in caller of this function.
2521 unsigned MinReservedArea = ArgOffset;
2523 static const uint16_t GPR_32[] = { // 32-bit registers.
2524 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2525 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2527 static const uint16_t GPR_64[] = { // 64-bit registers.
2528 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2529 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2532 static const uint16_t *FPR = GetFPR();
2534 static const uint16_t VR[] = {
2535 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2536 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2539 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2540 const unsigned Num_FPR_Regs = 13;
2541 const unsigned Num_VR_Regs = array_lengthof( VR);
2543 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2545 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2547 // In 32-bit non-varargs functions, the stack space for vectors is after the
2548 // stack space for non-vectors. We do not use this space unless we have
2549 // too many vectors to fit in registers, something that only occurs in
2550 // constructed examples:), but we have to walk the arglist to figure
2551 // that out...for the pathological case, compute VecArgOffset as the
2552 // start of the vector parameter area. Computing VecArgOffset is the
2553 // entire point of the following loop.
2554 unsigned VecArgOffset = ArgOffset;
2555 if (!isVarArg && !isPPC64) {
2556 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2558 EVT ObjectVT = Ins[ArgNo].VT;
2559 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2561 if (Flags.isByVal()) {
2562 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2563 unsigned ObjSize = Flags.getByValSize();
2565 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2566 VecArgOffset += ArgSize;
2570 switch(ObjectVT.getSimpleVT().SimpleTy) {
2571 default: llvm_unreachable("Unhandled argument type!");
2576 case MVT::i64: // PPC64
2578 // FIXME: We are guaranteed to be !isPPC64 at this point.
2579 // Does MVT::i64 apply?
2586 // Nothing to do, we're only looking at Nonvector args here.
2591 // We've found where the vector parameter area in memory is. Skip the
2592 // first 12 parameters; these don't use that memory.
2593 VecArgOffset = ((VecArgOffset+15)/16)*16;
2594 VecArgOffset += 12*16;
2596 // Add DAG nodes to load the arguments or copy them out of registers. On
2597 // entry to a function on PPC, the arguments start after the linkage area,
2598 // although the first ones are often in registers.
2600 SmallVector<SDValue, 8> MemOps;
2601 unsigned nAltivecParamsAtEnd = 0;
2602 // FIXME: FuncArg and Ins[ArgNo] must reference the same argument.
2603 // When passing anonymous aggregates, this is currently not true.
2604 // See LowerFormalArguments_64SVR4 for a fix.
2605 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2606 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo, ++FuncArg) {
2608 bool needsLoad = false;
2609 EVT ObjectVT = Ins[ArgNo].VT;
2610 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2611 unsigned ArgSize = ObjSize;
2612 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2614 unsigned CurArgOffset = ArgOffset;
2616 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2617 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2618 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2619 if (isVarArg || isPPC64) {
2620 MinReservedArea = ((MinReservedArea+15)/16)*16;
2621 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2624 } else nAltivecParamsAtEnd++;
2626 // Calculate min reserved area.
2627 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2631 // FIXME the codegen can be much improved in some cases.
2632 // We do not have to keep everything in memory.
2633 if (Flags.isByVal()) {
2634 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2635 ObjSize = Flags.getByValSize();
2636 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2637 // Objects of size 1 and 2 are right justified, everything else is
2638 // left justified. This means the memory address is adjusted forwards.
2639 if (ObjSize==1 || ObjSize==2) {
2640 CurArgOffset = CurArgOffset + (4 - ObjSize);
2642 // The value of the object is its address.
2643 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2644 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2645 InVals.push_back(FIN);
2646 if (ObjSize==1 || ObjSize==2) {
2647 if (GPR_idx != Num_GPR_Regs) {
2650 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2652 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2653 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2654 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2655 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2656 MachinePointerInfo(FuncArg,
2658 ObjType, false, false, 0);
2659 MemOps.push_back(Store);
2663 ArgOffset += PtrByteSize;
2667 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2668 // Store whatever pieces of the object are in registers
2669 // to memory. ArgOffset will be the address of the beginning
2671 if (GPR_idx != Num_GPR_Regs) {
2674 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2676 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2677 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2678 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2679 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2680 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2681 MachinePointerInfo(FuncArg, ArgOffset),
2683 MemOps.push_back(Store);
2685 ArgOffset += PtrByteSize;
2687 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2694 switch (ObjectVT.getSimpleVT().SimpleTy) {
2695 default: llvm_unreachable("Unhandled argument type!");
2698 if (GPR_idx != Num_GPR_Regs) {
2699 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2700 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2704 ArgSize = PtrByteSize;
2706 // All int arguments reserve stack space in the Darwin ABI.
2707 ArgOffset += PtrByteSize;
2711 case MVT::i64: // PPC64
2712 if (GPR_idx != Num_GPR_Regs) {
2713 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2714 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2716 if (ObjectVT == MVT::i32)
2717 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2718 // value to MVT::i64 and then truncate to the correct register size.
2719 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2724 ArgSize = PtrByteSize;
2726 // All int arguments reserve stack space in the Darwin ABI.
2732 // Every 4 bytes of argument space consumes one of the GPRs available for
2733 // argument passing.
2734 if (GPR_idx != Num_GPR_Regs) {
2736 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2739 if (FPR_idx != Num_FPR_Regs) {
2742 if (ObjectVT == MVT::f32)
2743 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2745 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2747 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2753 // All FP arguments reserve stack space in the Darwin ABI.
2754 ArgOffset += isPPC64 ? 8 : ObjSize;
2760 // Note that vector arguments in registers don't reserve stack space,
2761 // except in varargs functions.
2762 if (VR_idx != Num_VR_Regs) {
2763 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2764 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2766 while ((ArgOffset % 16) != 0) {
2767 ArgOffset += PtrByteSize;
2768 if (GPR_idx != Num_GPR_Regs)
2772 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2776 if (!isVarArg && !isPPC64) {
2777 // Vectors go after all the nonvectors.
2778 CurArgOffset = VecArgOffset;
2781 // Vectors are aligned.
2782 ArgOffset = ((ArgOffset+15)/16)*16;
2783 CurArgOffset = ArgOffset;
2791 // We need to load the argument to a virtual register if we determined above
2792 // that we ran out of physical registers of the appropriate type.
2794 int FI = MFI->CreateFixedObject(ObjSize,
2795 CurArgOffset + (ArgSize - ObjSize),
2797 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2798 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2799 false, false, false, 0);
2802 InVals.push_back(ArgVal);
2805 // Set the size that is at least reserved in caller of this function. Tail
2806 // call optimized functions' reserved stack space needs to be aligned so that
2807 // taking the difference between two stack areas will result in an aligned
2809 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
2811 // If the function takes variable number of arguments, make a frame index for
2812 // the start of the first vararg value... for expansion of llvm.va_start.
2814 int Depth = ArgOffset;
2816 FuncInfo->setVarArgsFrameIndex(
2817 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2819 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2821 // If this function is vararg, store any remaining integer argument regs
2822 // to their spots on the stack so that they may be loaded by deferencing the
2823 // result of va_next.
2824 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2828 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2830 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2832 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2833 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2834 MachinePointerInfo(), false, false, 0);
2835 MemOps.push_back(Store);
2836 // Increment the address by four for the next argument to store
2837 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2838 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2842 if (!MemOps.empty())
2843 Chain = DAG.getNode(ISD::TokenFactor, dl,
2844 MVT::Other, &MemOps[0], MemOps.size());
2849 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
2850 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
2852 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2856 const SmallVectorImpl<ISD::OutputArg>
2858 const SmallVectorImpl<SDValue> &OutVals,
2859 unsigned &nAltivecParamsAtEnd) {
2860 // Count how many bytes are to be pushed on the stack, including the linkage
2861 // area, and parameter passing area. We start with 24/48 bytes, which is
2862 // prereserved space for [SP][CR][LR][3 x unused].
2863 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2864 unsigned NumOps = Outs.size();
2865 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2867 // Add up all the space actually used.
2868 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2869 // they all go in registers, but we must reserve stack space for them for
2870 // possible use by the caller. In varargs or 64-bit calls, parameters are
2871 // assigned stack space in order, with padding so Altivec parameters are
2873 nAltivecParamsAtEnd = 0;
2874 for (unsigned i = 0; i != NumOps; ++i) {
2875 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2876 EVT ArgVT = Outs[i].VT;
2877 // Varargs Altivec parameters are padded to a 16 byte boundary.
2878 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2879 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2880 if (!isVarArg && !isPPC64) {
2881 // Non-varargs Altivec parameters go after all the non-Altivec
2882 // parameters; handle those later so we know how much padding we need.
2883 nAltivecParamsAtEnd++;
2886 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2887 NumBytes = ((NumBytes+15)/16)*16;
2889 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2892 // Allow for Altivec parameters at the end, if needed.
2893 if (nAltivecParamsAtEnd) {
2894 NumBytes = ((NumBytes+15)/16)*16;
2895 NumBytes += 16*nAltivecParamsAtEnd;
2898 // The prolog code of the callee may store up to 8 GPR argument registers to
2899 // the stack, allowing va_start to index over them in memory if its varargs.
2900 // Because we cannot tell if this is needed on the caller side, we have to
2901 // conservatively assume that it is needed. As such, make sure we have at
2902 // least enough stack space for the caller to store the 8 GPRs.
2903 NumBytes = std::max(NumBytes,
2904 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2906 // Tail call needs the stack to be aligned.
2907 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2908 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2909 getFrameLowering()->getStackAlignment();
2910 unsigned AlignMask = TargetAlign-1;
2911 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2917 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2918 /// adjusted to accommodate the arguments for the tailcall.
2919 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2920 unsigned ParamSize) {
2922 if (!isTailCall) return 0;
2924 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2925 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2926 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2927 // Remember only if the new adjustement is bigger.
2928 if (SPDiff < FI->getTailCallSPDelta())
2929 FI->setTailCallSPDelta(SPDiff);
2934 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2935 /// for tail call optimization. Targets which want to do tail call
2936 /// optimization should implement this function.
2938 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2939 CallingConv::ID CalleeCC,
2941 const SmallVectorImpl<ISD::InputArg> &Ins,
2942 SelectionDAG& DAG) const {
2943 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2946 // Variable argument functions are not supported.
2950 MachineFunction &MF = DAG.getMachineFunction();
2951 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2952 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2953 // Functions containing by val parameters are not supported.
2954 for (unsigned i = 0; i != Ins.size(); i++) {
2955 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2956 if (Flags.isByVal()) return false;
2959 // Non PIC/GOT tail calls are supported.
2960 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2963 // At the moment we can only do local tail calls (in same module, hidden
2964 // or protected) if we are generating PIC.
2965 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2966 return G->getGlobal()->hasHiddenVisibility()
2967 || G->getGlobal()->hasProtectedVisibility();
2973 /// isCallCompatibleAddress - Return the immediate to use if the specified
2974 /// 32-bit value is representable in the immediate field of a BxA instruction.
2975 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2976 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2979 int Addr = C->getZExtValue();
2980 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2981 SignExtend32<26>(Addr) != Addr)
2982 return 0; // Top 6 bits have to be sext of immediate.
2984 return DAG.getConstant((int)C->getZExtValue() >> 2,
2985 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2990 struct TailCallArgumentInfo {
2995 TailCallArgumentInfo() : FrameIdx(0) {}
3000 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3002 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3004 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
3005 SmallVector<SDValue, 8> &MemOpChains,
3007 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3008 SDValue Arg = TailCallArgs[i].Arg;
3009 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3010 int FI = TailCallArgs[i].FrameIdx;
3011 // Store relative to framepointer.
3012 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3013 MachinePointerInfo::getFixedStack(FI),
3018 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3019 /// the appropriate stack slot for the tail call optimized function call.
3020 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3021 MachineFunction &MF,
3030 // Calculate the new stack slot for the return address.
3031 int SlotSize = isPPC64 ? 8 : 4;
3032 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3034 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3035 NewRetAddrLoc, true);
3036 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3037 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3038 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3039 MachinePointerInfo::getFixedStack(NewRetAddr),
3042 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3043 // slot as the FP is never overwritten.
3046 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3047 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3049 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3050 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3051 MachinePointerInfo::getFixedStack(NewFPIdx),
3058 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3059 /// the position of the argument.
3061 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3062 SDValue Arg, int SPDiff, unsigned ArgOffset,
3063 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
3064 int Offset = ArgOffset + SPDiff;
3065 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3066 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3067 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3068 SDValue FIN = DAG.getFrameIndex(FI, VT);
3069 TailCallArgumentInfo Info;
3071 Info.FrameIdxOp = FIN;
3073 TailCallArguments.push_back(Info);
3076 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3077 /// stack slot. Returns the chain as result and the loaded frame pointers in
3078 /// LROpOut/FPOpout. Used when tail calling.
3079 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3085 DebugLoc dl) const {
3087 // Load the LR and FP stack slot for later adjusting.
3088 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3089 LROpOut = getReturnAddrFrameIndex(DAG);
3090 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3091 false, false, false, 0);
3092 Chain = SDValue(LROpOut.getNode(), 1);
3094 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3095 // slot as the FP is never overwritten.
3097 FPOpOut = getFramePointerFrameIndex(DAG);
3098 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3099 false, false, false, 0);
3100 Chain = SDValue(FPOpOut.getNode(), 1);
3106 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3107 /// by "Src" to address "Dst" of size "Size". Alignment information is
3108 /// specified by the specific parameter attribute. The copy will be passed as
3109 /// a byval function parameter.
3110 /// Sometimes what we are copying is the end of a larger object, the part that
3111 /// does not fit in registers.
3113 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3114 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3116 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3117 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3118 false, false, MachinePointerInfo(0),
3119 MachinePointerInfo(0));
3122 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3125 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3126 SDValue Arg, SDValue PtrOff, int SPDiff,
3127 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3128 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
3129 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
3131 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3136 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3138 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3139 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3140 DAG.getConstant(ArgOffset, PtrVT));
3142 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3143 MachinePointerInfo(), false, false, 0));
3144 // Calculate and remember argument location.
3145 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3150 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3151 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3152 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3153 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
3154 MachineFunction &MF = DAG.getMachineFunction();
3156 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3157 // might overwrite each other in case of tail call optimization.
3158 SmallVector<SDValue, 8> MemOpChains2;
3159 // Do not flag preceding copytoreg stuff together with the following stuff.
3161 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3163 if (!MemOpChains2.empty())
3164 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3165 &MemOpChains2[0], MemOpChains2.size());
3167 // Store the return address to the appropriate stack slot.
3168 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3169 isPPC64, isDarwinABI, dl);
3171 // Emit callseq_end just before tailcall node.
3172 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3173 DAG.getIntPtrConstant(0, true), InFlag);
3174 InFlag = Chain.getValue(1);
3178 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3179 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
3180 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
3181 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
3182 const PPCSubtarget &PPCSubTarget) {
3184 bool isPPC64 = PPCSubTarget.isPPC64();
3185 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3187 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3188 NodeTys.push_back(MVT::Other); // Returns a chain
3189 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3191 unsigned CallOpc = PPCISD::CALL;
3193 bool needIndirectCall = true;
3194 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3195 // If this is an absolute destination address, use the munged value.
3196 Callee = SDValue(Dest, 0);
3197 needIndirectCall = false;
3200 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3201 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3202 // Use indirect calls for ALL functions calls in JIT mode, since the
3203 // far-call stubs may be outside relocation limits for a BL instruction.
3204 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3205 unsigned OpFlags = 0;
3206 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3207 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3208 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3209 (G->getGlobal()->isDeclaration() ||
3210 G->getGlobal()->isWeakForLinker())) {
3211 // PC-relative references to external symbols should go through $stub,
3212 // unless we're building with the leopard linker or later, which
3213 // automatically synthesizes these stubs.
3214 OpFlags = PPCII::MO_DARWIN_STUB;
3217 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3218 // every direct call is) turn it into a TargetGlobalAddress /
3219 // TargetExternalSymbol node so that legalize doesn't hack it.
3220 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3221 Callee.getValueType(),
3223 needIndirectCall = false;
3227 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3228 unsigned char OpFlags = 0;
3230 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3231 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3232 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3233 // PC-relative references to external symbols should go through $stub,
3234 // unless we're building with the leopard linker or later, which
3235 // automatically synthesizes these stubs.
3236 OpFlags = PPCII::MO_DARWIN_STUB;
3239 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3241 needIndirectCall = false;
3244 if (needIndirectCall) {
3245 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3246 // to do the call, we can't use PPCISD::CALL.
3247 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3249 if (isSVR4ABI && isPPC64) {
3250 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3251 // entry point, but to the function descriptor (the function entry point
3252 // address is part of the function descriptor though).
3253 // The function descriptor is a three doubleword structure with the
3254 // following fields: function entry point, TOC base address and
3255 // environment pointer.
3256 // Thus for a call through a function pointer, the following actions need
3258 // 1. Save the TOC of the caller in the TOC save area of its stack
3259 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3260 // 2. Load the address of the function entry point from the function
3262 // 3. Load the TOC of the callee from the function descriptor into r2.
3263 // 4. Load the environment pointer from the function descriptor into
3265 // 5. Branch to the function entry point address.
3266 // 6. On return of the callee, the TOC of the caller needs to be
3267 // restored (this is done in FinishCall()).
3269 // All those operations are flagged together to ensure that no other
3270 // operations can be scheduled in between. E.g. without flagging the
3271 // operations together, a TOC access in the caller could be scheduled
3272 // between the load of the callee TOC and the branch to the callee, which
3273 // results in the TOC access going through the TOC of the callee instead
3274 // of going through the TOC of the caller, which leads to incorrect code.
3276 // Load the address of the function entry point from the function
3278 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3279 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
3280 InFlag.getNode() ? 3 : 2);
3281 Chain = LoadFuncPtr.getValue(1);
3282 InFlag = LoadFuncPtr.getValue(2);
3284 // Load environment pointer into r11.
3285 // Offset of the environment pointer within the function descriptor.
3286 SDValue PtrOff = DAG.getIntPtrConstant(16);
3288 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3289 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3291 Chain = LoadEnvPtr.getValue(1);
3292 InFlag = LoadEnvPtr.getValue(2);
3294 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3296 Chain = EnvVal.getValue(0);
3297 InFlag = EnvVal.getValue(1);
3299 // Load TOC of the callee into r2. We are using a target-specific load
3300 // with r2 hard coded, because the result of a target-independent load
3301 // would never go directly into r2, since r2 is a reserved register (which
3302 // prevents the register allocator from allocating it), resulting in an
3303 // additional register being allocated and an unnecessary move instruction
3305 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3306 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3308 Chain = LoadTOCPtr.getValue(0);
3309 InFlag = LoadTOCPtr.getValue(1);
3311 MTCTROps[0] = Chain;
3312 MTCTROps[1] = LoadFuncPtr;
3313 MTCTROps[2] = InFlag;
3316 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
3317 2 + (InFlag.getNode() != 0));
3318 InFlag = Chain.getValue(1);
3321 NodeTys.push_back(MVT::Other);
3322 NodeTys.push_back(MVT::Glue);
3323 Ops.push_back(Chain);
3324 CallOpc = PPCISD::BCTRL;
3326 // Add use of X11 (holding environment pointer)
3327 if (isSVR4ABI && isPPC64)
3328 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3329 // Add CTR register as callee so a bctr can be emitted later.
3331 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3334 // If this is a direct call, pass the chain and the callee.
3335 if (Callee.getNode()) {
3336 Ops.push_back(Chain);
3337 Ops.push_back(Callee);
3339 // If this is a tail call add stack pointer delta.
3341 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3343 // Add argument registers to the end of the list so that they are known live
3345 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3346 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3347 RegsToPass[i].second.getValueType()));
3353 bool isLocalCall(const SDValue &Callee)
3355 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3356 return !G->getGlobal()->isDeclaration() &&
3357 !G->getGlobal()->isWeakForLinker();
3362 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3363 CallingConv::ID CallConv, bool isVarArg,
3364 const SmallVectorImpl<ISD::InputArg> &Ins,
3365 DebugLoc dl, SelectionDAG &DAG,
3366 SmallVectorImpl<SDValue> &InVals) const {
3368 SmallVector<CCValAssign, 16> RVLocs;
3369 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3370 getTargetMachine(), RVLocs, *DAG.getContext());
3371 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3373 // Copy all of the result registers out of their specified physreg.
3374 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3375 CCValAssign &VA = RVLocs[i];
3376 assert(VA.isRegLoc() && "Can only return in registers!");
3378 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3379 VA.getLocReg(), VA.getLocVT(), InFlag);
3380 Chain = Val.getValue(1);
3381 InFlag = Val.getValue(2);
3383 switch (VA.getLocInfo()) {
3384 default: llvm_unreachable("Unknown loc info!");
3385 case CCValAssign::Full: break;
3386 case CCValAssign::AExt:
3387 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3389 case CCValAssign::ZExt:
3390 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3391 DAG.getValueType(VA.getValVT()));
3392 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3394 case CCValAssign::SExt:
3395 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3396 DAG.getValueType(VA.getValVT()));
3397 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3401 InVals.push_back(Val);
3408 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
3409 bool isTailCall, bool isVarArg,
3411 SmallVector<std::pair<unsigned, SDValue>, 8>
3413 SDValue InFlag, SDValue Chain,
3415 int SPDiff, unsigned NumBytes,
3416 const SmallVectorImpl<ISD::InputArg> &Ins,
3417 SmallVectorImpl<SDValue> &InVals) const {
3418 std::vector<EVT> NodeTys;
3419 SmallVector<SDValue, 8> Ops;
3420 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3421 isTailCall, RegsToPass, Ops, NodeTys,
3424 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3425 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3426 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3428 // When performing tail call optimization the callee pops its arguments off
3429 // the stack. Account for this here so these bytes can be pushed back on in
3430 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3431 int BytesCalleePops =
3432 (CallConv == CallingConv::Fast &&
3433 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3435 // Add a register mask operand representing the call-preserved registers.
3436 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3437 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3438 assert(Mask && "Missing call preserved mask for calling convention");
3439 Ops.push_back(DAG.getRegisterMask(Mask));
3441 if (InFlag.getNode())
3442 Ops.push_back(InFlag);
3446 assert(((Callee.getOpcode() == ISD::Register &&
3447 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3448 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3449 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3450 isa<ConstantSDNode>(Callee)) &&
3451 "Expecting an global address, external symbol, absolute value or register");
3453 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3456 // Add a NOP immediately after the branch instruction when using the 64-bit
3457 // SVR4 ABI. At link time, if caller and callee are in a different module and
3458 // thus have a different TOC, the call will be replaced with a call to a stub
3459 // function which saves the current TOC, loads the TOC of the callee and
3460 // branches to the callee. The NOP will be replaced with a load instruction
3461 // which restores the TOC of the caller from the TOC save slot of the current
3462 // stack frame. If caller and callee belong to the same module (and have the
3463 // same TOC), the NOP will remain unchanged.
3465 bool needsTOCRestore = false;
3466 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3467 if (CallOpc == PPCISD::BCTRL) {
3468 // This is a call through a function pointer.
3469 // Restore the caller TOC from the save area into R2.
3470 // See PrepareCall() for more information about calls through function
3471 // pointers in the 64-bit SVR4 ABI.
3472 // We are using a target-specific load with r2 hard coded, because the
3473 // result of a target-independent load would never go directly into r2,
3474 // since r2 is a reserved register (which prevents the register allocator
3475 // from allocating it), resulting in an additional register being
3476 // allocated and an unnecessary move instruction being generated.
3477 needsTOCRestore = true;
3478 } else if ((CallOpc == PPCISD::CALL) && !isLocalCall(Callee)) {
3479 // Otherwise insert NOP for non-local calls.
3480 CallOpc = PPCISD::CALL_NOP;
3484 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
3485 InFlag = Chain.getValue(1);
3487 if (needsTOCRestore) {
3488 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3489 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3490 InFlag = Chain.getValue(1);
3493 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3494 DAG.getIntPtrConstant(BytesCalleePops, true),
3497 InFlag = Chain.getValue(1);
3499 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3500 Ins, dl, DAG, InVals);
3504 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3505 SmallVectorImpl<SDValue> &InVals) const {
3506 SelectionDAG &DAG = CLI.DAG;
3507 DebugLoc &dl = CLI.DL;
3508 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
3509 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
3510 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
3511 SDValue Chain = CLI.Chain;
3512 SDValue Callee = CLI.Callee;
3513 bool &isTailCall = CLI.IsTailCall;
3514 CallingConv::ID CallConv = CLI.CallConv;
3515 bool isVarArg = CLI.IsVarArg;
3518 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3521 if (PPCSubTarget.isSVR4ABI()) {
3522 if (PPCSubTarget.isPPC64())
3523 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3524 isTailCall, Outs, OutVals, Ins,
3527 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3528 isTailCall, Outs, OutVals, Ins,
3532 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3533 isTailCall, Outs, OutVals, Ins,
3538 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3539 CallingConv::ID CallConv, bool isVarArg,
3541 const SmallVectorImpl<ISD::OutputArg> &Outs,
3542 const SmallVectorImpl<SDValue> &OutVals,
3543 const SmallVectorImpl<ISD::InputArg> &Ins,
3544 DebugLoc dl, SelectionDAG &DAG,
3545 SmallVectorImpl<SDValue> &InVals) const {
3546 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3547 // of the 32-bit SVR4 ABI stack frame layout.
3549 assert((CallConv == CallingConv::C ||
3550 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3552 unsigned PtrByteSize = 4;
3554 MachineFunction &MF = DAG.getMachineFunction();
3556 // Mark this function as potentially containing a function that contains a
3557 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3558 // and restoring the callers stack pointer in this functions epilog. This is
3559 // done because by tail calling the called function might overwrite the value
3560 // in this function's (MF) stack pointer stack slot 0(SP).
3561 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3562 CallConv == CallingConv::Fast)
3563 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3565 // Count how many bytes are to be pushed on the stack, including the linkage
3566 // area, parameter list area and the part of the local variable space which
3567 // contains copies of aggregates which are passed by value.
3569 // Assign locations to all of the outgoing arguments.
3570 SmallVector<CCValAssign, 16> ArgLocs;
3571 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3572 getTargetMachine(), ArgLocs, *DAG.getContext());
3574 // Reserve space for the linkage area on the stack.
3575 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3578 // Handle fixed and variable vector arguments differently.
3579 // Fixed vector arguments go into registers as long as registers are
3580 // available. Variable vector arguments always go into memory.
3581 unsigned NumArgs = Outs.size();
3583 for (unsigned i = 0; i != NumArgs; ++i) {
3584 MVT ArgVT = Outs[i].VT;
3585 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3588 if (Outs[i].IsFixed) {
3589 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3592 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3598 errs() << "Call operand #" << i << " has unhandled type "
3599 << EVT(ArgVT).getEVTString() << "\n";
3601 llvm_unreachable(0);
3605 // All arguments are treated the same.
3606 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3609 // Assign locations to all of the outgoing aggregate by value arguments.
3610 SmallVector<CCValAssign, 16> ByValArgLocs;
3611 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3612 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3614 // Reserve stack space for the allocations in CCInfo.
3615 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3617 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3619 // Size of the linkage area, parameter list area and the part of the local
3620 // space variable where copies of aggregates which are passed by value are
3622 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3624 // Calculate by how many bytes the stack has to be adjusted in case of tail
3625 // call optimization.
3626 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3628 // Adjust the stack pointer for the new arguments...
3629 // These operations are automatically eliminated by the prolog/epilog pass
3630 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3631 SDValue CallSeqStart = Chain;
3633 // Load the return address and frame pointer so it can be moved somewhere else
3636 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3639 // Set up a copy of the stack pointer for use loading and storing any
3640 // arguments that may not fit in the registers available for argument
3642 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3644 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3645 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3646 SmallVector<SDValue, 8> MemOpChains;
3648 bool seenFloatArg = false;
3649 // Walk the register/memloc assignments, inserting copies/loads.
3650 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3653 CCValAssign &VA = ArgLocs[i];
3654 SDValue Arg = OutVals[i];
3655 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3657 if (Flags.isByVal()) {
3658 // Argument is an aggregate which is passed by value, thus we need to
3659 // create a copy of it in the local variable space of the current stack
3660 // frame (which is the stack frame of the caller) and pass the address of
3661 // this copy to the callee.
3662 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3663 CCValAssign &ByValVA = ByValArgLocs[j++];
3664 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3666 // Memory reserved in the local variable space of the callers stack frame.
3667 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3669 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3670 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3672 // Create a copy of the argument in the local area of the current
3674 SDValue MemcpyCall =
3675 CreateCopyOfByValArgument(Arg, PtrOff,
3676 CallSeqStart.getNode()->getOperand(0),
3679 // This must go outside the CALLSEQ_START..END.
3680 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3681 CallSeqStart.getNode()->getOperand(1));
3682 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3683 NewCallSeqStart.getNode());
3684 Chain = CallSeqStart = NewCallSeqStart;
3686 // Pass the address of the aggregate copy on the stack either in a
3687 // physical register or in the parameter list area of the current stack
3688 // frame to the callee.
3692 if (VA.isRegLoc()) {
3693 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3694 // Put argument in a physical register.
3695 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3697 // Put argument in the parameter list area of the current stack frame.
3698 assert(VA.isMemLoc());
3699 unsigned LocMemOffset = VA.getLocMemOffset();
3702 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3703 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3705 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3706 MachinePointerInfo(),
3709 // Calculate and remember argument location.
3710 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3716 if (!MemOpChains.empty())
3717 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3718 &MemOpChains[0], MemOpChains.size());
3720 // Build a sequence of copy-to-reg nodes chained together with token chain
3721 // and flag operands which copy the outgoing args into the appropriate regs.
3723 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3724 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3725 RegsToPass[i].second, InFlag);
3726 InFlag = Chain.getValue(1);
3729 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3732 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3733 SDValue Ops[] = { Chain, InFlag };
3735 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3736 dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
3738 InFlag = Chain.getValue(1);
3742 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3743 false, TailCallArguments);
3745 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3746 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3750 // Copy an argument into memory, being careful to do this outside the
3751 // call sequence for the call to which the argument belongs.
3753 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3754 SDValue CallSeqStart,
3755 ISD::ArgFlagsTy Flags,
3757 DebugLoc dl) const {
3758 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3759 CallSeqStart.getNode()->getOperand(0),
3761 // The MEMCPY must go outside the CALLSEQ_START..END.
3762 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3763 CallSeqStart.getNode()->getOperand(1));
3764 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3765 NewCallSeqStart.getNode());
3766 return NewCallSeqStart;
3770 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3771 CallingConv::ID CallConv, bool isVarArg,
3773 const SmallVectorImpl<ISD::OutputArg> &Outs,
3774 const SmallVectorImpl<SDValue> &OutVals,
3775 const SmallVectorImpl<ISD::InputArg> &Ins,
3776 DebugLoc dl, SelectionDAG &DAG,
3777 SmallVectorImpl<SDValue> &InVals) const {
3779 unsigned NumOps = Outs.size();
3781 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3782 unsigned PtrByteSize = 8;
3784 MachineFunction &MF = DAG.getMachineFunction();
3786 // Mark this function as potentially containing a function that contains a
3787 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3788 // and restoring the callers stack pointer in this functions epilog. This is
3789 // done because by tail calling the called function might overwrite the value
3790 // in this function's (MF) stack pointer stack slot 0(SP).
3791 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3792 CallConv == CallingConv::Fast)
3793 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3795 unsigned nAltivecParamsAtEnd = 0;
3797 // Count how many bytes are to be pushed on the stack, including the linkage
3798 // area, and parameter passing area. We start with at least 48 bytes, which
3799 // is reserved space for [SP][CR][LR][3 x unused].
3800 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
3803 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
3804 Outs, OutVals, nAltivecParamsAtEnd);
3806 // Calculate by how many bytes the stack has to be adjusted in case of tail
3807 // call optimization.
3808 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3810 // To protect arguments on the stack from being clobbered in a tail call,
3811 // force all the loads to happen before doing any other lowering.
3813 Chain = DAG.getStackArgumentTokenFactor(Chain);
3815 // Adjust the stack pointer for the new arguments...
3816 // These operations are automatically eliminated by the prolog/epilog pass
3817 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3818 SDValue CallSeqStart = Chain;
3820 // Load the return address and frame pointer so it can be move somewhere else
3823 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3826 // Set up a copy of the stack pointer for use loading and storing any
3827 // arguments that may not fit in the registers available for argument
3829 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3831 // Figure out which arguments are going to go in registers, and which in
3832 // memory. Also, if this is a vararg function, floating point operations
3833 // must be stored to our stack, and loaded into integer regs as well, if
3834 // any integer regs are available for argument passing.
3835 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
3836 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3838 static const uint16_t GPR[] = {
3839 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3840 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3842 static const uint16_t *FPR = GetFPR();
3844 static const uint16_t VR[] = {
3845 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3846 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3848 const unsigned NumGPRs = array_lengthof(GPR);
3849 const unsigned NumFPRs = 13;
3850 const unsigned NumVRs = array_lengthof(VR);
3852 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3853 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3855 SmallVector<SDValue, 8> MemOpChains;
3856 for (unsigned i = 0; i != NumOps; ++i) {
3857 SDValue Arg = OutVals[i];
3858 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3860 // PtrOff will be used to store the current argument to the stack if a
3861 // register cannot be found for it.
3864 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3866 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3868 // Promote integers to 64-bit values.
3869 if (Arg.getValueType() == MVT::i32) {
3870 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3871 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3872 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3875 // FIXME memcpy is used way more than necessary. Correctness first.
3876 // Note: "by value" is code for passing a structure by value, not
3878 if (Flags.isByVal()) {
3879 // Note: Size includes alignment padding, so
3880 // struct x { short a; char b; }
3881 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
3882 // These are the proper values we need for right-justifying the
3883 // aggregate in a parameter register.
3884 unsigned Size = Flags.getByValSize();
3886 // An empty aggregate parameter takes up no storage and no
3891 // All aggregates smaller than 8 bytes must be passed right-justified.
3892 if (Size==1 || Size==2 || Size==4) {
3893 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
3894 if (GPR_idx != NumGPRs) {
3895 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3896 MachinePointerInfo(), VT,
3898 MemOpChains.push_back(Load.getValue(1));
3899 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3901 ArgOffset += PtrByteSize;
3906 if (GPR_idx == NumGPRs && Size < 8) {
3907 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3908 PtrOff.getValueType());
3909 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3910 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3913 ArgOffset += PtrByteSize;
3916 // Copy entire object into memory. There are cases where gcc-generated
3917 // code assumes it is there, even if it could be put entirely into
3918 // registers. (This is not what the doc says.)
3920 // FIXME: The above statement is likely due to a misunderstanding of the
3921 // documents. All arguments must be copied into the parameter area BY
3922 // THE CALLEE in the event that the callee takes the address of any
3923 // formal argument. That has not yet been implemented. However, it is
3924 // reasonable to use the stack area as a staging area for the register
3927 // Skip this for small aggregates, as we will use the same slot for a
3928 // right-justified copy, below.
3930 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
3934 // When a register is available, pass a small aggregate right-justified.
3935 if (Size < 8 && GPR_idx != NumGPRs) {
3936 // The easiest way to get this right-justified in a register
3937 // is to copy the structure into the rightmost portion of a
3938 // local variable slot, then load the whole slot into the
3940 // FIXME: The memcpy seems to produce pretty awful code for
3941 // small aggregates, particularly for packed ones.
3942 // FIXME: It would be preferable to use the slot in the
3943 // parameter save area instead of a new local variable.
3944 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
3945 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3946 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3950 // Load the slot into the register.
3951 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
3952 MachinePointerInfo(),
3953 false, false, false, 0);
3954 MemOpChains.push_back(Load.getValue(1));
3955 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3957 // Done with this argument.
3958 ArgOffset += PtrByteSize;
3962 // For aggregates larger than PtrByteSize, copy the pieces of the
3963 // object that fit into registers from the parameter save area.
3964 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3965 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3966 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3967 if (GPR_idx != NumGPRs) {
3968 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3969 MachinePointerInfo(),
3970 false, false, false, 0);
3971 MemOpChains.push_back(Load.getValue(1));
3972 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3973 ArgOffset += PtrByteSize;
3975 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3982 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3983 default: llvm_unreachable("Unexpected ValueType for argument!");
3986 if (GPR_idx != NumGPRs) {
3987 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3989 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3990 true, isTailCall, false, MemOpChains,
3991 TailCallArguments, dl);
3993 ArgOffset += PtrByteSize;
3997 if (FPR_idx != NumFPRs) {
3998 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4001 // A single float or an aggregate containing only a single float
4002 // must be passed right-justified in the stack doubleword, and
4003 // in the GPR, if one is available.
4005 if (Arg.getValueType().getSimpleVT().SimpleTy == MVT::f32) {
4006 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4007 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4011 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
4012 MachinePointerInfo(), false, false, 0);
4013 MemOpChains.push_back(Store);
4015 // Float varargs are always shadowed in available integer registers
4016 if (GPR_idx != NumGPRs) {
4017 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4018 MachinePointerInfo(), false, false,
4020 MemOpChains.push_back(Load.getValue(1));
4021 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4023 } else if (GPR_idx != NumGPRs)
4024 // If we have any FPRs remaining, we may also have GPRs remaining.
4027 // Single-precision floating-point values are mapped to the
4028 // second (rightmost) word of the stack doubleword.
4029 if (Arg.getValueType() == MVT::f32) {
4030 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4031 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4034 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4035 true, isTailCall, false, MemOpChains,
4036 TailCallArguments, dl);
4045 // These go aligned on the stack, or in the corresponding R registers
4046 // when within range. The Darwin PPC ABI doc claims they also go in
4047 // V registers; in fact gcc does this only for arguments that are
4048 // prototyped, not for those that match the ... We do it for all
4049 // arguments, seems to work.
4050 while (ArgOffset % 16 !=0) {
4051 ArgOffset += PtrByteSize;
4052 if (GPR_idx != NumGPRs)
4055 // We could elide this store in the case where the object fits
4056 // entirely in R registers. Maybe later.
4057 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4058 DAG.getConstant(ArgOffset, PtrVT));
4059 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4060 MachinePointerInfo(), false, false, 0);
4061 MemOpChains.push_back(Store);
4062 if (VR_idx != NumVRs) {
4063 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4064 MachinePointerInfo(),
4065 false, false, false, 0);
4066 MemOpChains.push_back(Load.getValue(1));
4067 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4070 for (unsigned i=0; i<16; i+=PtrByteSize) {
4071 if (GPR_idx == NumGPRs)
4073 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4074 DAG.getConstant(i, PtrVT));
4075 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4076 false, false, false, 0);
4077 MemOpChains.push_back(Load.getValue(1));
4078 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4083 // Non-varargs Altivec params generally go in registers, but have
4084 // stack space allocated at the end.
4085 if (VR_idx != NumVRs) {
4086 // Doesn't have GPR space allocated.
4087 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4089 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4090 true, isTailCall, true, MemOpChains,
4091 TailCallArguments, dl);
4098 if (!MemOpChains.empty())
4099 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4100 &MemOpChains[0], MemOpChains.size());
4102 // Check if this is an indirect call (MTCTR/BCTRL).
4103 // See PrepareCall() for more information about calls through function
4104 // pointers in the 64-bit SVR4 ABI.
4106 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4107 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4108 !isBLACompatibleAddress(Callee, DAG)) {
4109 // Load r2 into a virtual register and store it to the TOC save area.
4110 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4111 // TOC save area offset.
4112 SDValue PtrOff = DAG.getIntPtrConstant(40);
4113 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4114 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4116 // R12 must contain the address of an indirect callee. This does not
4117 // mean the MTCTR instruction must use R12; it's easier to model this
4118 // as an extra parameter, so do that.
4119 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4122 // Build a sequence of copy-to-reg nodes chained together with token chain
4123 // and flag operands which copy the outgoing args into the appropriate regs.
4125 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4126 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4127 RegsToPass[i].second, InFlag);
4128 InFlag = Chain.getValue(1);
4132 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4133 FPOp, true, TailCallArguments);
4135 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4136 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4141 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4142 CallingConv::ID CallConv, bool isVarArg,
4144 const SmallVectorImpl<ISD::OutputArg> &Outs,
4145 const SmallVectorImpl<SDValue> &OutVals,
4146 const SmallVectorImpl<ISD::InputArg> &Ins,
4147 DebugLoc dl, SelectionDAG &DAG,
4148 SmallVectorImpl<SDValue> &InVals) const {
4150 unsigned NumOps = Outs.size();
4152 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4153 bool isPPC64 = PtrVT == MVT::i64;
4154 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4156 MachineFunction &MF = DAG.getMachineFunction();
4158 // Mark this function as potentially containing a function that contains a
4159 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4160 // and restoring the callers stack pointer in this functions epilog. This is
4161 // done because by tail calling the called function might overwrite the value
4162 // in this function's (MF) stack pointer stack slot 0(SP).
4163 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4164 CallConv == CallingConv::Fast)
4165 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4167 unsigned nAltivecParamsAtEnd = 0;
4169 // Count how many bytes are to be pushed on the stack, including the linkage
4170 // area, and parameter passing area. We start with 24/48 bytes, which is
4171 // prereserved space for [SP][CR][LR][3 x unused].
4173 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4175 nAltivecParamsAtEnd);
4177 // Calculate by how many bytes the stack has to be adjusted in case of tail
4178 // call optimization.
4179 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4181 // To protect arguments on the stack from being clobbered in a tail call,
4182 // force all the loads to happen before doing any other lowering.
4184 Chain = DAG.getStackArgumentTokenFactor(Chain);
4186 // Adjust the stack pointer for the new arguments...
4187 // These operations are automatically eliminated by the prolog/epilog pass
4188 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
4189 SDValue CallSeqStart = Chain;
4191 // Load the return address and frame pointer so it can be move somewhere else
4194 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4197 // Set up a copy of the stack pointer for use loading and storing any
4198 // arguments that may not fit in the registers available for argument
4202 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4204 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4206 // Figure out which arguments are going to go in registers, and which in
4207 // memory. Also, if this is a vararg function, floating point operations
4208 // must be stored to our stack, and loaded into integer regs as well, if
4209 // any integer regs are available for argument passing.
4210 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4211 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4213 static const uint16_t GPR_32[] = { // 32-bit registers.
4214 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4215 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4217 static const uint16_t GPR_64[] = { // 64-bit registers.
4218 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4219 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4221 static const uint16_t *FPR = GetFPR();
4223 static const uint16_t VR[] = {
4224 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4225 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4227 const unsigned NumGPRs = array_lengthof(GPR_32);
4228 const unsigned NumFPRs = 13;
4229 const unsigned NumVRs = array_lengthof(VR);
4231 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4233 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4234 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4236 SmallVector<SDValue, 8> MemOpChains;
4237 for (unsigned i = 0; i != NumOps; ++i) {
4238 SDValue Arg = OutVals[i];
4239 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4241 // PtrOff will be used to store the current argument to the stack if a
4242 // register cannot be found for it.
4245 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4247 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4249 // On PPC64, promote integers to 64-bit values.
4250 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4251 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4252 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4253 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4256 // FIXME memcpy is used way more than necessary. Correctness first.
4257 // Note: "by value" is code for passing a structure by value, not
4259 if (Flags.isByVal()) {
4260 unsigned Size = Flags.getByValSize();
4261 // Very small objects are passed right-justified. Everything else is
4262 // passed left-justified.
4263 if (Size==1 || Size==2) {
4264 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4265 if (GPR_idx != NumGPRs) {
4266 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4267 MachinePointerInfo(), VT,
4269 MemOpChains.push_back(Load.getValue(1));
4270 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4272 ArgOffset += PtrByteSize;
4274 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4275 PtrOff.getValueType());
4276 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4277 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4280 ArgOffset += PtrByteSize;
4284 // Copy entire object into memory. There are cases where gcc-generated
4285 // code assumes it is there, even if it could be put entirely into
4286 // registers. (This is not what the doc says.)
4287 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4291 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4292 // copy the pieces of the object that fit into registers from the
4293 // parameter save area.
4294 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4295 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4296 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4297 if (GPR_idx != NumGPRs) {
4298 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4299 MachinePointerInfo(),
4300 false, false, false, 0);
4301 MemOpChains.push_back(Load.getValue(1));
4302 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4303 ArgOffset += PtrByteSize;
4305 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4312 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
4313 default: llvm_unreachable("Unexpected ValueType for argument!");
4316 if (GPR_idx != NumGPRs) {
4317 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4319 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4320 isPPC64, isTailCall, false, MemOpChains,
4321 TailCallArguments, dl);
4323 ArgOffset += PtrByteSize;
4327 if (FPR_idx != NumFPRs) {
4328 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4331 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4332 MachinePointerInfo(), false, false, 0);
4333 MemOpChains.push_back(Store);
4335 // Float varargs are always shadowed in available integer registers
4336 if (GPR_idx != NumGPRs) {
4337 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4338 MachinePointerInfo(), false, false,
4340 MemOpChains.push_back(Load.getValue(1));
4341 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4343 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4344 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4345 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4346 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4347 MachinePointerInfo(),
4348 false, false, false, 0);
4349 MemOpChains.push_back(Load.getValue(1));
4350 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4353 // If we have any FPRs remaining, we may also have GPRs remaining.
4354 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4356 if (GPR_idx != NumGPRs)
4358 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4359 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4363 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4364 isPPC64, isTailCall, false, MemOpChains,
4365 TailCallArguments, dl);
4369 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4376 // These go aligned on the stack, or in the corresponding R registers
4377 // when within range. The Darwin PPC ABI doc claims they also go in
4378 // V registers; in fact gcc does this only for arguments that are
4379 // prototyped, not for those that match the ... We do it for all
4380 // arguments, seems to work.
4381 while (ArgOffset % 16 !=0) {
4382 ArgOffset += PtrByteSize;
4383 if (GPR_idx != NumGPRs)
4386 // We could elide this store in the case where the object fits
4387 // entirely in R registers. Maybe later.
4388 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4389 DAG.getConstant(ArgOffset, PtrVT));
4390 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4391 MachinePointerInfo(), false, false, 0);
4392 MemOpChains.push_back(Store);
4393 if (VR_idx != NumVRs) {
4394 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4395 MachinePointerInfo(),
4396 false, false, false, 0);
4397 MemOpChains.push_back(Load.getValue(1));
4398 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4401 for (unsigned i=0; i<16; i+=PtrByteSize) {
4402 if (GPR_idx == NumGPRs)
4404 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4405 DAG.getConstant(i, PtrVT));
4406 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4407 false, false, false, 0);
4408 MemOpChains.push_back(Load.getValue(1));
4409 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4414 // Non-varargs Altivec params generally go in registers, but have
4415 // stack space allocated at the end.
4416 if (VR_idx != NumVRs) {
4417 // Doesn't have GPR space allocated.
4418 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4419 } else if (nAltivecParamsAtEnd==0) {
4420 // We are emitting Altivec params in order.
4421 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4422 isPPC64, isTailCall, true, MemOpChains,
4423 TailCallArguments, dl);
4429 // If all Altivec parameters fit in registers, as they usually do,
4430 // they get stack space following the non-Altivec parameters. We
4431 // don't track this here because nobody below needs it.
4432 // If there are more Altivec parameters than fit in registers emit
4434 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4436 // Offset is aligned; skip 1st 12 params which go in V registers.
4437 ArgOffset = ((ArgOffset+15)/16)*16;
4439 for (unsigned i = 0; i != NumOps; ++i) {
4440 SDValue Arg = OutVals[i];
4441 EVT ArgType = Outs[i].VT;
4442 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4443 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4446 // We are emitting Altivec params in order.
4447 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4448 isPPC64, isTailCall, true, MemOpChains,
4449 TailCallArguments, dl);
4456 if (!MemOpChains.empty())
4457 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4458 &MemOpChains[0], MemOpChains.size());
4460 // On Darwin, R12 must contain the address of an indirect callee. This does
4461 // not mean the MTCTR instruction must use R12; it's easier to model this as
4462 // an extra parameter, so do that.
4464 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4465 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4466 !isBLACompatibleAddress(Callee, DAG))
4467 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4468 PPC::R12), Callee));
4470 // Build a sequence of copy-to-reg nodes chained together with token chain
4471 // and flag operands which copy the outgoing args into the appropriate regs.
4473 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4474 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4475 RegsToPass[i].second, InFlag);
4476 InFlag = Chain.getValue(1);
4480 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4481 FPOp, true, TailCallArguments);
4483 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4484 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4489 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4490 MachineFunction &MF, bool isVarArg,
4491 const SmallVectorImpl<ISD::OutputArg> &Outs,
4492 LLVMContext &Context) const {
4493 SmallVector<CCValAssign, 16> RVLocs;
4494 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4496 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4500 PPCTargetLowering::LowerReturn(SDValue Chain,
4501 CallingConv::ID CallConv, bool isVarArg,
4502 const SmallVectorImpl<ISD::OutputArg> &Outs,
4503 const SmallVectorImpl<SDValue> &OutVals,
4504 DebugLoc dl, SelectionDAG &DAG) const {
4506 SmallVector<CCValAssign, 16> RVLocs;
4507 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4508 getTargetMachine(), RVLocs, *DAG.getContext());
4509 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4512 SmallVector<SDValue, 4> RetOps(1, Chain);
4514 // Copy the result values into the output registers.
4515 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4516 CCValAssign &VA = RVLocs[i];
4517 assert(VA.isRegLoc() && "Can only return in registers!");
4519 SDValue Arg = OutVals[i];
4521 switch (VA.getLocInfo()) {
4522 default: llvm_unreachable("Unknown loc info!");
4523 case CCValAssign::Full: break;
4524 case CCValAssign::AExt:
4525 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4527 case CCValAssign::ZExt:
4528 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4530 case CCValAssign::SExt:
4531 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4535 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4536 Flag = Chain.getValue(1);
4537 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4540 RetOps[0] = Chain; // Update chain.
4542 // Add the flag if we have it.
4544 RetOps.push_back(Flag);
4546 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4547 &RetOps[0], RetOps.size());
4550 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4551 const PPCSubtarget &Subtarget) const {
4552 // When we pop the dynamic allocation we need to restore the SP link.
4553 DebugLoc dl = Op.getDebugLoc();
4555 // Get the corect type for pointers.
4556 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4558 // Construct the stack pointer operand.
4559 bool isPPC64 = Subtarget.isPPC64();
4560 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4561 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4563 // Get the operands for the STACKRESTORE.
4564 SDValue Chain = Op.getOperand(0);
4565 SDValue SaveSP = Op.getOperand(1);
4567 // Load the old link SP.
4568 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4569 MachinePointerInfo(),
4570 false, false, false, 0);
4572 // Restore the stack pointer.
4573 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4575 // Store the old link SP.
4576 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4583 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4584 MachineFunction &MF = DAG.getMachineFunction();
4585 bool isPPC64 = PPCSubTarget.isPPC64();
4586 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4587 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4589 // Get current frame pointer save index. The users of this index will be
4590 // primarily DYNALLOC instructions.
4591 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4592 int RASI = FI->getReturnAddrSaveIndex();
4594 // If the frame pointer save index hasn't been defined yet.
4596 // Find out what the fix offset of the frame pointer save area.
4597 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4598 // Allocate the frame index for frame pointer save area.
4599 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4601 FI->setReturnAddrSaveIndex(RASI);
4603 return DAG.getFrameIndex(RASI, PtrVT);
4607 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4608 MachineFunction &MF = DAG.getMachineFunction();
4609 bool isPPC64 = PPCSubTarget.isPPC64();
4610 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4611 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4613 // Get current frame pointer save index. The users of this index will be
4614 // primarily DYNALLOC instructions.
4615 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4616 int FPSI = FI->getFramePointerSaveIndex();
4618 // If the frame pointer save index hasn't been defined yet.
4620 // Find out what the fix offset of the frame pointer save area.
4621 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4624 // Allocate the frame index for frame pointer save area.
4625 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4627 FI->setFramePointerSaveIndex(FPSI);
4629 return DAG.getFrameIndex(FPSI, PtrVT);
4632 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4634 const PPCSubtarget &Subtarget) const {
4636 SDValue Chain = Op.getOperand(0);
4637 SDValue Size = Op.getOperand(1);
4638 DebugLoc dl = Op.getDebugLoc();
4640 // Get the corect type for pointers.
4641 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4643 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4644 DAG.getConstant(0, PtrVT), Size);
4645 // Construct a node for the frame pointer save index.
4646 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4647 // Build a DYNALLOC node.
4648 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4649 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4650 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
4653 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4654 SelectionDAG &DAG) const {
4655 DebugLoc DL = Op.getDebugLoc();
4656 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4657 DAG.getVTList(MVT::i32, MVT::Other),
4658 Op.getOperand(0), Op.getOperand(1));
4661 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4662 SelectionDAG &DAG) const {
4663 DebugLoc DL = Op.getDebugLoc();
4664 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4665 Op.getOperand(0), Op.getOperand(1));
4668 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4670 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4671 // Not FP? Not a fsel.
4672 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4673 !Op.getOperand(2).getValueType().isFloatingPoint())
4676 // We might be able to do better than this under some circumstances, but in
4677 // general, fsel-based lowering of select is a finite-math-only optimization.
4678 // For more information, see section F.3 of the 2.06 ISA specification.
4679 if (!DAG.getTarget().Options.NoInfsFPMath ||
4680 !DAG.getTarget().Options.NoNaNsFPMath)
4683 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4685 EVT ResVT = Op.getValueType();
4686 EVT CmpVT = Op.getOperand(0).getValueType();
4687 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4688 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4689 DebugLoc dl = Op.getDebugLoc();
4691 // If the RHS of the comparison is a 0.0, we don't need to do the
4692 // subtraction at all.
4694 if (isFloatingPointZero(RHS))
4696 default: break; // SETUO etc aren't handled by fsel.
4700 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4701 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4702 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4703 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4704 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4705 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4706 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
4709 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4712 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4713 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4714 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4717 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4720 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4721 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4722 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4723 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4728 default: break; // SETUO etc aren't handled by fsel.
4732 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4733 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4734 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4735 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4736 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4737 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4738 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4739 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
4742 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4743 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4744 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4745 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4748 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4749 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4750 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4751 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4754 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4755 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4756 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4757 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4760 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4761 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4762 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4763 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4768 // FIXME: Split this code up when LegalizeDAGTypes lands.
4769 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
4770 DebugLoc dl) const {
4771 assert(Op.getOperand(0).getValueType().isFloatingPoint());
4772 SDValue Src = Op.getOperand(0);
4773 if (Src.getValueType() == MVT::f32)
4774 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4777 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4778 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
4780 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4781 (PPCSubTarget.hasFPCVT() ? PPCISD::FCTIWUZ :
4786 assert((Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT()) &&
4787 "i64 FP_TO_UINT is supported only with FPCVT");
4788 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
4794 // Convert the FP value to an int value through memory.
4795 bool i32Stack = Op.getValueType() == MVT::i32 && PPCSubTarget.hasSTFIWX() &&
4796 (Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT());
4797 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
4798 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
4799 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
4801 // Emit a store to the stack slot.
4804 MachineFunction &MF = DAG.getMachineFunction();
4805 MachineMemOperand *MMO =
4806 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
4807 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
4808 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
4809 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
4812 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
4813 MPI, false, false, 0);
4815 // Result is a load from the stack slot. If loading 4 bytes, make sure to
4817 if (Op.getValueType() == MVT::i32 && !i32Stack) {
4818 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
4819 DAG.getConstant(4, FIPtr.getValueType()));
4820 MPI = MachinePointerInfo();
4823 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
4824 false, false, false, 0);
4827 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
4828 SelectionDAG &DAG) const {
4829 DebugLoc dl = Op.getDebugLoc();
4830 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
4831 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4834 assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) &&
4835 "UINT_TO_FP is supported only with FPCVT");
4837 // If we have FCFIDS, then use it when converting to single-precision.
4838 // Otherwise, convert to double-precision and then round.
4839 unsigned FCFOp = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4840 (Op.getOpcode() == ISD::UINT_TO_FP ?
4841 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
4842 (Op.getOpcode() == ISD::UINT_TO_FP ?
4843 PPCISD::FCFIDU : PPCISD::FCFID);
4844 MVT FCFTy = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4845 MVT::f32 : MVT::f64;
4847 if (Op.getOperand(0).getValueType() == MVT::i64) {
4848 SDValue SINT = Op.getOperand(0);
4849 // When converting to single-precision, we actually need to convert
4850 // to double-precision first and then round to single-precision.
4851 // To avoid double-rounding effects during that operation, we have
4852 // to prepare the input operand. Bits that might be truncated when
4853 // converting to double-precision are replaced by a bit that won't
4854 // be lost at this stage, but is below the single-precision rounding
4857 // However, if -enable-unsafe-fp-math is in effect, accept double
4858 // rounding to avoid the extra overhead.
4859 if (Op.getValueType() == MVT::f32 &&
4860 !PPCSubTarget.hasFPCVT() &&
4861 !DAG.getTarget().Options.UnsafeFPMath) {
4863 // Twiddle input to make sure the low 11 bits are zero. (If this
4864 // is the case, we are guaranteed the value will fit into the 53 bit
4865 // mantissa of an IEEE double-precision value without rounding.)
4866 // If any of those low 11 bits were not zero originally, make sure
4867 // bit 12 (value 2048) is set instead, so that the final rounding
4868 // to single-precision gets the correct result.
4869 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4870 SINT, DAG.getConstant(2047, MVT::i64));
4871 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4872 Round, DAG.getConstant(2047, MVT::i64));
4873 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4874 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4875 Round, DAG.getConstant(-2048, MVT::i64));
4877 // However, we cannot use that value unconditionally: if the magnitude
4878 // of the input value is small, the bit-twiddling we did above might
4879 // end up visibly changing the output. Fortunately, in that case, we
4880 // don't need to twiddle bits since the original input will convert
4881 // exactly to double-precision floating-point already. Therefore,
4882 // construct a conditional to use the original value if the top 11
4883 // bits are all sign-bit copies, and use the rounded value computed
4885 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4886 SINT, DAG.getConstant(53, MVT::i32));
4887 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4888 Cond, DAG.getConstant(1, MVT::i64));
4889 Cond = DAG.getSetCC(dl, MVT::i32,
4890 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4892 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4895 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4896 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
4898 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4899 FP = DAG.getNode(ISD::FP_ROUND, dl,
4900 MVT::f32, FP, DAG.getIntPtrConstant(0));
4904 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
4905 "Unhandled INT_TO_FP type in custom expander!");
4906 // Since we only generate this in 64-bit mode, we can take advantage of
4907 // 64-bit registers. In particular, sign extend the input value into the
4908 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
4909 // then lfd it and fcfid it.
4910 MachineFunction &MF = DAG.getMachineFunction();
4911 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
4912 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4915 if (PPCSubTarget.hasLFIWAX() || PPCSubTarget.hasFPCVT()) {
4916 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
4917 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4919 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
4920 MachinePointerInfo::getFixedStack(FrameIdx),
4923 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
4924 "Expected an i32 store");
4925 MachineMemOperand *MMO =
4926 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
4927 MachineMemOperand::MOLoad, 4, 4);
4928 SDValue Ops[] = { Store, FIdx };
4929 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
4930 PPCISD::LFIWZX : PPCISD::LFIWAX,
4931 dl, DAG.getVTList(MVT::f64, MVT::Other),
4932 Ops, 2, MVT::i32, MMO);
4934 assert(PPCSubTarget.isPPC64() &&
4935 "i32->FP without LFIWAX supported only on PPC64");
4937 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
4938 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4940 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
4943 // STD the extended value into the stack slot.
4944 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
4945 MachinePointerInfo::getFixedStack(FrameIdx),
4948 // Load the value as a double.
4949 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
4950 MachinePointerInfo::getFixedStack(FrameIdx),
4951 false, false, false, 0);
4954 // FCFID it and return it.
4955 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
4956 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4957 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
4961 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4962 SelectionDAG &DAG) const {
4963 DebugLoc dl = Op.getDebugLoc();
4965 The rounding mode is in bits 30:31 of FPSR, and has the following
4972 FLT_ROUNDS, on the other hand, expects the following:
4979 To perform the conversion, we do:
4980 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
4983 MachineFunction &MF = DAG.getMachineFunction();
4984 EVT VT = Op.getValueType();
4985 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4986 SDValue MFFSreg, InFlag;
4988 // Save FP Control Word to register
4990 MVT::f64, // return register
4991 MVT::Glue // unused in this context
4993 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4995 // Save FP register to stack slot
4996 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
4997 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
4998 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
4999 StackSlot, MachinePointerInfo(), false, false,0);
5001 // Load FP Control Word from low 32 bits of stack slot.
5002 SDValue Four = DAG.getConstant(4, PtrVT);
5003 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5004 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5005 false, false, false, 0);
5007 // Transform as necessary
5009 DAG.getNode(ISD::AND, dl, MVT::i32,
5010 CWD, DAG.getConstant(3, MVT::i32));
5012 DAG.getNode(ISD::SRL, dl, MVT::i32,
5013 DAG.getNode(ISD::AND, dl, MVT::i32,
5014 DAG.getNode(ISD::XOR, dl, MVT::i32,
5015 CWD, DAG.getConstant(3, MVT::i32)),
5016 DAG.getConstant(3, MVT::i32)),
5017 DAG.getConstant(1, MVT::i32));
5020 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5022 return DAG.getNode((VT.getSizeInBits() < 16 ?
5023 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5026 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5027 EVT VT = Op.getValueType();
5028 unsigned BitWidth = VT.getSizeInBits();
5029 DebugLoc dl = Op.getDebugLoc();
5030 assert(Op.getNumOperands() == 3 &&
5031 VT == Op.getOperand(1).getValueType() &&
5034 // Expand into a bunch of logical ops. Note that these ops
5035 // depend on the PPC behavior for oversized shift amounts.
5036 SDValue Lo = Op.getOperand(0);
5037 SDValue Hi = Op.getOperand(1);
5038 SDValue Amt = Op.getOperand(2);
5039 EVT AmtVT = Amt.getValueType();
5041 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5042 DAG.getConstant(BitWidth, AmtVT), Amt);
5043 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5044 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5045 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5046 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5047 DAG.getConstant(-BitWidth, AmtVT));
5048 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5049 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5050 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5051 SDValue OutOps[] = { OutLo, OutHi };
5052 return DAG.getMergeValues(OutOps, 2, dl);
5055 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5056 EVT VT = Op.getValueType();
5057 DebugLoc dl = Op.getDebugLoc();
5058 unsigned BitWidth = VT.getSizeInBits();
5059 assert(Op.getNumOperands() == 3 &&
5060 VT == Op.getOperand(1).getValueType() &&
5063 // Expand into a bunch of logical ops. Note that these ops
5064 // depend on the PPC behavior for oversized shift amounts.
5065 SDValue Lo = Op.getOperand(0);
5066 SDValue Hi = Op.getOperand(1);
5067 SDValue Amt = Op.getOperand(2);
5068 EVT AmtVT = Amt.getValueType();
5070 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5071 DAG.getConstant(BitWidth, AmtVT), Amt);
5072 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5073 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5074 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5075 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5076 DAG.getConstant(-BitWidth, AmtVT));
5077 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5078 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5079 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5080 SDValue OutOps[] = { OutLo, OutHi };
5081 return DAG.getMergeValues(OutOps, 2, dl);
5084 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5085 DebugLoc dl = Op.getDebugLoc();
5086 EVT VT = Op.getValueType();
5087 unsigned BitWidth = VT.getSizeInBits();
5088 assert(Op.getNumOperands() == 3 &&
5089 VT == Op.getOperand(1).getValueType() &&
5092 // Expand into a bunch of logical ops, followed by a select_cc.
5093 SDValue Lo = Op.getOperand(0);
5094 SDValue Hi = Op.getOperand(1);
5095 SDValue Amt = Op.getOperand(2);
5096 EVT AmtVT = Amt.getValueType();
5098 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5099 DAG.getConstant(BitWidth, AmtVT), Amt);
5100 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5101 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5102 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5103 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5104 DAG.getConstant(-BitWidth, AmtVT));
5105 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5106 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5107 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5108 Tmp4, Tmp6, ISD::SETLE);
5109 SDValue OutOps[] = { OutLo, OutHi };
5110 return DAG.getMergeValues(OutOps, 2, dl);
5113 //===----------------------------------------------------------------------===//
5114 // Vector related lowering.
5117 /// BuildSplatI - Build a canonical splati of Val with an element size of
5118 /// SplatSize. Cast the result to VT.
5119 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5120 SelectionDAG &DAG, DebugLoc dl) {
5121 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5123 static const EVT VTys[] = { // canonical VT to use for each size.
5124 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5127 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5129 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5133 EVT CanonicalVT = VTys[SplatSize-1];
5135 // Build a canonical splat for this value.
5136 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5137 SmallVector<SDValue, 8> Ops;
5138 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5139 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
5140 &Ops[0], Ops.size());
5141 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5144 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5145 /// specified intrinsic ID.
5146 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5147 SelectionDAG &DAG, DebugLoc dl,
5148 EVT DestVT = MVT::Other) {
5149 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5150 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5151 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5154 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5155 /// specified intrinsic ID.
5156 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5157 SDValue Op2, SelectionDAG &DAG,
5158 DebugLoc dl, EVT DestVT = MVT::Other) {
5159 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5160 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5161 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5165 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5166 /// amount. The result has the specified value type.
5167 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5168 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
5169 // Force LHS/RHS to be the right type.
5170 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5171 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5174 for (unsigned i = 0; i != 16; ++i)
5176 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5177 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5180 // If this is a case we can't handle, return null and let the default
5181 // expansion code take care of it. If we CAN select this case, and if it
5182 // selects to a single instruction, return Op. Otherwise, if we can codegen
5183 // this case more efficiently than a constant pool load, lower it to the
5184 // sequence of ops that should be used.
5185 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5186 SelectionDAG &DAG) const {
5187 DebugLoc dl = Op.getDebugLoc();
5188 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5189 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5191 // Check if this is a splat of a constant value.
5192 APInt APSplatBits, APSplatUndef;
5193 unsigned SplatBitSize;
5195 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5196 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5199 unsigned SplatBits = APSplatBits.getZExtValue();
5200 unsigned SplatUndef = APSplatUndef.getZExtValue();
5201 unsigned SplatSize = SplatBitSize / 8;
5203 // First, handle single instruction cases.
5206 if (SplatBits == 0) {
5207 // Canonicalize all zero vectors to be v4i32.
5208 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5209 SDValue Z = DAG.getConstant(0, MVT::i32);
5210 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5211 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5216 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5217 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5219 if (SextVal >= -16 && SextVal <= 15)
5220 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5223 // Two instruction sequences.
5225 // If this value is in the range [-32,30] and is even, use:
5226 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5227 // If this value is in the range [17,31] and is odd, use:
5228 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5229 // If this value is in the range [-31,-17] and is odd, use:
5230 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5231 // Note the last two are three-instruction sequences.
5232 if (SextVal >= -32 && SextVal <= 31) {
5233 // To avoid having these optimizations undone by constant folding,
5234 // we convert to a pseudo that will be expanded later into one of
5236 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5237 EVT VT = Op.getValueType();
5238 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5239 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5240 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5243 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5244 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5246 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5247 // Make -1 and vspltisw -1:
5248 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5250 // Make the VSLW intrinsic, computing 0x8000_0000.
5251 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5254 // xor by OnesV to invert it.
5255 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5256 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5259 // Check to see if this is a wide variety of vsplti*, binop self cases.
5260 static const signed char SplatCsts[] = {
5261 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5262 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5265 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5266 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5267 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5268 int i = SplatCsts[idx];
5270 // Figure out what shift amount will be used by altivec if shifted by i in
5272 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5274 // vsplti + shl self.
5275 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5276 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5277 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5278 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5279 Intrinsic::ppc_altivec_vslw
5281 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5282 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5285 // vsplti + srl self.
5286 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5287 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5288 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5289 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5290 Intrinsic::ppc_altivec_vsrw
5292 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5293 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5296 // vsplti + sra self.
5297 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5298 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5299 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5300 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5301 Intrinsic::ppc_altivec_vsraw
5303 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5304 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5307 // vsplti + rol self.
5308 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5309 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5310 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5311 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5312 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5313 Intrinsic::ppc_altivec_vrlw
5315 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5316 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5319 // t = vsplti c, result = vsldoi t, t, 1
5320 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5321 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5322 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5324 // t = vsplti c, result = vsldoi t, t, 2
5325 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5326 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5327 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5329 // t = vsplti c, result = vsldoi t, t, 3
5330 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5331 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5332 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5339 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5340 /// the specified operations to build the shuffle.
5341 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5342 SDValue RHS, SelectionDAG &DAG,
5344 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5345 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5346 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5349 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5361 if (OpNum == OP_COPY) {
5362 if (LHSID == (1*9+2)*9+3) return LHS;
5363 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5367 SDValue OpLHS, OpRHS;
5368 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5369 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5373 default: llvm_unreachable("Unknown i32 permute!");
5375 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5376 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5377 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5378 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5381 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5382 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5383 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5384 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5387 for (unsigned i = 0; i != 16; ++i)
5388 ShufIdxs[i] = (i&3)+0;
5391 for (unsigned i = 0; i != 16; ++i)
5392 ShufIdxs[i] = (i&3)+4;
5395 for (unsigned i = 0; i != 16; ++i)
5396 ShufIdxs[i] = (i&3)+8;
5399 for (unsigned i = 0; i != 16; ++i)
5400 ShufIdxs[i] = (i&3)+12;
5403 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5405 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5407 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5409 EVT VT = OpLHS.getValueType();
5410 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5411 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5412 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5413 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5416 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5417 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5418 /// return the code it can be lowered into. Worst case, it can always be
5419 /// lowered into a vperm.
5420 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5421 SelectionDAG &DAG) const {
5422 DebugLoc dl = Op.getDebugLoc();
5423 SDValue V1 = Op.getOperand(0);
5424 SDValue V2 = Op.getOperand(1);
5425 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5426 EVT VT = Op.getValueType();
5428 // Cases that are handled by instructions that take permute immediates
5429 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5430 // selected by the instruction selector.
5431 if (V2.getOpcode() == ISD::UNDEF) {
5432 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5433 PPC::isSplatShuffleMask(SVOp, 2) ||
5434 PPC::isSplatShuffleMask(SVOp, 4) ||
5435 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5436 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5437 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5438 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5439 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5440 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5441 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5442 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5443 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5448 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5449 // and produce a fixed permutation. If any of these match, do not lower to
5451 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5452 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5453 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5454 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5455 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5456 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5457 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5458 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5459 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5462 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5463 // perfect shuffle table to emit an optimal matching sequence.
5464 ArrayRef<int> PermMask = SVOp->getMask();
5466 unsigned PFIndexes[4];
5467 bool isFourElementShuffle = true;
5468 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5469 unsigned EltNo = 8; // Start out undef.
5470 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5471 if (PermMask[i*4+j] < 0)
5472 continue; // Undef, ignore it.
5474 unsigned ByteSource = PermMask[i*4+j];
5475 if ((ByteSource & 3) != j) {
5476 isFourElementShuffle = false;
5481 EltNo = ByteSource/4;
5482 } else if (EltNo != ByteSource/4) {
5483 isFourElementShuffle = false;
5487 PFIndexes[i] = EltNo;
5490 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5491 // perfect shuffle vector to determine if it is cost effective to do this as
5492 // discrete instructions, or whether we should use a vperm.
5493 if (isFourElementShuffle) {
5494 // Compute the index in the perfect shuffle table.
5495 unsigned PFTableIndex =
5496 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5498 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5499 unsigned Cost = (PFEntry >> 30);
5501 // Determining when to avoid vperm is tricky. Many things affect the cost
5502 // of vperm, particularly how many times the perm mask needs to be computed.
5503 // For example, if the perm mask can be hoisted out of a loop or is already
5504 // used (perhaps because there are multiple permutes with the same shuffle
5505 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5506 // the loop requires an extra register.
5508 // As a compromise, we only emit discrete instructions if the shuffle can be
5509 // generated in 3 or fewer operations. When we have loop information
5510 // available, if this block is within a loop, we should avoid using vperm
5511 // for 3-operation perms and use a constant pool load instead.
5513 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5516 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5517 // vector that will get spilled to the constant pool.
5518 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5520 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5521 // that it is in input element units, not in bytes. Convert now.
5522 EVT EltVT = V1.getValueType().getVectorElementType();
5523 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5525 SmallVector<SDValue, 16> ResultMask;
5526 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5527 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5529 for (unsigned j = 0; j != BytesPerElement; ++j)
5530 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5534 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5535 &ResultMask[0], ResultMask.size());
5536 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5539 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5540 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5541 /// information about the intrinsic.
5542 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5544 unsigned IntrinsicID =
5545 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5548 switch (IntrinsicID) {
5549 default: return false;
5550 // Comparison predicates.
5551 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5552 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5553 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5554 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5555 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5556 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5557 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5558 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5559 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5560 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5561 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5562 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5563 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5565 // Normal Comparisons.
5566 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5567 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5568 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5569 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5570 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5571 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5572 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5573 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5574 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5575 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5576 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5577 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5578 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5583 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5584 /// lower, do it, otherwise return null.
5585 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5586 SelectionDAG &DAG) const {
5587 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5588 // opcode number of the comparison.
5589 DebugLoc dl = Op.getDebugLoc();
5592 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5593 return SDValue(); // Don't custom lower most intrinsics.
5595 // If this is a non-dot comparison, make the VCMP node and we are done.
5597 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5598 Op.getOperand(1), Op.getOperand(2),
5599 DAG.getConstant(CompareOpc, MVT::i32));
5600 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5603 // Create the PPCISD altivec 'dot' comparison node.
5605 Op.getOperand(2), // LHS
5606 Op.getOperand(3), // RHS
5607 DAG.getConstant(CompareOpc, MVT::i32)
5609 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5610 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5612 // Now that we have the comparison, emit a copy from the CR to a GPR.
5613 // This is flagged to the above dot comparison.
5614 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
5615 DAG.getRegister(PPC::CR6, MVT::i32),
5616 CompNode.getValue(1));
5618 // Unpack the result based on how the target uses it.
5619 unsigned BitNo; // Bit # of CR6.
5620 bool InvertBit; // Invert result?
5621 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5622 default: // Can't happen, don't crash on invalid number though.
5623 case 0: // Return the value of the EQ bit of CR6.
5624 BitNo = 0; InvertBit = false;
5626 case 1: // Return the inverted value of the EQ bit of CR6.
5627 BitNo = 0; InvertBit = true;
5629 case 2: // Return the value of the LT bit of CR6.
5630 BitNo = 2; InvertBit = false;
5632 case 3: // Return the inverted value of the LT bit of CR6.
5633 BitNo = 2; InvertBit = true;
5637 // Shift the bit into the low position.
5638 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5639 DAG.getConstant(8-(3-BitNo), MVT::i32));
5641 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5642 DAG.getConstant(1, MVT::i32));
5644 // If we are supposed to, toggle the bit.
5646 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5647 DAG.getConstant(1, MVT::i32));
5651 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5652 SelectionDAG &DAG) const {
5653 DebugLoc dl = Op.getDebugLoc();
5654 // Create a stack slot that is 16-byte aligned.
5655 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5656 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5657 EVT PtrVT = getPointerTy();
5658 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5660 // Store the input value into Value#0 of the stack slot.
5661 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5662 Op.getOperand(0), FIdx, MachinePointerInfo(),
5665 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5666 false, false, false, 0);
5669 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5670 DebugLoc dl = Op.getDebugLoc();
5671 if (Op.getValueType() == MVT::v4i32) {
5672 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5674 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5675 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5677 SDValue RHSSwap = // = vrlw RHS, 16
5678 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
5680 // Shrinkify inputs to v8i16.
5681 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5682 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5683 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5685 // Low parts multiplied together, generating 32-bit results (we ignore the
5687 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
5688 LHS, RHS, DAG, dl, MVT::v4i32);
5690 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
5691 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5692 // Shift the high parts up 16 bits.
5693 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
5695 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5696 } else if (Op.getValueType() == MVT::v8i16) {
5697 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5699 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5701 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
5702 LHS, RHS, Zero, DAG, dl);
5703 } else if (Op.getValueType() == MVT::v16i8) {
5704 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5706 // Multiply the even 8-bit parts, producing 16-bit sums.
5707 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
5708 LHS, RHS, DAG, dl, MVT::v8i16);
5709 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5711 // Multiply the odd 8-bit parts, producing 16-bit sums.
5712 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
5713 LHS, RHS, DAG, dl, MVT::v8i16);
5714 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5716 // Merge the results together.
5718 for (unsigned i = 0; i != 8; ++i) {
5720 Ops[i*2+1] = 2*i+1+16;
5722 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5724 llvm_unreachable("Unknown mul to lower!");
5728 /// LowerOperation - Provide custom lowering hooks for some operations.
5730 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5731 switch (Op.getOpcode()) {
5732 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
5733 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5734 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5735 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5736 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5737 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5738 case ISD::SETCC: return LowerSETCC(Op, DAG);
5739 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
5740 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
5742 return LowerVASTART(Op, DAG, PPCSubTarget);
5745 return LowerVAARG(Op, DAG, PPCSubTarget);
5747 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
5748 case ISD::DYNAMIC_STACKALLOC:
5749 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
5751 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
5752 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
5754 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5755 case ISD::FP_TO_UINT:
5756 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
5758 case ISD::UINT_TO_FP:
5759 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
5760 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5762 // Lower 64-bit shifts.
5763 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
5764 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
5765 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
5767 // Vector-related lowering.
5768 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5769 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5770 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5771 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5772 case ISD::MUL: return LowerMUL(Op, DAG);
5774 // Frame & Return address.
5775 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5776 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5780 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
5781 SmallVectorImpl<SDValue>&Results,
5782 SelectionDAG &DAG) const {
5783 const TargetMachine &TM = getTargetMachine();
5784 DebugLoc dl = N->getDebugLoc();
5785 switch (N->getOpcode()) {
5787 llvm_unreachable("Do not know how to custom type legalize this operation!");
5789 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
5790 || TM.getSubtarget<PPCSubtarget>().isPPC64())
5793 EVT VT = N->getValueType(0);
5795 if (VT == MVT::i64) {
5796 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
5798 Results.push_back(NewNode);
5799 Results.push_back(NewNode.getValue(1));
5803 case ISD::FP_ROUND_INREG: {
5804 assert(N->getValueType(0) == MVT::ppcf128);
5805 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5806 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5807 MVT::f64, N->getOperand(0),
5808 DAG.getIntPtrConstant(0));
5809 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5810 MVT::f64, N->getOperand(0),
5811 DAG.getIntPtrConstant(1));
5813 // Add the two halves of the long double in round-to-zero mode.
5814 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
5816 // We know the low half is about to be thrown away, so just use something
5818 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5822 case ISD::FP_TO_SINT:
5823 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
5829 //===----------------------------------------------------------------------===//
5830 // Other Lowering Code
5831 //===----------------------------------------------------------------------===//
5834 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5835 bool is64bit, unsigned BinOpcode) const {
5836 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5837 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5839 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5840 MachineFunction *F = BB->getParent();
5841 MachineFunction::iterator It = BB;
5844 unsigned dest = MI->getOperand(0).getReg();
5845 unsigned ptrA = MI->getOperand(1).getReg();
5846 unsigned ptrB = MI->getOperand(2).getReg();
5847 unsigned incr = MI->getOperand(3).getReg();
5848 DebugLoc dl = MI->getDebugLoc();
5850 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5851 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5852 F->insert(It, loopMBB);
5853 F->insert(It, exitMBB);
5854 exitMBB->splice(exitMBB->begin(), BB,
5855 llvm::next(MachineBasicBlock::iterator(MI)),
5857 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5859 MachineRegisterInfo &RegInfo = F->getRegInfo();
5860 unsigned TmpReg = (!BinOpcode) ? incr :
5861 RegInfo.createVirtualRegister(
5862 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5863 (const TargetRegisterClass *) &PPC::GPRCRegClass);
5867 // fallthrough --> loopMBB
5868 BB->addSuccessor(loopMBB);
5871 // l[wd]arx dest, ptr
5872 // add r0, dest, incr
5873 // st[wd]cx. r0, ptr
5875 // fallthrough --> exitMBB
5877 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5878 .addReg(ptrA).addReg(ptrB);
5880 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
5881 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5882 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
5883 BuildMI(BB, dl, TII->get(PPC::BCC))
5884 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5885 BB->addSuccessor(loopMBB);
5886 BB->addSuccessor(exitMBB);
5895 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
5896 MachineBasicBlock *BB,
5897 bool is8bit, // operation
5898 unsigned BinOpcode) const {
5899 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5900 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5901 // In 64 bit mode we have to use 64 bits for addresses, even though the
5902 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
5903 // registers without caring whether they're 32 or 64, but here we're
5904 // doing actual arithmetic on the addresses.
5905 bool is64bit = PPCSubTarget.isPPC64();
5906 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
5908 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5909 MachineFunction *F = BB->getParent();
5910 MachineFunction::iterator It = BB;
5913 unsigned dest = MI->getOperand(0).getReg();
5914 unsigned ptrA = MI->getOperand(1).getReg();
5915 unsigned ptrB = MI->getOperand(2).getReg();
5916 unsigned incr = MI->getOperand(3).getReg();
5917 DebugLoc dl = MI->getDebugLoc();
5919 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5920 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5921 F->insert(It, loopMBB);
5922 F->insert(It, exitMBB);
5923 exitMBB->splice(exitMBB->begin(), BB,
5924 llvm::next(MachineBasicBlock::iterator(MI)),
5926 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5928 MachineRegisterInfo &RegInfo = F->getRegInfo();
5929 const TargetRegisterClass *RC =
5930 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5931 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5932 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5933 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5934 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5935 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
5936 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
5937 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
5938 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
5939 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
5940 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
5941 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
5942 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
5944 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
5948 // fallthrough --> loopMBB
5949 BB->addSuccessor(loopMBB);
5951 // The 4-byte load must be aligned, while a char or short may be
5952 // anywhere in the word. Hence all this nasty bookkeeping code.
5953 // add ptr1, ptrA, ptrB [copy if ptrA==0]
5954 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
5955 // xori shift, shift1, 24 [16]
5956 // rlwinm ptr, ptr1, 0, 0, 29
5957 // slw incr2, incr, shift
5958 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
5959 // slw mask, mask2, shift
5961 // lwarx tmpDest, ptr
5962 // add tmp, tmpDest, incr2
5963 // andc tmp2, tmpDest, mask
5964 // and tmp3, tmp, mask
5965 // or tmp4, tmp3, tmp2
5968 // fallthrough --> exitMBB
5969 // srw dest, tmpDest, shift
5970 if (ptrA != ZeroReg) {
5971 Ptr1Reg = RegInfo.createVirtualRegister(RC);
5972 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
5973 .addReg(ptrA).addReg(ptrB);
5977 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5978 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
5979 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5980 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
5982 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
5983 .addReg(Ptr1Reg).addImm(0).addImm(61);
5985 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
5986 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
5987 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
5988 .addReg(incr).addReg(ShiftReg);
5990 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
5992 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
5993 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
5995 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
5996 .addReg(Mask2Reg).addReg(ShiftReg);
5999 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6000 .addReg(ZeroReg).addReg(PtrReg);
6002 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6003 .addReg(Incr2Reg).addReg(TmpDestReg);
6004 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6005 .addReg(TmpDestReg).addReg(MaskReg);
6006 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6007 .addReg(TmpReg).addReg(MaskReg);
6008 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6009 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6010 BuildMI(BB, dl, TII->get(PPC::STWCX))
6011 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6012 BuildMI(BB, dl, TII->get(PPC::BCC))
6013 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6014 BB->addSuccessor(loopMBB);
6015 BB->addSuccessor(exitMBB);
6020 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6025 llvm::MachineBasicBlock*
6026 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6027 MachineBasicBlock *MBB) const {
6028 DebugLoc DL = MI->getDebugLoc();
6029 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6031 MachineFunction *MF = MBB->getParent();
6032 MachineRegisterInfo &MRI = MF->getRegInfo();
6034 const BasicBlock *BB = MBB->getBasicBlock();
6035 MachineFunction::iterator I = MBB;
6039 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6040 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6042 unsigned DstReg = MI->getOperand(0).getReg();
6043 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6044 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6045 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6046 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6048 MVT PVT = getPointerTy();
6049 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6050 "Invalid Pointer Size!");
6051 // For v = setjmp(buf), we generate
6054 // SjLjSetup mainMBB
6060 // buf[LabelOffset] = LR
6064 // v = phi(main, restore)
6067 MachineBasicBlock *thisMBB = MBB;
6068 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6069 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6070 MF->insert(I, mainMBB);
6071 MF->insert(I, sinkMBB);
6073 MachineInstrBuilder MIB;
6075 // Transfer the remainder of BB and its successor edges to sinkMBB.
6076 sinkMBB->splice(sinkMBB->begin(), MBB,
6077 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
6078 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6080 // Note that the structure of the jmp_buf used here is not compatible
6081 // with that used by libc, and is not designed to be. Specifically, it
6082 // stores only those 'reserved' registers that LLVM does not otherwise
6083 // understand how to spill. Also, by convention, by the time this
6084 // intrinsic is called, Clang has already stored the frame address in the
6085 // first slot of the buffer and stack address in the third. Following the
6086 // X86 target code, we'll store the jump address in the second slot. We also
6087 // need to save the TOC pointer (R2) to handle jumps between shared
6088 // libraries, and that will be stored in the fourth slot. The thread
6089 // identifier (R13) is not affected.
6092 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6093 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6095 // Prepare IP either in reg.
6096 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6097 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6098 unsigned BufReg = MI->getOperand(1).getReg();
6100 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) {
6101 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6103 .addImm(TOCOffset / 4)
6106 MIB.setMemRefs(MMOBegin, MMOEnd);
6110 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6111 MIB.addRegMask(PPCRegInfo->getNoPreservedMask());
6113 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6115 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6117 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6119 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6120 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6124 MIB = BuildMI(mainMBB, DL,
6125 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6128 if (PPCSubTarget.isPPC64()) {
6129 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6131 .addImm(LabelOffset / 4)
6134 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6136 .addImm(LabelOffset)
6140 MIB.setMemRefs(MMOBegin, MMOEnd);
6142 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6143 mainMBB->addSuccessor(sinkMBB);
6146 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6147 TII->get(PPC::PHI), DstReg)
6148 .addReg(mainDstReg).addMBB(mainMBB)
6149 .addReg(restoreDstReg).addMBB(thisMBB);
6151 MI->eraseFromParent();
6156 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6157 MachineBasicBlock *MBB) const {
6158 DebugLoc DL = MI->getDebugLoc();
6159 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6161 MachineFunction *MF = MBB->getParent();
6162 MachineRegisterInfo &MRI = MF->getRegInfo();
6165 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6166 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6168 MVT PVT = getPointerTy();
6169 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6170 "Invalid Pointer Size!");
6172 const TargetRegisterClass *RC =
6173 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6174 unsigned Tmp = MRI.createVirtualRegister(RC);
6175 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6176 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6177 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6179 MachineInstrBuilder MIB;
6181 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6182 const int64_t SPOffset = 2 * PVT.getStoreSize();
6183 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6185 unsigned BufReg = MI->getOperand(0).getReg();
6187 // Reload FP (the jumped-to function may not have had a
6188 // frame pointer, and if so, then its r31 will be restored
6190 if (PVT == MVT::i64) {
6191 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6195 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6199 MIB.setMemRefs(MMOBegin, MMOEnd);
6202 if (PVT == MVT::i64) {
6203 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6204 .addImm(LabelOffset / 4)
6207 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6208 .addImm(LabelOffset)
6211 MIB.setMemRefs(MMOBegin, MMOEnd);
6214 if (PVT == MVT::i64) {
6215 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6216 .addImm(SPOffset / 4)
6219 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6223 MIB.setMemRefs(MMOBegin, MMOEnd);
6225 // FIXME: When we also support base pointers, that register must also be
6229 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6230 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6231 .addImm(TOCOffset / 4)
6234 MIB.setMemRefs(MMOBegin, MMOEnd);
6238 BuildMI(*MBB, MI, DL,
6239 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6240 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6242 MI->eraseFromParent();
6247 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6248 MachineBasicBlock *BB) const {
6249 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6250 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6251 return emitEHSjLjSetJmp(MI, BB);
6252 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6253 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6254 return emitEHSjLjLongJmp(MI, BB);
6257 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6259 // To "insert" these instructions we actually have to insert their
6260 // control-flow patterns.
6261 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6262 MachineFunction::iterator It = BB;
6265 MachineFunction *F = BB->getParent();
6267 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6268 MI->getOpcode() == PPC::SELECT_CC_I8)) {
6269 SmallVector<MachineOperand, 2> Cond;
6270 Cond.push_back(MI->getOperand(4));
6271 Cond.push_back(MI->getOperand(1));
6273 DebugLoc dl = MI->getDebugLoc();
6274 PPCII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(), Cond,
6275 MI->getOperand(2).getReg(), MI->getOperand(3).getReg());
6276 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6277 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6278 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6279 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6280 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
6283 // The incoming instruction knows the destination vreg to set, the
6284 // condition code register to branch on, the true/false values to
6285 // select between, and a branch opcode to use.
6290 // cmpTY ccX, r1, r2
6292 // fallthrough --> copy0MBB
6293 MachineBasicBlock *thisMBB = BB;
6294 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6295 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6296 unsigned SelectPred = MI->getOperand(4).getImm();
6297 DebugLoc dl = MI->getDebugLoc();
6298 F->insert(It, copy0MBB);
6299 F->insert(It, sinkMBB);
6301 // Transfer the remainder of BB and its successor edges to sinkMBB.
6302 sinkMBB->splice(sinkMBB->begin(), BB,
6303 llvm::next(MachineBasicBlock::iterator(MI)),
6305 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6307 // Next, add the true and fallthrough blocks as its successors.
6308 BB->addSuccessor(copy0MBB);
6309 BB->addSuccessor(sinkMBB);
6311 BuildMI(BB, dl, TII->get(PPC::BCC))
6312 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6315 // %FalseValue = ...
6316 // # fallthrough to sinkMBB
6319 // Update machine-CFG edges
6320 BB->addSuccessor(sinkMBB);
6323 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6326 BuildMI(*BB, BB->begin(), dl,
6327 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6328 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6329 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6331 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6332 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6333 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6334 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6335 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6336 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6337 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6338 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6340 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6341 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6342 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6343 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6344 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6345 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6346 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6347 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6349 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6350 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6351 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6352 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6353 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6354 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6355 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6356 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6358 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6359 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6360 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6361 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6362 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6363 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6364 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6365 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6367 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6368 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6369 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6370 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6371 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6372 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6373 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6374 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6376 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6377 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6378 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6379 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6380 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6381 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6382 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6383 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6385 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6386 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6387 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6388 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6389 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6390 BB = EmitAtomicBinary(MI, BB, false, 0);
6391 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6392 BB = EmitAtomicBinary(MI, BB, true, 0);
6394 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6395 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6396 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6398 unsigned dest = MI->getOperand(0).getReg();
6399 unsigned ptrA = MI->getOperand(1).getReg();
6400 unsigned ptrB = MI->getOperand(2).getReg();
6401 unsigned oldval = MI->getOperand(3).getReg();
6402 unsigned newval = MI->getOperand(4).getReg();
6403 DebugLoc dl = MI->getDebugLoc();
6405 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6406 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6407 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6408 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6409 F->insert(It, loop1MBB);
6410 F->insert(It, loop2MBB);
6411 F->insert(It, midMBB);
6412 F->insert(It, exitMBB);
6413 exitMBB->splice(exitMBB->begin(), BB,
6414 llvm::next(MachineBasicBlock::iterator(MI)),
6416 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6420 // fallthrough --> loopMBB
6421 BB->addSuccessor(loop1MBB);
6424 // l[wd]arx dest, ptr
6425 // cmp[wd] dest, oldval
6428 // st[wd]cx. newval, ptr
6432 // st[wd]cx. dest, ptr
6435 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6436 .addReg(ptrA).addReg(ptrB);
6437 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6438 .addReg(oldval).addReg(dest);
6439 BuildMI(BB, dl, TII->get(PPC::BCC))
6440 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6441 BB->addSuccessor(loop2MBB);
6442 BB->addSuccessor(midMBB);
6445 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6446 .addReg(newval).addReg(ptrA).addReg(ptrB);
6447 BuildMI(BB, dl, TII->get(PPC::BCC))
6448 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6449 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6450 BB->addSuccessor(loop1MBB);
6451 BB->addSuccessor(exitMBB);
6454 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6455 .addReg(dest).addReg(ptrA).addReg(ptrB);
6456 BB->addSuccessor(exitMBB);
6461 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6462 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6463 // We must use 64-bit registers for addresses when targeting 64-bit,
6464 // since we're actually doing arithmetic on them. Other registers
6466 bool is64bit = PPCSubTarget.isPPC64();
6467 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6469 unsigned dest = MI->getOperand(0).getReg();
6470 unsigned ptrA = MI->getOperand(1).getReg();
6471 unsigned ptrB = MI->getOperand(2).getReg();
6472 unsigned oldval = MI->getOperand(3).getReg();
6473 unsigned newval = MI->getOperand(4).getReg();
6474 DebugLoc dl = MI->getDebugLoc();
6476 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6477 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6478 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6479 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6480 F->insert(It, loop1MBB);
6481 F->insert(It, loop2MBB);
6482 F->insert(It, midMBB);
6483 F->insert(It, exitMBB);
6484 exitMBB->splice(exitMBB->begin(), BB,
6485 llvm::next(MachineBasicBlock::iterator(MI)),
6487 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6489 MachineRegisterInfo &RegInfo = F->getRegInfo();
6490 const TargetRegisterClass *RC =
6491 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6492 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6493 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6494 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6495 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6496 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6497 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6498 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6499 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6500 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6501 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6502 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6503 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6504 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6505 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6507 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6508 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6511 // fallthrough --> loopMBB
6512 BB->addSuccessor(loop1MBB);
6514 // The 4-byte load must be aligned, while a char or short may be
6515 // anywhere in the word. Hence all this nasty bookkeeping code.
6516 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6517 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6518 // xori shift, shift1, 24 [16]
6519 // rlwinm ptr, ptr1, 0, 0, 29
6520 // slw newval2, newval, shift
6521 // slw oldval2, oldval,shift
6522 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6523 // slw mask, mask2, shift
6524 // and newval3, newval2, mask
6525 // and oldval3, oldval2, mask
6527 // lwarx tmpDest, ptr
6528 // and tmp, tmpDest, mask
6529 // cmpw tmp, oldval3
6532 // andc tmp2, tmpDest, mask
6533 // or tmp4, tmp2, newval3
6538 // stwcx. tmpDest, ptr
6540 // srw dest, tmpDest, shift
6541 if (ptrA != ZeroReg) {
6542 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6543 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6544 .addReg(ptrA).addReg(ptrB);
6548 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6549 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6550 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6551 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6553 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6554 .addReg(Ptr1Reg).addImm(0).addImm(61);
6556 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6557 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6558 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6559 .addReg(newval).addReg(ShiftReg);
6560 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6561 .addReg(oldval).addReg(ShiftReg);
6563 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6565 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6566 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6567 .addReg(Mask3Reg).addImm(65535);
6569 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6570 .addReg(Mask2Reg).addReg(ShiftReg);
6571 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6572 .addReg(NewVal2Reg).addReg(MaskReg);
6573 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6574 .addReg(OldVal2Reg).addReg(MaskReg);
6577 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6578 .addReg(ZeroReg).addReg(PtrReg);
6579 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6580 .addReg(TmpDestReg).addReg(MaskReg);
6581 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6582 .addReg(TmpReg).addReg(OldVal3Reg);
6583 BuildMI(BB, dl, TII->get(PPC::BCC))
6584 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6585 BB->addSuccessor(loop2MBB);
6586 BB->addSuccessor(midMBB);
6589 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6590 .addReg(TmpDestReg).addReg(MaskReg);
6591 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6592 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6593 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6594 .addReg(ZeroReg).addReg(PtrReg);
6595 BuildMI(BB, dl, TII->get(PPC::BCC))
6596 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6597 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6598 BB->addSuccessor(loop1MBB);
6599 BB->addSuccessor(exitMBB);
6602 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
6603 .addReg(ZeroReg).addReg(PtrReg);
6604 BB->addSuccessor(exitMBB);
6609 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
6611 } else if (MI->getOpcode() == PPC::FADDrtz) {
6612 // This pseudo performs an FADD with rounding mode temporarily forced
6613 // to round-to-zero. We emit this via custom inserter since the FPSCR
6614 // is not modeled at the SelectionDAG level.
6615 unsigned Dest = MI->getOperand(0).getReg();
6616 unsigned Src1 = MI->getOperand(1).getReg();
6617 unsigned Src2 = MI->getOperand(2).getReg();
6618 DebugLoc dl = MI->getDebugLoc();
6620 MachineRegisterInfo &RegInfo = F->getRegInfo();
6621 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
6623 // Save FPSCR value.
6624 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
6626 // Set rounding mode to round-to-zero.
6627 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
6628 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
6630 // Perform addition.
6631 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
6633 // Restore FPSCR value.
6634 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
6635 } else if (MI->getOpcode() == PPC::FRINDrint ||
6636 MI->getOpcode() == PPC::FRINSrint) {
6637 bool isf32 = MI->getOpcode() == PPC::FRINSrint;
6638 unsigned Dest = MI->getOperand(0).getReg();
6639 unsigned Src = MI->getOperand(1).getReg();
6640 DebugLoc dl = MI->getDebugLoc();
6642 MachineRegisterInfo &RegInfo = F->getRegInfo();
6643 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
6645 // Perform the rounding.
6646 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FRINS : PPC::FRIND), Dest)
6649 // Compare the results.
6650 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FCMPUS : PPC::FCMPUD), CRReg)
6651 .addReg(Dest).addReg(Src);
6653 // If the results were not equal, then set the FPSCR XX bit.
6654 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6655 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6656 F->insert(It, midMBB);
6657 F->insert(It, exitMBB);
6658 exitMBB->splice(exitMBB->begin(), BB,
6659 llvm::next(MachineBasicBlock::iterator(MI)),
6661 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6663 BuildMI(*BB, MI, dl, TII->get(PPC::BCC))
6664 .addImm(PPC::PRED_EQ).addReg(CRReg).addMBB(exitMBB);
6666 BB->addSuccessor(midMBB);
6667 BB->addSuccessor(exitMBB);
6671 // Set the FPSCR XX bit (FE_INEXACT). Note that we cannot just set
6672 // the FI bit here because that will not automatically set XX also,
6673 // and XX is what libm interprets as the FE_INEXACT flag.
6674 BuildMI(BB, dl, TII->get(PPC::MTFSB1)).addImm(/* 38 - 32 = */ 6);
6675 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6677 BB->addSuccessor(exitMBB);
6681 llvm_unreachable("Unexpected instr type to insert");
6684 MI->eraseFromParent(); // The pseudo instruction is gone now.
6688 //===----------------------------------------------------------------------===//
6689 // Target Optimization Hooks
6690 //===----------------------------------------------------------------------===//
6692 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
6693 DAGCombinerInfo &DCI) const {
6694 if (DCI.isAfterLegalizeVectorOps())
6697 EVT VT = Op.getValueType();
6699 if ((VT == MVT::f32 && PPCSubTarget.hasFRES()) ||
6700 (VT == MVT::f64 && PPCSubTarget.hasFRE()) ||
6701 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6703 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6704 // For the reciprocal, we need to find the zero of the function:
6705 // F(X) = A X - 1 [which has a zero at X = 1/A]
6707 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
6708 // does not require additional intermediate precision]
6710 // Convergence is quadratic, so we essentially double the number of digits
6711 // correct after every iteration. The minimum architected relative
6712 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6713 // 23 digits and double has 52 digits.
6714 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6715 if (VT.getScalarType() == MVT::f64)
6718 SelectionDAG &DAG = DCI.DAG;
6719 DebugLoc dl = Op.getDebugLoc();
6722 DAG.getConstantFP(1.0, VT.getScalarType());
6723 if (VT.isVector()) {
6724 assert(VT.getVectorNumElements() == 4 &&
6725 "Unknown vector type");
6726 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6727 FPOne, FPOne, FPOne, FPOne);
6730 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
6731 DCI.AddToWorklist(Est.getNode());
6733 // Newton iterations: Est = Est + Est (1 - Arg * Est)
6734 for (int i = 0; i < Iterations; ++i) {
6735 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
6736 DCI.AddToWorklist(NewEst.getNode());
6738 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
6739 DCI.AddToWorklist(NewEst.getNode());
6741 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6742 DCI.AddToWorklist(NewEst.getNode());
6744 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
6745 DCI.AddToWorklist(Est.getNode());
6754 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
6755 DAGCombinerInfo &DCI) const {
6756 if (DCI.isAfterLegalizeVectorOps())
6759 EVT VT = Op.getValueType();
6761 if ((VT == MVT::f32 && PPCSubTarget.hasFRSQRTES()) ||
6762 (VT == MVT::f64 && PPCSubTarget.hasFRSQRTE()) ||
6763 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6765 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6766 // For the reciprocal sqrt, we need to find the zero of the function:
6767 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
6769 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
6770 // As a result, we precompute A/2 prior to the iteration loop.
6772 // Convergence is quadratic, so we essentially double the number of digits
6773 // correct after every iteration. The minimum architected relative
6774 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6775 // 23 digits and double has 52 digits.
6776 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6777 if (VT.getScalarType() == MVT::f64)
6780 SelectionDAG &DAG = DCI.DAG;
6781 DebugLoc dl = Op.getDebugLoc();
6783 SDValue FPThreeHalves =
6784 DAG.getConstantFP(1.5, VT.getScalarType());
6785 if (VT.isVector()) {
6786 assert(VT.getVectorNumElements() == 4 &&
6787 "Unknown vector type");
6788 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6789 FPThreeHalves, FPThreeHalves,
6790 FPThreeHalves, FPThreeHalves);
6793 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
6794 DCI.AddToWorklist(Est.getNode());
6796 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
6797 // this entire sequence requires only one FP constant.
6798 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
6799 DCI.AddToWorklist(HalfArg.getNode());
6801 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
6802 DCI.AddToWorklist(HalfArg.getNode());
6804 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
6805 for (int i = 0; i < Iterations; ++i) {
6806 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
6807 DCI.AddToWorklist(NewEst.getNode());
6809 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
6810 DCI.AddToWorklist(NewEst.getNode());
6812 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
6813 DCI.AddToWorklist(NewEst.getNode());
6815 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6816 DCI.AddToWorklist(Est.getNode());
6825 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
6826 DAGCombinerInfo &DCI) const {
6827 const TargetMachine &TM = getTargetMachine();
6828 SelectionDAG &DAG = DCI.DAG;
6829 DebugLoc dl = N->getDebugLoc();
6830 switch (N->getOpcode()) {
6833 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6834 if (C->isNullValue()) // 0 << V -> 0.
6835 return N->getOperand(0);
6839 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6840 if (C->isNullValue()) // 0 >>u V -> 0.
6841 return N->getOperand(0);
6845 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6846 if (C->isNullValue() || // 0 >>s V -> 0.
6847 C->isAllOnesValue()) // -1 >>s V -> -1.
6848 return N->getOperand(0);
6852 assert(TM.Options.UnsafeFPMath &&
6853 "Reciprocal estimates require UnsafeFPMath");
6855 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
6857 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
6858 if (RV.getNode() != 0) {
6859 DCI.AddToWorklist(RV.getNode());
6860 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6861 N->getOperand(0), RV);
6863 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
6864 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
6866 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
6868 if (RV.getNode() != 0) {
6869 DCI.AddToWorklist(RV.getNode());
6870 RV = DAG.getNode(ISD::FP_EXTEND, N->getOperand(1).getDebugLoc(),
6871 N->getValueType(0), RV);
6872 DCI.AddToWorklist(RV.getNode());
6873 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6874 N->getOperand(0), RV);
6876 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
6877 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
6879 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
6881 if (RV.getNode() != 0) {
6882 DCI.AddToWorklist(RV.getNode());
6883 RV = DAG.getNode(ISD::FP_ROUND, N->getOperand(1).getDebugLoc(),
6884 N->getValueType(0), RV,
6885 N->getOperand(1).getOperand(1));
6886 DCI.AddToWorklist(RV.getNode());
6887 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6888 N->getOperand(0), RV);
6892 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
6893 if (RV.getNode() != 0) {
6894 DCI.AddToWorklist(RV.getNode());
6895 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6896 N->getOperand(0), RV);
6902 assert(TM.Options.UnsafeFPMath &&
6903 "Reciprocal estimates require UnsafeFPMath");
6905 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
6907 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
6908 if (RV.getNode() != 0) {
6909 DCI.AddToWorklist(RV.getNode());
6910 RV = DAGCombineFastRecip(RV, DCI);
6911 if (RV.getNode() != 0)
6917 case ISD::SINT_TO_FP:
6918 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
6919 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
6920 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
6921 // We allow the src/dst to be either f32/f64, but the intermediate
6922 // type must be i64.
6923 if (N->getOperand(0).getValueType() == MVT::i64 &&
6924 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
6925 SDValue Val = N->getOperand(0).getOperand(0);
6926 if (Val.getValueType() == MVT::f32) {
6927 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
6928 DCI.AddToWorklist(Val.getNode());
6931 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
6932 DCI.AddToWorklist(Val.getNode());
6933 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
6934 DCI.AddToWorklist(Val.getNode());
6935 if (N->getValueType(0) == MVT::f32) {
6936 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
6937 DAG.getIntPtrConstant(0));
6938 DCI.AddToWorklist(Val.getNode());
6941 } else if (N->getOperand(0).getValueType() == MVT::i32) {
6942 // If the intermediate type is i32, we can avoid the load/store here
6949 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
6950 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
6951 !cast<StoreSDNode>(N)->isTruncatingStore() &&
6952 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
6953 N->getOperand(1).getValueType() == MVT::i32 &&
6954 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
6955 SDValue Val = N->getOperand(1).getOperand(0);
6956 if (Val.getValueType() == MVT::f32) {
6957 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
6958 DCI.AddToWorklist(Val.getNode());
6960 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
6961 DCI.AddToWorklist(Val.getNode());
6964 N->getOperand(0), Val, N->getOperand(2),
6965 DAG.getValueType(N->getOperand(1).getValueType())
6968 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
6969 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
6970 cast<StoreSDNode>(N)->getMemoryVT(),
6971 cast<StoreSDNode>(N)->getMemOperand());
6972 DCI.AddToWorklist(Val.getNode());
6976 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
6977 if (cast<StoreSDNode>(N)->isUnindexed() &&
6978 N->getOperand(1).getOpcode() == ISD::BSWAP &&
6979 N->getOperand(1).getNode()->hasOneUse() &&
6980 (N->getOperand(1).getValueType() == MVT::i32 ||
6981 N->getOperand(1).getValueType() == MVT::i16 ||
6982 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
6983 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
6984 N->getOperand(1).getValueType() == MVT::i64))) {
6985 SDValue BSwapOp = N->getOperand(1).getOperand(0);
6986 // Do an any-extend to 32-bits if this is a half-word input.
6987 if (BSwapOp.getValueType() == MVT::i16)
6988 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
6991 N->getOperand(0), BSwapOp, N->getOperand(2),
6992 DAG.getValueType(N->getOperand(1).getValueType())
6995 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
6996 Ops, array_lengthof(Ops),
6997 cast<StoreSDNode>(N)->getMemoryVT(),
6998 cast<StoreSDNode>(N)->getMemOperand());
7002 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
7003 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
7004 N->getOperand(0).hasOneUse() &&
7005 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
7006 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7007 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7008 N->getValueType(0) == MVT::i64))) {
7009 SDValue Load = N->getOperand(0);
7010 LoadSDNode *LD = cast<LoadSDNode>(Load);
7011 // Create the byte-swapping load.
7013 LD->getChain(), // Chain
7014 LD->getBasePtr(), // Ptr
7015 DAG.getValueType(N->getValueType(0)) // VT
7018 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
7019 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
7020 MVT::i64 : MVT::i32, MVT::Other),
7021 Ops, 3, LD->getMemoryVT(), LD->getMemOperand());
7023 // If this is an i16 load, insert the truncate.
7024 SDValue ResVal = BSLoad;
7025 if (N->getValueType(0) == MVT::i16)
7026 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
7028 // First, combine the bswap away. This makes the value produced by the
7030 DCI.CombineTo(N, ResVal);
7032 // Next, combine the load away, we give it a bogus result value but a real
7033 // chain result. The result value is dead because the bswap is dead.
7034 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
7036 // Return N so it doesn't get rechecked!
7037 return SDValue(N, 0);
7041 case PPCISD::VCMP: {
7042 // If a VCMPo node already exists with exactly the same operands as this
7043 // node, use its result instead of this node (VCMPo computes both a CR6 and
7044 // a normal output).
7046 if (!N->getOperand(0).hasOneUse() &&
7047 !N->getOperand(1).hasOneUse() &&
7048 !N->getOperand(2).hasOneUse()) {
7050 // Scan all of the users of the LHS, looking for VCMPo's that match.
7051 SDNode *VCMPoNode = 0;
7053 SDNode *LHSN = N->getOperand(0).getNode();
7054 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
7056 if (UI->getOpcode() == PPCISD::VCMPo &&
7057 UI->getOperand(1) == N->getOperand(1) &&
7058 UI->getOperand(2) == N->getOperand(2) &&
7059 UI->getOperand(0) == N->getOperand(0)) {
7064 // If there is no VCMPo node, or if the flag value has a single use, don't
7066 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
7069 // Look at the (necessarily single) use of the flag value. If it has a
7070 // chain, this transformation is more complex. Note that multiple things
7071 // could use the value result, which we should ignore.
7072 SDNode *FlagUser = 0;
7073 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
7074 FlagUser == 0; ++UI) {
7075 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
7077 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
7078 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
7085 // If the user is a MFCR instruction, we know this is safe. Otherwise we
7086 // give up for right now.
7087 if (FlagUser->getOpcode() == PPCISD::MFCR)
7088 return SDValue(VCMPoNode, 0);
7093 // If this is a branch on an altivec predicate comparison, lower this so
7094 // that we don't have to do a MFCR: instead, branch directly on CR6. This
7095 // lowering is done pre-legalize, because the legalizer lowers the predicate
7096 // compare down to code that is difficult to reassemble.
7097 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
7098 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
7102 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7103 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
7104 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
7105 assert(isDot && "Can't compare against a vector result!");
7107 // If this is a comparison against something other than 0/1, then we know
7108 // that the condition is never/always true.
7109 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7110 if (Val != 0 && Val != 1) {
7111 if (CC == ISD::SETEQ) // Cond never true, remove branch.
7112 return N->getOperand(0);
7113 // Always !=, turn it into an unconditional branch.
7114 return DAG.getNode(ISD::BR, dl, MVT::Other,
7115 N->getOperand(0), N->getOperand(4));
7118 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
7120 // Create the PPCISD altivec 'dot' comparison node.
7122 LHS.getOperand(2), // LHS of compare
7123 LHS.getOperand(3), // RHS of compare
7124 DAG.getConstant(CompareOpc, MVT::i32)
7126 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
7127 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
7129 // Unpack the result based on how the target uses it.
7130 PPC::Predicate CompOpc;
7131 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
7132 default: // Can't happen, don't crash on invalid number though.
7133 case 0: // Branch on the value of the EQ bit of CR6.
7134 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
7136 case 1: // Branch on the inverted value of the EQ bit of CR6.
7137 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
7139 case 2: // Branch on the value of the LT bit of CR6.
7140 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
7142 case 3: // Branch on the inverted value of the LT bit of CR6.
7143 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
7147 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
7148 DAG.getConstant(CompOpc, MVT::i32),
7149 DAG.getRegister(PPC::CR6, MVT::i32),
7150 N->getOperand(4), CompNode.getValue(1));
7159 //===----------------------------------------------------------------------===//
7160 // Inline Assembly Support
7161 //===----------------------------------------------------------------------===//
7163 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7166 const SelectionDAG &DAG,
7167 unsigned Depth) const {
7168 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
7169 switch (Op.getOpcode()) {
7171 case PPCISD::LBRX: {
7172 // lhbrx is known to have the top bits cleared out.
7173 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
7174 KnownZero = 0xFFFF0000;
7177 case ISD::INTRINSIC_WO_CHAIN: {
7178 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
7180 case Intrinsic::ppc_altivec_vcmpbfp_p:
7181 case Intrinsic::ppc_altivec_vcmpeqfp_p:
7182 case Intrinsic::ppc_altivec_vcmpequb_p:
7183 case Intrinsic::ppc_altivec_vcmpequh_p:
7184 case Intrinsic::ppc_altivec_vcmpequw_p:
7185 case Intrinsic::ppc_altivec_vcmpgefp_p:
7186 case Intrinsic::ppc_altivec_vcmpgtfp_p:
7187 case Intrinsic::ppc_altivec_vcmpgtsb_p:
7188 case Intrinsic::ppc_altivec_vcmpgtsh_p:
7189 case Intrinsic::ppc_altivec_vcmpgtsw_p:
7190 case Intrinsic::ppc_altivec_vcmpgtub_p:
7191 case Intrinsic::ppc_altivec_vcmpgtuh_p:
7192 case Intrinsic::ppc_altivec_vcmpgtuw_p:
7193 KnownZero = ~1U; // All bits but the low one are known to be zero.
7201 /// getConstraintType - Given a constraint, return the type of
7202 /// constraint it is for this target.
7203 PPCTargetLowering::ConstraintType
7204 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
7205 if (Constraint.size() == 1) {
7206 switch (Constraint[0]) {
7213 return C_RegisterClass;
7215 // FIXME: While Z does indicate a memory constraint, it specifically
7216 // indicates an r+r address (used in conjunction with the 'y' modifier
7217 // in the replacement string). Currently, we're forcing the base
7218 // register to be r0 in the asm printer (which is interpreted as zero)
7219 // and forming the complete address in the second register. This is
7224 return TargetLowering::getConstraintType(Constraint);
7227 /// Examine constraint type and operand type and determine a weight value.
7228 /// This object must already have been set up with the operand type
7229 /// and the current alternative constraint selected.
7230 TargetLowering::ConstraintWeight
7231 PPCTargetLowering::getSingleConstraintMatchWeight(
7232 AsmOperandInfo &info, const char *constraint) const {
7233 ConstraintWeight weight = CW_Invalid;
7234 Value *CallOperandVal = info.CallOperandVal;
7235 // If we don't have a value, we can't do a match,
7236 // but allow it at the lowest weight.
7237 if (CallOperandVal == NULL)
7239 Type *type = CallOperandVal->getType();
7240 // Look at the constraint type.
7241 switch (*constraint) {
7243 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
7246 if (type->isIntegerTy())
7247 weight = CW_Register;
7250 if (type->isFloatTy())
7251 weight = CW_Register;
7254 if (type->isDoubleTy())
7255 weight = CW_Register;
7258 if (type->isVectorTy())
7259 weight = CW_Register;
7262 weight = CW_Register;
7271 std::pair<unsigned, const TargetRegisterClass*>
7272 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7274 if (Constraint.size() == 1) {
7275 // GCC RS6000 Constraint Letters
7276 switch (Constraint[0]) {
7278 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7279 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
7280 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
7282 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7283 return std::make_pair(0U, &PPC::G8RCRegClass);
7284 return std::make_pair(0U, &PPC::GPRCRegClass);
7286 if (VT == MVT::f32 || VT == MVT::i32)
7287 return std::make_pair(0U, &PPC::F4RCRegClass);
7288 if (VT == MVT::f64 || VT == MVT::i64)
7289 return std::make_pair(0U, &PPC::F8RCRegClass);
7292 return std::make_pair(0U, &PPC::VRRCRegClass);
7294 return std::make_pair(0U, &PPC::CRRCRegClass);
7298 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7302 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7303 /// vector. If it is invalid, don't add anything to Ops.
7304 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7305 std::string &Constraint,
7306 std::vector<SDValue>&Ops,
7307 SelectionDAG &DAG) const {
7308 SDValue Result(0,0);
7310 // Only support length 1 constraints.
7311 if (Constraint.length() > 1) return;
7313 char Letter = Constraint[0];
7324 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
7325 if (!CST) return; // Must be an immediate to match.
7326 unsigned Value = CST->getZExtValue();
7328 default: llvm_unreachable("Unknown constraint letter!");
7329 case 'I': // "I" is a signed 16-bit constant.
7330 if ((short)Value == (int)Value)
7331 Result = DAG.getTargetConstant(Value, Op.getValueType());
7333 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
7334 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
7335 if ((short)Value == 0)
7336 Result = DAG.getTargetConstant(Value, Op.getValueType());
7338 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
7339 if ((Value >> 16) == 0)
7340 Result = DAG.getTargetConstant(Value, Op.getValueType());
7342 case 'M': // "M" is a constant that is greater than 31.
7344 Result = DAG.getTargetConstant(Value, Op.getValueType());
7346 case 'N': // "N" is a positive constant that is an exact power of two.
7347 if ((int)Value > 0 && isPowerOf2_32(Value))
7348 Result = DAG.getTargetConstant(Value, Op.getValueType());
7350 case 'O': // "O" is the constant zero.
7352 Result = DAG.getTargetConstant(Value, Op.getValueType());
7354 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
7355 if ((short)-Value == (int)-Value)
7356 Result = DAG.getTargetConstant(Value, Op.getValueType());
7363 if (Result.getNode()) {
7364 Ops.push_back(Result);
7368 // Handle standard constraint letters.
7369 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7372 // isLegalAddressingMode - Return true if the addressing mode represented
7373 // by AM is legal for this target, for a load/store of the specified type.
7374 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
7376 // FIXME: PPC does not allow r+i addressing modes for vectors!
7378 // PPC allows a sign-extended 16-bit immediate field.
7379 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
7382 // No global is ever allowed as a base.
7386 // PPC only support r+r,
7388 case 0: // "r+i" or just "i", depending on HasBaseReg.
7391 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
7393 // Otherwise we have r+r or r+i.
7396 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
7398 // Allow 2*r as r+r.
7401 // No other scales are supported.
7408 /// isLegalAddressImmediate - Return true if the integer value can be used
7409 /// as the offset of the target addressing mode for load / store of the
7411 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,Type *Ty) const{
7412 // PPC allows a sign-extended 16-bit immediate field.
7413 return (V > -(1 << 16) && V < (1 << 16)-1);
7416 bool PPCTargetLowering::isLegalAddressImmediate(GlobalValue* GV) const {
7420 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
7421 SelectionDAG &DAG) const {
7422 MachineFunction &MF = DAG.getMachineFunction();
7423 MachineFrameInfo *MFI = MF.getFrameInfo();
7424 MFI->setReturnAddressIsTaken(true);
7426 DebugLoc dl = Op.getDebugLoc();
7427 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7429 // Make sure the function does not optimize away the store of the RA to
7431 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
7432 FuncInfo->setLRStoreRequired();
7433 bool isPPC64 = PPCSubTarget.isPPC64();
7434 bool isDarwinABI = PPCSubTarget.isDarwinABI();
7437 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7440 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
7441 isPPC64? MVT::i64 : MVT::i32);
7442 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7443 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7445 MachinePointerInfo(), false, false, false, 0);
7448 // Just load the return address off the stack.
7449 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
7450 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7451 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
7454 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
7455 SelectionDAG &DAG) const {
7456 DebugLoc dl = Op.getDebugLoc();
7457 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7459 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
7460 bool isPPC64 = PtrVT == MVT::i64;
7462 MachineFunction &MF = DAG.getMachineFunction();
7463 MachineFrameInfo *MFI = MF.getFrameInfo();
7464 MFI->setFrameAddressIsTaken(true);
7466 // Naked functions never have a frame pointer, and so we use r1. For all
7467 // other functions, this decision must be delayed until during PEI.
7469 if (MF.getFunction()->getAttributes().hasAttribute(
7470 AttributeSet::FunctionIndex, Attribute::Naked))
7471 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
7473 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
7475 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
7478 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
7479 FrameAddr, MachinePointerInfo(), false, false,
7485 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7486 // The PowerPC target isn't yet aware of offsets.
7490 /// getOptimalMemOpType - Returns the target specific optimal type for load
7491 /// and store operations as a result of memset, memcpy, and memmove
7492 /// lowering. If DstAlign is zero that means it's safe to destination
7493 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
7494 /// means there isn't a need to check it against alignment requirement,
7495 /// probably because the source does not need to be loaded. If 'IsMemset' is
7496 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
7497 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
7498 /// source is constant so it does not need to be loaded.
7499 /// It returns EVT::Other if the type should be determined using generic
7500 /// target-independent logic.
7501 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
7502 unsigned DstAlign, unsigned SrcAlign,
7503 bool IsMemset, bool ZeroMemset,
7505 MachineFunction &MF) const {
7506 if (this->PPCSubTarget.isPPC64()) {
7513 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
7515 if (DisablePPCUnaligned)
7518 // PowerPC supports unaligned memory access for simple non-vector types.
7519 // Although accessing unaligned addresses is not as efficient as accessing
7520 // aligned addresses, it is generally more efficient than manual expansion,
7521 // and generally only traps for software emulation when crossing page
7527 if (VT.getSimpleVT().isVector())
7530 if (VT == MVT::ppcf128)
7539 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
7540 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
7541 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
7542 /// is expanded to mul + add.
7543 bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const {
7547 switch (VT.getSimpleVT().SimpleTy) {
7559 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
7561 return TargetLowering::getSchedulingPreference(N);