1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
44 // FIXME: Remove this once soft-float is supported.
45 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
46 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
49 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
51 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
52 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
54 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
55 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
57 // FIXME: Remove this once the bug has been fixed!
58 extern cl::opt<bool> ANDIGlueBug;
60 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
61 const PPCSubtarget &STI)
62 : TargetLowering(TM), Subtarget(STI) {
63 // Use _setjmp/_longjmp instead of setjmp/longjmp.
64 setUseUnderscoreSetJmp(true);
65 setUseUnderscoreLongJmp(true);
67 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
68 // arguments are at least 4/8 bytes aligned.
69 bool isPPC64 = Subtarget.isPPC64();
70 setMinStackArgumentAlignment(isPPC64 ? 8:4);
72 // Set up the register classes.
73 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
74 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
75 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
77 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
78 for (MVT VT : MVT::integer_valuetypes()) {
79 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
85 // PowerPC has pre-inc load and store's.
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
101 if (Subtarget.useCRBits()) {
102 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
104 if (isPPC64 || Subtarget.hasFPCVT()) {
105 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
106 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
107 isPPC64 ? MVT::i64 : MVT::i32);
108 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
109 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
110 isPPC64 ? MVT::i64 : MVT::i32);
112 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
113 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
116 // PowerPC does not support direct load / store of condition registers
117 setOperationAction(ISD::LOAD, MVT::i1, Custom);
118 setOperationAction(ISD::STORE, MVT::i1, Custom);
120 // FIXME: Remove this once the ANDI glue bug is fixed:
122 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
124 for (MVT VT : MVT::integer_valuetypes()) {
125 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
126 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
127 setTruncStoreAction(VT, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget.hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
185 Subtarget.hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget.hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget.hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget.hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget.useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget.isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget.isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget.has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget.use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget.hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (MVT VT : MVT::vector_valuetypes()) {
404 // add/sub are legal for all supported vector VT's.
405 setOperationAction(ISD::ADD , VT, Legal);
406 setOperationAction(ISD::SUB , VT, Legal);
408 // Vector instructions introduced in P8
409 if (Subtarget.hasP8Altivec()) {
410 setOperationAction(ISD::CTPOP, VT, Legal);
411 setOperationAction(ISD::CTLZ, VT, Legal);
414 setOperationAction(ISD::CTPOP, VT, Expand);
415 setOperationAction(ISD::CTLZ, VT, Expand);
418 // We promote all shuffles to v16i8.
419 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
420 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
422 // We promote all non-typed operations to v4i32.
423 setOperationAction(ISD::AND , VT, Promote);
424 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
425 setOperationAction(ISD::OR , VT, Promote);
426 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
427 setOperationAction(ISD::XOR , VT, Promote);
428 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
429 setOperationAction(ISD::LOAD , VT, Promote);
430 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
431 setOperationAction(ISD::SELECT, VT, Promote);
432 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
433 setOperationAction(ISD::STORE, VT, Promote);
434 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
436 // No other operations are legal.
437 setOperationAction(ISD::MUL , VT, Expand);
438 setOperationAction(ISD::SDIV, VT, Expand);
439 setOperationAction(ISD::SREM, VT, Expand);
440 setOperationAction(ISD::UDIV, VT, Expand);
441 setOperationAction(ISD::UREM, VT, Expand);
442 setOperationAction(ISD::FDIV, VT, Expand);
443 setOperationAction(ISD::FREM, VT, Expand);
444 setOperationAction(ISD::FNEG, VT, Expand);
445 setOperationAction(ISD::FSQRT, VT, Expand);
446 setOperationAction(ISD::FLOG, VT, Expand);
447 setOperationAction(ISD::FLOG10, VT, Expand);
448 setOperationAction(ISD::FLOG2, VT, Expand);
449 setOperationAction(ISD::FEXP, VT, Expand);
450 setOperationAction(ISD::FEXP2, VT, Expand);
451 setOperationAction(ISD::FSIN, VT, Expand);
452 setOperationAction(ISD::FCOS, VT, Expand);
453 setOperationAction(ISD::FABS, VT, Expand);
454 setOperationAction(ISD::FPOWI, VT, Expand);
455 setOperationAction(ISD::FFLOOR, VT, Expand);
456 setOperationAction(ISD::FCEIL, VT, Expand);
457 setOperationAction(ISD::FTRUNC, VT, Expand);
458 setOperationAction(ISD::FRINT, VT, Expand);
459 setOperationAction(ISD::FNEARBYINT, VT, Expand);
460 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
461 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
462 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
463 setOperationAction(ISD::MULHU, VT, Expand);
464 setOperationAction(ISD::MULHS, VT, Expand);
465 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
466 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
467 setOperationAction(ISD::UDIVREM, VT, Expand);
468 setOperationAction(ISD::SDIVREM, VT, Expand);
469 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
470 setOperationAction(ISD::FPOW, VT, Expand);
471 setOperationAction(ISD::BSWAP, VT, Expand);
472 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
473 setOperationAction(ISD::CTTZ, VT, Expand);
474 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
475 setOperationAction(ISD::VSELECT, VT, Expand);
476 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
478 for (MVT InnerVT : MVT::vector_valuetypes()) {
479 setTruncStoreAction(VT, InnerVT, Expand);
480 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
481 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
482 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
486 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
487 // with merges, splats, etc.
488 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
490 setOperationAction(ISD::AND , MVT::v4i32, Legal);
491 setOperationAction(ISD::OR , MVT::v4i32, Legal);
492 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
493 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
494 setOperationAction(ISD::SELECT, MVT::v4i32,
495 Subtarget.useCRBits() ? Legal : Expand);
496 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
497 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
498 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
499 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
500 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
501 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
502 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
503 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
504 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
506 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
507 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
508 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
509 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
511 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
512 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
514 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
515 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
516 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
519 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
520 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
521 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
523 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
524 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
526 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
527 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
528 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
529 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
531 // Altivec does not contain unordered floating-point compare instructions
532 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
533 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
534 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
535 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
537 if (Subtarget.hasVSX()) {
538 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
541 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
542 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
543 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
544 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
545 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
547 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
549 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
550 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
552 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
553 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
559 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
561 // Share the Altivec comparison restrictions.
562 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
563 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
564 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
565 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
567 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
568 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
570 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
572 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
574 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
575 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
577 // VSX v2i64 only supports non-arithmetic operations.
578 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
579 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
581 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
582 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
583 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
585 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
587 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
588 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
589 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
590 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
592 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
594 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
595 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
596 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
597 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
599 // Vector operation legalization checks the result type of
600 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
601 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
602 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
603 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
604 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
606 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
609 if (Subtarget.hasP8Altivec())
610 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
613 if (Subtarget.hasQPX()) {
614 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
615 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
616 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
617 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
619 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
620 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand);
622 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
623 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
625 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
626 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
628 if (!Subtarget.useCRBits())
629 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
630 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
632 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);
633 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
634 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
635 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
636 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
637 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
638 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
640 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
641 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
643 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
644 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
645 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
647 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
648 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
649 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
650 setOperationAction(ISD::FCOS , MVT::v4f64, Expand);
651 setOperationAction(ISD::FPOWI , MVT::v4f64, Expand);
652 setOperationAction(ISD::FPOW , MVT::v4f64, Expand);
653 setOperationAction(ISD::FLOG , MVT::v4f64, Expand);
654 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
655 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand);
656 setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
657 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
659 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
660 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
662 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
663 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
665 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
667 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
668 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
669 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
670 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
672 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
673 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
675 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
676 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
678 if (!Subtarget.useCRBits())
679 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
680 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
682 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
683 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
684 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
685 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
686 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
687 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
688 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
690 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
691 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
693 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
694 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
695 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
696 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
697 setOperationAction(ISD::FPOWI , MVT::v4f32, Expand);
698 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
699 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
700 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
701 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
702 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
703 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
705 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
706 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
708 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
709 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
711 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
713 setOperationAction(ISD::AND , MVT::v4i1, Legal);
714 setOperationAction(ISD::OR , MVT::v4i1, Legal);
715 setOperationAction(ISD::XOR , MVT::v4i1, Legal);
717 if (!Subtarget.useCRBits())
718 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
719 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
721 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
722 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
724 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);
725 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
726 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
727 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand);
728 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
729 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
730 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
732 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
733 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
735 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
737 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
738 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
739 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
740 setOperationAction(ISD::FROUND, MVT::v4f64, Legal);
742 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
743 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
744 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
745 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
747 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
748 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
750 // These need to set FE_INEXACT, and so cannot be vectorized here.
751 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
752 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
754 if (TM.Options.UnsafeFPMath) {
755 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
756 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
758 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
759 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
761 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
762 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
764 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
765 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
769 if (Subtarget.has64BitSupport())
770 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
772 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
775 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
776 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
779 setBooleanContents(ZeroOrOneBooleanContent);
781 if (Subtarget.hasAltivec()) {
782 // Altivec instructions set fields to all zeros or all ones.
783 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
787 // These libcalls are not available in 32-bit.
788 setLibcallName(RTLIB::SHL_I128, nullptr);
789 setLibcallName(RTLIB::SRL_I128, nullptr);
790 setLibcallName(RTLIB::SRA_I128, nullptr);
794 setStackPointerRegisterToSaveRestore(PPC::X1);
795 setExceptionPointerRegister(PPC::X3);
796 setExceptionSelectorRegister(PPC::X4);
798 setStackPointerRegisterToSaveRestore(PPC::R1);
799 setExceptionPointerRegister(PPC::R3);
800 setExceptionSelectorRegister(PPC::R4);
803 // We have target-specific dag combine patterns for the following nodes:
804 setTargetDAGCombine(ISD::SINT_TO_FP);
805 if (Subtarget.hasFPCVT())
806 setTargetDAGCombine(ISD::UINT_TO_FP);
807 setTargetDAGCombine(ISD::LOAD);
808 setTargetDAGCombine(ISD::STORE);
809 setTargetDAGCombine(ISD::BR_CC);
810 if (Subtarget.useCRBits())
811 setTargetDAGCombine(ISD::BRCOND);
812 setTargetDAGCombine(ISD::BSWAP);
813 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
814 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
815 setTargetDAGCombine(ISD::INTRINSIC_VOID);
817 setTargetDAGCombine(ISD::SIGN_EXTEND);
818 setTargetDAGCombine(ISD::ZERO_EXTEND);
819 setTargetDAGCombine(ISD::ANY_EXTEND);
821 if (Subtarget.useCRBits()) {
822 setTargetDAGCombine(ISD::TRUNCATE);
823 setTargetDAGCombine(ISD::SETCC);
824 setTargetDAGCombine(ISD::SELECT_CC);
827 // Use reciprocal estimates.
828 if (TM.Options.UnsafeFPMath) {
829 setTargetDAGCombine(ISD::FDIV);
830 setTargetDAGCombine(ISD::FSQRT);
833 // Darwin long double math library functions have $LDBL128 appended.
834 if (Subtarget.isDarwin()) {
835 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
836 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
837 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
838 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
839 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
840 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
841 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
842 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
843 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
844 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
847 // With 32 condition bits, we don't need to sink (and duplicate) compares
848 // aggressively in CodeGenPrep.
849 if (Subtarget.useCRBits()) {
850 setHasMultipleConditionRegisters();
851 setJumpIsExpensive();
854 setMinFunctionAlignment(2);
855 if (Subtarget.isDarwin())
856 setPrefFunctionAlignment(4);
858 switch (Subtarget.getDarwinDirective()) {
862 case PPC::DIR_E500mc:
871 setPrefFunctionAlignment(4);
872 setPrefLoopAlignment(4);
876 setInsertFencesForAtomic(true);
878 if (Subtarget.enableMachineScheduler())
879 setSchedulingPreference(Sched::Source);
881 setSchedulingPreference(Sched::Hybrid);
883 computeRegisterProperties();
885 // The Freescale cores do better with aggressive inlining of memcpy and
886 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
887 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
888 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
889 MaxStoresPerMemset = 32;
890 MaxStoresPerMemsetOptSize = 16;
891 MaxStoresPerMemcpy = 32;
892 MaxStoresPerMemcpyOptSize = 8;
893 MaxStoresPerMemmove = 32;
894 MaxStoresPerMemmoveOptSize = 8;
898 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
899 /// the desired ByVal argument alignment.
900 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
901 unsigned MaxMaxAlign) {
902 if (MaxAlign == MaxMaxAlign)
904 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
905 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
907 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
909 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
910 unsigned EltAlign = 0;
911 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
912 if (EltAlign > MaxAlign)
914 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
915 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
916 unsigned EltAlign = 0;
917 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
918 if (EltAlign > MaxAlign)
920 if (MaxAlign == MaxMaxAlign)
926 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
927 /// function arguments in the caller parameter area.
928 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
929 // Darwin passes everything on 4 byte boundary.
930 if (Subtarget.isDarwin())
933 // 16byte and wider vectors are passed on 16byte boundary.
934 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
935 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
936 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
937 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
941 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
943 default: return nullptr;
944 case PPCISD::FSEL: return "PPCISD::FSEL";
945 case PPCISD::FCFID: return "PPCISD::FCFID";
946 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
947 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
948 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
949 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
950 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
951 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
952 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
953 case PPCISD::FRE: return "PPCISD::FRE";
954 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
955 case PPCISD::STFIWX: return "PPCISD::STFIWX";
956 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
957 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
958 case PPCISD::VPERM: return "PPCISD::VPERM";
959 case PPCISD::CMPB: return "PPCISD::CMPB";
960 case PPCISD::Hi: return "PPCISD::Hi";
961 case PPCISD::Lo: return "PPCISD::Lo";
962 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
963 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
964 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
965 case PPCISD::SRL: return "PPCISD::SRL";
966 case PPCISD::SRA: return "PPCISD::SRA";
967 case PPCISD::SHL: return "PPCISD::SHL";
968 case PPCISD::CALL: return "PPCISD::CALL";
969 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
970 case PPCISD::MTCTR: return "PPCISD::MTCTR";
971 case PPCISD::BCTRL: return "PPCISD::BCTRL";
972 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
973 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
974 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
975 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
976 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
977 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
978 case PPCISD::VCMP: return "PPCISD::VCMP";
979 case PPCISD::VCMPo: return "PPCISD::VCMPo";
980 case PPCISD::LBRX: return "PPCISD::LBRX";
981 case PPCISD::STBRX: return "PPCISD::STBRX";
982 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
983 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
984 case PPCISD::LARX: return "PPCISD::LARX";
985 case PPCISD::STCX: return "PPCISD::STCX";
986 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
987 case PPCISD::BDNZ: return "PPCISD::BDNZ";
988 case PPCISD::BDZ: return "PPCISD::BDZ";
989 case PPCISD::MFFS: return "PPCISD::MFFS";
990 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
991 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
992 case PPCISD::CR6SET: return "PPCISD::CR6SET";
993 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
994 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
995 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
996 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
997 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
998 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
999 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1000 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1001 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1002 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1003 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1004 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1005 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1006 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1007 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1008 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1009 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1010 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1011 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1012 case PPCISD::SC: return "PPCISD::SC";
1013 case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1014 case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1015 case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1016 case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1017 case PPCISD::QBFLT: return "PPCISD::QBFLT";
1018 case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1022 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &C, EVT VT) const {
1024 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1026 if (Subtarget.hasQPX())
1027 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
1029 return VT.changeVectorElementTypeToInteger();
1032 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1033 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1037 //===----------------------------------------------------------------------===//
1038 // Node matching predicates, for use by the tblgen matching code.
1039 //===----------------------------------------------------------------------===//
1041 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1042 static bool isFloatingPointZero(SDValue Op) {
1043 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1044 return CFP->getValueAPF().isZero();
1045 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1046 // Maybe this has already been legalized into the constant pool?
1047 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1048 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1049 return CFP->getValueAPF().isZero();
1054 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1055 /// true if Op is undef or if it matches the specified value.
1056 static bool isConstantOrUndef(int Op, int Val) {
1057 return Op < 0 || Op == Val;
1060 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1061 /// VPKUHUM instruction.
1062 /// The ShuffleKind distinguishes between big-endian operations with
1063 /// two different inputs (0), either-endian operations with two identical
1064 /// inputs (1), and little-endian operantion with two different inputs (2).
1065 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1066 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1067 SelectionDAG &DAG) {
1068 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1069 if (ShuffleKind == 0) {
1072 for (unsigned i = 0; i != 16; ++i)
1073 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1075 } else if (ShuffleKind == 2) {
1078 for (unsigned i = 0; i != 16; ++i)
1079 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1081 } else if (ShuffleKind == 1) {
1082 unsigned j = IsLE ? 0 : 1;
1083 for (unsigned i = 0; i != 8; ++i)
1084 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1085 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1091 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1092 /// VPKUWUM instruction.
1093 /// The ShuffleKind distinguishes between big-endian operations with
1094 /// two different inputs (0), either-endian operations with two identical
1095 /// inputs (1), and little-endian operantion with two different inputs (2).
1096 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1097 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1098 SelectionDAG &DAG) {
1099 bool IsLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1100 if (ShuffleKind == 0) {
1103 for (unsigned i = 0; i != 16; i += 2)
1104 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1105 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1107 } else if (ShuffleKind == 2) {
1110 for (unsigned i = 0; i != 16; i += 2)
1111 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1112 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1114 } else if (ShuffleKind == 1) {
1115 unsigned j = IsLE ? 0 : 2;
1116 for (unsigned i = 0; i != 8; i += 2)
1117 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1118 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1119 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1120 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1126 /// isVMerge - Common function, used to match vmrg* shuffles.
1128 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1129 unsigned LHSStart, unsigned RHSStart) {
1130 if (N->getValueType(0) != MVT::v16i8)
1132 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1133 "Unsupported merge size!");
1135 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1136 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1137 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1138 LHSStart+j+i*UnitSize) ||
1139 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1140 RHSStart+j+i*UnitSize))
1146 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1147 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1148 /// The ShuffleKind distinguishes between big-endian merges with two
1149 /// different inputs (0), either-endian merges with two identical inputs (1),
1150 /// and little-endian merges with two different inputs (2). For the latter,
1151 /// the input operands are swapped (see PPCInstrAltivec.td).
1152 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1153 unsigned ShuffleKind, SelectionDAG &DAG) {
1154 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
1155 if (ShuffleKind == 1) // unary
1156 return isVMerge(N, UnitSize, 0, 0);
1157 else if (ShuffleKind == 2) // swapped
1158 return isVMerge(N, UnitSize, 0, 16);
1162 if (ShuffleKind == 1) // unary
1163 return isVMerge(N, UnitSize, 8, 8);
1164 else if (ShuffleKind == 0) // normal
1165 return isVMerge(N, UnitSize, 8, 24);
1171 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1172 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1173 /// The ShuffleKind distinguishes between big-endian merges with two
1174 /// different inputs (0), either-endian merges with two identical inputs (1),
1175 /// and little-endian merges with two different inputs (2). For the latter,
1176 /// the input operands are swapped (see PPCInstrAltivec.td).
1177 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1178 unsigned ShuffleKind, SelectionDAG &DAG) {
1179 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
1180 if (ShuffleKind == 1) // unary
1181 return isVMerge(N, UnitSize, 8, 8);
1182 else if (ShuffleKind == 2) // swapped
1183 return isVMerge(N, UnitSize, 8, 24);
1187 if (ShuffleKind == 1) // unary
1188 return isVMerge(N, UnitSize, 0, 0);
1189 else if (ShuffleKind == 0) // normal
1190 return isVMerge(N, UnitSize, 0, 16);
1197 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1198 /// amount, otherwise return -1.
1199 /// The ShuffleKind distinguishes between big-endian operations with two
1200 /// different inputs (0), either-endian operations with two identical inputs
1201 /// (1), and little-endian operations with two different inputs (2). For the
1202 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1203 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1204 SelectionDAG &DAG) {
1205 if (N->getValueType(0) != MVT::v16i8)
1208 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1210 // Find the first non-undef value in the shuffle mask.
1212 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1215 if (i == 16) return -1; // all undef.
1217 // Otherwise, check to see if the rest of the elements are consecutively
1218 // numbered from this value.
1219 unsigned ShiftAmt = SVOp->getMaskElt(i);
1220 if (ShiftAmt < i) return -1;
1223 bool isLE = DAG.getTarget().getDataLayout()->isLittleEndian();
1225 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1226 // Check the rest of the elements to see if they are consecutive.
1227 for (++i; i != 16; ++i)
1228 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1230 } else if (ShuffleKind == 1) {
1231 // Check the rest of the elements to see if they are consecutive.
1232 for (++i; i != 16; ++i)
1233 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1238 if (ShuffleKind == 2 && isLE)
1239 ShiftAmt = 16 - ShiftAmt;
1244 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1245 /// specifies a splat of a single element that is suitable for input to
1246 /// VSPLTB/VSPLTH/VSPLTW.
1247 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1248 assert(N->getValueType(0) == MVT::v16i8 &&
1249 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1251 // This is a splat operation if each element of the permute is the same, and
1252 // if the value doesn't reference the second vector.
1253 unsigned ElementBase = N->getMaskElt(0);
1255 // FIXME: Handle UNDEF elements too!
1256 if (ElementBase >= 16)
1259 // Check that the indices are consecutive, in the case of a multi-byte element
1260 // splatted with a v16i8 mask.
1261 for (unsigned i = 1; i != EltSize; ++i)
1262 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1265 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1266 if (N->getMaskElt(i) < 0) continue;
1267 for (unsigned j = 0; j != EltSize; ++j)
1268 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1274 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1276 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1277 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1279 APInt APVal, APUndef;
1283 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1284 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1285 return CFP->getValueAPF().isNegZero();
1290 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1291 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1292 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1293 SelectionDAG &DAG) {
1294 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1295 assert(isSplatShuffleMask(SVOp, EltSize));
1296 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1297 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1299 return SVOp->getMaskElt(0) / EltSize;
1302 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1303 /// by using a vspltis[bhw] instruction of the specified element size, return
1304 /// the constant being splatted. The ByteSize field indicates the number of
1305 /// bytes of each element [124] -> [bhw].
1306 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1307 SDValue OpVal(nullptr, 0);
1309 // If ByteSize of the splat is bigger than the element size of the
1310 // build_vector, then we have a case where we are checking for a splat where
1311 // multiple elements of the buildvector are folded together into a single
1312 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1313 unsigned EltSize = 16/N->getNumOperands();
1314 if (EltSize < ByteSize) {
1315 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1316 SDValue UniquedVals[4];
1317 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1319 // See if all of the elements in the buildvector agree across.
1320 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1321 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1322 // If the element isn't a constant, bail fully out.
1323 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1326 if (!UniquedVals[i&(Multiple-1)].getNode())
1327 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1328 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1329 return SDValue(); // no match.
1332 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1333 // either constant or undef values that are identical for each chunk. See
1334 // if these chunks can form into a larger vspltis*.
1336 // Check to see if all of the leading entries are either 0 or -1. If
1337 // neither, then this won't fit into the immediate field.
1338 bool LeadingZero = true;
1339 bool LeadingOnes = true;
1340 for (unsigned i = 0; i != Multiple-1; ++i) {
1341 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1343 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1344 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1346 // Finally, check the least significant entry.
1348 if (!UniquedVals[Multiple-1].getNode())
1349 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1350 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1352 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1355 if (!UniquedVals[Multiple-1].getNode())
1356 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1357 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1358 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1359 return DAG.getTargetConstant(Val, MVT::i32);
1365 // Check to see if this buildvec has a single non-undef value in its elements.
1366 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1367 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1368 if (!OpVal.getNode())
1369 OpVal = N->getOperand(i);
1370 else if (OpVal != N->getOperand(i))
1374 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1376 unsigned ValSizeInBytes = EltSize;
1378 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1379 Value = CN->getZExtValue();
1380 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1381 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1382 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1385 // If the splat value is larger than the element value, then we can never do
1386 // this splat. The only case that we could fit the replicated bits into our
1387 // immediate field for would be zero, and we prefer to use vxor for it.
1388 if (ValSizeInBytes < ByteSize) return SDValue();
1390 // If the element value is larger than the splat value, cut it in half and
1391 // check to see if the two halves are equal. Continue doing this until we
1392 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1393 while (ValSizeInBytes > ByteSize) {
1394 ValSizeInBytes >>= 1;
1396 // If the top half equals the bottom half, we're still ok.
1397 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1398 (Value & ((1 << (8*ValSizeInBytes))-1)))
1402 // Properly sign extend the value.
1403 int MaskVal = SignExtend32(Value, ByteSize * 8);
1405 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1406 if (MaskVal == 0) return SDValue();
1408 // Finally, if this value fits in a 5 bit sext field, return it
1409 if (SignExtend32<5>(MaskVal) == MaskVal)
1410 return DAG.getTargetConstant(MaskVal, MVT::i32);
1414 /// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
1415 /// amount, otherwise return -1.
1416 int PPC::isQVALIGNIShuffleMask(SDNode *N) {
1417 EVT VT = N->getValueType(0);
1418 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
1421 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1423 // Find the first non-undef value in the shuffle mask.
1425 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
1428 if (i == 4) return -1; // all undef.
1430 // Otherwise, check to see if the rest of the elements are consecutively
1431 // numbered from this value.
1432 unsigned ShiftAmt = SVOp->getMaskElt(i);
1433 if (ShiftAmt < i) return -1;
1436 // Check the rest of the elements to see if they are consecutive.
1437 for (++i; i != 4; ++i)
1438 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1444 //===----------------------------------------------------------------------===//
1445 // Addressing Mode Selection
1446 //===----------------------------------------------------------------------===//
1448 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1449 /// or 64-bit immediate, and if the value can be accurately represented as a
1450 /// sign extension from a 16-bit value. If so, this returns true and the
1452 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1453 if (!isa<ConstantSDNode>(N))
1456 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1457 if (N->getValueType(0) == MVT::i32)
1458 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1460 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1462 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1463 return isIntS16Immediate(Op.getNode(), Imm);
1467 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1468 /// can be represented as an indexed [r+r] operation. Returns false if it
1469 /// can be more efficiently represented with [r+imm].
1470 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1472 SelectionDAG &DAG) const {
1474 if (N.getOpcode() == ISD::ADD) {
1475 if (isIntS16Immediate(N.getOperand(1), imm))
1476 return false; // r+i
1477 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1478 return false; // r+i
1480 Base = N.getOperand(0);
1481 Index = N.getOperand(1);
1483 } else if (N.getOpcode() == ISD::OR) {
1484 if (isIntS16Immediate(N.getOperand(1), imm))
1485 return false; // r+i can fold it if we can.
1487 // If this is an or of disjoint bitfields, we can codegen this as an add
1488 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1490 APInt LHSKnownZero, LHSKnownOne;
1491 APInt RHSKnownZero, RHSKnownOne;
1492 DAG.computeKnownBits(N.getOperand(0),
1493 LHSKnownZero, LHSKnownOne);
1495 if (LHSKnownZero.getBoolValue()) {
1496 DAG.computeKnownBits(N.getOperand(1),
1497 RHSKnownZero, RHSKnownOne);
1498 // If all of the bits are known zero on the LHS or RHS, the add won't
1500 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1501 Base = N.getOperand(0);
1502 Index = N.getOperand(1);
1511 // If we happen to be doing an i64 load or store into a stack slot that has
1512 // less than a 4-byte alignment, then the frame-index elimination may need to
1513 // use an indexed load or store instruction (because the offset may not be a
1514 // multiple of 4). The extra register needed to hold the offset comes from the
1515 // register scavenger, and it is possible that the scavenger will need to use
1516 // an emergency spill slot. As a result, we need to make sure that a spill slot
1517 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1519 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1520 // FIXME: This does not handle the LWA case.
1524 // NOTE: We'll exclude negative FIs here, which come from argument
1525 // lowering, because there are no known test cases triggering this problem
1526 // using packed structures (or similar). We can remove this exclusion if
1527 // we find such a test case. The reason why this is so test-case driven is
1528 // because this entire 'fixup' is only to prevent crashes (from the
1529 // register scavenger) on not-really-valid inputs. For example, if we have:
1531 // %b = bitcast i1* %a to i64*
1532 // store i64* a, i64 b
1533 // then the store should really be marked as 'align 1', but is not. If it
1534 // were marked as 'align 1' then the indexed form would have been
1535 // instruction-selected initially, and the problem this 'fixup' is preventing
1536 // won't happen regardless.
1540 MachineFunction &MF = DAG.getMachineFunction();
1541 MachineFrameInfo *MFI = MF.getFrameInfo();
1543 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1547 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1548 FuncInfo->setHasNonRISpills();
1551 /// Returns true if the address N can be represented by a base register plus
1552 /// a signed 16-bit displacement [r+imm], and if it is not better
1553 /// represented as reg+reg. If Aligned is true, only accept displacements
1554 /// suitable for STD and friends, i.e. multiples of 4.
1555 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1558 bool Aligned) const {
1559 // FIXME dl should come from parent load or store, not from address
1561 // If this can be more profitably realized as r+r, fail.
1562 if (SelectAddressRegReg(N, Disp, Base, DAG))
1565 if (N.getOpcode() == ISD::ADD) {
1567 if (isIntS16Immediate(N.getOperand(1), imm) &&
1568 (!Aligned || (imm & 3) == 0)) {
1569 Disp = DAG.getTargetConstant(imm, N.getValueType());
1570 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1571 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1572 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1574 Base = N.getOperand(0);
1576 return true; // [r+i]
1577 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1578 // Match LOAD (ADD (X, Lo(G))).
1579 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1580 && "Cannot handle constant offsets yet!");
1581 Disp = N.getOperand(1).getOperand(0); // The global address.
1582 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1583 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1584 Disp.getOpcode() == ISD::TargetConstantPool ||
1585 Disp.getOpcode() == ISD::TargetJumpTable);
1586 Base = N.getOperand(0);
1587 return true; // [&g+r]
1589 } else if (N.getOpcode() == ISD::OR) {
1591 if (isIntS16Immediate(N.getOperand(1), imm) &&
1592 (!Aligned || (imm & 3) == 0)) {
1593 // If this is an or of disjoint bitfields, we can codegen this as an add
1594 // (for better address arithmetic) if the LHS and RHS of the OR are
1595 // provably disjoint.
1596 APInt LHSKnownZero, LHSKnownOne;
1597 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1599 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1600 // If all of the bits are known zero on the LHS or RHS, the add won't
1602 if (FrameIndexSDNode *FI =
1603 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1604 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1605 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1607 Base = N.getOperand(0);
1609 Disp = DAG.getTargetConstant(imm, N.getValueType());
1613 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1614 // Loading from a constant address.
1616 // If this address fits entirely in a 16-bit sext immediate field, codegen
1619 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1620 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1621 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1622 CN->getValueType(0));
1626 // Handle 32-bit sext immediates with LIS + addr mode.
1627 if ((CN->getValueType(0) == MVT::i32 ||
1628 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1629 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1630 int Addr = (int)CN->getZExtValue();
1632 // Otherwise, break this down into an LIS + disp.
1633 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1635 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1636 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1637 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1642 Disp = DAG.getTargetConstant(0, getPointerTy());
1643 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1644 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1645 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1648 return true; // [r+0]
1651 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1652 /// represented as an indexed [r+r] operation.
1653 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1655 SelectionDAG &DAG) const {
1656 // Check to see if we can easily represent this as an [r+r] address. This
1657 // will fail if it thinks that the address is more profitably represented as
1658 // reg+imm, e.g. where imm = 0.
1659 if (SelectAddressRegReg(N, Base, Index, DAG))
1662 // If the operand is an addition, always emit this as [r+r], since this is
1663 // better (for code size, and execution, as the memop does the add for free)
1664 // than emitting an explicit add.
1665 if (N.getOpcode() == ISD::ADD) {
1666 Base = N.getOperand(0);
1667 Index = N.getOperand(1);
1671 // Otherwise, do it the hard way, using R0 as the base register.
1672 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1678 /// getPreIndexedAddressParts - returns true by value, base pointer and
1679 /// offset pointer and addressing mode by reference if the node's address
1680 /// can be legally represented as pre-indexed load / store address.
1681 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1683 ISD::MemIndexedMode &AM,
1684 SelectionDAG &DAG) const {
1685 if (DisablePPCPreinc) return false;
1691 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1692 Ptr = LD->getBasePtr();
1693 VT = LD->getMemoryVT();
1694 Alignment = LD->getAlignment();
1695 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1696 Ptr = ST->getBasePtr();
1697 VT = ST->getMemoryVT();
1698 Alignment = ST->getAlignment();
1703 // PowerPC doesn't have preinc load/store instructions for vectors (except
1704 // for QPX, which does have preinc r+r forms).
1705 if (VT.isVector()) {
1706 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
1708 } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
1714 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1716 // Common code will reject creating a pre-inc form if the base pointer
1717 // is a frame index, or if N is a store and the base pointer is either
1718 // the same as or a predecessor of the value being stored. Check for
1719 // those situations here, and try with swapped Base/Offset instead.
1722 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1725 SDValue Val = cast<StoreSDNode>(N)->getValue();
1726 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1731 std::swap(Base, Offset);
1737 // LDU/STU can only handle immediates that are a multiple of 4.
1738 if (VT != MVT::i64) {
1739 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1742 // LDU/STU need an address with at least 4-byte alignment.
1746 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1750 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1751 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1752 // sext i32 to i64 when addr mode is r+i.
1753 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1754 LD->getExtensionType() == ISD::SEXTLOAD &&
1755 isa<ConstantSDNode>(Offset))
1763 //===----------------------------------------------------------------------===//
1764 // LowerOperation implementation
1765 //===----------------------------------------------------------------------===//
1767 /// GetLabelAccessInfo - Return true if we should reference labels using a
1768 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1769 static bool GetLabelAccessInfo(const TargetMachine &TM,
1770 const PPCSubtarget &Subtarget,
1771 unsigned &HiOpFlags, unsigned &LoOpFlags,
1772 const GlobalValue *GV = nullptr) {
1773 HiOpFlags = PPCII::MO_HA;
1774 LoOpFlags = PPCII::MO_LO;
1776 // Don't use the pic base if not in PIC relocation model.
1777 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1780 HiOpFlags |= PPCII::MO_PIC_FLAG;
1781 LoOpFlags |= PPCII::MO_PIC_FLAG;
1784 // If this is a reference to a global value that requires a non-lazy-ptr, make
1785 // sure that instruction lowering adds it.
1786 if (GV && Subtarget.hasLazyResolverStub(GV)) {
1787 HiOpFlags |= PPCII::MO_NLP_FLAG;
1788 LoOpFlags |= PPCII::MO_NLP_FLAG;
1790 if (GV->hasHiddenVisibility()) {
1791 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1792 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1799 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1800 SelectionDAG &DAG) {
1801 EVT PtrVT = HiPart.getValueType();
1802 SDValue Zero = DAG.getConstant(0, PtrVT);
1805 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1806 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1808 // With PIC, the first instruction is actually "GR+hi(&G)".
1810 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1811 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1813 // Generate non-pic code that has direct accesses to the constant pool.
1814 // The address of the global is just (hi(&g)+lo(&g)).
1815 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1818 static void setUsesTOCBasePtr(MachineFunction &MF) {
1819 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1820 FuncInfo->setUsesTOCBasePtr();
1823 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
1824 setUsesTOCBasePtr(DAG.getMachineFunction());
1827 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1828 SelectionDAG &DAG) const {
1829 EVT PtrVT = Op.getValueType();
1830 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1831 const Constant *C = CP->getConstVal();
1833 // 64-bit SVR4 ABI code is always position-independent.
1834 // The actual address of the GlobalValue is stored in the TOC.
1835 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1836 setUsesTOCBasePtr(DAG);
1837 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1838 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1839 DAG.getRegister(PPC::X2, MVT::i64));
1842 unsigned MOHiFlag, MOLoFlag;
1844 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
1846 if (isPIC && Subtarget.isSVR4ABI()) {
1847 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1848 PPCII::MO_PIC_FLAG);
1850 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1851 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1855 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1857 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1858 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1861 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1862 EVT PtrVT = Op.getValueType();
1863 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1865 // 64-bit SVR4 ABI code is always position-independent.
1866 // The actual address of the GlobalValue is stored in the TOC.
1867 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1868 setUsesTOCBasePtr(DAG);
1869 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1870 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1871 DAG.getRegister(PPC::X2, MVT::i64));
1874 unsigned MOHiFlag, MOLoFlag;
1876 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
1878 if (isPIC && Subtarget.isSVR4ABI()) {
1879 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1880 PPCII::MO_PIC_FLAG);
1882 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1883 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1886 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1887 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1888 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1891 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1892 SelectionDAG &DAG) const {
1893 EVT PtrVT = Op.getValueType();
1894 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
1895 const BlockAddress *BA = BASDN->getBlockAddress();
1897 // 64-bit SVR4 ABI code is always position-independent.
1898 // The actual BlockAddress is stored in the TOC.
1899 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1900 setUsesTOCBasePtr(DAG);
1901 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
1902 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(BASDN), MVT::i64, GA,
1903 DAG.getRegister(PPC::X2, MVT::i64));
1906 unsigned MOHiFlag, MOLoFlag;
1908 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
1909 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1910 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1911 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1914 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1915 SelectionDAG &DAG) const {
1917 // FIXME: TLS addresses currently use medium model code sequences,
1918 // which is the most useful form. Eventually support for small and
1919 // large models could be added if users need it, at the cost of
1920 // additional complexity.
1921 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1923 const GlobalValue *GV = GA->getGlobal();
1924 EVT PtrVT = getPointerTy();
1925 bool is64bit = Subtarget.isPPC64();
1926 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
1927 PICLevel::Level picLevel = M->getPICLevel();
1929 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1931 if (Model == TLSModel::LocalExec) {
1932 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1933 PPCII::MO_TPREL_HA);
1934 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1935 PPCII::MO_TPREL_LO);
1936 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1937 is64bit ? MVT::i64 : MVT::i32);
1938 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1939 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1942 if (Model == TLSModel::InitialExec) {
1943 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1944 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1948 setUsesTOCBasePtr(DAG);
1949 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1950 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1951 PtrVT, GOTReg, TGA);
1953 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1954 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1955 PtrVT, TGA, GOTPtr);
1956 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1959 if (Model == TLSModel::GeneralDynamic) {
1960 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1963 setUsesTOCBasePtr(DAG);
1964 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1965 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1968 if (picLevel == PICLevel::Small)
1969 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1971 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1973 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
1977 if (Model == TLSModel::LocalDynamic) {
1978 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1981 setUsesTOCBasePtr(DAG);
1982 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1983 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1986 if (picLevel == PICLevel::Small)
1987 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1989 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1991 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
1992 PtrVT, GOTPtr, TGA, TGA);
1993 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
1994 PtrVT, TLSAddr, TGA);
1995 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1998 llvm_unreachable("Unknown TLS model!");
2001 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2002 SelectionDAG &DAG) const {
2003 EVT PtrVT = Op.getValueType();
2004 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2006 const GlobalValue *GV = GSDN->getGlobal();
2008 // 64-bit SVR4 ABI code is always position-independent.
2009 // The actual address of the GlobalValue is stored in the TOC.
2010 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2011 setUsesTOCBasePtr(DAG);
2012 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2013 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
2014 DAG.getRegister(PPC::X2, MVT::i64));
2017 unsigned MOHiFlag, MOLoFlag;
2019 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag, GV);
2021 if (isPIC && Subtarget.isSVR4ABI()) {
2022 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2024 PPCII::MO_PIC_FLAG);
2025 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
2026 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
2030 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2032 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2034 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
2036 // If the global reference is actually to a non-lazy-pointer, we have to do an
2037 // extra load to get the address of the global.
2038 if (MOHiFlag & PPCII::MO_NLP_FLAG)
2039 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
2040 false, false, false, 0);
2044 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2045 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2048 if (Op.getValueType() == MVT::v2i64) {
2049 // When the operands themselves are v2i64 values, we need to do something
2050 // special because VSX has no underlying comparison operations for these.
2051 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2052 // Equality can be handled by casting to the legal type for Altivec
2053 // comparisons, everything else needs to be expanded.
2054 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2055 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2056 DAG.getSetCC(dl, MVT::v4i32,
2057 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2058 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2065 // We handle most of these in the usual way.
2069 // If we're comparing for equality to zero, expose the fact that this is
2070 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
2071 // fold the new nodes.
2072 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2073 if (C->isNullValue() && CC == ISD::SETEQ) {
2074 EVT VT = Op.getOperand(0).getValueType();
2075 SDValue Zext = Op.getOperand(0);
2076 if (VT.bitsLT(MVT::i32)) {
2078 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
2080 unsigned Log2b = Log2_32(VT.getSizeInBits());
2081 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
2082 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
2083 DAG.getConstant(Log2b, MVT::i32));
2084 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
2086 // Leave comparisons against 0 and -1 alone for now, since they're usually
2087 // optimized. FIXME: revisit this when we can custom lower all setcc
2089 if (C->isAllOnesValue() || C->isNullValue())
2093 // If we have an integer seteq/setne, turn it into a compare against zero
2094 // by xor'ing the rhs with the lhs, which is faster than setting a
2095 // condition register, reading it back out, and masking the correct bit. The
2096 // normal approach here uses sub to do this instead of xor. Using xor exposes
2097 // the result to other bit-twiddling opportunities.
2098 EVT LHSVT = Op.getOperand(0).getValueType();
2099 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2100 EVT VT = Op.getValueType();
2101 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2103 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
2108 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
2109 const PPCSubtarget &Subtarget) const {
2110 SDNode *Node = Op.getNode();
2111 EVT VT = Node->getValueType(0);
2112 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2113 SDValue InChain = Node->getOperand(0);
2114 SDValue VAListPtr = Node->getOperand(1);
2115 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2118 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
2121 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2122 VAListPtr, MachinePointerInfo(SV), MVT::i8,
2123 false, false, false, 0);
2124 InChain = GprIndex.getValue(1);
2126 if (VT == MVT::i64) {
2127 // Check if GprIndex is even
2128 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2129 DAG.getConstant(1, MVT::i32));
2130 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2131 DAG.getConstant(0, MVT::i32), ISD::SETNE);
2132 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2133 DAG.getConstant(1, MVT::i32));
2134 // Align GprIndex to be even if it isn't
2135 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2139 // fpr index is 1 byte after gpr
2140 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2141 DAG.getConstant(1, MVT::i32));
2144 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2145 FprPtr, MachinePointerInfo(SV), MVT::i8,
2146 false, false, false, 0);
2147 InChain = FprIndex.getValue(1);
2149 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2150 DAG.getConstant(8, MVT::i32));
2152 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2153 DAG.getConstant(4, MVT::i32));
2156 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
2157 MachinePointerInfo(), false, false,
2159 InChain = OverflowArea.getValue(1);
2161 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
2162 MachinePointerInfo(), false, false,
2164 InChain = RegSaveArea.getValue(1);
2166 // select overflow_area if index > 8
2167 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
2168 DAG.getConstant(8, MVT::i32), ISD::SETLT);
2170 // adjustment constant gpr_index * 4/8
2171 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
2172 VT.isInteger() ? GprIndex : FprIndex,
2173 DAG.getConstant(VT.isInteger() ? 4 : 8,
2176 // OurReg = RegSaveArea + RegConstant
2177 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2180 // Floating types are 32 bytes into RegSaveArea
2181 if (VT.isFloatingPoint())
2182 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2183 DAG.getConstant(32, MVT::i32));
2185 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
2186 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2187 VT.isInteger() ? GprIndex : FprIndex,
2188 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
2191 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
2192 VT.isInteger() ? VAListPtr : FprPtr,
2193 MachinePointerInfo(SV),
2194 MVT::i8, false, false, 0);
2196 // determine if we should load from reg_save_area or overflow_area
2197 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
2199 // increase overflow_area by 4/8 if gpr/fpr > 8
2200 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2201 DAG.getConstant(VT.isInteger() ? 4 : 8,
2204 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2207 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
2209 MachinePointerInfo(),
2210 MVT::i32, false, false, 0);
2212 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
2213 false, false, false, 0);
2216 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2217 const PPCSubtarget &Subtarget) const {
2218 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2220 // We have to copy the entire va_list struct:
2221 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2222 return DAG.getMemcpy(Op.getOperand(0), Op,
2223 Op.getOperand(1), Op.getOperand(2),
2224 DAG.getConstant(12, MVT::i32), 8, false, true,
2225 MachinePointerInfo(), MachinePointerInfo());
2228 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2229 SelectionDAG &DAG) const {
2230 return Op.getOperand(0);
2233 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2234 SelectionDAG &DAG) const {
2235 SDValue Chain = Op.getOperand(0);
2236 SDValue Trmp = Op.getOperand(1); // trampoline
2237 SDValue FPtr = Op.getOperand(2); // nested function
2238 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2241 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2242 bool isPPC64 = (PtrVT == MVT::i64);
2244 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2247 TargetLowering::ArgListTy Args;
2248 TargetLowering::ArgListEntry Entry;
2250 Entry.Ty = IntPtrTy;
2251 Entry.Node = Trmp; Args.push_back(Entry);
2253 // TrampSize == (isPPC64 ? 48 : 40);
2254 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2255 isPPC64 ? MVT::i64 : MVT::i32);
2256 Args.push_back(Entry);
2258 Entry.Node = FPtr; Args.push_back(Entry);
2259 Entry.Node = Nest; Args.push_back(Entry);
2261 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2262 TargetLowering::CallLoweringInfo CLI(DAG);
2263 CLI.setDebugLoc(dl).setChain(Chain)
2264 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2265 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2266 std::move(Args), 0);
2268 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2269 return CallResult.second;
2272 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2273 const PPCSubtarget &Subtarget) const {
2274 MachineFunction &MF = DAG.getMachineFunction();
2275 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2279 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2280 // vastart just stores the address of the VarArgsFrameIndex slot into the
2281 // memory location argument.
2282 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2283 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2284 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2285 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2286 MachinePointerInfo(SV),
2290 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2291 // We suppose the given va_list is already allocated.
2294 // char gpr; /* index into the array of 8 GPRs
2295 // * stored in the register save area
2296 // * gpr=0 corresponds to r3,
2297 // * gpr=1 to r4, etc.
2299 // char fpr; /* index into the array of 8 FPRs
2300 // * stored in the register save area
2301 // * fpr=0 corresponds to f1,
2302 // * fpr=1 to f2, etc.
2304 // char *overflow_arg_area;
2305 // /* location on stack that holds
2306 // * the next overflow argument
2308 // char *reg_save_area;
2309 // /* where r3:r10 and f1:f8 (if saved)
2315 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2316 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2319 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2321 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2323 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2326 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2327 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2329 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2330 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2332 uint64_t FPROffset = 1;
2333 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2335 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2337 // Store first byte : number of int regs
2338 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2340 MachinePointerInfo(SV),
2341 MVT::i8, false, false, 0);
2342 uint64_t nextOffset = FPROffset;
2343 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2346 // Store second byte : number of float regs
2347 SDValue secondStore =
2348 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2349 MachinePointerInfo(SV, nextOffset), MVT::i8,
2351 nextOffset += StackOffset;
2352 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2354 // Store second word : arguments given on stack
2355 SDValue thirdStore =
2356 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2357 MachinePointerInfo(SV, nextOffset),
2359 nextOffset += FrameOffset;
2360 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2362 // Store third word : arguments given in registers
2363 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2364 MachinePointerInfo(SV, nextOffset),
2369 #include "PPCGenCallingConv.inc"
2371 // Function whose sole purpose is to kill compiler warnings
2372 // stemming from unused functions included from PPCGenCallingConv.inc.
2373 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2374 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2377 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2378 CCValAssign::LocInfo &LocInfo,
2379 ISD::ArgFlagsTy &ArgFlags,
2384 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2386 CCValAssign::LocInfo &LocInfo,
2387 ISD::ArgFlagsTy &ArgFlags,
2389 static const MCPhysReg ArgRegs[] = {
2390 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2391 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2393 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2395 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2397 // Skip one register if the first unallocated register has an even register
2398 // number and there are still argument registers available which have not been
2399 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2400 // need to skip a register if RegNum is odd.
2401 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2402 State.AllocateReg(ArgRegs[RegNum]);
2405 // Always return false here, as this function only makes sure that the first
2406 // unallocated register has an odd register number and does not actually
2407 // allocate a register for the current argument.
2411 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2413 CCValAssign::LocInfo &LocInfo,
2414 ISD::ArgFlagsTy &ArgFlags,
2416 static const MCPhysReg ArgRegs[] = {
2417 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2421 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2423 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2425 // If there is only one Floating-point register left we need to put both f64
2426 // values of a split ppc_fp128 value on the stack.
2427 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2428 State.AllocateReg(ArgRegs[RegNum]);
2431 // Always return false here, as this function only makes sure that the two f64
2432 // values a ppc_fp128 value is split into are both passed in registers or both
2433 // passed on the stack and does not actually allocate a register for the
2434 // current argument.
2438 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2440 static const MCPhysReg *GetFPR() {
2441 static const MCPhysReg FPR[] = {
2442 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2443 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2449 /// GetQFPR - Get the set of QPX registers that should be allocated for
2451 static const MCPhysReg *GetQFPR() {
2452 static const MCPhysReg QFPR[] = {
2453 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
2454 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13
2460 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2462 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2463 unsigned PtrByteSize) {
2464 unsigned ArgSize = ArgVT.getStoreSize();
2465 if (Flags.isByVal())
2466 ArgSize = Flags.getByValSize();
2468 // Round up to multiples of the pointer size, except for array members,
2469 // which are always packed.
2470 if (!Flags.isInConsecutiveRegs())
2471 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2476 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2478 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2479 ISD::ArgFlagsTy Flags,
2480 unsigned PtrByteSize) {
2481 unsigned Align = PtrByteSize;
2483 // Altivec parameters are padded to a 16 byte boundary.
2484 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2485 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2486 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2488 // QPX vector types stored in double-precision are padded to a 32 byte
2490 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
2493 // ByVal parameters are aligned as requested.
2494 if (Flags.isByVal()) {
2495 unsigned BVAlign = Flags.getByValAlign();
2496 if (BVAlign > PtrByteSize) {
2497 if (BVAlign % PtrByteSize != 0)
2499 "ByVal alignment is not a multiple of the pointer size");
2505 // Array members are always packed to their original alignment.
2506 if (Flags.isInConsecutiveRegs()) {
2507 // If the array member was split into multiple registers, the first
2508 // needs to be aligned to the size of the full type. (Except for
2509 // ppcf128, which is only aligned as its f64 components.)
2510 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2511 Align = OrigVT.getStoreSize();
2513 Align = ArgVT.getStoreSize();
2519 /// CalculateStackSlotUsed - Return whether this argument will use its
2520 /// stack slot (instead of being passed in registers). ArgOffset,
2521 /// AvailableFPRs, and AvailableVRs must hold the current argument
2522 /// position, and will be updated to account for this argument.
2523 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2524 ISD::ArgFlagsTy Flags,
2525 unsigned PtrByteSize,
2526 unsigned LinkageSize,
2527 unsigned ParamAreaSize,
2528 unsigned &ArgOffset,
2529 unsigned &AvailableFPRs,
2530 unsigned &AvailableVRs, bool HasQPX) {
2531 bool UseMemory = false;
2533 // Respect alignment of argument on the stack.
2535 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2536 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2537 // If there's no space left in the argument save area, we must
2538 // use memory (this check also catches zero-sized arguments).
2539 if (ArgOffset >= LinkageSize + ParamAreaSize)
2542 // Allocate argument on the stack.
2543 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2544 if (Flags.isInConsecutiveRegsLast())
2545 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2546 // If we overran the argument save area, we must use memory
2547 // (this check catches arguments passed partially in memory)
2548 if (ArgOffset > LinkageSize + ParamAreaSize)
2551 // However, if the argument is actually passed in an FPR or a VR,
2552 // we don't use memory after all.
2553 if (!Flags.isByVal()) {
2554 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
2555 // QPX registers overlap with the scalar FP registers.
2556 (HasQPX && (ArgVT == MVT::v4f32 ||
2557 ArgVT == MVT::v4f64 ||
2558 ArgVT == MVT::v4i1)))
2559 if (AvailableFPRs > 0) {
2563 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2564 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2565 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2566 if (AvailableVRs > 0) {
2575 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2576 /// ensure minimum alignment required for target.
2577 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2578 unsigned NumBytes) {
2579 unsigned TargetAlign = Lowering->getStackAlignment();
2580 unsigned AlignMask = TargetAlign - 1;
2581 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2586 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2587 CallingConv::ID CallConv, bool isVarArg,
2588 const SmallVectorImpl<ISD::InputArg>
2590 SDLoc dl, SelectionDAG &DAG,
2591 SmallVectorImpl<SDValue> &InVals)
2593 if (Subtarget.isSVR4ABI()) {
2594 if (Subtarget.isPPC64())
2595 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2598 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2601 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2607 PPCTargetLowering::LowerFormalArguments_32SVR4(
2609 CallingConv::ID CallConv, bool isVarArg,
2610 const SmallVectorImpl<ISD::InputArg>
2612 SDLoc dl, SelectionDAG &DAG,
2613 SmallVectorImpl<SDValue> &InVals) const {
2615 // 32-bit SVR4 ABI Stack Frame Layout:
2616 // +-----------------------------------+
2617 // +--> | Back chain |
2618 // | +-----------------------------------+
2619 // | | Floating-point register save area |
2620 // | +-----------------------------------+
2621 // | | General register save area |
2622 // | +-----------------------------------+
2623 // | | CR save word |
2624 // | +-----------------------------------+
2625 // | | VRSAVE save word |
2626 // | +-----------------------------------+
2627 // | | Alignment padding |
2628 // | +-----------------------------------+
2629 // | | Vector register save area |
2630 // | +-----------------------------------+
2631 // | | Local variable space |
2632 // | +-----------------------------------+
2633 // | | Parameter list area |
2634 // | +-----------------------------------+
2635 // | | LR save word |
2636 // | +-----------------------------------+
2637 // SP--> +--- | Back chain |
2638 // +-----------------------------------+
2641 // System V Application Binary Interface PowerPC Processor Supplement
2642 // AltiVec Technology Programming Interface Manual
2644 MachineFunction &MF = DAG.getMachineFunction();
2645 MachineFrameInfo *MFI = MF.getFrameInfo();
2646 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2648 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2649 // Potential tail calls could cause overwriting of argument stack slots.
2650 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2651 (CallConv == CallingConv::Fast));
2652 unsigned PtrByteSize = 4;
2654 // Assign locations to all of the incoming arguments.
2655 SmallVector<CCValAssign, 16> ArgLocs;
2656 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2659 // Reserve space for the linkage area on the stack.
2660 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
2661 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2663 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2665 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2666 CCValAssign &VA = ArgLocs[i];
2668 // Arguments stored in registers.
2669 if (VA.isRegLoc()) {
2670 const TargetRegisterClass *RC;
2671 EVT ValVT = VA.getValVT();
2673 switch (ValVT.getSimpleVT().SimpleTy) {
2675 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2678 RC = &PPC::GPRCRegClass;
2681 RC = &PPC::F4RCRegClass;
2684 if (Subtarget.hasVSX())
2685 RC = &PPC::VSFRCRegClass;
2687 RC = &PPC::F8RCRegClass;
2692 RC = &PPC::VRRCRegClass;
2695 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
2699 RC = &PPC::VSHRCRegClass;
2702 RC = &PPC::QFRCRegClass;
2705 RC = &PPC::QBRCRegClass;
2709 // Transform the arguments stored in physical registers into virtual ones.
2710 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2711 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2712 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2714 if (ValVT == MVT::i1)
2715 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2717 InVals.push_back(ArgValue);
2719 // Argument stored in memory.
2720 assert(VA.isMemLoc());
2722 unsigned ArgSize = VA.getLocVT().getStoreSize();
2723 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2726 // Create load nodes to retrieve arguments from the stack.
2727 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2728 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2729 MachinePointerInfo(),
2730 false, false, false, 0));
2734 // Assign locations to all of the incoming aggregate by value arguments.
2735 // Aggregates passed by value are stored in the local variable space of the
2736 // caller's stack frame, right above the parameter list area.
2737 SmallVector<CCValAssign, 16> ByValArgLocs;
2738 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2739 ByValArgLocs, *DAG.getContext());
2741 // Reserve stack space for the allocations in CCInfo.
2742 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2744 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2746 // Area that is at least reserved in the caller of this function.
2747 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2748 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2750 // Set the size that is at least reserved in caller of this function. Tail
2751 // call optimized function's reserved stack space needs to be aligned so that
2752 // taking the difference between two stack areas will result in an aligned
2755 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2756 FuncInfo->setMinReservedArea(MinReservedArea);
2758 SmallVector<SDValue, 8> MemOps;
2760 // If the function takes variable number of arguments, make a frame index for
2761 // the start of the first vararg value... for expansion of llvm.va_start.
2763 static const MCPhysReg GPArgRegs[] = {
2764 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2765 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2767 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2769 static const MCPhysReg FPArgRegs[] = {
2770 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2773 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2774 if (DisablePPCFloatInVariadic)
2777 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
2778 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
2780 // Make room for NumGPArgRegs and NumFPArgRegs.
2781 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2782 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2784 FuncInfo->setVarArgsStackOffset(
2785 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2786 CCInfo.getNextStackOffset(), true));
2788 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2789 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2791 // The fixed integer arguments of a variadic function are stored to the
2792 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2793 // the result of va_next.
2794 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2795 // Get an existing live-in vreg, or add a new one.
2796 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2798 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2800 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2801 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2802 MachinePointerInfo(), false, false, 0);
2803 MemOps.push_back(Store);
2804 // Increment the address by four for the next argument to store
2805 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2806 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2809 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2811 // The double arguments are stored to the VarArgsFrameIndex
2813 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2814 // Get an existing live-in vreg, or add a new one.
2815 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2817 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2819 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2820 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2821 MachinePointerInfo(), false, false, 0);
2822 MemOps.push_back(Store);
2823 // Increment the address by eight for the next argument to store
2824 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
2826 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2830 if (!MemOps.empty())
2831 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2836 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2837 // value to MVT::i64 and then truncate to the correct register size.
2839 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2840 SelectionDAG &DAG, SDValue ArgVal,
2843 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2844 DAG.getValueType(ObjectVT));
2845 else if (Flags.isZExt())
2846 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2847 DAG.getValueType(ObjectVT));
2849 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2853 PPCTargetLowering::LowerFormalArguments_64SVR4(
2855 CallingConv::ID CallConv, bool isVarArg,
2856 const SmallVectorImpl<ISD::InputArg>
2858 SDLoc dl, SelectionDAG &DAG,
2859 SmallVectorImpl<SDValue> &InVals) const {
2860 // TODO: add description of PPC stack frame format, or at least some docs.
2862 bool isELFv2ABI = Subtarget.isELFv2ABI();
2863 bool isLittleEndian = Subtarget.isLittleEndian();
2864 MachineFunction &MF = DAG.getMachineFunction();
2865 MachineFrameInfo *MFI = MF.getFrameInfo();
2866 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2868 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
2869 "fastcc not supported on varargs functions");
2871 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2872 // Potential tail calls could cause overwriting of argument stack slots.
2873 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2874 (CallConv == CallingConv::Fast));
2875 unsigned PtrByteSize = 8;
2876 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
2878 static const MCPhysReg GPR[] = {
2879 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2880 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2883 static const MCPhysReg *FPR = GetFPR();
2885 static const MCPhysReg VR[] = {
2886 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2887 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2889 static const MCPhysReg VSRH[] = {
2890 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2891 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2894 static const MCPhysReg *QFPR = GetQFPR();
2896 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2897 const unsigned Num_FPR_Regs = 13;
2898 const unsigned Num_VR_Regs = array_lengthof(VR);
2899 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
2901 // Do a first pass over the arguments to determine whether the ABI
2902 // guarantees that our caller has allocated the parameter save area
2903 // on its stack frame. In the ELFv1 ABI, this is always the case;
2904 // in the ELFv2 ABI, it is true if this is a vararg function or if
2905 // any parameter is located in a stack slot.
2907 bool HasParameterArea = !isELFv2ABI || isVarArg;
2908 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2909 unsigned NumBytes = LinkageSize;
2910 unsigned AvailableFPRs = Num_FPR_Regs;
2911 unsigned AvailableVRs = Num_VR_Regs;
2912 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2913 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2914 PtrByteSize, LinkageSize, ParamAreaSize,
2915 NumBytes, AvailableFPRs, AvailableVRs,
2916 Subtarget.hasQPX()))
2917 HasParameterArea = true;
2919 // Add DAG nodes to load the arguments or copy them out of registers. On
2920 // entry to a function on PPC, the arguments start after the linkage area,
2921 // although the first ones are often in registers.
2923 unsigned ArgOffset = LinkageSize;
2924 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2925 unsigned &QFPR_idx = FPR_idx;
2926 SmallVector<SDValue, 8> MemOps;
2927 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2928 unsigned CurArgIdx = 0;
2929 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2931 bool needsLoad = false;
2932 EVT ObjectVT = Ins[ArgNo].VT;
2933 EVT OrigVT = Ins[ArgNo].ArgVT;
2934 unsigned ObjSize = ObjectVT.getStoreSize();
2935 unsigned ArgSize = ObjSize;
2936 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2937 if (Ins[ArgNo].isOrigArg()) {
2938 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
2939 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
2941 // We re-align the argument offset for each argument, except when using the
2942 // fast calling convention, when we need to make sure we do that only when
2943 // we'll actually use a stack slot.
2944 unsigned CurArgOffset, Align;
2945 auto ComputeArgOffset = [&]() {
2946 /* Respect alignment of argument on the stack. */
2947 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2948 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2949 CurArgOffset = ArgOffset;
2952 if (CallConv != CallingConv::Fast) {
2955 /* Compute GPR index associated with argument offset. */
2956 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2957 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2960 // FIXME the codegen can be much improved in some cases.
2961 // We do not have to keep everything in memory.
2962 if (Flags.isByVal()) {
2963 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
2965 if (CallConv == CallingConv::Fast)
2968 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2969 ObjSize = Flags.getByValSize();
2970 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2971 // Empty aggregate parameters do not take up registers. Examples:
2975 // etc. However, we have to provide a place-holder in InVals, so
2976 // pretend we have an 8-byte item at the current address for that
2979 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2980 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2981 InVals.push_back(FIN);
2985 // Create a stack object covering all stack doublewords occupied
2986 // by the argument. If the argument is (fully or partially) on
2987 // the stack, or if the argument is fully in registers but the
2988 // caller has allocated the parameter save anyway, we can refer
2989 // directly to the caller's stack frame. Otherwise, create a
2990 // local copy in our own frame.
2992 if (HasParameterArea ||
2993 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2994 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
2996 FI = MFI->CreateStackObject(ArgSize, Align, false);
2997 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2999 // Handle aggregates smaller than 8 bytes.
3000 if (ObjSize < PtrByteSize) {
3001 // The value of the object is its address, which differs from the
3002 // address of the enclosing doubleword on big-endian systems.
3004 if (!isLittleEndian) {
3005 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
3006 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3008 InVals.push_back(Arg);
3010 if (GPR_idx != Num_GPR_Regs) {
3011 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3012 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3015 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3016 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3017 (ObjSize == 2 ? MVT::i16 : MVT::i32));
3018 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3019 MachinePointerInfo(FuncArg),
3020 ObjType, false, false, 0);
3022 // For sizes that don't fit a truncating store (3, 5, 6, 7),
3023 // store the whole register as-is to the parameter save area
3025 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3026 MachinePointerInfo(FuncArg),
3030 MemOps.push_back(Store);
3032 // Whether we copied from a register or not, advance the offset
3033 // into the parameter save area by a full doubleword.
3034 ArgOffset += PtrByteSize;
3038 // The value of the object is its address, which is the address of
3039 // its first stack doubleword.
3040 InVals.push_back(FIN);
3042 // Store whatever pieces of the object are in registers to memory.
3043 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3044 if (GPR_idx == Num_GPR_Regs)
3047 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3048 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3051 SDValue Off = DAG.getConstant(j, PtrVT);
3052 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3054 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
3055 MachinePointerInfo(FuncArg, j),
3057 MemOps.push_back(Store);
3060 ArgOffset += ArgSize;
3064 switch (ObjectVT.getSimpleVT().SimpleTy) {
3065 default: llvm_unreachable("Unhandled argument type!");
3069 // These can be scalar arguments or elements of an integer array type
3070 // passed directly. Clang may use those instead of "byval" aggregate
3071 // types to avoid forcing arguments to memory unnecessarily.
3072 if (GPR_idx != Num_GPR_Regs) {
3073 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3074 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3076 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3077 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3078 // value to MVT::i64 and then truncate to the correct register size.
3079 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3081 if (CallConv == CallingConv::Fast)
3085 ArgSize = PtrByteSize;
3087 if (CallConv != CallingConv::Fast || needsLoad)
3093 // These can be scalar arguments or elements of a float array type
3094 // passed directly. The latter are used to implement ELFv2 homogenous
3095 // float aggregates.
3096 if (FPR_idx != Num_FPR_Regs) {
3099 if (ObjectVT == MVT::f32)
3100 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3102 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3103 ? &PPC::VSFRCRegClass
3104 : &PPC::F8RCRegClass);
3106 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3108 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3109 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3110 // once we support fp <-> gpr moves.
3112 // This can only ever happen in the presence of f32 array types,
3113 // since otherwise we never run out of FPRs before running out
3115 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3116 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3118 if (ObjectVT == MVT::f32) {
3119 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3120 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3121 DAG.getConstant(32, MVT::i32));
3122 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3125 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3127 if (CallConv == CallingConv::Fast)
3133 // When passing an array of floats, the array occupies consecutive
3134 // space in the argument area; only round up to the next doubleword
3135 // at the end of the array. Otherwise, each float takes 8 bytes.
3136 if (CallConv != CallingConv::Fast || needsLoad) {
3137 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3138 ArgOffset += ArgSize;
3139 if (Flags.isInConsecutiveRegsLast())
3140 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3149 if (!Subtarget.hasQPX()) {
3150 // These can be scalar arguments or elements of a vector array type
3151 // passed directly. The latter are used to implement ELFv2 homogenous
3152 // vector aggregates.
3153 if (VR_idx != Num_VR_Regs) {
3154 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
3155 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
3156 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3157 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3160 if (CallConv == CallingConv::Fast)
3165 if (CallConv != CallingConv::Fast || needsLoad)
3170 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
3171 "Invalid QPX parameter type");
3176 // QPX vectors are treated like their scalar floating-point subregisters
3177 // (except that they're larger).
3178 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3179 if (QFPR_idx != Num_QFPR_Regs) {
3180 const TargetRegisterClass *RC;
3181 switch (ObjectVT.getSimpleVT().SimpleTy) {
3182 case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3183 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3184 default: RC = &PPC::QBRCRegClass; break;
3187 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3188 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3191 if (CallConv == CallingConv::Fast)
3195 if (CallConv != CallingConv::Fast || needsLoad)
3200 // We need to load the argument to a virtual register if we determined
3201 // above that we ran out of physical registers of the appropriate type.
3203 if (ObjSize < ArgSize && !isLittleEndian)
3204 CurArgOffset += ArgSize - ObjSize;
3205 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
3206 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3207 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3208 false, false, false, 0);
3211 InVals.push_back(ArgVal);
3214 // Area that is at least reserved in the caller of this function.
3215 unsigned MinReservedArea;
3216 if (HasParameterArea)
3217 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
3219 MinReservedArea = LinkageSize;
3221 // Set the size that is at least reserved in caller of this function. Tail
3222 // call optimized functions' reserved stack space needs to be aligned so that
3223 // taking the difference between two stack areas will result in an aligned
3226 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3227 FuncInfo->setMinReservedArea(MinReservedArea);
3229 // If the function takes variable number of arguments, make a frame index for
3230 // the start of the first vararg value... for expansion of llvm.va_start.
3232 int Depth = ArgOffset;
3234 FuncInfo->setVarArgsFrameIndex(
3235 MFI->CreateFixedObject(PtrByteSize, Depth, true));
3236 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3238 // If this function is vararg, store any remaining integer argument regs
3239 // to their spots on the stack so that they may be loaded by deferencing the
3240 // result of va_next.
3241 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3242 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
3243 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3244 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3245 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3246 MachinePointerInfo(), false, false, 0);
3247 MemOps.push_back(Store);
3248 // Increment the address by four for the next argument to store
3249 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
3250 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3254 if (!MemOps.empty())
3255 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3261 PPCTargetLowering::LowerFormalArguments_Darwin(
3263 CallingConv::ID CallConv, bool isVarArg,
3264 const SmallVectorImpl<ISD::InputArg>
3266 SDLoc dl, SelectionDAG &DAG,
3267 SmallVectorImpl<SDValue> &InVals) const {
3268 // TODO: add description of PPC stack frame format, or at least some docs.
3270 MachineFunction &MF = DAG.getMachineFunction();
3271 MachineFrameInfo *MFI = MF.getFrameInfo();
3272 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3274 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3275 bool isPPC64 = PtrVT == MVT::i64;
3276 // Potential tail calls could cause overwriting of argument stack slots.
3277 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3278 (CallConv == CallingConv::Fast));
3279 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3280 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3281 unsigned ArgOffset = LinkageSize;
3282 // Area that is at least reserved in caller of this function.
3283 unsigned MinReservedArea = ArgOffset;
3285 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3286 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3287 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3289 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3290 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3291 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3294 static const MCPhysReg *FPR = GetFPR();
3296 static const MCPhysReg VR[] = {
3297 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3298 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3301 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3302 const unsigned Num_FPR_Regs = 13;
3303 const unsigned Num_VR_Regs = array_lengthof( VR);
3305 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3307 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3309 // In 32-bit non-varargs functions, the stack space for vectors is after the
3310 // stack space for non-vectors. We do not use this space unless we have
3311 // too many vectors to fit in registers, something that only occurs in
3312 // constructed examples:), but we have to walk the arglist to figure
3313 // that out...for the pathological case, compute VecArgOffset as the
3314 // start of the vector parameter area. Computing VecArgOffset is the
3315 // entire point of the following loop.
3316 unsigned VecArgOffset = ArgOffset;
3317 if (!isVarArg && !isPPC64) {
3318 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3320 EVT ObjectVT = Ins[ArgNo].VT;
3321 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3323 if (Flags.isByVal()) {
3324 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3325 unsigned ObjSize = Flags.getByValSize();
3327 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3328 VecArgOffset += ArgSize;
3332 switch(ObjectVT.getSimpleVT().SimpleTy) {
3333 default: llvm_unreachable("Unhandled argument type!");
3339 case MVT::i64: // PPC64
3341 // FIXME: We are guaranteed to be !isPPC64 at this point.
3342 // Does MVT::i64 apply?
3349 // Nothing to do, we're only looking at Nonvector args here.
3354 // We've found where the vector parameter area in memory is. Skip the
3355 // first 12 parameters; these don't use that memory.
3356 VecArgOffset = ((VecArgOffset+15)/16)*16;
3357 VecArgOffset += 12*16;
3359 // Add DAG nodes to load the arguments or copy them out of registers. On
3360 // entry to a function on PPC, the arguments start after the linkage area,
3361 // although the first ones are often in registers.
3363 SmallVector<SDValue, 8> MemOps;
3364 unsigned nAltivecParamsAtEnd = 0;
3365 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3366 unsigned CurArgIdx = 0;
3367 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3369 bool needsLoad = false;
3370 EVT ObjectVT = Ins[ArgNo].VT;
3371 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3372 unsigned ArgSize = ObjSize;
3373 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3374 if (Ins[ArgNo].isOrigArg()) {
3375 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3376 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3378 unsigned CurArgOffset = ArgOffset;
3380 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3381 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3382 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3383 if (isVarArg || isPPC64) {
3384 MinReservedArea = ((MinReservedArea+15)/16)*16;
3385 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3388 } else nAltivecParamsAtEnd++;
3390 // Calculate min reserved area.
3391 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3395 // FIXME the codegen can be much improved in some cases.
3396 // We do not have to keep everything in memory.
3397 if (Flags.isByVal()) {
3398 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3400 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3401 ObjSize = Flags.getByValSize();
3402 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3403 // Objects of size 1 and 2 are right justified, everything else is
3404 // left justified. This means the memory address is adjusted forwards.
3405 if (ObjSize==1 || ObjSize==2) {
3406 CurArgOffset = CurArgOffset + (4 - ObjSize);
3408 // The value of the object is its address.
3409 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3410 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3411 InVals.push_back(FIN);
3412 if (ObjSize==1 || ObjSize==2) {
3413 if (GPR_idx != Num_GPR_Regs) {
3416 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3418 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3419 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3420 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3421 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3422 MachinePointerInfo(FuncArg),
3423 ObjType, false, false, 0);
3424 MemOps.push_back(Store);
3428 ArgOffset += PtrByteSize;
3432 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3433 // Store whatever pieces of the object are in registers
3434 // to memory. ArgOffset will be the address of the beginning
3436 if (GPR_idx != Num_GPR_Regs) {
3439 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3441 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3442 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3443 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3444 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3445 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3446 MachinePointerInfo(FuncArg, j),
3448 MemOps.push_back(Store);
3450 ArgOffset += PtrByteSize;
3452 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3459 switch (ObjectVT.getSimpleVT().SimpleTy) {
3460 default: llvm_unreachable("Unhandled argument type!");
3464 if (GPR_idx != Num_GPR_Regs) {
3465 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3466 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3468 if (ObjectVT == MVT::i1)
3469 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3474 ArgSize = PtrByteSize;
3476 // All int arguments reserve stack space in the Darwin ABI.
3477 ArgOffset += PtrByteSize;
3481 case MVT::i64: // PPC64
3482 if (GPR_idx != Num_GPR_Regs) {
3483 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3484 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3486 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3487 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3488 // value to MVT::i64 and then truncate to the correct register size.
3489 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3494 ArgSize = PtrByteSize;
3496 // All int arguments reserve stack space in the Darwin ABI.
3502 // Every 4 bytes of argument space consumes one of the GPRs available for
3503 // argument passing.
3504 if (GPR_idx != Num_GPR_Regs) {
3506 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3509 if (FPR_idx != Num_FPR_Regs) {
3512 if (ObjectVT == MVT::f32)
3513 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3515 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3517 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3523 // All FP arguments reserve stack space in the Darwin ABI.
3524 ArgOffset += isPPC64 ? 8 : ObjSize;
3530 // Note that vector arguments in registers don't reserve stack space,
3531 // except in varargs functions.
3532 if (VR_idx != Num_VR_Regs) {
3533 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3534 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3536 while ((ArgOffset % 16) != 0) {
3537 ArgOffset += PtrByteSize;
3538 if (GPR_idx != Num_GPR_Regs)
3542 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3546 if (!isVarArg && !isPPC64) {
3547 // Vectors go after all the nonvectors.
3548 CurArgOffset = VecArgOffset;
3551 // Vectors are aligned.
3552 ArgOffset = ((ArgOffset+15)/16)*16;
3553 CurArgOffset = ArgOffset;
3561 // We need to load the argument to a virtual register if we determined above
3562 // that we ran out of physical registers of the appropriate type.
3564 int FI = MFI->CreateFixedObject(ObjSize,
3565 CurArgOffset + (ArgSize - ObjSize),
3567 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3568 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3569 false, false, false, 0);
3572 InVals.push_back(ArgVal);
3575 // Allow for Altivec parameters at the end, if needed.
3576 if (nAltivecParamsAtEnd) {
3577 MinReservedArea = ((MinReservedArea+15)/16)*16;
3578 MinReservedArea += 16*nAltivecParamsAtEnd;
3581 // Area that is at least reserved in the caller of this function.
3582 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3584 // Set the size that is at least reserved in caller of this function. Tail
3585 // call optimized functions' reserved stack space needs to be aligned so that
3586 // taking the difference between two stack areas will result in an aligned
3589 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3590 FuncInfo->setMinReservedArea(MinReservedArea);
3592 // If the function takes variable number of arguments, make a frame index for
3593 // the start of the first vararg value... for expansion of llvm.va_start.
3595 int Depth = ArgOffset;
3597 FuncInfo->setVarArgsFrameIndex(
3598 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3600 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3602 // If this function is vararg, store any remaining integer argument regs
3603 // to their spots on the stack so that they may be loaded by deferencing the
3604 // result of va_next.
3605 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3609 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3611 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3613 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3614 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3615 MachinePointerInfo(), false, false, 0);
3616 MemOps.push_back(Store);
3617 // Increment the address by four for the next argument to store
3618 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3619 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3623 if (!MemOps.empty())
3624 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3629 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3630 /// adjusted to accommodate the arguments for the tailcall.
3631 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3632 unsigned ParamSize) {
3634 if (!isTailCall) return 0;
3636 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3637 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3638 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3639 // Remember only if the new adjustement is bigger.
3640 if (SPDiff < FI->getTailCallSPDelta())
3641 FI->setTailCallSPDelta(SPDiff);
3646 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3647 /// for tail call optimization. Targets which want to do tail call
3648 /// optimization should implement this function.
3650 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3651 CallingConv::ID CalleeCC,
3653 const SmallVectorImpl<ISD::InputArg> &Ins,
3654 SelectionDAG& DAG) const {
3655 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3658 // Variable argument functions are not supported.
3662 MachineFunction &MF = DAG.getMachineFunction();
3663 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3664 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3665 // Functions containing by val parameters are not supported.
3666 for (unsigned i = 0; i != Ins.size(); i++) {
3667 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3668 if (Flags.isByVal()) return false;
3671 // Non-PIC/GOT tail calls are supported.
3672 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3675 // At the moment we can only do local tail calls (in same module, hidden
3676 // or protected) if we are generating PIC.
3677 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3678 return G->getGlobal()->hasHiddenVisibility()
3679 || G->getGlobal()->hasProtectedVisibility();
3685 /// isCallCompatibleAddress - Return the immediate to use if the specified
3686 /// 32-bit value is representable in the immediate field of a BxA instruction.
3687 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3688 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3689 if (!C) return nullptr;
3691 int Addr = C->getZExtValue();
3692 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3693 SignExtend32<26>(Addr) != Addr)
3694 return nullptr; // Top 6 bits have to be sext of immediate.
3696 return DAG.getConstant((int)C->getZExtValue() >> 2,
3697 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3702 struct TailCallArgumentInfo {
3707 TailCallArgumentInfo() : FrameIdx(0) {}
3712 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3714 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3716 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3717 SmallVectorImpl<SDValue> &MemOpChains,
3719 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3720 SDValue Arg = TailCallArgs[i].Arg;
3721 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3722 int FI = TailCallArgs[i].FrameIdx;
3723 // Store relative to framepointer.
3724 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3725 MachinePointerInfo::getFixedStack(FI),
3730 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3731 /// the appropriate stack slot for the tail call optimized function call.
3732 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3733 MachineFunction &MF,
3742 // Calculate the new stack slot for the return address.
3743 int SlotSize = isPPC64 ? 8 : 4;
3744 const PPCFrameLowering *FL =
3745 MF.getSubtarget<PPCSubtarget>().getFrameLowering();
3746 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
3747 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3748 NewRetAddrLoc, true);
3749 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3750 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3751 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3752 MachinePointerInfo::getFixedStack(NewRetAddr),
3755 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3756 // slot as the FP is never overwritten.
3758 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
3759 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3761 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3762 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3763 MachinePointerInfo::getFixedStack(NewFPIdx),
3770 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3771 /// the position of the argument.
3773 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3774 SDValue Arg, int SPDiff, unsigned ArgOffset,
3775 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3776 int Offset = ArgOffset + SPDiff;
3777 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3778 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3779 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3780 SDValue FIN = DAG.getFrameIndex(FI, VT);
3781 TailCallArgumentInfo Info;
3783 Info.FrameIdxOp = FIN;
3785 TailCallArguments.push_back(Info);
3788 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3789 /// stack slot. Returns the chain as result and the loaded frame pointers in
3790 /// LROpOut/FPOpout. Used when tail calling.
3791 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3799 // Load the LR and FP stack slot for later adjusting.
3800 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3801 LROpOut = getReturnAddrFrameIndex(DAG);
3802 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3803 false, false, false, 0);
3804 Chain = SDValue(LROpOut.getNode(), 1);
3806 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3807 // slot as the FP is never overwritten.
3809 FPOpOut = getFramePointerFrameIndex(DAG);
3810 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3811 false, false, false, 0);
3812 Chain = SDValue(FPOpOut.getNode(), 1);
3818 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3819 /// by "Src" to address "Dst" of size "Size". Alignment information is
3820 /// specified by the specific parameter attribute. The copy will be passed as
3821 /// a byval function parameter.
3822 /// Sometimes what we are copying is the end of a larger object, the part that
3823 /// does not fit in registers.
3825 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3826 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3828 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3829 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3830 false, false, MachinePointerInfo(),
3831 MachinePointerInfo());
3834 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3837 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3838 SDValue Arg, SDValue PtrOff, int SPDiff,
3839 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3840 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3841 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3843 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3848 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3850 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3851 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3852 DAG.getConstant(ArgOffset, PtrVT));
3854 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3855 MachinePointerInfo(), false, false, 0));
3856 // Calculate and remember argument location.
3857 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3862 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3863 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3864 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3865 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3866 MachineFunction &MF = DAG.getMachineFunction();
3868 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3869 // might overwrite each other in case of tail call optimization.
3870 SmallVector<SDValue, 8> MemOpChains2;
3871 // Do not flag preceding copytoreg stuff together with the following stuff.
3873 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3875 if (!MemOpChains2.empty())
3876 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3878 // Store the return address to the appropriate stack slot.
3879 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3880 isPPC64, isDarwinABI, dl);
3882 // Emit callseq_end just before tailcall node.
3883 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3884 DAG.getIntPtrConstant(0, true), InFlag, dl);
3885 InFlag = Chain.getValue(1);
3888 // Is this global address that of a function that can be called by name? (as
3889 // opposed to something that must hold a descriptor for an indirect call).
3890 static bool isFunctionGlobalAddress(SDValue Callee) {
3891 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3892 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
3893 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
3896 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
3903 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3904 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
3905 bool isTailCall, bool IsPatchPoint,
3906 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3907 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3908 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
3910 bool isPPC64 = Subtarget.isPPC64();
3911 bool isSVR4ABI = Subtarget.isSVR4ABI();
3912 bool isELFv2ABI = Subtarget.isELFv2ABI();
3914 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3915 NodeTys.push_back(MVT::Other); // Returns a chain
3916 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3918 unsigned CallOpc = PPCISD::CALL;
3920 bool needIndirectCall = true;
3921 if (!isSVR4ABI || !isPPC64)
3922 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3923 // If this is an absolute destination address, use the munged value.
3924 Callee = SDValue(Dest, 0);
3925 needIndirectCall = false;
3928 if (isFunctionGlobalAddress(Callee)) {
3929 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
3930 // A call to a TLS address is actually an indirect call to a
3931 // thread-specific pointer.
3932 unsigned OpFlags = 0;
3933 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3934 (Subtarget.getTargetTriple().isMacOSX() &&
3935 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3936 (G->getGlobal()->isDeclaration() ||
3937 G->getGlobal()->isWeakForLinker())) ||
3938 (Subtarget.isTargetELF() && !isPPC64 &&
3939 !G->getGlobal()->hasLocalLinkage() &&
3940 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3941 // PC-relative references to external symbols should go through $stub,
3942 // unless we're building with the leopard linker or later, which
3943 // automatically synthesizes these stubs.
3944 OpFlags = PPCII::MO_PLT_OR_STUB;
3947 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3948 // every direct call is) turn it into a TargetGlobalAddress /
3949 // TargetExternalSymbol node so that legalize doesn't hack it.
3950 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3951 Callee.getValueType(), 0, OpFlags);
3952 needIndirectCall = false;
3955 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3956 unsigned char OpFlags = 0;
3958 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3959 (Subtarget.getTargetTriple().isMacOSX() &&
3960 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3961 (Subtarget.isTargetELF() && !isPPC64 &&
3962 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3963 // PC-relative references to external symbols should go through $stub,
3964 // unless we're building with the leopard linker or later, which
3965 // automatically synthesizes these stubs.
3966 OpFlags = PPCII::MO_PLT_OR_STUB;
3969 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3971 needIndirectCall = false;
3975 // We'll form an invalid direct call when lowering a patchpoint; the full
3976 // sequence for an indirect call is complicated, and many of the
3977 // instructions introduced might have side effects (and, thus, can't be
3978 // removed later). The call itself will be removed as soon as the
3979 // argument/return lowering is complete, so the fact that it has the wrong
3980 // kind of operands should not really matter.
3981 needIndirectCall = false;
3984 if (needIndirectCall) {
3985 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3986 // to do the call, we can't use PPCISD::CALL.
3987 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3989 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3990 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3991 // entry point, but to the function descriptor (the function entry point
3992 // address is part of the function descriptor though).
3993 // The function descriptor is a three doubleword structure with the
3994 // following fields: function entry point, TOC base address and
3995 // environment pointer.
3996 // Thus for a call through a function pointer, the following actions need
3998 // 1. Save the TOC of the caller in the TOC save area of its stack
3999 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
4000 // 2. Load the address of the function entry point from the function
4002 // 3. Load the TOC of the callee from the function descriptor into r2.
4003 // 4. Load the environment pointer from the function descriptor into
4005 // 5. Branch to the function entry point address.
4006 // 6. On return of the callee, the TOC of the caller needs to be
4007 // restored (this is done in FinishCall()).
4009 // The loads are scheduled at the beginning of the call sequence, and the
4010 // register copies are flagged together to ensure that no other
4011 // operations can be scheduled in between. E.g. without flagging the
4012 // copies together, a TOC access in the caller could be scheduled between
4013 // the assignment of the callee TOC and the branch to the callee, which
4014 // results in the TOC access going through the TOC of the callee instead
4015 // of going through the TOC of the caller, which leads to incorrect code.
4017 // Load the address of the function entry point from the function
4019 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
4020 if (LDChain.getValueType() == MVT::Glue)
4021 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
4023 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
4025 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
4026 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
4027 false, false, LoadsInv, 8);
4029 // Load environment pointer into r11.
4030 SDValue PtrOff = DAG.getIntPtrConstant(16);
4031 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
4032 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
4033 MPI.getWithOffset(16), false, false,
4036 SDValue TOCOff = DAG.getIntPtrConstant(8);
4037 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
4038 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
4039 MPI.getWithOffset(8), false, false,
4042 setUsesTOCBasePtr(DAG);
4043 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
4045 Chain = TOCVal.getValue(0);
4046 InFlag = TOCVal.getValue(1);
4048 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
4051 Chain = EnvVal.getValue(0);
4052 InFlag = EnvVal.getValue(1);
4054 MTCTROps[0] = Chain;
4055 MTCTROps[1] = LoadFuncPtr;
4056 MTCTROps[2] = InFlag;
4059 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
4060 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
4061 InFlag = Chain.getValue(1);
4064 NodeTys.push_back(MVT::Other);
4065 NodeTys.push_back(MVT::Glue);
4066 Ops.push_back(Chain);
4067 CallOpc = PPCISD::BCTRL;
4068 Callee.setNode(nullptr);
4069 // Add use of X11 (holding environment pointer)
4070 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
4071 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
4072 // Add CTR register as callee so a bctr can be emitted later.
4074 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
4077 // If this is a direct call, pass the chain and the callee.
4078 if (Callee.getNode()) {
4079 Ops.push_back(Chain);
4080 Ops.push_back(Callee);
4082 // If this is a tail call add stack pointer delta.
4084 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
4086 // Add argument registers to the end of the list so that they are known live
4088 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4089 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4090 RegsToPass[i].second.getValueType()));
4092 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
4094 if (isSVR4ABI && isPPC64 && !IsPatchPoint) {
4095 setUsesTOCBasePtr(DAG);
4096 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
4103 bool isLocalCall(const SDValue &Callee)
4105 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4106 return !G->getGlobal()->isDeclaration() &&
4107 !G->getGlobal()->isWeakForLinker();
4112 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
4113 CallingConv::ID CallConv, bool isVarArg,
4114 const SmallVectorImpl<ISD::InputArg> &Ins,
4115 SDLoc dl, SelectionDAG &DAG,
4116 SmallVectorImpl<SDValue> &InVals) const {
4118 SmallVector<CCValAssign, 16> RVLocs;
4119 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
4121 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
4123 // Copy all of the result registers out of their specified physreg.
4124 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4125 CCValAssign &VA = RVLocs[i];
4126 assert(VA.isRegLoc() && "Can only return in registers!");
4128 SDValue Val = DAG.getCopyFromReg(Chain, dl,
4129 VA.getLocReg(), VA.getLocVT(), InFlag);
4130 Chain = Val.getValue(1);
4131 InFlag = Val.getValue(2);
4133 switch (VA.getLocInfo()) {
4134 default: llvm_unreachable("Unknown loc info!");
4135 case CCValAssign::Full: break;
4136 case CCValAssign::AExt:
4137 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4139 case CCValAssign::ZExt:
4140 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
4141 DAG.getValueType(VA.getValVT()));
4142 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4144 case CCValAssign::SExt:
4145 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
4146 DAG.getValueType(VA.getValVT()));
4147 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4151 InVals.push_back(Val);
4158 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
4159 bool isTailCall, bool isVarArg, bool IsPatchPoint,
4161 SmallVector<std::pair<unsigned, SDValue>, 8>
4163 SDValue InFlag, SDValue Chain,
4164 SDValue CallSeqStart, SDValue &Callee,
4165 int SPDiff, unsigned NumBytes,
4166 const SmallVectorImpl<ISD::InputArg> &Ins,
4167 SmallVectorImpl<SDValue> &InVals,
4168 ImmutableCallSite *CS) const {
4170 std::vector<EVT> NodeTys;
4171 SmallVector<SDValue, 8> Ops;
4172 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
4173 SPDiff, isTailCall, IsPatchPoint, RegsToPass,
4174 Ops, NodeTys, CS, Subtarget);
4176 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
4177 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
4178 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
4180 // When performing tail call optimization the callee pops its arguments off
4181 // the stack. Account for this here so these bytes can be pushed back on in
4182 // PPCFrameLowering::eliminateCallFramePseudoInstr.
4183 int BytesCalleePops =
4184 (CallConv == CallingConv::Fast &&
4185 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
4187 // Add a register mask operand representing the call-preserved registers.
4188 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4189 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
4190 assert(Mask && "Missing call preserved mask for calling convention");
4191 Ops.push_back(DAG.getRegisterMask(Mask));
4193 if (InFlag.getNode())
4194 Ops.push_back(InFlag);
4198 assert(((Callee.getOpcode() == ISD::Register &&
4199 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
4200 Callee.getOpcode() == ISD::TargetExternalSymbol ||
4201 Callee.getOpcode() == ISD::TargetGlobalAddress ||
4202 isa<ConstantSDNode>(Callee)) &&
4203 "Expecting an global address, external symbol, absolute value or register");
4205 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
4208 // Add a NOP immediately after the branch instruction when using the 64-bit
4209 // SVR4 ABI. At link time, if caller and callee are in a different module and
4210 // thus have a different TOC, the call will be replaced with a call to a stub
4211 // function which saves the current TOC, loads the TOC of the callee and
4212 // branches to the callee. The NOP will be replaced with a load instruction
4213 // which restores the TOC of the caller from the TOC save slot of the current
4214 // stack frame. If caller and callee belong to the same module (and have the
4215 // same TOC), the NOP will remain unchanged.
4217 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
4219 if (CallOpc == PPCISD::BCTRL) {
4220 // This is a call through a function pointer.
4221 // Restore the caller TOC from the save area into R2.
4222 // See PrepareCall() for more information about calls through function
4223 // pointers in the 64-bit SVR4 ABI.
4224 // We are using a target-specific load with r2 hard coded, because the
4225 // result of a target-independent load would never go directly into r2,
4226 // since r2 is a reserved register (which prevents the register allocator
4227 // from allocating it), resulting in an additional register being
4228 // allocated and an unnecessary move instruction being generated.
4229 CallOpc = PPCISD::BCTRL_LOAD_TOC;
4231 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4232 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
4233 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
4234 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
4235 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
4237 // The address needs to go after the chain input but before the flag (or
4238 // any other variadic arguments).
4239 Ops.insert(std::next(Ops.begin()), AddTOC);
4240 } else if ((CallOpc == PPCISD::CALL) &&
4241 (!isLocalCall(Callee) ||
4242 DAG.getTarget().getRelocationModel() == Reloc::PIC_))
4243 // Otherwise insert NOP for non-local calls.
4244 CallOpc = PPCISD::CALL_NOP;
4247 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
4248 InFlag = Chain.getValue(1);
4250 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
4251 DAG.getIntPtrConstant(BytesCalleePops, true),
4254 InFlag = Chain.getValue(1);
4256 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
4257 Ins, dl, DAG, InVals);
4261 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
4262 SmallVectorImpl<SDValue> &InVals) const {
4263 SelectionDAG &DAG = CLI.DAG;
4265 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
4266 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4267 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4268 SDValue Chain = CLI.Chain;
4269 SDValue Callee = CLI.Callee;
4270 bool &isTailCall = CLI.IsTailCall;
4271 CallingConv::ID CallConv = CLI.CallConv;
4272 bool isVarArg = CLI.IsVarArg;
4273 bool IsPatchPoint = CLI.IsPatchPoint;
4274 ImmutableCallSite *CS = CLI.CS;
4277 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
4280 if (!isTailCall && CS && CS->isMustTailCall())
4281 report_fatal_error("failed to perform tail call elimination on a call "
4282 "site marked musttail");
4284 if (Subtarget.isSVR4ABI()) {
4285 if (Subtarget.isPPC64())
4286 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4287 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4288 dl, DAG, InVals, CS);
4290 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4291 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4292 dl, DAG, InVals, CS);
4295 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4296 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4297 dl, DAG, InVals, CS);
4301 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4302 CallingConv::ID CallConv, bool isVarArg,
4303 bool isTailCall, bool IsPatchPoint,
4304 const SmallVectorImpl<ISD::OutputArg> &Outs,
4305 const SmallVectorImpl<SDValue> &OutVals,
4306 const SmallVectorImpl<ISD::InputArg> &Ins,
4307 SDLoc dl, SelectionDAG &DAG,
4308 SmallVectorImpl<SDValue> &InVals,
4309 ImmutableCallSite *CS) const {
4310 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4311 // of the 32-bit SVR4 ABI stack frame layout.
4313 assert((CallConv == CallingConv::C ||
4314 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4316 unsigned PtrByteSize = 4;
4318 MachineFunction &MF = DAG.getMachineFunction();
4320 // Mark this function as potentially containing a function that contains a
4321 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4322 // and restoring the callers stack pointer in this functions epilog. This is
4323 // done because by tail calling the called function might overwrite the value
4324 // in this function's (MF) stack pointer stack slot 0(SP).
4325 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4326 CallConv == CallingConv::Fast)
4327 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4329 // Count how many bytes are to be pushed on the stack, including the linkage
4330 // area, parameter list area and the part of the local variable space which
4331 // contains copies of aggregates which are passed by value.
4333 // Assign locations to all of the outgoing arguments.
4334 SmallVector<CCValAssign, 16> ArgLocs;
4335 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4338 // Reserve space for the linkage area on the stack.
4339 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
4343 // Handle fixed and variable vector arguments differently.
4344 // Fixed vector arguments go into registers as long as registers are
4345 // available. Variable vector arguments always go into memory.
4346 unsigned NumArgs = Outs.size();
4348 for (unsigned i = 0; i != NumArgs; ++i) {
4349 MVT ArgVT = Outs[i].VT;
4350 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4353 if (Outs[i].IsFixed) {
4354 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4357 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4363 errs() << "Call operand #" << i << " has unhandled type "
4364 << EVT(ArgVT).getEVTString() << "\n";
4366 llvm_unreachable(nullptr);
4370 // All arguments are treated the same.
4371 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4374 // Assign locations to all of the outgoing aggregate by value arguments.
4375 SmallVector<CCValAssign, 16> ByValArgLocs;
4376 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4377 ByValArgLocs, *DAG.getContext());
4379 // Reserve stack space for the allocations in CCInfo.
4380 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4382 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4384 // Size of the linkage area, parameter list area and the part of the local
4385 // space variable where copies of aggregates which are passed by value are
4387 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4389 // Calculate by how many bytes the stack has to be adjusted in case of tail
4390 // call optimization.
4391 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4393 // Adjust the stack pointer for the new arguments...
4394 // These operations are automatically eliminated by the prolog/epilog pass
4395 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4397 SDValue CallSeqStart = Chain;
4399 // Load the return address and frame pointer so it can be moved somewhere else
4402 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4405 // Set up a copy of the stack pointer for use loading and storing any
4406 // arguments that may not fit in the registers available for argument
4408 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4410 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4411 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4412 SmallVector<SDValue, 8> MemOpChains;
4414 bool seenFloatArg = false;
4415 // Walk the register/memloc assignments, inserting copies/loads.
4416 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4419 CCValAssign &VA = ArgLocs[i];
4420 SDValue Arg = OutVals[i];
4421 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4423 if (Flags.isByVal()) {
4424 // Argument is an aggregate which is passed by value, thus we need to
4425 // create a copy of it in the local variable space of the current stack
4426 // frame (which is the stack frame of the caller) and pass the address of
4427 // this copy to the callee.
4428 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4429 CCValAssign &ByValVA = ByValArgLocs[j++];
4430 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4432 // Memory reserved in the local variable space of the callers stack frame.
4433 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4435 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4436 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4438 // Create a copy of the argument in the local area of the current
4440 SDValue MemcpyCall =
4441 CreateCopyOfByValArgument(Arg, PtrOff,
4442 CallSeqStart.getNode()->getOperand(0),
4445 // This must go outside the CALLSEQ_START..END.
4446 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4447 CallSeqStart.getNode()->getOperand(1),
4449 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4450 NewCallSeqStart.getNode());
4451 Chain = CallSeqStart = NewCallSeqStart;
4453 // Pass the address of the aggregate copy on the stack either in a
4454 // physical register or in the parameter list area of the current stack
4455 // frame to the callee.
4459 if (VA.isRegLoc()) {
4460 if (Arg.getValueType() == MVT::i1)
4461 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4463 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4464 // Put argument in a physical register.
4465 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4467 // Put argument in the parameter list area of the current stack frame.
4468 assert(VA.isMemLoc());
4469 unsigned LocMemOffset = VA.getLocMemOffset();
4472 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4473 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4475 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4476 MachinePointerInfo(),
4479 // Calculate and remember argument location.
4480 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4486 if (!MemOpChains.empty())
4487 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4489 // Build a sequence of copy-to-reg nodes chained together with token chain
4490 // and flag operands which copy the outgoing args into the appropriate regs.
4492 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4493 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4494 RegsToPass[i].second, InFlag);
4495 InFlag = Chain.getValue(1);
4498 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4501 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4502 SDValue Ops[] = { Chain, InFlag };
4504 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4505 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4507 InFlag = Chain.getValue(1);
4511 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4512 false, TailCallArguments);
4514 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
4515 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4516 NumBytes, Ins, InVals, CS);
4519 // Copy an argument into memory, being careful to do this outside the
4520 // call sequence for the call to which the argument belongs.
4522 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4523 SDValue CallSeqStart,
4524 ISD::ArgFlagsTy Flags,
4527 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4528 CallSeqStart.getNode()->getOperand(0),
4530 // The MEMCPY must go outside the CALLSEQ_START..END.
4531 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4532 CallSeqStart.getNode()->getOperand(1),
4534 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4535 NewCallSeqStart.getNode());
4536 return NewCallSeqStart;
4540 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4541 CallingConv::ID CallConv, bool isVarArg,
4542 bool isTailCall, bool IsPatchPoint,
4543 const SmallVectorImpl<ISD::OutputArg> &Outs,
4544 const SmallVectorImpl<SDValue> &OutVals,
4545 const SmallVectorImpl<ISD::InputArg> &Ins,
4546 SDLoc dl, SelectionDAG &DAG,
4547 SmallVectorImpl<SDValue> &InVals,
4548 ImmutableCallSite *CS) const {
4550 bool isELFv2ABI = Subtarget.isELFv2ABI();
4551 bool isLittleEndian = Subtarget.isLittleEndian();
4552 unsigned NumOps = Outs.size();
4554 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4555 unsigned PtrByteSize = 8;
4557 MachineFunction &MF = DAG.getMachineFunction();
4559 // Mark this function as potentially containing a function that contains a
4560 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4561 // and restoring the callers stack pointer in this functions epilog. This is
4562 // done because by tail calling the called function might overwrite the value
4563 // in this function's (MF) stack pointer stack slot 0(SP).
4564 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4565 CallConv == CallingConv::Fast)
4566 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4568 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
4569 "fastcc not supported on varargs functions");
4571 // Count how many bytes are to be pushed on the stack, including the linkage
4572 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4573 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4574 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4575 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4576 unsigned NumBytes = LinkageSize;
4577 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4578 unsigned &QFPR_idx = FPR_idx;
4580 static const MCPhysReg GPR[] = {
4581 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4582 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4584 static const MCPhysReg *FPR = GetFPR();
4586 static const MCPhysReg VR[] = {
4587 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4588 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4590 static const MCPhysReg VSRH[] = {
4591 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4592 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4595 static const MCPhysReg *QFPR = GetQFPR();
4597 const unsigned NumGPRs = array_lengthof(GPR);
4598 const unsigned NumFPRs = 13;
4599 const unsigned NumVRs = array_lengthof(VR);
4600 const unsigned NumQFPRs = NumFPRs;
4602 // When using the fast calling convention, we don't provide backing for
4603 // arguments that will be in registers.
4604 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
4606 // Add up all the space actually used.
4607 for (unsigned i = 0; i != NumOps; ++i) {
4608 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4609 EVT ArgVT = Outs[i].VT;
4610 EVT OrigVT = Outs[i].ArgVT;
4612 if (CallConv == CallingConv::Fast) {
4613 if (Flags.isByVal())
4614 NumGPRsUsed += (Flags.getByValSize()+7)/8;
4616 switch (ArgVT.getSimpleVT().SimpleTy) {
4617 default: llvm_unreachable("Unexpected ValueType for argument!");
4621 if (++NumGPRsUsed <= NumGPRs)
4629 if (++NumVRsUsed <= NumVRs)
4633 // When using QPX, this is handled like a FP register, otherwise, it
4634 // is an Altivec register.
4635 if (Subtarget.hasQPX()) {
4636 if (++NumFPRsUsed <= NumFPRs)
4639 if (++NumVRsUsed <= NumVRs)
4645 case MVT::v4f64: // QPX
4646 case MVT::v4i1: // QPX
4647 if (++NumFPRsUsed <= NumFPRs)
4653 /* Respect alignment of argument on the stack. */
4655 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4656 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4658 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4659 if (Flags.isInConsecutiveRegsLast())
4660 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4663 unsigned NumBytesActuallyUsed = NumBytes;
4665 // The prolog code of the callee may store up to 8 GPR argument registers to
4666 // the stack, allowing va_start to index over them in memory if its varargs.
4667 // Because we cannot tell if this is needed on the caller side, we have to
4668 // conservatively assume that it is needed. As such, make sure we have at
4669 // least enough stack space for the caller to store the 8 GPRs.
4670 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4671 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4673 // Tail call needs the stack to be aligned.
4674 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4675 CallConv == CallingConv::Fast)
4676 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4678 // Calculate by how many bytes the stack has to be adjusted in case of tail
4679 // call optimization.
4680 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4682 // To protect arguments on the stack from being clobbered in a tail call,
4683 // force all the loads to happen before doing any other lowering.
4685 Chain = DAG.getStackArgumentTokenFactor(Chain);
4687 // Adjust the stack pointer for the new arguments...
4688 // These operations are automatically eliminated by the prolog/epilog pass
4689 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4691 SDValue CallSeqStart = Chain;
4693 // Load the return address and frame pointer so it can be move somewhere else
4696 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4699 // Set up a copy of the stack pointer for use loading and storing any
4700 // arguments that may not fit in the registers available for argument
4702 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4704 // Figure out which arguments are going to go in registers, and which in
4705 // memory. Also, if this is a vararg function, floating point operations
4706 // must be stored to our stack, and loaded into integer regs as well, if
4707 // any integer regs are available for argument passing.
4708 unsigned ArgOffset = LinkageSize;
4710 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4711 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4713 SmallVector<SDValue, 8> MemOpChains;
4714 for (unsigned i = 0; i != NumOps; ++i) {
4715 SDValue Arg = OutVals[i];
4716 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4717 EVT ArgVT = Outs[i].VT;
4718 EVT OrigVT = Outs[i].ArgVT;
4720 // PtrOff will be used to store the current argument to the stack if a
4721 // register cannot be found for it.
4724 // We re-align the argument offset for each argument, except when using the
4725 // fast calling convention, when we need to make sure we do that only when
4726 // we'll actually use a stack slot.
4727 auto ComputePtrOff = [&]() {
4728 /* Respect alignment of argument on the stack. */
4730 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4731 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4733 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4735 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4738 if (CallConv != CallingConv::Fast) {
4741 /* Compute GPR index associated with argument offset. */
4742 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4743 GPR_idx = std::min(GPR_idx, NumGPRs);
4746 // Promote integers to 64-bit values.
4747 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4748 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4749 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4750 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4753 // FIXME memcpy is used way more than necessary. Correctness first.
4754 // Note: "by value" is code for passing a structure by value, not
4756 if (Flags.isByVal()) {
4757 // Note: Size includes alignment padding, so
4758 // struct x { short a; char b; }
4759 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4760 // These are the proper values we need for right-justifying the
4761 // aggregate in a parameter register.
4762 unsigned Size = Flags.getByValSize();
4764 // An empty aggregate parameter takes up no storage and no
4769 if (CallConv == CallingConv::Fast)
4772 // All aggregates smaller than 8 bytes must be passed right-justified.
4773 if (Size==1 || Size==2 || Size==4) {
4774 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4775 if (GPR_idx != NumGPRs) {
4776 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4777 MachinePointerInfo(), VT,
4778 false, false, false, 0);
4779 MemOpChains.push_back(Load.getValue(1));
4780 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4782 ArgOffset += PtrByteSize;
4787 if (GPR_idx == NumGPRs && Size < 8) {
4788 SDValue AddPtr = PtrOff;
4789 if (!isLittleEndian) {
4790 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4791 PtrOff.getValueType());
4792 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4794 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4797 ArgOffset += PtrByteSize;
4800 // Copy entire object into memory. There are cases where gcc-generated
4801 // code assumes it is there, even if it could be put entirely into
4802 // registers. (This is not what the doc says.)
4804 // FIXME: The above statement is likely due to a misunderstanding of the
4805 // documents. All arguments must be copied into the parameter area BY
4806 // THE CALLEE in the event that the callee takes the address of any
4807 // formal argument. That has not yet been implemented. However, it is
4808 // reasonable to use the stack area as a staging area for the register
4811 // Skip this for small aggregates, as we will use the same slot for a
4812 // right-justified copy, below.
4814 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4818 // When a register is available, pass a small aggregate right-justified.
4819 if (Size < 8 && GPR_idx != NumGPRs) {
4820 // The easiest way to get this right-justified in a register
4821 // is to copy the structure into the rightmost portion of a
4822 // local variable slot, then load the whole slot into the
4824 // FIXME: The memcpy seems to produce pretty awful code for
4825 // small aggregates, particularly for packed ones.
4826 // FIXME: It would be preferable to use the slot in the
4827 // parameter save area instead of a new local variable.
4828 SDValue AddPtr = PtrOff;
4829 if (!isLittleEndian) {
4830 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4831 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4833 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4837 // Load the slot into the register.
4838 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4839 MachinePointerInfo(),
4840 false, false, false, 0);
4841 MemOpChains.push_back(Load.getValue(1));
4842 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4844 // Done with this argument.
4845 ArgOffset += PtrByteSize;
4849 // For aggregates larger than PtrByteSize, copy the pieces of the
4850 // object that fit into registers from the parameter save area.
4851 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4852 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4853 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4854 if (GPR_idx != NumGPRs) {
4855 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4856 MachinePointerInfo(),
4857 false, false, false, 0);
4858 MemOpChains.push_back(Load.getValue(1));
4859 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4860 ArgOffset += PtrByteSize;
4862 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4869 switch (Arg.getSimpleValueType().SimpleTy) {
4870 default: llvm_unreachable("Unexpected ValueType for argument!");
4874 // These can be scalar arguments or elements of an integer array type
4875 // passed directly. Clang may use those instead of "byval" aggregate
4876 // types to avoid forcing arguments to memory unnecessarily.
4877 if (GPR_idx != NumGPRs) {
4878 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4880 if (CallConv == CallingConv::Fast)
4883 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4884 true, isTailCall, false, MemOpChains,
4885 TailCallArguments, dl);
4886 if (CallConv == CallingConv::Fast)
4887 ArgOffset += PtrByteSize;
4889 if (CallConv != CallingConv::Fast)
4890 ArgOffset += PtrByteSize;
4894 // These can be scalar arguments or elements of a float array type
4895 // passed directly. The latter are used to implement ELFv2 homogenous
4896 // float aggregates.
4898 // Named arguments go into FPRs first, and once they overflow, the
4899 // remaining arguments go into GPRs and then the parameter save area.
4900 // Unnamed arguments for vararg functions always go to GPRs and
4901 // then the parameter save area. For now, put all arguments to vararg
4902 // routines always in both locations (FPR *and* GPR or stack slot).
4903 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4904 bool NeededLoad = false;
4906 // First load the argument into the next available FPR.
4907 if (FPR_idx != NumFPRs)
4908 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4910 // Next, load the argument into GPR or stack slot if needed.
4911 if (!NeedGPROrStack)
4913 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
4914 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
4915 // once we support fp <-> gpr moves.
4917 // In the non-vararg case, this can only ever happen in the
4918 // presence of f32 array types, since otherwise we never run
4919 // out of FPRs before running out of GPRs.
4922 // Double values are always passed in a single GPR.
4923 if (Arg.getValueType() != MVT::f32) {
4924 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4926 // Non-array float values are extended and passed in a GPR.
4927 } else if (!Flags.isInConsecutiveRegs()) {
4928 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4929 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4931 // If we have an array of floats, we collect every odd element
4932 // together with its predecessor into one GPR.
4933 } else if (ArgOffset % PtrByteSize != 0) {
4935 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4936 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4937 if (!isLittleEndian)
4939 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4941 // The final element, if even, goes into the first half of a GPR.
4942 } else if (Flags.isInConsecutiveRegsLast()) {
4943 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4944 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4945 if (!isLittleEndian)
4946 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4947 DAG.getConstant(32, MVT::i32));
4949 // Non-final even elements are skipped; they will be handled
4950 // together the with subsequent argument on the next go-around.
4954 if (ArgVal.getNode())
4955 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
4957 if (CallConv == CallingConv::Fast)
4960 // Single-precision floating-point values are mapped to the
4961 // second (rightmost) word of the stack doubleword.
4962 if (Arg.getValueType() == MVT::f32 &&
4963 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4964 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4965 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4968 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4969 true, isTailCall, false, MemOpChains,
4970 TailCallArguments, dl);
4974 // When passing an array of floats, the array occupies consecutive
4975 // space in the argument area; only round up to the next doubleword
4976 // at the end of the array. Otherwise, each float takes 8 bytes.
4977 if (CallConv != CallingConv::Fast || NeededLoad) {
4978 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4979 Flags.isInConsecutiveRegs()) ? 4 : 8;
4980 if (Flags.isInConsecutiveRegsLast())
4981 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4991 if (!Subtarget.hasQPX()) {
4992 // These can be scalar arguments or elements of a vector array type
4993 // passed directly. The latter are used to implement ELFv2 homogenous
4994 // vector aggregates.
4996 // For a varargs call, named arguments go into VRs or on the stack as
4997 // usual; unnamed arguments always go to the stack or the corresponding
4998 // GPRs when within range. For now, we always put the value in both
4999 // locations (or even all three).
5001 // We could elide this store in the case where the object fits
5002 // entirely in R registers. Maybe later.
5003 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5004 MachinePointerInfo(), false, false, 0);
5005 MemOpChains.push_back(Store);
5006 if (VR_idx != NumVRs) {
5007 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5008 MachinePointerInfo(),
5009 false, false, false, 0);
5010 MemOpChains.push_back(Load.getValue(1));
5012 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5013 Arg.getSimpleValueType() == MVT::v2i64) ?
5014 VSRH[VR_idx] : VR[VR_idx];
5017 RegsToPass.push_back(std::make_pair(VReg, Load));
5020 for (unsigned i=0; i<16; i+=PtrByteSize) {
5021 if (GPR_idx == NumGPRs)
5023 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5024 DAG.getConstant(i, PtrVT));
5025 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5026 false, false, false, 0);
5027 MemOpChains.push_back(Load.getValue(1));
5028 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5033 // Non-varargs Altivec params go into VRs or on the stack.
5034 if (VR_idx != NumVRs) {
5035 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5036 Arg.getSimpleValueType() == MVT::v2i64) ?
5037 VSRH[VR_idx] : VR[VR_idx];
5040 RegsToPass.push_back(std::make_pair(VReg, Arg));
5042 if (CallConv == CallingConv::Fast)
5045 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5046 true, isTailCall, true, MemOpChains,
5047 TailCallArguments, dl);
5048 if (CallConv == CallingConv::Fast)
5052 if (CallConv != CallingConv::Fast)
5057 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
5058 "Invalid QPX parameter type");
5063 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;
5065 // We could elide this store in the case where the object fits
5066 // entirely in R registers. Maybe later.
5067 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5068 MachinePointerInfo(), false, false, 0);
5069 MemOpChains.push_back(Store);
5070 if (QFPR_idx != NumQFPRs) {
5071 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl,
5072 Store, PtrOff, MachinePointerInfo(),
5073 false, false, false, 0);
5074 MemOpChains.push_back(Load.getValue(1));
5075 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Load));
5077 ArgOffset += (IsF32 ? 16 : 32);
5078 for (unsigned i = 0; i < (IsF32 ? 16U : 32U); i += PtrByteSize) {
5079 if (GPR_idx == NumGPRs)
5081 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5082 DAG.getConstant(i, PtrVT));
5083 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5084 false, false, false, 0);
5085 MemOpChains.push_back(Load.getValue(1));
5086 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5091 // Non-varargs QPX params go into registers or on the stack.
5092 if (QFPR_idx != NumQFPRs) {
5093 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Arg));
5095 if (CallConv == CallingConv::Fast)
5098 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5099 true, isTailCall, true, MemOpChains,
5100 TailCallArguments, dl);
5101 if (CallConv == CallingConv::Fast)
5102 ArgOffset += (IsF32 ? 16 : 32);
5105 if (CallConv != CallingConv::Fast)
5106 ArgOffset += (IsF32 ? 16 : 32);
5112 assert(NumBytesActuallyUsed == ArgOffset);
5113 (void)NumBytesActuallyUsed;
5115 if (!MemOpChains.empty())
5116 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5118 // Check if this is an indirect call (MTCTR/BCTRL).
5119 // See PrepareCall() for more information about calls through function
5120 // pointers in the 64-bit SVR4 ABI.
5121 if (!isTailCall && !IsPatchPoint &&
5122 !isFunctionGlobalAddress(Callee) &&
5123 !isa<ExternalSymbolSDNode>(Callee)) {
5124 // Load r2 into a virtual register and store it to the TOC save area.
5125 setUsesTOCBasePtr(DAG);
5126 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
5127 // TOC save area offset.
5128 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5129 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
5130 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5131 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr,
5132 MachinePointerInfo::getStack(TOCSaveOffset),
5134 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
5135 // This does not mean the MTCTR instruction must use R12; it's easier
5136 // to model this as an extra parameter, so do that.
5137 if (isELFv2ABI && !IsPatchPoint)
5138 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
5141 // Build a sequence of copy-to-reg nodes chained together with token chain
5142 // and flag operands which copy the outgoing args into the appropriate regs.
5144 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5145 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5146 RegsToPass[i].second, InFlag);
5147 InFlag = Chain.getValue(1);
5151 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
5152 FPOp, true, TailCallArguments);
5154 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
5155 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5156 NumBytes, Ins, InVals, CS);
5160 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
5161 CallingConv::ID CallConv, bool isVarArg,
5162 bool isTailCall, bool IsPatchPoint,
5163 const SmallVectorImpl<ISD::OutputArg> &Outs,
5164 const SmallVectorImpl<SDValue> &OutVals,
5165 const SmallVectorImpl<ISD::InputArg> &Ins,
5166 SDLoc dl, SelectionDAG &DAG,
5167 SmallVectorImpl<SDValue> &InVals,
5168 ImmutableCallSite *CS) const {
5170 unsigned NumOps = Outs.size();
5172 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5173 bool isPPC64 = PtrVT == MVT::i64;
5174 unsigned PtrByteSize = isPPC64 ? 8 : 4;
5176 MachineFunction &MF = DAG.getMachineFunction();
5178 // Mark this function as potentially containing a function that contains a
5179 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5180 // and restoring the callers stack pointer in this functions epilog. This is
5181 // done because by tail calling the called function might overwrite the value
5182 // in this function's (MF) stack pointer stack slot 0(SP).
5183 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5184 CallConv == CallingConv::Fast)
5185 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5187 // Count how many bytes are to be pushed on the stack, including the linkage
5188 // area, and parameter passing area. We start with 24/48 bytes, which is
5189 // prereserved space for [SP][CR][LR][3 x unused].
5190 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5191 unsigned NumBytes = LinkageSize;
5193 // Add up all the space actually used.
5194 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
5195 // they all go in registers, but we must reserve stack space for them for
5196 // possible use by the caller. In varargs or 64-bit calls, parameters are
5197 // assigned stack space in order, with padding so Altivec parameters are
5199 unsigned nAltivecParamsAtEnd = 0;
5200 for (unsigned i = 0; i != NumOps; ++i) {
5201 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5202 EVT ArgVT = Outs[i].VT;
5203 // Varargs Altivec parameters are padded to a 16 byte boundary.
5204 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
5205 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
5206 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
5207 if (!isVarArg && !isPPC64) {
5208 // Non-varargs Altivec parameters go after all the non-Altivec
5209 // parameters; handle those later so we know how much padding we need.
5210 nAltivecParamsAtEnd++;
5213 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
5214 NumBytes = ((NumBytes+15)/16)*16;
5216 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
5219 // Allow for Altivec parameters at the end, if needed.
5220 if (nAltivecParamsAtEnd) {
5221 NumBytes = ((NumBytes+15)/16)*16;
5222 NumBytes += 16*nAltivecParamsAtEnd;
5225 // The prolog code of the callee may store up to 8 GPR argument registers to
5226 // the stack, allowing va_start to index over them in memory if its varargs.
5227 // Because we cannot tell if this is needed on the caller side, we have to
5228 // conservatively assume that it is needed. As such, make sure we have at
5229 // least enough stack space for the caller to store the 8 GPRs.
5230 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
5232 // Tail call needs the stack to be aligned.
5233 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5234 CallConv == CallingConv::Fast)
5235 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
5237 // Calculate by how many bytes the stack has to be adjusted in case of tail
5238 // call optimization.
5239 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5241 // To protect arguments on the stack from being clobbered in a tail call,
5242 // force all the loads to happen before doing any other lowering.
5244 Chain = DAG.getStackArgumentTokenFactor(Chain);
5246 // Adjust the stack pointer for the new arguments...
5247 // These operations are automatically eliminated by the prolog/epilog pass
5248 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
5250 SDValue CallSeqStart = Chain;
5252 // Load the return address and frame pointer so it can be move somewhere else
5255 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
5258 // Set up a copy of the stack pointer for use loading and storing any
5259 // arguments that may not fit in the registers available for argument
5263 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5265 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5267 // Figure out which arguments are going to go in registers, and which in
5268 // memory. Also, if this is a vararg function, floating point operations
5269 // must be stored to our stack, and loaded into integer regs as well, if
5270 // any integer regs are available for argument passing.
5271 unsigned ArgOffset = LinkageSize;
5272 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5274 static const MCPhysReg GPR_32[] = { // 32-bit registers.
5275 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
5276 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
5278 static const MCPhysReg GPR_64[] = { // 64-bit registers.
5279 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5280 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5282 static const MCPhysReg *FPR = GetFPR();
5284 static const MCPhysReg VR[] = {
5285 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5286 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5288 const unsigned NumGPRs = array_lengthof(GPR_32);
5289 const unsigned NumFPRs = 13;
5290 const unsigned NumVRs = array_lengthof(VR);
5292 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
5294 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5295 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5297 SmallVector<SDValue, 8> MemOpChains;
5298 for (unsigned i = 0; i != NumOps; ++i) {
5299 SDValue Arg = OutVals[i];
5300 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5302 // PtrOff will be used to store the current argument to the stack if a
5303 // register cannot be found for it.
5306 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
5308 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5310 // On PPC64, promote integers to 64-bit values.
5311 if (isPPC64 && Arg.getValueType() == MVT::i32) {
5312 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
5313 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5314 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
5317 // FIXME memcpy is used way more than necessary. Correctness first.
5318 // Note: "by value" is code for passing a structure by value, not
5320 if (Flags.isByVal()) {
5321 unsigned Size = Flags.getByValSize();
5322 // Very small objects are passed right-justified. Everything else is
5323 // passed left-justified.
5324 if (Size==1 || Size==2) {
5325 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
5326 if (GPR_idx != NumGPRs) {
5327 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5328 MachinePointerInfo(), VT,
5329 false, false, false, 0);
5330 MemOpChains.push_back(Load.getValue(1));
5331 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5333 ArgOffset += PtrByteSize;
5335 SDValue Const = DAG.getConstant(PtrByteSize - Size,
5336 PtrOff.getValueType());
5337 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5338 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5341 ArgOffset += PtrByteSize;
5345 // Copy entire object into memory. There are cases where gcc-generated
5346 // code assumes it is there, even if it could be put entirely into
5347 // registers. (This is not what the doc says.)
5348 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5352 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5353 // copy the pieces of the object that fit into registers from the
5354 // parameter save area.
5355 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5356 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
5357 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5358 if (GPR_idx != NumGPRs) {
5359 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5360 MachinePointerInfo(),
5361 false, false, false, 0);
5362 MemOpChains.push_back(Load.getValue(1));
5363 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5364 ArgOffset += PtrByteSize;
5366 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5373 switch (Arg.getSimpleValueType().SimpleTy) {
5374 default: llvm_unreachable("Unexpected ValueType for argument!");
5378 if (GPR_idx != NumGPRs) {
5379 if (Arg.getValueType() == MVT::i1)
5380 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5382 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5384 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5385 isPPC64, isTailCall, false, MemOpChains,
5386 TailCallArguments, dl);
5388 ArgOffset += PtrByteSize;
5392 if (FPR_idx != NumFPRs) {
5393 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5396 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5397 MachinePointerInfo(), false, false, 0);
5398 MemOpChains.push_back(Store);
5400 // Float varargs are always shadowed in available integer registers
5401 if (GPR_idx != NumGPRs) {
5402 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5403 MachinePointerInfo(), false, false,
5405 MemOpChains.push_back(Load.getValue(1));
5406 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5408 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5409 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
5410 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5411 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5412 MachinePointerInfo(),
5413 false, false, false, 0);
5414 MemOpChains.push_back(Load.getValue(1));
5415 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5418 // If we have any FPRs remaining, we may also have GPRs remaining.
5419 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5421 if (GPR_idx != NumGPRs)
5423 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5424 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5428 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5429 isPPC64, isTailCall, false, MemOpChains,
5430 TailCallArguments, dl);
5434 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5441 // These go aligned on the stack, or in the corresponding R registers
5442 // when within range. The Darwin PPC ABI doc claims they also go in
5443 // V registers; in fact gcc does this only for arguments that are
5444 // prototyped, not for those that match the ... We do it for all
5445 // arguments, seems to work.
5446 while (ArgOffset % 16 !=0) {
5447 ArgOffset += PtrByteSize;
5448 if (GPR_idx != NumGPRs)
5451 // We could elide this store in the case where the object fits
5452 // entirely in R registers. Maybe later.
5453 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5454 DAG.getConstant(ArgOffset, PtrVT));
5455 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5456 MachinePointerInfo(), false, false, 0);
5457 MemOpChains.push_back(Store);
5458 if (VR_idx != NumVRs) {
5459 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5460 MachinePointerInfo(),
5461 false, false, false, 0);
5462 MemOpChains.push_back(Load.getValue(1));
5463 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5466 for (unsigned i=0; i<16; i+=PtrByteSize) {
5467 if (GPR_idx == NumGPRs)
5469 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5470 DAG.getConstant(i, PtrVT));
5471 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5472 false, false, false, 0);
5473 MemOpChains.push_back(Load.getValue(1));
5474 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5479 // Non-varargs Altivec params generally go in registers, but have
5480 // stack space allocated at the end.
5481 if (VR_idx != NumVRs) {
5482 // Doesn't have GPR space allocated.
5483 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5484 } else if (nAltivecParamsAtEnd==0) {
5485 // We are emitting Altivec params in order.
5486 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5487 isPPC64, isTailCall, true, MemOpChains,
5488 TailCallArguments, dl);
5494 // If all Altivec parameters fit in registers, as they usually do,
5495 // they get stack space following the non-Altivec parameters. We
5496 // don't track this here because nobody below needs it.
5497 // If there are more Altivec parameters than fit in registers emit
5499 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5501 // Offset is aligned; skip 1st 12 params which go in V registers.
5502 ArgOffset = ((ArgOffset+15)/16)*16;
5504 for (unsigned i = 0; i != NumOps; ++i) {
5505 SDValue Arg = OutVals[i];
5506 EVT ArgType = Outs[i].VT;
5507 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5508 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5511 // We are emitting Altivec params in order.
5512 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5513 isPPC64, isTailCall, true, MemOpChains,
5514 TailCallArguments, dl);
5521 if (!MemOpChains.empty())
5522 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5524 // On Darwin, R12 must contain the address of an indirect callee. This does
5525 // not mean the MTCTR instruction must use R12; it's easier to model this as
5526 // an extra parameter, so do that.
5528 !isFunctionGlobalAddress(Callee) &&
5529 !isa<ExternalSymbolSDNode>(Callee) &&
5530 !isBLACompatibleAddress(Callee, DAG))
5531 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5532 PPC::R12), Callee));
5534 // Build a sequence of copy-to-reg nodes chained together with token chain
5535 // and flag operands which copy the outgoing args into the appropriate regs.
5537 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5538 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5539 RegsToPass[i].second, InFlag);
5540 InFlag = Chain.getValue(1);
5544 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5545 FPOp, true, TailCallArguments);
5547 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
5548 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5549 NumBytes, Ins, InVals, CS);
5553 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5554 MachineFunction &MF, bool isVarArg,
5555 const SmallVectorImpl<ISD::OutputArg> &Outs,
5556 LLVMContext &Context) const {
5557 SmallVector<CCValAssign, 16> RVLocs;
5558 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5559 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5563 PPCTargetLowering::LowerReturn(SDValue Chain,
5564 CallingConv::ID CallConv, bool isVarArg,
5565 const SmallVectorImpl<ISD::OutputArg> &Outs,
5566 const SmallVectorImpl<SDValue> &OutVals,
5567 SDLoc dl, SelectionDAG &DAG) const {
5569 SmallVector<CCValAssign, 16> RVLocs;
5570 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5572 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5575 SmallVector<SDValue, 4> RetOps(1, Chain);
5577 // Copy the result values into the output registers.
5578 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5579 CCValAssign &VA = RVLocs[i];
5580 assert(VA.isRegLoc() && "Can only return in registers!");
5582 SDValue Arg = OutVals[i];
5584 switch (VA.getLocInfo()) {
5585 default: llvm_unreachable("Unknown loc info!");
5586 case CCValAssign::Full: break;
5587 case CCValAssign::AExt:
5588 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5590 case CCValAssign::ZExt:
5591 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5593 case CCValAssign::SExt:
5594 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5598 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5599 Flag = Chain.getValue(1);
5600 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5603 RetOps[0] = Chain; // Update chain.
5605 // Add the flag if we have it.
5607 RetOps.push_back(Flag);
5609 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5612 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5613 const PPCSubtarget &Subtarget) const {
5614 // When we pop the dynamic allocation we need to restore the SP link.
5617 // Get the corect type for pointers.
5618 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5620 // Construct the stack pointer operand.
5621 bool isPPC64 = Subtarget.isPPC64();
5622 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5623 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5625 // Get the operands for the STACKRESTORE.
5626 SDValue Chain = Op.getOperand(0);
5627 SDValue SaveSP = Op.getOperand(1);
5629 // Load the old link SP.
5630 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5631 MachinePointerInfo(),
5632 false, false, false, 0);
5634 // Restore the stack pointer.
5635 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5637 // Store the old link SP.
5638 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5645 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5646 MachineFunction &MF = DAG.getMachineFunction();
5647 bool isPPC64 = Subtarget.isPPC64();
5648 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5650 // Get current frame pointer save index. The users of this index will be
5651 // primarily DYNALLOC instructions.
5652 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5653 int RASI = FI->getReturnAddrSaveIndex();
5655 // If the frame pointer save index hasn't been defined yet.
5657 // Find out what the fix offset of the frame pointer save area.
5658 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset();
5659 // Allocate the frame index for frame pointer save area.
5660 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5662 FI->setReturnAddrSaveIndex(RASI);
5664 return DAG.getFrameIndex(RASI, PtrVT);
5668 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5669 MachineFunction &MF = DAG.getMachineFunction();
5670 bool isPPC64 = Subtarget.isPPC64();
5671 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5673 // Get current frame pointer save index. The users of this index will be
5674 // primarily DYNALLOC instructions.
5675 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5676 int FPSI = FI->getFramePointerSaveIndex();
5678 // If the frame pointer save index hasn't been defined yet.
5680 // Find out what the fix offset of the frame pointer save area.
5681 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset();
5682 // Allocate the frame index for frame pointer save area.
5683 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5685 FI->setFramePointerSaveIndex(FPSI);
5687 return DAG.getFrameIndex(FPSI, PtrVT);
5690 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5692 const PPCSubtarget &Subtarget) const {
5694 SDValue Chain = Op.getOperand(0);
5695 SDValue Size = Op.getOperand(1);
5698 // Get the corect type for pointers.
5699 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5701 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5702 DAG.getConstant(0, PtrVT), Size);
5703 // Construct a node for the frame pointer save index.
5704 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5705 // Build a DYNALLOC node.
5706 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5707 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5708 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5711 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5712 SelectionDAG &DAG) const {
5714 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5715 DAG.getVTList(MVT::i32, MVT::Other),
5716 Op.getOperand(0), Op.getOperand(1));
5719 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5720 SelectionDAG &DAG) const {
5722 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5723 Op.getOperand(0), Op.getOperand(1));
5726 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5727 if (Op.getValueType().isVector())
5728 return LowerVectorLoad(Op, DAG);
5730 assert(Op.getValueType() == MVT::i1 &&
5731 "Custom lowering only for i1 loads");
5733 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5736 LoadSDNode *LD = cast<LoadSDNode>(Op);
5738 SDValue Chain = LD->getChain();
5739 SDValue BasePtr = LD->getBasePtr();
5740 MachineMemOperand *MMO = LD->getMemOperand();
5742 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5743 BasePtr, MVT::i8, MMO);
5744 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5746 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5747 return DAG.getMergeValues(Ops, dl);
5750 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5751 if (Op.getOperand(1).getValueType().isVector())
5752 return LowerVectorStore(Op, DAG);
5754 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5755 "Custom lowering only for i1 stores");
5757 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5760 StoreSDNode *ST = cast<StoreSDNode>(Op);
5762 SDValue Chain = ST->getChain();
5763 SDValue BasePtr = ST->getBasePtr();
5764 SDValue Value = ST->getValue();
5765 MachineMemOperand *MMO = ST->getMemOperand();
5767 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5768 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5771 // FIXME: Remove this once the ANDI glue bug is fixed:
5772 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5773 assert(Op.getValueType() == MVT::i1 &&
5774 "Custom lowering only for i1 results");
5777 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5781 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5783 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5784 // Not FP? Not a fsel.
5785 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5786 !Op.getOperand(2).getValueType().isFloatingPoint())
5789 // We might be able to do better than this under some circumstances, but in
5790 // general, fsel-based lowering of select is a finite-math-only optimization.
5791 // For more information, see section F.3 of the 2.06 ISA specification.
5792 if (!DAG.getTarget().Options.NoInfsFPMath ||
5793 !DAG.getTarget().Options.NoNaNsFPMath)
5796 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5798 EVT ResVT = Op.getValueType();
5799 EVT CmpVT = Op.getOperand(0).getValueType();
5800 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5801 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5804 // If the RHS of the comparison is a 0.0, we don't need to do the
5805 // subtraction at all.
5807 if (isFloatingPointZero(RHS))
5809 default: break; // SETUO etc aren't handled by fsel.
5813 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5814 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5815 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5816 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5817 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5818 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5819 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5822 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5825 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5826 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5827 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5830 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5833 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5834 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5835 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5836 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5841 default: break; // SETUO etc aren't handled by fsel.
5845 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5846 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5847 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5848 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5849 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5850 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5851 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5852 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5855 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5856 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5857 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5858 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5861 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5862 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5863 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5864 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5867 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5868 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5869 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5870 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5873 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5874 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5875 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5876 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5881 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
5884 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5885 SDValue Src = Op.getOperand(0);
5886 if (Src.getValueType() == MVT::f32)
5887 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5890 switch (Op.getSimpleValueType().SimpleTy) {
5891 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5894 Op.getOpcode() == ISD::FP_TO_SINT
5896 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
5900 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5901 "i64 FP_TO_UINT is supported only with FPCVT");
5902 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5908 // Convert the FP value to an int value through memory.
5909 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5910 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5911 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5912 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5913 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5915 // Emit a store to the stack slot.
5918 MachineFunction &MF = DAG.getMachineFunction();
5919 MachineMemOperand *MMO =
5920 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5921 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5922 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5923 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5925 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5926 MPI, false, false, 0);
5928 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5930 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5931 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5932 DAG.getConstant(4, FIPtr.getValueType()));
5933 MPI = MPI.getWithOffset(4);
5941 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5944 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5946 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5947 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5951 // We're trying to insert a regular store, S, and then a load, L. If the
5952 // incoming value, O, is a load, we might just be able to have our load use the
5953 // address used by O. However, we don't know if anything else will store to
5954 // that address before we can load from it. To prevent this situation, we need
5955 // to insert our load, L, into the chain as a peer of O. To do this, we give L
5956 // the same chain operand as O, we create a token factor from the chain results
5957 // of O and L, and we replace all uses of O's chain result with that token
5958 // factor (see spliceIntoChain below for this last part).
5959 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
5962 ISD::LoadExtType ET) const {
5964 if (ET == ISD::NON_EXTLOAD &&
5965 (Op.getOpcode() == ISD::FP_TO_UINT ||
5966 Op.getOpcode() == ISD::FP_TO_SINT) &&
5967 isOperationLegalOrCustom(Op.getOpcode(),
5968 Op.getOperand(0).getValueType())) {
5970 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5974 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
5975 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
5976 LD->isNonTemporal())
5978 if (LD->getMemoryVT() != MemVT)
5981 RLI.Ptr = LD->getBasePtr();
5982 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
5983 assert(LD->getAddressingMode() == ISD::PRE_INC &&
5984 "Non-pre-inc AM on PPC?");
5985 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
5989 RLI.Chain = LD->getChain();
5990 RLI.MPI = LD->getPointerInfo();
5991 RLI.IsInvariant = LD->isInvariant();
5992 RLI.Alignment = LD->getAlignment();
5993 RLI.AAInfo = LD->getAAInfo();
5994 RLI.Ranges = LD->getRanges();
5996 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
6000 // Given the head of the old chain, ResChain, insert a token factor containing
6001 // it and NewResChain, and make users of ResChain now be users of that token
6003 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
6004 SDValue NewResChain,
6005 SelectionDAG &DAG) const {
6009 SDLoc dl(NewResChain);
6011 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6012 NewResChain, DAG.getUNDEF(MVT::Other));
6013 assert(TF.getNode() != NewResChain.getNode() &&
6014 "A new TF really is required here");
6016 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
6017 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
6020 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
6021 SelectionDAG &DAG) const {
6024 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) {
6025 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64)
6028 SDValue Value = Op.getOperand(0);
6029 // The values are now known to be -1 (false) or 1 (true). To convert this
6030 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
6031 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
6032 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
6034 SDValue FPHalfs = DAG.getConstantFP(0.5, MVT::f64);
6035 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6036 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
6038 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
6040 if (Op.getValueType() != MVT::v4f64)
6041 Value = DAG.getNode(ISD::FP_ROUND, dl,
6042 Op.getValueType(), Value, DAG.getIntPtrConstant(1));
6046 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
6047 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
6050 if (Op.getOperand(0).getValueType() == MVT::i1)
6051 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
6052 DAG.getConstantFP(1.0, Op.getValueType()),
6053 DAG.getConstantFP(0.0, Op.getValueType()));
6055 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
6056 "UINT_TO_FP is supported only with FPCVT");
6058 // If we have FCFIDS, then use it when converting to single-precision.
6059 // Otherwise, convert to double-precision and then round.
6060 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6061 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
6063 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
6065 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6069 if (Op.getOperand(0).getValueType() == MVT::i64) {
6070 SDValue SINT = Op.getOperand(0);
6071 // When converting to single-precision, we actually need to convert
6072 // to double-precision first and then round to single-precision.
6073 // To avoid double-rounding effects during that operation, we have
6074 // to prepare the input operand. Bits that might be truncated when
6075 // converting to double-precision are replaced by a bit that won't
6076 // be lost at this stage, but is below the single-precision rounding
6079 // However, if -enable-unsafe-fp-math is in effect, accept double
6080 // rounding to avoid the extra overhead.
6081 if (Op.getValueType() == MVT::f32 &&
6082 !Subtarget.hasFPCVT() &&
6083 !DAG.getTarget().Options.UnsafeFPMath) {
6085 // Twiddle input to make sure the low 11 bits are zero. (If this
6086 // is the case, we are guaranteed the value will fit into the 53 bit
6087 // mantissa of an IEEE double-precision value without rounding.)
6088 // If any of those low 11 bits were not zero originally, make sure
6089 // bit 12 (value 2048) is set instead, so that the final rounding
6090 // to single-precision gets the correct result.
6091 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6092 SINT, DAG.getConstant(2047, MVT::i64));
6093 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
6094 Round, DAG.getConstant(2047, MVT::i64));
6095 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
6096 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6097 Round, DAG.getConstant(-2048, MVT::i64));
6099 // However, we cannot use that value unconditionally: if the magnitude
6100 // of the input value is small, the bit-twiddling we did above might
6101 // end up visibly changing the output. Fortunately, in that case, we
6102 // don't need to twiddle bits since the original input will convert
6103 // exactly to double-precision floating-point already. Therefore,
6104 // construct a conditional to use the original value if the top 11
6105 // bits are all sign-bit copies, and use the rounded value computed
6107 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
6108 SINT, DAG.getConstant(53, MVT::i32));
6109 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
6110 Cond, DAG.getConstant(1, MVT::i64));
6111 Cond = DAG.getSetCC(dl, MVT::i32,
6112 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
6114 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
6120 MachineFunction &MF = DAG.getMachineFunction();
6121 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
6122 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6123 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6125 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6126 } else if (Subtarget.hasLFIWAX() &&
6127 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
6128 MachineMemOperand *MMO =
6129 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6130 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6131 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6132 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
6133 DAG.getVTList(MVT::f64, MVT::Other),
6134 Ops, MVT::i32, MMO);
6135 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6136 } else if (Subtarget.hasFPCVT() &&
6137 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
6138 MachineMemOperand *MMO =
6139 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6140 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6141 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6142 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
6143 DAG.getVTList(MVT::f64, MVT::Other),
6144 Ops, MVT::i32, MMO);
6145 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6146 } else if (((Subtarget.hasLFIWAX() &&
6147 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
6148 (Subtarget.hasFPCVT() &&
6149 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
6150 SINT.getOperand(0).getValueType() == MVT::i32) {
6151 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6152 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
6154 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6155 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6158 DAG.getStore(DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
6159 MachinePointerInfo::getFixedStack(FrameIdx),
6162 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6163 "Expected an i32 store");
6167 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
6170 MachineMemOperand *MMO =
6171 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6172 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6173 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6174 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
6175 PPCISD::LFIWZX : PPCISD::LFIWAX,
6176 dl, DAG.getVTList(MVT::f64, MVT::Other),
6177 Ops, MVT::i32, MMO);
6179 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
6181 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
6183 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6184 FP = DAG.getNode(ISD::FP_ROUND, dl,
6185 MVT::f32, FP, DAG.getIntPtrConstant(0));
6189 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
6190 "Unhandled INT_TO_FP type in custom expander!");
6191 // Since we only generate this in 64-bit mode, we can take advantage of
6192 // 64-bit registers. In particular, sign extend the input value into the
6193 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
6194 // then lfd it and fcfid it.
6195 MachineFunction &MF = DAG.getMachineFunction();
6196 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6197 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
6200 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
6203 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
6205 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6206 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6208 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
6209 MachinePointerInfo::getFixedStack(FrameIdx),
6212 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6213 "Expected an i32 store");
6217 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
6221 MachineMemOperand *MMO =
6222 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6223 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6224 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6225 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
6226 PPCISD::LFIWZX : PPCISD::LFIWAX,
6227 dl, DAG.getVTList(MVT::f64, MVT::Other),
6228 Ops, MVT::i32, MMO);
6230 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
6232 assert(Subtarget.isPPC64() &&
6233 "i32->FP without LFIWAX supported only on PPC64");
6235 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
6236 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6238 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
6241 // STD the extended value into the stack slot.
6242 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
6243 MachinePointerInfo::getFixedStack(FrameIdx),
6246 // Load the value as a double.
6247 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
6248 MachinePointerInfo::getFixedStack(FrameIdx),
6249 false, false, false, 0);
6252 // FCFID it and return it.
6253 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
6254 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6255 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
6259 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
6260 SelectionDAG &DAG) const {
6263 The rounding mode is in bits 30:31 of FPSR, and has the following
6270 FLT_ROUNDS, on the other hand, expects the following:
6277 To perform the conversion, we do:
6278 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
6281 MachineFunction &MF = DAG.getMachineFunction();
6282 EVT VT = Op.getValueType();
6283 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
6285 // Save FP Control Word to register
6287 MVT::f64, // return register
6288 MVT::Glue // unused in this context
6290 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
6292 // Save FP register to stack slot
6293 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
6294 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
6295 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
6296 StackSlot, MachinePointerInfo(), false, false,0);
6298 // Load FP Control Word from low 32 bits of stack slot.
6299 SDValue Four = DAG.getConstant(4, PtrVT);
6300 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
6301 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
6302 false, false, false, 0);
6304 // Transform as necessary
6306 DAG.getNode(ISD::AND, dl, MVT::i32,
6307 CWD, DAG.getConstant(3, MVT::i32));
6309 DAG.getNode(ISD::SRL, dl, MVT::i32,
6310 DAG.getNode(ISD::AND, dl, MVT::i32,
6311 DAG.getNode(ISD::XOR, dl, MVT::i32,
6312 CWD, DAG.getConstant(3, MVT::i32)),
6313 DAG.getConstant(3, MVT::i32)),
6314 DAG.getConstant(1, MVT::i32));
6317 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
6319 return DAG.getNode((VT.getSizeInBits() < 16 ?
6320 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6323 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6324 EVT VT = Op.getValueType();
6325 unsigned BitWidth = VT.getSizeInBits();
6327 assert(Op.getNumOperands() == 3 &&
6328 VT == Op.getOperand(1).getValueType() &&
6331 // Expand into a bunch of logical ops. Note that these ops
6332 // depend on the PPC behavior for oversized shift amounts.
6333 SDValue Lo = Op.getOperand(0);
6334 SDValue Hi = Op.getOperand(1);
6335 SDValue Amt = Op.getOperand(2);
6336 EVT AmtVT = Amt.getValueType();
6338 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6339 DAG.getConstant(BitWidth, AmtVT), Amt);
6340 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
6341 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
6342 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
6343 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6344 DAG.getConstant(-BitWidth, AmtVT));
6345 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
6346 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6347 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
6348 SDValue OutOps[] = { OutLo, OutHi };
6349 return DAG.getMergeValues(OutOps, dl);
6352 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6353 EVT VT = Op.getValueType();
6355 unsigned BitWidth = VT.getSizeInBits();
6356 assert(Op.getNumOperands() == 3 &&
6357 VT == Op.getOperand(1).getValueType() &&
6360 // Expand into a bunch of logical ops. Note that these ops
6361 // depend on the PPC behavior for oversized shift amounts.
6362 SDValue Lo = Op.getOperand(0);
6363 SDValue Hi = Op.getOperand(1);
6364 SDValue Amt = Op.getOperand(2);
6365 EVT AmtVT = Amt.getValueType();
6367 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6368 DAG.getConstant(BitWidth, AmtVT), Amt);
6369 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6370 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6371 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6372 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6373 DAG.getConstant(-BitWidth, AmtVT));
6374 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
6375 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6376 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
6377 SDValue OutOps[] = { OutLo, OutHi };
6378 return DAG.getMergeValues(OutOps, dl);
6381 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6383 EVT VT = Op.getValueType();
6384 unsigned BitWidth = VT.getSizeInBits();
6385 assert(Op.getNumOperands() == 3 &&
6386 VT == Op.getOperand(1).getValueType() &&
6389 // Expand into a bunch of logical ops, followed by a select_cc.
6390 SDValue Lo = Op.getOperand(0);
6391 SDValue Hi = Op.getOperand(1);
6392 SDValue Amt = Op.getOperand(2);
6393 EVT AmtVT = Amt.getValueType();
6395 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6396 DAG.getConstant(BitWidth, AmtVT), Amt);
6397 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6398 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6399 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6400 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6401 DAG.getConstant(-BitWidth, AmtVT));
6402 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
6403 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
6404 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
6405 Tmp4, Tmp6, ISD::SETLE);
6406 SDValue OutOps[] = { OutLo, OutHi };
6407 return DAG.getMergeValues(OutOps, dl);
6410 //===----------------------------------------------------------------------===//
6411 // Vector related lowering.
6414 /// BuildSplatI - Build a canonical splati of Val with an element size of
6415 /// SplatSize. Cast the result to VT.
6416 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6417 SelectionDAG &DAG, SDLoc dl) {
6418 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
6420 static const EVT VTys[] = { // canonical VT to use for each size.
6421 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6424 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
6426 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
6430 EVT CanonicalVT = VTys[SplatSize-1];
6432 // Build a canonical splat for this value.
6433 SDValue Elt = DAG.getConstant(Val, MVT::i32);
6434 SmallVector<SDValue, 8> Ops;
6435 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
6436 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
6437 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
6440 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
6441 /// specified intrinsic ID.
6442 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6443 SelectionDAG &DAG, SDLoc dl,
6444 EVT DestVT = MVT::Other) {
6445 if (DestVT == MVT::Other) DestVT = Op.getValueType();
6446 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6447 DAG.getConstant(IID, MVT::i32), Op);
6450 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
6451 /// specified intrinsic ID.
6452 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6453 SelectionDAG &DAG, SDLoc dl,
6454 EVT DestVT = MVT::Other) {
6455 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
6456 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6457 DAG.getConstant(IID, MVT::i32), LHS, RHS);
6460 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
6461 /// specified intrinsic ID.
6462 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6463 SDValue Op2, SelectionDAG &DAG,
6464 SDLoc dl, EVT DestVT = MVT::Other) {
6465 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6466 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6467 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
6471 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6472 /// amount. The result has the specified value type.
6473 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6474 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6475 // Force LHS/RHS to be the right type.
6476 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6477 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6480 for (unsigned i = 0; i != 16; ++i)
6482 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6483 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6486 // If this is a case we can't handle, return null and let the default
6487 // expansion code take care of it. If we CAN select this case, and if it
6488 // selects to a single instruction, return Op. Otherwise, if we can codegen
6489 // this case more efficiently than a constant pool load, lower it to the
6490 // sequence of ops that should be used.
6491 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6492 SelectionDAG &DAG) const {
6494 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6495 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6497 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) {
6498 // We first build an i32 vector, load it into a QPX register,
6499 // then convert it to a floating-point vector and compare it
6500 // to a zero vector to get the boolean result.
6501 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6502 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6503 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FrameIdx);
6504 EVT PtrVT = getPointerTy();
6505 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6507 assert(BVN->getNumOperands() == 4 &&
6508 "BUILD_VECTOR for v4i1 does not have 4 operands");
6510 bool IsConst = true;
6511 for (unsigned i = 0; i < 4; ++i) {
6512 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6513 if (!isa<ConstantSDNode>(BVN->getOperand(i))) {
6521 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), 1.0);
6523 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), -1.0);
6525 SmallVector<Constant*, 4> CV(4, NegOne);
6526 for (unsigned i = 0; i < 4; ++i) {
6527 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF)
6528 CV[i] = UndefValue::get(Type::getFloatTy(*DAG.getContext()));
6529 else if (cast<ConstantSDNode>(BVN->getOperand(i))->
6530 getConstantIntValue()->isZero())
6536 Constant *CP = ConstantVector::get(CV);
6537 SDValue CPIdx = DAG.getConstantPool(CP, getPointerTy(),
6538 16 /* alignment */);
6540 SmallVector<SDValue, 2> Ops;
6541 Ops.push_back(DAG.getEntryNode());
6542 Ops.push_back(CPIdx);
6544 SmallVector<EVT, 2> ValueVTs;
6545 ValueVTs.push_back(MVT::v4i1);
6546 ValueVTs.push_back(MVT::Other); // chain
6547 SDVTList VTs = DAG.getVTList(ValueVTs);
6549 return DAG.getMemIntrinsicNode(PPCISD::QVLFSb,
6550 dl, VTs, Ops, MVT::v4f32,
6551 MachinePointerInfo::getConstantPool());
6554 SmallVector<SDValue, 4> Stores;
6555 for (unsigned i = 0; i < 4; ++i) {
6556 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6558 unsigned Offset = 4*i;
6559 SDValue Idx = DAG.getConstant(Offset, FIdx.getValueType());
6560 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
6562 unsigned StoreSize = BVN->getOperand(i).getValueType().getStoreSize();
6563 if (StoreSize > 4) {
6564 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
6565 BVN->getOperand(i), Idx,
6566 PtrInfo.getWithOffset(Offset),
6567 MVT::i32, false, false, 0));
6569 SDValue StoreValue = BVN->getOperand(i);
6571 StoreValue = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, StoreValue);
6573 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
6575 PtrInfo.getWithOffset(Offset),
6581 if (!Stores.empty())
6582 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
6584 StoreChain = DAG.getEntryNode();
6586 // Now load from v4i32 into the QPX register; this will extend it to
6587 // v4i64 but not yet convert it to a floating point. Nevertheless, this
6588 // is typed as v4f64 because the QPX register integer states are not
6589 // explicitly represented.
6591 SmallVector<SDValue, 2> Ops;
6592 Ops.push_back(StoreChain);
6593 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvlfiwz, MVT::i32));
6594 Ops.push_back(FIdx);
6596 SmallVector<EVT, 2> ValueVTs;
6597 ValueVTs.push_back(MVT::v4f64);
6598 ValueVTs.push_back(MVT::Other); // chain
6599 SDVTList VTs = DAG.getVTList(ValueVTs);
6601 SDValue LoadedVect = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN,
6602 dl, VTs, Ops, MVT::v4i32, PtrInfo);
6603 LoadedVect = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
6604 DAG.getConstant(Intrinsic::ppc_qpx_qvfcfidu, MVT::i32),
6607 SDValue FPZeros = DAG.getConstantFP(0.0, MVT::f64);
6608 FPZeros = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6609 FPZeros, FPZeros, FPZeros, FPZeros);
6611 return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ);
6614 // All other QPX vectors are handled by generic code.
6615 if (Subtarget.hasQPX())
6618 // Check if this is a splat of a constant value.
6619 APInt APSplatBits, APSplatUndef;
6620 unsigned SplatBitSize;
6622 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6623 HasAnyUndefs, 0, true) || SplatBitSize > 32)
6626 unsigned SplatBits = APSplatBits.getZExtValue();
6627 unsigned SplatUndef = APSplatUndef.getZExtValue();
6628 unsigned SplatSize = SplatBitSize / 8;
6630 // First, handle single instruction cases.
6633 if (SplatBits == 0) {
6634 // Canonicalize all zero vectors to be v4i32.
6635 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6636 SDValue Z = DAG.getConstant(0, MVT::i32);
6637 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6638 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6643 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6644 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6646 if (SextVal >= -16 && SextVal <= 15)
6647 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6650 // Two instruction sequences.
6652 // If this value is in the range [-32,30] and is even, use:
6653 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6654 // If this value is in the range [17,31] and is odd, use:
6655 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6656 // If this value is in the range [-31,-17] and is odd, use:
6657 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6658 // Note the last two are three-instruction sequences.
6659 if (SextVal >= -32 && SextVal <= 31) {
6660 // To avoid having these optimizations undone by constant folding,
6661 // we convert to a pseudo that will be expanded later into one of
6663 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
6664 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6665 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6666 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
6667 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6668 if (VT == Op.getValueType())
6671 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6674 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6675 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6677 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6678 // Make -1 and vspltisw -1:
6679 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6681 // Make the VSLW intrinsic, computing 0x8000_0000.
6682 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6685 // xor by OnesV to invert it.
6686 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6687 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6690 // The remaining cases assume either big endian element order or
6691 // a splat-size that equates to the element size of the vector
6692 // to be built. An example that doesn't work for little endian is
6693 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
6694 // and a vector element size of 16 bits. The code below will
6695 // produce the vector in big endian element order, which for little
6696 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
6698 // For now, just avoid these optimizations in that case.
6699 // FIXME: Develop correct optimizations for LE with mismatched
6700 // splat and element sizes.
6702 if (Subtarget.isLittleEndian() &&
6703 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
6706 // Check to see if this is a wide variety of vsplti*, binop self cases.
6707 static const signed char SplatCsts[] = {
6708 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6709 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6712 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6713 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6714 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6715 int i = SplatCsts[idx];
6717 // Figure out what shift amount will be used by altivec if shifted by i in
6719 unsigned TypeShiftAmt = i & (SplatBitSize-1);
6721 // vsplti + shl self.
6722 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
6723 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6724 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6725 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
6726 Intrinsic::ppc_altivec_vslw
6728 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6729 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6732 // vsplti + srl self.
6733 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6734 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6735 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6736 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
6737 Intrinsic::ppc_altivec_vsrw
6739 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6740 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6743 // vsplti + sra self.
6744 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6745 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6746 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6747 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
6748 Intrinsic::ppc_altivec_vsraw
6750 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6751 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6754 // vsplti + rol self.
6755 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
6756 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
6757 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6758 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6759 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
6760 Intrinsic::ppc_altivec_vrlw
6762 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6763 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6766 // t = vsplti c, result = vsldoi t, t, 1
6767 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
6768 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6769 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
6771 // t = vsplti c, result = vsldoi t, t, 2
6772 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
6773 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6774 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
6776 // t = vsplti c, result = vsldoi t, t, 3
6777 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
6778 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6779 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
6786 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
6787 /// the specified operations to build the shuffle.
6788 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
6789 SDValue RHS, SelectionDAG &DAG,
6791 unsigned OpNum = (PFEntry >> 26) & 0x0F;
6792 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
6793 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
6796 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
6808 if (OpNum == OP_COPY) {
6809 if (LHSID == (1*9+2)*9+3) return LHS;
6810 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
6814 SDValue OpLHS, OpRHS;
6815 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
6816 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
6820 default: llvm_unreachable("Unknown i32 permute!");
6822 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
6823 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
6824 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
6825 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
6828 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
6829 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
6830 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
6831 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6834 for (unsigned i = 0; i != 16; ++i)
6835 ShufIdxs[i] = (i&3)+0;
6838 for (unsigned i = 0; i != 16; ++i)
6839 ShufIdxs[i] = (i&3)+4;
6842 for (unsigned i = 0; i != 16; ++i)
6843 ShufIdxs[i] = (i&3)+8;
6846 for (unsigned i = 0; i != 16; ++i)
6847 ShufIdxs[i] = (i&3)+12;
6850 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6852 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6854 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6856 EVT VT = OpLHS.getValueType();
6857 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6858 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6859 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6860 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6863 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6864 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6865 /// return the code it can be lowered into. Worst case, it can always be
6866 /// lowered into a vperm.
6867 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6868 SelectionDAG &DAG) const {
6870 SDValue V1 = Op.getOperand(0);
6871 SDValue V2 = Op.getOperand(1);
6872 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6873 EVT VT = Op.getValueType();
6874 bool isLittleEndian = Subtarget.isLittleEndian();
6876 if (Subtarget.hasQPX()) {
6877 if (VT.getVectorNumElements() != 4)
6880 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6882 int AlignIdx = PPC::isQVALIGNIShuffleMask(SVOp);
6883 if (AlignIdx != -1) {
6884 return DAG.getNode(PPCISD::QVALIGNI, dl, VT, V1, V2,
6885 DAG.getConstant(AlignIdx, MVT::i32));
6886 } else if (SVOp->isSplat()) {
6887 int SplatIdx = SVOp->getSplatIndex();
6888 if (SplatIdx >= 4) {
6893 // FIXME: If SplatIdx == 0 and the input came from a load, then there is
6896 return DAG.getNode(PPCISD::QVESPLATI, dl, VT, V1,
6897 DAG.getConstant(SplatIdx, MVT::i32));
6900 // Lower this into a qvgpci/qvfperm pair.
6902 // Compute the qvgpci literal
6904 for (unsigned i = 0; i < 4; ++i) {
6905 int m = SVOp->getMaskElt(i);
6906 unsigned mm = m >= 0 ? (unsigned) m : i;
6907 idx |= mm << (3-i)*3;
6910 SDValue V3 = DAG.getNode(PPCISD::QVGPCI, dl, MVT::v4f64,
6911 DAG.getConstant(idx, MVT::i32));
6912 return DAG.getNode(PPCISD::QVFPERM, dl, VT, V1, V2, V3);
6915 // Cases that are handled by instructions that take permute immediates
6916 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6917 // selected by the instruction selector.
6918 if (V2.getOpcode() == ISD::UNDEF) {
6919 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6920 PPC::isSplatShuffleMask(SVOp, 2) ||
6921 PPC::isSplatShuffleMask(SVOp, 4) ||
6922 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6923 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6924 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
6925 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6926 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6927 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6928 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6929 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6930 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6935 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6936 // and produce a fixed permutation. If any of these match, do not lower to
6938 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6939 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6940 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6941 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
6942 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6943 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6944 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6945 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6946 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6947 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6950 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6951 // perfect shuffle table to emit an optimal matching sequence.
6952 ArrayRef<int> PermMask = SVOp->getMask();
6954 unsigned PFIndexes[4];
6955 bool isFourElementShuffle = true;
6956 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6957 unsigned EltNo = 8; // Start out undef.
6958 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6959 if (PermMask[i*4+j] < 0)
6960 continue; // Undef, ignore it.
6962 unsigned ByteSource = PermMask[i*4+j];
6963 if ((ByteSource & 3) != j) {
6964 isFourElementShuffle = false;
6969 EltNo = ByteSource/4;
6970 } else if (EltNo != ByteSource/4) {
6971 isFourElementShuffle = false;
6975 PFIndexes[i] = EltNo;
6978 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6979 // perfect shuffle vector to determine if it is cost effective to do this as
6980 // discrete instructions, or whether we should use a vperm.
6981 // For now, we skip this for little endian until such time as we have a
6982 // little-endian perfect shuffle table.
6983 if (isFourElementShuffle && !isLittleEndian) {
6984 // Compute the index in the perfect shuffle table.
6985 unsigned PFTableIndex =
6986 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6988 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6989 unsigned Cost = (PFEntry >> 30);
6991 // Determining when to avoid vperm is tricky. Many things affect the cost
6992 // of vperm, particularly how many times the perm mask needs to be computed.
6993 // For example, if the perm mask can be hoisted out of a loop or is already
6994 // used (perhaps because there are multiple permutes with the same shuffle
6995 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6996 // the loop requires an extra register.
6998 // As a compromise, we only emit discrete instructions if the shuffle can be
6999 // generated in 3 or fewer operations. When we have loop information
7000 // available, if this block is within a loop, we should avoid using vperm
7001 // for 3-operation perms and use a constant pool load instead.
7003 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
7006 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
7007 // vector that will get spilled to the constant pool.
7008 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7010 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
7011 // that it is in input element units, not in bytes. Convert now.
7013 // For little endian, the order of the input vectors is reversed, and
7014 // the permutation mask is complemented with respect to 31. This is
7015 // necessary to produce proper semantics with the big-endian-biased vperm
7017 EVT EltVT = V1.getValueType().getVectorElementType();
7018 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
7020 SmallVector<SDValue, 16> ResultMask;
7021 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
7022 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
7024 for (unsigned j = 0; j != BytesPerElement; ++j)
7026 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
7029 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
7033 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
7036 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7039 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7043 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
7044 /// altivec comparison. If it is, return true and fill in Opc/isDot with
7045 /// information about the intrinsic.
7046 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
7048 unsigned IntrinsicID =
7049 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
7052 switch (IntrinsicID) {
7053 default: return false;
7054 // Comparison predicates.
7055 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
7056 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
7057 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
7058 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
7059 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
7060 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
7061 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
7062 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
7063 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
7064 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
7065 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
7066 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
7067 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
7069 // Normal Comparisons.
7070 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
7071 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
7072 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
7073 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
7074 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
7075 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
7076 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
7077 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
7078 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
7079 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
7080 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
7081 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
7082 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
7087 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
7088 /// lower, do it, otherwise return null.
7089 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
7090 SelectionDAG &DAG) const {
7091 // If this is a lowered altivec predicate compare, CompareOpc is set to the
7092 // opcode number of the comparison.
7096 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
7097 return SDValue(); // Don't custom lower most intrinsics.
7099 // If this is a non-dot comparison, make the VCMP node and we are done.
7101 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
7102 Op.getOperand(1), Op.getOperand(2),
7103 DAG.getConstant(CompareOpc, MVT::i32));
7104 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
7107 // Create the PPCISD altivec 'dot' comparison node.
7109 Op.getOperand(2), // LHS
7110 Op.getOperand(3), // RHS
7111 DAG.getConstant(CompareOpc, MVT::i32)
7113 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
7114 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
7116 // Now that we have the comparison, emit a copy from the CR to a GPR.
7117 // This is flagged to the above dot comparison.
7118 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
7119 DAG.getRegister(PPC::CR6, MVT::i32),
7120 CompNode.getValue(1));
7122 // Unpack the result based on how the target uses it.
7123 unsigned BitNo; // Bit # of CR6.
7124 bool InvertBit; // Invert result?
7125 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
7126 default: // Can't happen, don't crash on invalid number though.
7127 case 0: // Return the value of the EQ bit of CR6.
7128 BitNo = 0; InvertBit = false;
7130 case 1: // Return the inverted value of the EQ bit of CR6.
7131 BitNo = 0; InvertBit = true;
7133 case 2: // Return the value of the LT bit of CR6.
7134 BitNo = 2; InvertBit = false;
7136 case 3: // Return the inverted value of the LT bit of CR6.
7137 BitNo = 2; InvertBit = true;
7141 // Shift the bit into the low position.
7142 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
7143 DAG.getConstant(8-(3-BitNo), MVT::i32));
7145 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
7146 DAG.getConstant(1, MVT::i32));
7148 // If we are supposed to, toggle the bit.
7150 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
7151 DAG.getConstant(1, MVT::i32));
7155 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
7156 SelectionDAG &DAG) const {
7158 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
7159 // instructions), but for smaller types, we need to first extend up to v2i32
7160 // before doing going farther.
7161 if (Op.getValueType() == MVT::v2i64) {
7162 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
7163 if (ExtVT != MVT::v2i32) {
7164 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
7165 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
7166 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
7167 ExtVT.getVectorElementType(), 4)));
7168 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
7169 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
7170 DAG.getValueType(MVT::v2i32));
7179 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
7180 SelectionDAG &DAG) const {
7182 // Create a stack slot that is 16-byte aligned.
7183 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7184 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7185 EVT PtrVT = getPointerTy();
7186 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7188 // Store the input value into Value#0 of the stack slot.
7189 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
7190 Op.getOperand(0), FIdx, MachinePointerInfo(),
7193 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
7194 false, false, false, 0);
7197 SDValue PPCTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7198 SelectionDAG &DAG) const {
7200 SDNode *N = Op.getNode();
7202 assert(N->getOperand(0).getValueType() == MVT::v4i1 &&
7203 "Unknown extract_vector_elt type");
7205 SDValue Value = N->getOperand(0);
7207 // The first part of this is like the store lowering except that we don't
7208 // need to track the chain.
7210 // The values are now known to be -1 (false) or 1 (true). To convert this
7211 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7212 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7213 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7215 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7216 // understand how to form the extending load.
7217 SDValue FPHalfs = DAG.getConstantFP(0.5, MVT::f64);
7218 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7219 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7221 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7223 // Now convert to an integer and store.
7224 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7225 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, MVT::i32),
7228 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7229 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7230 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FrameIdx);
7231 EVT PtrVT = getPointerTy();
7232 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7234 SDValue StoreChain = DAG.getEntryNode();
7235 SmallVector<SDValue, 2> Ops;
7236 Ops.push_back(StoreChain);
7237 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, MVT::i32));
7238 Ops.push_back(Value);
7239 Ops.push_back(FIdx);
7241 SmallVector<EVT, 2> ValueVTs;
7242 ValueVTs.push_back(MVT::Other); // chain
7243 SDVTList VTs = DAG.getVTList(ValueVTs);
7245 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7246 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7248 // Extract the value requested.
7249 unsigned Offset = 4*cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7250 SDValue Idx = DAG.getConstant(Offset, FIdx.getValueType());
7251 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7253 SDValue IntVal = DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7254 PtrInfo.getWithOffset(Offset),
7255 false, false, false, 0);
7257 if (!Subtarget.useCRBits())
7260 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, IntVal);
7263 /// Lowering for QPX v4i1 loads
7264 SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
7265 SelectionDAG &DAG) const {
7267 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
7268 SDValue LoadChain = LN->getChain();
7269 SDValue BasePtr = LN->getBasePtr();
7271 if (Op.getValueType() == MVT::v4f64 ||
7272 Op.getValueType() == MVT::v4f32) {
7273 EVT MemVT = LN->getMemoryVT();
7274 unsigned Alignment = LN->getAlignment();
7276 // If this load is properly aligned, then it is legal.
7277 if (Alignment >= MemVT.getStoreSize())
7280 EVT ScalarVT = Op.getValueType().getScalarType(),
7281 ScalarMemVT = MemVT.getScalarType();
7282 unsigned Stride = ScalarMemVT.getStoreSize();
7284 SmallVector<SDValue, 8> Vals, LoadChains;
7285 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7287 if (ScalarVT != ScalarMemVT)
7289 DAG.getExtLoad(LN->getExtensionType(), dl, ScalarVT, LoadChain,
7291 LN->getPointerInfo().getWithOffset(Idx*Stride),
7292 ScalarMemVT, LN->isVolatile(), LN->isNonTemporal(),
7293 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7297 DAG.getLoad(ScalarVT, dl, LoadChain, BasePtr,
7298 LN->getPointerInfo().getWithOffset(Idx*Stride),
7299 LN->isVolatile(), LN->isNonTemporal(),
7300 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7303 if (Idx == 0 && LN->isIndexed()) {
7304 assert(LN->getAddressingMode() == ISD::PRE_INC &&
7305 "Unknown addressing mode on vector load");
7306 Load = DAG.getIndexedLoad(Load, dl, BasePtr, LN->getOffset(),
7307 LN->getAddressingMode());
7310 Vals.push_back(Load);
7311 LoadChains.push_back(Load.getValue(1));
7313 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7314 DAG.getConstant(Stride, BasePtr.getValueType()));
7317 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7318 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
7319 Op.getValueType(), Vals);
7321 if (LN->isIndexed()) {
7322 SDValue RetOps[] = { Value, Vals[0].getValue(1), TF };
7323 return DAG.getMergeValues(RetOps, dl);
7326 SDValue RetOps[] = { Value, TF };
7327 return DAG.getMergeValues(RetOps, dl);
7330 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower");
7331 assert(LN->isUnindexed() && "Indexed v4i1 loads are not supported");
7333 // To lower v4i1 from a byte array, we load the byte elements of the
7334 // vector and then reuse the BUILD_VECTOR logic.
7336 SmallVector<SDValue, 4> VectElmts, VectElmtChains;
7337 for (unsigned i = 0; i < 4; ++i) {
7338 SDValue Idx = DAG.getConstant(i, BasePtr.getValueType());
7339 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7341 VectElmts.push_back(DAG.getExtLoad(ISD::EXTLOAD,
7342 dl, MVT::i32, LoadChain, Idx,
7343 LN->getPointerInfo().getWithOffset(i),
7344 MVT::i8 /* memory type */,
7345 LN->isVolatile(), LN->isNonTemporal(),
7347 1 /* alignment */, LN->getAAInfo()));
7348 VectElmtChains.push_back(VectElmts[i].getValue(1));
7351 LoadChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, VectElmtChains);
7352 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i1, VectElmts);
7354 SDValue RVals[] = { Value, LoadChain };
7355 return DAG.getMergeValues(RVals, dl);
7358 /// Lowering for QPX v4i1 stores
7359 SDValue PPCTargetLowering::LowerVectorStore(SDValue Op,
7360 SelectionDAG &DAG) const {
7362 StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
7363 SDValue StoreChain = SN->getChain();
7364 SDValue BasePtr = SN->getBasePtr();
7365 SDValue Value = SN->getValue();
7367 if (Value.getValueType() == MVT::v4f64 ||
7368 Value.getValueType() == MVT::v4f32) {
7369 EVT MemVT = SN->getMemoryVT();
7370 unsigned Alignment = SN->getAlignment();
7372 // If this store is properly aligned, then it is legal.
7373 if (Alignment >= MemVT.getStoreSize())
7376 EVT ScalarVT = Value.getValueType().getScalarType(),
7377 ScalarMemVT = MemVT.getScalarType();
7378 unsigned Stride = ScalarMemVT.getStoreSize();
7380 SmallVector<SDValue, 8> Stores;
7381 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7383 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, Value,
7384 DAG.getConstant(Idx, getVectorIdxTy()));
7386 if (ScalarVT != ScalarMemVT)
7388 DAG.getTruncStore(StoreChain, dl, Ex, BasePtr,
7389 SN->getPointerInfo().getWithOffset(Idx*Stride),
7390 ScalarMemVT, SN->isVolatile(), SN->isNonTemporal(),
7391 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7394 DAG.getStore(StoreChain, dl, Ex, BasePtr,
7395 SN->getPointerInfo().getWithOffset(Idx*Stride),
7396 SN->isVolatile(), SN->isNonTemporal(),
7397 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7399 if (Idx == 0 && SN->isIndexed()) {
7400 assert(SN->getAddressingMode() == ISD::PRE_INC &&
7401 "Unknown addressing mode on vector store");
7402 Store = DAG.getIndexedStore(Store, dl, BasePtr, SN->getOffset(),
7403 SN->getAddressingMode());
7406 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7407 DAG.getConstant(Stride, BasePtr.getValueType()));
7408 Stores.push_back(Store);
7411 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7413 if (SN->isIndexed()) {
7414 SDValue RetOps[] = { TF, Stores[0].getValue(1) };
7415 return DAG.getMergeValues(RetOps, dl);
7421 assert(SN->isUnindexed() && "Indexed v4i1 stores are not supported");
7422 assert(Value.getValueType() == MVT::v4i1 && "Unknown store to lower");
7424 // The values are now known to be -1 (false) or 1 (true). To convert this
7425 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7426 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7427 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7429 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7430 // understand how to form the extending load.
7431 SDValue FPHalfs = DAG.getConstantFP(0.5, MVT::f64);
7432 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7433 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7435 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7437 // Now convert to an integer and store.
7438 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7439 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, MVT::i32),
7442 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7443 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7444 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FrameIdx);
7445 EVT PtrVT = getPointerTy();
7446 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7448 SmallVector<SDValue, 2> Ops;
7449 Ops.push_back(StoreChain);
7450 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, MVT::i32));
7451 Ops.push_back(Value);
7452 Ops.push_back(FIdx);
7454 SmallVector<EVT, 2> ValueVTs;
7455 ValueVTs.push_back(MVT::Other); // chain
7456 SDVTList VTs = DAG.getVTList(ValueVTs);
7458 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7459 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7461 // Move data into the byte array.
7462 SmallVector<SDValue, 4> Loads, LoadChains;
7463 for (unsigned i = 0; i < 4; ++i) {
7464 unsigned Offset = 4*i;
7465 SDValue Idx = DAG.getConstant(Offset, FIdx.getValueType());
7466 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7468 Loads.push_back(DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7469 PtrInfo.getWithOffset(Offset),
7470 false, false, false, 0));
7471 LoadChains.push_back(Loads[i].getValue(1));
7474 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7476 SmallVector<SDValue, 4> Stores;
7477 for (unsigned i = 0; i < 4; ++i) {
7478 SDValue Idx = DAG.getConstant(i, BasePtr.getValueType());
7479 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7481 Stores.push_back(DAG.getTruncStore(StoreChain, dl, Loads[i], Idx,
7482 SN->getPointerInfo().getWithOffset(i),
7483 MVT::i8 /* memory type */,
7484 SN->isNonTemporal(), SN->isVolatile(),
7485 1 /* alignment */, SN->getAAInfo()));
7488 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7493 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
7495 if (Op.getValueType() == MVT::v4i32) {
7496 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7498 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
7499 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
7501 SDValue RHSSwap = // = vrlw RHS, 16
7502 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
7504 // Shrinkify inputs to v8i16.
7505 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
7506 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
7507 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
7509 // Low parts multiplied together, generating 32-bit results (we ignore the
7511 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
7512 LHS, RHS, DAG, dl, MVT::v4i32);
7514 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
7515 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
7516 // Shift the high parts up 16 bits.
7517 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
7519 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
7520 } else if (Op.getValueType() == MVT::v8i16) {
7521 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7523 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
7525 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
7526 LHS, RHS, Zero, DAG, dl);
7527 } else if (Op.getValueType() == MVT::v16i8) {
7528 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7529 bool isLittleEndian = Subtarget.isLittleEndian();
7531 // Multiply the even 8-bit parts, producing 16-bit sums.
7532 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
7533 LHS, RHS, DAG, dl, MVT::v8i16);
7534 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
7536 // Multiply the odd 8-bit parts, producing 16-bit sums.
7537 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
7538 LHS, RHS, DAG, dl, MVT::v8i16);
7539 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
7541 // Merge the results together. Because vmuleub and vmuloub are
7542 // instructions with a big-endian bias, we must reverse the
7543 // element numbering and reverse the meaning of "odd" and "even"
7544 // when generating little endian code.
7546 for (unsigned i = 0; i != 8; ++i) {
7547 if (isLittleEndian) {
7549 Ops[i*2+1] = 2*i+16;
7552 Ops[i*2+1] = 2*i+1+16;
7556 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
7558 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
7560 llvm_unreachable("Unknown mul to lower!");
7564 /// LowerOperation - Provide custom lowering hooks for some operations.
7566 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7567 switch (Op.getOpcode()) {
7568 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
7569 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7570 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7571 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7572 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7573 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7574 case ISD::SETCC: return LowerSETCC(Op, DAG);
7575 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
7576 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
7578 return LowerVASTART(Op, DAG, Subtarget);
7581 return LowerVAARG(Op, DAG, Subtarget);
7584 return LowerVACOPY(Op, DAG, Subtarget);
7586 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
7587 case ISD::DYNAMIC_STACKALLOC:
7588 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
7590 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
7591 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
7593 case ISD::LOAD: return LowerLOAD(Op, DAG);
7594 case ISD::STORE: return LowerSTORE(Op, DAG);
7595 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
7596 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
7597 case ISD::FP_TO_UINT:
7598 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
7600 case ISD::UINT_TO_FP:
7601 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
7602 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7604 // Lower 64-bit shifts.
7605 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
7606 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
7607 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
7609 // Vector-related lowering.
7610 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7611 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7612 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7613 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7614 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
7615 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7616 case ISD::MUL: return LowerMUL(Op, DAG);
7618 // For counter-based loop handling.
7619 case ISD::INTRINSIC_W_CHAIN: return SDValue();
7621 // Frame & Return address.
7622 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7623 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7627 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
7628 SmallVectorImpl<SDValue>&Results,
7629 SelectionDAG &DAG) const {
7631 switch (N->getOpcode()) {
7633 llvm_unreachable("Do not know how to custom type legalize this operation!");
7634 case ISD::READCYCLECOUNTER: {
7635 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7636 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
7638 Results.push_back(RTB);
7639 Results.push_back(RTB.getValue(1));
7640 Results.push_back(RTB.getValue(2));
7643 case ISD::INTRINSIC_W_CHAIN: {
7644 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
7645 Intrinsic::ppc_is_decremented_ctr_nonzero)
7648 assert(N->getValueType(0) == MVT::i1 &&
7649 "Unexpected result type for CTR decrement intrinsic");
7650 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
7651 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
7652 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
7655 Results.push_back(NewInt);
7656 Results.push_back(NewInt.getValue(1));
7660 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
7663 EVT VT = N->getValueType(0);
7665 if (VT == MVT::i64) {
7666 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
7668 Results.push_back(NewNode);
7669 Results.push_back(NewNode.getValue(1));
7673 case ISD::FP_ROUND_INREG: {
7674 assert(N->getValueType(0) == MVT::ppcf128);
7675 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
7676 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
7677 MVT::f64, N->getOperand(0),
7678 DAG.getIntPtrConstant(0));
7679 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
7680 MVT::f64, N->getOperand(0),
7681 DAG.getIntPtrConstant(1));
7683 // Add the two halves of the long double in round-to-zero mode.
7684 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
7686 // We know the low half is about to be thrown away, so just use something
7688 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
7692 case ISD::FP_TO_SINT:
7693 // LowerFP_TO_INT() can only handle f32 and f64.
7694 if (N->getOperand(0).getValueType() == MVT::ppcf128)
7696 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
7702 //===----------------------------------------------------------------------===//
7703 // Other Lowering Code
7704 //===----------------------------------------------------------------------===//
7706 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
7707 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
7708 Function *Func = Intrinsic::getDeclaration(M, Id);
7709 return Builder.CreateCall(Func);
7712 // The mappings for emitLeading/TrailingFence is taken from
7713 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
7714 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
7715 AtomicOrdering Ord, bool IsStore,
7716 bool IsLoad) const {
7717 if (Ord == SequentiallyConsistent)
7718 return callIntrinsic(Builder, Intrinsic::ppc_sync);
7719 else if (isAtLeastRelease(Ord))
7720 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
7725 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
7726 AtomicOrdering Ord, bool IsStore,
7727 bool IsLoad) const {
7728 if (IsLoad && isAtLeastAcquire(Ord))
7729 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
7730 // FIXME: this is too conservative, a dependent branch + isync is enough.
7731 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
7732 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
7733 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
7739 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
7740 bool is64bit, unsigned BinOpcode) const {
7741 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
7742 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
7744 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7745 MachineFunction *F = BB->getParent();
7746 MachineFunction::iterator It = BB;
7749 unsigned dest = MI->getOperand(0).getReg();
7750 unsigned ptrA = MI->getOperand(1).getReg();
7751 unsigned ptrB = MI->getOperand(2).getReg();
7752 unsigned incr = MI->getOperand(3).getReg();
7753 DebugLoc dl = MI->getDebugLoc();
7755 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
7756 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7757 F->insert(It, loopMBB);
7758 F->insert(It, exitMBB);
7759 exitMBB->splice(exitMBB->begin(), BB,
7760 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7761 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7763 MachineRegisterInfo &RegInfo = F->getRegInfo();
7764 unsigned TmpReg = (!BinOpcode) ? incr :
7765 RegInfo.createVirtualRegister( is64bit ? &PPC::G8RCRegClass
7766 : &PPC::GPRCRegClass);
7770 // fallthrough --> loopMBB
7771 BB->addSuccessor(loopMBB);
7774 // l[wd]arx dest, ptr
7775 // add r0, dest, incr
7776 // st[wd]cx. r0, ptr
7778 // fallthrough --> exitMBB
7780 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7781 .addReg(ptrA).addReg(ptrB);
7783 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
7784 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7785 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
7786 BuildMI(BB, dl, TII->get(PPC::BCC))
7787 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
7788 BB->addSuccessor(loopMBB);
7789 BB->addSuccessor(exitMBB);
7798 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
7799 MachineBasicBlock *BB,
7800 bool is8bit, // operation
7801 unsigned BinOpcode) const {
7802 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
7803 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
7804 // In 64 bit mode we have to use 64 bits for addresses, even though the
7805 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
7806 // registers without caring whether they're 32 or 64, but here we're
7807 // doing actual arithmetic on the addresses.
7808 bool is64bit = Subtarget.isPPC64();
7809 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7811 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7812 MachineFunction *F = BB->getParent();
7813 MachineFunction::iterator It = BB;
7816 unsigned dest = MI->getOperand(0).getReg();
7817 unsigned ptrA = MI->getOperand(1).getReg();
7818 unsigned ptrB = MI->getOperand(2).getReg();
7819 unsigned incr = MI->getOperand(3).getReg();
7820 DebugLoc dl = MI->getDebugLoc();
7822 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
7823 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7824 F->insert(It, loopMBB);
7825 F->insert(It, exitMBB);
7826 exitMBB->splice(exitMBB->begin(), BB,
7827 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7828 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7830 MachineRegisterInfo &RegInfo = F->getRegInfo();
7831 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
7832 : &PPC::GPRCRegClass;
7833 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7834 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7835 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7836 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
7837 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7838 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7839 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7840 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7841 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
7842 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7843 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7845 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
7849 // fallthrough --> loopMBB
7850 BB->addSuccessor(loopMBB);
7852 // The 4-byte load must be aligned, while a char or short may be
7853 // anywhere in the word. Hence all this nasty bookkeeping code.
7854 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7855 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7856 // xori shift, shift1, 24 [16]
7857 // rlwinm ptr, ptr1, 0, 0, 29
7858 // slw incr2, incr, shift
7859 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7860 // slw mask, mask2, shift
7862 // lwarx tmpDest, ptr
7863 // add tmp, tmpDest, incr2
7864 // andc tmp2, tmpDest, mask
7865 // and tmp3, tmp, mask
7866 // or tmp4, tmp3, tmp2
7869 // fallthrough --> exitMBB
7870 // srw dest, tmpDest, shift
7871 if (ptrA != ZeroReg) {
7872 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7873 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7874 .addReg(ptrA).addReg(ptrB);
7878 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7879 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7880 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7881 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7883 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7884 .addReg(Ptr1Reg).addImm(0).addImm(61);
7886 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7887 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7888 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
7889 .addReg(incr).addReg(ShiftReg);
7891 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7893 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7894 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
7896 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7897 .addReg(Mask2Reg).addReg(ShiftReg);
7900 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7901 .addReg(ZeroReg).addReg(PtrReg);
7903 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
7904 .addReg(Incr2Reg).addReg(TmpDestReg);
7905 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
7906 .addReg(TmpDestReg).addReg(MaskReg);
7907 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
7908 .addReg(TmpReg).addReg(MaskReg);
7909 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
7910 .addReg(Tmp3Reg).addReg(Tmp2Reg);
7911 BuildMI(BB, dl, TII->get(PPC::STWCX))
7912 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
7913 BuildMI(BB, dl, TII->get(PPC::BCC))
7914 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
7915 BB->addSuccessor(loopMBB);
7916 BB->addSuccessor(exitMBB);
7921 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
7926 llvm::MachineBasicBlock*
7927 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
7928 MachineBasicBlock *MBB) const {
7929 DebugLoc DL = MI->getDebugLoc();
7930 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
7932 MachineFunction *MF = MBB->getParent();
7933 MachineRegisterInfo &MRI = MF->getRegInfo();
7935 const BasicBlock *BB = MBB->getBasicBlock();
7936 MachineFunction::iterator I = MBB;
7940 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
7941 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
7943 unsigned DstReg = MI->getOperand(0).getReg();
7944 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
7945 assert(RC->hasType(MVT::i32) && "Invalid destination!");
7946 unsigned mainDstReg = MRI.createVirtualRegister(RC);
7947 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
7949 MVT PVT = getPointerTy();
7950 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
7951 "Invalid Pointer Size!");
7952 // For v = setjmp(buf), we generate
7955 // SjLjSetup mainMBB
7961 // buf[LabelOffset] = LR
7965 // v = phi(main, restore)
7968 MachineBasicBlock *thisMBB = MBB;
7969 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
7970 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
7971 MF->insert(I, mainMBB);
7972 MF->insert(I, sinkMBB);
7974 MachineInstrBuilder MIB;
7976 // Transfer the remainder of BB and its successor edges to sinkMBB.
7977 sinkMBB->splice(sinkMBB->begin(), MBB,
7978 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
7979 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
7981 // Note that the structure of the jmp_buf used here is not compatible
7982 // with that used by libc, and is not designed to be. Specifically, it
7983 // stores only those 'reserved' registers that LLVM does not otherwise
7984 // understand how to spill. Also, by convention, by the time this
7985 // intrinsic is called, Clang has already stored the frame address in the
7986 // first slot of the buffer and stack address in the third. Following the
7987 // X86 target code, we'll store the jump address in the second slot. We also
7988 // need to save the TOC pointer (R2) to handle jumps between shared
7989 // libraries, and that will be stored in the fourth slot. The thread
7990 // identifier (R13) is not affected.
7993 const int64_t LabelOffset = 1 * PVT.getStoreSize();
7994 const int64_t TOCOffset = 3 * PVT.getStoreSize();
7995 const int64_t BPOffset = 4 * PVT.getStoreSize();
7997 // Prepare IP either in reg.
7998 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
7999 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
8000 unsigned BufReg = MI->getOperand(1).getReg();
8002 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
8003 setUsesTOCBasePtr(*MBB->getParent());
8004 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
8008 MIB.setMemRefs(MMOBegin, MMOEnd);
8011 // Naked functions never have a base pointer, and so we use r1. For all
8012 // other functions, this decision must be delayed until during PEI.
8014 if (MF->getFunction()->hasFnAttribute(Attribute::Naked))
8015 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
8017 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
8019 MIB = BuildMI(*thisMBB, MI, DL,
8020 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
8024 MIB.setMemRefs(MMOBegin, MMOEnd);
8027 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
8028 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
8029 MIB.addRegMask(TRI->getNoPreservedMask());
8031 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
8033 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
8035 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
8037 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
8038 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
8043 BuildMI(mainMBB, DL,
8044 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
8047 if (Subtarget.isPPC64()) {
8048 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
8050 .addImm(LabelOffset)
8053 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
8055 .addImm(LabelOffset)
8059 MIB.setMemRefs(MMOBegin, MMOEnd);
8061 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
8062 mainMBB->addSuccessor(sinkMBB);
8065 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
8066 TII->get(PPC::PHI), DstReg)
8067 .addReg(mainDstReg).addMBB(mainMBB)
8068 .addReg(restoreDstReg).addMBB(thisMBB);
8070 MI->eraseFromParent();
8075 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
8076 MachineBasicBlock *MBB) const {
8077 DebugLoc DL = MI->getDebugLoc();
8078 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8080 MachineFunction *MF = MBB->getParent();
8081 MachineRegisterInfo &MRI = MF->getRegInfo();
8084 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8085 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8087 MVT PVT = getPointerTy();
8088 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8089 "Invalid Pointer Size!");
8091 const TargetRegisterClass *RC =
8092 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
8093 unsigned Tmp = MRI.createVirtualRegister(RC);
8094 // Since FP is only updated here but NOT referenced, it's treated as GPR.
8095 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
8096 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
8100 : (Subtarget.isSVR4ABI() &&
8101 MF->getTarget().getRelocationModel() == Reloc::PIC_
8105 MachineInstrBuilder MIB;
8107 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8108 const int64_t SPOffset = 2 * PVT.getStoreSize();
8109 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8110 const int64_t BPOffset = 4 * PVT.getStoreSize();
8112 unsigned BufReg = MI->getOperand(0).getReg();
8114 // Reload FP (the jumped-to function may not have had a
8115 // frame pointer, and if so, then its r31 will be restored
8117 if (PVT == MVT::i64) {
8118 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
8122 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
8126 MIB.setMemRefs(MMOBegin, MMOEnd);
8129 if (PVT == MVT::i64) {
8130 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
8131 .addImm(LabelOffset)
8134 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
8135 .addImm(LabelOffset)
8138 MIB.setMemRefs(MMOBegin, MMOEnd);
8141 if (PVT == MVT::i64) {
8142 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
8146 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
8150 MIB.setMemRefs(MMOBegin, MMOEnd);
8153 if (PVT == MVT::i64) {
8154 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
8158 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
8162 MIB.setMemRefs(MMOBegin, MMOEnd);
8165 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
8166 setUsesTOCBasePtr(*MBB->getParent());
8167 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
8171 MIB.setMemRefs(MMOBegin, MMOEnd);
8175 BuildMI(*MBB, MI, DL,
8176 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
8177 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
8179 MI->eraseFromParent();
8184 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8185 MachineBasicBlock *BB) const {
8186 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
8187 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8188 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
8189 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8190 // Call lowering should have added an r2 operand to indicate a dependence
8191 // on the TOC base pointer value. It can't however, because there is no
8192 // way to mark the dependence as implicit there, and so the stackmap code
8193 // will confuse it with a regular operand. Instead, add the dependence
8195 setUsesTOCBasePtr(*BB->getParent());
8196 MI->addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
8199 return emitPatchPoint(MI, BB);
8202 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
8203 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
8204 return emitEHSjLjSetJmp(MI, BB);
8205 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
8206 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
8207 return emitEHSjLjLongJmp(MI, BB);
8210 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8212 // To "insert" these instructions we actually have to insert their
8213 // control-flow patterns.
8214 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8215 MachineFunction::iterator It = BB;
8218 MachineFunction *F = BB->getParent();
8220 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8221 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8222 MI->getOpcode() == PPC::SELECT_I4 ||
8223 MI->getOpcode() == PPC::SELECT_I8)) {
8224 SmallVector<MachineOperand, 2> Cond;
8225 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8226 MI->getOpcode() == PPC::SELECT_CC_I8)
8227 Cond.push_back(MI->getOperand(4));
8229 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
8230 Cond.push_back(MI->getOperand(1));
8232 DebugLoc dl = MI->getDebugLoc();
8233 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
8234 Cond, MI->getOperand(2).getReg(),
8235 MI->getOperand(3).getReg());
8236 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8237 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8238 MI->getOpcode() == PPC::SELECT_CC_F4 ||
8239 MI->getOpcode() == PPC::SELECT_CC_F8 ||
8240 MI->getOpcode() == PPC::SELECT_CC_QFRC ||
8241 MI->getOpcode() == PPC::SELECT_CC_QSRC ||
8242 MI->getOpcode() == PPC::SELECT_CC_QBRC ||
8243 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
8244 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
8245 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
8246 MI->getOpcode() == PPC::SELECT_I4 ||
8247 MI->getOpcode() == PPC::SELECT_I8 ||
8248 MI->getOpcode() == PPC::SELECT_F4 ||
8249 MI->getOpcode() == PPC::SELECT_F8 ||
8250 MI->getOpcode() == PPC::SELECT_QFRC ||
8251 MI->getOpcode() == PPC::SELECT_QSRC ||
8252 MI->getOpcode() == PPC::SELECT_QBRC ||
8253 MI->getOpcode() == PPC::SELECT_VRRC ||
8254 MI->getOpcode() == PPC::SELECT_VSFRC ||
8255 MI->getOpcode() == PPC::SELECT_VSRC) {
8256 // The incoming instruction knows the destination vreg to set, the
8257 // condition code register to branch on, the true/false values to
8258 // select between, and a branch opcode to use.
8263 // cmpTY ccX, r1, r2
8265 // fallthrough --> copy0MBB
8266 MachineBasicBlock *thisMBB = BB;
8267 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8268 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8269 DebugLoc dl = MI->getDebugLoc();
8270 F->insert(It, copy0MBB);
8271 F->insert(It, sinkMBB);
8273 // Transfer the remainder of BB and its successor edges to sinkMBB.
8274 sinkMBB->splice(sinkMBB->begin(), BB,
8275 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8276 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8278 // Next, add the true and fallthrough blocks as its successors.
8279 BB->addSuccessor(copy0MBB);
8280 BB->addSuccessor(sinkMBB);
8282 if (MI->getOpcode() == PPC::SELECT_I4 ||
8283 MI->getOpcode() == PPC::SELECT_I8 ||
8284 MI->getOpcode() == PPC::SELECT_F4 ||
8285 MI->getOpcode() == PPC::SELECT_F8 ||
8286 MI->getOpcode() == PPC::SELECT_QFRC ||
8287 MI->getOpcode() == PPC::SELECT_QSRC ||
8288 MI->getOpcode() == PPC::SELECT_QBRC ||
8289 MI->getOpcode() == PPC::SELECT_VRRC ||
8290 MI->getOpcode() == PPC::SELECT_VSFRC ||
8291 MI->getOpcode() == PPC::SELECT_VSRC) {
8292 BuildMI(BB, dl, TII->get(PPC::BC))
8293 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8295 unsigned SelectPred = MI->getOperand(4).getImm();
8296 BuildMI(BB, dl, TII->get(PPC::BCC))
8297 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8301 // %FalseValue = ...
8302 // # fallthrough to sinkMBB
8305 // Update machine-CFG edges
8306 BB->addSuccessor(sinkMBB);
8309 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8312 BuildMI(*BB, BB->begin(), dl,
8313 TII->get(PPC::PHI), MI->getOperand(0).getReg())
8314 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
8315 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8316 } else if (MI->getOpcode() == PPC::ReadTB) {
8317 // To read the 64-bit time-base register on a 32-bit target, we read the
8318 // two halves. Should the counter have wrapped while it was being read, we
8319 // need to try again.
8322 // mfspr Rx,TBU # load from TBU
8323 // mfspr Ry,TB # load from TB
8324 // mfspr Rz,TBU # load from TBU
8325 // cmpw crX,Rx,Rz # check if ‘old’=’new’
8326 // bne readLoop # branch if they're not equal
8329 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
8330 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8331 DebugLoc dl = MI->getDebugLoc();
8332 F->insert(It, readMBB);
8333 F->insert(It, sinkMBB);
8335 // Transfer the remainder of BB and its successor edges to sinkMBB.
8336 sinkMBB->splice(sinkMBB->begin(), BB,
8337 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8338 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8340 BB->addSuccessor(readMBB);
8343 MachineRegisterInfo &RegInfo = F->getRegInfo();
8344 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
8345 unsigned LoReg = MI->getOperand(0).getReg();
8346 unsigned HiReg = MI->getOperand(1).getReg();
8348 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
8349 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
8350 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
8352 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
8354 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
8355 .addReg(HiReg).addReg(ReadAgainReg);
8356 BuildMI(BB, dl, TII->get(PPC::BCC))
8357 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
8359 BB->addSuccessor(readMBB);
8360 BB->addSuccessor(sinkMBB);
8362 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
8363 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
8364 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
8365 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
8366 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
8367 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
8368 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
8369 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
8371 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
8372 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
8373 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
8374 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
8375 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
8376 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
8377 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
8378 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
8380 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
8381 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
8382 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
8383 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
8384 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
8385 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
8386 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
8387 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
8389 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
8390 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
8391 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
8392 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
8393 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
8394 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
8395 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
8396 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
8398 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
8399 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
8400 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
8401 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
8402 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
8403 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
8404 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
8405 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
8407 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
8408 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
8409 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
8410 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
8411 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
8412 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
8413 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
8414 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
8416 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
8417 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
8418 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
8419 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
8420 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
8421 BB = EmitAtomicBinary(MI, BB, false, 0);
8422 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
8423 BB = EmitAtomicBinary(MI, BB, true, 0);
8425 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
8426 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
8427 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
8429 unsigned dest = MI->getOperand(0).getReg();
8430 unsigned ptrA = MI->getOperand(1).getReg();
8431 unsigned ptrB = MI->getOperand(2).getReg();
8432 unsigned oldval = MI->getOperand(3).getReg();
8433 unsigned newval = MI->getOperand(4).getReg();
8434 DebugLoc dl = MI->getDebugLoc();
8436 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8437 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8438 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8439 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8440 F->insert(It, loop1MBB);
8441 F->insert(It, loop2MBB);
8442 F->insert(It, midMBB);
8443 F->insert(It, exitMBB);
8444 exitMBB->splice(exitMBB->begin(), BB,
8445 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8446 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8450 // fallthrough --> loopMBB
8451 BB->addSuccessor(loop1MBB);
8454 // l[wd]arx dest, ptr
8455 // cmp[wd] dest, oldval
8458 // st[wd]cx. newval, ptr
8462 // st[wd]cx. dest, ptr
8465 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
8466 .addReg(ptrA).addReg(ptrB);
8467 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
8468 .addReg(oldval).addReg(dest);
8469 BuildMI(BB, dl, TII->get(PPC::BCC))
8470 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
8471 BB->addSuccessor(loop2MBB);
8472 BB->addSuccessor(midMBB);
8475 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
8476 .addReg(newval).addReg(ptrA).addReg(ptrB);
8477 BuildMI(BB, dl, TII->get(PPC::BCC))
8478 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
8479 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
8480 BB->addSuccessor(loop1MBB);
8481 BB->addSuccessor(exitMBB);
8484 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
8485 .addReg(dest).addReg(ptrA).addReg(ptrB);
8486 BB->addSuccessor(exitMBB);
8491 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
8492 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
8493 // We must use 64-bit registers for addresses when targeting 64-bit,
8494 // since we're actually doing arithmetic on them. Other registers
8496 bool is64bit = Subtarget.isPPC64();
8497 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
8499 unsigned dest = MI->getOperand(0).getReg();
8500 unsigned ptrA = MI->getOperand(1).getReg();
8501 unsigned ptrB = MI->getOperand(2).getReg();
8502 unsigned oldval = MI->getOperand(3).getReg();
8503 unsigned newval = MI->getOperand(4).getReg();
8504 DebugLoc dl = MI->getDebugLoc();
8506 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8507 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8508 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8509 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8510 F->insert(It, loop1MBB);
8511 F->insert(It, loop2MBB);
8512 F->insert(It, midMBB);
8513 F->insert(It, exitMBB);
8514 exitMBB->splice(exitMBB->begin(), BB,
8515 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8516 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8518 MachineRegisterInfo &RegInfo = F->getRegInfo();
8519 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8520 : &PPC::GPRCRegClass;
8521 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8522 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8523 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8524 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
8525 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
8526 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
8527 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
8528 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8529 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8530 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8531 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8532 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8533 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8535 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
8536 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8539 // fallthrough --> loopMBB
8540 BB->addSuccessor(loop1MBB);
8542 // The 4-byte load must be aligned, while a char or short may be
8543 // anywhere in the word. Hence all this nasty bookkeeping code.
8544 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8545 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8546 // xori shift, shift1, 24 [16]
8547 // rlwinm ptr, ptr1, 0, 0, 29
8548 // slw newval2, newval, shift
8549 // slw oldval2, oldval,shift
8550 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8551 // slw mask, mask2, shift
8552 // and newval3, newval2, mask
8553 // and oldval3, oldval2, mask
8555 // lwarx tmpDest, ptr
8556 // and tmp, tmpDest, mask
8557 // cmpw tmp, oldval3
8560 // andc tmp2, tmpDest, mask
8561 // or tmp4, tmp2, newval3
8566 // stwcx. tmpDest, ptr
8568 // srw dest, tmpDest, shift
8569 if (ptrA != ZeroReg) {
8570 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8571 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8572 .addReg(ptrA).addReg(ptrB);
8576 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8577 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8578 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8579 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8581 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8582 .addReg(Ptr1Reg).addImm(0).addImm(61);
8584 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8585 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8586 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
8587 .addReg(newval).addReg(ShiftReg);
8588 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
8589 .addReg(oldval).addReg(ShiftReg);
8591 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
8593 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
8594 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
8595 .addReg(Mask3Reg).addImm(65535);
8597 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
8598 .addReg(Mask2Reg).addReg(ShiftReg);
8599 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
8600 .addReg(NewVal2Reg).addReg(MaskReg);
8601 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
8602 .addReg(OldVal2Reg).addReg(MaskReg);
8605 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
8606 .addReg(ZeroReg).addReg(PtrReg);
8607 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
8608 .addReg(TmpDestReg).addReg(MaskReg);
8609 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
8610 .addReg(TmpReg).addReg(OldVal3Reg);
8611 BuildMI(BB, dl, TII->get(PPC::BCC))
8612 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
8613 BB->addSuccessor(loop2MBB);
8614 BB->addSuccessor(midMBB);
8617 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
8618 .addReg(TmpDestReg).addReg(MaskReg);
8619 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
8620 .addReg(Tmp2Reg).addReg(NewVal3Reg);
8621 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
8622 .addReg(ZeroReg).addReg(PtrReg);
8623 BuildMI(BB, dl, TII->get(PPC::BCC))
8624 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
8625 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
8626 BB->addSuccessor(loop1MBB);
8627 BB->addSuccessor(exitMBB);
8630 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
8631 .addReg(ZeroReg).addReg(PtrReg);
8632 BB->addSuccessor(exitMBB);
8637 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
8639 } else if (MI->getOpcode() == PPC::FADDrtz) {
8640 // This pseudo performs an FADD with rounding mode temporarily forced
8641 // to round-to-zero. We emit this via custom inserter since the FPSCR
8642 // is not modeled at the SelectionDAG level.
8643 unsigned Dest = MI->getOperand(0).getReg();
8644 unsigned Src1 = MI->getOperand(1).getReg();
8645 unsigned Src2 = MI->getOperand(2).getReg();
8646 DebugLoc dl = MI->getDebugLoc();
8648 MachineRegisterInfo &RegInfo = F->getRegInfo();
8649 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
8651 // Save FPSCR value.
8652 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
8654 // Set rounding mode to round-to-zero.
8655 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
8656 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
8658 // Perform addition.
8659 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
8661 // Restore FPSCR value.
8662 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
8663 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
8664 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
8665 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
8666 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
8667 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
8668 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
8669 PPC::ANDIo8 : PPC::ANDIo;
8670 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
8671 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
8673 MachineRegisterInfo &RegInfo = F->getRegInfo();
8674 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
8675 &PPC::GPRCRegClass :
8676 &PPC::G8RCRegClass);
8678 DebugLoc dl = MI->getDebugLoc();
8679 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
8680 .addReg(MI->getOperand(1).getReg()).addImm(1);
8681 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
8682 MI->getOperand(0).getReg())
8683 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
8685 llvm_unreachable("Unexpected instr type to insert");
8688 MI->eraseFromParent(); // The pseudo instruction is gone now.
8692 //===----------------------------------------------------------------------===//
8693 // Target Optimization Hooks
8694 //===----------------------------------------------------------------------===//
8696 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
8697 DAGCombinerInfo &DCI,
8698 unsigned &RefinementSteps,
8699 bool &UseOneConstNR) const {
8700 EVT VT = Operand.getValueType();
8701 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
8702 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
8703 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
8704 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
8705 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
8706 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
8707 // Convergence is quadratic, so we essentially double the number of digits
8708 // correct after every iteration. For both FRE and FRSQRTE, the minimum
8709 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
8710 // 2^-14. IEEE float has 23 digits and double has 52 digits.
8711 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
8712 if (VT.getScalarType() == MVT::f64)
8714 UseOneConstNR = true;
8715 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
8720 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
8721 DAGCombinerInfo &DCI,
8722 unsigned &RefinementSteps) const {
8723 EVT VT = Operand.getValueType();
8724 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
8725 (VT == MVT::f64 && Subtarget.hasFRE()) ||
8726 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
8727 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
8728 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
8729 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
8730 // Convergence is quadratic, so we essentially double the number of digits
8731 // correct after every iteration. For both FRE and FRSQRTE, the minimum
8732 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
8733 // 2^-14. IEEE float has 23 digits and double has 52 digits.
8734 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
8735 if (VT.getScalarType() == MVT::f64)
8737 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
8742 bool PPCTargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
8743 // Note: This functionality is used only when unsafe-fp-math is enabled, and
8744 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
8745 // enabled for division), this functionality is redundant with the default
8746 // combiner logic (once the division -> reciprocal/multiply transformation
8747 // has taken place). As a result, this matters more for older cores than for
8750 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
8751 // reciprocal if there are two or more FDIVs (for embedded cores with only
8752 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
8753 switch (Subtarget.getDarwinDirective()) {
8755 return NumUsers > 2;
8758 case PPC::DIR_E500mc:
8759 case PPC::DIR_E5500:
8760 return NumUsers > 1;
8764 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
8765 unsigned Bytes, int Dist,
8766 SelectionDAG &DAG) {
8767 if (VT.getSizeInBits() / 8 != Bytes)
8770 SDValue BaseLoc = Base->getBasePtr();
8771 if (Loc.getOpcode() == ISD::FrameIndex) {
8772 if (BaseLoc.getOpcode() != ISD::FrameIndex)
8774 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
8775 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
8776 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
8777 int FS = MFI->getObjectSize(FI);
8778 int BFS = MFI->getObjectSize(BFI);
8779 if (FS != BFS || FS != (int)Bytes) return false;
8780 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
8784 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
8785 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
8788 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
8789 const GlobalValue *GV1 = nullptr;
8790 const GlobalValue *GV2 = nullptr;
8791 int64_t Offset1 = 0;
8792 int64_t Offset2 = 0;
8793 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
8794 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
8795 if (isGA1 && isGA2 && GV1 == GV2)
8796 return Offset1 == (Offset2 + Dist*Bytes);
8800 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
8801 // not enforce equality of the chain operands.
8802 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
8803 unsigned Bytes, int Dist,
8804 SelectionDAG &DAG) {
8805 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
8806 EVT VT = LS->getMemoryVT();
8807 SDValue Loc = LS->getBasePtr();
8808 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
8811 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
8813 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8814 default: return false;
8815 case Intrinsic::ppc_qpx_qvlfd:
8816 case Intrinsic::ppc_qpx_qvlfda:
8819 case Intrinsic::ppc_qpx_qvlfs:
8820 case Intrinsic::ppc_qpx_qvlfsa:
8823 case Intrinsic::ppc_qpx_qvlfcd:
8824 case Intrinsic::ppc_qpx_qvlfcda:
8827 case Intrinsic::ppc_qpx_qvlfcs:
8828 case Intrinsic::ppc_qpx_qvlfcsa:
8831 case Intrinsic::ppc_qpx_qvlfiwa:
8832 case Intrinsic::ppc_qpx_qvlfiwz:
8833 case Intrinsic::ppc_altivec_lvx:
8834 case Intrinsic::ppc_altivec_lvxl:
8835 case Intrinsic::ppc_vsx_lxvw4x:
8838 case Intrinsic::ppc_vsx_lxvd2x:
8841 case Intrinsic::ppc_altivec_lvebx:
8844 case Intrinsic::ppc_altivec_lvehx:
8847 case Intrinsic::ppc_altivec_lvewx:
8852 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
8855 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
8857 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8858 default: return false;
8859 case Intrinsic::ppc_qpx_qvstfd:
8860 case Intrinsic::ppc_qpx_qvstfda:
8863 case Intrinsic::ppc_qpx_qvstfs:
8864 case Intrinsic::ppc_qpx_qvstfsa:
8867 case Intrinsic::ppc_qpx_qvstfcd:
8868 case Intrinsic::ppc_qpx_qvstfcda:
8871 case Intrinsic::ppc_qpx_qvstfcs:
8872 case Intrinsic::ppc_qpx_qvstfcsa:
8875 case Intrinsic::ppc_qpx_qvstfiw:
8876 case Intrinsic::ppc_qpx_qvstfiwa:
8877 case Intrinsic::ppc_altivec_stvx:
8878 case Intrinsic::ppc_altivec_stvxl:
8879 case Intrinsic::ppc_vsx_stxvw4x:
8882 case Intrinsic::ppc_vsx_stxvd2x:
8885 case Intrinsic::ppc_altivec_stvebx:
8888 case Intrinsic::ppc_altivec_stvehx:
8891 case Intrinsic::ppc_altivec_stvewx:
8896 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
8902 // Return true is there is a nearyby consecutive load to the one provided
8903 // (regardless of alignment). We search up and down the chain, looking though
8904 // token factors and other loads (but nothing else). As a result, a true result
8905 // indicates that it is safe to create a new consecutive load adjacent to the
8907 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
8908 SDValue Chain = LD->getChain();
8909 EVT VT = LD->getMemoryVT();
8911 SmallSet<SDNode *, 16> LoadRoots;
8912 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
8913 SmallSet<SDNode *, 16> Visited;
8915 // First, search up the chain, branching to follow all token-factor operands.
8916 // If we find a consecutive load, then we're done, otherwise, record all
8917 // nodes just above the top-level loads and token factors.
8918 while (!Queue.empty()) {
8919 SDNode *ChainNext = Queue.pop_back_val();
8920 if (!Visited.insert(ChainNext).second)
8923 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
8924 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
8927 if (!Visited.count(ChainLD->getChain().getNode()))
8928 Queue.push_back(ChainLD->getChain().getNode());
8929 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
8930 for (const SDUse &O : ChainNext->ops())
8931 if (!Visited.count(O.getNode()))
8932 Queue.push_back(O.getNode());
8934 LoadRoots.insert(ChainNext);
8937 // Second, search down the chain, starting from the top-level nodes recorded
8938 // in the first phase. These top-level nodes are the nodes just above all
8939 // loads and token factors. Starting with their uses, recursively look though
8940 // all loads (just the chain uses) and token factors to find a consecutive
8945 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
8946 IE = LoadRoots.end(); I != IE; ++I) {
8947 Queue.push_back(*I);
8949 while (!Queue.empty()) {
8950 SDNode *LoadRoot = Queue.pop_back_val();
8951 if (!Visited.insert(LoadRoot).second)
8954 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
8955 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
8958 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
8959 UE = LoadRoot->use_end(); UI != UE; ++UI)
8960 if (((isa<MemSDNode>(*UI) &&
8961 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
8962 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
8963 Queue.push_back(*UI);
8970 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
8971 DAGCombinerInfo &DCI) const {
8972 SelectionDAG &DAG = DCI.DAG;
8975 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits");
8976 // If we're tracking CR bits, we need to be careful that we don't have:
8977 // trunc(binary-ops(zext(x), zext(y)))
8979 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
8980 // such that we're unnecessarily moving things into GPRs when it would be
8981 // better to keep them in CR bits.
8983 // Note that trunc here can be an actual i1 trunc, or can be the effective
8984 // truncation that comes from a setcc or select_cc.
8985 if (N->getOpcode() == ISD::TRUNCATE &&
8986 N->getValueType(0) != MVT::i1)
8989 if (N->getOperand(0).getValueType() != MVT::i32 &&
8990 N->getOperand(0).getValueType() != MVT::i64)
8993 if (N->getOpcode() == ISD::SETCC ||
8994 N->getOpcode() == ISD::SELECT_CC) {
8995 // If we're looking at a comparison, then we need to make sure that the
8996 // high bits (all except for the first) don't matter the result.
8998 cast<CondCodeSDNode>(N->getOperand(
8999 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
9000 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
9002 if (ISD::isSignedIntSetCC(CC)) {
9003 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
9004 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
9006 } else if (ISD::isUnsignedIntSetCC(CC)) {
9007 if (!DAG.MaskedValueIsZero(N->getOperand(0),
9008 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
9009 !DAG.MaskedValueIsZero(N->getOperand(1),
9010 APInt::getHighBitsSet(OpBits, OpBits-1)))
9013 // This is neither a signed nor an unsigned comparison, just make sure
9014 // that the high bits are equal.
9015 APInt Op1Zero, Op1One;
9016 APInt Op2Zero, Op2One;
9017 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
9018 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
9020 // We don't really care about what is known about the first bit (if
9021 // anything), so clear it in all masks prior to comparing them.
9022 Op1Zero.clearBit(0); Op1One.clearBit(0);
9023 Op2Zero.clearBit(0); Op2One.clearBit(0);
9025 if (Op1Zero != Op2Zero || Op1One != Op2One)
9030 // We now know that the higher-order bits are irrelevant, we just need to
9031 // make sure that all of the intermediate operations are bit operations, and
9032 // all inputs are extensions.
9033 if (N->getOperand(0).getOpcode() != ISD::AND &&
9034 N->getOperand(0).getOpcode() != ISD::OR &&
9035 N->getOperand(0).getOpcode() != ISD::XOR &&
9036 N->getOperand(0).getOpcode() != ISD::SELECT &&
9037 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
9038 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
9039 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
9040 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
9041 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
9044 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
9045 N->getOperand(1).getOpcode() != ISD::AND &&
9046 N->getOperand(1).getOpcode() != ISD::OR &&
9047 N->getOperand(1).getOpcode() != ISD::XOR &&
9048 N->getOperand(1).getOpcode() != ISD::SELECT &&
9049 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
9050 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
9051 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
9052 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
9053 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
9056 SmallVector<SDValue, 4> Inputs;
9057 SmallVector<SDValue, 8> BinOps, PromOps;
9058 SmallPtrSet<SDNode *, 16> Visited;
9060 for (unsigned i = 0; i < 2; ++i) {
9061 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9062 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9063 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9064 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9065 isa<ConstantSDNode>(N->getOperand(i)))
9066 Inputs.push_back(N->getOperand(i));
9068 BinOps.push_back(N->getOperand(i));
9070 if (N->getOpcode() == ISD::TRUNCATE)
9074 // Visit all inputs, collect all binary operations (and, or, xor and
9075 // select) that are all fed by extensions.
9076 while (!BinOps.empty()) {
9077 SDValue BinOp = BinOps.back();
9080 if (!Visited.insert(BinOp.getNode()).second)
9083 PromOps.push_back(BinOp);
9085 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9086 // The condition of the select is not promoted.
9087 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9089 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9092 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9093 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9094 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9095 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9096 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9097 Inputs.push_back(BinOp.getOperand(i));
9098 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9099 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9100 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9101 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9102 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
9103 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9104 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9105 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9106 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
9107 BinOps.push_back(BinOp.getOperand(i));
9109 // We have an input that is not an extension or another binary
9110 // operation; we'll abort this transformation.
9116 // Make sure that this is a self-contained cluster of operations (which
9117 // is not quite the same thing as saying that everything has only one
9119 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9120 if (isa<ConstantSDNode>(Inputs[i]))
9123 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9124 UE = Inputs[i].getNode()->use_end();
9127 if (User != N && !Visited.count(User))
9130 // Make sure that we're not going to promote the non-output-value
9131 // operand(s) or SELECT or SELECT_CC.
9132 // FIXME: Although we could sometimes handle this, and it does occur in
9133 // practice that one of the condition inputs to the select is also one of
9134 // the outputs, we currently can't deal with this.
9135 if (User->getOpcode() == ISD::SELECT) {
9136 if (User->getOperand(0) == Inputs[i])
9138 } else if (User->getOpcode() == ISD::SELECT_CC) {
9139 if (User->getOperand(0) == Inputs[i] ||
9140 User->getOperand(1) == Inputs[i])
9146 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9147 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9148 UE = PromOps[i].getNode()->use_end();
9151 if (User != N && !Visited.count(User))
9154 // Make sure that we're not going to promote the non-output-value
9155 // operand(s) or SELECT or SELECT_CC.
9156 // FIXME: Although we could sometimes handle this, and it does occur in
9157 // practice that one of the condition inputs to the select is also one of
9158 // the outputs, we currently can't deal with this.
9159 if (User->getOpcode() == ISD::SELECT) {
9160 if (User->getOperand(0) == PromOps[i])
9162 } else if (User->getOpcode() == ISD::SELECT_CC) {
9163 if (User->getOperand(0) == PromOps[i] ||
9164 User->getOperand(1) == PromOps[i])
9170 // Replace all inputs with the extension operand.
9171 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9172 // Constants may have users outside the cluster of to-be-promoted nodes,
9173 // and so we need to replace those as we do the promotions.
9174 if (isa<ConstantSDNode>(Inputs[i]))
9177 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
9180 // Replace all operations (these are all the same, but have a different
9181 // (i1) return type). DAG.getNode will validate that the types of
9182 // a binary operator match, so go through the list in reverse so that
9183 // we've likely promoted both operands first. Any intermediate truncations or
9184 // extensions disappear.
9185 while (!PromOps.empty()) {
9186 SDValue PromOp = PromOps.back();
9189 if (PromOp.getOpcode() == ISD::TRUNCATE ||
9190 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
9191 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
9192 PromOp.getOpcode() == ISD::ANY_EXTEND) {
9193 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
9194 PromOp.getOperand(0).getValueType() != MVT::i1) {
9195 // The operand is not yet ready (see comment below).
9196 PromOps.insert(PromOps.begin(), PromOp);
9200 SDValue RepValue = PromOp.getOperand(0);
9201 if (isa<ConstantSDNode>(RepValue))
9202 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
9204 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
9209 switch (PromOp.getOpcode()) {
9210 default: C = 0; break;
9211 case ISD::SELECT: C = 1; break;
9212 case ISD::SELECT_CC: C = 2; break;
9215 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9216 PromOp.getOperand(C).getValueType() != MVT::i1) ||
9217 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9218 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
9219 // The to-be-promoted operands of this node have not yet been
9220 // promoted (this should be rare because we're going through the
9221 // list backward, but if one of the operands has several users in
9222 // this cluster of to-be-promoted nodes, it is possible).
9223 PromOps.insert(PromOps.begin(), PromOp);
9227 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9228 PromOp.getNode()->op_end());
9230 // If there are any constant inputs, make sure they're replaced now.
9231 for (unsigned i = 0; i < 2; ++i)
9232 if (isa<ConstantSDNode>(Ops[C+i]))
9233 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
9235 DAG.ReplaceAllUsesOfValueWith(PromOp,
9236 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
9239 // Now we're left with the initial truncation itself.
9240 if (N->getOpcode() == ISD::TRUNCATE)
9241 return N->getOperand(0);
9243 // Otherwise, this is a comparison. The operands to be compared have just
9244 // changed type (to i1), but everything else is the same.
9245 return SDValue(N, 0);
9248 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
9249 DAGCombinerInfo &DCI) const {
9250 SelectionDAG &DAG = DCI.DAG;
9253 // If we're tracking CR bits, we need to be careful that we don't have:
9254 // zext(binary-ops(trunc(x), trunc(y)))
9256 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
9257 // such that we're unnecessarily moving things into CR bits that can more
9258 // efficiently stay in GPRs. Note that if we're not certain that the high
9259 // bits are set as required by the final extension, we still may need to do
9260 // some masking to get the proper behavior.
9262 // This same functionality is important on PPC64 when dealing with
9263 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
9264 // the return values of functions. Because it is so similar, it is handled
9267 if (N->getValueType(0) != MVT::i32 &&
9268 N->getValueType(0) != MVT::i64)
9271 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
9272 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
9275 if (N->getOperand(0).getOpcode() != ISD::AND &&
9276 N->getOperand(0).getOpcode() != ISD::OR &&
9277 N->getOperand(0).getOpcode() != ISD::XOR &&
9278 N->getOperand(0).getOpcode() != ISD::SELECT &&
9279 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
9282 SmallVector<SDValue, 4> Inputs;
9283 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
9284 SmallPtrSet<SDNode *, 16> Visited;
9286 // Visit all inputs, collect all binary operations (and, or, xor and
9287 // select) that are all fed by truncations.
9288 while (!BinOps.empty()) {
9289 SDValue BinOp = BinOps.back();
9292 if (!Visited.insert(BinOp.getNode()).second)
9295 PromOps.push_back(BinOp);
9297 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9298 // The condition of the select is not promoted.
9299 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9301 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9304 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9305 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9306 Inputs.push_back(BinOp.getOperand(i));
9307 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9308 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9309 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9310 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9311 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
9312 BinOps.push_back(BinOp.getOperand(i));
9314 // We have an input that is not a truncation or another binary
9315 // operation; we'll abort this transformation.
9321 // The operands of a select that must be truncated when the select is
9322 // promoted because the operand is actually part of the to-be-promoted set.
9323 DenseMap<SDNode *, EVT> SelectTruncOp[2];
9325 // Make sure that this is a self-contained cluster of operations (which
9326 // is not quite the same thing as saying that everything has only one
9328 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9329 if (isa<ConstantSDNode>(Inputs[i]))
9332 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9333 UE = Inputs[i].getNode()->use_end();
9336 if (User != N && !Visited.count(User))
9339 // If we're going to promote the non-output-value operand(s) or SELECT or
9340 // SELECT_CC, record them for truncation.
9341 if (User->getOpcode() == ISD::SELECT) {
9342 if (User->getOperand(0) == Inputs[i])
9343 SelectTruncOp[0].insert(std::make_pair(User,
9344 User->getOperand(0).getValueType()));
9345 } else if (User->getOpcode() == ISD::SELECT_CC) {
9346 if (User->getOperand(0) == Inputs[i])
9347 SelectTruncOp[0].insert(std::make_pair(User,
9348 User->getOperand(0).getValueType()));
9349 if (User->getOperand(1) == Inputs[i])
9350 SelectTruncOp[1].insert(std::make_pair(User,
9351 User->getOperand(1).getValueType()));
9356 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9357 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9358 UE = PromOps[i].getNode()->use_end();
9361 if (User != N && !Visited.count(User))
9364 // If we're going to promote the non-output-value operand(s) or SELECT or
9365 // SELECT_CC, record them for truncation.
9366 if (User->getOpcode() == ISD::SELECT) {
9367 if (User->getOperand(0) == PromOps[i])
9368 SelectTruncOp[0].insert(std::make_pair(User,
9369 User->getOperand(0).getValueType()));
9370 } else if (User->getOpcode() == ISD::SELECT_CC) {
9371 if (User->getOperand(0) == PromOps[i])
9372 SelectTruncOp[0].insert(std::make_pair(User,
9373 User->getOperand(0).getValueType()));
9374 if (User->getOperand(1) == PromOps[i])
9375 SelectTruncOp[1].insert(std::make_pair(User,
9376 User->getOperand(1).getValueType()));
9381 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
9382 bool ReallyNeedsExt = false;
9383 if (N->getOpcode() != ISD::ANY_EXTEND) {
9384 // If all of the inputs are not already sign/zero extended, then
9385 // we'll still need to do that at the end.
9386 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9387 if (isa<ConstantSDNode>(Inputs[i]))
9391 Inputs[i].getOperand(0).getValueSizeInBits();
9392 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
9394 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
9395 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
9396 APInt::getHighBitsSet(OpBits,
9397 OpBits-PromBits))) ||
9398 (N->getOpcode() == ISD::SIGN_EXTEND &&
9399 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
9400 (OpBits-(PromBits-1)))) {
9401 ReallyNeedsExt = true;
9407 // Replace all inputs, either with the truncation operand, or a
9408 // truncation or extension to the final output type.
9409 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9410 // Constant inputs need to be replaced with the to-be-promoted nodes that
9411 // use them because they might have users outside of the cluster of
9413 if (isa<ConstantSDNode>(Inputs[i]))
9416 SDValue InSrc = Inputs[i].getOperand(0);
9417 if (Inputs[i].getValueType() == N->getValueType(0))
9418 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
9419 else if (N->getOpcode() == ISD::SIGN_EXTEND)
9420 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9421 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
9422 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9423 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9424 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
9426 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9427 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
9430 // Replace all operations (these are all the same, but have a different
9431 // (promoted) return type). DAG.getNode will validate that the types of
9432 // a binary operator match, so go through the list in reverse so that
9433 // we've likely promoted both operands first.
9434 while (!PromOps.empty()) {
9435 SDValue PromOp = PromOps.back();
9439 switch (PromOp.getOpcode()) {
9440 default: C = 0; break;
9441 case ISD::SELECT: C = 1; break;
9442 case ISD::SELECT_CC: C = 2; break;
9445 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9446 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
9447 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9448 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
9449 // The to-be-promoted operands of this node have not yet been
9450 // promoted (this should be rare because we're going through the
9451 // list backward, but if one of the operands has several users in
9452 // this cluster of to-be-promoted nodes, it is possible).
9453 PromOps.insert(PromOps.begin(), PromOp);
9457 // For SELECT and SELECT_CC nodes, we do a similar check for any
9458 // to-be-promoted comparison inputs.
9459 if (PromOp.getOpcode() == ISD::SELECT ||
9460 PromOp.getOpcode() == ISD::SELECT_CC) {
9461 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
9462 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
9463 (SelectTruncOp[1].count(PromOp.getNode()) &&
9464 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
9465 PromOps.insert(PromOps.begin(), PromOp);
9470 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9471 PromOp.getNode()->op_end());
9473 // If this node has constant inputs, then they'll need to be promoted here.
9474 for (unsigned i = 0; i < 2; ++i) {
9475 if (!isa<ConstantSDNode>(Ops[C+i]))
9477 if (Ops[C+i].getValueType() == N->getValueType(0))
9480 if (N->getOpcode() == ISD::SIGN_EXTEND)
9481 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9482 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9483 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9485 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9488 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
9489 // truncate them again to the original value type.
9490 if (PromOp.getOpcode() == ISD::SELECT ||
9491 PromOp.getOpcode() == ISD::SELECT_CC) {
9492 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
9493 if (SI0 != SelectTruncOp[0].end())
9494 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
9495 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
9496 if (SI1 != SelectTruncOp[1].end())
9497 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
9500 DAG.ReplaceAllUsesOfValueWith(PromOp,
9501 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
9504 // Now we're left with the initial extension itself.
9505 if (!ReallyNeedsExt)
9506 return N->getOperand(0);
9508 // To zero extend, just mask off everything except for the first bit (in the
9510 if (N->getOpcode() == ISD::ZERO_EXTEND)
9511 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
9512 DAG.getConstant(APInt::getLowBitsSet(
9513 N->getValueSizeInBits(0), PromBits),
9514 N->getValueType(0)));
9516 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
9517 "Invalid extension type");
9518 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
9520 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
9521 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
9522 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
9523 N->getOperand(0), ShiftCst), ShiftCst);
9526 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
9527 DAGCombinerInfo &DCI) const {
9528 assert((N->getOpcode() == ISD::SINT_TO_FP ||
9529 N->getOpcode() == ISD::UINT_TO_FP) &&
9530 "Need an int -> FP conversion node here");
9532 if (!Subtarget.has64BitSupport())
9535 SelectionDAG &DAG = DCI.DAG;
9539 // Don't handle ppc_fp128 here or i1 conversions.
9540 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
9542 if (Op.getOperand(0).getValueType() == MVT::i1)
9545 // For i32 intermediate values, unfortunately, the conversion functions
9546 // leave the upper 32 bits of the value are undefined. Within the set of
9547 // scalar instructions, we have no method for zero- or sign-extending the
9548 // value. Thus, we cannot handle i32 intermediate values here.
9549 if (Op.getOperand(0).getValueType() == MVT::i32)
9552 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
9553 "UINT_TO_FP is supported only with FPCVT");
9555 // If we have FCFIDS, then use it when converting to single-precision.
9556 // Otherwise, convert to double-precision and then round.
9557 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
9558 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
9560 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
9562 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
9566 // If we're converting from a float, to an int, and back to a float again,
9567 // then we don't need the store/load pair at all.
9568 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
9569 Subtarget.hasFPCVT()) ||
9570 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
9571 SDValue Src = Op.getOperand(0).getOperand(0);
9572 if (Src.getValueType() == MVT::f32) {
9573 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
9574 DCI.AddToWorklist(Src.getNode());
9578 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
9581 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
9582 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
9584 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
9585 FP = DAG.getNode(ISD::FP_ROUND, dl,
9586 MVT::f32, FP, DAG.getIntPtrConstant(0));
9587 DCI.AddToWorklist(FP.getNode());
9596 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
9597 // builtins) into loads with swaps.
9598 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
9599 DAGCombinerInfo &DCI) const {
9600 SelectionDAG &DAG = DCI.DAG;
9604 MachineMemOperand *MMO;
9606 switch (N->getOpcode()) {
9608 llvm_unreachable("Unexpected opcode for little endian VSX load");
9610 LoadSDNode *LD = cast<LoadSDNode>(N);
9611 Chain = LD->getChain();
9612 Base = LD->getBasePtr();
9613 MMO = LD->getMemOperand();
9614 // If the MMO suggests this isn't a load of a full vector, leave
9615 // things alone. For a built-in, we have to make the change for
9616 // correctness, so if there is a size problem that will be a bug.
9617 if (MMO->getSize() < 16)
9621 case ISD::INTRINSIC_W_CHAIN: {
9622 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
9623 Chain = Intrin->getChain();
9624 Base = Intrin->getBasePtr();
9625 MMO = Intrin->getMemOperand();
9630 MVT VecTy = N->getValueType(0).getSimpleVT();
9631 SDValue LoadOps[] = { Chain, Base };
9632 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
9633 DAG.getVTList(VecTy, MVT::Other),
9634 LoadOps, VecTy, MMO);
9635 DCI.AddToWorklist(Load.getNode());
9636 Chain = Load.getValue(1);
9637 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
9638 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
9639 DCI.AddToWorklist(Swap.getNode());
9643 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
9644 // builtins) into stores with swaps.
9645 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
9646 DAGCombinerInfo &DCI) const {
9647 SelectionDAG &DAG = DCI.DAG;
9652 MachineMemOperand *MMO;
9654 switch (N->getOpcode()) {
9656 llvm_unreachable("Unexpected opcode for little endian VSX store");
9658 StoreSDNode *ST = cast<StoreSDNode>(N);
9659 Chain = ST->getChain();
9660 Base = ST->getBasePtr();
9661 MMO = ST->getMemOperand();
9663 // If the MMO suggests this isn't a store of a full vector, leave
9664 // things alone. For a built-in, we have to make the change for
9665 // correctness, so if there is a size problem that will be a bug.
9666 if (MMO->getSize() < 16)
9670 case ISD::INTRINSIC_VOID: {
9671 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
9672 Chain = Intrin->getChain();
9673 // Intrin->getBasePtr() oddly does not get what we want.
9674 Base = Intrin->getOperand(3);
9675 MMO = Intrin->getMemOperand();
9681 SDValue Src = N->getOperand(SrcOpnd);
9682 MVT VecTy = Src.getValueType().getSimpleVT();
9683 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
9684 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
9685 DCI.AddToWorklist(Swap.getNode());
9686 Chain = Swap.getValue(1);
9687 SDValue StoreOps[] = { Chain, Swap, Base };
9688 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
9689 DAG.getVTList(MVT::Other),
9690 StoreOps, VecTy, MMO);
9691 DCI.AddToWorklist(Store.getNode());
9695 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
9696 DAGCombinerInfo &DCI) const {
9697 SelectionDAG &DAG = DCI.DAG;
9699 switch (N->getOpcode()) {
9702 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9703 if (C->isNullValue()) // 0 << V -> 0.
9704 return N->getOperand(0);
9708 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9709 if (C->isNullValue()) // 0 >>u V -> 0.
9710 return N->getOperand(0);
9714 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
9715 if (C->isNullValue() || // 0 >>s V -> 0.
9716 C->isAllOnesValue()) // -1 >>s V -> -1.
9717 return N->getOperand(0);
9720 case ISD::SIGN_EXTEND:
9721 case ISD::ZERO_EXTEND:
9722 case ISD::ANY_EXTEND:
9723 return DAGCombineExtBoolTrunc(N, DCI);
9726 case ISD::SELECT_CC:
9727 return DAGCombineTruncBoolExt(N, DCI);
9728 case ISD::SINT_TO_FP:
9729 case ISD::UINT_TO_FP:
9730 return combineFPToIntToFP(N, DCI);
9732 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
9733 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() &&
9734 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
9735 N->getOperand(1).getValueType() == MVT::i32 &&
9736 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
9737 SDValue Val = N->getOperand(1).getOperand(0);
9738 if (Val.getValueType() == MVT::f32) {
9739 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
9740 DCI.AddToWorklist(Val.getNode());
9742 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
9743 DCI.AddToWorklist(Val.getNode());
9746 N->getOperand(0), Val, N->getOperand(2),
9747 DAG.getValueType(N->getOperand(1).getValueType())
9750 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
9751 DAG.getVTList(MVT::Other), Ops,
9752 cast<StoreSDNode>(N)->getMemoryVT(),
9753 cast<StoreSDNode>(N)->getMemOperand());
9754 DCI.AddToWorklist(Val.getNode());
9758 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
9759 if (cast<StoreSDNode>(N)->isUnindexed() &&
9760 N->getOperand(1).getOpcode() == ISD::BSWAP &&
9761 N->getOperand(1).getNode()->hasOneUse() &&
9762 (N->getOperand(1).getValueType() == MVT::i32 ||
9763 N->getOperand(1).getValueType() == MVT::i16 ||
9764 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
9765 N->getOperand(1).getValueType() == MVT::i64))) {
9766 SDValue BSwapOp = N->getOperand(1).getOperand(0);
9767 // Do an any-extend to 32-bits if this is a half-word input.
9768 if (BSwapOp.getValueType() == MVT::i16)
9769 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
9772 N->getOperand(0), BSwapOp, N->getOperand(2),
9773 DAG.getValueType(N->getOperand(1).getValueType())
9776 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
9777 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
9778 cast<StoreSDNode>(N)->getMemOperand());
9781 // For little endian, VSX stores require generating xxswapd/lxvd2x.
9782 EVT VT = N->getOperand(1).getValueType();
9783 if (VT.isSimple()) {
9784 MVT StoreVT = VT.getSimpleVT();
9785 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
9786 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
9787 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
9788 return expandVSXStoreForLE(N, DCI);
9793 LoadSDNode *LD = cast<LoadSDNode>(N);
9794 EVT VT = LD->getValueType(0);
9796 // For little endian, VSX loads require generating lxvd2x/xxswapd.
9797 if (VT.isSimple()) {
9798 MVT LoadVT = VT.getSimpleVT();
9799 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
9800 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
9801 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
9802 return expandVSXLoadForLE(N, DCI);
9805 EVT MemVT = LD->getMemoryVT();
9806 Type *Ty = MemVT.getTypeForEVT(*DAG.getContext());
9807 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
9808 Type *STy = MemVT.getScalarType().getTypeForEVT(*DAG.getContext());
9809 unsigned ScalarABIAlignment = getDataLayout()->getABITypeAlignment(STy);
9810 if (LD->isUnindexed() && VT.isVector() &&
9811 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) &&
9812 // P8 and later hardware should just use LOAD.
9813 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 ||
9814 VT == MVT::v4i32 || VT == MVT::v4f32)) ||
9815 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) &&
9816 LD->getAlignment() >= ScalarABIAlignment)) &&
9817 LD->getAlignment() < ABIAlignment) {
9818 // This is a type-legal unaligned Altivec or QPX load.
9819 SDValue Chain = LD->getChain();
9820 SDValue Ptr = LD->getBasePtr();
9821 bool isLittleEndian = Subtarget.isLittleEndian();
9823 // This implements the loading of unaligned vectors as described in
9824 // the venerable Apple Velocity Engine overview. Specifically:
9825 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
9826 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
9828 // The general idea is to expand a sequence of one or more unaligned
9829 // loads into an alignment-based permutation-control instruction (lvsl
9830 // or lvsr), a series of regular vector loads (which always truncate
9831 // their input address to an aligned address), and a series of
9832 // permutations. The results of these permutations are the requested
9833 // loaded values. The trick is that the last "extra" load is not taken
9834 // from the address you might suspect (sizeof(vector) bytes after the
9835 // last requested load), but rather sizeof(vector) - 1 bytes after the
9836 // last requested vector. The point of this is to avoid a page fault if
9837 // the base address happened to be aligned. This works because if the
9838 // base address is aligned, then adding less than a full vector length
9839 // will cause the last vector in the sequence to be (re)loaded.
9840 // Otherwise, the next vector will be fetched as you might suspect was
9843 // We might be able to reuse the permutation generation from
9844 // a different base address offset from this one by an aligned amount.
9845 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
9846 // optimization later.
9847 Intrinsic::ID Intr, IntrLD, IntrPerm;
9848 MVT PermCntlTy, PermTy, LDTy;
9849 if (Subtarget.hasAltivec()) {
9850 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr :
9851 Intrinsic::ppc_altivec_lvsl;
9852 IntrLD = Intrinsic::ppc_altivec_lvx;
9853 IntrPerm = Intrinsic::ppc_altivec_vperm;
9854 PermCntlTy = MVT::v16i8;
9855 PermTy = MVT::v4i32;
9858 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld :
9859 Intrinsic::ppc_qpx_qvlpcls;
9860 IntrLD = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlfd :
9861 Intrinsic::ppc_qpx_qvlfs;
9862 IntrPerm = Intrinsic::ppc_qpx_qvfperm;
9863 PermCntlTy = MVT::v4f64;
9864 PermTy = MVT::v4f64;
9865 LDTy = MemVT.getSimpleVT();
9868 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, PermCntlTy);
9870 // Create the new MMO for the new base load. It is like the original MMO,
9871 // but represents an area in memory almost twice the vector size centered
9872 // on the original address. If the address is unaligned, we might start
9873 // reading up to (sizeof(vector)-1) bytes below the address of the
9874 // original unaligned load.
9875 MachineFunction &MF = DAG.getMachineFunction();
9876 MachineMemOperand *BaseMMO =
9877 MF.getMachineMemOperand(LD->getMemOperand(), -MemVT.getStoreSize()+1,
9878 2*MemVT.getStoreSize()-1);
9880 // Create the new base load.
9881 SDValue LDXIntID = DAG.getTargetConstant(IntrLD, getPointerTy());
9882 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
9884 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
9885 DAG.getVTList(PermTy, MVT::Other),
9886 BaseLoadOps, LDTy, BaseMMO);
9888 // Note that the value of IncOffset (which is provided to the next
9889 // load's pointer info offset value, and thus used to calculate the
9890 // alignment), and the value of IncValue (which is actually used to
9891 // increment the pointer value) are different! This is because we
9892 // require the next load to appear to be aligned, even though it
9893 // is actually offset from the base pointer by a lesser amount.
9894 int IncOffset = VT.getSizeInBits() / 8;
9895 int IncValue = IncOffset;
9897 // Walk (both up and down) the chain looking for another load at the real
9898 // (aligned) offset (the alignment of the other load does not matter in
9899 // this case). If found, then do not use the offset reduction trick, as
9900 // that will prevent the loads from being later combined (as they would
9901 // otherwise be duplicates).
9902 if (!findConsecutiveLoad(LD, DAG))
9905 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
9906 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
9908 MachineMemOperand *ExtraMMO =
9909 MF.getMachineMemOperand(LD->getMemOperand(),
9910 1, 2*MemVT.getStoreSize()-1);
9911 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
9913 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
9914 DAG.getVTList(PermTy, MVT::Other),
9915 ExtraLoadOps, LDTy, ExtraMMO);
9917 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
9918 BaseLoad.getValue(1), ExtraLoad.getValue(1));
9920 // Because vperm has a big-endian bias, we must reverse the order
9921 // of the input vectors and complement the permute control vector
9922 // when generating little endian code. We have already handled the
9923 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
9924 // and ExtraLoad here.
9927 Perm = BuildIntrinsicOp(IntrPerm,
9928 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
9930 Perm = BuildIntrinsicOp(IntrPerm,
9931 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
9934 Perm = Subtarget.hasAltivec() ?
9935 DAG.getNode(ISD::BITCAST, dl, VT, Perm) :
9936 DAG.getNode(ISD::FP_ROUND, dl, VT, Perm, // QPX
9937 DAG.getTargetConstant(1, MVT::i64));
9938 // second argument is 1 because this rounding
9941 // The output of the permutation is our loaded result, the TokenFactor is
9943 DCI.CombineTo(N, Perm, TF);
9944 return SDValue(N, 0);
9948 case ISD::INTRINSIC_WO_CHAIN: {
9949 bool isLittleEndian = Subtarget.isLittleEndian();
9950 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
9951 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
9952 : Intrinsic::ppc_altivec_lvsl);
9954 IID == Intrinsic::ppc_qpx_qvlpcld ||
9955 IID == Intrinsic::ppc_qpx_qvlpcls) &&
9956 N->getOperand(1)->getOpcode() == ISD::ADD) {
9957 SDValue Add = N->getOperand(1);
9959 int Bits = IID == Intrinsic::ppc_qpx_qvlpcld ?
9960 5 /* 32 byte alignment */ : 4 /* 16 byte alignment */;
9962 if (DAG.MaskedValueIsZero(
9964 APInt::getAllOnesValue(Bits /* alignment */)
9966 Add.getValueType().getScalarType().getSizeInBits()))) {
9967 SDNode *BasePtr = Add->getOperand(0).getNode();
9968 for (SDNode::use_iterator UI = BasePtr->use_begin(),
9969 UE = BasePtr->use_end();
9971 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
9972 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() == IID) {
9973 // We've found another LVSL/LVSR, and this address is an aligned
9974 // multiple of that one. The results will be the same, so use the
9975 // one we've just found instead.
9977 return SDValue(*UI, 0);
9982 if (isa<ConstantSDNode>(Add->getOperand(1))) {
9983 SDNode *BasePtr = Add->getOperand(0).getNode();
9984 for (SDNode::use_iterator UI = BasePtr->use_begin(),
9985 UE = BasePtr->use_end(); UI != UE; ++UI) {
9986 if (UI->getOpcode() == ISD::ADD &&
9987 isa<ConstantSDNode>(UI->getOperand(1)) &&
9988 (cast<ConstantSDNode>(Add->getOperand(1))->getZExtValue() -
9989 cast<ConstantSDNode>(UI->getOperand(1))->getZExtValue()) %
9991 SDNode *OtherAdd = *UI;
9992 for (SDNode::use_iterator VI = OtherAdd->use_begin(),
9993 VE = OtherAdd->use_end(); VI != VE; ++VI) {
9994 if (VI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
9995 cast<ConstantSDNode>(VI->getOperand(0))->getZExtValue() == IID) {
9996 return SDValue(*VI, 0);
10006 case ISD::INTRINSIC_W_CHAIN: {
10007 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10008 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10009 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10012 case Intrinsic::ppc_vsx_lxvw4x:
10013 case Intrinsic::ppc_vsx_lxvd2x:
10014 return expandVSXLoadForLE(N, DCI);
10019 case ISD::INTRINSIC_VOID: {
10020 // For little endian, VSX stores require generating xxswapd/stxvd2x.
10021 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10022 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10025 case Intrinsic::ppc_vsx_stxvw4x:
10026 case Intrinsic::ppc_vsx_stxvd2x:
10027 return expandVSXStoreForLE(N, DCI);
10033 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
10034 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
10035 N->getOperand(0).hasOneUse() &&
10036 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
10037 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10038 N->getValueType(0) == MVT::i64))) {
10039 SDValue Load = N->getOperand(0);
10040 LoadSDNode *LD = cast<LoadSDNode>(Load);
10041 // Create the byte-swapping load.
10043 LD->getChain(), // Chain
10044 LD->getBasePtr(), // Ptr
10045 DAG.getValueType(N->getValueType(0)) // VT
10048 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
10049 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
10050 MVT::i64 : MVT::i32, MVT::Other),
10051 Ops, LD->getMemoryVT(), LD->getMemOperand());
10053 // If this is an i16 load, insert the truncate.
10054 SDValue ResVal = BSLoad;
10055 if (N->getValueType(0) == MVT::i16)
10056 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
10058 // First, combine the bswap away. This makes the value produced by the
10060 DCI.CombineTo(N, ResVal);
10062 // Next, combine the load away, we give it a bogus result value but a real
10063 // chain result. The result value is dead because the bswap is dead.
10064 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
10066 // Return N so it doesn't get rechecked!
10067 return SDValue(N, 0);
10071 case PPCISD::VCMP: {
10072 // If a VCMPo node already exists with exactly the same operands as this
10073 // node, use its result instead of this node (VCMPo computes both a CR6 and
10074 // a normal output).
10076 if (!N->getOperand(0).hasOneUse() &&
10077 !N->getOperand(1).hasOneUse() &&
10078 !N->getOperand(2).hasOneUse()) {
10080 // Scan all of the users of the LHS, looking for VCMPo's that match.
10081 SDNode *VCMPoNode = nullptr;
10083 SDNode *LHSN = N->getOperand(0).getNode();
10084 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
10086 if (UI->getOpcode() == PPCISD::VCMPo &&
10087 UI->getOperand(1) == N->getOperand(1) &&
10088 UI->getOperand(2) == N->getOperand(2) &&
10089 UI->getOperand(0) == N->getOperand(0)) {
10094 // If there is no VCMPo node, or if the flag value has a single use, don't
10096 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
10099 // Look at the (necessarily single) use of the flag value. If it has a
10100 // chain, this transformation is more complex. Note that multiple things
10101 // could use the value result, which we should ignore.
10102 SDNode *FlagUser = nullptr;
10103 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
10104 FlagUser == nullptr; ++UI) {
10105 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
10106 SDNode *User = *UI;
10107 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
10108 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
10115 // If the user is a MFOCRF instruction, we know this is safe.
10116 // Otherwise we give up for right now.
10117 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
10118 return SDValue(VCMPoNode, 0);
10122 case ISD::BRCOND: {
10123 SDValue Cond = N->getOperand(1);
10124 SDValue Target = N->getOperand(2);
10126 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10127 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
10128 Intrinsic::ppc_is_decremented_ctr_nonzero) {
10130 // We now need to make the intrinsic dead (it cannot be instruction
10132 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
10133 assert(Cond.getNode()->hasOneUse() &&
10134 "Counter decrement has more than one use");
10136 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
10137 N->getOperand(0), Target);
10142 // If this is a branch on an altivec predicate comparison, lower this so
10143 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
10144 // lowering is done pre-legalize, because the legalizer lowers the predicate
10145 // compare down to code that is difficult to reassemble.
10146 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
10147 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
10149 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
10150 // value. If so, pass-through the AND to get to the intrinsic.
10151 if (LHS.getOpcode() == ISD::AND &&
10152 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10153 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
10154 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10155 isa<ConstantSDNode>(LHS.getOperand(1)) &&
10156 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
10158 LHS = LHS.getOperand(0);
10160 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10161 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
10162 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10163 isa<ConstantSDNode>(RHS)) {
10164 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
10165 "Counter decrement comparison is not EQ or NE");
10167 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10168 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
10169 (CC == ISD::SETNE && !Val);
10171 // We now need to make the intrinsic dead (it cannot be instruction
10173 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
10174 assert(LHS.getNode()->hasOneUse() &&
10175 "Counter decrement has more than one use");
10177 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
10178 N->getOperand(0), N->getOperand(4));
10184 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10185 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
10186 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
10187 assert(isDot && "Can't compare against a vector result!");
10189 // If this is a comparison against something other than 0/1, then we know
10190 // that the condition is never/always true.
10191 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10192 if (Val != 0 && Val != 1) {
10193 if (CC == ISD::SETEQ) // Cond never true, remove branch.
10194 return N->getOperand(0);
10195 // Always !=, turn it into an unconditional branch.
10196 return DAG.getNode(ISD::BR, dl, MVT::Other,
10197 N->getOperand(0), N->getOperand(4));
10200 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
10202 // Create the PPCISD altivec 'dot' comparison node.
10204 LHS.getOperand(2), // LHS of compare
10205 LHS.getOperand(3), // RHS of compare
10206 DAG.getConstant(CompareOpc, MVT::i32)
10208 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
10209 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
10211 // Unpack the result based on how the target uses it.
10212 PPC::Predicate CompOpc;
10213 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
10214 default: // Can't happen, don't crash on invalid number though.
10215 case 0: // Branch on the value of the EQ bit of CR6.
10216 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
10218 case 1: // Branch on the inverted value of the EQ bit of CR6.
10219 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
10221 case 2: // Branch on the value of the LT bit of CR6.
10222 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
10224 case 3: // Branch on the inverted value of the LT bit of CR6.
10225 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
10229 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
10230 DAG.getConstant(CompOpc, MVT::i32),
10231 DAG.getRegister(PPC::CR6, MVT::i32),
10232 N->getOperand(4), CompNode.getValue(1));
10242 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
10244 std::vector<SDNode *> *Created) const {
10245 // fold (sdiv X, pow2)
10246 EVT VT = N->getValueType(0);
10247 if (VT == MVT::i64 && !Subtarget.isPPC64())
10249 if ((VT != MVT::i32 && VT != MVT::i64) ||
10250 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
10254 SDValue N0 = N->getOperand(0);
10256 bool IsNegPow2 = (-Divisor).isPowerOf2();
10257 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
10258 SDValue ShiftAmt = DAG.getConstant(Lg2, VT);
10260 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
10262 Created->push_back(Op.getNode());
10265 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), Op);
10267 Created->push_back(Op.getNode());
10273 //===----------------------------------------------------------------------===//
10274 // Inline Assembly Support
10275 //===----------------------------------------------------------------------===//
10277 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10280 const SelectionDAG &DAG,
10281 unsigned Depth) const {
10282 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
10283 switch (Op.getOpcode()) {
10285 case PPCISD::LBRX: {
10286 // lhbrx is known to have the top bits cleared out.
10287 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
10288 KnownZero = 0xFFFF0000;
10291 case ISD::INTRINSIC_WO_CHAIN: {
10292 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
10294 case Intrinsic::ppc_altivec_vcmpbfp_p:
10295 case Intrinsic::ppc_altivec_vcmpeqfp_p:
10296 case Intrinsic::ppc_altivec_vcmpequb_p:
10297 case Intrinsic::ppc_altivec_vcmpequh_p:
10298 case Intrinsic::ppc_altivec_vcmpequw_p:
10299 case Intrinsic::ppc_altivec_vcmpgefp_p:
10300 case Intrinsic::ppc_altivec_vcmpgtfp_p:
10301 case Intrinsic::ppc_altivec_vcmpgtsb_p:
10302 case Intrinsic::ppc_altivec_vcmpgtsh_p:
10303 case Intrinsic::ppc_altivec_vcmpgtsw_p:
10304 case Intrinsic::ppc_altivec_vcmpgtub_p:
10305 case Intrinsic::ppc_altivec_vcmpgtuh_p:
10306 case Intrinsic::ppc_altivec_vcmpgtuw_p:
10307 KnownZero = ~1U; // All bits but the low one are known to be zero.
10314 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
10315 switch (Subtarget.getDarwinDirective()) {
10318 case PPC::DIR_PWR4:
10319 case PPC::DIR_PWR5:
10320 case PPC::DIR_PWR5X:
10321 case PPC::DIR_PWR6:
10322 case PPC::DIR_PWR6X:
10323 case PPC::DIR_PWR7:
10324 case PPC::DIR_PWR8: {
10328 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
10330 // For small loops (between 5 and 8 instructions), align to a 32-byte
10331 // boundary so that the entire loop fits in one instruction-cache line.
10332 uint64_t LoopSize = 0;
10333 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
10334 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
10335 LoopSize += TII->GetInstSizeInBytes(J);
10337 if (LoopSize > 16 && LoopSize <= 32)
10344 return TargetLowering::getPrefLoopAlignment(ML);
10347 /// getConstraintType - Given a constraint, return the type of
10348 /// constraint it is for this target.
10349 PPCTargetLowering::ConstraintType
10350 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
10351 if (Constraint.size() == 1) {
10352 switch (Constraint[0]) {
10359 return C_RegisterClass;
10361 // FIXME: While Z does indicate a memory constraint, it specifically
10362 // indicates an r+r address (used in conjunction with the 'y' modifier
10363 // in the replacement string). Currently, we're forcing the base
10364 // register to be r0 in the asm printer (which is interpreted as zero)
10365 // and forming the complete address in the second register. This is
10369 } else if (Constraint == "wc") { // individual CR bits.
10370 return C_RegisterClass;
10371 } else if (Constraint == "wa" || Constraint == "wd" ||
10372 Constraint == "wf" || Constraint == "ws") {
10373 return C_RegisterClass; // VSX registers.
10375 return TargetLowering::getConstraintType(Constraint);
10378 /// Examine constraint type and operand type and determine a weight value.
10379 /// This object must already have been set up with the operand type
10380 /// and the current alternative constraint selected.
10381 TargetLowering::ConstraintWeight
10382 PPCTargetLowering::getSingleConstraintMatchWeight(
10383 AsmOperandInfo &info, const char *constraint) const {
10384 ConstraintWeight weight = CW_Invalid;
10385 Value *CallOperandVal = info.CallOperandVal;
10386 // If we don't have a value, we can't do a match,
10387 // but allow it at the lowest weight.
10388 if (!CallOperandVal)
10390 Type *type = CallOperandVal->getType();
10392 // Look at the constraint type.
10393 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
10394 return CW_Register; // an individual CR bit.
10395 else if ((StringRef(constraint) == "wa" ||
10396 StringRef(constraint) == "wd" ||
10397 StringRef(constraint) == "wf") &&
10398 type->isVectorTy())
10399 return CW_Register;
10400 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
10401 return CW_Register;
10403 switch (*constraint) {
10405 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10408 if (type->isIntegerTy())
10409 weight = CW_Register;
10412 if (type->isFloatTy())
10413 weight = CW_Register;
10416 if (type->isDoubleTy())
10417 weight = CW_Register;
10420 if (type->isVectorTy())
10421 weight = CW_Register;
10424 weight = CW_Register;
10427 weight = CW_Memory;
10433 std::pair<unsigned, const TargetRegisterClass*>
10434 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
10436 if (Constraint.size() == 1) {
10437 // GCC RS6000 Constraint Letters
10438 switch (Constraint[0]) {
10439 case 'b': // R1-R31
10440 if (VT == MVT::i64 && Subtarget.isPPC64())
10441 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
10442 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
10443 case 'r': // R0-R31
10444 if (VT == MVT::i64 && Subtarget.isPPC64())
10445 return std::make_pair(0U, &PPC::G8RCRegClass);
10446 return std::make_pair(0U, &PPC::GPRCRegClass);
10448 if (VT == MVT::f32 || VT == MVT::i32)
10449 return std::make_pair(0U, &PPC::F4RCRegClass);
10450 if (VT == MVT::f64 || VT == MVT::i64)
10451 return std::make_pair(0U, &PPC::F8RCRegClass);
10452 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10453 return std::make_pair(0U, &PPC::QFRCRegClass);
10454 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10455 return std::make_pair(0U, &PPC::QSRCRegClass);
10458 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10459 return std::make_pair(0U, &PPC::QFRCRegClass);
10460 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10461 return std::make_pair(0U, &PPC::QSRCRegClass);
10462 return std::make_pair(0U, &PPC::VRRCRegClass);
10464 return std::make_pair(0U, &PPC::CRRCRegClass);
10466 } else if (Constraint == "wc") { // an individual CR bit.
10467 return std::make_pair(0U, &PPC::CRBITRCRegClass);
10468 } else if (Constraint == "wa" || Constraint == "wd" ||
10469 Constraint == "wf") {
10470 return std::make_pair(0U, &PPC::VSRCRegClass);
10471 } else if (Constraint == "ws") {
10472 return std::make_pair(0U, &PPC::VSFRCRegClass);
10475 std::pair<unsigned, const TargetRegisterClass*> R =
10476 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
10478 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
10479 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
10480 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
10482 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
10483 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
10484 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
10485 PPC::GPRCRegClass.contains(R.first)) {
10486 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
10487 return std::make_pair(TRI->getMatchingSuperReg(R.first,
10488 PPC::sub_32, &PPC::G8RCRegClass),
10489 &PPC::G8RCRegClass);
10492 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
10493 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
10494 R.first = PPC::CR0;
10495 R.second = &PPC::CRRCRegClass;
10502 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10503 /// vector. If it is invalid, don't add anything to Ops.
10504 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10505 std::string &Constraint,
10506 std::vector<SDValue>&Ops,
10507 SelectionDAG &DAG) const {
10510 // Only support length 1 constraints.
10511 if (Constraint.length() > 1) return;
10513 char Letter = Constraint[0];
10524 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
10525 if (!CST) return; // Must be an immediate to match.
10526 int64_t Value = CST->getSExtValue();
10527 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
10528 // numbers are printed as such.
10530 default: llvm_unreachable("Unknown constraint letter!");
10531 case 'I': // "I" is a signed 16-bit constant.
10532 if (isInt<16>(Value))
10533 Result = DAG.getTargetConstant(Value, TCVT);
10535 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
10536 if (isShiftedUInt<16, 16>(Value))
10537 Result = DAG.getTargetConstant(Value, TCVT);
10539 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
10540 if (isShiftedInt<16, 16>(Value))
10541 Result = DAG.getTargetConstant(Value, TCVT);
10543 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
10544 if (isUInt<16>(Value))
10545 Result = DAG.getTargetConstant(Value, TCVT);
10547 case 'M': // "M" is a constant that is greater than 31.
10549 Result = DAG.getTargetConstant(Value, TCVT);
10551 case 'N': // "N" is a positive constant that is an exact power of two.
10552 if (Value > 0 && isPowerOf2_64(Value))
10553 Result = DAG.getTargetConstant(Value, TCVT);
10555 case 'O': // "O" is the constant zero.
10557 Result = DAG.getTargetConstant(Value, TCVT);
10559 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
10560 if (isInt<16>(-Value))
10561 Result = DAG.getTargetConstant(Value, TCVT);
10568 if (Result.getNode()) {
10569 Ops.push_back(Result);
10573 // Handle standard constraint letters.
10574 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
10577 // isLegalAddressingMode - Return true if the addressing mode represented
10578 // by AM is legal for this target, for a load/store of the specified type.
10579 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
10581 // PPC does not allow r+i addressing modes for vectors!
10582 if (Ty->isVectorTy() && AM.BaseOffs != 0)
10585 // PPC allows a sign-extended 16-bit immediate field.
10586 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
10589 // No global is ever allowed as a base.
10593 // PPC only support r+r,
10594 switch (AM.Scale) {
10595 case 0: // "r+i" or just "i", depending on HasBaseReg.
10598 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
10600 // Otherwise we have r+r or r+i.
10603 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
10605 // Allow 2*r as r+r.
10608 // No other scales are supported.
10615 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
10616 SelectionDAG &DAG) const {
10617 MachineFunction &MF = DAG.getMachineFunction();
10618 MachineFrameInfo *MFI = MF.getFrameInfo();
10619 MFI->setReturnAddressIsTaken(true);
10621 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
10625 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10627 // Make sure the function does not optimize away the store of the RA to
10629 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
10630 FuncInfo->setLRStoreRequired();
10631 bool isPPC64 = Subtarget.isPPC64();
10634 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
10636 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(),
10637 isPPC64 ? MVT::i64 : MVT::i32);
10638 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
10639 DAG.getNode(ISD::ADD, dl, getPointerTy(),
10640 FrameAddr, Offset),
10641 MachinePointerInfo(), false, false, false, 0);
10644 // Just load the return address off the stack.
10645 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
10646 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
10647 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
10650 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
10651 SelectionDAG &DAG) const {
10653 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
10655 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
10656 bool isPPC64 = PtrVT == MVT::i64;
10658 MachineFunction &MF = DAG.getMachineFunction();
10659 MachineFrameInfo *MFI = MF.getFrameInfo();
10660 MFI->setFrameAddressIsTaken(true);
10662 // Naked functions never have a frame pointer, and so we use r1. For all
10663 // other functions, this decision must be delayed until during PEI.
10665 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
10666 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
10668 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
10670 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
10673 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
10674 FrameAddr, MachinePointerInfo(), false, false,
10679 // FIXME? Maybe this could be a TableGen attribute on some registers and
10680 // this table could be generated automatically from RegInfo.
10681 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
10683 bool isPPC64 = Subtarget.isPPC64();
10684 bool isDarwinABI = Subtarget.isDarwinABI();
10686 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
10687 (!isPPC64 && VT != MVT::i32))
10688 report_fatal_error("Invalid register global variable type");
10690 bool is64Bit = isPPC64 && VT == MVT::i64;
10691 unsigned Reg = StringSwitch<unsigned>(RegName)
10692 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
10693 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2)
10694 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
10695 (is64Bit ? PPC::X13 : PPC::R13))
10700 report_fatal_error("Invalid register name global variable");
10704 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
10705 // The PowerPC target isn't yet aware of offsets.
10709 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
10711 unsigned Intrinsic) const {
10713 switch (Intrinsic) {
10714 case Intrinsic::ppc_qpx_qvlfd:
10715 case Intrinsic::ppc_qpx_qvlfs:
10716 case Intrinsic::ppc_qpx_qvlfcd:
10717 case Intrinsic::ppc_qpx_qvlfcs:
10718 case Intrinsic::ppc_qpx_qvlfiwa:
10719 case Intrinsic::ppc_qpx_qvlfiwz:
10720 case Intrinsic::ppc_altivec_lvx:
10721 case Intrinsic::ppc_altivec_lvxl:
10722 case Intrinsic::ppc_altivec_lvebx:
10723 case Intrinsic::ppc_altivec_lvehx:
10724 case Intrinsic::ppc_altivec_lvewx:
10725 case Intrinsic::ppc_vsx_lxvd2x:
10726 case Intrinsic::ppc_vsx_lxvw4x: {
10728 switch (Intrinsic) {
10729 case Intrinsic::ppc_altivec_lvebx:
10732 case Intrinsic::ppc_altivec_lvehx:
10735 case Intrinsic::ppc_altivec_lvewx:
10738 case Intrinsic::ppc_vsx_lxvd2x:
10741 case Intrinsic::ppc_qpx_qvlfd:
10744 case Intrinsic::ppc_qpx_qvlfs:
10747 case Intrinsic::ppc_qpx_qvlfcd:
10750 case Intrinsic::ppc_qpx_qvlfcs:
10758 Info.opc = ISD::INTRINSIC_W_CHAIN;
10760 Info.ptrVal = I.getArgOperand(0);
10761 Info.offset = -VT.getStoreSize()+1;
10762 Info.size = 2*VT.getStoreSize()-1;
10765 Info.readMem = true;
10766 Info.writeMem = false;
10769 case Intrinsic::ppc_qpx_qvlfda:
10770 case Intrinsic::ppc_qpx_qvlfsa:
10771 case Intrinsic::ppc_qpx_qvlfcda:
10772 case Intrinsic::ppc_qpx_qvlfcsa:
10773 case Intrinsic::ppc_qpx_qvlfiwaa:
10774 case Intrinsic::ppc_qpx_qvlfiwza: {
10776 switch (Intrinsic) {
10777 case Intrinsic::ppc_qpx_qvlfda:
10780 case Intrinsic::ppc_qpx_qvlfsa:
10783 case Intrinsic::ppc_qpx_qvlfcda:
10786 case Intrinsic::ppc_qpx_qvlfcsa:
10794 Info.opc = ISD::INTRINSIC_W_CHAIN;
10796 Info.ptrVal = I.getArgOperand(0);
10798 Info.size = VT.getStoreSize();
10801 Info.readMem = true;
10802 Info.writeMem = false;
10805 case Intrinsic::ppc_qpx_qvstfd:
10806 case Intrinsic::ppc_qpx_qvstfs:
10807 case Intrinsic::ppc_qpx_qvstfcd:
10808 case Intrinsic::ppc_qpx_qvstfcs:
10809 case Intrinsic::ppc_qpx_qvstfiw:
10810 case Intrinsic::ppc_altivec_stvx:
10811 case Intrinsic::ppc_altivec_stvxl:
10812 case Intrinsic::ppc_altivec_stvebx:
10813 case Intrinsic::ppc_altivec_stvehx:
10814 case Intrinsic::ppc_altivec_stvewx:
10815 case Intrinsic::ppc_vsx_stxvd2x:
10816 case Intrinsic::ppc_vsx_stxvw4x: {
10818 switch (Intrinsic) {
10819 case Intrinsic::ppc_altivec_stvebx:
10822 case Intrinsic::ppc_altivec_stvehx:
10825 case Intrinsic::ppc_altivec_stvewx:
10828 case Intrinsic::ppc_vsx_stxvd2x:
10831 case Intrinsic::ppc_qpx_qvstfd:
10834 case Intrinsic::ppc_qpx_qvstfs:
10837 case Intrinsic::ppc_qpx_qvstfcd:
10840 case Intrinsic::ppc_qpx_qvstfcs:
10848 Info.opc = ISD::INTRINSIC_VOID;
10850 Info.ptrVal = I.getArgOperand(1);
10851 Info.offset = -VT.getStoreSize()+1;
10852 Info.size = 2*VT.getStoreSize()-1;
10855 Info.readMem = false;
10856 Info.writeMem = true;
10859 case Intrinsic::ppc_qpx_qvstfda:
10860 case Intrinsic::ppc_qpx_qvstfsa:
10861 case Intrinsic::ppc_qpx_qvstfcda:
10862 case Intrinsic::ppc_qpx_qvstfcsa:
10863 case Intrinsic::ppc_qpx_qvstfiwa: {
10865 switch (Intrinsic) {
10866 case Intrinsic::ppc_qpx_qvstfda:
10869 case Intrinsic::ppc_qpx_qvstfsa:
10872 case Intrinsic::ppc_qpx_qvstfcda:
10875 case Intrinsic::ppc_qpx_qvstfcsa:
10883 Info.opc = ISD::INTRINSIC_VOID;
10885 Info.ptrVal = I.getArgOperand(1);
10887 Info.size = VT.getStoreSize();
10890 Info.readMem = false;
10891 Info.writeMem = true;
10901 /// getOptimalMemOpType - Returns the target specific optimal type for load
10902 /// and store operations as a result of memset, memcpy, and memmove
10903 /// lowering. If DstAlign is zero that means it's safe to destination
10904 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
10905 /// means there isn't a need to check it against alignment requirement,
10906 /// probably because the source does not need to be loaded. If 'IsMemset' is
10907 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
10908 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
10909 /// source is constant so it does not need to be loaded.
10910 /// It returns EVT::Other if the type should be determined using generic
10911 /// target-independent logic.
10912 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
10913 unsigned DstAlign, unsigned SrcAlign,
10914 bool IsMemset, bool ZeroMemset,
10916 MachineFunction &MF) const {
10917 if (Subtarget.isPPC64()) {
10924 /// \brief Returns true if it is beneficial to convert a load of a constant
10925 /// to just the constant itself.
10926 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
10928 assert(Ty->isIntegerTy());
10930 unsigned BitSize = Ty->getPrimitiveSizeInBits();
10931 if (BitSize == 0 || BitSize > 64)
10936 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
10937 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
10939 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
10940 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
10941 return NumBits1 == 64 && NumBits2 == 32;
10944 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
10945 if (!VT1.isInteger() || !VT2.isInteger())
10947 unsigned NumBits1 = VT1.getSizeInBits();
10948 unsigned NumBits2 = VT2.getSizeInBits();
10949 return NumBits1 == 64 && NumBits2 == 32;
10952 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
10953 // Generally speaking, zexts are not free, but they are free when they can be
10954 // folded with other operations.
10955 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
10956 EVT MemVT = LD->getMemoryVT();
10957 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
10958 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
10959 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
10960 LD->getExtensionType() == ISD::ZEXTLOAD))
10964 // FIXME: Add other cases...
10965 // - 32-bit shifts with a zext to i64
10966 // - zext after ctlz, bswap, etc.
10967 // - zext after and by a constant mask
10969 return TargetLowering::isZExtFree(Val, VT2);
10972 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
10973 assert(VT.isFloatingPoint());
10977 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
10978 return isInt<16>(Imm) || isUInt<16>(Imm);
10981 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
10982 return isInt<16>(Imm) || isUInt<16>(Imm);
10985 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
10988 bool *Fast) const {
10989 if (DisablePPCUnaligned)
10992 // PowerPC supports unaligned memory access for simple non-vector types.
10993 // Although accessing unaligned addresses is not as efficient as accessing
10994 // aligned addresses, it is generally more efficient than manual expansion,
10995 // and generally only traps for software emulation when crossing page
10998 if (!VT.isSimple())
11001 if (VT.getSimpleVT().isVector()) {
11002 if (Subtarget.hasVSX()) {
11003 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
11004 VT != MVT::v4f32 && VT != MVT::v4i32)
11011 if (VT == MVT::ppcf128)
11020 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
11021 VT = VT.getScalarType();
11023 if (!VT.isSimple())
11026 switch (VT.getSimpleVT().SimpleTy) {
11038 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
11039 // LR is a callee-save register, but we must treat it as clobbered by any call
11040 // site. Hence we include LR in the scratch registers, which are in turn added
11041 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
11042 // to CTR, which is used by any indirect call.
11043 static const MCPhysReg ScratchRegs[] = {
11044 PPC::X12, PPC::LR8, PPC::CTR8, 0
11047 return ScratchRegs;
11051 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
11052 EVT VT , unsigned DefinedValues) const {
11053 if (VT == MVT::v2i64)
11056 if (Subtarget.hasQPX()) {
11057 if (VT == MVT::v4f32 || VT == MVT::v4f64 || VT == MVT::v4i1)
11061 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
11064 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
11065 if (DisableILPPref || Subtarget.enableMachineScheduler())
11066 return TargetLowering::getSchedulingPreference(N);
11071 // Create a fast isel object.
11073 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
11074 const TargetLibraryInfo *LibInfo) const {
11075 return PPC::createFastISel(FuncInfo, LibInfo);