1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCTargetMachine.h"
16 #include "PPCPerfectShuffle.h"
17 #include "llvm/ADT/VectorExtras.h"
18 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Function.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Target/TargetOptions.h"
31 PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
32 : TargetLowering(TM) {
34 // Fold away setcc operations if possible.
35 setSetCCIsExpensive();
38 // Use _setjmp/_longjmp instead of setjmp/longjmp.
39 setUseUnderscoreSetJmpLongJmp(true);
41 // Set up the register classes.
42 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
43 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
44 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
46 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
47 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
49 // PowerPC has no intrinsics for these particular operations
50 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
51 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
52 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
54 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
55 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
56 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
58 // PowerPC has no SREM/UREM instructions
59 setOperationAction(ISD::SREM, MVT::i32, Expand);
60 setOperationAction(ISD::UREM, MVT::i32, Expand);
62 // We don't support sin/cos/sqrt/fmod
63 setOperationAction(ISD::FSIN , MVT::f64, Expand);
64 setOperationAction(ISD::FCOS , MVT::f64, Expand);
65 setOperationAction(ISD::FREM , MVT::f64, Expand);
66 setOperationAction(ISD::FSIN , MVT::f32, Expand);
67 setOperationAction(ISD::FCOS , MVT::f32, Expand);
68 setOperationAction(ISD::FREM , MVT::f32, Expand);
70 // If we're enabling GP optimizations, use hardware square root
71 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
72 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
73 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
76 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
77 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
79 // PowerPC does not have BSWAP, CTPOP or CTTZ
80 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
81 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
82 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
84 // PowerPC does not have ROTR
85 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
87 // PowerPC does not have Select
88 setOperationAction(ISD::SELECT, MVT::i32, Expand);
89 setOperationAction(ISD::SELECT, MVT::f32, Expand);
90 setOperationAction(ISD::SELECT, MVT::f64, Expand);
92 // PowerPC wants to turn select_cc of FP into fsel when possible.
93 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
94 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
96 // PowerPC wants to optimize integer setcc a bit
97 setOperationAction(ISD::SETCC, MVT::i32, Custom);
99 // PowerPC does not have BRCOND which requires SetCC
100 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
102 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
103 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
105 // PowerPC does not have [U|S]INT_TO_FP
106 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
109 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
110 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
112 // PowerPC does not have truncstore for i1.
113 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
115 // We cannot sextinreg(i1). Expand to shifts.
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
119 // Support label based line numbers.
120 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
121 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
122 // FIXME - use subtarget debug flags
123 if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
124 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
126 // We want to legalize GlobalAddress and ConstantPool nodes into the
127 // appropriate instructions to materialize the address.
128 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
129 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
130 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
131 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
132 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
133 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
135 // RET must be custom lowered, to meet ABI requirements
136 setOperationAction(ISD::RET , MVT::Other, Custom);
138 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
139 setOperationAction(ISD::VASTART , MVT::Other, Custom);
141 // Use the default implementation.
142 setOperationAction(ISD::VAARG , MVT::Other, Expand);
143 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
144 setOperationAction(ISD::VAEND , MVT::Other, Expand);
145 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
146 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
147 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
149 // We want to custom lower some of our intrinsics.
150 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
152 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
153 // They also have instructions for converting between i64 and fp.
154 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
155 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
157 // FIXME: disable this lowered code. This generates 64-bit register values,
158 // and we don't model the fact that the top part is clobbered by calls. We
159 // need to flag these together so that the value isn't live across a call.
160 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
162 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
163 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
165 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
166 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
169 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
170 // 64 bit PowerPC implementations can support i64 types directly
171 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
172 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
173 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
175 // 32 bit PowerPC wants to expand i64 shifts itself.
176 setOperationAction(ISD::SHL, MVT::i64, Custom);
177 setOperationAction(ISD::SRL, MVT::i64, Custom);
178 setOperationAction(ISD::SRA, MVT::i64, Custom);
181 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
182 // First set operation action for all vector types to expand. Then we
183 // will selectively turn on ones that can be effectively codegen'd.
184 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
185 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
186 // add/sub are legal for all supported vector VT's.
187 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
188 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
190 // We promote all shuffles to v16i8.
191 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
192 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
194 // We promote all non-typed operations to v4i32.
195 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
196 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
197 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
198 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
199 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
200 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
201 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
202 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
203 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
204 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
205 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
206 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
208 // No other operations are legal.
209 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
210 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
211 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
212 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
213 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
214 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
215 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
216 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
217 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
219 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
222 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
223 // with merges, splats, etc.
224 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
226 setOperationAction(ISD::AND , MVT::v4i32, Legal);
227 setOperationAction(ISD::OR , MVT::v4i32, Legal);
228 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
229 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
230 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
231 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
233 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
234 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
235 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
236 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
238 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
239 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
240 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
241 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
243 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
244 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
246 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
247 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
248 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
249 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
252 setSetCCResultContents(ZeroOrOneSetCCResult);
253 setStackPointerRegisterToSaveRestore(PPC::R1);
255 // We have target-specific dag combine patterns for the following nodes:
256 setTargetDAGCombine(ISD::SINT_TO_FP);
257 setTargetDAGCombine(ISD::STORE);
258 setTargetDAGCombine(ISD::BR_CC);
260 computeRegisterProperties();
263 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
266 case PPCISD::FSEL: return "PPCISD::FSEL";
267 case PPCISD::FCFID: return "PPCISD::FCFID";
268 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
269 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
270 case PPCISD::STFIWX: return "PPCISD::STFIWX";
271 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
272 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
273 case PPCISD::VPERM: return "PPCISD::VPERM";
274 case PPCISD::Hi: return "PPCISD::Hi";
275 case PPCISD::Lo: return "PPCISD::Lo";
276 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
277 case PPCISD::SRL: return "PPCISD::SRL";
278 case PPCISD::SRA: return "PPCISD::SRA";
279 case PPCISD::SHL: return "PPCISD::SHL";
280 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
281 case PPCISD::STD_32: return "PPCISD::STD_32";
282 case PPCISD::CALL: return "PPCISD::CALL";
283 case PPCISD::MTCTR: return "PPCISD::MTCTR";
284 case PPCISD::BCTRL: return "PPCISD::BCTRL";
285 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
286 case PPCISD::MFCR: return "PPCISD::MFCR";
287 case PPCISD::VCMP: return "PPCISD::VCMP";
288 case PPCISD::VCMPo: return "PPCISD::VCMPo";
289 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
293 //===----------------------------------------------------------------------===//
294 // Node matching predicates, for use by the tblgen matching code.
295 //===----------------------------------------------------------------------===//
297 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
298 static bool isFloatingPointZero(SDOperand Op) {
299 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
300 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
301 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
302 // Maybe this has already been legalized into the constant pool?
303 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
304 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
305 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
310 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
311 /// true if Op is undef or if it matches the specified value.
312 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
313 return Op.getOpcode() == ISD::UNDEF ||
314 cast<ConstantSDNode>(Op)->getValue() == Val;
317 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
318 /// VPKUHUM instruction.
319 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
321 for (unsigned i = 0; i != 16; ++i)
322 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
325 for (unsigned i = 0; i != 8; ++i)
326 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
327 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
333 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
334 /// VPKUWUM instruction.
335 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
337 for (unsigned i = 0; i != 16; i += 2)
338 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
339 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
342 for (unsigned i = 0; i != 8; i += 2)
343 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
344 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
345 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
346 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
352 /// isVMerge - Common function, used to match vmrg* shuffles.
354 static bool isVMerge(SDNode *N, unsigned UnitSize,
355 unsigned LHSStart, unsigned RHSStart) {
356 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
357 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
358 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
359 "Unsupported merge size!");
361 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
362 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
363 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
364 LHSStart+j+i*UnitSize) ||
365 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
366 RHSStart+j+i*UnitSize))
372 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
373 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
374 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
376 return isVMerge(N, UnitSize, 8, 24);
377 return isVMerge(N, UnitSize, 8, 8);
380 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
381 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
382 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
384 return isVMerge(N, UnitSize, 0, 16);
385 return isVMerge(N, UnitSize, 0, 0);
389 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
390 /// amount, otherwise return -1.
391 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
392 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
393 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
394 // Find the first non-undef value in the shuffle mask.
396 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
399 if (i == 16) return -1; // all undef.
401 // Otherwise, check to see if the rest of the elements are consequtively
402 // numbered from this value.
403 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
404 if (ShiftAmt < i) return -1;
408 // Check the rest of the elements to see if they are consequtive.
409 for (++i; i != 16; ++i)
410 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
413 // Check the rest of the elements to see if they are consequtive.
414 for (++i; i != 16; ++i)
415 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
422 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
423 /// specifies a splat of a single element that is suitable for input to
424 /// VSPLTB/VSPLTH/VSPLTW.
425 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
426 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
427 N->getNumOperands() == 16 &&
428 (EltSize == 1 || EltSize == 2 || EltSize == 4));
430 // This is a splat operation if each element of the permute is the same, and
431 // if the value doesn't reference the second vector.
432 unsigned ElementBase = 0;
433 SDOperand Elt = N->getOperand(0);
434 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
435 ElementBase = EltV->getValue();
437 return false; // FIXME: Handle UNDEF elements too!
439 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
442 // Check that they are consequtive.
443 for (unsigned i = 1; i != EltSize; ++i) {
444 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
445 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
449 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
450 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
451 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
452 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
453 "Invalid VECTOR_SHUFFLE mask!");
454 for (unsigned j = 0; j != EltSize; ++j)
455 if (N->getOperand(i+j) != N->getOperand(j))
462 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
463 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
464 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
465 assert(isSplatShuffleMask(N, EltSize));
466 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
469 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
470 /// by using a vspltis[bhw] instruction of the specified element size, return
471 /// the constant being splatted. The ByteSize field indicates the number of
472 /// bytes of each element [124] -> [bhw].
473 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
474 SDOperand OpVal(0, 0);
476 // If ByteSize of the splat is bigger than the element size of the
477 // build_vector, then we have a case where we are checking for a splat where
478 // multiple elements of the buildvector are folded together into a single
479 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
480 unsigned EltSize = 16/N->getNumOperands();
481 if (EltSize < ByteSize) {
482 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
483 SDOperand UniquedVals[4];
484 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
486 // See if all of the elements in the buildvector agree across.
487 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
488 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
489 // If the element isn't a constant, bail fully out.
490 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
493 if (UniquedVals[i&(Multiple-1)].Val == 0)
494 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
495 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
496 return SDOperand(); // no match.
499 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
500 // either constant or undef values that are identical for each chunk. See
501 // if these chunks can form into a larger vspltis*.
503 // Check to see if all of the leading entries are either 0 or -1. If
504 // neither, then this won't fit into the immediate field.
505 bool LeadingZero = true;
506 bool LeadingOnes = true;
507 for (unsigned i = 0; i != Multiple-1; ++i) {
508 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
510 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
511 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
513 // Finally, check the least significant entry.
515 if (UniquedVals[Multiple-1].Val == 0)
516 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
517 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
519 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
522 if (UniquedVals[Multiple-1].Val == 0)
523 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
524 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
525 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
526 return DAG.getTargetConstant(Val, MVT::i32);
532 // Check to see if this buildvec has a single non-undef value in its elements.
533 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
534 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
536 OpVal = N->getOperand(i);
537 else if (OpVal != N->getOperand(i))
541 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
543 unsigned ValSizeInBytes = 0;
545 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
546 Value = CN->getValue();
547 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
548 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
549 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
550 Value = FloatToBits(CN->getValue());
554 // If the splat value is larger than the element value, then we can never do
555 // this splat. The only case that we could fit the replicated bits into our
556 // immediate field for would be zero, and we prefer to use vxor for it.
557 if (ValSizeInBytes < ByteSize) return SDOperand();
559 // If the element value is larger than the splat value, cut it in half and
560 // check to see if the two halves are equal. Continue doing this until we
561 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
562 while (ValSizeInBytes > ByteSize) {
563 ValSizeInBytes >>= 1;
565 // If the top half equals the bottom half, we're still ok.
566 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
567 (Value & ((1 << (8*ValSizeInBytes))-1)))
571 // Properly sign extend the value.
572 int ShAmt = (4-ByteSize)*8;
573 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
575 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
576 if (MaskVal == 0) return SDOperand();
578 // Finally, if this value fits in a 5 bit sext field, return it
579 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
580 return DAG.getTargetConstant(MaskVal, MVT::i32);
584 //===----------------------------------------------------------------------===//
585 // LowerOperation implementation
586 //===----------------------------------------------------------------------===//
588 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
589 MVT::ValueType PtrVT = Op.getValueType();
590 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
591 Constant *C = CP->get();
592 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
593 SDOperand Zero = DAG.getConstant(0, PtrVT);
595 const TargetMachine &TM = DAG.getTarget();
597 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
598 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
600 // If this is a non-darwin platform, we don't support non-static relo models
602 if (TM.getRelocationModel() == Reloc::Static ||
603 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
604 // Generate non-pic code that has direct accesses to the constant pool.
605 // The address of the global is just (hi(&g)+lo(&g)).
606 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
609 if (TM.getRelocationModel() == Reloc::PIC) {
610 // With PIC, the first instruction is actually "GR+hi(&G)".
611 Hi = DAG.getNode(ISD::ADD, PtrVT,
612 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
615 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
619 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
620 MVT::ValueType PtrVT = Op.getValueType();
621 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
622 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
623 SDOperand Zero = DAG.getConstant(0, PtrVT);
625 const TargetMachine &TM = DAG.getTarget();
627 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
628 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
630 // If this is a non-darwin platform, we don't support non-static relo models
632 if (TM.getRelocationModel() == Reloc::Static ||
633 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
634 // Generate non-pic code that has direct accesses to the constant pool.
635 // The address of the global is just (hi(&g)+lo(&g)).
636 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
639 if (TM.getRelocationModel() == Reloc::PIC) {
640 // With PIC, the first instruction is actually "GR+hi(&G)".
641 Hi = DAG.getNode(ISD::ADD, PtrVT,
642 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
645 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
649 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
650 MVT::ValueType PtrVT = Op.getValueType();
651 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
652 GlobalValue *GV = GSDN->getGlobal();
653 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
654 SDOperand Zero = DAG.getConstant(0, PtrVT);
656 const TargetMachine &TM = DAG.getTarget();
658 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
659 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
661 // If this is a non-darwin platform, we don't support non-static relo models
663 if (TM.getRelocationModel() == Reloc::Static ||
664 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
665 // Generate non-pic code that has direct accesses to globals.
666 // The address of the global is just (hi(&g)+lo(&g)).
667 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
670 if (TM.getRelocationModel() == Reloc::PIC) {
671 // With PIC, the first instruction is actually "GR+hi(&G)".
672 Hi = DAG.getNode(ISD::ADD, PtrVT,
673 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
676 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
678 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() &&
679 (!GV->isExternal() || GV->hasNotBeenReadFromBytecode()))
682 // If the global is weak or external, we have to go through the lazy
684 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
687 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
688 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
690 // If we're comparing for equality to zero, expose the fact that this is
691 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
692 // fold the new nodes.
693 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
694 if (C->isNullValue() && CC == ISD::SETEQ) {
695 MVT::ValueType VT = Op.getOperand(0).getValueType();
696 SDOperand Zext = Op.getOperand(0);
699 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
701 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
702 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
703 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
704 DAG.getConstant(Log2b, MVT::i32));
705 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
707 // Leave comparisons against 0 and -1 alone for now, since they're usually
708 // optimized. FIXME: revisit this when we can custom lower all setcc
710 if (C->isAllOnesValue() || C->isNullValue())
714 // If we have an integer seteq/setne, turn it into a compare against zero
715 // by subtracting the rhs from the lhs, which is faster than setting a
716 // condition register, reading it back out, and masking the correct bit.
717 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
718 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
719 MVT::ValueType VT = Op.getValueType();
720 SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0),
722 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
727 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
728 unsigned VarArgsFrameIndex) {
729 // vastart just stores the address of the VarArgsFrameIndex slot into the
730 // memory location argument.
731 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
732 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
733 Op.getOperand(1), Op.getOperand(2));
736 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
737 int &VarArgsFrameIndex) {
738 // TODO: add description of PPC stack frame format, or at least some docs.
740 MachineFunction &MF = DAG.getMachineFunction();
741 MachineFrameInfo *MFI = MF.getFrameInfo();
742 SSARegMap *RegMap = MF.getSSARegMap();
743 std::vector<SDOperand> ArgValues;
744 SDOperand Root = Op.getOperand(0);
746 unsigned ArgOffset = 24;
747 const unsigned Num_GPR_Regs = 8;
748 const unsigned Num_FPR_Regs = 13;
749 const unsigned Num_VR_Regs = 12;
750 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
752 static const unsigned GPR_32[] = { // 32-bit registers.
753 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
754 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
756 static const unsigned GPR_64[] = { // 64-bit registers.
757 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
758 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
760 static const unsigned FPR[] = {
761 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
762 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
764 static const unsigned VR[] = {
765 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
766 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
769 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
770 bool isPPC64 = PtrVT == MVT::i64;
771 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
773 // Add DAG nodes to load the arguments or copy them out of registers. On
774 // entry to a function on PPC, the arguments start at offset 24, although the
775 // first ones are often in registers.
776 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
778 bool needsLoad = false;
779 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
780 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
782 unsigned CurArgOffset = ArgOffset;
784 default: assert(0 && "Unhandled argument type!");
786 // All int arguments reserve stack space.
787 ArgOffset += isPPC64 ? 8 : 4;
789 if (GPR_idx != Num_GPR_Regs) {
790 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
791 MF.addLiveIn(GPR[GPR_idx], VReg);
792 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
798 case MVT::i64: // PPC64
799 // All int arguments reserve stack space.
802 if (GPR_idx != Num_GPR_Regs) {
803 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
804 MF.addLiveIn(GPR[GPR_idx], VReg);
805 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
813 // All FP arguments reserve stack space.
814 ArgOffset += ObjSize;
816 // Every 4 bytes of argument space consumes one of the GPRs available for
818 if (GPR_idx != Num_GPR_Regs) {
820 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs)
823 if (FPR_idx != Num_FPR_Regs) {
825 if (ObjectVT == MVT::f32)
826 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
828 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
829 MF.addLiveIn(FPR[FPR_idx], VReg);
830 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
840 // Note that vector arguments in registers don't reserve stack space.
841 if (VR_idx != Num_VR_Regs) {
842 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass);
843 MF.addLiveIn(VR[VR_idx], VReg);
844 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
847 // This should be simple, but requires getting 16-byte aligned stack
849 assert(0 && "Loading VR argument not implemented yet!");
855 // We need to load the argument to a virtual register if we determined above
856 // that we ran out of physical registers of the appropriate type
858 // If the argument is actually used, emit a load from the right stack
860 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
861 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
862 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
863 ArgVal = DAG.getLoad(ObjectVT, Root, FIN,
864 DAG.getSrcValue(NULL));
866 // Don't emit a dead load.
867 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
871 ArgValues.push_back(ArgVal);
874 // If the function takes variable number of arguments, make a frame index for
875 // the start of the first vararg value... for expansion of llvm.va_start.
876 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
878 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
880 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
881 // If this function is vararg, store any remaining integer argument regs
882 // to their spots on the stack so that they may be loaded by deferencing the
883 // result of va_next.
884 std::vector<SDOperand> MemOps;
885 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
886 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
887 MF.addLiveIn(GPR[GPR_idx], VReg);
888 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
889 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
890 Val, FIN, DAG.getSrcValue(NULL));
891 MemOps.push_back(Store);
892 // Increment the address by four for the next argument to store
893 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
894 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
897 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
900 ArgValues.push_back(Root);
902 // Return the new list of results.
903 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
904 Op.Val->value_end());
905 return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
908 /// isCallCompatibleAddress - Return the immediate to use if the specified
909 /// 32-bit value is representable in the immediate field of a BxA instruction.
910 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
911 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
914 int Addr = C->getValue();
915 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
916 (Addr << 6 >> 6) != Addr)
917 return 0; // Top 6 bits have to be sext of immediate.
919 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
923 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
924 SDOperand Chain = Op.getOperand(0);
925 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
926 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
927 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
928 SDOperand Callee = Op.getOperand(4);
929 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
931 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
932 bool isPPC64 = PtrVT == MVT::i64;
933 unsigned PtrByteSize = isPPC64 ? 8 : 4;
936 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
937 // SelectExpr to use to put the arguments in the appropriate registers.
938 std::vector<SDOperand> args_to_use;
940 // Count how many bytes are to be pushed on the stack, including the linkage
941 // area, and parameter passing area. We start with 24/48 bytes, which is
942 // prereserved space for [SP][CR][LR][3 x unused].
943 unsigned NumBytes = 6*PtrByteSize;
945 // Add up all the space actually used.
946 for (unsigned i = 0; i != NumOps; ++i)
947 NumBytes += MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
949 // The prolog code of the callee may store up to 8 GPR argument registers to
950 // the stack, allowing va_start to index over them in memory if its varargs.
951 // Because we cannot tell if this is needed on the caller side, we have to
952 // conservatively assume that it is needed. As such, make sure we have at
953 // least enough stack space for the caller to store the 8 GPRs.
954 if (NumBytes < 6*PtrByteSize+8*PtrByteSize)
955 NumBytes = 6*PtrByteSize+8*PtrByteSize;
957 // Adjust the stack pointer for the new arguments...
958 // These operations are automatically eliminated by the prolog/epilog pass
959 Chain = DAG.getCALLSEQ_START(Chain,
960 DAG.getConstant(NumBytes, PtrVT));
962 // Set up a copy of the stack pointer for use loading and storing any
963 // arguments that may not fit in the registers available for argument
967 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
969 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
971 // Figure out which arguments are going to go in registers, and which in
972 // memory. Also, if this is a vararg function, floating point operations
973 // must be stored to our stack, and loaded into integer regs as well, if
974 // any integer regs are available for argument passing.
975 unsigned ArgOffset = 6*PtrByteSize;
976 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
977 static const unsigned GPR_32[] = { // 32-bit registers.
978 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
979 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
981 static const unsigned GPR_64[] = { // 64-bit registers.
982 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
983 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
985 static const unsigned FPR[] = {
986 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
987 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
989 static const unsigned VR[] = {
990 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
991 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
993 const unsigned NumGPRs = sizeof(GPR_32)/sizeof(GPR_32[0]);
994 const unsigned NumFPRs = sizeof(FPR)/sizeof(FPR[0]);
995 const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]);
997 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
999 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1000 std::vector<SDOperand> MemOpChains;
1001 for (unsigned i = 0; i != NumOps; ++i) {
1002 SDOperand Arg = Op.getOperand(5+2*i);
1004 // PtrOff will be used to store the current argument to the stack if a
1005 // register cannot be found for it.
1006 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1007 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1009 // On PPC64, promote integers to 64-bit values.
1010 if (isPPC64 && Arg.getValueType() == MVT::i32) {
1011 unsigned ExtOp = ISD::ZERO_EXTEND;
1012 if (cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue())
1013 ExtOp = ISD::SIGN_EXTEND;
1014 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1017 switch (Arg.getValueType()) {
1018 default: assert(0 && "Unexpected ValueType for argument!");
1021 if (GPR_idx != NumGPRs) {
1022 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
1024 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1025 Arg, PtrOff, DAG.getSrcValue(NULL)));
1027 ArgOffset += PtrByteSize;
1031 if (FPR_idx != NumFPRs) {
1032 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1035 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
1037 DAG.getSrcValue(NULL));
1038 MemOpChains.push_back(Store);
1040 // Float varargs are always shadowed in available integer registers
1041 if (GPR_idx != NumGPRs) {
1042 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff,
1043 DAG.getSrcValue(NULL));
1044 MemOpChains.push_back(Load.getValue(1));
1045 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1047 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) {
1048 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1049 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
1050 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff,
1051 DAG.getSrcValue(NULL));
1052 MemOpChains.push_back(Load.getValue(1));
1053 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1056 // If we have any FPRs remaining, we may also have GPRs remaining.
1057 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1059 if (GPR_idx != NumGPRs)
1061 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64)
1065 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1066 Arg, PtrOff, DAG.getSrcValue(NULL)));
1071 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1077 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1078 assert(VR_idx != NumVRs &&
1079 "Don't support passing more than 12 vector args yet!");
1080 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1084 if (!MemOpChains.empty())
1085 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOpChains);
1087 // Build a sequence of copy-to-reg nodes chained together with token chain
1088 // and flag operands which copy the outgoing args into the appropriate regs.
1090 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1091 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1093 InFlag = Chain.getValue(1);
1096 std::vector<MVT::ValueType> NodeTys;
1097 NodeTys.push_back(MVT::Other); // Returns a chain
1098 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1100 std::vector<SDOperand> Ops;
1101 unsigned CallOpc = PPCISD::CALL;
1103 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1104 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1105 // node so that legalize doesn't hack it.
1106 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1107 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1108 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1109 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1110 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1111 // If this is an absolute destination address, use the munged value.
1112 Callee = SDOperand(Dest, 0);
1114 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1115 // to do the call, we can't use PPCISD::CALL.
1116 Ops.push_back(Chain);
1117 Ops.push_back(Callee);
1120 Ops.push_back(InFlag);
1121 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, Ops);
1122 InFlag = Chain.getValue(1);
1124 // Copy the callee address into R12 on darwin.
1125 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1126 InFlag = Chain.getValue(1);
1129 NodeTys.push_back(MVT::Other);
1130 NodeTys.push_back(MVT::Flag);
1132 Ops.push_back(Chain);
1133 CallOpc = PPCISD::BCTRL;
1137 // If this is a direct call, pass the chain and the callee.
1139 Ops.push_back(Chain);
1140 Ops.push_back(Callee);
1143 // Add argument registers to the end of the list so that they are known live
1145 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1146 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1147 RegsToPass[i].second.getValueType()));
1150 Ops.push_back(InFlag);
1151 Chain = DAG.getNode(CallOpc, NodeTys, Ops);
1152 InFlag = Chain.getValue(1);
1154 std::vector<SDOperand> ResultVals;
1157 // If the call has results, copy the values out of the ret val registers.
1158 switch (Op.Val->getValueType(0)) {
1159 default: assert(0 && "Unexpected ret value!");
1160 case MVT::Other: break;
1162 if (Op.Val->getValueType(1) == MVT::i32) {
1163 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1);
1164 ResultVals.push_back(Chain.getValue(0));
1165 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32,
1166 Chain.getValue(2)).getValue(1);
1167 ResultVals.push_back(Chain.getValue(0));
1168 NodeTys.push_back(MVT::i32);
1170 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1171 ResultVals.push_back(Chain.getValue(0));
1173 NodeTys.push_back(MVT::i32);
1176 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
1177 ResultVals.push_back(Chain.getValue(0));
1178 NodeTys.push_back(MVT::i64);
1182 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1183 InFlag).getValue(1);
1184 ResultVals.push_back(Chain.getValue(0));
1185 NodeTys.push_back(Op.Val->getValueType(0));
1191 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1192 InFlag).getValue(1);
1193 ResultVals.push_back(Chain.getValue(0));
1194 NodeTys.push_back(Op.Val->getValueType(0));
1198 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1199 DAG.getConstant(NumBytes, PtrVT));
1200 NodeTys.push_back(MVT::Other);
1202 // If the function returns void, just return the chain.
1203 if (ResultVals.empty())
1206 // Otherwise, merge everything together with a MERGE_VALUES node.
1207 ResultVals.push_back(Chain);
1208 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, ResultVals);
1209 return Res.getValue(Op.ResNo);
1212 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
1214 switch(Op.getNumOperands()) {
1216 assert(0 && "Do not know how to return this many arguments!");
1219 return SDOperand(); // ret void is legal
1221 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
1223 if (ArgVT == MVT::i32) {
1225 } else if (ArgVT == MVT::i64) {
1227 } else if (MVT::isFloatingPoint(ArgVT)) {
1230 assert(MVT::isVector(ArgVT));
1234 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
1237 // If we haven't noted the R3/F1 are live out, do so now.
1238 if (DAG.getMachineFunction().liveout_empty())
1239 DAG.getMachineFunction().addLiveOut(ArgReg);
1243 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3),
1245 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
1246 // If we haven't noted the R3+R4 are live out, do so now.
1247 if (DAG.getMachineFunction().liveout_empty()) {
1248 DAG.getMachineFunction().addLiveOut(PPC::R3);
1249 DAG.getMachineFunction().addLiveOut(PPC::R4);
1253 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
1256 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
1258 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
1259 // Not FP? Not a fsel.
1260 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
1261 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
1264 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1266 // Cannot handle SETEQ/SETNE.
1267 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
1269 MVT::ValueType ResVT = Op.getValueType();
1270 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
1271 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1272 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
1274 // If the RHS of the comparison is a 0.0, we don't need to do the
1275 // subtraction at all.
1276 if (isFloatingPointZero(RHS))
1278 default: break; // SETUO etc aren't handled by fsel.
1282 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1286 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1287 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1288 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
1292 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1296 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1297 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1298 return DAG.getNode(PPCISD::FSEL, ResVT,
1299 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
1304 default: break; // SETUO etc aren't handled by fsel.
1308 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1309 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1310 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1311 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1315 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1316 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1317 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1318 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1322 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1323 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1324 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1325 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1329 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1330 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1331 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1332 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1337 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
1338 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
1339 SDOperand Src = Op.getOperand(0);
1340 if (Src.getValueType() == MVT::f32)
1341 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
1344 switch (Op.getValueType()) {
1345 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
1347 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
1350 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
1354 // Convert the FP value to an int value through memory.
1355 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
1356 if (Op.getValueType() == MVT::i32)
1357 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
1361 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1362 if (Op.getOperand(0).getValueType() == MVT::i64) {
1363 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
1364 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
1365 if (Op.getValueType() == MVT::f32)
1366 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1370 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
1371 "Unhandled SINT_TO_FP type in custom expander!");
1372 // Since we only generate this in 64-bit mode, we can take advantage of
1373 // 64-bit registers. In particular, sign extend the input value into the
1374 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
1375 // then lfd it and fcfid it.
1376 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
1377 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
1378 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
1380 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
1383 // STD the extended value into the stack slot.
1384 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
1385 DAG.getEntryNode(), Ext64, FIdx,
1386 DAG.getSrcValue(NULL));
1387 // Load the value as a double.
1388 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL));
1390 // FCFID it and return it.
1391 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
1392 if (Op.getValueType() == MVT::f32)
1393 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1397 static SDOperand LowerSHL(SDOperand Op, SelectionDAG &DAG,
1398 MVT::ValueType PtrVT) {
1399 assert(Op.getValueType() == MVT::i64 &&
1400 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
1401 // The generic code does a fine job expanding shift by a constant.
1402 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
1404 // Otherwise, expand into a bunch of logical ops. Note that these ops
1405 // depend on the PPC behavior for oversized shift amounts.
1406 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1407 DAG.getConstant(0, PtrVT));
1408 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1409 DAG.getConstant(1, PtrVT));
1410 SDOperand Amt = Op.getOperand(1);
1412 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1413 DAG.getConstant(32, MVT::i32), Amt);
1414 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
1415 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
1416 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1417 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1418 DAG.getConstant(-32U, MVT::i32));
1419 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
1420 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1421 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
1422 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
1425 static SDOperand LowerSRL(SDOperand Op, SelectionDAG &DAG,
1426 MVT::ValueType PtrVT) {
1427 assert(Op.getValueType() == MVT::i64 &&
1428 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
1429 // The generic code does a fine job expanding shift by a constant.
1430 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
1432 // Otherwise, expand into a bunch of logical ops. Note that these ops
1433 // depend on the PPC behavior for oversized shift amounts.
1434 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1435 DAG.getConstant(0, PtrVT));
1436 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1437 DAG.getConstant(1, PtrVT));
1438 SDOperand Amt = Op.getOperand(1);
1440 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1441 DAG.getConstant(32, MVT::i32), Amt);
1442 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1443 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1444 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1445 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1446 DAG.getConstant(-32U, MVT::i32));
1447 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
1448 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1449 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
1450 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
1453 static SDOperand LowerSRA(SDOperand Op, SelectionDAG &DAG,
1454 MVT::ValueType PtrVT) {
1455 assert(Op.getValueType() == MVT::i64 &&
1456 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
1457 // The generic code does a fine job expanding shift by a constant.
1458 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
1460 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
1461 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1462 DAG.getConstant(0, PtrVT));
1463 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1464 DAG.getConstant(1, PtrVT));
1465 SDOperand Amt = Op.getOperand(1);
1467 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1468 DAG.getConstant(32, MVT::i32), Amt);
1469 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1470 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1471 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1472 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1473 DAG.getConstant(-32U, MVT::i32));
1474 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
1475 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
1476 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
1477 Tmp4, Tmp6, ISD::SETLE);
1478 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
1481 //===----------------------------------------------------------------------===//
1482 // Vector related lowering.
1485 // If this is a vector of constants or undefs, get the bits. A bit in
1486 // UndefBits is set if the corresponding element of the vector is an
1487 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1488 // zero. Return true if this is not an array of constants, false if it is.
1490 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
1491 uint64_t UndefBits[2]) {
1492 // Start with zero'd results.
1493 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
1495 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
1496 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
1497 SDOperand OpVal = BV->getOperand(i);
1499 unsigned PartNo = i >= e/2; // In the upper 128 bits?
1500 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
1502 uint64_t EltBits = 0;
1503 if (OpVal.getOpcode() == ISD::UNDEF) {
1504 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
1505 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
1507 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1508 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
1509 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1510 assert(CN->getValueType(0) == MVT::f32 &&
1511 "Only one legal FP vector type!");
1512 EltBits = FloatToBits(CN->getValue());
1514 // Nonconstant element.
1518 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
1521 //printf("%llx %llx %llx %llx\n",
1522 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
1526 // If this is a splat (repetition) of a value across the whole vector, return
1527 // the smallest size that splats it. For example, "0x01010101010101..." is a
1528 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1529 // SplatSize = 1 byte.
1530 static bool isConstantSplat(const uint64_t Bits128[2],
1531 const uint64_t Undef128[2],
1532 unsigned &SplatBits, unsigned &SplatUndef,
1533 unsigned &SplatSize) {
1535 // Don't let undefs prevent splats from matching. See if the top 64-bits are
1536 // the same as the lower 64-bits, ignoring undefs.
1537 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
1538 return false; // Can't be a splat if two pieces don't match.
1540 uint64_t Bits64 = Bits128[0] | Bits128[1];
1541 uint64_t Undef64 = Undef128[0] & Undef128[1];
1543 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
1545 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
1546 return false; // Can't be a splat if two pieces don't match.
1548 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
1549 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
1551 // If the top 16-bits are different than the lower 16-bits, ignoring
1552 // undefs, we have an i32 splat.
1553 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
1555 SplatUndef = Undef32;
1560 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
1561 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
1563 // If the top 8-bits are different than the lower 8-bits, ignoring
1564 // undefs, we have an i16 splat.
1565 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
1567 SplatUndef = Undef16;
1572 // Otherwise, we have an 8-bit splat.
1573 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
1574 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
1579 /// BuildSplatI - Build a canonical splati of Val with an element size of
1580 /// SplatSize. Cast the result to VT.
1581 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
1582 SelectionDAG &DAG) {
1583 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
1585 // Force vspltis[hw] -1 to vspltisb -1.
1586 if (Val == -1) SplatSize = 1;
1588 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
1589 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
1591 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
1593 // Build a canonical splat for this value.
1594 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT));
1595 std::vector<SDOperand> Ops(MVT::getVectorNumElements(CanonicalVT), Elt);
1596 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops);
1597 return DAG.getNode(ISD::BIT_CONVERT, VT, Res);
1600 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
1601 /// specified intrinsic ID.
1602 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
1604 MVT::ValueType DestVT = MVT::Other) {
1605 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
1606 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1607 DAG.getConstant(IID, MVT::i32), LHS, RHS);
1610 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
1611 /// specified intrinsic ID.
1612 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
1613 SDOperand Op2, SelectionDAG &DAG,
1614 MVT::ValueType DestVT = MVT::Other) {
1615 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
1616 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1617 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
1621 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
1622 /// amount. The result has the specified value type.
1623 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
1624 MVT::ValueType VT, SelectionDAG &DAG) {
1625 // Force LHS/RHS to be the right type.
1626 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
1627 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
1629 std::vector<SDOperand> Ops;
1630 for (unsigned i = 0; i != 16; ++i)
1631 Ops.push_back(DAG.getConstant(i+Amt, MVT::i32));
1632 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
1633 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
1634 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
1637 // If this is a case we can't handle, return null and let the default
1638 // expansion code take care of it. If we CAN select this case, and if it
1639 // selects to a single instruction, return Op. Otherwise, if we can codegen
1640 // this case more efficiently than a constant pool load, lower it to the
1641 // sequence of ops that should be used.
1642 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
1643 // If this is a vector of constants or undefs, get the bits. A bit in
1644 // UndefBits is set if the corresponding element of the vector is an
1645 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1647 uint64_t VectorBits[2];
1648 uint64_t UndefBits[2];
1649 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
1650 return SDOperand(); // Not a constant vector.
1652 // If this is a splat (repetition) of a value across the whole vector, return
1653 // the smallest size that splats it. For example, "0x01010101010101..." is a
1654 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1655 // SplatSize = 1 byte.
1656 unsigned SplatBits, SplatUndef, SplatSize;
1657 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
1658 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
1660 // First, handle single instruction cases.
1663 if (SplatBits == 0) {
1664 // Canonicalize all zero vectors to be v4i32.
1665 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
1666 SDOperand Z = DAG.getConstant(0, MVT::i32);
1667 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
1668 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
1673 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
1674 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
1675 if (SextVal >= -16 && SextVal <= 15)
1676 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
1679 // Two instruction sequences.
1681 // If this value is in the range [-32,30] and is even, use:
1682 // tmp = VSPLTI[bhw], result = add tmp, tmp
1683 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
1684 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
1685 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
1688 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
1689 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
1691 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
1692 // Make -1 and vspltisw -1:
1693 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
1695 // Make the VSLW intrinsic, computing 0x8000_0000.
1696 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
1699 // xor by OnesV to invert it.
1700 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
1701 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
1704 // Check to see if this is a wide variety of vsplti*, binop self cases.
1705 unsigned SplatBitSize = SplatSize*8;
1706 static const char SplatCsts[] = {
1707 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
1708 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
1710 for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){
1711 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
1712 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
1713 int i = SplatCsts[idx];
1715 // Figure out what shift amount will be used by altivec if shifted by i in
1717 unsigned TypeShiftAmt = i & (SplatBitSize-1);
1719 // vsplti + shl self.
1720 if (SextVal == (i << (int)TypeShiftAmt)) {
1721 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1722 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1723 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
1724 Intrinsic::ppc_altivec_vslw
1726 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1729 // vsplti + srl self.
1730 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
1731 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1732 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1733 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
1734 Intrinsic::ppc_altivec_vsrw
1736 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1739 // vsplti + sra self.
1740 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
1741 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1742 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1743 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
1744 Intrinsic::ppc_altivec_vsraw
1746 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1749 // vsplti + rol self.
1750 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
1751 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
1752 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1753 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1754 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
1755 Intrinsic::ppc_altivec_vrlw
1757 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1760 // t = vsplti c, result = vsldoi t, t, 1
1761 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
1762 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1763 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
1765 // t = vsplti c, result = vsldoi t, t, 2
1766 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
1767 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1768 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
1770 // t = vsplti c, result = vsldoi t, t, 3
1771 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
1772 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1773 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
1777 // Three instruction sequences.
1779 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
1780 if (SextVal >= 0 && SextVal <= 31) {
1781 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, Op.getValueType(),DAG);
1782 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
1783 return DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
1785 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
1786 if (SextVal >= -31 && SextVal <= 0) {
1787 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, Op.getValueType(),DAG);
1788 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
1789 return DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
1796 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
1797 /// the specified operations to build the shuffle.
1798 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
1799 SDOperand RHS, SelectionDAG &DAG) {
1800 unsigned OpNum = (PFEntry >> 26) & 0x0F;
1801 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
1802 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
1805 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
1817 if (OpNum == OP_COPY) {
1818 if (LHSID == (1*9+2)*9+3) return LHS;
1819 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
1823 SDOperand OpLHS, OpRHS;
1824 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
1825 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
1827 unsigned ShufIdxs[16];
1829 default: assert(0 && "Unknown i32 permute!");
1831 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
1832 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
1833 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
1834 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
1837 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
1838 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
1839 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
1840 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
1843 for (unsigned i = 0; i != 16; ++i)
1844 ShufIdxs[i] = (i&3)+0;
1847 for (unsigned i = 0; i != 16; ++i)
1848 ShufIdxs[i] = (i&3)+4;
1851 for (unsigned i = 0; i != 16; ++i)
1852 ShufIdxs[i] = (i&3)+8;
1855 for (unsigned i = 0; i != 16; ++i)
1856 ShufIdxs[i] = (i&3)+12;
1859 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
1861 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
1863 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
1865 std::vector<SDOperand> Ops;
1866 for (unsigned i = 0; i != 16; ++i)
1867 Ops.push_back(DAG.getConstant(ShufIdxs[i], MVT::i32));
1869 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
1870 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
1873 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
1874 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
1875 /// return the code it can be lowered into. Worst case, it can always be
1876 /// lowered into a vperm.
1877 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
1878 SDOperand V1 = Op.getOperand(0);
1879 SDOperand V2 = Op.getOperand(1);
1880 SDOperand PermMask = Op.getOperand(2);
1882 // Cases that are handled by instructions that take permute immediates
1883 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
1884 // selected by the instruction selector.
1885 if (V2.getOpcode() == ISD::UNDEF) {
1886 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
1887 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
1888 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
1889 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
1890 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
1891 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
1892 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
1893 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
1894 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
1895 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
1896 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
1897 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
1902 // Altivec has a variety of "shuffle immediates" that take two vector inputs
1903 // and produce a fixed permutation. If any of these match, do not lower to
1905 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
1906 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
1907 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
1908 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
1909 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
1910 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
1911 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
1912 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
1913 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
1916 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
1917 // perfect shuffle table to emit an optimal matching sequence.
1918 unsigned PFIndexes[4];
1919 bool isFourElementShuffle = true;
1920 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
1921 unsigned EltNo = 8; // Start out undef.
1922 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
1923 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
1924 continue; // Undef, ignore it.
1926 unsigned ByteSource =
1927 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
1928 if ((ByteSource & 3) != j) {
1929 isFourElementShuffle = false;
1934 EltNo = ByteSource/4;
1935 } else if (EltNo != ByteSource/4) {
1936 isFourElementShuffle = false;
1940 PFIndexes[i] = EltNo;
1943 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
1944 // perfect shuffle vector to determine if it is cost effective to do this as
1945 // discrete instructions, or whether we should use a vperm.
1946 if (isFourElementShuffle) {
1947 // Compute the index in the perfect shuffle table.
1948 unsigned PFTableIndex =
1949 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
1951 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
1952 unsigned Cost = (PFEntry >> 30);
1954 // Determining when to avoid vperm is tricky. Many things affect the cost
1955 // of vperm, particularly how many times the perm mask needs to be computed.
1956 // For example, if the perm mask can be hoisted out of a loop or is already
1957 // used (perhaps because there are multiple permutes with the same shuffle
1958 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
1959 // the loop requires an extra register.
1961 // As a compromise, we only emit discrete instructions if the shuffle can be
1962 // generated in 3 or fewer operations. When we have loop information
1963 // available, if this block is within a loop, we should avoid using vperm
1964 // for 3-operation perms and use a constant pool load instead.
1966 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
1969 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
1970 // vector that will get spilled to the constant pool.
1971 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
1973 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
1974 // that it is in input element units, not in bytes. Convert now.
1975 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
1976 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
1978 std::vector<SDOperand> ResultMask;
1979 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
1981 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
1984 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
1986 for (unsigned j = 0; j != BytesPerElement; ++j)
1987 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
1991 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask);
1992 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
1995 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
1996 /// altivec comparison. If it is, return true and fill in Opc/isDot with
1997 /// information about the intrinsic.
1998 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
2000 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
2003 switch (IntrinsicID) {
2004 default: return false;
2005 // Comparison predicates.
2006 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
2007 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
2008 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
2009 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
2010 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
2011 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
2012 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
2013 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
2014 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
2015 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
2016 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
2017 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
2018 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
2020 // Normal Comparisons.
2021 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
2022 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
2023 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
2024 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
2025 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
2026 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
2027 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
2028 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
2029 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
2030 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
2031 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
2032 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
2033 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
2038 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
2039 /// lower, do it, otherwise return null.
2040 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
2041 // If this is a lowered altivec predicate compare, CompareOpc is set to the
2042 // opcode number of the comparison.
2045 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
2046 return SDOperand(); // Don't custom lower most intrinsics.
2048 // If this is a non-dot comparison, make the VCMP node and we are done.
2050 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
2051 Op.getOperand(1), Op.getOperand(2),
2052 DAG.getConstant(CompareOpc, MVT::i32));
2053 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
2056 // Create the PPCISD altivec 'dot' comparison node.
2057 std::vector<SDOperand> Ops;
2058 std::vector<MVT::ValueType> VTs;
2059 Ops.push_back(Op.getOperand(2)); // LHS
2060 Ops.push_back(Op.getOperand(3)); // RHS
2061 Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32));
2062 VTs.push_back(Op.getOperand(2).getValueType());
2063 VTs.push_back(MVT::Flag);
2064 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops);
2066 // Now that we have the comparison, emit a copy from the CR to a GPR.
2067 // This is flagged to the above dot comparison.
2068 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
2069 DAG.getRegister(PPC::CR6, MVT::i32),
2070 CompNode.getValue(1));
2072 // Unpack the result based on how the target uses it.
2073 unsigned BitNo; // Bit # of CR6.
2074 bool InvertBit; // Invert result?
2075 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
2076 default: // Can't happen, don't crash on invalid number though.
2077 case 0: // Return the value of the EQ bit of CR6.
2078 BitNo = 0; InvertBit = false;
2080 case 1: // Return the inverted value of the EQ bit of CR6.
2081 BitNo = 0; InvertBit = true;
2083 case 2: // Return the value of the LT bit of CR6.
2084 BitNo = 2; InvertBit = false;
2086 case 3: // Return the inverted value of the LT bit of CR6.
2087 BitNo = 2; InvertBit = true;
2091 // Shift the bit into the low position.
2092 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
2093 DAG.getConstant(8-(3-BitNo), MVT::i32));
2095 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
2096 DAG.getConstant(1, MVT::i32));
2098 // If we are supposed to, toggle the bit.
2100 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
2101 DAG.getConstant(1, MVT::i32));
2105 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2106 // Create a stack slot that is 16-byte aligned.
2107 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2108 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
2109 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
2111 // Store the input value into Value#0 of the stack slot.
2112 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
2113 Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
2115 return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL));
2118 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
2119 if (Op.getValueType() == MVT::v4i32) {
2120 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2122 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
2123 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
2125 SDOperand RHSSwap = // = vrlw RHS, 16
2126 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
2128 // Shrinkify inputs to v8i16.
2129 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
2130 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
2131 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
2133 // Low parts multiplied together, generating 32-bit results (we ignore the
2135 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
2136 LHS, RHS, DAG, MVT::v4i32);
2138 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
2139 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
2140 // Shift the high parts up 16 bits.
2141 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
2142 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
2143 } else if (Op.getValueType() == MVT::v8i16) {
2144 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2146 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
2148 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
2149 LHS, RHS, Zero, DAG);
2150 } else if (Op.getValueType() == MVT::v16i8) {
2151 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2153 // Multiply the even 8-bit parts, producing 16-bit sums.
2154 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
2155 LHS, RHS, DAG, MVT::v8i16);
2156 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
2158 // Multiply the odd 8-bit parts, producing 16-bit sums.
2159 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
2160 LHS, RHS, DAG, MVT::v8i16);
2161 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
2163 // Merge the results together.
2164 std::vector<SDOperand> Ops;
2165 for (unsigned i = 0; i != 8; ++i) {
2166 Ops.push_back(DAG.getConstant(2*i+1, MVT::i8));
2167 Ops.push_back(DAG.getConstant(2*i+1+16, MVT::i8));
2170 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
2171 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
2173 assert(0 && "Unknown mul to lower!");
2178 /// LowerOperation - Provide custom lowering hooks for some operations.
2180 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2181 switch (Op.getOpcode()) {
2182 default: assert(0 && "Wasn't expecting to be able to lower this!");
2183 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2184 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2185 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2186 case ISD::SETCC: return LowerSETCC(Op, DAG);
2187 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2188 case ISD::FORMAL_ARGUMENTS:
2189 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex);
2190 case ISD::CALL: return LowerCALL(Op, DAG);
2191 case ISD::RET: return LowerRET(Op, DAG);
2193 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2194 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
2195 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
2197 // Lower 64-bit shifts.
2198 case ISD::SHL: return LowerSHL(Op, DAG, getPointerTy());
2199 case ISD::SRL: return LowerSRL(Op, DAG, getPointerTy());
2200 case ISD::SRA: return LowerSRA(Op, DAG, getPointerTy());
2202 // Vector-related lowering.
2203 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2204 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2205 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2206 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2207 case ISD::MUL: return LowerMUL(Op, DAG);
2212 //===----------------------------------------------------------------------===//
2213 // Other Lowering Code
2214 //===----------------------------------------------------------------------===//
2217 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2218 MachineBasicBlock *BB) {
2219 assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
2220 MI->getOpcode() == PPC::SELECT_CC_F4 ||
2221 MI->getOpcode() == PPC::SELECT_CC_F8 ||
2222 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
2223 "Unexpected instr type to insert");
2225 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2226 // control-flow pattern. The incoming instruction knows the destination vreg
2227 // to set, the condition code register to branch on, the true/false values to
2228 // select between, and a branch opcode to use.
2229 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2230 ilist<MachineBasicBlock>::iterator It = BB;
2236 // cmpTY ccX, r1, r2
2238 // fallthrough --> copy0MBB
2239 MachineBasicBlock *thisMBB = BB;
2240 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2241 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2242 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
2243 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
2244 MachineFunction *F = BB->getParent();
2245 F->getBasicBlockList().insert(It, copy0MBB);
2246 F->getBasicBlockList().insert(It, sinkMBB);
2247 // Update machine-CFG edges by first adding all successors of the current
2248 // block to the new block which will contain the Phi node for the select.
2249 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2250 e = BB->succ_end(); i != e; ++i)
2251 sinkMBB->addSuccessor(*i);
2252 // Next, remove all successors of the current block, and add the true
2253 // and fallthrough blocks as its successors.
2254 while(!BB->succ_empty())
2255 BB->removeSuccessor(BB->succ_begin());
2256 BB->addSuccessor(copy0MBB);
2257 BB->addSuccessor(sinkMBB);
2260 // %FalseValue = ...
2261 // # fallthrough to sinkMBB
2264 // Update machine-CFG edges
2265 BB->addSuccessor(sinkMBB);
2268 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2271 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
2272 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
2273 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2275 delete MI; // The pseudo instruction is gone now.
2279 //===----------------------------------------------------------------------===//
2280 // Target Optimization Hooks
2281 //===----------------------------------------------------------------------===//
2283 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
2284 DAGCombinerInfo &DCI) const {
2285 TargetMachine &TM = getTargetMachine();
2286 SelectionDAG &DAG = DCI.DAG;
2287 switch (N->getOpcode()) {
2289 case ISD::SINT_TO_FP:
2290 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
2291 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
2292 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
2293 // We allow the src/dst to be either f32/f64, but the intermediate
2294 // type must be i64.
2295 if (N->getOperand(0).getValueType() == MVT::i64) {
2296 SDOperand Val = N->getOperand(0).getOperand(0);
2297 if (Val.getValueType() == MVT::f32) {
2298 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2299 DCI.AddToWorklist(Val.Val);
2302 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
2303 DCI.AddToWorklist(Val.Val);
2304 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
2305 DCI.AddToWorklist(Val.Val);
2306 if (N->getValueType(0) == MVT::f32) {
2307 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
2308 DCI.AddToWorklist(Val.Val);
2311 } else if (N->getOperand(0).getValueType() == MVT::i32) {
2312 // If the intermediate type is i32, we can avoid the load/store here
2319 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
2320 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
2321 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
2322 N->getOperand(1).getValueType() == MVT::i32) {
2323 SDOperand Val = N->getOperand(1).getOperand(0);
2324 if (Val.getValueType() == MVT::f32) {
2325 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2326 DCI.AddToWorklist(Val.Val);
2328 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
2329 DCI.AddToWorklist(Val.Val);
2331 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
2332 N->getOperand(2), N->getOperand(3));
2333 DCI.AddToWorklist(Val.Val);
2337 case PPCISD::VCMP: {
2338 // If a VCMPo node already exists with exactly the same operands as this
2339 // node, use its result instead of this node (VCMPo computes both a CR6 and
2340 // a normal output).
2342 if (!N->getOperand(0).hasOneUse() &&
2343 !N->getOperand(1).hasOneUse() &&
2344 !N->getOperand(2).hasOneUse()) {
2346 // Scan all of the users of the LHS, looking for VCMPo's that match.
2347 SDNode *VCMPoNode = 0;
2349 SDNode *LHSN = N->getOperand(0).Val;
2350 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
2352 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
2353 (*UI)->getOperand(1) == N->getOperand(1) &&
2354 (*UI)->getOperand(2) == N->getOperand(2) &&
2355 (*UI)->getOperand(0) == N->getOperand(0)) {
2360 // If there is no VCMPo node, or if the flag value has a single use, don't
2362 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
2365 // Look at the (necessarily single) use of the flag value. If it has a
2366 // chain, this transformation is more complex. Note that multiple things
2367 // could use the value result, which we should ignore.
2368 SDNode *FlagUser = 0;
2369 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
2370 FlagUser == 0; ++UI) {
2371 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
2373 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2374 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
2381 // If the user is a MFCR instruction, we know this is safe. Otherwise we
2382 // give up for right now.
2383 if (FlagUser->getOpcode() == PPCISD::MFCR)
2384 return SDOperand(VCMPoNode, 0);
2389 // If this is a branch on an altivec predicate comparison, lower this so
2390 // that we don't have to do a MFCR: instead, branch directly on CR6. This
2391 // lowering is done pre-legalize, because the legalizer lowers the predicate
2392 // compare down to code that is difficult to reassemble.
2393 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
2394 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
2398 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2399 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
2400 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
2401 assert(isDot && "Can't compare against a vector result!");
2403 // If this is a comparison against something other than 0/1, then we know
2404 // that the condition is never/always true.
2405 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
2406 if (Val != 0 && Val != 1) {
2407 if (CC == ISD::SETEQ) // Cond never true, remove branch.
2408 return N->getOperand(0);
2409 // Always !=, turn it into an unconditional branch.
2410 return DAG.getNode(ISD::BR, MVT::Other,
2411 N->getOperand(0), N->getOperand(4));
2414 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
2416 // Create the PPCISD altivec 'dot' comparison node.
2417 std::vector<SDOperand> Ops;
2418 std::vector<MVT::ValueType> VTs;
2419 Ops.push_back(LHS.getOperand(2)); // LHS of compare
2420 Ops.push_back(LHS.getOperand(3)); // RHS of compare
2421 Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32));
2422 VTs.push_back(LHS.getOperand(2).getValueType());
2423 VTs.push_back(MVT::Flag);
2424 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops);
2426 // Unpack the result based on how the target uses it.
2428 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
2429 default: // Can't happen, don't crash on invalid number though.
2430 case 0: // Branch on the value of the EQ bit of CR6.
2431 CompOpc = BranchOnWhenPredTrue ? PPC::BEQ : PPC::BNE;
2433 case 1: // Branch on the inverted value of the EQ bit of CR6.
2434 CompOpc = BranchOnWhenPredTrue ? PPC::BNE : PPC::BEQ;
2436 case 2: // Branch on the value of the LT bit of CR6.
2437 CompOpc = BranchOnWhenPredTrue ? PPC::BLT : PPC::BGE;
2439 case 3: // Branch on the inverted value of the LT bit of CR6.
2440 CompOpc = BranchOnWhenPredTrue ? PPC::BGE : PPC::BLT;
2444 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
2445 DAG.getRegister(PPC::CR6, MVT::i32),
2446 DAG.getConstant(CompOpc, MVT::i32),
2447 N->getOperand(4), CompNode.getValue(1));
2456 //===----------------------------------------------------------------------===//
2457 // Inline Assembly Support
2458 //===----------------------------------------------------------------------===//
2460 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
2462 uint64_t &KnownZero,
2464 unsigned Depth) const {
2467 switch (Op.getOpcode()) {
2469 case ISD::INTRINSIC_WO_CHAIN: {
2470 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
2472 case Intrinsic::ppc_altivec_vcmpbfp_p:
2473 case Intrinsic::ppc_altivec_vcmpeqfp_p:
2474 case Intrinsic::ppc_altivec_vcmpequb_p:
2475 case Intrinsic::ppc_altivec_vcmpequh_p:
2476 case Intrinsic::ppc_altivec_vcmpequw_p:
2477 case Intrinsic::ppc_altivec_vcmpgefp_p:
2478 case Intrinsic::ppc_altivec_vcmpgtfp_p:
2479 case Intrinsic::ppc_altivec_vcmpgtsb_p:
2480 case Intrinsic::ppc_altivec_vcmpgtsh_p:
2481 case Intrinsic::ppc_altivec_vcmpgtsw_p:
2482 case Intrinsic::ppc_altivec_vcmpgtub_p:
2483 case Intrinsic::ppc_altivec_vcmpgtuh_p:
2484 case Intrinsic::ppc_altivec_vcmpgtuw_p:
2485 KnownZero = ~1U; // All bits but the low one are known to be zero.
2493 /// getConstraintType - Given a constraint letter, return the type of
2494 /// constraint it is for this target.
2495 PPCTargetLowering::ConstraintType
2496 PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
2497 switch (ConstraintLetter) {
2504 return C_RegisterClass;
2506 return TargetLowering::getConstraintType(ConstraintLetter);
2510 std::vector<unsigned> PPCTargetLowering::
2511 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2512 MVT::ValueType VT) const {
2513 if (Constraint.size() == 1) {
2514 switch (Constraint[0]) { // GCC RS6000 Constraint Letters
2515 default: break; // Unknown constriant letter
2517 return make_vector<unsigned>(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 ,
2518 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
2519 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
2520 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
2521 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
2522 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
2523 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
2524 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
2527 return make_vector<unsigned>(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 ,
2528 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
2529 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
2530 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
2531 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
2532 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
2533 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
2534 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
2537 return make_vector<unsigned>(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 ,
2538 PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 ,
2539 PPC::F8 , PPC::F9 , PPC::F10, PPC::F11,
2540 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
2541 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
2542 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
2543 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
2544 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
2547 return make_vector<unsigned>(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 ,
2548 PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
2549 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11,
2550 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
2551 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
2552 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
2553 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
2554 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
2557 return make_vector<unsigned>(PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
2558 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7,
2563 return std::vector<unsigned>();
2566 // isOperandValidForConstraint
2567 bool PPCTargetLowering::
2568 isOperandValidForConstraint(SDOperand Op, char Letter) {
2579 if (!isa<ConstantSDNode>(Op)) return false; // Must be an immediate.
2580 unsigned Value = cast<ConstantSDNode>(Op)->getValue();
2582 default: assert(0 && "Unknown constraint letter!");
2583 case 'I': // "I" is a signed 16-bit constant.
2584 return (short)Value == (int)Value;
2585 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
2586 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
2587 return (short)Value == 0;
2588 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
2589 return (Value >> 16) == 0;
2590 case 'M': // "M" is a constant that is greater than 31.
2592 case 'N': // "N" is a positive constant that is an exact power of two.
2593 return (int)Value > 0 && isPowerOf2_32(Value);
2594 case 'O': // "O" is the constant zero.
2596 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
2597 return (short)-Value == (int)-Value;
2603 // Handle standard constraint letters.
2604 return TargetLowering::isOperandValidForConstraint(Op, Letter);
2607 /// isLegalAddressImmediate - Return true if the integer value can be used
2608 /// as the offset of the target addressing mode.
2609 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const {
2610 // PPC allows a sign-extended 16-bit immediate field.
2611 return (V > -(1 << 16) && V < (1 << 16)-1);