1 //===-- PPC32ISelLowering.cpp - PPC32 DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC32ISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPC32ISelLowering.h"
15 #include "PPC32TargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Function.h"
24 PPC32TargetLowering::PPC32TargetLowering(TargetMachine &TM)
25 : TargetLowering(TM) {
27 // Fold away setcc operations if possible.
28 setSetCCIsExpensive();
30 // Set up the register classes.
31 addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
32 addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
33 addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
35 // PowerPC has no intrinsics for these particular operations
36 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
37 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
38 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
40 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
41 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
42 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
44 // PowerPC has no SREM/UREM instructions
45 setOperationAction(ISD::SREM, MVT::i32, Expand);
46 setOperationAction(ISD::UREM, MVT::i32, Expand);
48 // We don't support sin/cos/sqrt/fmod
49 setOperationAction(ISD::FSIN , MVT::f64, Expand);
50 setOperationAction(ISD::FCOS , MVT::f64, Expand);
51 setOperationAction(ISD::SREM , MVT::f64, Expand);
52 setOperationAction(ISD::FSIN , MVT::f32, Expand);
53 setOperationAction(ISD::FCOS , MVT::f32, Expand);
54 setOperationAction(ISD::SREM , MVT::f32, Expand);
56 // If we're enabling GP optimizations, use hardware square root
57 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
58 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
59 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
62 // PowerPC does not have CTPOP or CTTZ
63 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
64 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
66 // PowerPC does not have Select
67 setOperationAction(ISD::SELECT, MVT::i32, Expand);
68 setOperationAction(ISD::SELECT, MVT::f32, Expand);
69 setOperationAction(ISD::SELECT, MVT::f64, Expand);
71 // PowerPC wants to turn select_cc of FP into fsel when possible.
72 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
73 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
75 // PowerPC wants to expand i64 shifts itself.
76 setOperationAction(ISD::SHL, MVT::i64, Custom);
77 setOperationAction(ISD::SRL, MVT::i64, Custom);
78 setOperationAction(ISD::SRA, MVT::i64, Custom);
80 // PowerPC does not have BRCOND* which requires SetCC
81 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
82 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
84 // PowerPC does not have FP_TO_UINT
85 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
87 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
88 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
90 // PowerPC does not have [U|S]INT_TO_FP
91 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
92 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
94 // 64 bit PowerPC implementations have instructions to facilitate conversion
95 // between i64 and fp.
96 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
97 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
98 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
101 setSetCCResultContents(ZeroOrOneSetCCResult);
103 computeRegisterProperties();
106 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
107 static bool isFloatingPointZero(SDOperand Op) {
108 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
109 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
110 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
111 // Maybe this has already been legalized into the constant pool?
112 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
113 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
114 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
119 /// LowerOperation - Provide custom lowering hooks for some operations.
121 SDOperand PPC32TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
122 switch (Op.getOpcode()) {
123 default: assert(0 && "Wasn't expecting to be able to lower this!");
124 case ISD::FP_TO_SINT: {
125 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
126 switch (Op.getValueType()) {
127 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
129 Op = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Op.getOperand(0));
132 Op = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Op.getOperand(0));
137 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
138 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
139 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
140 Op, FI, DAG.getSrcValue(0));
141 if (Op.getOpcode() == PPCISD::FCTIDZ) {
142 Op = DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
144 FI = DAG.getNode(ISD::ADD, MVT::i32, FI, DAG.getConstant(4, MVT::i32));
145 Op = DAG.getLoad(MVT::i32, ST, FI, DAG.getSrcValue(0));
149 case ISD::SINT_TO_FP: {
150 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
151 "Unhandled SINT_TO_FP type in custom expander!");
153 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
154 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
155 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
156 Op.getOperand(0), FI, DAG.getSrcValue(0));
157 SDOperand LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
158 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, LD);
159 if (MVT::f32 == Op.getValueType())
160 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
163 case ISD::SELECT_CC: {
164 // Turn FP only select_cc's into fsel instructions.
165 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
166 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
169 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
171 // Cannot handle SETEQ/SETNE.
172 if (CC == ISD::SETEQ || CC == ISD::SETNE) break;
174 MVT::ValueType ResVT = Op.getValueType();
175 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
176 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
177 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
179 // If the RHS of the comparison is a 0.0, we don't need to do the
180 // subtraction at all.
181 if (isFloatingPointZero(RHS))
183 default: assert(0 && "Invalid FSEL condition"); abort();
186 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
189 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
192 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
195 return DAG.getNode(PPCISD::FSEL, ResVT,
196 DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV);
200 default: assert(0 && "Invalid FSEL condition"); abort();
203 return DAG.getNode(PPCISD::FSEL, ResVT,
204 DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), FV, TV);
207 return DAG.getNode(PPCISD::FSEL, ResVT,
208 DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), TV, FV);
211 return DAG.getNode(PPCISD::FSEL, ResVT,
212 DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), FV, TV);
215 return DAG.getNode(PPCISD::FSEL, ResVT,
216 DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), TV, FV);
221 assert(Op.getValueType() == MVT::i64 &&
222 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
223 // The generic code does a fine job expanding shift by a constant.
224 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
226 // Otherwise, expand into a bunch of logical ops. Note that these ops
227 // depend on the PPC behavior for oversized shift amounts.
228 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
229 DAG.getConstant(0, MVT::i32));
230 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
231 DAG.getConstant(1, MVT::i32));
232 SDOperand Amt = Op.getOperand(1);
234 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
235 DAG.getConstant(32, MVT::i32), Amt);
236 SDOperand Tmp2 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Amt);
237 SDOperand Tmp3 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Tmp1);
238 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
239 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
240 DAG.getConstant(-32U, MVT::i32));
241 SDOperand Tmp6 = DAG.getNode(ISD::SHL, MVT::i32, Lo, Tmp5);
242 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
243 SDOperand OutLo = DAG.getNode(ISD::SHL, MVT::i32, Lo, Amt);
244 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
247 assert(Op.getValueType() == MVT::i64 &&
248 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
249 // The generic code does a fine job expanding shift by a constant.
250 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
252 // Otherwise, expand into a bunch of logical ops. Note that these ops
253 // depend on the PPC behavior for oversized shift amounts.
254 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
255 DAG.getConstant(0, MVT::i32));
256 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
257 DAG.getConstant(1, MVT::i32));
258 SDOperand Amt = Op.getOperand(1);
260 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
261 DAG.getConstant(32, MVT::i32), Amt);
262 SDOperand Tmp2 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Amt);
263 SDOperand Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Tmp1);
264 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
265 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
266 DAG.getConstant(-32U, MVT::i32));
267 SDOperand Tmp6 = DAG.getNode(ISD::SRL, MVT::i32, Hi, Tmp5);
268 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
269 SDOperand OutHi = DAG.getNode(ISD::SRL, MVT::i32, Hi, Amt);
270 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
273 assert(Op.getValueType() == MVT::i64 &&
274 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
275 // The generic code does a fine job expanding shift by a constant.
276 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
278 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
279 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
280 DAG.getConstant(0, MVT::i32));
281 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
282 DAG.getConstant(1, MVT::i32));
283 SDOperand Amt = Op.getOperand(1);
285 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
286 DAG.getConstant(32, MVT::i32), Amt);
287 SDOperand Tmp2 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Amt);
288 SDOperand Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Tmp1);
289 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
290 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
291 DAG.getConstant(-32U, MVT::i32));
292 SDOperand Tmp6 = DAG.getNode(ISD::SRA, MVT::i32, Hi, Tmp5);
293 SDOperand OutHi = DAG.getNode(ISD::SRA, MVT::i32, Hi, Amt);
294 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
295 Tmp4, Tmp6, ISD::SETLE);
296 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
302 std::vector<SDOperand>
303 PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
305 // add beautiful description of PPC stack frame format, or at least some docs
307 MachineFunction &MF = DAG.getMachineFunction();
308 MachineFrameInfo *MFI = MF.getFrameInfo();
309 MachineBasicBlock& BB = MF.front();
310 std::vector<SDOperand> ArgValues;
312 // Due to the rather complicated nature of the PowerPC ABI, rather than a
313 // fixed size array of physical args, for the sake of simplicity let the STL
314 // handle tracking them for us.
315 std::vector<unsigned> argVR, argPR, argOp;
316 unsigned ArgOffset = 24;
317 unsigned GPR_remaining = 8;
318 unsigned FPR_remaining = 13;
319 unsigned GPR_idx = 0, FPR_idx = 0;
320 static const unsigned GPR[] = {
321 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
322 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
324 static const unsigned FPR[] = {
325 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
326 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
329 // Add DAG nodes to load the arguments... On entry to a function on PPC,
330 // the arguments start at offset 24, although they are likely to be passed
332 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
333 SDOperand newroot, argt;
335 bool needsLoad = false;
336 bool ArgLive = !I->use_empty();
337 MVT::ValueType ObjectVT = getValueType(I->getType());
340 default: assert(0 && "Unhandled argument type!");
347 if (GPR_remaining > 0) {
348 MF.addLiveIn(GPR[GPR_idx]);
349 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
350 GPR[GPR_idx], MVT::i32);
351 if (ObjectVT != MVT::i32) {
352 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
354 argt = DAG.getNode(AssertOp, MVT::i32, argt,
355 DAG.getValueType(ObjectVT));
356 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
362 case MVT::i64: ObjSize = 8;
364 if (GPR_remaining > 0) {
365 SDOperand argHi, argLo;
366 MF.addLiveIn(GPR[GPR_idx]);
367 argHi = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
368 // If we have two or more remaining argument registers, then both halves
369 // of the i64 can be sourced from there. Otherwise, the lower half will
370 // have to come off the stack. This can happen when an i64 is preceded
371 // by 28 bytes of arguments.
372 if (GPR_remaining > 1) {
373 MF.addLiveIn(GPR[GPR_idx+1]);
374 argLo = DAG.getCopyFromReg(argHi, GPR[GPR_idx+1], MVT::i32);
376 int FI = MFI->CreateFixedObject(4, ArgOffset+4);
377 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
378 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
379 DAG.getSrcValue(NULL));
381 // Build the outgoing arg thingy
382 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
390 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
392 if (FPR_remaining > 0) {
393 MF.addLiveIn(FPR[FPR_idx]);
394 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
395 FPR[FPR_idx], ObjectVT);
404 // We need to load the argument to a virtual register if we determined above
405 // that we ran out of physical registers of the appropriate type
407 unsigned SubregOffset = 0;
408 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
409 if (ObjectVT == MVT::i16) SubregOffset = 2;
410 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
411 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
412 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
413 DAG.getConstant(SubregOffset, MVT::i32));
414 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
415 DAG.getSrcValue(NULL));
418 // Every 4 bytes of argument space consumes one of the GPRs available for
420 if (GPR_remaining > 0) {
421 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
422 GPR_remaining -= delta;
425 ArgOffset += ObjSize;
427 DAG.setRoot(newroot.getValue(1));
429 ArgValues.push_back(argt);
432 // If the function takes variable number of arguments, make a frame index for
433 // the start of the first vararg value... for expansion of llvm.va_start.
435 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
436 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
437 // If this function is vararg, store any remaining integer argument regs
438 // to their spots on the stack so that they may be loaded by deferencing the
439 // result of va_next.
440 std::vector<SDOperand> MemOps;
441 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
442 MF.addLiveIn(GPR[GPR_idx]);
443 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
444 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
445 Val, FIN, DAG.getSrcValue(NULL));
446 MemOps.push_back(Store);
447 // Increment the address by four for the next argument to store
448 SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
449 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
451 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
454 // Finally, inform the code generator which regs we return values in.
455 switch (getValueType(F.getReturnType())) {
456 default: assert(0 && "Unknown type!");
457 case MVT::isVoid: break;
462 MF.addLiveOut(PPC::R3);
465 MF.addLiveOut(PPC::R3);
466 MF.addLiveOut(PPC::R4);
470 MF.addLiveOut(PPC::F1);
477 std::pair<SDOperand, SDOperand>
478 PPC32TargetLowering::LowerCallTo(SDOperand Chain,
479 const Type *RetTy, bool isVarArg,
480 unsigned CallingConv, bool isTailCall,
481 SDOperand Callee, ArgListTy &Args,
483 // args_to_use will accumulate outgoing args for the ISD::CALL case in
484 // SelectExpr to use to put the arguments in the appropriate registers.
485 std::vector<SDOperand> args_to_use;
487 // Count how many bytes are to be pushed on the stack, including the linkage
488 // area, and parameter passing area.
489 unsigned NumBytes = 24;
492 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
493 DAG.getConstant(NumBytes, getPointerTy()));
495 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
496 switch (getValueType(Args[i].second)) {
497 default: assert(0 && "Unknown value type!");
512 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
513 // plus 32 bytes of argument space in case any called code gets funky on us.
514 // (Required by ABI to support var arg)
515 if (NumBytes < 56) NumBytes = 56;
517 // Adjust the stack pointer for the new arguments...
518 // These operations are automatically eliminated by the prolog/epilog pass
519 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
520 DAG.getConstant(NumBytes, getPointerTy()));
522 // Set up a copy of the stack pointer for use loading and storing any
523 // arguments that may not fit in the registers available for argument
525 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
528 // Figure out which arguments are going to go in registers, and which in
529 // memory. Also, if this is a vararg function, floating point operations
530 // must be stored to our stack, and loaded into integer regs as well, if
531 // any integer regs are available for argument passing.
532 unsigned ArgOffset = 24;
533 unsigned GPR_remaining = 8;
534 unsigned FPR_remaining = 13;
536 std::vector<SDOperand> MemOps;
537 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
538 // PtrOff will be used to store the current argument to the stack if a
539 // register cannot be found for it.
540 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
541 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
542 MVT::ValueType ArgVT = getValueType(Args[i].second);
545 default: assert(0 && "Unexpected ValueType for argument!");
549 // Promote the integer to 32 bits. If the input type is signed use a
550 // sign extend, otherwise use a zero extend.
551 if (Args[i].second->isSigned())
552 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
554 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
557 if (GPR_remaining > 0) {
558 args_to_use.push_back(Args[i].first);
561 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
562 Args[i].first, PtrOff,
563 DAG.getSrcValue(NULL)));
568 // If we have one free GPR left, we can place the upper half of the i64
569 // in it, and store the other half to the stack. If we have two or more
570 // free GPRs, then we can pass both halves of the i64 in registers.
571 if (GPR_remaining > 0) {
572 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
573 Args[i].first, DAG.getConstant(1, MVT::i32));
574 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
575 Args[i].first, DAG.getConstant(0, MVT::i32));
576 args_to_use.push_back(Hi);
578 if (GPR_remaining > 0) {
579 args_to_use.push_back(Lo);
582 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
583 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
584 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
585 Lo, PtrOff, DAG.getSrcValue(NULL)));
588 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
589 Args[i].first, PtrOff,
590 DAG.getSrcValue(NULL)));
596 if (FPR_remaining > 0) {
597 args_to_use.push_back(Args[i].first);
600 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
601 Args[i].first, PtrOff,
602 DAG.getSrcValue(NULL));
603 MemOps.push_back(Store);
604 // Float varargs are always shadowed in available integer registers
605 if (GPR_remaining > 0) {
606 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
607 DAG.getSrcValue(NULL));
608 MemOps.push_back(Load);
609 args_to_use.push_back(Load);
612 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
613 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
614 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
615 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
616 DAG.getSrcValue(NULL));
617 MemOps.push_back(Load);
618 args_to_use.push_back(Load);
622 // If we have any FPRs remaining, we may also have GPRs remaining.
623 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
625 if (GPR_remaining > 0) {
626 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
629 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
630 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
635 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
636 Args[i].first, PtrOff,
637 DAG.getSrcValue(NULL)));
639 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
644 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
647 std::vector<MVT::ValueType> RetVals;
648 MVT::ValueType RetTyVT = getValueType(RetTy);
649 MVT::ValueType ActualRetTyVT = RetTyVT;
650 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16)
651 ActualRetTyVT = MVT::i32; // Promote result to i32.
653 if (RetTyVT != MVT::isVoid)
654 RetVals.push_back(ActualRetTyVT);
655 RetVals.push_back(MVT::Other);
657 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
658 Chain, Callee, args_to_use), 0);
659 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
660 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
661 DAG.getConstant(NumBytes, getPointerTy()));
662 SDOperand RetVal = TheCall;
664 // If the result is a small value, add a note so that we keep track of the
665 // information about whether it is sign or zero extended.
666 if (RetTyVT != ActualRetTyVT) {
667 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
668 MVT::i32, RetVal, DAG.getValueType(RetTyVT));
669 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
672 return std::make_pair(RetVal, Chain);
675 SDOperand PPC32TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
676 Value *VAListV, SelectionDAG &DAG) {
677 // vastart just stores the address of the VarArgsFrameIndex slot into the
678 // memory location argument.
679 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
680 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
681 DAG.getSrcValue(VAListV));
684 std::pair<SDOperand,SDOperand>
685 PPC32TargetLowering::LowerVAArg(SDOperand Chain,
686 SDOperand VAListP, Value *VAListV,
687 const Type *ArgTy, SelectionDAG &DAG) {
688 MVT::ValueType ArgVT = getValueType(ArgTy);
691 DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV));
692 SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL));
694 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
697 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
698 "Other types should have been promoted for varargs!");
701 VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
702 DAG.getConstant(Amt, VAList.getValueType()));
703 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
704 VAList, VAListP, DAG.getSrcValue(VAListV));
705 return std::make_pair(Result, Chain);
709 std::pair<SDOperand, SDOperand> PPC32TargetLowering::
710 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
712 assert(0 && "LowerFrameReturnAddress unimplemented");
717 PPC32TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
718 MachineBasicBlock *BB) {
719 assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
720 MI->getOpcode() == PPC::SELECT_CC_FP) &&
721 "Unexpected instr type to insert");
723 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
724 // control-flow pattern. The incoming instruction knows the destination vreg
725 // to set, the condition code register to branch on, the true/false values to
726 // select between, and a branch opcode to use.
727 const BasicBlock *LLVM_BB = BB->getBasicBlock();
728 ilist<MachineBasicBlock>::iterator It = BB;
736 // fallthrough --> copy0MBB
737 MachineBasicBlock *thisMBB = BB;
738 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
739 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
740 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
741 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
742 MachineFunction *F = BB->getParent();
743 F->getBasicBlockList().insert(It, copy0MBB);
744 F->getBasicBlockList().insert(It, sinkMBB);
745 // Update machine-CFG edges
746 BB->addSuccessor(copy0MBB);
747 BB->addSuccessor(sinkMBB);
751 // # fallthrough to sinkMBB
754 // Update machine-CFG edges
755 BB->addSuccessor(sinkMBB);
758 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
761 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
762 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
763 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
765 delete MI; // The pseudo instruction is gone now.