1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCTargetMachine.h"
16 #include "PPCPerfectShuffle.h"
17 #include "llvm/ADT/VectorExtras.h"
18 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Function.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Target/TargetOptions.h"
31 PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
32 : TargetLowering(TM) {
34 // Fold away setcc operations if possible.
35 setSetCCIsExpensive();
38 // Use _setjmp/_longjmp instead of setjmp/longjmp.
39 setUseUnderscoreSetJmpLongJmp(true);
41 // Set up the register classes.
42 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
43 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
44 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
46 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
47 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
49 // PowerPC has no intrinsics for these particular operations
50 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
51 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
52 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
54 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
55 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
56 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
58 // PowerPC has no SREM/UREM instructions
59 setOperationAction(ISD::SREM, MVT::i32, Expand);
60 setOperationAction(ISD::UREM, MVT::i32, Expand);
62 // We don't support sin/cos/sqrt/fmod
63 setOperationAction(ISD::FSIN , MVT::f64, Expand);
64 setOperationAction(ISD::FCOS , MVT::f64, Expand);
65 setOperationAction(ISD::FREM , MVT::f64, Expand);
66 setOperationAction(ISD::FSIN , MVT::f32, Expand);
67 setOperationAction(ISD::FCOS , MVT::f32, Expand);
68 setOperationAction(ISD::FREM , MVT::f32, Expand);
70 // If we're enabling GP optimizations, use hardware square root
71 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
72 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
73 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
76 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
77 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
79 // PowerPC does not have BSWAP, CTPOP or CTTZ
80 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
81 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
82 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
84 // PowerPC does not have ROTR
85 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
87 // PowerPC does not have Select
88 setOperationAction(ISD::SELECT, MVT::i32, Expand);
89 setOperationAction(ISD::SELECT, MVT::f32, Expand);
90 setOperationAction(ISD::SELECT, MVT::f64, Expand);
92 // PowerPC wants to turn select_cc of FP into fsel when possible.
93 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
94 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
96 // PowerPC wants to optimize integer setcc a bit
97 setOperationAction(ISD::SETCC, MVT::i32, Custom);
99 // PowerPC does not have BRCOND which requires SetCC
100 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
102 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
103 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
105 // PowerPC does not have [U|S]INT_TO_FP
106 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
109 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
110 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
112 // PowerPC does not have truncstore for i1.
113 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
115 // We cannot sextinreg(i1). Expand to shifts.
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
119 // Support label based line numbers.
120 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
121 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
122 // FIXME - use subtarget debug flags
123 if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
124 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
126 // We want to legalize GlobalAddress and ConstantPool nodes into the
127 // appropriate instructions to materialize the address.
128 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
129 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
130 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
132 // RET must be custom lowered, to meet ABI requirements
133 setOperationAction(ISD::RET , MVT::Other, Custom);
135 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
136 setOperationAction(ISD::VASTART , MVT::Other, Custom);
138 // Use the default implementation.
139 setOperationAction(ISD::VAARG , MVT::Other, Expand);
140 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
141 setOperationAction(ISD::VAEND , MVT::Other, Expand);
142 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
143 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
144 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
146 // We want to custom lower some of our intrinsics.
147 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
149 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
150 // They also have instructions for converting between i64 and fp.
151 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
152 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
154 // FIXME: disable this lowered code. This generates 64-bit register values,
155 // and we don't model the fact that the top part is clobbered by calls. We
156 // need to flag these together so that the value isn't live across a call.
157 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
159 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
160 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
162 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
163 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
166 if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) {
167 // 64 bit PowerPC implementations can support i64 types directly
168 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
169 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
170 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
172 // 32 bit PowerPC wants to expand i64 shifts itself.
173 setOperationAction(ISD::SHL, MVT::i64, Custom);
174 setOperationAction(ISD::SRL, MVT::i64, Custom);
175 setOperationAction(ISD::SRA, MVT::i64, Custom);
178 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
179 // First set operation action for all vector types to expand. Then we
180 // will selectively turn on ones that can be effectively codegen'd.
181 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
182 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
183 // add/sub are legal for all supported vector VT's.
184 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
185 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
187 // We promote all shuffles to v16i8.
188 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
189 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
191 // We promote all non-typed operations to v4i32.
192 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
193 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
194 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
195 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
196 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
197 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
198 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
199 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
200 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
201 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
202 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
203 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
205 // No other operations are legal.
206 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
207 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
208 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
209 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
210 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
211 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
212 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
213 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
215 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
218 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
219 // with merges, splats, etc.
220 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
222 setOperationAction(ISD::AND , MVT::v4i32, Legal);
223 setOperationAction(ISD::OR , MVT::v4i32, Legal);
224 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
225 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
226 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
227 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
229 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
230 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
231 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
232 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
234 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
235 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
236 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
237 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
239 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
240 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
242 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
243 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
244 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
245 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
248 setSetCCResultContents(ZeroOrOneSetCCResult);
249 setStackPointerRegisterToSaveRestore(PPC::R1);
251 // We have target-specific dag combine patterns for the following nodes:
252 setTargetDAGCombine(ISD::SINT_TO_FP);
253 setTargetDAGCombine(ISD::STORE);
254 setTargetDAGCombine(ISD::BR_CC);
256 computeRegisterProperties();
259 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
262 case PPCISD::FSEL: return "PPCISD::FSEL";
263 case PPCISD::FCFID: return "PPCISD::FCFID";
264 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
265 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
266 case PPCISD::STFIWX: return "PPCISD::STFIWX";
267 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
268 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
269 case PPCISD::VPERM: return "PPCISD::VPERM";
270 case PPCISD::Hi: return "PPCISD::Hi";
271 case PPCISD::Lo: return "PPCISD::Lo";
272 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
273 case PPCISD::SRL: return "PPCISD::SRL";
274 case PPCISD::SRA: return "PPCISD::SRA";
275 case PPCISD::SHL: return "PPCISD::SHL";
276 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
277 case PPCISD::STD_32: return "PPCISD::STD_32";
278 case PPCISD::CALL: return "PPCISD::CALL";
279 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
280 case PPCISD::MFCR: return "PPCISD::MFCR";
281 case PPCISD::VCMP: return "PPCISD::VCMP";
282 case PPCISD::VCMPo: return "PPCISD::VCMPo";
283 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
287 //===----------------------------------------------------------------------===//
288 // Node matching predicates, for use by the tblgen matching code.
289 //===----------------------------------------------------------------------===//
291 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
292 static bool isFloatingPointZero(SDOperand Op) {
293 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
294 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
295 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
296 // Maybe this has already been legalized into the constant pool?
297 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
298 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
299 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
304 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
305 /// true if Op is undef or if it matches the specified value.
306 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
307 return Op.getOpcode() == ISD::UNDEF ||
308 cast<ConstantSDNode>(Op)->getValue() == Val;
311 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
312 /// VPKUHUM instruction.
313 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
315 for (unsigned i = 0; i != 16; ++i)
316 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
319 for (unsigned i = 0; i != 8; ++i)
320 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
321 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
327 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
328 /// VPKUWUM instruction.
329 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
331 for (unsigned i = 0; i != 16; i += 2)
332 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
333 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
336 for (unsigned i = 0; i != 8; i += 2)
337 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
338 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
339 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
340 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
346 /// isVMerge - Common function, used to match vmrg* shuffles.
348 static bool isVMerge(SDNode *N, unsigned UnitSize,
349 unsigned LHSStart, unsigned RHSStart) {
350 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
351 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
352 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
353 "Unsupported merge size!");
355 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
356 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
357 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
358 LHSStart+j+i*UnitSize) ||
359 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
360 RHSStart+j+i*UnitSize))
366 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
367 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
368 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
370 return isVMerge(N, UnitSize, 8, 24);
371 return isVMerge(N, UnitSize, 8, 8);
374 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
375 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
376 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
378 return isVMerge(N, UnitSize, 0, 16);
379 return isVMerge(N, UnitSize, 0, 0);
383 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
384 /// amount, otherwise return -1.
385 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
386 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
387 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
388 // Find the first non-undef value in the shuffle mask.
390 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
393 if (i == 16) return -1; // all undef.
395 // Otherwise, check to see if the rest of the elements are consequtively
396 // numbered from this value.
397 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
398 if (ShiftAmt < i) return -1;
402 // Check the rest of the elements to see if they are consequtive.
403 for (++i; i != 16; ++i)
404 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
407 // Check the rest of the elements to see if they are consequtive.
408 for (++i; i != 16; ++i)
409 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
416 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
417 /// specifies a splat of a single element that is suitable for input to
418 /// VSPLTB/VSPLTH/VSPLTW.
419 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
420 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
421 N->getNumOperands() == 16 &&
422 (EltSize == 1 || EltSize == 2 || EltSize == 4));
424 // This is a splat operation if each element of the permute is the same, and
425 // if the value doesn't reference the second vector.
426 unsigned ElementBase = 0;
427 SDOperand Elt = N->getOperand(0);
428 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
429 ElementBase = EltV->getValue();
431 return false; // FIXME: Handle UNDEF elements too!
433 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
436 // Check that they are consequtive.
437 for (unsigned i = 1; i != EltSize; ++i) {
438 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
439 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
443 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
444 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
445 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
446 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
447 "Invalid VECTOR_SHUFFLE mask!");
448 for (unsigned j = 0; j != EltSize; ++j)
449 if (N->getOperand(i+j) != N->getOperand(j))
456 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
457 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
458 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
459 assert(isSplatShuffleMask(N, EltSize));
460 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
463 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
464 /// by using a vspltis[bhw] instruction of the specified element size, return
465 /// the constant being splatted. The ByteSize field indicates the number of
466 /// bytes of each element [124] -> [bhw].
467 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
468 SDOperand OpVal(0, 0);
470 // If ByteSize of the splat is bigger than the element size of the
471 // build_vector, then we have a case where we are checking for a splat where
472 // multiple elements of the buildvector are folded together into a single
473 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
474 unsigned EltSize = 16/N->getNumOperands();
475 if (EltSize < ByteSize) {
476 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
477 SDOperand UniquedVals[4];
478 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
480 // See if all of the elements in the buildvector agree across.
481 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
482 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
483 // If the element isn't a constant, bail fully out.
484 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
487 if (UniquedVals[i&(Multiple-1)].Val == 0)
488 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
489 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
490 return SDOperand(); // no match.
493 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
494 // either constant or undef values that are identical for each chunk. See
495 // if these chunks can form into a larger vspltis*.
497 // Check to see if all of the leading entries are either 0 or -1. If
498 // neither, then this won't fit into the immediate field.
499 bool LeadingZero = true;
500 bool LeadingOnes = true;
501 for (unsigned i = 0; i != Multiple-1; ++i) {
502 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
504 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
505 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
507 // Finally, check the least significant entry.
509 if (UniquedVals[Multiple-1].Val == 0)
510 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
511 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
513 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
516 if (UniquedVals[Multiple-1].Val == 0)
517 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
518 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
519 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
520 return DAG.getTargetConstant(Val, MVT::i32);
526 // Check to see if this buildvec has a single non-undef value in its elements.
527 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
528 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
530 OpVal = N->getOperand(i);
531 else if (OpVal != N->getOperand(i))
535 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
537 unsigned ValSizeInBytes = 0;
539 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
540 Value = CN->getValue();
541 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
542 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
543 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
544 Value = FloatToBits(CN->getValue());
548 // If the splat value is larger than the element value, then we can never do
549 // this splat. The only case that we could fit the replicated bits into our
550 // immediate field for would be zero, and we prefer to use vxor for it.
551 if (ValSizeInBytes < ByteSize) return SDOperand();
553 // If the element value is larger than the splat value, cut it in half and
554 // check to see if the two halves are equal. Continue doing this until we
555 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
556 while (ValSizeInBytes > ByteSize) {
557 ValSizeInBytes >>= 1;
559 // If the top half equals the bottom half, we're still ok.
560 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
561 (Value & ((1 << (8*ValSizeInBytes))-1)))
565 // Properly sign extend the value.
566 int ShAmt = (4-ByteSize)*8;
567 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
569 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
570 if (MaskVal == 0) return SDOperand();
572 // Finally, if this value fits in a 5 bit sext field, return it
573 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
574 return DAG.getTargetConstant(MaskVal, MVT::i32);
578 //===----------------------------------------------------------------------===//
579 // LowerOperation implementation
580 //===----------------------------------------------------------------------===//
582 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
583 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
584 Constant *C = CP->get();
585 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32, CP->getAlignment());
586 SDOperand Zero = DAG.getConstant(0, MVT::i32);
588 const TargetMachine &TM = DAG.getTarget();
590 // If this is a non-darwin platform, we don't support non-static relo models
592 if (TM.getRelocationModel() == Reloc::Static ||
593 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
594 // Generate non-pic code that has direct accesses to the constant pool.
595 // The address of the global is just (hi(&g)+lo(&g)).
596 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
597 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
598 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
601 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
602 if (TM.getRelocationModel() == Reloc::PIC) {
603 // With PIC, the first instruction is actually "GR+hi(&G)".
604 Hi = DAG.getNode(ISD::ADD, MVT::i32,
605 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
608 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
609 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
613 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
614 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
615 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
616 SDOperand Zero = DAG.getConstant(0, MVT::i32);
618 const TargetMachine &TM = DAG.getTarget();
620 // If this is a non-darwin platform, we don't support non-static relo models
622 if (TM.getRelocationModel() == Reloc::Static ||
623 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
624 // Generate non-pic code that has direct accesses to the constant pool.
625 // The address of the global is just (hi(&g)+lo(&g)).
626 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, JTI, Zero);
627 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, JTI, Zero);
628 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
631 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, JTI, Zero);
632 if (TM.getRelocationModel() == Reloc::PIC) {
633 // With PIC, the first instruction is actually "GR+hi(&G)".
634 Hi = DAG.getNode(ISD::ADD, MVT::i32,
635 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
638 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, JTI, Zero);
639 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
643 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
644 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
645 GlobalValue *GV = GSDN->getGlobal();
646 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset());
647 SDOperand Zero = DAG.getConstant(0, MVT::i32);
649 const TargetMachine &TM = DAG.getTarget();
651 // If this is a non-darwin platform, we don't support non-static relo models
653 if (TM.getRelocationModel() == Reloc::Static ||
654 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
655 // Generate non-pic code that has direct accesses to globals.
656 // The address of the global is just (hi(&g)+lo(&g)).
657 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
658 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
659 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
662 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
663 if (TM.getRelocationModel() == Reloc::PIC) {
664 // With PIC, the first instruction is actually "GR+hi(&G)".
665 Hi = DAG.getNode(ISD::ADD, MVT::i32,
666 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
669 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
670 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
672 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() &&
673 (!GV->isExternal() || GV->hasNotBeenReadFromBytecode()))
676 // If the global is weak or external, we have to go through the lazy
678 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
681 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
682 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
684 // If we're comparing for equality to zero, expose the fact that this is
685 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
686 // fold the new nodes.
687 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
688 if (C->isNullValue() && CC == ISD::SETEQ) {
689 MVT::ValueType VT = Op.getOperand(0).getValueType();
690 SDOperand Zext = Op.getOperand(0);
693 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
695 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
696 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
697 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
698 DAG.getConstant(Log2b, MVT::i32));
699 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
701 // Leave comparisons against 0 and -1 alone for now, since they're usually
702 // optimized. FIXME: revisit this when we can custom lower all setcc
704 if (C->isAllOnesValue() || C->isNullValue())
708 // If we have an integer seteq/setne, turn it into a compare against zero
709 // by subtracting the rhs from the lhs, which is faster than setting a
710 // condition register, reading it back out, and masking the correct bit.
711 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
712 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
713 MVT::ValueType VT = Op.getValueType();
714 SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0),
716 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
721 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
722 unsigned VarArgsFrameIndex) {
723 // vastart just stores the address of the VarArgsFrameIndex slot into the
724 // memory location argument.
725 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
726 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
727 Op.getOperand(1), Op.getOperand(2));
730 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
731 int &VarArgsFrameIndex) {
732 // TODO: add description of PPC stack frame format, or at least some docs.
734 MachineFunction &MF = DAG.getMachineFunction();
735 MachineFrameInfo *MFI = MF.getFrameInfo();
736 SSARegMap *RegMap = MF.getSSARegMap();
737 std::vector<SDOperand> ArgValues;
738 SDOperand Root = Op.getOperand(0);
740 unsigned ArgOffset = 24;
741 const unsigned Num_GPR_Regs = 8;
742 const unsigned Num_FPR_Regs = 13;
743 const unsigned Num_VR_Regs = 12;
744 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
745 static const unsigned GPR[] = {
746 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
747 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
749 static const unsigned FPR[] = {
750 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
751 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
753 static const unsigned VR[] = {
754 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
755 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
758 // Add DAG nodes to load the arguments or copy them out of registers. On
759 // entry to a function on PPC, the arguments start at offset 24, although the
760 // first ones are often in registers.
761 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
763 bool needsLoad = false;
764 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
765 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
767 unsigned CurArgOffset = ArgOffset;
770 default: assert(0 && "Unhandled argument type!");
772 // All int arguments reserve stack space.
775 if (GPR_idx != Num_GPR_Regs) {
776 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
777 MF.addLiveIn(GPR[GPR_idx], VReg);
778 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
786 // All FP arguments reserve stack space.
787 ArgOffset += ObjSize;
789 // Every 4 bytes of argument space consumes one of the GPRs available for
791 if (GPR_idx != Num_GPR_Regs) {
793 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs)
796 if (FPR_idx != Num_FPR_Regs) {
798 if (ObjectVT == MVT::f32)
799 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
801 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
802 MF.addLiveIn(FPR[FPR_idx], VReg);
803 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
813 // Note that vector arguments in registers don't reserve stack space.
814 if (VR_idx != Num_VR_Regs) {
815 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass);
816 MF.addLiveIn(VR[VR_idx], VReg);
817 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
820 // This should be simple, but requires getting 16-byte aligned stack
822 assert(0 && "Loading VR argument not implemented yet!");
828 // We need to load the argument to a virtual register if we determined above
829 // that we ran out of physical registers of the appropriate type
831 // If the argument is actually used, emit a load from the right stack
833 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
834 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
835 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
836 ArgVal = DAG.getLoad(ObjectVT, Root, FIN,
837 DAG.getSrcValue(NULL));
839 // Don't emit a dead load.
840 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
844 ArgValues.push_back(ArgVal);
847 // If the function takes variable number of arguments, make a frame index for
848 // the start of the first vararg value... for expansion of llvm.va_start.
849 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
851 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
852 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
853 // If this function is vararg, store any remaining integer argument regs
854 // to their spots on the stack so that they may be loaded by deferencing the
855 // result of va_next.
856 std::vector<SDOperand> MemOps;
857 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
858 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
859 MF.addLiveIn(GPR[GPR_idx], VReg);
860 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
861 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
862 Val, FIN, DAG.getSrcValue(NULL));
863 MemOps.push_back(Store);
864 // Increment the address by four for the next argument to store
865 SDOperand PtrOff = DAG.getConstant(4, MVT::i32);
866 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
869 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
872 ArgValues.push_back(Root);
874 // Return the new list of results.
875 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
876 Op.Val->value_end());
877 return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
880 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
881 SDOperand Chain = Op.getOperand(0);
882 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
883 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
884 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
885 SDOperand Callee = Op.getOperand(4);
887 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
888 // SelectExpr to use to put the arguments in the appropriate registers.
889 std::vector<SDOperand> args_to_use;
891 // Count how many bytes are to be pushed on the stack, including the linkage
892 // area, and parameter passing area.
893 unsigned NumBytes = 24;
895 if (Op.getNumOperands() == 5) {
896 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, MVT::i32));
898 for (unsigned i = 5, e = Op.getNumOperands(); i != e; ++i)
899 NumBytes += MVT::getSizeInBits(Op.getOperand(i).getValueType())/8;
901 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
902 // plus 32 bytes of argument space in case any called code gets funky on us.
903 // (Required by ABI to support var arg)
904 if (NumBytes < 56) NumBytes = 56;
906 // Adjust the stack pointer for the new arguments...
907 // These operations are automatically eliminated by the prolog/epilog pass
908 Chain = DAG.getCALLSEQ_START(Chain,
909 DAG.getConstant(NumBytes, MVT::i32));
911 // Set up a copy of the stack pointer for use loading and storing any
912 // arguments that may not fit in the registers available for argument
914 SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
916 // Figure out which arguments are going to go in registers, and which in
917 // memory. Also, if this is a vararg function, floating point operations
918 // must be stored to our stack, and loaded into integer regs as well, if
919 // any integer regs are available for argument passing.
920 unsigned ArgOffset = 24;
921 unsigned GPR_remaining = 8;
922 unsigned FPR_remaining = 13;
923 unsigned VR_remaining = 12;
925 std::vector<SDOperand> MemOps;
926 for (unsigned i = 5, e = Op.getNumOperands(); i != e; ++i) {
927 SDOperand Arg = Op.getOperand(i);
929 // PtrOff will be used to store the current argument to the stack if a
930 // register cannot be found for it.
931 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
932 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
933 switch (Arg.getValueType()) {
934 default: assert(0 && "Unexpected ValueType for argument!");
936 if (GPR_remaining > 0) {
937 args_to_use.push_back(Arg);
940 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
941 Arg, PtrOff, DAG.getSrcValue(NULL)));
947 if (FPR_remaining > 0) {
948 args_to_use.push_back(Arg);
951 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
953 DAG.getSrcValue(NULL));
954 MemOps.push_back(Store);
955 // Float varargs are always shadowed in available integer registers
956 if (GPR_remaining > 0) {
957 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
958 DAG.getSrcValue(NULL));
959 MemOps.push_back(Load.getValue(1));
960 args_to_use.push_back(Load);
963 if (GPR_remaining > 0 && Arg.getValueType() == MVT::f64) {
964 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
965 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
966 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
967 DAG.getSrcValue(NULL));
968 MemOps.push_back(Load.getValue(1));
969 args_to_use.push_back(Load);
973 // If we have any FPRs remaining, we may also have GPRs remaining.
974 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
976 if (GPR_remaining > 0) {
977 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
980 if (GPR_remaining > 0 && Arg.getValueType() == MVT::f64) {
981 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
986 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
987 Arg, PtrOff, DAG.getSrcValue(NULL)));
989 ArgOffset += (Arg.getValueType() == MVT::f32) ? 4 : 8;
995 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
996 assert(VR_remaining &&
997 "Don't support passing more than 12 vector args yet!");
998 args_to_use.push_back(Arg);
1003 if (!MemOps.empty())
1004 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
1007 std::vector<MVT::ValueType> RetVals(Op.Val->value_begin(),
1008 Op.Val->value_end());
1010 // If the callee is a GlobalAddress node (quite common, every direct call is)
1011 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1012 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1013 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
1015 std::vector<SDOperand> Ops;
1016 Ops.push_back(Chain);
1017 Ops.push_back(Callee);
1018 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
1019 SDOperand TheCall = DAG.getNode(PPCISD::CALL, RetVals, Ops);
1021 Chain = TheCall.getValue(TheCall.Val->getNumValues()-1);
1022 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1023 DAG.getConstant(NumBytes, MVT::i32));
1025 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1026 Op.Val->value_end());
1029 for (unsigned i = 0, e = TheCall.Val->getNumValues()-1; i != e; ++i)
1030 Ops.push_back(SDOperand(TheCall.Val, i));
1031 Ops.push_back(Chain);
1032 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, RetVT, Ops);
1034 return Res.getValue(Op.ResNo);
1037 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
1039 switch(Op.getNumOperands()) {
1041 assert(0 && "Do not know how to return this many arguments!");
1044 return SDOperand(); // ret void is legal
1046 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
1048 if (MVT::isVector(ArgVT))
1050 else if (MVT::isInteger(ArgVT))
1053 assert(MVT::isFloatingPoint(ArgVT));
1057 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
1060 // If we haven't noted the R3/F1 are live out, do so now.
1061 if (DAG.getMachineFunction().liveout_empty())
1062 DAG.getMachineFunction().addLiveOut(ArgReg);
1066 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2),
1068 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
1069 // If we haven't noted the R3+R4 are live out, do so now.
1070 if (DAG.getMachineFunction().liveout_empty()) {
1071 DAG.getMachineFunction().addLiveOut(PPC::R3);
1072 DAG.getMachineFunction().addLiveOut(PPC::R4);
1076 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
1079 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
1081 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
1082 // Not FP? Not a fsel.
1083 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
1084 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
1087 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1089 // Cannot handle SETEQ/SETNE.
1090 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
1092 MVT::ValueType ResVT = Op.getValueType();
1093 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
1094 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1095 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
1097 // If the RHS of the comparison is a 0.0, we don't need to do the
1098 // subtraction at all.
1099 if (isFloatingPointZero(RHS))
1101 default: break; // SETUO etc aren't handled by fsel.
1104 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1107 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1108 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1109 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
1112 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1115 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1116 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1117 return DAG.getNode(PPCISD::FSEL, ResVT,
1118 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
1123 default: break; // SETUO etc aren't handled by fsel.
1126 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1127 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1128 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1129 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1132 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1133 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1134 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1135 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1138 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1139 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1140 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1141 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1144 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1145 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1146 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1147 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1152 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
1153 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
1154 SDOperand Src = Op.getOperand(0);
1155 if (Src.getValueType() == MVT::f32)
1156 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
1159 switch (Op.getValueType()) {
1160 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
1162 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
1165 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
1169 // Convert the FP value to an int value through memory.
1170 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
1171 if (Op.getValueType() == MVT::i32)
1172 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
1176 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1177 if (Op.getOperand(0).getValueType() == MVT::i64) {
1178 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
1179 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
1180 if (Op.getValueType() == MVT::f32)
1181 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1185 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
1186 "Unhandled SINT_TO_FP type in custom expander!");
1187 // Since we only generate this in 64-bit mode, we can take advantage of
1188 // 64-bit registers. In particular, sign extend the input value into the
1189 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
1190 // then lfd it and fcfid it.
1191 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
1192 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
1193 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
1195 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
1198 // STD the extended value into the stack slot.
1199 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
1200 DAG.getEntryNode(), Ext64, FIdx,
1201 DAG.getSrcValue(NULL));
1202 // Load the value as a double.
1203 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL));
1205 // FCFID it and return it.
1206 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
1207 if (Op.getValueType() == MVT::f32)
1208 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1212 static SDOperand LowerSHL(SDOperand Op, SelectionDAG &DAG) {
1213 assert(Op.getValueType() == MVT::i64 &&
1214 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
1215 // The generic code does a fine job expanding shift by a constant.
1216 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
1218 // Otherwise, expand into a bunch of logical ops. Note that these ops
1219 // depend on the PPC behavior for oversized shift amounts.
1220 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1221 DAG.getConstant(0, MVT::i32));
1222 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1223 DAG.getConstant(1, MVT::i32));
1224 SDOperand Amt = Op.getOperand(1);
1226 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1227 DAG.getConstant(32, MVT::i32), Amt);
1228 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
1229 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
1230 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1231 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1232 DAG.getConstant(-32U, MVT::i32));
1233 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
1234 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1235 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
1236 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
1239 static SDOperand LowerSRL(SDOperand Op, SelectionDAG &DAG) {
1240 assert(Op.getValueType() == MVT::i64 &&
1241 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
1242 // The generic code does a fine job expanding shift by a constant.
1243 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
1245 // Otherwise, expand into a bunch of logical ops. Note that these ops
1246 // depend on the PPC behavior for oversized shift amounts.
1247 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1248 DAG.getConstant(0, MVT::i32));
1249 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1250 DAG.getConstant(1, MVT::i32));
1251 SDOperand Amt = Op.getOperand(1);
1253 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1254 DAG.getConstant(32, MVT::i32), Amt);
1255 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1256 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1257 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1258 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1259 DAG.getConstant(-32U, MVT::i32));
1260 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
1261 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1262 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
1263 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
1266 static SDOperand LowerSRA(SDOperand Op, SelectionDAG &DAG) {
1267 assert(Op.getValueType() == MVT::i64 &&
1268 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
1269 // The generic code does a fine job expanding shift by a constant.
1270 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
1272 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
1273 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1274 DAG.getConstant(0, MVT::i32));
1275 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1276 DAG.getConstant(1, MVT::i32));
1277 SDOperand Amt = Op.getOperand(1);
1279 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1280 DAG.getConstant(32, MVT::i32), Amt);
1281 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1282 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1283 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1284 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1285 DAG.getConstant(-32U, MVT::i32));
1286 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
1287 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
1288 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
1289 Tmp4, Tmp6, ISD::SETLE);
1290 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
1293 //===----------------------------------------------------------------------===//
1294 // Vector related lowering.
1297 // If this is a vector of constants or undefs, get the bits. A bit in
1298 // UndefBits is set if the corresponding element of the vector is an
1299 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1300 // zero. Return true if this is not an array of constants, false if it is.
1302 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
1303 uint64_t UndefBits[2]) {
1304 // Start with zero'd results.
1305 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
1307 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
1308 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
1309 SDOperand OpVal = BV->getOperand(i);
1311 unsigned PartNo = i >= e/2; // In the upper 128 bits?
1312 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
1314 uint64_t EltBits = 0;
1315 if (OpVal.getOpcode() == ISD::UNDEF) {
1316 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
1317 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
1319 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1320 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
1321 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1322 assert(CN->getValueType(0) == MVT::f32 &&
1323 "Only one legal FP vector type!");
1324 EltBits = FloatToBits(CN->getValue());
1326 // Nonconstant element.
1330 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
1333 //printf("%llx %llx %llx %llx\n",
1334 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
1338 // If this is a splat (repetition) of a value across the whole vector, return
1339 // the smallest size that splats it. For example, "0x01010101010101..." is a
1340 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1341 // SplatSize = 1 byte.
1342 static bool isConstantSplat(const uint64_t Bits128[2],
1343 const uint64_t Undef128[2],
1344 unsigned &SplatBits, unsigned &SplatUndef,
1345 unsigned &SplatSize) {
1347 // Don't let undefs prevent splats from matching. See if the top 64-bits are
1348 // the same as the lower 64-bits, ignoring undefs.
1349 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
1350 return false; // Can't be a splat if two pieces don't match.
1352 uint64_t Bits64 = Bits128[0] | Bits128[1];
1353 uint64_t Undef64 = Undef128[0] & Undef128[1];
1355 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
1357 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
1358 return false; // Can't be a splat if two pieces don't match.
1360 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
1361 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
1363 // If the top 16-bits are different than the lower 16-bits, ignoring
1364 // undefs, we have an i32 splat.
1365 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
1367 SplatUndef = Undef32;
1372 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
1373 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
1375 // If the top 8-bits are different than the lower 8-bits, ignoring
1376 // undefs, we have an i16 splat.
1377 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
1379 SplatUndef = Undef16;
1384 // Otherwise, we have an 8-bit splat.
1385 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
1386 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
1391 /// BuildSplatI - Build a canonical splati of Val with an element size of
1392 /// SplatSize. Cast the result to VT.
1393 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
1394 SelectionDAG &DAG) {
1395 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
1397 // Force vspltis[hw] -1 to vspltisb -1.
1398 if (Val == -1) SplatSize = 1;
1400 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
1401 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
1403 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
1405 // Build a canonical splat for this value.
1406 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT));
1407 std::vector<SDOperand> Ops(MVT::getVectorNumElements(CanonicalVT), Elt);
1408 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops);
1409 return DAG.getNode(ISD::BIT_CONVERT, VT, Res);
1412 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
1413 /// specified intrinsic ID.
1414 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
1416 MVT::ValueType DestVT = MVT::Other) {
1417 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
1418 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1419 DAG.getConstant(IID, MVT::i32), LHS, RHS);
1422 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
1423 /// specified intrinsic ID.
1424 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
1425 SDOperand Op2, SelectionDAG &DAG,
1426 MVT::ValueType DestVT = MVT::Other) {
1427 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
1428 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1429 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
1433 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
1434 /// amount. The result has the specified value type.
1435 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
1436 MVT::ValueType VT, SelectionDAG &DAG) {
1437 // Force LHS/RHS to be the right type.
1438 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
1439 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
1441 std::vector<SDOperand> Ops;
1442 for (unsigned i = 0; i != 16; ++i)
1443 Ops.push_back(DAG.getConstant(i+Amt, MVT::i32));
1444 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
1445 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
1446 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
1449 // If this is a case we can't handle, return null and let the default
1450 // expansion code take care of it. If we CAN select this case, and if it
1451 // selects to a single instruction, return Op. Otherwise, if we can codegen
1452 // this case more efficiently than a constant pool load, lower it to the
1453 // sequence of ops that should be used.
1454 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
1455 // If this is a vector of constants or undefs, get the bits. A bit in
1456 // UndefBits is set if the corresponding element of the vector is an
1457 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1459 uint64_t VectorBits[2];
1460 uint64_t UndefBits[2];
1461 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
1462 return SDOperand(); // Not a constant vector.
1464 // If this is a splat (repetition) of a value across the whole vector, return
1465 // the smallest size that splats it. For example, "0x01010101010101..." is a
1466 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1467 // SplatSize = 1 byte.
1468 unsigned SplatBits, SplatUndef, SplatSize;
1469 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
1470 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
1472 // First, handle single instruction cases.
1475 if (SplatBits == 0) {
1476 // Canonicalize all zero vectors to be v4i32.
1477 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
1478 SDOperand Z = DAG.getConstant(0, MVT::i32);
1479 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
1480 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
1485 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
1486 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
1487 if (SextVal >= -16 && SextVal <= 15)
1488 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
1491 // Two instruction sequences.
1493 // If this value is in the range [-32,30] and is even, use:
1494 // tmp = VSPLTI[bhw], result = add tmp, tmp
1495 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
1496 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
1497 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
1500 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
1501 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
1503 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
1504 // Make -1 and vspltisw -1:
1505 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
1507 // Make the VSLW intrinsic, computing 0x8000_0000.
1508 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
1511 // xor by OnesV to invert it.
1512 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
1513 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
1516 // Check to see if this is a wide variety of vsplti*, binop self cases.
1517 unsigned SplatBitSize = SplatSize*8;
1518 static const char SplatCsts[] = {
1519 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
1520 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
1522 for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){
1523 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
1524 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
1525 int i = SplatCsts[idx];
1527 // Figure out what shift amount will be used by altivec if shifted by i in
1529 unsigned TypeShiftAmt = i & (SplatBitSize-1);
1531 // vsplti + shl self.
1532 if (SextVal == (i << (int)TypeShiftAmt)) {
1533 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1534 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1535 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
1536 Intrinsic::ppc_altivec_vslw
1538 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1541 // vsplti + srl self.
1542 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
1543 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1544 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1545 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
1546 Intrinsic::ppc_altivec_vsrw
1548 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1551 // vsplti + sra self.
1552 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
1553 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1554 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1555 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
1556 Intrinsic::ppc_altivec_vsraw
1558 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1561 // vsplti + rol self.
1562 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
1563 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
1564 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1565 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1566 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
1567 Intrinsic::ppc_altivec_vrlw
1569 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1572 // t = vsplti c, result = vsldoi t, t, 1
1573 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
1574 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1575 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
1577 // t = vsplti c, result = vsldoi t, t, 2
1578 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
1579 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1580 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
1582 // t = vsplti c, result = vsldoi t, t, 3
1583 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
1584 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1585 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
1589 // Three instruction sequences.
1591 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
1592 if (SextVal >= 0 && SextVal <= 31) {
1593 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, Op.getValueType(),DAG);
1594 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
1595 return DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
1597 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
1598 if (SextVal >= -31 && SextVal <= 0) {
1599 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, Op.getValueType(),DAG);
1600 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
1601 return DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
1608 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
1609 /// the specified operations to build the shuffle.
1610 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
1611 SDOperand RHS, SelectionDAG &DAG) {
1612 unsigned OpNum = (PFEntry >> 26) & 0x0F;
1613 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
1614 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
1617 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
1629 if (OpNum == OP_COPY) {
1630 if (LHSID == (1*9+2)*9+3) return LHS;
1631 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
1635 SDOperand OpLHS, OpRHS;
1636 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
1637 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
1639 unsigned ShufIdxs[16];
1641 default: assert(0 && "Unknown i32 permute!");
1643 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
1644 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
1645 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
1646 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
1649 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
1650 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
1651 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
1652 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
1655 for (unsigned i = 0; i != 16; ++i)
1656 ShufIdxs[i] = (i&3)+0;
1659 for (unsigned i = 0; i != 16; ++i)
1660 ShufIdxs[i] = (i&3)+4;
1663 for (unsigned i = 0; i != 16; ++i)
1664 ShufIdxs[i] = (i&3)+8;
1667 for (unsigned i = 0; i != 16; ++i)
1668 ShufIdxs[i] = (i&3)+12;
1671 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
1673 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
1675 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
1677 std::vector<SDOperand> Ops;
1678 for (unsigned i = 0; i != 16; ++i)
1679 Ops.push_back(DAG.getConstant(ShufIdxs[i], MVT::i32));
1681 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
1682 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
1685 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
1686 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
1687 /// return the code it can be lowered into. Worst case, it can always be
1688 /// lowered into a vperm.
1689 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
1690 SDOperand V1 = Op.getOperand(0);
1691 SDOperand V2 = Op.getOperand(1);
1692 SDOperand PermMask = Op.getOperand(2);
1694 // Cases that are handled by instructions that take permute immediates
1695 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
1696 // selected by the instruction selector.
1697 if (V2.getOpcode() == ISD::UNDEF) {
1698 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
1699 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
1700 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
1701 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
1702 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
1703 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
1704 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
1705 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
1706 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
1707 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
1708 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
1709 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
1714 // Altivec has a variety of "shuffle immediates" that take two vector inputs
1715 // and produce a fixed permutation. If any of these match, do not lower to
1717 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
1718 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
1719 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
1720 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
1721 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
1722 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
1723 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
1724 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
1725 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
1728 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
1729 // perfect shuffle table to emit an optimal matching sequence.
1730 unsigned PFIndexes[4];
1731 bool isFourElementShuffle = true;
1732 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
1733 unsigned EltNo = 8; // Start out undef.
1734 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
1735 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
1736 continue; // Undef, ignore it.
1738 unsigned ByteSource =
1739 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
1740 if ((ByteSource & 3) != j) {
1741 isFourElementShuffle = false;
1746 EltNo = ByteSource/4;
1747 } else if (EltNo != ByteSource/4) {
1748 isFourElementShuffle = false;
1752 PFIndexes[i] = EltNo;
1755 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
1756 // perfect shuffle vector to determine if it is cost effective to do this as
1757 // discrete instructions, or whether we should use a vperm.
1758 if (isFourElementShuffle) {
1759 // Compute the index in the perfect shuffle table.
1760 unsigned PFTableIndex =
1761 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
1763 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
1764 unsigned Cost = (PFEntry >> 30);
1766 // Determining when to avoid vperm is tricky. Many things affect the cost
1767 // of vperm, particularly how many times the perm mask needs to be computed.
1768 // For example, if the perm mask can be hoisted out of a loop or is already
1769 // used (perhaps because there are multiple permutes with the same shuffle
1770 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
1771 // the loop requires an extra register.
1773 // As a compromise, we only emit discrete instructions if the shuffle can be
1774 // generated in 3 or fewer operations. When we have loop information
1775 // available, if this block is within a loop, we should avoid using vperm
1776 // for 3-operation perms and use a constant pool load instead.
1778 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
1781 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
1782 // vector that will get spilled to the constant pool.
1783 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
1785 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
1786 // that it is in input element units, not in bytes. Convert now.
1787 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
1788 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
1790 std::vector<SDOperand> ResultMask;
1791 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
1793 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
1796 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
1798 for (unsigned j = 0; j != BytesPerElement; ++j)
1799 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
1803 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask);
1804 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
1807 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
1808 /// altivec comparison. If it is, return true and fill in Opc/isDot with
1809 /// information about the intrinsic.
1810 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
1812 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
1815 switch (IntrinsicID) {
1816 default: return false;
1817 // Comparison predicates.
1818 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
1819 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
1820 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
1821 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
1822 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
1823 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
1824 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
1825 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
1826 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
1827 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
1828 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
1829 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
1830 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
1832 // Normal Comparisons.
1833 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
1834 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
1835 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
1836 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
1837 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
1838 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
1839 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
1840 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
1841 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
1842 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
1843 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
1844 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
1845 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
1850 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
1851 /// lower, do it, otherwise return null.
1852 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
1853 // If this is a lowered altivec predicate compare, CompareOpc is set to the
1854 // opcode number of the comparison.
1857 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
1858 return SDOperand(); // Don't custom lower most intrinsics.
1860 // If this is a non-dot comparison, make the VCMP node and we are done.
1862 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
1863 Op.getOperand(1), Op.getOperand(2),
1864 DAG.getConstant(CompareOpc, MVT::i32));
1865 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
1868 // Create the PPCISD altivec 'dot' comparison node.
1869 std::vector<SDOperand> Ops;
1870 std::vector<MVT::ValueType> VTs;
1871 Ops.push_back(Op.getOperand(2)); // LHS
1872 Ops.push_back(Op.getOperand(3)); // RHS
1873 Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32));
1874 VTs.push_back(Op.getOperand(2).getValueType());
1875 VTs.push_back(MVT::Flag);
1876 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops);
1878 // Now that we have the comparison, emit a copy from the CR to a GPR.
1879 // This is flagged to the above dot comparison.
1880 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
1881 DAG.getRegister(PPC::CR6, MVT::i32),
1882 CompNode.getValue(1));
1884 // Unpack the result based on how the target uses it.
1885 unsigned BitNo; // Bit # of CR6.
1886 bool InvertBit; // Invert result?
1887 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
1888 default: // Can't happen, don't crash on invalid number though.
1889 case 0: // Return the value of the EQ bit of CR6.
1890 BitNo = 0; InvertBit = false;
1892 case 1: // Return the inverted value of the EQ bit of CR6.
1893 BitNo = 0; InvertBit = true;
1895 case 2: // Return the value of the LT bit of CR6.
1896 BitNo = 2; InvertBit = false;
1898 case 3: // Return the inverted value of the LT bit of CR6.
1899 BitNo = 2; InvertBit = true;
1903 // Shift the bit into the low position.
1904 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
1905 DAG.getConstant(8-(3-BitNo), MVT::i32));
1907 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
1908 DAG.getConstant(1, MVT::i32));
1910 // If we are supposed to, toggle the bit.
1912 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
1913 DAG.getConstant(1, MVT::i32));
1917 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
1918 // Create a stack slot that is 16-byte aligned.
1919 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
1920 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
1921 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
1923 // Store the input value into Value#0 of the stack slot.
1924 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
1925 Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
1927 return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL));
1930 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
1931 if (Op.getValueType() == MVT::v4i32) {
1932 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1934 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
1935 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
1937 SDOperand RHSSwap = // = vrlw RHS, 16
1938 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
1940 // Shrinkify inputs to v8i16.
1941 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
1942 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
1943 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
1945 // Low parts multiplied together, generating 32-bit results (we ignore the
1947 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
1948 LHS, RHS, DAG, MVT::v4i32);
1950 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
1951 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
1952 // Shift the high parts up 16 bits.
1953 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
1954 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
1955 } else if (Op.getValueType() == MVT::v8i16) {
1956 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1958 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
1960 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
1961 LHS, RHS, Zero, DAG);
1962 } else if (Op.getValueType() == MVT::v16i8) {
1963 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1965 // Multiply the even 8-bit parts, producing 16-bit sums.
1966 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
1967 LHS, RHS, DAG, MVT::v8i16);
1968 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
1970 // Multiply the odd 8-bit parts, producing 16-bit sums.
1971 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
1972 LHS, RHS, DAG, MVT::v8i16);
1973 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
1975 // Merge the results together.
1976 std::vector<SDOperand> Ops;
1977 for (unsigned i = 0; i != 8; ++i) {
1978 Ops.push_back(DAG.getConstant(2*i+1, MVT::i8));
1979 Ops.push_back(DAG.getConstant(2*i+1+16, MVT::i8));
1982 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
1983 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
1985 assert(0 && "Unknown mul to lower!");
1990 /// LowerOperation - Provide custom lowering hooks for some operations.
1992 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1993 switch (Op.getOpcode()) {
1994 default: assert(0 && "Wasn't expecting to be able to lower this!");
1995 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1996 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
1997 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
1998 case ISD::SETCC: return LowerSETCC(Op, DAG);
1999 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2000 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
2002 case ISD::CALL: return LowerCALL(Op, DAG);
2003 case ISD::RET: return LowerRET(Op, DAG);
2005 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2006 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
2007 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
2009 // Lower 64-bit shifts.
2010 case ISD::SHL: return LowerSHL(Op, DAG);
2011 case ISD::SRL: return LowerSRL(Op, DAG);
2012 case ISD::SRA: return LowerSRA(Op, DAG);
2014 // Vector-related lowering.
2015 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2016 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2017 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2018 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2019 case ISD::MUL: return LowerMUL(Op, DAG);
2024 //===----------------------------------------------------------------------===//
2025 // Other Lowering Code
2026 //===----------------------------------------------------------------------===//
2029 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2030 MachineBasicBlock *BB) {
2031 assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
2032 MI->getOpcode() == PPC::SELECT_CC_F4 ||
2033 MI->getOpcode() == PPC::SELECT_CC_F8 ||
2034 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
2035 "Unexpected instr type to insert");
2037 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2038 // control-flow pattern. The incoming instruction knows the destination vreg
2039 // to set, the condition code register to branch on, the true/false values to
2040 // select between, and a branch opcode to use.
2041 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2042 ilist<MachineBasicBlock>::iterator It = BB;
2048 // cmpTY ccX, r1, r2
2050 // fallthrough --> copy0MBB
2051 MachineBasicBlock *thisMBB = BB;
2052 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2053 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2054 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
2055 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
2056 MachineFunction *F = BB->getParent();
2057 F->getBasicBlockList().insert(It, copy0MBB);
2058 F->getBasicBlockList().insert(It, sinkMBB);
2059 // Update machine-CFG edges by first adding all successors of the current
2060 // block to the new block which will contain the Phi node for the select.
2061 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2062 e = BB->succ_end(); i != e; ++i)
2063 sinkMBB->addSuccessor(*i);
2064 // Next, remove all successors of the current block, and add the true
2065 // and fallthrough blocks as its successors.
2066 while(!BB->succ_empty())
2067 BB->removeSuccessor(BB->succ_begin());
2068 BB->addSuccessor(copy0MBB);
2069 BB->addSuccessor(sinkMBB);
2072 // %FalseValue = ...
2073 // # fallthrough to sinkMBB
2076 // Update machine-CFG edges
2077 BB->addSuccessor(sinkMBB);
2080 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2083 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
2084 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
2085 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2087 delete MI; // The pseudo instruction is gone now.
2091 //===----------------------------------------------------------------------===//
2092 // Target Optimization Hooks
2093 //===----------------------------------------------------------------------===//
2095 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
2096 DAGCombinerInfo &DCI) const {
2097 TargetMachine &TM = getTargetMachine();
2098 SelectionDAG &DAG = DCI.DAG;
2099 switch (N->getOpcode()) {
2101 case ISD::SINT_TO_FP:
2102 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
2103 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
2104 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
2105 // We allow the src/dst to be either f32/f64, but the intermediate
2106 // type must be i64.
2107 if (N->getOperand(0).getValueType() == MVT::i64) {
2108 SDOperand Val = N->getOperand(0).getOperand(0);
2109 if (Val.getValueType() == MVT::f32) {
2110 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2111 DCI.AddToWorklist(Val.Val);
2114 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
2115 DCI.AddToWorklist(Val.Val);
2116 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
2117 DCI.AddToWorklist(Val.Val);
2118 if (N->getValueType(0) == MVT::f32) {
2119 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
2120 DCI.AddToWorklist(Val.Val);
2123 } else if (N->getOperand(0).getValueType() == MVT::i32) {
2124 // If the intermediate type is i32, we can avoid the load/store here
2131 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
2132 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
2133 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
2134 N->getOperand(1).getValueType() == MVT::i32) {
2135 SDOperand Val = N->getOperand(1).getOperand(0);
2136 if (Val.getValueType() == MVT::f32) {
2137 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2138 DCI.AddToWorklist(Val.Val);
2140 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
2141 DCI.AddToWorklist(Val.Val);
2143 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
2144 N->getOperand(2), N->getOperand(3));
2145 DCI.AddToWorklist(Val.Val);
2149 case PPCISD::VCMP: {
2150 // If a VCMPo node already exists with exactly the same operands as this
2151 // node, use its result instead of this node (VCMPo computes both a CR6 and
2152 // a normal output).
2154 if (!N->getOperand(0).hasOneUse() &&
2155 !N->getOperand(1).hasOneUse() &&
2156 !N->getOperand(2).hasOneUse()) {
2158 // Scan all of the users of the LHS, looking for VCMPo's that match.
2159 SDNode *VCMPoNode = 0;
2161 SDNode *LHSN = N->getOperand(0).Val;
2162 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
2164 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
2165 (*UI)->getOperand(1) == N->getOperand(1) &&
2166 (*UI)->getOperand(2) == N->getOperand(2) &&
2167 (*UI)->getOperand(0) == N->getOperand(0)) {
2172 // If there is no VCMPo node, or if the flag value has a single use, don't
2174 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
2177 // Look at the (necessarily single) use of the flag value. If it has a
2178 // chain, this transformation is more complex. Note that multiple things
2179 // could use the value result, which we should ignore.
2180 SDNode *FlagUser = 0;
2181 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
2182 FlagUser == 0; ++UI) {
2183 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
2185 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2186 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
2193 // If the user is a MFCR instruction, we know this is safe. Otherwise we
2194 // give up for right now.
2195 if (FlagUser->getOpcode() == PPCISD::MFCR)
2196 return SDOperand(VCMPoNode, 0);
2201 // If this is a branch on an altivec predicate comparison, lower this so
2202 // that we don't have to do a MFCR: instead, branch directly on CR6. This
2203 // lowering is done pre-legalize, because the legalizer lowers the predicate
2204 // compare down to code that is difficult to reassemble.
2205 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
2206 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
2210 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2211 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
2212 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
2213 assert(isDot && "Can't compare against a vector result!");
2215 // If this is a comparison against something other than 0/1, then we know
2216 // that the condition is never/always true.
2217 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
2218 if (Val != 0 && Val != 1) {
2219 if (CC == ISD::SETEQ) // Cond never true, remove branch.
2220 return N->getOperand(0);
2221 // Always !=, turn it into an unconditional branch.
2222 return DAG.getNode(ISD::BR, MVT::Other,
2223 N->getOperand(0), N->getOperand(4));
2226 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
2228 // Create the PPCISD altivec 'dot' comparison node.
2229 std::vector<SDOperand> Ops;
2230 std::vector<MVT::ValueType> VTs;
2231 Ops.push_back(LHS.getOperand(2)); // LHS of compare
2232 Ops.push_back(LHS.getOperand(3)); // RHS of compare
2233 Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32));
2234 VTs.push_back(LHS.getOperand(2).getValueType());
2235 VTs.push_back(MVT::Flag);
2236 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops);
2238 // Unpack the result based on how the target uses it.
2240 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
2241 default: // Can't happen, don't crash on invalid number though.
2242 case 0: // Branch on the value of the EQ bit of CR6.
2243 CompOpc = BranchOnWhenPredTrue ? PPC::BEQ : PPC::BNE;
2245 case 1: // Branch on the inverted value of the EQ bit of CR6.
2246 CompOpc = BranchOnWhenPredTrue ? PPC::BNE : PPC::BEQ;
2248 case 2: // Branch on the value of the LT bit of CR6.
2249 CompOpc = BranchOnWhenPredTrue ? PPC::BLT : PPC::BGE;
2251 case 3: // Branch on the inverted value of the LT bit of CR6.
2252 CompOpc = BranchOnWhenPredTrue ? PPC::BGE : PPC::BLT;
2256 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
2257 DAG.getRegister(PPC::CR6, MVT::i32),
2258 DAG.getConstant(CompOpc, MVT::i32),
2259 N->getOperand(4), CompNode.getValue(1));
2268 //===----------------------------------------------------------------------===//
2269 // Inline Assembly Support
2270 //===----------------------------------------------------------------------===//
2272 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
2274 uint64_t &KnownZero,
2276 unsigned Depth) const {
2279 switch (Op.getOpcode()) {
2281 case ISD::INTRINSIC_WO_CHAIN: {
2282 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
2284 case Intrinsic::ppc_altivec_vcmpbfp_p:
2285 case Intrinsic::ppc_altivec_vcmpeqfp_p:
2286 case Intrinsic::ppc_altivec_vcmpequb_p:
2287 case Intrinsic::ppc_altivec_vcmpequh_p:
2288 case Intrinsic::ppc_altivec_vcmpequw_p:
2289 case Intrinsic::ppc_altivec_vcmpgefp_p:
2290 case Intrinsic::ppc_altivec_vcmpgtfp_p:
2291 case Intrinsic::ppc_altivec_vcmpgtsb_p:
2292 case Intrinsic::ppc_altivec_vcmpgtsh_p:
2293 case Intrinsic::ppc_altivec_vcmpgtsw_p:
2294 case Intrinsic::ppc_altivec_vcmpgtub_p:
2295 case Intrinsic::ppc_altivec_vcmpgtuh_p:
2296 case Intrinsic::ppc_altivec_vcmpgtuw_p:
2297 KnownZero = ~1U; // All bits but the low one are known to be zero.
2305 /// getConstraintType - Given a constraint letter, return the type of
2306 /// constraint it is for this target.
2307 PPCTargetLowering::ConstraintType
2308 PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
2309 switch (ConstraintLetter) {
2316 return C_RegisterClass;
2318 return TargetLowering::getConstraintType(ConstraintLetter);
2322 std::vector<unsigned> PPCTargetLowering::
2323 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2324 MVT::ValueType VT) const {
2325 if (Constraint.size() == 1) {
2326 switch (Constraint[0]) { // GCC RS6000 Constraint Letters
2327 default: break; // Unknown constriant letter
2329 return make_vector<unsigned>(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 ,
2330 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
2331 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
2332 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
2333 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
2334 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
2335 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
2336 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
2339 return make_vector<unsigned>(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 ,
2340 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
2341 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
2342 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
2343 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
2344 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
2345 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
2346 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
2349 return make_vector<unsigned>(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 ,
2350 PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 ,
2351 PPC::F8 , PPC::F9 , PPC::F10, PPC::F11,
2352 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
2353 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
2354 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
2355 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
2356 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
2359 return make_vector<unsigned>(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 ,
2360 PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
2361 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11,
2362 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
2363 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
2364 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
2365 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
2366 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
2369 return make_vector<unsigned>(PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
2370 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7,
2375 return std::vector<unsigned>();
2378 // isOperandValidForConstraint
2379 bool PPCTargetLowering::
2380 isOperandValidForConstraint(SDOperand Op, char Letter) {
2391 if (!isa<ConstantSDNode>(Op)) return false; // Must be an immediate.
2392 unsigned Value = cast<ConstantSDNode>(Op)->getValue();
2394 default: assert(0 && "Unknown constraint letter!");
2395 case 'I': // "I" is a signed 16-bit constant.
2396 return (short)Value == (int)Value;
2397 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
2398 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
2399 return (short)Value == 0;
2400 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
2401 return (Value >> 16) == 0;
2402 case 'M': // "M" is a constant that is greater than 31.
2404 case 'N': // "N" is a positive constant that is an exact power of two.
2405 return (int)Value > 0 && isPowerOf2_32(Value);
2406 case 'O': // "O" is the constant zero.
2408 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
2409 return (short)-Value == (int)-Value;
2415 // Handle standard constraint letters.
2416 return TargetLowering::isOperandValidForConstraint(Op, Letter);
2419 /// isLegalAddressImmediate - Return true if the integer value can be used
2420 /// as the offset of the target addressing mode.
2421 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const {
2422 // PPC allows a sign-extended 16-bit immediate field.
2423 return (V > -(1 << 16) && V < (1 << 16)-1);