1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 // FIXME: Remove this once soft-float is supported.
43 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
44 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
46 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
47 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
49 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
50 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
52 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
53 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
55 // FIXME: Remove this once the bug has been fixed!
56 extern cl::opt<bool> ANDIGlueBug;
58 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM)
60 Subtarget(*TM.getSubtargetImpl()) {
61 // Use _setjmp/_longjmp instead of setjmp/longjmp.
62 setUseUnderscoreSetJmp(true);
63 setUseUnderscoreLongJmp(true);
65 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
66 // arguments are at least 4/8 bytes aligned.
67 bool isPPC64 = Subtarget.isPPC64();
68 setMinStackArgumentAlignment(isPPC64 ? 8:4);
70 // Set up the register classes.
71 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
72 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
73 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
75 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
76 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
77 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
79 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
81 // PowerPC has pre-inc load and store's.
82 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
83 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
84 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
85 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
87 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
88 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
89 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
90 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
93 if (Subtarget.useCRBits()) {
94 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
96 if (isPPC64 || Subtarget.hasFPCVT()) {
97 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
98 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
99 isPPC64 ? MVT::i64 : MVT::i32);
100 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
101 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
102 isPPC64 ? MVT::i64 : MVT::i32);
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
105 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
108 // PowerPC does not support direct load / store of condition registers
109 setOperationAction(ISD::LOAD, MVT::i1, Custom);
110 setOperationAction(ISD::STORE, MVT::i1, Custom);
112 // FIXME: Remove this once the ANDI glue bug is fixed:
114 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
116 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
117 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
118 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
119 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
120 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
121 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
123 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
126 // This is used in the ppcf128->int sequence. Note it has different semantics
127 // from FP_ROUND: that rounds to nearest, this rounds to zero.
128 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
130 // We do not currently implement these libm ops for PowerPC.
131 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
132 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
133 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
134 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
135 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
136 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
138 // PowerPC has no SREM/UREM instructions
139 setOperationAction(ISD::SREM, MVT::i32, Expand);
140 setOperationAction(ISD::UREM, MVT::i32, Expand);
141 setOperationAction(ISD::SREM, MVT::i64, Expand);
142 setOperationAction(ISD::UREM, MVT::i64, Expand);
144 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
145 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
146 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
147 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
148 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
149 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
150 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
151 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
152 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
154 // We don't support sin/cos/sqrt/fmod/pow
155 setOperationAction(ISD::FSIN , MVT::f64, Expand);
156 setOperationAction(ISD::FCOS , MVT::f64, Expand);
157 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
158 setOperationAction(ISD::FREM , MVT::f64, Expand);
159 setOperationAction(ISD::FPOW , MVT::f64, Expand);
160 setOperationAction(ISD::FMA , MVT::f64, Legal);
161 setOperationAction(ISD::FSIN , MVT::f32, Expand);
162 setOperationAction(ISD::FCOS , MVT::f32, Expand);
163 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
164 setOperationAction(ISD::FREM , MVT::f32, Expand);
165 setOperationAction(ISD::FPOW , MVT::f32, Expand);
166 setOperationAction(ISD::FMA , MVT::f32, Legal);
168 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
170 // If we're enabling GP optimizations, use hardware square root
171 if (!Subtarget.hasFSQRT() &&
172 !(TM.Options.UnsafeFPMath &&
173 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
174 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
176 if (!Subtarget.hasFSQRT() &&
177 !(TM.Options.UnsafeFPMath &&
178 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
179 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
181 if (Subtarget.hasFCPSGN()) {
182 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
183 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
185 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
186 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
189 if (Subtarget.hasFPRND()) {
190 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
191 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
192 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
193 setOperationAction(ISD::FROUND, MVT::f64, Legal);
195 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
196 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
197 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
198 setOperationAction(ISD::FROUND, MVT::f32, Legal);
201 // PowerPC does not have BSWAP, CTPOP or CTTZ
202 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
203 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
204 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
205 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
206 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
207 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
208 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
209 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
211 if (Subtarget.hasPOPCNTD()) {
212 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
213 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
215 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
216 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
219 // PowerPC does not have ROTR
220 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
221 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
223 if (!Subtarget.useCRBits()) {
224 // PowerPC does not have Select
225 setOperationAction(ISD::SELECT, MVT::i32, Expand);
226 setOperationAction(ISD::SELECT, MVT::i64, Expand);
227 setOperationAction(ISD::SELECT, MVT::f32, Expand);
228 setOperationAction(ISD::SELECT, MVT::f64, Expand);
231 // PowerPC wants to turn select_cc of FP into fsel when possible.
232 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
233 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
235 // PowerPC wants to optimize integer setcc a bit
236 if (!Subtarget.useCRBits())
237 setOperationAction(ISD::SETCC, MVT::i32, Custom);
239 // PowerPC does not have BRCOND which requires SetCC
240 if (!Subtarget.useCRBits())
241 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
243 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
245 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
246 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
248 // PowerPC does not have [U|S]INT_TO_FP
249 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
250 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
252 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
253 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
254 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
255 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
257 // We cannot sextinreg(i1). Expand to shifts.
258 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
260 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
261 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
262 // support continuation, user-level threading, and etc.. As a result, no
263 // other SjLj exception interfaces are implemented and please don't build
264 // your own exception handling based on them.
265 // LLVM/Clang supports zero-cost DWARF exception handling.
266 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
267 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
269 // We want to legalize GlobalAddress and ConstantPool nodes into the
270 // appropriate instructions to materialize the address.
271 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
272 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
273 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
274 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
275 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
276 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
277 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
278 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
279 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
280 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
283 setOperationAction(ISD::TRAP, MVT::Other, Legal);
285 // TRAMPOLINE is custom lowered.
286 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
287 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
289 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
290 setOperationAction(ISD::VASTART , MVT::Other, Custom);
292 if (Subtarget.isSVR4ABI()) {
294 // VAARG always uses double-word chunks, so promote anything smaller.
295 setOperationAction(ISD::VAARG, MVT::i1, Promote);
296 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
297 setOperationAction(ISD::VAARG, MVT::i8, Promote);
298 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
299 setOperationAction(ISD::VAARG, MVT::i16, Promote);
300 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
301 setOperationAction(ISD::VAARG, MVT::i32, Promote);
302 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
303 setOperationAction(ISD::VAARG, MVT::Other, Expand);
305 // VAARG is custom lowered with the 32-bit SVR4 ABI.
306 setOperationAction(ISD::VAARG, MVT::Other, Custom);
307 setOperationAction(ISD::VAARG, MVT::i64, Custom);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 if (Subtarget.isSVR4ABI() && !isPPC64)
313 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
314 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
316 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
318 // Use the default implementation.
319 setOperationAction(ISD::VAEND , MVT::Other, Expand);
320 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
321 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
322 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
323 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
325 // We want to custom lower some of our intrinsics.
326 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
328 // To handle counter-based loop conditions.
329 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
331 // Comparisons that require checking two conditions.
332 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
333 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
334 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
335 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
336 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
337 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
338 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
339 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
340 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
341 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
342 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
343 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
345 if (Subtarget.has64BitSupport()) {
346 // They also have instructions for converting between i64 and fp.
347 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
348 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
349 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
350 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
351 // This is just the low 32 bits of a (signed) fp->i64 conversion.
352 // We cannot do this with Promote because i64 is not a legal type.
353 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
355 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
356 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
358 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
359 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
362 // With the instructions enabled under FPCVT, we can do everything.
363 if (Subtarget.hasFPCVT()) {
364 if (Subtarget.has64BitSupport()) {
365 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
366 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
367 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
368 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
371 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
372 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
373 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
374 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
377 if (Subtarget.use64BitRegs()) {
378 // 64-bit PowerPC implementations can support i64 types directly
379 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
380 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
381 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
382 // 64-bit PowerPC wants to expand i128 shifts itself.
383 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
384 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
385 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
387 // 32-bit PowerPC wants to expand i64 shifts itself.
388 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
389 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
390 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
393 if (Subtarget.hasAltivec()) {
394 // First set operation action for all vector types to expand. Then we
395 // will selectively turn on ones that can be effectively codegen'd.
396 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
397 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
398 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
400 // add/sub are legal for all supported vector VT's.
401 setOperationAction(ISD::ADD , VT, Legal);
402 setOperationAction(ISD::SUB , VT, Legal);
404 // We promote all shuffles to v16i8.
405 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
406 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
408 // We promote all non-typed operations to v4i32.
409 setOperationAction(ISD::AND , VT, Promote);
410 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
411 setOperationAction(ISD::OR , VT, Promote);
412 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
413 setOperationAction(ISD::XOR , VT, Promote);
414 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
415 setOperationAction(ISD::LOAD , VT, Promote);
416 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
417 setOperationAction(ISD::SELECT, VT, Promote);
418 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
419 setOperationAction(ISD::STORE, VT, Promote);
420 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
422 // No other operations are legal.
423 setOperationAction(ISD::MUL , VT, Expand);
424 setOperationAction(ISD::SDIV, VT, Expand);
425 setOperationAction(ISD::SREM, VT, Expand);
426 setOperationAction(ISD::UDIV, VT, Expand);
427 setOperationAction(ISD::UREM, VT, Expand);
428 setOperationAction(ISD::FDIV, VT, Expand);
429 setOperationAction(ISD::FREM, VT, Expand);
430 setOperationAction(ISD::FNEG, VT, Expand);
431 setOperationAction(ISD::FSQRT, VT, Expand);
432 setOperationAction(ISD::FLOG, VT, Expand);
433 setOperationAction(ISD::FLOG10, VT, Expand);
434 setOperationAction(ISD::FLOG2, VT, Expand);
435 setOperationAction(ISD::FEXP, VT, Expand);
436 setOperationAction(ISD::FEXP2, VT, Expand);
437 setOperationAction(ISD::FSIN, VT, Expand);
438 setOperationAction(ISD::FCOS, VT, Expand);
439 setOperationAction(ISD::FABS, VT, Expand);
440 setOperationAction(ISD::FPOWI, VT, Expand);
441 setOperationAction(ISD::FFLOOR, VT, Expand);
442 setOperationAction(ISD::FCEIL, VT, Expand);
443 setOperationAction(ISD::FTRUNC, VT, Expand);
444 setOperationAction(ISD::FRINT, VT, Expand);
445 setOperationAction(ISD::FNEARBYINT, VT, Expand);
446 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
447 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
448 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
449 setOperationAction(ISD::MULHU, VT, Expand);
450 setOperationAction(ISD::MULHS, VT, Expand);
451 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
452 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
453 setOperationAction(ISD::UDIVREM, VT, Expand);
454 setOperationAction(ISD::SDIVREM, VT, Expand);
455 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
456 setOperationAction(ISD::FPOW, VT, Expand);
457 setOperationAction(ISD::BSWAP, VT, Expand);
458 setOperationAction(ISD::CTPOP, VT, Expand);
459 setOperationAction(ISD::CTLZ, VT, Expand);
460 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
461 setOperationAction(ISD::CTTZ, VT, Expand);
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
463 setOperationAction(ISD::VSELECT, VT, Expand);
464 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
466 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
467 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
468 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
469 setTruncStoreAction(VT, InnerVT, Expand);
471 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
472 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
473 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
476 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
477 // with merges, splats, etc.
478 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
480 setOperationAction(ISD::AND , MVT::v4i32, Legal);
481 setOperationAction(ISD::OR , MVT::v4i32, Legal);
482 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
483 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
484 setOperationAction(ISD::SELECT, MVT::v4i32,
485 Subtarget.useCRBits() ? Legal : Expand);
486 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
487 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
488 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
489 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
490 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
491 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
492 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
493 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
494 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
496 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
497 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
498 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
499 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
501 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
502 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
504 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
505 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
506 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
509 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
510 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
511 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
513 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
514 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
516 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
517 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
518 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
519 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
521 // Altivec does not contain unordered floating-point compare instructions
522 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
523 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
524 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
525 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
527 if (Subtarget.hasVSX()) {
528 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
529 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
531 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
532 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
533 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
534 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
535 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
537 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
539 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
540 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
542 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
543 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
545 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
546 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
547 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
548 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
549 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
551 // Share the Altivec comparison restrictions.
552 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
553 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
554 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
555 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
557 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
558 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
560 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
562 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
564 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
565 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
567 // VSX v2i64 only supports non-arithmetic operations.
568 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
569 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
571 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
572 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
573 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
575 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
577 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
578 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
579 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
580 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
582 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
584 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
585 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
586 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
587 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
589 // Vector operation legalization checks the result type of
590 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
591 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
592 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
593 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
594 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
596 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
600 if (Subtarget.has64BitSupport())
601 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
603 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
606 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
607 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
610 setBooleanContents(ZeroOrOneBooleanContent);
611 // Altivec instructions set fields to all zeros or all ones.
612 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
615 // These libcalls are not available in 32-bit.
616 setLibcallName(RTLIB::SHL_I128, nullptr);
617 setLibcallName(RTLIB::SRL_I128, nullptr);
618 setLibcallName(RTLIB::SRA_I128, nullptr);
622 setStackPointerRegisterToSaveRestore(PPC::X1);
623 setExceptionPointerRegister(PPC::X3);
624 setExceptionSelectorRegister(PPC::X4);
626 setStackPointerRegisterToSaveRestore(PPC::R1);
627 setExceptionPointerRegister(PPC::R3);
628 setExceptionSelectorRegister(PPC::R4);
631 // We have target-specific dag combine patterns for the following nodes:
632 setTargetDAGCombine(ISD::SINT_TO_FP);
633 setTargetDAGCombine(ISD::LOAD);
634 setTargetDAGCombine(ISD::STORE);
635 setTargetDAGCombine(ISD::BR_CC);
636 if (Subtarget.useCRBits())
637 setTargetDAGCombine(ISD::BRCOND);
638 setTargetDAGCombine(ISD::BSWAP);
639 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
640 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
641 setTargetDAGCombine(ISD::INTRINSIC_VOID);
643 setTargetDAGCombine(ISD::SIGN_EXTEND);
644 setTargetDAGCombine(ISD::ZERO_EXTEND);
645 setTargetDAGCombine(ISD::ANY_EXTEND);
647 if (Subtarget.useCRBits()) {
648 setTargetDAGCombine(ISD::TRUNCATE);
649 setTargetDAGCombine(ISD::SETCC);
650 setTargetDAGCombine(ISD::SELECT_CC);
653 // Use reciprocal estimates.
654 if (TM.Options.UnsafeFPMath) {
655 setTargetDAGCombine(ISD::FDIV);
656 setTargetDAGCombine(ISD::FSQRT);
659 // Darwin long double math library functions have $LDBL128 appended.
660 if (Subtarget.isDarwin()) {
661 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
662 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
663 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
664 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
665 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
666 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
667 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
668 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
669 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
670 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
673 // With 32 condition bits, we don't need to sink (and duplicate) compares
674 // aggressively in CodeGenPrep.
675 if (Subtarget.useCRBits())
676 setHasMultipleConditionRegisters();
678 setMinFunctionAlignment(2);
679 if (Subtarget.isDarwin())
680 setPrefFunctionAlignment(4);
682 setInsertFencesForAtomic(true);
684 if (Subtarget.enableMachineScheduler())
685 setSchedulingPreference(Sched::Source);
687 setSchedulingPreference(Sched::Hybrid);
689 computeRegisterProperties();
691 // The Freescale cores does better with aggressive inlining of memcpy and
692 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
693 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
694 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
695 MaxStoresPerMemset = 32;
696 MaxStoresPerMemsetOptSize = 16;
697 MaxStoresPerMemcpy = 32;
698 MaxStoresPerMemcpyOptSize = 8;
699 MaxStoresPerMemmove = 32;
700 MaxStoresPerMemmoveOptSize = 8;
702 setPrefFunctionAlignment(4);
706 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
707 /// the desired ByVal argument alignment.
708 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
709 unsigned MaxMaxAlign) {
710 if (MaxAlign == MaxMaxAlign)
712 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
713 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
715 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
717 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
718 unsigned EltAlign = 0;
719 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
720 if (EltAlign > MaxAlign)
722 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
723 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
724 unsigned EltAlign = 0;
725 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
726 if (EltAlign > MaxAlign)
728 if (MaxAlign == MaxMaxAlign)
734 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
735 /// function arguments in the caller parameter area.
736 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
737 // Darwin passes everything on 4 byte boundary.
738 if (Subtarget.isDarwin())
741 // 16byte and wider vectors are passed on 16byte boundary.
742 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
743 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
744 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
745 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
749 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
751 default: return nullptr;
752 case PPCISD::FSEL: return "PPCISD::FSEL";
753 case PPCISD::FCFID: return "PPCISD::FCFID";
754 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
755 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
756 case PPCISD::FRE: return "PPCISD::FRE";
757 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
758 case PPCISD::STFIWX: return "PPCISD::STFIWX";
759 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
760 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
761 case PPCISD::VPERM: return "PPCISD::VPERM";
762 case PPCISD::CMPB: return "PPCISD::CMPB";
763 case PPCISD::Hi: return "PPCISD::Hi";
764 case PPCISD::Lo: return "PPCISD::Lo";
765 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
766 case PPCISD::LOAD: return "PPCISD::LOAD";
767 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
768 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
769 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
770 case PPCISD::SRL: return "PPCISD::SRL";
771 case PPCISD::SRA: return "PPCISD::SRA";
772 case PPCISD::SHL: return "PPCISD::SHL";
773 case PPCISD::CALL: return "PPCISD::CALL";
774 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
775 case PPCISD::CALL_TLS: return "PPCISD::CALL_TLS";
776 case PPCISD::CALL_NOP_TLS: return "PPCISD::CALL_NOP_TLS";
777 case PPCISD::MTCTR: return "PPCISD::MTCTR";
778 case PPCISD::BCTRL: return "PPCISD::BCTRL";
779 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
780 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
781 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
782 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
783 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
784 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
785 case PPCISD::VCMP: return "PPCISD::VCMP";
786 case PPCISD::VCMPo: return "PPCISD::VCMPo";
787 case PPCISD::LBRX: return "PPCISD::LBRX";
788 case PPCISD::STBRX: return "PPCISD::STBRX";
789 case PPCISD::LARX: return "PPCISD::LARX";
790 case PPCISD::STCX: return "PPCISD::STCX";
791 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
792 case PPCISD::BDNZ: return "PPCISD::BDNZ";
793 case PPCISD::BDZ: return "PPCISD::BDZ";
794 case PPCISD::MFFS: return "PPCISD::MFFS";
795 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
796 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
797 case PPCISD::CR6SET: return "PPCISD::CR6SET";
798 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
799 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
800 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
801 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
802 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
803 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
804 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
805 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
806 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
807 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
808 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
809 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
810 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
811 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
812 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
813 case PPCISD::SC: return "PPCISD::SC";
817 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
819 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
820 return VT.changeVectorElementTypeToInteger();
823 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
824 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
828 //===----------------------------------------------------------------------===//
829 // Node matching predicates, for use by the tblgen matching code.
830 //===----------------------------------------------------------------------===//
832 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
833 static bool isFloatingPointZero(SDValue Op) {
834 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
835 return CFP->getValueAPF().isZero();
836 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
837 // Maybe this has already been legalized into the constant pool?
838 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
839 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
840 return CFP->getValueAPF().isZero();
845 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
846 /// true if Op is undef or if it matches the specified value.
847 static bool isConstantOrUndef(int Op, int Val) {
848 return Op < 0 || Op == Val;
851 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
852 /// VPKUHUM instruction.
853 /// The ShuffleKind distinguishes between big-endian operations with
854 /// two different inputs (0), either-endian operations with two identical
855 /// inputs (1), and little-endian operantion with two different inputs (2).
856 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
857 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
859 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
860 if (ShuffleKind == 0) {
863 for (unsigned i = 0; i != 16; ++i)
864 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
866 } else if (ShuffleKind == 2) {
869 for (unsigned i = 0; i != 16; ++i)
870 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
872 } else if (ShuffleKind == 1) {
873 unsigned j = IsLE ? 0 : 1;
874 for (unsigned i = 0; i != 8; ++i)
875 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
876 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
882 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
883 /// VPKUWUM instruction.
884 /// The ShuffleKind distinguishes between big-endian operations with
885 /// two different inputs (0), either-endian operations with two identical
886 /// inputs (1), and little-endian operantion with two different inputs (2).
887 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
888 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
890 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
891 if (ShuffleKind == 0) {
894 for (unsigned i = 0; i != 16; i += 2)
895 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
896 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
898 } else if (ShuffleKind == 2) {
901 for (unsigned i = 0; i != 16; i += 2)
902 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
903 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
905 } else if (ShuffleKind == 1) {
906 unsigned j = IsLE ? 0 : 2;
907 for (unsigned i = 0; i != 8; i += 2)
908 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
909 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
910 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
911 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
917 /// isVMerge - Common function, used to match vmrg* shuffles.
919 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
920 unsigned LHSStart, unsigned RHSStart) {
921 if (N->getValueType(0) != MVT::v16i8)
923 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
924 "Unsupported merge size!");
926 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
927 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
928 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
929 LHSStart+j+i*UnitSize) ||
930 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
931 RHSStart+j+i*UnitSize))
937 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
938 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
939 /// The ShuffleKind distinguishes between big-endian merges with two
940 /// different inputs (0), either-endian merges with two identical inputs (1),
941 /// and little-endian merges with two different inputs (2). For the latter,
942 /// the input operands are swapped (see PPCInstrAltivec.td).
943 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
944 unsigned ShuffleKind, SelectionDAG &DAG) {
945 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
946 if (ShuffleKind == 1) // unary
947 return isVMerge(N, UnitSize, 0, 0);
948 else if (ShuffleKind == 2) // swapped
949 return isVMerge(N, UnitSize, 0, 16);
953 if (ShuffleKind == 1) // unary
954 return isVMerge(N, UnitSize, 8, 8);
955 else if (ShuffleKind == 0) // normal
956 return isVMerge(N, UnitSize, 8, 24);
962 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
963 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
964 /// The ShuffleKind distinguishes between big-endian merges with two
965 /// different inputs (0), either-endian merges with two identical inputs (1),
966 /// and little-endian merges with two different inputs (2). For the latter,
967 /// the input operands are swapped (see PPCInstrAltivec.td).
968 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
969 unsigned ShuffleKind, SelectionDAG &DAG) {
970 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
971 if (ShuffleKind == 1) // unary
972 return isVMerge(N, UnitSize, 8, 8);
973 else if (ShuffleKind == 2) // swapped
974 return isVMerge(N, UnitSize, 8, 24);
978 if (ShuffleKind == 1) // unary
979 return isVMerge(N, UnitSize, 0, 0);
980 else if (ShuffleKind == 0) // normal
981 return isVMerge(N, UnitSize, 0, 16);
988 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
989 /// amount, otherwise return -1.
990 /// The ShuffleKind distinguishes between big-endian operations with two
991 /// different inputs (0), either-endian operations with two identical inputs
992 /// (1), and little-endian operations with two different inputs (2). For the
993 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
994 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
996 if (N->getValueType(0) != MVT::v16i8)
999 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1001 // Find the first non-undef value in the shuffle mask.
1003 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1006 if (i == 16) return -1; // all undef.
1008 // Otherwise, check to see if the rest of the elements are consecutively
1009 // numbered from this value.
1010 unsigned ShiftAmt = SVOp->getMaskElt(i);
1011 if (ShiftAmt < i) return -1;
1014 bool isLE = DAG.getTarget().getSubtargetImpl()->getDataLayout()->
1017 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1018 // Check the rest of the elements to see if they are consecutive.
1019 for (++i; i != 16; ++i)
1020 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1022 } else if (ShuffleKind == 1) {
1023 // Check the rest of the elements to see if they are consecutive.
1024 for (++i; i != 16; ++i)
1025 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1030 if (ShuffleKind == 2 && isLE)
1031 ShiftAmt = 16 - ShiftAmt;
1036 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1037 /// specifies a splat of a single element that is suitable for input to
1038 /// VSPLTB/VSPLTH/VSPLTW.
1039 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1040 assert(N->getValueType(0) == MVT::v16i8 &&
1041 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1043 // This is a splat operation if each element of the permute is the same, and
1044 // if the value doesn't reference the second vector.
1045 unsigned ElementBase = N->getMaskElt(0);
1047 // FIXME: Handle UNDEF elements too!
1048 if (ElementBase >= 16)
1051 // Check that the indices are consecutive, in the case of a multi-byte element
1052 // splatted with a v16i8 mask.
1053 for (unsigned i = 1; i != EltSize; ++i)
1054 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1057 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1058 if (N->getMaskElt(i) < 0) continue;
1059 for (unsigned j = 0; j != EltSize; ++j)
1060 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1066 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1068 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1069 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1071 APInt APVal, APUndef;
1075 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1076 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1077 return CFP->getValueAPF().isNegZero();
1082 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1083 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1084 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1085 SelectionDAG &DAG) {
1086 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1087 assert(isSplatShuffleMask(SVOp, EltSize));
1088 if (DAG.getSubtarget().getDataLayout()->isLittleEndian())
1089 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1091 return SVOp->getMaskElt(0) / EltSize;
1094 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1095 /// by using a vspltis[bhw] instruction of the specified element size, return
1096 /// the constant being splatted. The ByteSize field indicates the number of
1097 /// bytes of each element [124] -> [bhw].
1098 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1099 SDValue OpVal(nullptr, 0);
1101 // If ByteSize of the splat is bigger than the element size of the
1102 // build_vector, then we have a case where we are checking for a splat where
1103 // multiple elements of the buildvector are folded together into a single
1104 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1105 unsigned EltSize = 16/N->getNumOperands();
1106 if (EltSize < ByteSize) {
1107 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1108 SDValue UniquedVals[4];
1109 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1111 // See if all of the elements in the buildvector agree across.
1112 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1113 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1114 // If the element isn't a constant, bail fully out.
1115 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1118 if (!UniquedVals[i&(Multiple-1)].getNode())
1119 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1120 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1121 return SDValue(); // no match.
1124 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1125 // either constant or undef values that are identical for each chunk. See
1126 // if these chunks can form into a larger vspltis*.
1128 // Check to see if all of the leading entries are either 0 or -1. If
1129 // neither, then this won't fit into the immediate field.
1130 bool LeadingZero = true;
1131 bool LeadingOnes = true;
1132 for (unsigned i = 0; i != Multiple-1; ++i) {
1133 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1135 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1136 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1138 // Finally, check the least significant entry.
1140 if (!UniquedVals[Multiple-1].getNode())
1141 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1142 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1144 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1147 if (!UniquedVals[Multiple-1].getNode())
1148 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1149 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1150 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1151 return DAG.getTargetConstant(Val, MVT::i32);
1157 // Check to see if this buildvec has a single non-undef value in its elements.
1158 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1159 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1160 if (!OpVal.getNode())
1161 OpVal = N->getOperand(i);
1162 else if (OpVal != N->getOperand(i))
1166 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1168 unsigned ValSizeInBytes = EltSize;
1170 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1171 Value = CN->getZExtValue();
1172 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1173 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1174 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1177 // If the splat value is larger than the element value, then we can never do
1178 // this splat. The only case that we could fit the replicated bits into our
1179 // immediate field for would be zero, and we prefer to use vxor for it.
1180 if (ValSizeInBytes < ByteSize) return SDValue();
1182 // If the element value is larger than the splat value, cut it in half and
1183 // check to see if the two halves are equal. Continue doing this until we
1184 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1185 while (ValSizeInBytes > ByteSize) {
1186 ValSizeInBytes >>= 1;
1188 // If the top half equals the bottom half, we're still ok.
1189 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1190 (Value & ((1 << (8*ValSizeInBytes))-1)))
1194 // Properly sign extend the value.
1195 int MaskVal = SignExtend32(Value, ByteSize * 8);
1197 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1198 if (MaskVal == 0) return SDValue();
1200 // Finally, if this value fits in a 5 bit sext field, return it
1201 if (SignExtend32<5>(MaskVal) == MaskVal)
1202 return DAG.getTargetConstant(MaskVal, MVT::i32);
1206 //===----------------------------------------------------------------------===//
1207 // Addressing Mode Selection
1208 //===----------------------------------------------------------------------===//
1210 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1211 /// or 64-bit immediate, and if the value can be accurately represented as a
1212 /// sign extension from a 16-bit value. If so, this returns true and the
1214 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1215 if (!isa<ConstantSDNode>(N))
1218 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1219 if (N->getValueType(0) == MVT::i32)
1220 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1222 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1224 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1225 return isIntS16Immediate(Op.getNode(), Imm);
1229 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1230 /// can be represented as an indexed [r+r] operation. Returns false if it
1231 /// can be more efficiently represented with [r+imm].
1232 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1234 SelectionDAG &DAG) const {
1236 if (N.getOpcode() == ISD::ADD) {
1237 if (isIntS16Immediate(N.getOperand(1), imm))
1238 return false; // r+i
1239 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1240 return false; // r+i
1242 Base = N.getOperand(0);
1243 Index = N.getOperand(1);
1245 } else if (N.getOpcode() == ISD::OR) {
1246 if (isIntS16Immediate(N.getOperand(1), imm))
1247 return false; // r+i can fold it if we can.
1249 // If this is an or of disjoint bitfields, we can codegen this as an add
1250 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1252 APInt LHSKnownZero, LHSKnownOne;
1253 APInt RHSKnownZero, RHSKnownOne;
1254 DAG.computeKnownBits(N.getOperand(0),
1255 LHSKnownZero, LHSKnownOne);
1257 if (LHSKnownZero.getBoolValue()) {
1258 DAG.computeKnownBits(N.getOperand(1),
1259 RHSKnownZero, RHSKnownOne);
1260 // If all of the bits are known zero on the LHS or RHS, the add won't
1262 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1263 Base = N.getOperand(0);
1264 Index = N.getOperand(1);
1273 // If we happen to be doing an i64 load or store into a stack slot that has
1274 // less than a 4-byte alignment, then the frame-index elimination may need to
1275 // use an indexed load or store instruction (because the offset may not be a
1276 // multiple of 4). The extra register needed to hold the offset comes from the
1277 // register scavenger, and it is possible that the scavenger will need to use
1278 // an emergency spill slot. As a result, we need to make sure that a spill slot
1279 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1281 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1282 // FIXME: This does not handle the LWA case.
1286 // NOTE: We'll exclude negative FIs here, which come from argument
1287 // lowering, because there are no known test cases triggering this problem
1288 // using packed structures (or similar). We can remove this exclusion if
1289 // we find such a test case. The reason why this is so test-case driven is
1290 // because this entire 'fixup' is only to prevent crashes (from the
1291 // register scavenger) on not-really-valid inputs. For example, if we have:
1293 // %b = bitcast i1* %a to i64*
1294 // store i64* a, i64 b
1295 // then the store should really be marked as 'align 1', but is not. If it
1296 // were marked as 'align 1' then the indexed form would have been
1297 // instruction-selected initially, and the problem this 'fixup' is preventing
1298 // won't happen regardless.
1302 MachineFunction &MF = DAG.getMachineFunction();
1303 MachineFrameInfo *MFI = MF.getFrameInfo();
1305 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1309 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1310 FuncInfo->setHasNonRISpills();
1313 /// Returns true if the address N can be represented by a base register plus
1314 /// a signed 16-bit displacement [r+imm], and if it is not better
1315 /// represented as reg+reg. If Aligned is true, only accept displacements
1316 /// suitable for STD and friends, i.e. multiples of 4.
1317 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1320 bool Aligned) const {
1321 // FIXME dl should come from parent load or store, not from address
1323 // If this can be more profitably realized as r+r, fail.
1324 if (SelectAddressRegReg(N, Disp, Base, DAG))
1327 if (N.getOpcode() == ISD::ADD) {
1329 if (isIntS16Immediate(N.getOperand(1), imm) &&
1330 (!Aligned || (imm & 3) == 0)) {
1331 Disp = DAG.getTargetConstant(imm, N.getValueType());
1332 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1333 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1334 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1336 Base = N.getOperand(0);
1338 return true; // [r+i]
1339 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1340 // Match LOAD (ADD (X, Lo(G))).
1341 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1342 && "Cannot handle constant offsets yet!");
1343 Disp = N.getOperand(1).getOperand(0); // The global address.
1344 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1345 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1346 Disp.getOpcode() == ISD::TargetConstantPool ||
1347 Disp.getOpcode() == ISD::TargetJumpTable);
1348 Base = N.getOperand(0);
1349 return true; // [&g+r]
1351 } else if (N.getOpcode() == ISD::OR) {
1353 if (isIntS16Immediate(N.getOperand(1), imm) &&
1354 (!Aligned || (imm & 3) == 0)) {
1355 // If this is an or of disjoint bitfields, we can codegen this as an add
1356 // (for better address arithmetic) if the LHS and RHS of the OR are
1357 // provably disjoint.
1358 APInt LHSKnownZero, LHSKnownOne;
1359 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1361 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1362 // If all of the bits are known zero on the LHS or RHS, the add won't
1364 if (FrameIndexSDNode *FI =
1365 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1366 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1367 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1369 Base = N.getOperand(0);
1371 Disp = DAG.getTargetConstant(imm, N.getValueType());
1375 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1376 // Loading from a constant address.
1378 // If this address fits entirely in a 16-bit sext immediate field, codegen
1381 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1382 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1383 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1384 CN->getValueType(0));
1388 // Handle 32-bit sext immediates with LIS + addr mode.
1389 if ((CN->getValueType(0) == MVT::i32 ||
1390 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1391 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1392 int Addr = (int)CN->getZExtValue();
1394 // Otherwise, break this down into an LIS + disp.
1395 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1397 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1398 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1399 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1404 Disp = DAG.getTargetConstant(0, getPointerTy());
1405 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1406 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1407 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1410 return true; // [r+0]
1413 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1414 /// represented as an indexed [r+r] operation.
1415 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1417 SelectionDAG &DAG) const {
1418 // Check to see if we can easily represent this as an [r+r] address. This
1419 // will fail if it thinks that the address is more profitably represented as
1420 // reg+imm, e.g. where imm = 0.
1421 if (SelectAddressRegReg(N, Base, Index, DAG))
1424 // If the operand is an addition, always emit this as [r+r], since this is
1425 // better (for code size, and execution, as the memop does the add for free)
1426 // than emitting an explicit add.
1427 if (N.getOpcode() == ISD::ADD) {
1428 Base = N.getOperand(0);
1429 Index = N.getOperand(1);
1433 // Otherwise, do it the hard way, using R0 as the base register.
1434 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1440 /// getPreIndexedAddressParts - returns true by value, base pointer and
1441 /// offset pointer and addressing mode by reference if the node's address
1442 /// can be legally represented as pre-indexed load / store address.
1443 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1445 ISD::MemIndexedMode &AM,
1446 SelectionDAG &DAG) const {
1447 if (DisablePPCPreinc) return false;
1453 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1454 Ptr = LD->getBasePtr();
1455 VT = LD->getMemoryVT();
1456 Alignment = LD->getAlignment();
1457 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1458 Ptr = ST->getBasePtr();
1459 VT = ST->getMemoryVT();
1460 Alignment = ST->getAlignment();
1465 // PowerPC doesn't have preinc load/store instructions for vectors.
1469 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1471 // Common code will reject creating a pre-inc form if the base pointer
1472 // is a frame index, or if N is a store and the base pointer is either
1473 // the same as or a predecessor of the value being stored. Check for
1474 // those situations here, and try with swapped Base/Offset instead.
1477 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1480 SDValue Val = cast<StoreSDNode>(N)->getValue();
1481 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1486 std::swap(Base, Offset);
1492 // LDU/STU can only handle immediates that are a multiple of 4.
1493 if (VT != MVT::i64) {
1494 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1497 // LDU/STU need an address with at least 4-byte alignment.
1501 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1505 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1506 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1507 // sext i32 to i64 when addr mode is r+i.
1508 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1509 LD->getExtensionType() == ISD::SEXTLOAD &&
1510 isa<ConstantSDNode>(Offset))
1518 //===----------------------------------------------------------------------===//
1519 // LowerOperation implementation
1520 //===----------------------------------------------------------------------===//
1522 /// GetLabelAccessInfo - Return true if we should reference labels using a
1523 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1524 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1525 unsigned &LoOpFlags,
1526 const GlobalValue *GV = nullptr) {
1527 HiOpFlags = PPCII::MO_HA;
1528 LoOpFlags = PPCII::MO_LO;
1530 // Don't use the pic base if not in PIC relocation model.
1531 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1534 HiOpFlags |= PPCII::MO_PIC_FLAG;
1535 LoOpFlags |= PPCII::MO_PIC_FLAG;
1538 // If this is a reference to a global value that requires a non-lazy-ptr, make
1539 // sure that instruction lowering adds it.
1540 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1541 HiOpFlags |= PPCII::MO_NLP_FLAG;
1542 LoOpFlags |= PPCII::MO_NLP_FLAG;
1544 if (GV->hasHiddenVisibility()) {
1545 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1546 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1553 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1554 SelectionDAG &DAG) {
1555 EVT PtrVT = HiPart.getValueType();
1556 SDValue Zero = DAG.getConstant(0, PtrVT);
1559 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1560 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1562 // With PIC, the first instruction is actually "GR+hi(&G)".
1564 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1565 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1567 // Generate non-pic code that has direct accesses to the constant pool.
1568 // The address of the global is just (hi(&g)+lo(&g)).
1569 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1572 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1573 SelectionDAG &DAG) const {
1574 EVT PtrVT = Op.getValueType();
1575 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1576 const Constant *C = CP->getConstVal();
1578 // 64-bit SVR4 ABI code is always position-independent.
1579 // The actual address of the GlobalValue is stored in the TOC.
1580 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1581 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1582 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1583 DAG.getRegister(PPC::X2, MVT::i64));
1586 unsigned MOHiFlag, MOLoFlag;
1587 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1589 if (isPIC && Subtarget.isSVR4ABI()) {
1590 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1591 PPCII::MO_PIC_FLAG);
1593 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1594 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1598 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1600 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1601 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1604 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1605 EVT PtrVT = Op.getValueType();
1606 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1608 // 64-bit SVR4 ABI code is always position-independent.
1609 // The actual address of the GlobalValue is stored in the TOC.
1610 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1611 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1612 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1613 DAG.getRegister(PPC::X2, MVT::i64));
1616 unsigned MOHiFlag, MOLoFlag;
1617 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1619 if (isPIC && Subtarget.isSVR4ABI()) {
1620 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1621 PPCII::MO_PIC_FLAG);
1623 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1624 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1627 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1628 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1629 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1632 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1633 SelectionDAG &DAG) const {
1634 EVT PtrVT = Op.getValueType();
1635 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
1636 const BlockAddress *BA = BASDN->getBlockAddress();
1638 // 64-bit SVR4 ABI code is always position-independent.
1639 // The actual BlockAddress is stored in the TOC.
1640 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1641 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
1642 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(BASDN), MVT::i64, GA,
1643 DAG.getRegister(PPC::X2, MVT::i64));
1646 unsigned MOHiFlag, MOLoFlag;
1647 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1648 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1649 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1650 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1653 // Generate a call to __tls_get_addr for the given GOT entry Op.
1654 std::pair<SDValue,SDValue>
1655 PPCTargetLowering::lowerTLSCall(SDValue Op, SDLoc dl,
1656 SelectionDAG &DAG) const {
1658 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
1659 TargetLowering::ArgListTy Args;
1660 TargetLowering::ArgListEntry Entry;
1662 Entry.Ty = IntPtrTy;
1663 Args.push_back(Entry);
1665 TargetLowering::CallLoweringInfo CLI(DAG);
1666 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1667 .setCallee(CallingConv::C, IntPtrTy,
1668 DAG.getTargetExternalSymbol("__tls_get_addr", getPointerTy()),
1669 std::move(Args), 0);
1671 return LowerCallTo(CLI);
1674 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1675 SelectionDAG &DAG) const {
1677 // FIXME: TLS addresses currently use medium model code sequences,
1678 // which is the most useful form. Eventually support for small and
1679 // large models could be added if users need it, at the cost of
1680 // additional complexity.
1681 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1683 const GlobalValue *GV = GA->getGlobal();
1684 EVT PtrVT = getPointerTy();
1685 bool is64bit = Subtarget.isPPC64();
1686 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
1687 PICLevel::Level picLevel = M->getPICLevel();
1689 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1691 if (Model == TLSModel::LocalExec) {
1692 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1693 PPCII::MO_TPREL_HA);
1694 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1695 PPCII::MO_TPREL_LO);
1696 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1697 is64bit ? MVT::i64 : MVT::i32);
1698 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1699 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1702 if (Model == TLSModel::InitialExec) {
1703 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1704 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1708 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1709 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1710 PtrVT, GOTReg, TGA);
1712 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1713 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1714 PtrVT, TGA, GOTPtr);
1715 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1718 if (Model == TLSModel::GeneralDynamic) {
1719 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1723 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1724 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1727 if (picLevel == PICLevel::Small)
1728 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1730 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1732 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1734 std::pair<SDValue, SDValue> CallResult = lowerTLSCall(GOTEntry, dl, DAG);
1735 return CallResult.first;
1738 if (Model == TLSModel::LocalDynamic) {
1739 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1743 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1744 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1747 if (picLevel == PICLevel::Small)
1748 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1750 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1752 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1754 std::pair<SDValue, SDValue> CallResult = lowerTLSCall(GOTEntry, dl, DAG);
1755 SDValue TLSAddr = CallResult.first;
1756 SDValue Chain = CallResult.second;
1757 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1758 Chain, TLSAddr, TGA);
1759 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1762 llvm_unreachable("Unknown TLS model!");
1765 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1766 SelectionDAG &DAG) const {
1767 EVT PtrVT = Op.getValueType();
1768 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1770 const GlobalValue *GV = GSDN->getGlobal();
1772 // 64-bit SVR4 ABI code is always position-independent.
1773 // The actual address of the GlobalValue is stored in the TOC.
1774 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1775 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1776 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1777 DAG.getRegister(PPC::X2, MVT::i64));
1780 unsigned MOHiFlag, MOLoFlag;
1781 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1783 if (isPIC && Subtarget.isSVR4ABI()) {
1784 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1786 PPCII::MO_PIC_FLAG);
1787 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1788 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1792 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1794 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1796 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1798 // If the global reference is actually to a non-lazy-pointer, we have to do an
1799 // extra load to get the address of the global.
1800 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1801 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1802 false, false, false, 0);
1806 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1807 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1810 if (Op.getValueType() == MVT::v2i64) {
1811 // When the operands themselves are v2i64 values, we need to do something
1812 // special because VSX has no underlying comparison operations for these.
1813 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1814 // Equality can be handled by casting to the legal type for Altivec
1815 // comparisons, everything else needs to be expanded.
1816 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1817 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1818 DAG.getSetCC(dl, MVT::v4i32,
1819 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1820 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1827 // We handle most of these in the usual way.
1831 // If we're comparing for equality to zero, expose the fact that this is
1832 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1833 // fold the new nodes.
1834 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1835 if (C->isNullValue() && CC == ISD::SETEQ) {
1836 EVT VT = Op.getOperand(0).getValueType();
1837 SDValue Zext = Op.getOperand(0);
1838 if (VT.bitsLT(MVT::i32)) {
1840 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1842 unsigned Log2b = Log2_32(VT.getSizeInBits());
1843 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1844 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1845 DAG.getConstant(Log2b, MVT::i32));
1846 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1848 // Leave comparisons against 0 and -1 alone for now, since they're usually
1849 // optimized. FIXME: revisit this when we can custom lower all setcc
1851 if (C->isAllOnesValue() || C->isNullValue())
1855 // If we have an integer seteq/setne, turn it into a compare against zero
1856 // by xor'ing the rhs with the lhs, which is faster than setting a
1857 // condition register, reading it back out, and masking the correct bit. The
1858 // normal approach here uses sub to do this instead of xor. Using xor exposes
1859 // the result to other bit-twiddling opportunities.
1860 EVT LHSVT = Op.getOperand(0).getValueType();
1861 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1862 EVT VT = Op.getValueType();
1863 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1865 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1870 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1871 const PPCSubtarget &Subtarget) const {
1872 SDNode *Node = Op.getNode();
1873 EVT VT = Node->getValueType(0);
1874 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1875 SDValue InChain = Node->getOperand(0);
1876 SDValue VAListPtr = Node->getOperand(1);
1877 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1880 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1883 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1884 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1885 false, false, false, 0);
1886 InChain = GprIndex.getValue(1);
1888 if (VT == MVT::i64) {
1889 // Check if GprIndex is even
1890 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1891 DAG.getConstant(1, MVT::i32));
1892 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1893 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1894 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1895 DAG.getConstant(1, MVT::i32));
1896 // Align GprIndex to be even if it isn't
1897 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1901 // fpr index is 1 byte after gpr
1902 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1903 DAG.getConstant(1, MVT::i32));
1906 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1907 FprPtr, MachinePointerInfo(SV), MVT::i8,
1908 false, false, false, 0);
1909 InChain = FprIndex.getValue(1);
1911 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1912 DAG.getConstant(8, MVT::i32));
1914 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1915 DAG.getConstant(4, MVT::i32));
1918 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1919 MachinePointerInfo(), false, false,
1921 InChain = OverflowArea.getValue(1);
1923 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1924 MachinePointerInfo(), false, false,
1926 InChain = RegSaveArea.getValue(1);
1928 // select overflow_area if index > 8
1929 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1930 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1932 // adjustment constant gpr_index * 4/8
1933 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1934 VT.isInteger() ? GprIndex : FprIndex,
1935 DAG.getConstant(VT.isInteger() ? 4 : 8,
1938 // OurReg = RegSaveArea + RegConstant
1939 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1942 // Floating types are 32 bytes into RegSaveArea
1943 if (VT.isFloatingPoint())
1944 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1945 DAG.getConstant(32, MVT::i32));
1947 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1948 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1949 VT.isInteger() ? GprIndex : FprIndex,
1950 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1953 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1954 VT.isInteger() ? VAListPtr : FprPtr,
1955 MachinePointerInfo(SV),
1956 MVT::i8, false, false, 0);
1958 // determine if we should load from reg_save_area or overflow_area
1959 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1961 // increase overflow_area by 4/8 if gpr/fpr > 8
1962 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1963 DAG.getConstant(VT.isInteger() ? 4 : 8,
1966 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1969 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1971 MachinePointerInfo(),
1972 MVT::i32, false, false, 0);
1974 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1975 false, false, false, 0);
1978 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1979 const PPCSubtarget &Subtarget) const {
1980 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1982 // We have to copy the entire va_list struct:
1983 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1984 return DAG.getMemcpy(Op.getOperand(0), Op,
1985 Op.getOperand(1), Op.getOperand(2),
1986 DAG.getConstant(12, MVT::i32), 8, false, true,
1987 MachinePointerInfo(), MachinePointerInfo());
1990 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1991 SelectionDAG &DAG) const {
1992 return Op.getOperand(0);
1995 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1996 SelectionDAG &DAG) const {
1997 SDValue Chain = Op.getOperand(0);
1998 SDValue Trmp = Op.getOperand(1); // trampoline
1999 SDValue FPtr = Op.getOperand(2); // nested function
2000 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2003 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2004 bool isPPC64 = (PtrVT == MVT::i64);
2006 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2009 TargetLowering::ArgListTy Args;
2010 TargetLowering::ArgListEntry Entry;
2012 Entry.Ty = IntPtrTy;
2013 Entry.Node = Trmp; Args.push_back(Entry);
2015 // TrampSize == (isPPC64 ? 48 : 40);
2016 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2017 isPPC64 ? MVT::i64 : MVT::i32);
2018 Args.push_back(Entry);
2020 Entry.Node = FPtr; Args.push_back(Entry);
2021 Entry.Node = Nest; Args.push_back(Entry);
2023 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2024 TargetLowering::CallLoweringInfo CLI(DAG);
2025 CLI.setDebugLoc(dl).setChain(Chain)
2026 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2027 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2028 std::move(Args), 0);
2030 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2031 return CallResult.second;
2034 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2035 const PPCSubtarget &Subtarget) const {
2036 MachineFunction &MF = DAG.getMachineFunction();
2037 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2041 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2042 // vastart just stores the address of the VarArgsFrameIndex slot into the
2043 // memory location argument.
2044 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2045 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2046 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2047 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2048 MachinePointerInfo(SV),
2052 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2053 // We suppose the given va_list is already allocated.
2056 // char gpr; /* index into the array of 8 GPRs
2057 // * stored in the register save area
2058 // * gpr=0 corresponds to r3,
2059 // * gpr=1 to r4, etc.
2061 // char fpr; /* index into the array of 8 FPRs
2062 // * stored in the register save area
2063 // * fpr=0 corresponds to f1,
2064 // * fpr=1 to f2, etc.
2066 // char *overflow_arg_area;
2067 // /* location on stack that holds
2068 // * the next overflow argument
2070 // char *reg_save_area;
2071 // /* where r3:r10 and f1:f8 (if saved)
2077 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2078 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2081 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2083 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2085 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2088 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2089 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2091 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2092 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2094 uint64_t FPROffset = 1;
2095 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2097 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2099 // Store first byte : number of int regs
2100 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2102 MachinePointerInfo(SV),
2103 MVT::i8, false, false, 0);
2104 uint64_t nextOffset = FPROffset;
2105 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2108 // Store second byte : number of float regs
2109 SDValue secondStore =
2110 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2111 MachinePointerInfo(SV, nextOffset), MVT::i8,
2113 nextOffset += StackOffset;
2114 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2116 // Store second word : arguments given on stack
2117 SDValue thirdStore =
2118 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2119 MachinePointerInfo(SV, nextOffset),
2121 nextOffset += FrameOffset;
2122 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2124 // Store third word : arguments given in registers
2125 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2126 MachinePointerInfo(SV, nextOffset),
2131 #include "PPCGenCallingConv.inc"
2133 // Function whose sole purpose is to kill compiler warnings
2134 // stemming from unused functions included from PPCGenCallingConv.inc.
2135 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2136 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2139 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2140 CCValAssign::LocInfo &LocInfo,
2141 ISD::ArgFlagsTy &ArgFlags,
2146 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2148 CCValAssign::LocInfo &LocInfo,
2149 ISD::ArgFlagsTy &ArgFlags,
2151 static const MCPhysReg ArgRegs[] = {
2152 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2153 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2155 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2157 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2159 // Skip one register if the first unallocated register has an even register
2160 // number and there are still argument registers available which have not been
2161 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2162 // need to skip a register if RegNum is odd.
2163 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2164 State.AllocateReg(ArgRegs[RegNum]);
2167 // Always return false here, as this function only makes sure that the first
2168 // unallocated register has an odd register number and does not actually
2169 // allocate a register for the current argument.
2173 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2175 CCValAssign::LocInfo &LocInfo,
2176 ISD::ArgFlagsTy &ArgFlags,
2178 static const MCPhysReg ArgRegs[] = {
2179 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2183 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2185 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2187 // If there is only one Floating-point register left we need to put both f64
2188 // values of a split ppc_fp128 value on the stack.
2189 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2190 State.AllocateReg(ArgRegs[RegNum]);
2193 // Always return false here, as this function only makes sure that the two f64
2194 // values a ppc_fp128 value is split into are both passed in registers or both
2195 // passed on the stack and does not actually allocate a register for the
2196 // current argument.
2200 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2202 static const MCPhysReg *GetFPR() {
2203 static const MCPhysReg FPR[] = {
2204 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2205 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2211 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2213 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2214 unsigned PtrByteSize) {
2215 unsigned ArgSize = ArgVT.getStoreSize();
2216 if (Flags.isByVal())
2217 ArgSize = Flags.getByValSize();
2219 // Round up to multiples of the pointer size, except for array members,
2220 // which are always packed.
2221 if (!Flags.isInConsecutiveRegs())
2222 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2227 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2229 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2230 ISD::ArgFlagsTy Flags,
2231 unsigned PtrByteSize) {
2232 unsigned Align = PtrByteSize;
2234 // Altivec parameters are padded to a 16 byte boundary.
2235 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2236 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2237 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2240 // ByVal parameters are aligned as requested.
2241 if (Flags.isByVal()) {
2242 unsigned BVAlign = Flags.getByValAlign();
2243 if (BVAlign > PtrByteSize) {
2244 if (BVAlign % PtrByteSize != 0)
2246 "ByVal alignment is not a multiple of the pointer size");
2252 // Array members are always packed to their original alignment.
2253 if (Flags.isInConsecutiveRegs()) {
2254 // If the array member was split into multiple registers, the first
2255 // needs to be aligned to the size of the full type. (Except for
2256 // ppcf128, which is only aligned as its f64 components.)
2257 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2258 Align = OrigVT.getStoreSize();
2260 Align = ArgVT.getStoreSize();
2266 /// CalculateStackSlotUsed - Return whether this argument will use its
2267 /// stack slot (instead of being passed in registers). ArgOffset,
2268 /// AvailableFPRs, and AvailableVRs must hold the current argument
2269 /// position, and will be updated to account for this argument.
2270 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2271 ISD::ArgFlagsTy Flags,
2272 unsigned PtrByteSize,
2273 unsigned LinkageSize,
2274 unsigned ParamAreaSize,
2275 unsigned &ArgOffset,
2276 unsigned &AvailableFPRs,
2277 unsigned &AvailableVRs) {
2278 bool UseMemory = false;
2280 // Respect alignment of argument on the stack.
2282 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2283 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2284 // If there's no space left in the argument save area, we must
2285 // use memory (this check also catches zero-sized arguments).
2286 if (ArgOffset >= LinkageSize + ParamAreaSize)
2289 // Allocate argument on the stack.
2290 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2291 if (Flags.isInConsecutiveRegsLast())
2292 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2293 // If we overran the argument save area, we must use memory
2294 // (this check catches arguments passed partially in memory)
2295 if (ArgOffset > LinkageSize + ParamAreaSize)
2298 // However, if the argument is actually passed in an FPR or a VR,
2299 // we don't use memory after all.
2300 if (!Flags.isByVal()) {
2301 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2302 if (AvailableFPRs > 0) {
2306 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2307 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2308 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2309 if (AvailableVRs > 0) {
2318 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2319 /// ensure minimum alignment required for target.
2320 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2321 unsigned NumBytes) {
2322 unsigned TargetAlign =
2323 Target.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
2324 unsigned AlignMask = TargetAlign - 1;
2325 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2330 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2331 CallingConv::ID CallConv, bool isVarArg,
2332 const SmallVectorImpl<ISD::InputArg>
2334 SDLoc dl, SelectionDAG &DAG,
2335 SmallVectorImpl<SDValue> &InVals)
2337 if (Subtarget.isSVR4ABI()) {
2338 if (Subtarget.isPPC64())
2339 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2342 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2345 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2351 PPCTargetLowering::LowerFormalArguments_32SVR4(
2353 CallingConv::ID CallConv, bool isVarArg,
2354 const SmallVectorImpl<ISD::InputArg>
2356 SDLoc dl, SelectionDAG &DAG,
2357 SmallVectorImpl<SDValue> &InVals) const {
2359 // 32-bit SVR4 ABI Stack Frame Layout:
2360 // +-----------------------------------+
2361 // +--> | Back chain |
2362 // | +-----------------------------------+
2363 // | | Floating-point register save area |
2364 // | +-----------------------------------+
2365 // | | General register save area |
2366 // | +-----------------------------------+
2367 // | | CR save word |
2368 // | +-----------------------------------+
2369 // | | VRSAVE save word |
2370 // | +-----------------------------------+
2371 // | | Alignment padding |
2372 // | +-----------------------------------+
2373 // | | Vector register save area |
2374 // | +-----------------------------------+
2375 // | | Local variable space |
2376 // | +-----------------------------------+
2377 // | | Parameter list area |
2378 // | +-----------------------------------+
2379 // | | LR save word |
2380 // | +-----------------------------------+
2381 // SP--> +--- | Back chain |
2382 // +-----------------------------------+
2385 // System V Application Binary Interface PowerPC Processor Supplement
2386 // AltiVec Technology Programming Interface Manual
2388 MachineFunction &MF = DAG.getMachineFunction();
2389 MachineFrameInfo *MFI = MF.getFrameInfo();
2390 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2392 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2393 // Potential tail calls could cause overwriting of argument stack slots.
2394 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2395 (CallConv == CallingConv::Fast));
2396 unsigned PtrByteSize = 4;
2398 // Assign locations to all of the incoming arguments.
2399 SmallVector<CCValAssign, 16> ArgLocs;
2400 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2403 // Reserve space for the linkage area on the stack.
2404 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2405 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2407 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2409 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2410 CCValAssign &VA = ArgLocs[i];
2412 // Arguments stored in registers.
2413 if (VA.isRegLoc()) {
2414 const TargetRegisterClass *RC;
2415 EVT ValVT = VA.getValVT();
2417 switch (ValVT.getSimpleVT().SimpleTy) {
2419 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2422 RC = &PPC::GPRCRegClass;
2425 RC = &PPC::F4RCRegClass;
2428 if (Subtarget.hasVSX())
2429 RC = &PPC::VSFRCRegClass;
2431 RC = &PPC::F8RCRegClass;
2437 RC = &PPC::VRRCRegClass;
2441 RC = &PPC::VSHRCRegClass;
2445 // Transform the arguments stored in physical registers into virtual ones.
2446 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2447 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2448 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2450 if (ValVT == MVT::i1)
2451 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2453 InVals.push_back(ArgValue);
2455 // Argument stored in memory.
2456 assert(VA.isMemLoc());
2458 unsigned ArgSize = VA.getLocVT().getStoreSize();
2459 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2462 // Create load nodes to retrieve arguments from the stack.
2463 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2464 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2465 MachinePointerInfo(),
2466 false, false, false, 0));
2470 // Assign locations to all of the incoming aggregate by value arguments.
2471 // Aggregates passed by value are stored in the local variable space of the
2472 // caller's stack frame, right above the parameter list area.
2473 SmallVector<CCValAssign, 16> ByValArgLocs;
2474 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2475 ByValArgLocs, *DAG.getContext());
2477 // Reserve stack space for the allocations in CCInfo.
2478 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2480 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2482 // Area that is at least reserved in the caller of this function.
2483 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2484 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2486 // Set the size that is at least reserved in caller of this function. Tail
2487 // call optimized function's reserved stack space needs to be aligned so that
2488 // taking the difference between two stack areas will result in an aligned
2490 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2491 FuncInfo->setMinReservedArea(MinReservedArea);
2493 SmallVector<SDValue, 8> MemOps;
2495 // If the function takes variable number of arguments, make a frame index for
2496 // the start of the first vararg value... for expansion of llvm.va_start.
2498 static const MCPhysReg GPArgRegs[] = {
2499 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2500 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2502 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2504 static const MCPhysReg FPArgRegs[] = {
2505 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2508 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2509 if (DisablePPCFloatInVariadic)
2512 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2514 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2517 // Make room for NumGPArgRegs and NumFPArgRegs.
2518 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2519 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2521 FuncInfo->setVarArgsStackOffset(
2522 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2523 CCInfo.getNextStackOffset(), true));
2525 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2526 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2528 // The fixed integer arguments of a variadic function are stored to the
2529 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2530 // the result of va_next.
2531 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2532 // Get an existing live-in vreg, or add a new one.
2533 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2535 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2537 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2538 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2539 MachinePointerInfo(), false, false, 0);
2540 MemOps.push_back(Store);
2541 // Increment the address by four for the next argument to store
2542 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2543 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2546 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2548 // The double arguments are stored to the VarArgsFrameIndex
2550 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2551 // Get an existing live-in vreg, or add a new one.
2552 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2554 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2556 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2557 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2558 MachinePointerInfo(), false, false, 0);
2559 MemOps.push_back(Store);
2560 // Increment the address by eight for the next argument to store
2561 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
2563 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2567 if (!MemOps.empty())
2568 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2573 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2574 // value to MVT::i64 and then truncate to the correct register size.
2576 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2577 SelectionDAG &DAG, SDValue ArgVal,
2580 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2581 DAG.getValueType(ObjectVT));
2582 else if (Flags.isZExt())
2583 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2584 DAG.getValueType(ObjectVT));
2586 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2590 PPCTargetLowering::LowerFormalArguments_64SVR4(
2592 CallingConv::ID CallConv, bool isVarArg,
2593 const SmallVectorImpl<ISD::InputArg>
2595 SDLoc dl, SelectionDAG &DAG,
2596 SmallVectorImpl<SDValue> &InVals) const {
2597 // TODO: add description of PPC stack frame format, or at least some docs.
2599 bool isELFv2ABI = Subtarget.isELFv2ABI();
2600 bool isLittleEndian = Subtarget.isLittleEndian();
2601 MachineFunction &MF = DAG.getMachineFunction();
2602 MachineFrameInfo *MFI = MF.getFrameInfo();
2603 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2605 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2606 // Potential tail calls could cause overwriting of argument stack slots.
2607 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2608 (CallConv == CallingConv::Fast));
2609 unsigned PtrByteSize = 8;
2611 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2614 static const MCPhysReg GPR[] = {
2615 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2616 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2619 static const MCPhysReg *FPR = GetFPR();
2621 static const MCPhysReg VR[] = {
2622 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2623 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2625 static const MCPhysReg VSRH[] = {
2626 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2627 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2630 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2631 const unsigned Num_FPR_Regs = 13;
2632 const unsigned Num_VR_Regs = array_lengthof(VR);
2634 // Do a first pass over the arguments to determine whether the ABI
2635 // guarantees that our caller has allocated the parameter save area
2636 // on its stack frame. In the ELFv1 ABI, this is always the case;
2637 // in the ELFv2 ABI, it is true if this is a vararg function or if
2638 // any parameter is located in a stack slot.
2640 bool HasParameterArea = !isELFv2ABI || isVarArg;
2641 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2642 unsigned NumBytes = LinkageSize;
2643 unsigned AvailableFPRs = Num_FPR_Regs;
2644 unsigned AvailableVRs = Num_VR_Regs;
2645 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2646 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2647 PtrByteSize, LinkageSize, ParamAreaSize,
2648 NumBytes, AvailableFPRs, AvailableVRs))
2649 HasParameterArea = true;
2651 // Add DAG nodes to load the arguments or copy them out of registers. On
2652 // entry to a function on PPC, the arguments start after the linkage area,
2653 // although the first ones are often in registers.
2655 unsigned ArgOffset = LinkageSize;
2656 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
2657 SmallVector<SDValue, 8> MemOps;
2658 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2659 unsigned CurArgIdx = 0;
2660 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2662 bool needsLoad = false;
2663 EVT ObjectVT = Ins[ArgNo].VT;
2664 EVT OrigVT = Ins[ArgNo].ArgVT;
2665 unsigned ObjSize = ObjectVT.getStoreSize();
2666 unsigned ArgSize = ObjSize;
2667 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2668 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2669 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2671 /* Respect alignment of argument on the stack. */
2673 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2674 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2675 unsigned CurArgOffset = ArgOffset;
2677 /* Compute GPR index associated with argument offset. */
2678 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2679 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2681 // FIXME the codegen can be much improved in some cases.
2682 // We do not have to keep everything in memory.
2683 if (Flags.isByVal()) {
2684 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2685 ObjSize = Flags.getByValSize();
2686 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2687 // Empty aggregate parameters do not take up registers. Examples:
2691 // etc. However, we have to provide a place-holder in InVals, so
2692 // pretend we have an 8-byte item at the current address for that
2695 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2696 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2697 InVals.push_back(FIN);
2701 // Create a stack object covering all stack doublewords occupied
2702 // by the argument. If the argument is (fully or partially) on
2703 // the stack, or if the argument is fully in registers but the
2704 // caller has allocated the parameter save anyway, we can refer
2705 // directly to the caller's stack frame. Otherwise, create a
2706 // local copy in our own frame.
2708 if (HasParameterArea ||
2709 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2710 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
2712 FI = MFI->CreateStackObject(ArgSize, Align, false);
2713 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2715 // Handle aggregates smaller than 8 bytes.
2716 if (ObjSize < PtrByteSize) {
2717 // The value of the object is its address, which differs from the
2718 // address of the enclosing doubleword on big-endian systems.
2720 if (!isLittleEndian) {
2721 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2722 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2724 InVals.push_back(Arg);
2726 if (GPR_idx != Num_GPR_Regs) {
2727 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2728 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2731 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2732 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2733 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2734 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2735 MachinePointerInfo(FuncArg),
2736 ObjType, false, false, 0);
2738 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2739 // store the whole register as-is to the parameter save area
2741 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2742 MachinePointerInfo(FuncArg),
2746 MemOps.push_back(Store);
2748 // Whether we copied from a register or not, advance the offset
2749 // into the parameter save area by a full doubleword.
2750 ArgOffset += PtrByteSize;
2754 // The value of the object is its address, which is the address of
2755 // its first stack doubleword.
2756 InVals.push_back(FIN);
2758 // Store whatever pieces of the object are in registers to memory.
2759 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2760 if (GPR_idx == Num_GPR_Regs)
2763 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2764 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2767 SDValue Off = DAG.getConstant(j, PtrVT);
2768 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2770 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2771 MachinePointerInfo(FuncArg, j),
2773 MemOps.push_back(Store);
2776 ArgOffset += ArgSize;
2780 switch (ObjectVT.getSimpleVT().SimpleTy) {
2781 default: llvm_unreachable("Unhandled argument type!");
2785 // These can be scalar arguments or elements of an integer array type
2786 // passed directly. Clang may use those instead of "byval" aggregate
2787 // types to avoid forcing arguments to memory unnecessarily.
2788 if (GPR_idx != Num_GPR_Regs) {
2789 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2790 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2792 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2793 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2794 // value to MVT::i64 and then truncate to the correct register size.
2795 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2798 ArgSize = PtrByteSize;
2805 // These can be scalar arguments or elements of a float array type
2806 // passed directly. The latter are used to implement ELFv2 homogenous
2807 // float aggregates.
2808 if (FPR_idx != Num_FPR_Regs) {
2811 if (ObjectVT == MVT::f32)
2812 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2814 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2815 &PPC::VSFRCRegClass :
2816 &PPC::F8RCRegClass);
2818 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2820 } else if (GPR_idx != Num_GPR_Regs) {
2821 // This can only ever happen in the presence of f32 array types,
2822 // since otherwise we never run out of FPRs before running out
2824 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2825 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2827 if (ObjectVT == MVT::f32) {
2828 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2829 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2830 DAG.getConstant(32, MVT::i32));
2831 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2834 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2839 // When passing an array of floats, the array occupies consecutive
2840 // space in the argument area; only round up to the next doubleword
2841 // at the end of the array. Otherwise, each float takes 8 bytes.
2842 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2843 ArgOffset += ArgSize;
2844 if (Flags.isInConsecutiveRegsLast())
2845 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2853 // These can be scalar arguments or elements of a vector array type
2854 // passed directly. The latter are used to implement ELFv2 homogenous
2855 // vector aggregates.
2856 if (VR_idx != Num_VR_Regs) {
2857 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2858 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2859 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2860 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2869 // We need to load the argument to a virtual register if we determined
2870 // above that we ran out of physical registers of the appropriate type.
2872 if (ObjSize < ArgSize && !isLittleEndian)
2873 CurArgOffset += ArgSize - ObjSize;
2874 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2875 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2876 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2877 false, false, false, 0);
2880 InVals.push_back(ArgVal);
2883 // Area that is at least reserved in the caller of this function.
2884 unsigned MinReservedArea;
2885 if (HasParameterArea)
2886 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2888 MinReservedArea = LinkageSize;
2890 // Set the size that is at least reserved in caller of this function. Tail
2891 // call optimized functions' reserved stack space needs to be aligned so that
2892 // taking the difference between two stack areas will result in an aligned
2894 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2895 FuncInfo->setMinReservedArea(MinReservedArea);
2897 // If the function takes variable number of arguments, make a frame index for
2898 // the start of the first vararg value... for expansion of llvm.va_start.
2900 int Depth = ArgOffset;
2902 FuncInfo->setVarArgsFrameIndex(
2903 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2904 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2906 // If this function is vararg, store any remaining integer argument regs
2907 // to their spots on the stack so that they may be loaded by deferencing the
2908 // result of va_next.
2909 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2910 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2911 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2912 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2913 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2914 MachinePointerInfo(), false, false, 0);
2915 MemOps.push_back(Store);
2916 // Increment the address by four for the next argument to store
2917 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2918 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2922 if (!MemOps.empty())
2923 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2929 PPCTargetLowering::LowerFormalArguments_Darwin(
2931 CallingConv::ID CallConv, bool isVarArg,
2932 const SmallVectorImpl<ISD::InputArg>
2934 SDLoc dl, SelectionDAG &DAG,
2935 SmallVectorImpl<SDValue> &InVals) const {
2936 // TODO: add description of PPC stack frame format, or at least some docs.
2938 MachineFunction &MF = DAG.getMachineFunction();
2939 MachineFrameInfo *MFI = MF.getFrameInfo();
2940 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2942 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2943 bool isPPC64 = PtrVT == MVT::i64;
2944 // Potential tail calls could cause overwriting of argument stack slots.
2945 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2946 (CallConv == CallingConv::Fast));
2947 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2949 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
2951 unsigned ArgOffset = LinkageSize;
2952 // Area that is at least reserved in caller of this function.
2953 unsigned MinReservedArea = ArgOffset;
2955 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2956 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2957 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2959 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2960 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2961 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2964 static const MCPhysReg *FPR = GetFPR();
2966 static const MCPhysReg VR[] = {
2967 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2968 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2971 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2972 const unsigned Num_FPR_Regs = 13;
2973 const unsigned Num_VR_Regs = array_lengthof( VR);
2975 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2977 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2979 // In 32-bit non-varargs functions, the stack space for vectors is after the
2980 // stack space for non-vectors. We do not use this space unless we have
2981 // too many vectors to fit in registers, something that only occurs in
2982 // constructed examples:), but we have to walk the arglist to figure
2983 // that out...for the pathological case, compute VecArgOffset as the
2984 // start of the vector parameter area. Computing VecArgOffset is the
2985 // entire point of the following loop.
2986 unsigned VecArgOffset = ArgOffset;
2987 if (!isVarArg && !isPPC64) {
2988 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2990 EVT ObjectVT = Ins[ArgNo].VT;
2991 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2993 if (Flags.isByVal()) {
2994 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2995 unsigned ObjSize = Flags.getByValSize();
2997 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2998 VecArgOffset += ArgSize;
3002 switch(ObjectVT.getSimpleVT().SimpleTy) {
3003 default: llvm_unreachable("Unhandled argument type!");
3009 case MVT::i64: // PPC64
3011 // FIXME: We are guaranteed to be !isPPC64 at this point.
3012 // Does MVT::i64 apply?
3019 // Nothing to do, we're only looking at Nonvector args here.
3024 // We've found where the vector parameter area in memory is. Skip the
3025 // first 12 parameters; these don't use that memory.
3026 VecArgOffset = ((VecArgOffset+15)/16)*16;
3027 VecArgOffset += 12*16;
3029 // Add DAG nodes to load the arguments or copy them out of registers. On
3030 // entry to a function on PPC, the arguments start after the linkage area,
3031 // although the first ones are often in registers.
3033 SmallVector<SDValue, 8> MemOps;
3034 unsigned nAltivecParamsAtEnd = 0;
3035 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3036 unsigned CurArgIdx = 0;
3037 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3039 bool needsLoad = false;
3040 EVT ObjectVT = Ins[ArgNo].VT;
3041 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3042 unsigned ArgSize = ObjSize;
3043 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3044 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3045 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3047 unsigned CurArgOffset = ArgOffset;
3049 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3050 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3051 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3052 if (isVarArg || isPPC64) {
3053 MinReservedArea = ((MinReservedArea+15)/16)*16;
3054 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3057 } else nAltivecParamsAtEnd++;
3059 // Calculate min reserved area.
3060 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3064 // FIXME the codegen can be much improved in some cases.
3065 // We do not have to keep everything in memory.
3066 if (Flags.isByVal()) {
3067 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3068 ObjSize = Flags.getByValSize();
3069 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3070 // Objects of size 1 and 2 are right justified, everything else is
3071 // left justified. This means the memory address is adjusted forwards.
3072 if (ObjSize==1 || ObjSize==2) {
3073 CurArgOffset = CurArgOffset + (4 - ObjSize);
3075 // The value of the object is its address.
3076 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3077 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3078 InVals.push_back(FIN);
3079 if (ObjSize==1 || ObjSize==2) {
3080 if (GPR_idx != Num_GPR_Regs) {
3083 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3085 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3086 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3087 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3088 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3089 MachinePointerInfo(FuncArg),
3090 ObjType, false, false, 0);
3091 MemOps.push_back(Store);
3095 ArgOffset += PtrByteSize;
3099 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3100 // Store whatever pieces of the object are in registers
3101 // to memory. ArgOffset will be the address of the beginning
3103 if (GPR_idx != Num_GPR_Regs) {
3106 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3108 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3109 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3110 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3111 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3112 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3113 MachinePointerInfo(FuncArg, j),
3115 MemOps.push_back(Store);
3117 ArgOffset += PtrByteSize;
3119 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3126 switch (ObjectVT.getSimpleVT().SimpleTy) {
3127 default: llvm_unreachable("Unhandled argument type!");
3131 if (GPR_idx != Num_GPR_Regs) {
3132 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3133 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3135 if (ObjectVT == MVT::i1)
3136 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3141 ArgSize = PtrByteSize;
3143 // All int arguments reserve stack space in the Darwin ABI.
3144 ArgOffset += PtrByteSize;
3148 case MVT::i64: // PPC64
3149 if (GPR_idx != Num_GPR_Regs) {
3150 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3151 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3153 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3154 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3155 // value to MVT::i64 and then truncate to the correct register size.
3156 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3161 ArgSize = PtrByteSize;
3163 // All int arguments reserve stack space in the Darwin ABI.
3169 // Every 4 bytes of argument space consumes one of the GPRs available for
3170 // argument passing.
3171 if (GPR_idx != Num_GPR_Regs) {
3173 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3176 if (FPR_idx != Num_FPR_Regs) {
3179 if (ObjectVT == MVT::f32)
3180 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3182 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3184 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3190 // All FP arguments reserve stack space in the Darwin ABI.
3191 ArgOffset += isPPC64 ? 8 : ObjSize;
3197 // Note that vector arguments in registers don't reserve stack space,
3198 // except in varargs functions.
3199 if (VR_idx != Num_VR_Regs) {
3200 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3201 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3203 while ((ArgOffset % 16) != 0) {
3204 ArgOffset += PtrByteSize;
3205 if (GPR_idx != Num_GPR_Regs)
3209 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3213 if (!isVarArg && !isPPC64) {
3214 // Vectors go after all the nonvectors.
3215 CurArgOffset = VecArgOffset;
3218 // Vectors are aligned.
3219 ArgOffset = ((ArgOffset+15)/16)*16;
3220 CurArgOffset = ArgOffset;
3228 // We need to load the argument to a virtual register if we determined above
3229 // that we ran out of physical registers of the appropriate type.
3231 int FI = MFI->CreateFixedObject(ObjSize,
3232 CurArgOffset + (ArgSize - ObjSize),
3234 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3235 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3236 false, false, false, 0);
3239 InVals.push_back(ArgVal);
3242 // Allow for Altivec parameters at the end, if needed.
3243 if (nAltivecParamsAtEnd) {
3244 MinReservedArea = ((MinReservedArea+15)/16)*16;
3245 MinReservedArea += 16*nAltivecParamsAtEnd;
3248 // Area that is at least reserved in the caller of this function.
3249 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3251 // Set the size that is at least reserved in caller of this function. Tail
3252 // call optimized functions' reserved stack space needs to be aligned so that
3253 // taking the difference between two stack areas will result in an aligned
3255 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3256 FuncInfo->setMinReservedArea(MinReservedArea);
3258 // If the function takes variable number of arguments, make a frame index for
3259 // the start of the first vararg value... for expansion of llvm.va_start.
3261 int Depth = ArgOffset;
3263 FuncInfo->setVarArgsFrameIndex(
3264 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3266 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3268 // If this function is vararg, store any remaining integer argument regs
3269 // to their spots on the stack so that they may be loaded by deferencing the
3270 // result of va_next.
3271 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3275 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3277 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3279 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3280 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3281 MachinePointerInfo(), false, false, 0);
3282 MemOps.push_back(Store);
3283 // Increment the address by four for the next argument to store
3284 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3285 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3289 if (!MemOps.empty())
3290 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3295 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3296 /// adjusted to accommodate the arguments for the tailcall.
3297 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3298 unsigned ParamSize) {
3300 if (!isTailCall) return 0;
3302 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3303 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3304 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3305 // Remember only if the new adjustement is bigger.
3306 if (SPDiff < FI->getTailCallSPDelta())
3307 FI->setTailCallSPDelta(SPDiff);
3312 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3313 /// for tail call optimization. Targets which want to do tail call
3314 /// optimization should implement this function.
3316 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3317 CallingConv::ID CalleeCC,
3319 const SmallVectorImpl<ISD::InputArg> &Ins,
3320 SelectionDAG& DAG) const {
3321 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3324 // Variable argument functions are not supported.
3328 MachineFunction &MF = DAG.getMachineFunction();
3329 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3330 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3331 // Functions containing by val parameters are not supported.
3332 for (unsigned i = 0; i != Ins.size(); i++) {
3333 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3334 if (Flags.isByVal()) return false;
3337 // Non-PIC/GOT tail calls are supported.
3338 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3341 // At the moment we can only do local tail calls (in same module, hidden
3342 // or protected) if we are generating PIC.
3343 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3344 return G->getGlobal()->hasHiddenVisibility()
3345 || G->getGlobal()->hasProtectedVisibility();
3351 /// isCallCompatibleAddress - Return the immediate to use if the specified
3352 /// 32-bit value is representable in the immediate field of a BxA instruction.
3353 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3354 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3355 if (!C) return nullptr;
3357 int Addr = C->getZExtValue();
3358 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3359 SignExtend32<26>(Addr) != Addr)
3360 return nullptr; // Top 6 bits have to be sext of immediate.
3362 return DAG.getConstant((int)C->getZExtValue() >> 2,
3363 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3368 struct TailCallArgumentInfo {
3373 TailCallArgumentInfo() : FrameIdx(0) {}
3378 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3380 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3382 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3383 SmallVectorImpl<SDValue> &MemOpChains,
3385 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3386 SDValue Arg = TailCallArgs[i].Arg;
3387 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3388 int FI = TailCallArgs[i].FrameIdx;
3389 // Store relative to framepointer.
3390 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3391 MachinePointerInfo::getFixedStack(FI),
3396 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3397 /// the appropriate stack slot for the tail call optimized function call.
3398 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3399 MachineFunction &MF,
3408 // Calculate the new stack slot for the return address.
3409 int SlotSize = isPPC64 ? 8 : 4;
3410 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3412 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3413 NewRetAddrLoc, true);
3414 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3415 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3416 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3417 MachinePointerInfo::getFixedStack(NewRetAddr),
3420 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3421 // slot as the FP is never overwritten.
3424 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3425 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3427 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3428 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3429 MachinePointerInfo::getFixedStack(NewFPIdx),
3436 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3437 /// the position of the argument.
3439 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3440 SDValue Arg, int SPDiff, unsigned ArgOffset,
3441 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3442 int Offset = ArgOffset + SPDiff;
3443 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3444 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3445 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3446 SDValue FIN = DAG.getFrameIndex(FI, VT);
3447 TailCallArgumentInfo Info;
3449 Info.FrameIdxOp = FIN;
3451 TailCallArguments.push_back(Info);
3454 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3455 /// stack slot. Returns the chain as result and the loaded frame pointers in
3456 /// LROpOut/FPOpout. Used when tail calling.
3457 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3465 // Load the LR and FP stack slot for later adjusting.
3466 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3467 LROpOut = getReturnAddrFrameIndex(DAG);
3468 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3469 false, false, false, 0);
3470 Chain = SDValue(LROpOut.getNode(), 1);
3472 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3473 // slot as the FP is never overwritten.
3475 FPOpOut = getFramePointerFrameIndex(DAG);
3476 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3477 false, false, false, 0);
3478 Chain = SDValue(FPOpOut.getNode(), 1);
3484 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3485 /// by "Src" to address "Dst" of size "Size". Alignment information is
3486 /// specified by the specific parameter attribute. The copy will be passed as
3487 /// a byval function parameter.
3488 /// Sometimes what we are copying is the end of a larger object, the part that
3489 /// does not fit in registers.
3491 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3492 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3494 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3495 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3496 false, false, MachinePointerInfo(),
3497 MachinePointerInfo());
3500 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3503 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3504 SDValue Arg, SDValue PtrOff, int SPDiff,
3505 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3506 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3507 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3509 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3514 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3516 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3517 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3518 DAG.getConstant(ArgOffset, PtrVT));
3520 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3521 MachinePointerInfo(), false, false, 0));
3522 // Calculate and remember argument location.
3523 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3528 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3529 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3530 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3531 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3532 MachineFunction &MF = DAG.getMachineFunction();
3534 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3535 // might overwrite each other in case of tail call optimization.
3536 SmallVector<SDValue, 8> MemOpChains2;
3537 // Do not flag preceding copytoreg stuff together with the following stuff.
3539 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3541 if (!MemOpChains2.empty())
3542 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3544 // Store the return address to the appropriate stack slot.
3545 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3546 isPPC64, isDarwinABI, dl);
3548 // Emit callseq_end just before tailcall node.
3549 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3550 DAG.getIntPtrConstant(0, true), InFlag, dl);
3551 InFlag = Chain.getValue(1);
3555 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3556 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3557 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3558 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3559 const PPCSubtarget &Subtarget) {
3561 bool isPPC64 = Subtarget.isPPC64();
3562 bool isSVR4ABI = Subtarget.isSVR4ABI();
3563 bool isELFv2ABI = Subtarget.isELFv2ABI();
3565 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3566 NodeTys.push_back(MVT::Other); // Returns a chain
3567 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3569 unsigned CallOpc = PPCISD::CALL;
3571 bool needIndirectCall = true;
3572 if (!isSVR4ABI || !isPPC64)
3573 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3574 // If this is an absolute destination address, use the munged value.
3575 Callee = SDValue(Dest, 0);
3576 needIndirectCall = false;
3579 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3580 unsigned OpFlags = 0;
3581 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3582 (Subtarget.getTargetTriple().isMacOSX() &&
3583 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3584 (G->getGlobal()->isDeclaration() ||
3585 G->getGlobal()->isWeakForLinker())) ||
3586 (Subtarget.isTargetELF() && !isPPC64 &&
3587 !G->getGlobal()->hasLocalLinkage() &&
3588 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3589 // PC-relative references to external symbols should go through $stub,
3590 // unless we're building with the leopard linker or later, which
3591 // automatically synthesizes these stubs.
3592 OpFlags = PPCII::MO_PLT_OR_STUB;
3595 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3596 // every direct call is) turn it into a TargetGlobalAddress /
3597 // TargetExternalSymbol node so that legalize doesn't hack it.
3598 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3599 Callee.getValueType(), 0, OpFlags);
3600 needIndirectCall = false;
3603 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3604 unsigned char OpFlags = 0;
3606 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3607 (Subtarget.getTargetTriple().isMacOSX() &&
3608 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3609 (Subtarget.isTargetELF() && !isPPC64 &&
3610 DAG.getTarget().getRelocationModel() == Reloc::PIC_) ) {
3611 // PC-relative references to external symbols should go through $stub,
3612 // unless we're building with the leopard linker or later, which
3613 // automatically synthesizes these stubs.
3614 OpFlags = PPCII::MO_PLT_OR_STUB;
3617 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3619 needIndirectCall = false;
3622 if (needIndirectCall) {
3623 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3624 // to do the call, we can't use PPCISD::CALL.
3625 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3627 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3628 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3629 // entry point, but to the function descriptor (the function entry point
3630 // address is part of the function descriptor though).
3631 // The function descriptor is a three doubleword structure with the
3632 // following fields: function entry point, TOC base address and
3633 // environment pointer.
3634 // Thus for a call through a function pointer, the following actions need
3636 // 1. Save the TOC of the caller in the TOC save area of its stack
3637 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3638 // 2. Load the address of the function entry point from the function
3640 // 3. Load the TOC of the callee from the function descriptor into r2.
3641 // 4. Load the environment pointer from the function descriptor into
3643 // 5. Branch to the function entry point address.
3644 // 6. On return of the callee, the TOC of the caller needs to be
3645 // restored (this is done in FinishCall()).
3647 // All those operations are flagged together to ensure that no other
3648 // operations can be scheduled in between. E.g. without flagging the
3649 // operations together, a TOC access in the caller could be scheduled
3650 // between the load of the callee TOC and the branch to the callee, which
3651 // results in the TOC access going through the TOC of the callee instead
3652 // of going through the TOC of the caller, which leads to incorrect code.
3654 // Load the address of the function entry point from the function
3656 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3657 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3658 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3659 Chain = LoadFuncPtr.getValue(1);
3660 InFlag = LoadFuncPtr.getValue(2);
3662 // Load environment pointer into r11.
3663 // Offset of the environment pointer within the function descriptor.
3664 SDValue PtrOff = DAG.getIntPtrConstant(16);
3666 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3667 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3669 Chain = LoadEnvPtr.getValue(1);
3670 InFlag = LoadEnvPtr.getValue(2);
3672 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3674 Chain = EnvVal.getValue(0);
3675 InFlag = EnvVal.getValue(1);
3677 // Load TOC of the callee into r2. We are using a target-specific load
3678 // with r2 hard coded, because the result of a target-independent load
3679 // would never go directly into r2, since r2 is a reserved register (which
3680 // prevents the register allocator from allocating it), resulting in an
3681 // additional register being allocated and an unnecessary move instruction
3683 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3684 SDValue TOCOff = DAG.getIntPtrConstant(8);
3685 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3686 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3688 Chain = LoadTOCPtr.getValue(0);
3689 InFlag = LoadTOCPtr.getValue(1);
3691 MTCTROps[0] = Chain;
3692 MTCTROps[1] = LoadFuncPtr;
3693 MTCTROps[2] = InFlag;
3696 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3697 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3698 InFlag = Chain.getValue(1);
3701 NodeTys.push_back(MVT::Other);
3702 NodeTys.push_back(MVT::Glue);
3703 Ops.push_back(Chain);
3704 CallOpc = PPCISD::BCTRL;
3705 Callee.setNode(nullptr);
3706 // Add use of X11 (holding environment pointer)
3707 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3708 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3709 // Add CTR register as callee so a bctr can be emitted later.
3711 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3714 // If this is a direct call, pass the chain and the callee.
3715 if (Callee.getNode()) {
3716 Ops.push_back(Chain);
3717 Ops.push_back(Callee);
3719 // If this is a call to __tls_get_addr, find the symbol whose address
3720 // is to be taken and add it to the list. This will be used to
3721 // generate __tls_get_addr(<sym>@tlsgd) or __tls_get_addr(<sym>@tlsld).
3722 // We find the symbol by walking the chain to the CopyFromReg, walking
3723 // back from the CopyFromReg to the ADDI_TLSGD_L or ADDI_TLSLD_L, and
3724 // pulling the symbol from that node.
3725 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
3726 if (!strcmp(S->getSymbol(), "__tls_get_addr")) {
3727 assert(!needIndirectCall && "Indirect call to __tls_get_addr???");
3728 SDNode *AddI = Chain.getNode()->getOperand(2).getNode();
3729 SDValue TGTAddr = AddI->getOperand(1);
3730 assert(TGTAddr.getNode()->getOpcode() == ISD::TargetGlobalTLSAddress &&
3731 "Didn't find target global TLS address where we expected one");
3732 Ops.push_back(TGTAddr);
3733 CallOpc = PPCISD::CALL_TLS;
3736 // If this is a tail call add stack pointer delta.
3738 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3740 // Add argument registers to the end of the list so that they are known live
3742 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3743 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3744 RegsToPass[i].second.getValueType()));
3746 // Direct calls in the ELFv2 ABI need the TOC register live into the call.
3747 if (Callee.getNode() && isELFv2ABI)
3748 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3754 bool isLocalCall(const SDValue &Callee)
3756 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3757 return !G->getGlobal()->isDeclaration() &&
3758 !G->getGlobal()->isWeakForLinker();
3763 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3764 CallingConv::ID CallConv, bool isVarArg,
3765 const SmallVectorImpl<ISD::InputArg> &Ins,
3766 SDLoc dl, SelectionDAG &DAG,
3767 SmallVectorImpl<SDValue> &InVals) const {
3769 SmallVector<CCValAssign, 16> RVLocs;
3770 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3772 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3774 // Copy all of the result registers out of their specified physreg.
3775 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3776 CCValAssign &VA = RVLocs[i];
3777 assert(VA.isRegLoc() && "Can only return in registers!");
3779 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3780 VA.getLocReg(), VA.getLocVT(), InFlag);
3781 Chain = Val.getValue(1);
3782 InFlag = Val.getValue(2);
3784 switch (VA.getLocInfo()) {
3785 default: llvm_unreachable("Unknown loc info!");
3786 case CCValAssign::Full: break;
3787 case CCValAssign::AExt:
3788 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3790 case CCValAssign::ZExt:
3791 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3792 DAG.getValueType(VA.getValVT()));
3793 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3795 case CCValAssign::SExt:
3796 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3797 DAG.getValueType(VA.getValVT()));
3798 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3802 InVals.push_back(Val);
3809 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3810 bool isTailCall, bool isVarArg,
3812 SmallVector<std::pair<unsigned, SDValue>, 8>
3814 SDValue InFlag, SDValue Chain,
3816 int SPDiff, unsigned NumBytes,
3817 const SmallVectorImpl<ISD::InputArg> &Ins,
3818 SmallVectorImpl<SDValue> &InVals) const {
3820 bool isELFv2ABI = Subtarget.isELFv2ABI();
3821 std::vector<EVT> NodeTys;
3822 SmallVector<SDValue, 8> Ops;
3823 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3824 isTailCall, RegsToPass, Ops, NodeTys,
3827 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3828 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3829 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3831 // When performing tail call optimization the callee pops its arguments off
3832 // the stack. Account for this here so these bytes can be pushed back on in
3833 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3834 int BytesCalleePops =
3835 (CallConv == CallingConv::Fast &&
3836 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3838 // Add a register mask operand representing the call-preserved registers.
3839 const TargetRegisterInfo *TRI =
3840 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3841 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3842 assert(Mask && "Missing call preserved mask for calling convention");
3843 Ops.push_back(DAG.getRegisterMask(Mask));
3845 if (InFlag.getNode())
3846 Ops.push_back(InFlag);
3850 assert(((Callee.getOpcode() == ISD::Register &&
3851 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3852 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3853 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3854 isa<ConstantSDNode>(Callee)) &&
3855 "Expecting an global address, external symbol, absolute value or register");
3857 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3860 // Add a NOP immediately after the branch instruction when using the 64-bit
3861 // SVR4 ABI. At link time, if caller and callee are in a different module and
3862 // thus have a different TOC, the call will be replaced with a call to a stub
3863 // function which saves the current TOC, loads the TOC of the callee and
3864 // branches to the callee. The NOP will be replaced with a load instruction
3865 // which restores the TOC of the caller from the TOC save slot of the current
3866 // stack frame. If caller and callee belong to the same module (and have the
3867 // same TOC), the NOP will remain unchanged.
3869 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3870 if (CallOpc == PPCISD::BCTRL) {
3871 // This is a call through a function pointer.
3872 // Restore the caller TOC from the save area into R2.
3873 // See PrepareCall() for more information about calls through function
3874 // pointers in the 64-bit SVR4 ABI.
3875 // We are using a target-specific load with r2 hard coded, because the
3876 // result of a target-independent load would never go directly into r2,
3877 // since r2 is a reserved register (which prevents the register allocator
3878 // from allocating it), resulting in an additional register being
3879 // allocated and an unnecessary move instruction being generated.
3880 CallOpc = PPCISD::BCTRL_LOAD_TOC;
3882 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3883 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3884 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3885 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3886 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3888 // The address needs to go after the chain input but before the flag (or
3889 // any other variadic arguments).
3890 Ops.insert(std::next(Ops.begin()), AddTOC);
3891 } else if ((CallOpc == PPCISD::CALL) &&
3892 (!isLocalCall(Callee) ||
3893 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3894 // Otherwise insert NOP for non-local calls.
3895 CallOpc = PPCISD::CALL_NOP;
3896 } else if (CallOpc == PPCISD::CALL_TLS)
3897 // For 64-bit SVR4, TLS calls are always non-local.
3898 CallOpc = PPCISD::CALL_NOP_TLS;
3901 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3902 InFlag = Chain.getValue(1);
3904 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3905 DAG.getIntPtrConstant(BytesCalleePops, true),
3908 InFlag = Chain.getValue(1);
3910 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3911 Ins, dl, DAG, InVals);
3915 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3916 SmallVectorImpl<SDValue> &InVals) const {
3917 SelectionDAG &DAG = CLI.DAG;
3919 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3920 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3921 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3922 SDValue Chain = CLI.Chain;
3923 SDValue Callee = CLI.Callee;
3924 bool &isTailCall = CLI.IsTailCall;
3925 CallingConv::ID CallConv = CLI.CallConv;
3926 bool isVarArg = CLI.IsVarArg;
3929 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3932 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3933 report_fatal_error("failed to perform tail call elimination on a call "
3934 "site marked musttail");
3936 if (Subtarget.isSVR4ABI()) {
3937 if (Subtarget.isPPC64())
3938 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3939 isTailCall, Outs, OutVals, Ins,
3942 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3943 isTailCall, Outs, OutVals, Ins,
3947 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3948 isTailCall, Outs, OutVals, Ins,
3953 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3954 CallingConv::ID CallConv, bool isVarArg,
3956 const SmallVectorImpl<ISD::OutputArg> &Outs,
3957 const SmallVectorImpl<SDValue> &OutVals,
3958 const SmallVectorImpl<ISD::InputArg> &Ins,
3959 SDLoc dl, SelectionDAG &DAG,
3960 SmallVectorImpl<SDValue> &InVals) const {
3961 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3962 // of the 32-bit SVR4 ABI stack frame layout.
3964 assert((CallConv == CallingConv::C ||
3965 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3967 unsigned PtrByteSize = 4;
3969 MachineFunction &MF = DAG.getMachineFunction();
3971 // Mark this function as potentially containing a function that contains a
3972 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3973 // and restoring the callers stack pointer in this functions epilog. This is
3974 // done because by tail calling the called function might overwrite the value
3975 // in this function's (MF) stack pointer stack slot 0(SP).
3976 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3977 CallConv == CallingConv::Fast)
3978 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3980 // Count how many bytes are to be pushed on the stack, including the linkage
3981 // area, parameter list area and the part of the local variable space which
3982 // contains copies of aggregates which are passed by value.
3984 // Assign locations to all of the outgoing arguments.
3985 SmallVector<CCValAssign, 16> ArgLocs;
3986 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3989 // Reserve space for the linkage area on the stack.
3990 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
3994 // Handle fixed and variable vector arguments differently.
3995 // Fixed vector arguments go into registers as long as registers are
3996 // available. Variable vector arguments always go into memory.
3997 unsigned NumArgs = Outs.size();
3999 for (unsigned i = 0; i != NumArgs; ++i) {
4000 MVT ArgVT = Outs[i].VT;
4001 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4004 if (Outs[i].IsFixed) {
4005 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4008 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4014 errs() << "Call operand #" << i << " has unhandled type "
4015 << EVT(ArgVT).getEVTString() << "\n";
4017 llvm_unreachable(nullptr);
4021 // All arguments are treated the same.
4022 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4025 // Assign locations to all of the outgoing aggregate by value arguments.
4026 SmallVector<CCValAssign, 16> ByValArgLocs;
4027 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4028 ByValArgLocs, *DAG.getContext());
4030 // Reserve stack space for the allocations in CCInfo.
4031 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4033 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4035 // Size of the linkage area, parameter list area and the part of the local
4036 // space variable where copies of aggregates which are passed by value are
4038 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4040 // Calculate by how many bytes the stack has to be adjusted in case of tail
4041 // call optimization.
4042 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4044 // Adjust the stack pointer for the new arguments...
4045 // These operations are automatically eliminated by the prolog/epilog pass
4046 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4048 SDValue CallSeqStart = Chain;
4050 // Load the return address and frame pointer so it can be moved somewhere else
4053 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4056 // Set up a copy of the stack pointer for use loading and storing any
4057 // arguments that may not fit in the registers available for argument
4059 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4061 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4062 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4063 SmallVector<SDValue, 8> MemOpChains;
4065 bool seenFloatArg = false;
4066 // Walk the register/memloc assignments, inserting copies/loads.
4067 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4070 CCValAssign &VA = ArgLocs[i];
4071 SDValue Arg = OutVals[i];
4072 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4074 if (Flags.isByVal()) {
4075 // Argument is an aggregate which is passed by value, thus we need to
4076 // create a copy of it in the local variable space of the current stack
4077 // frame (which is the stack frame of the caller) and pass the address of
4078 // this copy to the callee.
4079 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4080 CCValAssign &ByValVA = ByValArgLocs[j++];
4081 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4083 // Memory reserved in the local variable space of the callers stack frame.
4084 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4086 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4087 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4089 // Create a copy of the argument in the local area of the current
4091 SDValue MemcpyCall =
4092 CreateCopyOfByValArgument(Arg, PtrOff,
4093 CallSeqStart.getNode()->getOperand(0),
4096 // This must go outside the CALLSEQ_START..END.
4097 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4098 CallSeqStart.getNode()->getOperand(1),
4100 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4101 NewCallSeqStart.getNode());
4102 Chain = CallSeqStart = NewCallSeqStart;
4104 // Pass the address of the aggregate copy on the stack either in a
4105 // physical register or in the parameter list area of the current stack
4106 // frame to the callee.
4110 if (VA.isRegLoc()) {
4111 if (Arg.getValueType() == MVT::i1)
4112 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4114 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4115 // Put argument in a physical register.
4116 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4118 // Put argument in the parameter list area of the current stack frame.
4119 assert(VA.isMemLoc());
4120 unsigned LocMemOffset = VA.getLocMemOffset();
4123 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4124 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4126 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4127 MachinePointerInfo(),
4130 // Calculate and remember argument location.
4131 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4137 if (!MemOpChains.empty())
4138 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4140 // Build a sequence of copy-to-reg nodes chained together with token chain
4141 // and flag operands which copy the outgoing args into the appropriate regs.
4143 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4144 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4145 RegsToPass[i].second, InFlag);
4146 InFlag = Chain.getValue(1);
4149 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4152 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4153 SDValue Ops[] = { Chain, InFlag };
4155 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4156 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4158 InFlag = Chain.getValue(1);
4162 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4163 false, TailCallArguments);
4165 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4166 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4170 // Copy an argument into memory, being careful to do this outside the
4171 // call sequence for the call to which the argument belongs.
4173 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4174 SDValue CallSeqStart,
4175 ISD::ArgFlagsTy Flags,
4178 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4179 CallSeqStart.getNode()->getOperand(0),
4181 // The MEMCPY must go outside the CALLSEQ_START..END.
4182 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4183 CallSeqStart.getNode()->getOperand(1),
4185 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4186 NewCallSeqStart.getNode());
4187 return NewCallSeqStart;
4191 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4192 CallingConv::ID CallConv, bool isVarArg,
4194 const SmallVectorImpl<ISD::OutputArg> &Outs,
4195 const SmallVectorImpl<SDValue> &OutVals,
4196 const SmallVectorImpl<ISD::InputArg> &Ins,
4197 SDLoc dl, SelectionDAG &DAG,
4198 SmallVectorImpl<SDValue> &InVals) const {
4200 bool isELFv2ABI = Subtarget.isELFv2ABI();
4201 bool isLittleEndian = Subtarget.isLittleEndian();
4202 unsigned NumOps = Outs.size();
4204 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4205 unsigned PtrByteSize = 8;
4207 MachineFunction &MF = DAG.getMachineFunction();
4209 // Mark this function as potentially containing a function that contains a
4210 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4211 // and restoring the callers stack pointer in this functions epilog. This is
4212 // done because by tail calling the called function might overwrite the value
4213 // in this function's (MF) stack pointer stack slot 0(SP).
4214 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4215 CallConv == CallingConv::Fast)
4216 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4218 // Count how many bytes are to be pushed on the stack, including the linkage
4219 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4220 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4221 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4222 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4224 unsigned NumBytes = LinkageSize;
4226 // Add up all the space actually used.
4227 for (unsigned i = 0; i != NumOps; ++i) {
4228 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4229 EVT ArgVT = Outs[i].VT;
4230 EVT OrigVT = Outs[i].ArgVT;
4232 /* Respect alignment of argument on the stack. */
4234 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4235 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4237 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4238 if (Flags.isInConsecutiveRegsLast())
4239 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4242 unsigned NumBytesActuallyUsed = NumBytes;
4244 // The prolog code of the callee may store up to 8 GPR argument registers to
4245 // the stack, allowing va_start to index over them in memory if its varargs.
4246 // Because we cannot tell if this is needed on the caller side, we have to
4247 // conservatively assume that it is needed. As such, make sure we have at
4248 // least enough stack space for the caller to store the 8 GPRs.
4249 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4250 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4252 // Tail call needs the stack to be aligned.
4253 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4254 CallConv == CallingConv::Fast)
4255 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4257 // Calculate by how many bytes the stack has to be adjusted in case of tail
4258 // call optimization.
4259 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4261 // To protect arguments on the stack from being clobbered in a tail call,
4262 // force all the loads to happen before doing any other lowering.
4264 Chain = DAG.getStackArgumentTokenFactor(Chain);
4266 // Adjust the stack pointer for the new arguments...
4267 // These operations are automatically eliminated by the prolog/epilog pass
4268 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4270 SDValue CallSeqStart = Chain;
4272 // Load the return address and frame pointer so it can be move somewhere else
4275 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4278 // Set up a copy of the stack pointer for use loading and storing any
4279 // arguments that may not fit in the registers available for argument
4281 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4283 // Figure out which arguments are going to go in registers, and which in
4284 // memory. Also, if this is a vararg function, floating point operations
4285 // must be stored to our stack, and loaded into integer regs as well, if
4286 // any integer regs are available for argument passing.
4287 unsigned ArgOffset = LinkageSize;
4288 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
4290 static const MCPhysReg GPR[] = {
4291 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4292 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4294 static const MCPhysReg *FPR = GetFPR();
4296 static const MCPhysReg VR[] = {
4297 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4298 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4300 static const MCPhysReg VSRH[] = {
4301 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4302 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4305 const unsigned NumGPRs = array_lengthof(GPR);
4306 const unsigned NumFPRs = 13;
4307 const unsigned NumVRs = array_lengthof(VR);
4309 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4310 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4312 SmallVector<SDValue, 8> MemOpChains;
4313 for (unsigned i = 0; i != NumOps; ++i) {
4314 SDValue Arg = OutVals[i];
4315 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4316 EVT ArgVT = Outs[i].VT;
4317 EVT OrigVT = Outs[i].ArgVT;
4319 /* Respect alignment of argument on the stack. */
4321 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4322 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4324 /* Compute GPR index associated with argument offset. */
4325 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4326 GPR_idx = std::min(GPR_idx, NumGPRs);
4328 // PtrOff will be used to store the current argument to the stack if a
4329 // register cannot be found for it.
4332 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4334 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4336 // Promote integers to 64-bit values.
4337 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4338 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4339 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4340 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4343 // FIXME memcpy is used way more than necessary. Correctness first.
4344 // Note: "by value" is code for passing a structure by value, not
4346 if (Flags.isByVal()) {
4347 // Note: Size includes alignment padding, so
4348 // struct x { short a; char b; }
4349 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4350 // These are the proper values we need for right-justifying the
4351 // aggregate in a parameter register.
4352 unsigned Size = Flags.getByValSize();
4354 // An empty aggregate parameter takes up no storage and no
4359 // All aggregates smaller than 8 bytes must be passed right-justified.
4360 if (Size==1 || Size==2 || Size==4) {
4361 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4362 if (GPR_idx != NumGPRs) {
4363 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4364 MachinePointerInfo(), VT,
4365 false, false, false, 0);
4366 MemOpChains.push_back(Load.getValue(1));
4367 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4369 ArgOffset += PtrByteSize;
4374 if (GPR_idx == NumGPRs && Size < 8) {
4375 SDValue AddPtr = PtrOff;
4376 if (!isLittleEndian) {
4377 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4378 PtrOff.getValueType());
4379 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4381 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4384 ArgOffset += PtrByteSize;
4387 // Copy entire object into memory. There are cases where gcc-generated
4388 // code assumes it is there, even if it could be put entirely into
4389 // registers. (This is not what the doc says.)
4391 // FIXME: The above statement is likely due to a misunderstanding of the
4392 // documents. All arguments must be copied into the parameter area BY
4393 // THE CALLEE in the event that the callee takes the address of any
4394 // formal argument. That has not yet been implemented. However, it is
4395 // reasonable to use the stack area as a staging area for the register
4398 // Skip this for small aggregates, as we will use the same slot for a
4399 // right-justified copy, below.
4401 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4405 // When a register is available, pass a small aggregate right-justified.
4406 if (Size < 8 && GPR_idx != NumGPRs) {
4407 // The easiest way to get this right-justified in a register
4408 // is to copy the structure into the rightmost portion of a
4409 // local variable slot, then load the whole slot into the
4411 // FIXME: The memcpy seems to produce pretty awful code for
4412 // small aggregates, particularly for packed ones.
4413 // FIXME: It would be preferable to use the slot in the
4414 // parameter save area instead of a new local variable.
4415 SDValue AddPtr = PtrOff;
4416 if (!isLittleEndian) {
4417 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4418 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4420 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4424 // Load the slot into the register.
4425 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4426 MachinePointerInfo(),
4427 false, false, false, 0);
4428 MemOpChains.push_back(Load.getValue(1));
4429 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4431 // Done with this argument.
4432 ArgOffset += PtrByteSize;
4436 // For aggregates larger than PtrByteSize, copy the pieces of the
4437 // object that fit into registers from the parameter save area.
4438 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4439 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4440 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4441 if (GPR_idx != NumGPRs) {
4442 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4443 MachinePointerInfo(),
4444 false, false, false, 0);
4445 MemOpChains.push_back(Load.getValue(1));
4446 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4447 ArgOffset += PtrByteSize;
4449 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4456 switch (Arg.getSimpleValueType().SimpleTy) {
4457 default: llvm_unreachable("Unexpected ValueType for argument!");
4461 // These can be scalar arguments or elements of an integer array type
4462 // passed directly. Clang may use those instead of "byval" aggregate
4463 // types to avoid forcing arguments to memory unnecessarily.
4464 if (GPR_idx != NumGPRs) {
4465 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Arg));
4467 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4468 true, isTailCall, false, MemOpChains,
4469 TailCallArguments, dl);
4471 ArgOffset += PtrByteSize;
4475 // These can be scalar arguments or elements of a float array type
4476 // passed directly. The latter are used to implement ELFv2 homogenous
4477 // float aggregates.
4479 // Named arguments go into FPRs first, and once they overflow, the
4480 // remaining arguments go into GPRs and then the parameter save area.
4481 // Unnamed arguments for vararg functions always go to GPRs and
4482 // then the parameter save area. For now, put all arguments to vararg
4483 // routines always in both locations (FPR *and* GPR or stack slot).
4484 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4486 // First load the argument into the next available FPR.
4487 if (FPR_idx != NumFPRs)
4488 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4490 // Next, load the argument into GPR or stack slot if needed.
4491 if (!NeedGPROrStack)
4493 else if (GPR_idx != NumGPRs) {
4494 // In the non-vararg case, this can only ever happen in the
4495 // presence of f32 array types, since otherwise we never run
4496 // out of FPRs before running out of GPRs.
4499 // Double values are always passed in a single GPR.
4500 if (Arg.getValueType() != MVT::f32) {
4501 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4503 // Non-array float values are extended and passed in a GPR.
4504 } else if (!Flags.isInConsecutiveRegs()) {
4505 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4506 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4508 // If we have an array of floats, we collect every odd element
4509 // together with its predecessor into one GPR.
4510 } else if (ArgOffset % PtrByteSize != 0) {
4512 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4513 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4514 if (!isLittleEndian)
4516 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4518 // The final element, if even, goes into the first half of a GPR.
4519 } else if (Flags.isInConsecutiveRegsLast()) {
4520 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4521 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4522 if (!isLittleEndian)
4523 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4524 DAG.getConstant(32, MVT::i32));
4526 // Non-final even elements are skipped; they will be handled
4527 // together the with subsequent argument on the next go-around.
4531 if (ArgVal.getNode())
4532 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], ArgVal));
4534 // Single-precision floating-point values are mapped to the
4535 // second (rightmost) word of the stack doubleword.
4536 if (Arg.getValueType() == MVT::f32 &&
4537 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4538 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4539 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4542 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4543 true, isTailCall, false, MemOpChains,
4544 TailCallArguments, dl);
4546 // When passing an array of floats, the array occupies consecutive
4547 // space in the argument area; only round up to the next doubleword
4548 // at the end of the array. Otherwise, each float takes 8 bytes.
4549 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4550 Flags.isInConsecutiveRegs()) ? 4 : 8;
4551 if (Flags.isInConsecutiveRegsLast())
4552 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4561 // These can be scalar arguments or elements of a vector array type
4562 // passed directly. The latter are used to implement ELFv2 homogenous
4563 // vector aggregates.
4565 // For a varargs call, named arguments go into VRs or on the stack as
4566 // usual; unnamed arguments always go to the stack or the corresponding
4567 // GPRs when within range. For now, we always put the value in both
4568 // locations (or even all three).
4570 // We could elide this store in the case where the object fits
4571 // entirely in R registers. Maybe later.
4572 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4573 MachinePointerInfo(), false, false, 0);
4574 MemOpChains.push_back(Store);
4575 if (VR_idx != NumVRs) {
4576 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4577 MachinePointerInfo(),
4578 false, false, false, 0);
4579 MemOpChains.push_back(Load.getValue(1));
4581 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4582 Arg.getSimpleValueType() == MVT::v2i64) ?
4583 VSRH[VR_idx] : VR[VR_idx];
4586 RegsToPass.push_back(std::make_pair(VReg, Load));
4589 for (unsigned i=0; i<16; i+=PtrByteSize) {
4590 if (GPR_idx == NumGPRs)
4592 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4593 DAG.getConstant(i, PtrVT));
4594 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4595 false, false, false, 0);
4596 MemOpChains.push_back(Load.getValue(1));
4597 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4602 // Non-varargs Altivec params go into VRs or on the stack.
4603 if (VR_idx != NumVRs) {
4604 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4605 Arg.getSimpleValueType() == MVT::v2i64) ?
4606 VSRH[VR_idx] : VR[VR_idx];
4609 RegsToPass.push_back(std::make_pair(VReg, Arg));
4611 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4612 true, isTailCall, true, MemOpChains,
4613 TailCallArguments, dl);
4620 assert(NumBytesActuallyUsed == ArgOffset);
4621 (void)NumBytesActuallyUsed;
4623 if (!MemOpChains.empty())
4624 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4626 // Check if this is an indirect call (MTCTR/BCTRL).
4627 // See PrepareCall() for more information about calls through function
4628 // pointers in the 64-bit SVR4 ABI.
4630 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4631 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4632 // Load r2 into a virtual register and store it to the TOC save area.
4633 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4634 // TOC save area offset.
4635 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4636 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4637 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4638 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4640 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4641 // This does not mean the MTCTR instruction must use R12; it's easier
4642 // to model this as an extra parameter, so do that.
4644 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4647 // Build a sequence of copy-to-reg nodes chained together with token chain
4648 // and flag operands which copy the outgoing args into the appropriate regs.
4650 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4651 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4652 RegsToPass[i].second, InFlag);
4653 InFlag = Chain.getValue(1);
4657 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4658 FPOp, true, TailCallArguments);
4660 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4661 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4666 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4667 CallingConv::ID CallConv, bool isVarArg,
4669 const SmallVectorImpl<ISD::OutputArg> &Outs,
4670 const SmallVectorImpl<SDValue> &OutVals,
4671 const SmallVectorImpl<ISD::InputArg> &Ins,
4672 SDLoc dl, SelectionDAG &DAG,
4673 SmallVectorImpl<SDValue> &InVals) const {
4675 unsigned NumOps = Outs.size();
4677 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4678 bool isPPC64 = PtrVT == MVT::i64;
4679 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4681 MachineFunction &MF = DAG.getMachineFunction();
4683 // Mark this function as potentially containing a function that contains a
4684 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4685 // and restoring the callers stack pointer in this functions epilog. This is
4686 // done because by tail calling the called function might overwrite the value
4687 // in this function's (MF) stack pointer stack slot 0(SP).
4688 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4689 CallConv == CallingConv::Fast)
4690 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4692 // Count how many bytes are to be pushed on the stack, including the linkage
4693 // area, and parameter passing area. We start with 24/48 bytes, which is
4694 // prereserved space for [SP][CR][LR][3 x unused].
4695 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4697 unsigned NumBytes = LinkageSize;
4699 // Add up all the space actually used.
4700 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4701 // they all go in registers, but we must reserve stack space for them for
4702 // possible use by the caller. In varargs or 64-bit calls, parameters are
4703 // assigned stack space in order, with padding so Altivec parameters are
4705 unsigned nAltivecParamsAtEnd = 0;
4706 for (unsigned i = 0; i != NumOps; ++i) {
4707 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4708 EVT ArgVT = Outs[i].VT;
4709 // Varargs Altivec parameters are padded to a 16 byte boundary.
4710 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4711 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4712 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4713 if (!isVarArg && !isPPC64) {
4714 // Non-varargs Altivec parameters go after all the non-Altivec
4715 // parameters; handle those later so we know how much padding we need.
4716 nAltivecParamsAtEnd++;
4719 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4720 NumBytes = ((NumBytes+15)/16)*16;
4722 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4725 // Allow for Altivec parameters at the end, if needed.
4726 if (nAltivecParamsAtEnd) {
4727 NumBytes = ((NumBytes+15)/16)*16;
4728 NumBytes += 16*nAltivecParamsAtEnd;
4731 // The prolog code of the callee may store up to 8 GPR argument registers to
4732 // the stack, allowing va_start to index over them in memory if its varargs.
4733 // Because we cannot tell if this is needed on the caller side, we have to
4734 // conservatively assume that it is needed. As such, make sure we have at
4735 // least enough stack space for the caller to store the 8 GPRs.
4736 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4738 // Tail call needs the stack to be aligned.
4739 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4740 CallConv == CallingConv::Fast)
4741 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4743 // Calculate by how many bytes the stack has to be adjusted in case of tail
4744 // call optimization.
4745 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4747 // To protect arguments on the stack from being clobbered in a tail call,
4748 // force all the loads to happen before doing any other lowering.
4750 Chain = DAG.getStackArgumentTokenFactor(Chain);
4752 // Adjust the stack pointer for the new arguments...
4753 // These operations are automatically eliminated by the prolog/epilog pass
4754 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4756 SDValue CallSeqStart = Chain;
4758 // Load the return address and frame pointer so it can be move somewhere else
4761 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4764 // Set up a copy of the stack pointer for use loading and storing any
4765 // arguments that may not fit in the registers available for argument
4769 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4771 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4773 // Figure out which arguments are going to go in registers, and which in
4774 // memory. Also, if this is a vararg function, floating point operations
4775 // must be stored to our stack, and loaded into integer regs as well, if
4776 // any integer regs are available for argument passing.
4777 unsigned ArgOffset = LinkageSize;
4778 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4780 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4781 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4782 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4784 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4785 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4786 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4788 static const MCPhysReg *FPR = GetFPR();
4790 static const MCPhysReg VR[] = {
4791 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4792 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4794 const unsigned NumGPRs = array_lengthof(GPR_32);
4795 const unsigned NumFPRs = 13;
4796 const unsigned NumVRs = array_lengthof(VR);
4798 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4800 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4801 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4803 SmallVector<SDValue, 8> MemOpChains;
4804 for (unsigned i = 0; i != NumOps; ++i) {
4805 SDValue Arg = OutVals[i];
4806 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4808 // PtrOff will be used to store the current argument to the stack if a
4809 // register cannot be found for it.
4812 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4814 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4816 // On PPC64, promote integers to 64-bit values.
4817 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4818 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4819 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4820 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4823 // FIXME memcpy is used way more than necessary. Correctness first.
4824 // Note: "by value" is code for passing a structure by value, not
4826 if (Flags.isByVal()) {
4827 unsigned Size = Flags.getByValSize();
4828 // Very small objects are passed right-justified. Everything else is
4829 // passed left-justified.
4830 if (Size==1 || Size==2) {
4831 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4832 if (GPR_idx != NumGPRs) {
4833 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4834 MachinePointerInfo(), VT,
4835 false, false, false, 0);
4836 MemOpChains.push_back(Load.getValue(1));
4837 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4839 ArgOffset += PtrByteSize;
4841 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4842 PtrOff.getValueType());
4843 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4844 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4847 ArgOffset += PtrByteSize;
4851 // Copy entire object into memory. There are cases where gcc-generated
4852 // code assumes it is there, even if it could be put entirely into
4853 // registers. (This is not what the doc says.)
4854 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4858 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4859 // copy the pieces of the object that fit into registers from the
4860 // parameter save area.
4861 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4862 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4863 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4864 if (GPR_idx != NumGPRs) {
4865 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4866 MachinePointerInfo(),
4867 false, false, false, 0);
4868 MemOpChains.push_back(Load.getValue(1));
4869 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4870 ArgOffset += PtrByteSize;
4872 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4879 switch (Arg.getSimpleValueType().SimpleTy) {
4880 default: llvm_unreachable("Unexpected ValueType for argument!");
4884 if (GPR_idx != NumGPRs) {
4885 if (Arg.getValueType() == MVT::i1)
4886 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4888 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4890 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4891 isPPC64, isTailCall, false, MemOpChains,
4892 TailCallArguments, dl);
4894 ArgOffset += PtrByteSize;
4898 if (FPR_idx != NumFPRs) {
4899 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4902 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4903 MachinePointerInfo(), false, false, 0);
4904 MemOpChains.push_back(Store);
4906 // Float varargs are always shadowed in available integer registers
4907 if (GPR_idx != NumGPRs) {
4908 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4909 MachinePointerInfo(), false, false,
4911 MemOpChains.push_back(Load.getValue(1));
4912 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4914 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4915 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4916 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4917 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4918 MachinePointerInfo(),
4919 false, false, false, 0);
4920 MemOpChains.push_back(Load.getValue(1));
4921 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4924 // If we have any FPRs remaining, we may also have GPRs remaining.
4925 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4927 if (GPR_idx != NumGPRs)
4929 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4930 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4934 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4935 isPPC64, isTailCall, false, MemOpChains,
4936 TailCallArguments, dl);
4940 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4947 // These go aligned on the stack, or in the corresponding R registers
4948 // when within range. The Darwin PPC ABI doc claims they also go in
4949 // V registers; in fact gcc does this only for arguments that are
4950 // prototyped, not for those that match the ... We do it for all
4951 // arguments, seems to work.
4952 while (ArgOffset % 16 !=0) {
4953 ArgOffset += PtrByteSize;
4954 if (GPR_idx != NumGPRs)
4957 // We could elide this store in the case where the object fits
4958 // entirely in R registers. Maybe later.
4959 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4960 DAG.getConstant(ArgOffset, PtrVT));
4961 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4962 MachinePointerInfo(), false, false, 0);
4963 MemOpChains.push_back(Store);
4964 if (VR_idx != NumVRs) {
4965 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4966 MachinePointerInfo(),
4967 false, false, false, 0);
4968 MemOpChains.push_back(Load.getValue(1));
4969 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4972 for (unsigned i=0; i<16; i+=PtrByteSize) {
4973 if (GPR_idx == NumGPRs)
4975 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4976 DAG.getConstant(i, PtrVT));
4977 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4978 false, false, false, 0);
4979 MemOpChains.push_back(Load.getValue(1));
4980 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4985 // Non-varargs Altivec params generally go in registers, but have
4986 // stack space allocated at the end.
4987 if (VR_idx != NumVRs) {
4988 // Doesn't have GPR space allocated.
4989 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4990 } else if (nAltivecParamsAtEnd==0) {
4991 // We are emitting Altivec params in order.
4992 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4993 isPPC64, isTailCall, true, MemOpChains,
4994 TailCallArguments, dl);
5000 // If all Altivec parameters fit in registers, as they usually do,
5001 // they get stack space following the non-Altivec parameters. We
5002 // don't track this here because nobody below needs it.
5003 // If there are more Altivec parameters than fit in registers emit
5005 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5007 // Offset is aligned; skip 1st 12 params which go in V registers.
5008 ArgOffset = ((ArgOffset+15)/16)*16;
5010 for (unsigned i = 0; i != NumOps; ++i) {
5011 SDValue Arg = OutVals[i];
5012 EVT ArgType = Outs[i].VT;
5013 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5014 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5017 // We are emitting Altivec params in order.
5018 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5019 isPPC64, isTailCall, true, MemOpChains,
5020 TailCallArguments, dl);
5027 if (!MemOpChains.empty())
5028 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5030 // On Darwin, R12 must contain the address of an indirect callee. This does
5031 // not mean the MTCTR instruction must use R12; it's easier to model this as
5032 // an extra parameter, so do that.
5034 !dyn_cast<GlobalAddressSDNode>(Callee) &&
5035 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
5036 !isBLACompatibleAddress(Callee, DAG))
5037 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5038 PPC::R12), Callee));
5040 // Build a sequence of copy-to-reg nodes chained together with token chain
5041 // and flag operands which copy the outgoing args into the appropriate regs.
5043 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5044 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5045 RegsToPass[i].second, InFlag);
5046 InFlag = Chain.getValue(1);
5050 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5051 FPOp, true, TailCallArguments);
5053 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
5054 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
5059 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5060 MachineFunction &MF, bool isVarArg,
5061 const SmallVectorImpl<ISD::OutputArg> &Outs,
5062 LLVMContext &Context) const {
5063 SmallVector<CCValAssign, 16> RVLocs;
5064 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5065 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5069 PPCTargetLowering::LowerReturn(SDValue Chain,
5070 CallingConv::ID CallConv, bool isVarArg,
5071 const SmallVectorImpl<ISD::OutputArg> &Outs,
5072 const SmallVectorImpl<SDValue> &OutVals,
5073 SDLoc dl, SelectionDAG &DAG) const {
5075 SmallVector<CCValAssign, 16> RVLocs;
5076 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5078 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5081 SmallVector<SDValue, 4> RetOps(1, Chain);
5083 // Copy the result values into the output registers.
5084 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5085 CCValAssign &VA = RVLocs[i];
5086 assert(VA.isRegLoc() && "Can only return in registers!");
5088 SDValue Arg = OutVals[i];
5090 switch (VA.getLocInfo()) {
5091 default: llvm_unreachable("Unknown loc info!");
5092 case CCValAssign::Full: break;
5093 case CCValAssign::AExt:
5094 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5096 case CCValAssign::ZExt:
5097 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5099 case CCValAssign::SExt:
5100 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5104 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5105 Flag = Chain.getValue(1);
5106 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5109 RetOps[0] = Chain; // Update chain.
5111 // Add the flag if we have it.
5113 RetOps.push_back(Flag);
5115 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5118 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5119 const PPCSubtarget &Subtarget) const {
5120 // When we pop the dynamic allocation we need to restore the SP link.
5123 // Get the corect type for pointers.
5124 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5126 // Construct the stack pointer operand.
5127 bool isPPC64 = Subtarget.isPPC64();
5128 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5129 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5131 // Get the operands for the STACKRESTORE.
5132 SDValue Chain = Op.getOperand(0);
5133 SDValue SaveSP = Op.getOperand(1);
5135 // Load the old link SP.
5136 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5137 MachinePointerInfo(),
5138 false, false, false, 0);
5140 // Restore the stack pointer.
5141 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5143 // Store the old link SP.
5144 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5151 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5152 MachineFunction &MF = DAG.getMachineFunction();
5153 bool isPPC64 = Subtarget.isPPC64();
5154 bool isDarwinABI = Subtarget.isDarwinABI();
5155 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5157 // Get current frame pointer save index. The users of this index will be
5158 // primarily DYNALLOC instructions.
5159 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5160 int RASI = FI->getReturnAddrSaveIndex();
5162 // If the frame pointer save index hasn't been defined yet.
5164 // Find out what the fix offset of the frame pointer save area.
5165 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5166 // Allocate the frame index for frame pointer save area.
5167 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5169 FI->setReturnAddrSaveIndex(RASI);
5171 return DAG.getFrameIndex(RASI, PtrVT);
5175 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5176 MachineFunction &MF = DAG.getMachineFunction();
5177 bool isPPC64 = Subtarget.isPPC64();
5178 bool isDarwinABI = Subtarget.isDarwinABI();
5179 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5181 // Get current frame pointer save index. The users of this index will be
5182 // primarily DYNALLOC instructions.
5183 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5184 int FPSI = FI->getFramePointerSaveIndex();
5186 // If the frame pointer save index hasn't been defined yet.
5188 // Find out what the fix offset of the frame pointer save area.
5189 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5192 // Allocate the frame index for frame pointer save area.
5193 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5195 FI->setFramePointerSaveIndex(FPSI);
5197 return DAG.getFrameIndex(FPSI, PtrVT);
5200 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5202 const PPCSubtarget &Subtarget) const {
5204 SDValue Chain = Op.getOperand(0);
5205 SDValue Size = Op.getOperand(1);
5208 // Get the corect type for pointers.
5209 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5211 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5212 DAG.getConstant(0, PtrVT), Size);
5213 // Construct a node for the frame pointer save index.
5214 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5215 // Build a DYNALLOC node.
5216 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5217 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5218 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5221 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5222 SelectionDAG &DAG) const {
5224 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5225 DAG.getVTList(MVT::i32, MVT::Other),
5226 Op.getOperand(0), Op.getOperand(1));
5229 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5230 SelectionDAG &DAG) const {
5232 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5233 Op.getOperand(0), Op.getOperand(1));
5236 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5237 assert(Op.getValueType() == MVT::i1 &&
5238 "Custom lowering only for i1 loads");
5240 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5243 LoadSDNode *LD = cast<LoadSDNode>(Op);
5245 SDValue Chain = LD->getChain();
5246 SDValue BasePtr = LD->getBasePtr();
5247 MachineMemOperand *MMO = LD->getMemOperand();
5249 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5250 BasePtr, MVT::i8, MMO);
5251 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5253 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5254 return DAG.getMergeValues(Ops, dl);
5257 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5258 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5259 "Custom lowering only for i1 stores");
5261 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5264 StoreSDNode *ST = cast<StoreSDNode>(Op);
5266 SDValue Chain = ST->getChain();
5267 SDValue BasePtr = ST->getBasePtr();
5268 SDValue Value = ST->getValue();
5269 MachineMemOperand *MMO = ST->getMemOperand();
5271 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5272 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5275 // FIXME: Remove this once the ANDI glue bug is fixed:
5276 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5277 assert(Op.getValueType() == MVT::i1 &&
5278 "Custom lowering only for i1 results");
5281 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5285 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5287 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5288 // Not FP? Not a fsel.
5289 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5290 !Op.getOperand(2).getValueType().isFloatingPoint())
5293 // We might be able to do better than this under some circumstances, but in
5294 // general, fsel-based lowering of select is a finite-math-only optimization.
5295 // For more information, see section F.3 of the 2.06 ISA specification.
5296 if (!DAG.getTarget().Options.NoInfsFPMath ||
5297 !DAG.getTarget().Options.NoNaNsFPMath)
5300 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5302 EVT ResVT = Op.getValueType();
5303 EVT CmpVT = Op.getOperand(0).getValueType();
5304 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5305 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5308 // If the RHS of the comparison is a 0.0, we don't need to do the
5309 // subtraction at all.
5311 if (isFloatingPointZero(RHS))
5313 default: break; // SETUO etc aren't handled by fsel.
5317 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5318 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5319 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5320 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5321 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5322 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5323 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5326 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5329 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5330 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5331 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5334 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5337 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5338 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5339 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5340 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5345 default: break; // SETUO etc aren't handled by fsel.
5349 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5350 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5351 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5352 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5353 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5354 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5355 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5356 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5359 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5360 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5361 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5362 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5365 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5366 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5367 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5368 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5371 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5372 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5373 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5374 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5377 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5378 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5379 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5380 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5385 // FIXME: Split this code up when LegalizeDAGTypes lands.
5386 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5388 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5389 SDValue Src = Op.getOperand(0);
5390 if (Src.getValueType() == MVT::f32)
5391 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5394 switch (Op.getSimpleValueType().SimpleTy) {
5395 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5397 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5398 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5403 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5404 "i64 FP_TO_UINT is supported only with FPCVT");
5405 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5411 // Convert the FP value to an int value through memory.
5412 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5413 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5414 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5415 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5416 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5418 // Emit a store to the stack slot.
5421 MachineFunction &MF = DAG.getMachineFunction();
5422 MachineMemOperand *MMO =
5423 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5424 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5425 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5426 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5428 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5429 MPI, false, false, 0);
5431 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5433 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5434 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5435 DAG.getConstant(4, FIPtr.getValueType()));
5436 MPI = MachinePointerInfo();
5439 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5440 false, false, false, 0);
5443 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5444 SelectionDAG &DAG) const {
5446 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5447 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5450 if (Op.getOperand(0).getValueType() == MVT::i1)
5451 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5452 DAG.getConstantFP(1.0, Op.getValueType()),
5453 DAG.getConstantFP(0.0, Op.getValueType()));
5455 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5456 "UINT_TO_FP is supported only with FPCVT");
5458 // If we have FCFIDS, then use it when converting to single-precision.
5459 // Otherwise, convert to double-precision and then round.
5460 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5461 (Op.getOpcode() == ISD::UINT_TO_FP ?
5462 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5463 (Op.getOpcode() == ISD::UINT_TO_FP ?
5464 PPCISD::FCFIDU : PPCISD::FCFID);
5465 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5466 MVT::f32 : MVT::f64;
5468 if (Op.getOperand(0).getValueType() == MVT::i64) {
5469 SDValue SINT = Op.getOperand(0);
5470 // When converting to single-precision, we actually need to convert
5471 // to double-precision first and then round to single-precision.
5472 // To avoid double-rounding effects during that operation, we have
5473 // to prepare the input operand. Bits that might be truncated when
5474 // converting to double-precision are replaced by a bit that won't
5475 // be lost at this stage, but is below the single-precision rounding
5478 // However, if -enable-unsafe-fp-math is in effect, accept double
5479 // rounding to avoid the extra overhead.
5480 if (Op.getValueType() == MVT::f32 &&
5481 !Subtarget.hasFPCVT() &&
5482 !DAG.getTarget().Options.UnsafeFPMath) {
5484 // Twiddle input to make sure the low 11 bits are zero. (If this
5485 // is the case, we are guaranteed the value will fit into the 53 bit
5486 // mantissa of an IEEE double-precision value without rounding.)
5487 // If any of those low 11 bits were not zero originally, make sure
5488 // bit 12 (value 2048) is set instead, so that the final rounding
5489 // to single-precision gets the correct result.
5490 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5491 SINT, DAG.getConstant(2047, MVT::i64));
5492 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5493 Round, DAG.getConstant(2047, MVT::i64));
5494 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5495 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5496 Round, DAG.getConstant(-2048, MVT::i64));
5498 // However, we cannot use that value unconditionally: if the magnitude
5499 // of the input value is small, the bit-twiddling we did above might
5500 // end up visibly changing the output. Fortunately, in that case, we
5501 // don't need to twiddle bits since the original input will convert
5502 // exactly to double-precision floating-point already. Therefore,
5503 // construct a conditional to use the original value if the top 11
5504 // bits are all sign-bit copies, and use the rounded value computed
5506 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5507 SINT, DAG.getConstant(53, MVT::i32));
5508 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5509 Cond, DAG.getConstant(1, MVT::i64));
5510 Cond = DAG.getSetCC(dl, MVT::i32,
5511 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5513 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5516 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5517 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5519 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5520 FP = DAG.getNode(ISD::FP_ROUND, dl,
5521 MVT::f32, FP, DAG.getIntPtrConstant(0));
5525 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5526 "Unhandled INT_TO_FP type in custom expander!");
5527 // Since we only generate this in 64-bit mode, we can take advantage of
5528 // 64-bit registers. In particular, sign extend the input value into the
5529 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5530 // then lfd it and fcfid it.
5531 MachineFunction &MF = DAG.getMachineFunction();
5532 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5533 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5536 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5537 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5538 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5540 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5541 MachinePointerInfo::getFixedStack(FrameIdx),
5544 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5545 "Expected an i32 store");
5546 MachineMemOperand *MMO =
5547 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5548 MachineMemOperand::MOLoad, 4, 4);
5549 SDValue Ops[] = { Store, FIdx };
5550 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5551 PPCISD::LFIWZX : PPCISD::LFIWAX,
5552 dl, DAG.getVTList(MVT::f64, MVT::Other),
5553 Ops, MVT::i32, MMO);
5555 assert(Subtarget.isPPC64() &&
5556 "i32->FP without LFIWAX supported only on PPC64");
5558 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5559 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5561 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5564 // STD the extended value into the stack slot.
5565 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5566 MachinePointerInfo::getFixedStack(FrameIdx),
5569 // Load the value as a double.
5570 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5571 MachinePointerInfo::getFixedStack(FrameIdx),
5572 false, false, false, 0);
5575 // FCFID it and return it.
5576 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5577 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5578 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5582 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5583 SelectionDAG &DAG) const {
5586 The rounding mode is in bits 30:31 of FPSR, and has the following
5593 FLT_ROUNDS, on the other hand, expects the following:
5600 To perform the conversion, we do:
5601 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5604 MachineFunction &MF = DAG.getMachineFunction();
5605 EVT VT = Op.getValueType();
5606 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5608 // Save FP Control Word to register
5610 MVT::f64, // return register
5611 MVT::Glue // unused in this context
5613 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5615 // Save FP register to stack slot
5616 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5617 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5618 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5619 StackSlot, MachinePointerInfo(), false, false,0);
5621 // Load FP Control Word from low 32 bits of stack slot.
5622 SDValue Four = DAG.getConstant(4, PtrVT);
5623 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5624 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5625 false, false, false, 0);
5627 // Transform as necessary
5629 DAG.getNode(ISD::AND, dl, MVT::i32,
5630 CWD, DAG.getConstant(3, MVT::i32));
5632 DAG.getNode(ISD::SRL, dl, MVT::i32,
5633 DAG.getNode(ISD::AND, dl, MVT::i32,
5634 DAG.getNode(ISD::XOR, dl, MVT::i32,
5635 CWD, DAG.getConstant(3, MVT::i32)),
5636 DAG.getConstant(3, MVT::i32)),
5637 DAG.getConstant(1, MVT::i32));
5640 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5642 return DAG.getNode((VT.getSizeInBits() < 16 ?
5643 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5646 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5647 EVT VT = Op.getValueType();
5648 unsigned BitWidth = VT.getSizeInBits();
5650 assert(Op.getNumOperands() == 3 &&
5651 VT == Op.getOperand(1).getValueType() &&
5654 // Expand into a bunch of logical ops. Note that these ops
5655 // depend on the PPC behavior for oversized shift amounts.
5656 SDValue Lo = Op.getOperand(0);
5657 SDValue Hi = Op.getOperand(1);
5658 SDValue Amt = Op.getOperand(2);
5659 EVT AmtVT = Amt.getValueType();
5661 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5662 DAG.getConstant(BitWidth, AmtVT), Amt);
5663 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5664 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5665 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5666 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5667 DAG.getConstant(-BitWidth, AmtVT));
5668 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5669 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5670 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5671 SDValue OutOps[] = { OutLo, OutHi };
5672 return DAG.getMergeValues(OutOps, dl);
5675 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5676 EVT VT = Op.getValueType();
5678 unsigned BitWidth = VT.getSizeInBits();
5679 assert(Op.getNumOperands() == 3 &&
5680 VT == Op.getOperand(1).getValueType() &&
5683 // Expand into a bunch of logical ops. Note that these ops
5684 // depend on the PPC behavior for oversized shift amounts.
5685 SDValue Lo = Op.getOperand(0);
5686 SDValue Hi = Op.getOperand(1);
5687 SDValue Amt = Op.getOperand(2);
5688 EVT AmtVT = Amt.getValueType();
5690 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5691 DAG.getConstant(BitWidth, AmtVT), Amt);
5692 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5693 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5694 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5695 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5696 DAG.getConstant(-BitWidth, AmtVT));
5697 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5698 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5699 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5700 SDValue OutOps[] = { OutLo, OutHi };
5701 return DAG.getMergeValues(OutOps, dl);
5704 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5706 EVT VT = Op.getValueType();
5707 unsigned BitWidth = VT.getSizeInBits();
5708 assert(Op.getNumOperands() == 3 &&
5709 VT == Op.getOperand(1).getValueType() &&
5712 // Expand into a bunch of logical ops, followed by a select_cc.
5713 SDValue Lo = Op.getOperand(0);
5714 SDValue Hi = Op.getOperand(1);
5715 SDValue Amt = Op.getOperand(2);
5716 EVT AmtVT = Amt.getValueType();
5718 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5719 DAG.getConstant(BitWidth, AmtVT), Amt);
5720 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5721 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5722 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5723 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5724 DAG.getConstant(-BitWidth, AmtVT));
5725 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5726 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5727 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5728 Tmp4, Tmp6, ISD::SETLE);
5729 SDValue OutOps[] = { OutLo, OutHi };
5730 return DAG.getMergeValues(OutOps, dl);
5733 //===----------------------------------------------------------------------===//
5734 // Vector related lowering.
5737 /// BuildSplatI - Build a canonical splati of Val with an element size of
5738 /// SplatSize. Cast the result to VT.
5739 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5740 SelectionDAG &DAG, SDLoc dl) {
5741 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5743 static const EVT VTys[] = { // canonical VT to use for each size.
5744 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5747 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5749 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5753 EVT CanonicalVT = VTys[SplatSize-1];
5755 // Build a canonical splat for this value.
5756 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5757 SmallVector<SDValue, 8> Ops;
5758 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5759 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5760 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5763 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5764 /// specified intrinsic ID.
5765 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5766 SelectionDAG &DAG, SDLoc dl,
5767 EVT DestVT = MVT::Other) {
5768 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5769 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5770 DAG.getConstant(IID, MVT::i32), Op);
5773 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5774 /// specified intrinsic ID.
5775 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5776 SelectionDAG &DAG, SDLoc dl,
5777 EVT DestVT = MVT::Other) {
5778 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5779 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5780 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5783 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5784 /// specified intrinsic ID.
5785 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5786 SDValue Op2, SelectionDAG &DAG,
5787 SDLoc dl, EVT DestVT = MVT::Other) {
5788 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5789 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5790 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5794 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5795 /// amount. The result has the specified value type.
5796 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5797 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5798 // Force LHS/RHS to be the right type.
5799 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5800 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5803 for (unsigned i = 0; i != 16; ++i)
5805 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5806 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5809 // If this is a case we can't handle, return null and let the default
5810 // expansion code take care of it. If we CAN select this case, and if it
5811 // selects to a single instruction, return Op. Otherwise, if we can codegen
5812 // this case more efficiently than a constant pool load, lower it to the
5813 // sequence of ops that should be used.
5814 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5815 SelectionDAG &DAG) const {
5817 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5818 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5820 // Check if this is a splat of a constant value.
5821 APInt APSplatBits, APSplatUndef;
5822 unsigned SplatBitSize;
5824 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5825 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5828 unsigned SplatBits = APSplatBits.getZExtValue();
5829 unsigned SplatUndef = APSplatUndef.getZExtValue();
5830 unsigned SplatSize = SplatBitSize / 8;
5832 // First, handle single instruction cases.
5835 if (SplatBits == 0) {
5836 // Canonicalize all zero vectors to be v4i32.
5837 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5838 SDValue Z = DAG.getConstant(0, MVT::i32);
5839 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5840 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5845 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5846 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5848 if (SextVal >= -16 && SextVal <= 15)
5849 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5852 // Two instruction sequences.
5854 // If this value is in the range [-32,30] and is even, use:
5855 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5856 // If this value is in the range [17,31] and is odd, use:
5857 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5858 // If this value is in the range [-31,-17] and is odd, use:
5859 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5860 // Note the last two are three-instruction sequences.
5861 if (SextVal >= -32 && SextVal <= 31) {
5862 // To avoid having these optimizations undone by constant folding,
5863 // we convert to a pseudo that will be expanded later into one of
5865 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5866 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5867 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5868 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5869 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5870 if (VT == Op.getValueType())
5873 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5876 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5877 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5879 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5880 // Make -1 and vspltisw -1:
5881 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5883 // Make the VSLW intrinsic, computing 0x8000_0000.
5884 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5887 // xor by OnesV to invert it.
5888 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5889 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5892 // The remaining cases assume either big endian element order or
5893 // a splat-size that equates to the element size of the vector
5894 // to be built. An example that doesn't work for little endian is
5895 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5896 // and a vector element size of 16 bits. The code below will
5897 // produce the vector in big endian element order, which for little
5898 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5900 // For now, just avoid these optimizations in that case.
5901 // FIXME: Develop correct optimizations for LE with mismatched
5902 // splat and element sizes.
5904 if (Subtarget.isLittleEndian() &&
5905 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5908 // Check to see if this is a wide variety of vsplti*, binop self cases.
5909 static const signed char SplatCsts[] = {
5910 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5911 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5914 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5915 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5916 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5917 int i = SplatCsts[idx];
5919 // Figure out what shift amount will be used by altivec if shifted by i in
5921 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5923 // vsplti + shl self.
5924 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5925 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5926 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5927 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5928 Intrinsic::ppc_altivec_vslw
5930 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5931 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5934 // vsplti + srl self.
5935 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5936 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5937 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5938 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5939 Intrinsic::ppc_altivec_vsrw
5941 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5942 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5945 // vsplti + sra self.
5946 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5947 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5948 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5949 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5950 Intrinsic::ppc_altivec_vsraw
5952 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5953 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5956 // vsplti + rol self.
5957 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5958 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5959 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5960 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5961 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5962 Intrinsic::ppc_altivec_vrlw
5964 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5965 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5968 // t = vsplti c, result = vsldoi t, t, 1
5969 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5970 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5971 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5973 // t = vsplti c, result = vsldoi t, t, 2
5974 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5975 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5976 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5978 // t = vsplti c, result = vsldoi t, t, 3
5979 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5980 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5981 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5988 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5989 /// the specified operations to build the shuffle.
5990 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5991 SDValue RHS, SelectionDAG &DAG,
5993 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5994 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5995 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5998 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
6010 if (OpNum == OP_COPY) {
6011 if (LHSID == (1*9+2)*9+3) return LHS;
6012 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
6016 SDValue OpLHS, OpRHS;
6017 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
6018 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
6022 default: llvm_unreachable("Unknown i32 permute!");
6024 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
6025 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
6026 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
6027 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
6030 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
6031 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
6032 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
6033 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6036 for (unsigned i = 0; i != 16; ++i)
6037 ShufIdxs[i] = (i&3)+0;
6040 for (unsigned i = 0; i != 16; ++i)
6041 ShufIdxs[i] = (i&3)+4;
6044 for (unsigned i = 0; i != 16; ++i)
6045 ShufIdxs[i] = (i&3)+8;
6048 for (unsigned i = 0; i != 16; ++i)
6049 ShufIdxs[i] = (i&3)+12;
6052 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6054 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6056 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6058 EVT VT = OpLHS.getValueType();
6059 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6060 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6061 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6062 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6065 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6066 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6067 /// return the code it can be lowered into. Worst case, it can always be
6068 /// lowered into a vperm.
6069 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6070 SelectionDAG &DAG) const {
6072 SDValue V1 = Op.getOperand(0);
6073 SDValue V2 = Op.getOperand(1);
6074 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6075 EVT VT = Op.getValueType();
6076 bool isLittleEndian = Subtarget.isLittleEndian();
6078 // Cases that are handled by instructions that take permute immediates
6079 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6080 // selected by the instruction selector.
6081 if (V2.getOpcode() == ISD::UNDEF) {
6082 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6083 PPC::isSplatShuffleMask(SVOp, 2) ||
6084 PPC::isSplatShuffleMask(SVOp, 4) ||
6085 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6086 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6087 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
6088 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6089 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6090 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6091 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6092 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6093 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6098 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6099 // and produce a fixed permutation. If any of these match, do not lower to
6101 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6102 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6103 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6104 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
6105 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6106 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6107 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6108 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6109 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6110 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6113 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6114 // perfect shuffle table to emit an optimal matching sequence.
6115 ArrayRef<int> PermMask = SVOp->getMask();
6117 unsigned PFIndexes[4];
6118 bool isFourElementShuffle = true;
6119 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6120 unsigned EltNo = 8; // Start out undef.
6121 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6122 if (PermMask[i*4+j] < 0)
6123 continue; // Undef, ignore it.
6125 unsigned ByteSource = PermMask[i*4+j];
6126 if ((ByteSource & 3) != j) {
6127 isFourElementShuffle = false;
6132 EltNo = ByteSource/4;
6133 } else if (EltNo != ByteSource/4) {
6134 isFourElementShuffle = false;
6138 PFIndexes[i] = EltNo;
6141 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6142 // perfect shuffle vector to determine if it is cost effective to do this as
6143 // discrete instructions, or whether we should use a vperm.
6144 // For now, we skip this for little endian until such time as we have a
6145 // little-endian perfect shuffle table.
6146 if (isFourElementShuffle && !isLittleEndian) {
6147 // Compute the index in the perfect shuffle table.
6148 unsigned PFTableIndex =
6149 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6151 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6152 unsigned Cost = (PFEntry >> 30);
6154 // Determining when to avoid vperm is tricky. Many things affect the cost
6155 // of vperm, particularly how many times the perm mask needs to be computed.
6156 // For example, if the perm mask can be hoisted out of a loop or is already
6157 // used (perhaps because there are multiple permutes with the same shuffle
6158 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6159 // the loop requires an extra register.
6161 // As a compromise, we only emit discrete instructions if the shuffle can be
6162 // generated in 3 or fewer operations. When we have loop information
6163 // available, if this block is within a loop, we should avoid using vperm
6164 // for 3-operation perms and use a constant pool load instead.
6166 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6169 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6170 // vector that will get spilled to the constant pool.
6171 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6173 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6174 // that it is in input element units, not in bytes. Convert now.
6176 // For little endian, the order of the input vectors is reversed, and
6177 // the permutation mask is complemented with respect to 31. This is
6178 // necessary to produce proper semantics with the big-endian-biased vperm
6180 EVT EltVT = V1.getValueType().getVectorElementType();
6181 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6183 SmallVector<SDValue, 16> ResultMask;
6184 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6185 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6187 for (unsigned j = 0; j != BytesPerElement; ++j)
6189 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6192 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6196 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6199 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6202 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6206 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6207 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6208 /// information about the intrinsic.
6209 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6211 unsigned IntrinsicID =
6212 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6215 switch (IntrinsicID) {
6216 default: return false;
6217 // Comparison predicates.
6218 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6219 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6220 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6221 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6222 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6223 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6224 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6225 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6226 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6227 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6228 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6229 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6230 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6232 // Normal Comparisons.
6233 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6234 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6235 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6236 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6237 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6238 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6239 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6240 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6241 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6242 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6243 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6244 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6245 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6250 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6251 /// lower, do it, otherwise return null.
6252 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6253 SelectionDAG &DAG) const {
6254 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6255 // opcode number of the comparison.
6259 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6260 return SDValue(); // Don't custom lower most intrinsics.
6262 // If this is a non-dot comparison, make the VCMP node and we are done.
6264 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6265 Op.getOperand(1), Op.getOperand(2),
6266 DAG.getConstant(CompareOpc, MVT::i32));
6267 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6270 // Create the PPCISD altivec 'dot' comparison node.
6272 Op.getOperand(2), // LHS
6273 Op.getOperand(3), // RHS
6274 DAG.getConstant(CompareOpc, MVT::i32)
6276 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6277 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6279 // Now that we have the comparison, emit a copy from the CR to a GPR.
6280 // This is flagged to the above dot comparison.
6281 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6282 DAG.getRegister(PPC::CR6, MVT::i32),
6283 CompNode.getValue(1));
6285 // Unpack the result based on how the target uses it.
6286 unsigned BitNo; // Bit # of CR6.
6287 bool InvertBit; // Invert result?
6288 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6289 default: // Can't happen, don't crash on invalid number though.
6290 case 0: // Return the value of the EQ bit of CR6.
6291 BitNo = 0; InvertBit = false;
6293 case 1: // Return the inverted value of the EQ bit of CR6.
6294 BitNo = 0; InvertBit = true;
6296 case 2: // Return the value of the LT bit of CR6.
6297 BitNo = 2; InvertBit = false;
6299 case 3: // Return the inverted value of the LT bit of CR6.
6300 BitNo = 2; InvertBit = true;
6304 // Shift the bit into the low position.
6305 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6306 DAG.getConstant(8-(3-BitNo), MVT::i32));
6308 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6309 DAG.getConstant(1, MVT::i32));
6311 // If we are supposed to, toggle the bit.
6313 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6314 DAG.getConstant(1, MVT::i32));
6318 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6319 SelectionDAG &DAG) const {
6321 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6322 // instructions), but for smaller types, we need to first extend up to v2i32
6323 // before doing going farther.
6324 if (Op.getValueType() == MVT::v2i64) {
6325 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6326 if (ExtVT != MVT::v2i32) {
6327 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6328 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6329 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6330 ExtVT.getVectorElementType(), 4)));
6331 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6332 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6333 DAG.getValueType(MVT::v2i32));
6342 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6343 SelectionDAG &DAG) const {
6345 // Create a stack slot that is 16-byte aligned.
6346 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6347 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6348 EVT PtrVT = getPointerTy();
6349 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6351 // Store the input value into Value#0 of the stack slot.
6352 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6353 Op.getOperand(0), FIdx, MachinePointerInfo(),
6356 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6357 false, false, false, 0);
6360 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6362 if (Op.getValueType() == MVT::v4i32) {
6363 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6365 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6366 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6368 SDValue RHSSwap = // = vrlw RHS, 16
6369 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6371 // Shrinkify inputs to v8i16.
6372 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6373 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6374 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6376 // Low parts multiplied together, generating 32-bit results (we ignore the
6378 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6379 LHS, RHS, DAG, dl, MVT::v4i32);
6381 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6382 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6383 // Shift the high parts up 16 bits.
6384 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6386 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6387 } else if (Op.getValueType() == MVT::v8i16) {
6388 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6390 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6392 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6393 LHS, RHS, Zero, DAG, dl);
6394 } else if (Op.getValueType() == MVT::v16i8) {
6395 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6396 bool isLittleEndian = Subtarget.isLittleEndian();
6398 // Multiply the even 8-bit parts, producing 16-bit sums.
6399 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6400 LHS, RHS, DAG, dl, MVT::v8i16);
6401 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6403 // Multiply the odd 8-bit parts, producing 16-bit sums.
6404 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6405 LHS, RHS, DAG, dl, MVT::v8i16);
6406 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6408 // Merge the results together. Because vmuleub and vmuloub are
6409 // instructions with a big-endian bias, we must reverse the
6410 // element numbering and reverse the meaning of "odd" and "even"
6411 // when generating little endian code.
6413 for (unsigned i = 0; i != 8; ++i) {
6414 if (isLittleEndian) {
6416 Ops[i*2+1] = 2*i+16;
6419 Ops[i*2+1] = 2*i+1+16;
6423 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6425 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6427 llvm_unreachable("Unknown mul to lower!");
6431 /// LowerOperation - Provide custom lowering hooks for some operations.
6433 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6434 switch (Op.getOpcode()) {
6435 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6436 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6437 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6438 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6439 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6440 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6441 case ISD::SETCC: return LowerSETCC(Op, DAG);
6442 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6443 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6445 return LowerVASTART(Op, DAG, Subtarget);
6448 return LowerVAARG(Op, DAG, Subtarget);
6451 return LowerVACOPY(Op, DAG, Subtarget);
6453 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6454 case ISD::DYNAMIC_STACKALLOC:
6455 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6457 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6458 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6460 case ISD::LOAD: return LowerLOAD(Op, DAG);
6461 case ISD::STORE: return LowerSTORE(Op, DAG);
6462 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6463 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6464 case ISD::FP_TO_UINT:
6465 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6467 case ISD::UINT_TO_FP:
6468 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6469 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6471 // Lower 64-bit shifts.
6472 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6473 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6474 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6476 // Vector-related lowering.
6477 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6478 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6479 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6480 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6481 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6482 case ISD::MUL: return LowerMUL(Op, DAG);
6484 // For counter-based loop handling.
6485 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6487 // Frame & Return address.
6488 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6489 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6493 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6494 SmallVectorImpl<SDValue>&Results,
6495 SelectionDAG &DAG) const {
6496 const TargetMachine &TM = getTargetMachine();
6498 switch (N->getOpcode()) {
6500 llvm_unreachable("Do not know how to custom type legalize this operation!");
6501 case ISD::READCYCLECOUNTER: {
6502 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6503 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
6505 Results.push_back(RTB);
6506 Results.push_back(RTB.getValue(1));
6507 Results.push_back(RTB.getValue(2));
6510 case ISD::INTRINSIC_W_CHAIN: {
6511 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6512 Intrinsic::ppc_is_decremented_ctr_nonzero)
6515 assert(N->getValueType(0) == MVT::i1 &&
6516 "Unexpected result type for CTR decrement intrinsic");
6517 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6518 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6519 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6522 Results.push_back(NewInt);
6523 Results.push_back(NewInt.getValue(1));
6527 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6528 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6531 EVT VT = N->getValueType(0);
6533 if (VT == MVT::i64) {
6534 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6536 Results.push_back(NewNode);
6537 Results.push_back(NewNode.getValue(1));
6541 case ISD::FP_ROUND_INREG: {
6542 assert(N->getValueType(0) == MVT::ppcf128);
6543 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6544 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6545 MVT::f64, N->getOperand(0),
6546 DAG.getIntPtrConstant(0));
6547 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6548 MVT::f64, N->getOperand(0),
6549 DAG.getIntPtrConstant(1));
6551 // Add the two halves of the long double in round-to-zero mode.
6552 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6554 // We know the low half is about to be thrown away, so just use something
6556 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6560 case ISD::FP_TO_SINT:
6561 // LowerFP_TO_INT() can only handle f32 and f64.
6562 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6564 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6570 //===----------------------------------------------------------------------===//
6571 // Other Lowering Code
6572 //===----------------------------------------------------------------------===//
6574 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
6575 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
6576 Function *Func = Intrinsic::getDeclaration(M, Id);
6577 return Builder.CreateCall(Func);
6580 // The mappings for emitLeading/TrailingFence is taken from
6581 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
6582 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
6583 AtomicOrdering Ord, bool IsStore,
6584 bool IsLoad) const {
6585 if (Ord == SequentiallyConsistent)
6586 return callIntrinsic(Builder, Intrinsic::ppc_sync);
6587 else if (isAtLeastRelease(Ord))
6588 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6593 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
6594 AtomicOrdering Ord, bool IsStore,
6595 bool IsLoad) const {
6596 if (IsLoad && isAtLeastAcquire(Ord))
6597 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6598 // FIXME: this is too conservative, a dependent branch + isync is enough.
6599 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
6600 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
6601 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
6607 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6608 bool is64bit, unsigned BinOpcode) const {
6609 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6610 const TargetInstrInfo *TII =
6611 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6613 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6614 MachineFunction *F = BB->getParent();
6615 MachineFunction::iterator It = BB;
6618 unsigned dest = MI->getOperand(0).getReg();
6619 unsigned ptrA = MI->getOperand(1).getReg();
6620 unsigned ptrB = MI->getOperand(2).getReg();
6621 unsigned incr = MI->getOperand(3).getReg();
6622 DebugLoc dl = MI->getDebugLoc();
6624 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6625 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6626 F->insert(It, loopMBB);
6627 F->insert(It, exitMBB);
6628 exitMBB->splice(exitMBB->begin(), BB,
6629 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6630 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6632 MachineRegisterInfo &RegInfo = F->getRegInfo();
6633 unsigned TmpReg = (!BinOpcode) ? incr :
6634 RegInfo.createVirtualRegister( is64bit ? &PPC::G8RCRegClass
6635 : &PPC::GPRCRegClass);
6639 // fallthrough --> loopMBB
6640 BB->addSuccessor(loopMBB);
6643 // l[wd]arx dest, ptr
6644 // add r0, dest, incr
6645 // st[wd]cx. r0, ptr
6647 // fallthrough --> exitMBB
6649 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6650 .addReg(ptrA).addReg(ptrB);
6652 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6653 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6654 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6655 BuildMI(BB, dl, TII->get(PPC::BCC))
6656 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6657 BB->addSuccessor(loopMBB);
6658 BB->addSuccessor(exitMBB);
6667 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6668 MachineBasicBlock *BB,
6669 bool is8bit, // operation
6670 unsigned BinOpcode) const {
6671 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6672 const TargetInstrInfo *TII =
6673 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6674 // In 64 bit mode we have to use 64 bits for addresses, even though the
6675 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6676 // registers without caring whether they're 32 or 64, but here we're
6677 // doing actual arithmetic on the addresses.
6678 bool is64bit = Subtarget.isPPC64();
6679 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6681 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6682 MachineFunction *F = BB->getParent();
6683 MachineFunction::iterator It = BB;
6686 unsigned dest = MI->getOperand(0).getReg();
6687 unsigned ptrA = MI->getOperand(1).getReg();
6688 unsigned ptrB = MI->getOperand(2).getReg();
6689 unsigned incr = MI->getOperand(3).getReg();
6690 DebugLoc dl = MI->getDebugLoc();
6692 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6693 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6694 F->insert(It, loopMBB);
6695 F->insert(It, exitMBB);
6696 exitMBB->splice(exitMBB->begin(), BB,
6697 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6698 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6700 MachineRegisterInfo &RegInfo = F->getRegInfo();
6701 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
6702 : &PPC::GPRCRegClass;
6703 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6704 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6705 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6706 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6707 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6708 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6709 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6710 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6711 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6712 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6713 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6715 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6719 // fallthrough --> loopMBB
6720 BB->addSuccessor(loopMBB);
6722 // The 4-byte load must be aligned, while a char or short may be
6723 // anywhere in the word. Hence all this nasty bookkeeping code.
6724 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6725 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6726 // xori shift, shift1, 24 [16]
6727 // rlwinm ptr, ptr1, 0, 0, 29
6728 // slw incr2, incr, shift
6729 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6730 // slw mask, mask2, shift
6732 // lwarx tmpDest, ptr
6733 // add tmp, tmpDest, incr2
6734 // andc tmp2, tmpDest, mask
6735 // and tmp3, tmp, mask
6736 // or tmp4, tmp3, tmp2
6739 // fallthrough --> exitMBB
6740 // srw dest, tmpDest, shift
6741 if (ptrA != ZeroReg) {
6742 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6743 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6744 .addReg(ptrA).addReg(ptrB);
6748 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6749 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6750 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6751 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6753 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6754 .addReg(Ptr1Reg).addImm(0).addImm(61);
6756 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6757 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6758 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6759 .addReg(incr).addReg(ShiftReg);
6761 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6763 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6764 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6766 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6767 .addReg(Mask2Reg).addReg(ShiftReg);
6770 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6771 .addReg(ZeroReg).addReg(PtrReg);
6773 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6774 .addReg(Incr2Reg).addReg(TmpDestReg);
6775 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6776 .addReg(TmpDestReg).addReg(MaskReg);
6777 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6778 .addReg(TmpReg).addReg(MaskReg);
6779 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6780 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6781 BuildMI(BB, dl, TII->get(PPC::STWCX))
6782 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6783 BuildMI(BB, dl, TII->get(PPC::BCC))
6784 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6785 BB->addSuccessor(loopMBB);
6786 BB->addSuccessor(exitMBB);
6791 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6796 llvm::MachineBasicBlock*
6797 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6798 MachineBasicBlock *MBB) const {
6799 DebugLoc DL = MI->getDebugLoc();
6800 const TargetInstrInfo *TII =
6801 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6803 MachineFunction *MF = MBB->getParent();
6804 MachineRegisterInfo &MRI = MF->getRegInfo();
6806 const BasicBlock *BB = MBB->getBasicBlock();
6807 MachineFunction::iterator I = MBB;
6811 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6812 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6814 unsigned DstReg = MI->getOperand(0).getReg();
6815 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6816 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6817 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6818 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6820 MVT PVT = getPointerTy();
6821 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6822 "Invalid Pointer Size!");
6823 // For v = setjmp(buf), we generate
6826 // SjLjSetup mainMBB
6832 // buf[LabelOffset] = LR
6836 // v = phi(main, restore)
6839 MachineBasicBlock *thisMBB = MBB;
6840 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6841 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6842 MF->insert(I, mainMBB);
6843 MF->insert(I, sinkMBB);
6845 MachineInstrBuilder MIB;
6847 // Transfer the remainder of BB and its successor edges to sinkMBB.
6848 sinkMBB->splice(sinkMBB->begin(), MBB,
6849 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6850 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6852 // Note that the structure of the jmp_buf used here is not compatible
6853 // with that used by libc, and is not designed to be. Specifically, it
6854 // stores only those 'reserved' registers that LLVM does not otherwise
6855 // understand how to spill. Also, by convention, by the time this
6856 // intrinsic is called, Clang has already stored the frame address in the
6857 // first slot of the buffer and stack address in the third. Following the
6858 // X86 target code, we'll store the jump address in the second slot. We also
6859 // need to save the TOC pointer (R2) to handle jumps between shared
6860 // libraries, and that will be stored in the fourth slot. The thread
6861 // identifier (R13) is not affected.
6864 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6865 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6866 const int64_t BPOffset = 4 * PVT.getStoreSize();
6868 // Prepare IP either in reg.
6869 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6870 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6871 unsigned BufReg = MI->getOperand(1).getReg();
6873 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6874 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6878 MIB.setMemRefs(MMOBegin, MMOEnd);
6881 // Naked functions never have a base pointer, and so we use r1. For all
6882 // other functions, this decision must be delayed until during PEI.
6884 if (MF->getFunction()->getAttributes().hasAttribute(
6885 AttributeSet::FunctionIndex, Attribute::Naked))
6886 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6888 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6890 MIB = BuildMI(*thisMBB, MI, DL,
6891 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6895 MIB.setMemRefs(MMOBegin, MMOEnd);
6898 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6899 const PPCRegisterInfo *TRI =
6900 getTargetMachine().getSubtarget<PPCSubtarget>().getRegisterInfo();
6901 MIB.addRegMask(TRI->getNoPreservedMask());
6903 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6905 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6907 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6909 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6910 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6914 MIB = BuildMI(mainMBB, DL,
6915 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6918 if (Subtarget.isPPC64()) {
6919 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6921 .addImm(LabelOffset)
6924 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6926 .addImm(LabelOffset)
6930 MIB.setMemRefs(MMOBegin, MMOEnd);
6932 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6933 mainMBB->addSuccessor(sinkMBB);
6936 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6937 TII->get(PPC::PHI), DstReg)
6938 .addReg(mainDstReg).addMBB(mainMBB)
6939 .addReg(restoreDstReg).addMBB(thisMBB);
6941 MI->eraseFromParent();
6946 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6947 MachineBasicBlock *MBB) const {
6948 DebugLoc DL = MI->getDebugLoc();
6949 const TargetInstrInfo *TII =
6950 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6952 MachineFunction *MF = MBB->getParent();
6953 MachineRegisterInfo &MRI = MF->getRegInfo();
6956 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6957 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6959 MVT PVT = getPointerTy();
6960 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6961 "Invalid Pointer Size!");
6963 const TargetRegisterClass *RC =
6964 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6965 unsigned Tmp = MRI.createVirtualRegister(RC);
6966 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6967 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6968 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6969 unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
6970 (Subtarget.isSVR4ABI() &&
6971 MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
6972 PPC::R29 : PPC::R30);
6974 MachineInstrBuilder MIB;
6976 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6977 const int64_t SPOffset = 2 * PVT.getStoreSize();
6978 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6979 const int64_t BPOffset = 4 * PVT.getStoreSize();
6981 unsigned BufReg = MI->getOperand(0).getReg();
6983 // Reload FP (the jumped-to function may not have had a
6984 // frame pointer, and if so, then its r31 will be restored
6986 if (PVT == MVT::i64) {
6987 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6991 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6995 MIB.setMemRefs(MMOBegin, MMOEnd);
6998 if (PVT == MVT::i64) {
6999 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
7000 .addImm(LabelOffset)
7003 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
7004 .addImm(LabelOffset)
7007 MIB.setMemRefs(MMOBegin, MMOEnd);
7010 if (PVT == MVT::i64) {
7011 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
7015 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
7019 MIB.setMemRefs(MMOBegin, MMOEnd);
7022 if (PVT == MVT::i64) {
7023 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
7027 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
7031 MIB.setMemRefs(MMOBegin, MMOEnd);
7034 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
7035 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
7039 MIB.setMemRefs(MMOBegin, MMOEnd);
7043 BuildMI(*MBB, MI, DL,
7044 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
7045 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
7047 MI->eraseFromParent();
7052 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7053 MachineBasicBlock *BB) const {
7054 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
7055 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
7056 return emitEHSjLjSetJmp(MI, BB);
7057 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
7058 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
7059 return emitEHSjLjLongJmp(MI, BB);
7062 const TargetInstrInfo *TII =
7063 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7065 // To "insert" these instructions we actually have to insert their
7066 // control-flow patterns.
7067 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7068 MachineFunction::iterator It = BB;
7071 MachineFunction *F = BB->getParent();
7073 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7074 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7075 MI->getOpcode() == PPC::SELECT_I4 ||
7076 MI->getOpcode() == PPC::SELECT_I8)) {
7077 SmallVector<MachineOperand, 2> Cond;
7078 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7079 MI->getOpcode() == PPC::SELECT_CC_I8)
7080 Cond.push_back(MI->getOperand(4));
7082 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
7083 Cond.push_back(MI->getOperand(1));
7085 DebugLoc dl = MI->getDebugLoc();
7086 const TargetInstrInfo *TII =
7087 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7088 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7089 Cond, MI->getOperand(2).getReg(),
7090 MI->getOperand(3).getReg());
7091 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7092 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7093 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7094 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7095 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7096 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
7097 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
7098 MI->getOpcode() == PPC::SELECT_I4 ||
7099 MI->getOpcode() == PPC::SELECT_I8 ||
7100 MI->getOpcode() == PPC::SELECT_F4 ||
7101 MI->getOpcode() == PPC::SELECT_F8 ||
7102 MI->getOpcode() == PPC::SELECT_VRRC ||
7103 MI->getOpcode() == PPC::SELECT_VSFRC ||
7104 MI->getOpcode() == PPC::SELECT_VSRC) {
7105 // The incoming instruction knows the destination vreg to set, the
7106 // condition code register to branch on, the true/false values to
7107 // select between, and a branch opcode to use.
7112 // cmpTY ccX, r1, r2
7114 // fallthrough --> copy0MBB
7115 MachineBasicBlock *thisMBB = BB;
7116 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7117 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7118 DebugLoc dl = MI->getDebugLoc();
7119 F->insert(It, copy0MBB);
7120 F->insert(It, sinkMBB);
7122 // Transfer the remainder of BB and its successor edges to sinkMBB.
7123 sinkMBB->splice(sinkMBB->begin(), BB,
7124 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7125 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7127 // Next, add the true and fallthrough blocks as its successors.
7128 BB->addSuccessor(copy0MBB);
7129 BB->addSuccessor(sinkMBB);
7131 if (MI->getOpcode() == PPC::SELECT_I4 ||
7132 MI->getOpcode() == PPC::SELECT_I8 ||
7133 MI->getOpcode() == PPC::SELECT_F4 ||
7134 MI->getOpcode() == PPC::SELECT_F8 ||
7135 MI->getOpcode() == PPC::SELECT_VRRC ||
7136 MI->getOpcode() == PPC::SELECT_VSFRC ||
7137 MI->getOpcode() == PPC::SELECT_VSRC) {
7138 BuildMI(BB, dl, TII->get(PPC::BC))
7139 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7141 unsigned SelectPred = MI->getOperand(4).getImm();
7142 BuildMI(BB, dl, TII->get(PPC::BCC))
7143 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7147 // %FalseValue = ...
7148 // # fallthrough to sinkMBB
7151 // Update machine-CFG edges
7152 BB->addSuccessor(sinkMBB);
7155 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7158 BuildMI(*BB, BB->begin(), dl,
7159 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7160 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7161 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7162 } else if (MI->getOpcode() == PPC::ReadTB) {
7163 // To read the 64-bit time-base register on a 32-bit target, we read the
7164 // two halves. Should the counter have wrapped while it was being read, we
7165 // need to try again.
7168 // mfspr Rx,TBU # load from TBU
7169 // mfspr Ry,TB # load from TB
7170 // mfspr Rz,TBU # load from TBU
7171 // cmpw crX,Rx,Rz # check if ‘old’=’new’
7172 // bne readLoop # branch if they're not equal
7175 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
7176 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7177 DebugLoc dl = MI->getDebugLoc();
7178 F->insert(It, readMBB);
7179 F->insert(It, sinkMBB);
7181 // Transfer the remainder of BB and its successor edges to sinkMBB.
7182 sinkMBB->splice(sinkMBB->begin(), BB,
7183 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7184 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7186 BB->addSuccessor(readMBB);
7189 MachineRegisterInfo &RegInfo = F->getRegInfo();
7190 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
7191 unsigned LoReg = MI->getOperand(0).getReg();
7192 unsigned HiReg = MI->getOperand(1).getReg();
7194 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
7195 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
7196 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
7198 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
7200 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
7201 .addReg(HiReg).addReg(ReadAgainReg);
7202 BuildMI(BB, dl, TII->get(PPC::BCC))
7203 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
7205 BB->addSuccessor(readMBB);
7206 BB->addSuccessor(sinkMBB);
7208 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7209 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7210 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7211 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7212 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7213 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7214 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7215 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7217 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7218 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7219 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7220 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7221 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7222 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7223 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7224 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7226 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7227 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7228 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7229 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7230 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7231 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7232 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7233 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7235 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7236 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7237 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7238 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7239 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7240 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7241 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7242 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7244 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7245 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7246 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7247 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7248 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7249 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7250 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7251 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7253 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7254 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7255 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7256 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7257 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7258 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7259 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7260 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7262 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7263 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7264 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7265 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7266 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7267 BB = EmitAtomicBinary(MI, BB, false, 0);
7268 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7269 BB = EmitAtomicBinary(MI, BB, true, 0);
7271 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7272 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7273 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7275 unsigned dest = MI->getOperand(0).getReg();
7276 unsigned ptrA = MI->getOperand(1).getReg();
7277 unsigned ptrB = MI->getOperand(2).getReg();
7278 unsigned oldval = MI->getOperand(3).getReg();
7279 unsigned newval = MI->getOperand(4).getReg();
7280 DebugLoc dl = MI->getDebugLoc();
7282 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7283 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7284 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7285 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7286 F->insert(It, loop1MBB);
7287 F->insert(It, loop2MBB);
7288 F->insert(It, midMBB);
7289 F->insert(It, exitMBB);
7290 exitMBB->splice(exitMBB->begin(), BB,
7291 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7292 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7296 // fallthrough --> loopMBB
7297 BB->addSuccessor(loop1MBB);
7300 // l[wd]arx dest, ptr
7301 // cmp[wd] dest, oldval
7304 // st[wd]cx. newval, ptr
7308 // st[wd]cx. dest, ptr
7311 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7312 .addReg(ptrA).addReg(ptrB);
7313 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7314 .addReg(oldval).addReg(dest);
7315 BuildMI(BB, dl, TII->get(PPC::BCC))
7316 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7317 BB->addSuccessor(loop2MBB);
7318 BB->addSuccessor(midMBB);
7321 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7322 .addReg(newval).addReg(ptrA).addReg(ptrB);
7323 BuildMI(BB, dl, TII->get(PPC::BCC))
7324 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7325 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7326 BB->addSuccessor(loop1MBB);
7327 BB->addSuccessor(exitMBB);
7330 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7331 .addReg(dest).addReg(ptrA).addReg(ptrB);
7332 BB->addSuccessor(exitMBB);
7337 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7338 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7339 // We must use 64-bit registers for addresses when targeting 64-bit,
7340 // since we're actually doing arithmetic on them. Other registers
7342 bool is64bit = Subtarget.isPPC64();
7343 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7345 unsigned dest = MI->getOperand(0).getReg();
7346 unsigned ptrA = MI->getOperand(1).getReg();
7347 unsigned ptrB = MI->getOperand(2).getReg();
7348 unsigned oldval = MI->getOperand(3).getReg();
7349 unsigned newval = MI->getOperand(4).getReg();
7350 DebugLoc dl = MI->getDebugLoc();
7352 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7353 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7354 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7355 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7356 F->insert(It, loop1MBB);
7357 F->insert(It, loop2MBB);
7358 F->insert(It, midMBB);
7359 F->insert(It, exitMBB);
7360 exitMBB->splice(exitMBB->begin(), BB,
7361 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7362 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7364 MachineRegisterInfo &RegInfo = F->getRegInfo();
7365 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
7366 : &PPC::GPRCRegClass;
7367 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7368 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7369 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7370 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7371 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7372 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7373 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7374 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7375 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7376 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7377 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7378 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7379 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7381 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7382 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7385 // fallthrough --> loopMBB
7386 BB->addSuccessor(loop1MBB);
7388 // The 4-byte load must be aligned, while a char or short may be
7389 // anywhere in the word. Hence all this nasty bookkeeping code.
7390 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7391 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7392 // xori shift, shift1, 24 [16]
7393 // rlwinm ptr, ptr1, 0, 0, 29
7394 // slw newval2, newval, shift
7395 // slw oldval2, oldval,shift
7396 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7397 // slw mask, mask2, shift
7398 // and newval3, newval2, mask
7399 // and oldval3, oldval2, mask
7401 // lwarx tmpDest, ptr
7402 // and tmp, tmpDest, mask
7403 // cmpw tmp, oldval3
7406 // andc tmp2, tmpDest, mask
7407 // or tmp4, tmp2, newval3
7412 // stwcx. tmpDest, ptr
7414 // srw dest, tmpDest, shift
7415 if (ptrA != ZeroReg) {
7416 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7417 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7418 .addReg(ptrA).addReg(ptrB);
7422 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7423 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7424 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7425 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7427 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7428 .addReg(Ptr1Reg).addImm(0).addImm(61);
7430 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7431 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7432 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7433 .addReg(newval).addReg(ShiftReg);
7434 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7435 .addReg(oldval).addReg(ShiftReg);
7437 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7439 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7440 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7441 .addReg(Mask3Reg).addImm(65535);
7443 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7444 .addReg(Mask2Reg).addReg(ShiftReg);
7445 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7446 .addReg(NewVal2Reg).addReg(MaskReg);
7447 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7448 .addReg(OldVal2Reg).addReg(MaskReg);
7451 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7452 .addReg(ZeroReg).addReg(PtrReg);
7453 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7454 .addReg(TmpDestReg).addReg(MaskReg);
7455 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7456 .addReg(TmpReg).addReg(OldVal3Reg);
7457 BuildMI(BB, dl, TII->get(PPC::BCC))
7458 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7459 BB->addSuccessor(loop2MBB);
7460 BB->addSuccessor(midMBB);
7463 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7464 .addReg(TmpDestReg).addReg(MaskReg);
7465 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7466 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7467 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7468 .addReg(ZeroReg).addReg(PtrReg);
7469 BuildMI(BB, dl, TII->get(PPC::BCC))
7470 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7471 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7472 BB->addSuccessor(loop1MBB);
7473 BB->addSuccessor(exitMBB);
7476 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7477 .addReg(ZeroReg).addReg(PtrReg);
7478 BB->addSuccessor(exitMBB);
7483 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7485 } else if (MI->getOpcode() == PPC::FADDrtz) {
7486 // This pseudo performs an FADD with rounding mode temporarily forced
7487 // to round-to-zero. We emit this via custom inserter since the FPSCR
7488 // is not modeled at the SelectionDAG level.
7489 unsigned Dest = MI->getOperand(0).getReg();
7490 unsigned Src1 = MI->getOperand(1).getReg();
7491 unsigned Src2 = MI->getOperand(2).getReg();
7492 DebugLoc dl = MI->getDebugLoc();
7494 MachineRegisterInfo &RegInfo = F->getRegInfo();
7495 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7497 // Save FPSCR value.
7498 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7500 // Set rounding mode to round-to-zero.
7501 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7502 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7504 // Perform addition.
7505 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7507 // Restore FPSCR value.
7508 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7509 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7510 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7511 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7512 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7513 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7514 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7515 PPC::ANDIo8 : PPC::ANDIo;
7516 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7517 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7519 MachineRegisterInfo &RegInfo = F->getRegInfo();
7520 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7521 &PPC::GPRCRegClass :
7522 &PPC::G8RCRegClass);
7524 DebugLoc dl = MI->getDebugLoc();
7525 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7526 .addReg(MI->getOperand(1).getReg()).addImm(1);
7527 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7528 MI->getOperand(0).getReg())
7529 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7531 llvm_unreachable("Unexpected instr type to insert");
7534 MI->eraseFromParent(); // The pseudo instruction is gone now.
7538 //===----------------------------------------------------------------------===//
7539 // Target Optimization Hooks
7540 //===----------------------------------------------------------------------===//
7542 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
7543 DAGCombinerInfo &DCI,
7544 unsigned &RefinementSteps,
7545 bool &UseOneConstNR) const {
7546 EVT VT = Operand.getValueType();
7547 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7548 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7549 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7550 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7551 // Convergence is quadratic, so we essentially double the number of digits
7552 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7553 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7554 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7555 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7556 if (VT.getScalarType() == MVT::f64)
7558 UseOneConstNR = true;
7559 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
7564 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
7565 DAGCombinerInfo &DCI,
7566 unsigned &RefinementSteps) const {
7567 EVT VT = Operand.getValueType();
7568 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7569 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7570 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7571 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7572 // Convergence is quadratic, so we essentially double the number of digits
7573 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7574 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7575 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7576 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7577 if (VT.getScalarType() == MVT::f64)
7579 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
7584 bool PPCTargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
7585 // Note: This functionality is used only when unsafe-fp-math is enabled, and
7586 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
7587 // enabled for division), this functionality is redundant with the default
7588 // combiner logic (once the division -> reciprocal/multiply transformation
7589 // has taken place). As a result, this matters more for older cores than for
7592 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
7593 // reciprocal if there are two or more FDIVs (for embedded cores with only
7594 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
7595 switch (Subtarget.getDarwinDirective()) {
7597 return NumUsers > 2;
7600 case PPC::DIR_E500mc:
7601 case PPC::DIR_E5500:
7602 return NumUsers > 1;
7606 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
7607 unsigned Bytes, int Dist,
7608 SelectionDAG &DAG) {
7609 if (VT.getSizeInBits() / 8 != Bytes)
7612 SDValue BaseLoc = Base->getBasePtr();
7613 if (Loc.getOpcode() == ISD::FrameIndex) {
7614 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7616 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7617 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7618 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7619 int FS = MFI->getObjectSize(FI);
7620 int BFS = MFI->getObjectSize(BFI);
7621 if (FS != BFS || FS != (int)Bytes) return false;
7622 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7626 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7627 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7630 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7631 const GlobalValue *GV1 = nullptr;
7632 const GlobalValue *GV2 = nullptr;
7633 int64_t Offset1 = 0;
7634 int64_t Offset2 = 0;
7635 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7636 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7637 if (isGA1 && isGA2 && GV1 == GV2)
7638 return Offset1 == (Offset2 + Dist*Bytes);
7642 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7643 // not enforce equality of the chain operands.
7644 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
7645 unsigned Bytes, int Dist,
7646 SelectionDAG &DAG) {
7647 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
7648 EVT VT = LS->getMemoryVT();
7649 SDValue Loc = LS->getBasePtr();
7650 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
7653 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
7655 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7656 default: return false;
7657 case Intrinsic::ppc_altivec_lvx:
7658 case Intrinsic::ppc_altivec_lvxl:
7659 case Intrinsic::ppc_vsx_lxvw4x:
7662 case Intrinsic::ppc_vsx_lxvd2x:
7665 case Intrinsic::ppc_altivec_lvebx:
7668 case Intrinsic::ppc_altivec_lvehx:
7671 case Intrinsic::ppc_altivec_lvewx:
7676 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
7679 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
7681 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7682 default: return false;
7683 case Intrinsic::ppc_altivec_stvx:
7684 case Intrinsic::ppc_altivec_stvxl:
7685 case Intrinsic::ppc_vsx_stxvw4x:
7688 case Intrinsic::ppc_vsx_stxvd2x:
7691 case Intrinsic::ppc_altivec_stvebx:
7694 case Intrinsic::ppc_altivec_stvehx:
7697 case Intrinsic::ppc_altivec_stvewx:
7702 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
7708 // Return true is there is a nearyby consecutive load to the one provided
7709 // (regardless of alignment). We search up and down the chain, looking though
7710 // token factors and other loads (but nothing else). As a result, a true result
7711 // indicates that it is safe to create a new consecutive load adjacent to the
7713 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7714 SDValue Chain = LD->getChain();
7715 EVT VT = LD->getMemoryVT();
7717 SmallSet<SDNode *, 16> LoadRoots;
7718 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7719 SmallSet<SDNode *, 16> Visited;
7721 // First, search up the chain, branching to follow all token-factor operands.
7722 // If we find a consecutive load, then we're done, otherwise, record all
7723 // nodes just above the top-level loads and token factors.
7724 while (!Queue.empty()) {
7725 SDNode *ChainNext = Queue.pop_back_val();
7726 if (!Visited.insert(ChainNext).second)
7729 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
7730 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7733 if (!Visited.count(ChainLD->getChain().getNode()))
7734 Queue.push_back(ChainLD->getChain().getNode());
7735 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7736 for (const SDUse &O : ChainNext->ops())
7737 if (!Visited.count(O.getNode()))
7738 Queue.push_back(O.getNode());
7740 LoadRoots.insert(ChainNext);
7743 // Second, search down the chain, starting from the top-level nodes recorded
7744 // in the first phase. These top-level nodes are the nodes just above all
7745 // loads and token factors. Starting with their uses, recursively look though
7746 // all loads (just the chain uses) and token factors to find a consecutive
7751 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7752 IE = LoadRoots.end(); I != IE; ++I) {
7753 Queue.push_back(*I);
7755 while (!Queue.empty()) {
7756 SDNode *LoadRoot = Queue.pop_back_val();
7757 if (!Visited.insert(LoadRoot).second)
7760 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
7761 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7764 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7765 UE = LoadRoot->use_end(); UI != UE; ++UI)
7766 if (((isa<MemSDNode>(*UI) &&
7767 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7768 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7769 Queue.push_back(*UI);
7776 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7777 DAGCombinerInfo &DCI) const {
7778 SelectionDAG &DAG = DCI.DAG;
7781 assert(Subtarget.useCRBits() &&
7782 "Expecting to be tracking CR bits");
7783 // If we're tracking CR bits, we need to be careful that we don't have:
7784 // trunc(binary-ops(zext(x), zext(y)))
7786 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7787 // such that we're unnecessarily moving things into GPRs when it would be
7788 // better to keep them in CR bits.
7790 // Note that trunc here can be an actual i1 trunc, or can be the effective
7791 // truncation that comes from a setcc or select_cc.
7792 if (N->getOpcode() == ISD::TRUNCATE &&
7793 N->getValueType(0) != MVT::i1)
7796 if (N->getOperand(0).getValueType() != MVT::i32 &&
7797 N->getOperand(0).getValueType() != MVT::i64)
7800 if (N->getOpcode() == ISD::SETCC ||
7801 N->getOpcode() == ISD::SELECT_CC) {
7802 // If we're looking at a comparison, then we need to make sure that the
7803 // high bits (all except for the first) don't matter the result.
7805 cast<CondCodeSDNode>(N->getOperand(
7806 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7807 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7809 if (ISD::isSignedIntSetCC(CC)) {
7810 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7811 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7813 } else if (ISD::isUnsignedIntSetCC(CC)) {
7814 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7815 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7816 !DAG.MaskedValueIsZero(N->getOperand(1),
7817 APInt::getHighBitsSet(OpBits, OpBits-1)))
7820 // This is neither a signed nor an unsigned comparison, just make sure
7821 // that the high bits are equal.
7822 APInt Op1Zero, Op1One;
7823 APInt Op2Zero, Op2One;
7824 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7825 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7827 // We don't really care about what is known about the first bit (if
7828 // anything), so clear it in all masks prior to comparing them.
7829 Op1Zero.clearBit(0); Op1One.clearBit(0);
7830 Op2Zero.clearBit(0); Op2One.clearBit(0);
7832 if (Op1Zero != Op2Zero || Op1One != Op2One)
7837 // We now know that the higher-order bits are irrelevant, we just need to
7838 // make sure that all of the intermediate operations are bit operations, and
7839 // all inputs are extensions.
7840 if (N->getOperand(0).getOpcode() != ISD::AND &&
7841 N->getOperand(0).getOpcode() != ISD::OR &&
7842 N->getOperand(0).getOpcode() != ISD::XOR &&
7843 N->getOperand(0).getOpcode() != ISD::SELECT &&
7844 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7845 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7846 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7847 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7848 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7851 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7852 N->getOperand(1).getOpcode() != ISD::AND &&
7853 N->getOperand(1).getOpcode() != ISD::OR &&
7854 N->getOperand(1).getOpcode() != ISD::XOR &&
7855 N->getOperand(1).getOpcode() != ISD::SELECT &&
7856 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7857 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7858 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7859 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7860 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7863 SmallVector<SDValue, 4> Inputs;
7864 SmallVector<SDValue, 8> BinOps, PromOps;
7865 SmallPtrSet<SDNode *, 16> Visited;
7867 for (unsigned i = 0; i < 2; ++i) {
7868 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7869 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7870 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7871 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7872 isa<ConstantSDNode>(N->getOperand(i)))
7873 Inputs.push_back(N->getOperand(i));
7875 BinOps.push_back(N->getOperand(i));
7877 if (N->getOpcode() == ISD::TRUNCATE)
7881 // Visit all inputs, collect all binary operations (and, or, xor and
7882 // select) that are all fed by extensions.
7883 while (!BinOps.empty()) {
7884 SDValue BinOp = BinOps.back();
7887 if (!Visited.insert(BinOp.getNode()).second)
7890 PromOps.push_back(BinOp);
7892 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7893 // The condition of the select is not promoted.
7894 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7896 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7899 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7900 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7901 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7902 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7903 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7904 Inputs.push_back(BinOp.getOperand(i));
7905 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7906 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7907 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7908 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7909 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7910 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7911 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7912 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7913 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7914 BinOps.push_back(BinOp.getOperand(i));
7916 // We have an input that is not an extension or another binary
7917 // operation; we'll abort this transformation.
7923 // Make sure that this is a self-contained cluster of operations (which
7924 // is not quite the same thing as saying that everything has only one
7926 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7927 if (isa<ConstantSDNode>(Inputs[i]))
7930 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7931 UE = Inputs[i].getNode()->use_end();
7934 if (User != N && !Visited.count(User))
7937 // Make sure that we're not going to promote the non-output-value
7938 // operand(s) or SELECT or SELECT_CC.
7939 // FIXME: Although we could sometimes handle this, and it does occur in
7940 // practice that one of the condition inputs to the select is also one of
7941 // the outputs, we currently can't deal with this.
7942 if (User->getOpcode() == ISD::SELECT) {
7943 if (User->getOperand(0) == Inputs[i])
7945 } else if (User->getOpcode() == ISD::SELECT_CC) {
7946 if (User->getOperand(0) == Inputs[i] ||
7947 User->getOperand(1) == Inputs[i])
7953 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7954 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7955 UE = PromOps[i].getNode()->use_end();
7958 if (User != N && !Visited.count(User))
7961 // Make sure that we're not going to promote the non-output-value
7962 // operand(s) or SELECT or SELECT_CC.
7963 // FIXME: Although we could sometimes handle this, and it does occur in
7964 // practice that one of the condition inputs to the select is also one of
7965 // the outputs, we currently can't deal with this.
7966 if (User->getOpcode() == ISD::SELECT) {
7967 if (User->getOperand(0) == PromOps[i])
7969 } else if (User->getOpcode() == ISD::SELECT_CC) {
7970 if (User->getOperand(0) == PromOps[i] ||
7971 User->getOperand(1) == PromOps[i])
7977 // Replace all inputs with the extension operand.
7978 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7979 // Constants may have users outside the cluster of to-be-promoted nodes,
7980 // and so we need to replace those as we do the promotions.
7981 if (isa<ConstantSDNode>(Inputs[i]))
7984 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7987 // Replace all operations (these are all the same, but have a different
7988 // (i1) return type). DAG.getNode will validate that the types of
7989 // a binary operator match, so go through the list in reverse so that
7990 // we've likely promoted both operands first. Any intermediate truncations or
7991 // extensions disappear.
7992 while (!PromOps.empty()) {
7993 SDValue PromOp = PromOps.back();
7996 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7997 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7998 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7999 PromOp.getOpcode() == ISD::ANY_EXTEND) {
8000 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
8001 PromOp.getOperand(0).getValueType() != MVT::i1) {
8002 // The operand is not yet ready (see comment below).
8003 PromOps.insert(PromOps.begin(), PromOp);
8007 SDValue RepValue = PromOp.getOperand(0);
8008 if (isa<ConstantSDNode>(RepValue))
8009 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
8011 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
8016 switch (PromOp.getOpcode()) {
8017 default: C = 0; break;
8018 case ISD::SELECT: C = 1; break;
8019 case ISD::SELECT_CC: C = 2; break;
8022 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8023 PromOp.getOperand(C).getValueType() != MVT::i1) ||
8024 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8025 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
8026 // The to-be-promoted operands of this node have not yet been
8027 // promoted (this should be rare because we're going through the
8028 // list backward, but if one of the operands has several users in
8029 // this cluster of to-be-promoted nodes, it is possible).
8030 PromOps.insert(PromOps.begin(), PromOp);
8034 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8035 PromOp.getNode()->op_end());
8037 // If there are any constant inputs, make sure they're replaced now.
8038 for (unsigned i = 0; i < 2; ++i)
8039 if (isa<ConstantSDNode>(Ops[C+i]))
8040 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
8042 DAG.ReplaceAllUsesOfValueWith(PromOp,
8043 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
8046 // Now we're left with the initial truncation itself.
8047 if (N->getOpcode() == ISD::TRUNCATE)
8048 return N->getOperand(0);
8050 // Otherwise, this is a comparison. The operands to be compared have just
8051 // changed type (to i1), but everything else is the same.
8052 return SDValue(N, 0);
8055 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
8056 DAGCombinerInfo &DCI) const {
8057 SelectionDAG &DAG = DCI.DAG;
8060 // If we're tracking CR bits, we need to be careful that we don't have:
8061 // zext(binary-ops(trunc(x), trunc(y)))
8063 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
8064 // such that we're unnecessarily moving things into CR bits that can more
8065 // efficiently stay in GPRs. Note that if we're not certain that the high
8066 // bits are set as required by the final extension, we still may need to do
8067 // some masking to get the proper behavior.
8069 // This same functionality is important on PPC64 when dealing with
8070 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
8071 // the return values of functions. Because it is so similar, it is handled
8074 if (N->getValueType(0) != MVT::i32 &&
8075 N->getValueType(0) != MVT::i64)
8078 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
8079 Subtarget.useCRBits()) ||
8080 (N->getOperand(0).getValueType() == MVT::i32 &&
8081 Subtarget.isPPC64())))
8084 if (N->getOperand(0).getOpcode() != ISD::AND &&
8085 N->getOperand(0).getOpcode() != ISD::OR &&
8086 N->getOperand(0).getOpcode() != ISD::XOR &&
8087 N->getOperand(0).getOpcode() != ISD::SELECT &&
8088 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
8091 SmallVector<SDValue, 4> Inputs;
8092 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
8093 SmallPtrSet<SDNode *, 16> Visited;
8095 // Visit all inputs, collect all binary operations (and, or, xor and
8096 // select) that are all fed by truncations.
8097 while (!BinOps.empty()) {
8098 SDValue BinOp = BinOps.back();
8101 if (!Visited.insert(BinOp.getNode()).second)
8104 PromOps.push_back(BinOp);
8106 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8107 // The condition of the select is not promoted.
8108 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8110 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8113 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8114 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8115 Inputs.push_back(BinOp.getOperand(i));
8116 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8117 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8118 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8119 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8120 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
8121 BinOps.push_back(BinOp.getOperand(i));
8123 // We have an input that is not a truncation or another binary
8124 // operation; we'll abort this transformation.
8130 // The operands of a select that must be truncated when the select is
8131 // promoted because the operand is actually part of the to-be-promoted set.
8132 DenseMap<SDNode *, EVT> SelectTruncOp[2];
8134 // Make sure that this is a self-contained cluster of operations (which
8135 // is not quite the same thing as saying that everything has only one
8137 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8138 if (isa<ConstantSDNode>(Inputs[i]))
8141 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8142 UE = Inputs[i].getNode()->use_end();
8145 if (User != N && !Visited.count(User))
8148 // If we're going to promote the non-output-value operand(s) or SELECT or
8149 // SELECT_CC, record them for truncation.
8150 if (User->getOpcode() == ISD::SELECT) {
8151 if (User->getOperand(0) == Inputs[i])
8152 SelectTruncOp[0].insert(std::make_pair(User,
8153 User->getOperand(0).getValueType()));
8154 } else if (User->getOpcode() == ISD::SELECT_CC) {
8155 if (User->getOperand(0) == Inputs[i])
8156 SelectTruncOp[0].insert(std::make_pair(User,
8157 User->getOperand(0).getValueType()));
8158 if (User->getOperand(1) == Inputs[i])
8159 SelectTruncOp[1].insert(std::make_pair(User,
8160 User->getOperand(1).getValueType()));
8165 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8166 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8167 UE = PromOps[i].getNode()->use_end();
8170 if (User != N && !Visited.count(User))
8173 // If we're going to promote the non-output-value operand(s) or SELECT or
8174 // SELECT_CC, record them for truncation.
8175 if (User->getOpcode() == ISD::SELECT) {
8176 if (User->getOperand(0) == PromOps[i])
8177 SelectTruncOp[0].insert(std::make_pair(User,
8178 User->getOperand(0).getValueType()));
8179 } else if (User->getOpcode() == ISD::SELECT_CC) {
8180 if (User->getOperand(0) == PromOps[i])
8181 SelectTruncOp[0].insert(std::make_pair(User,
8182 User->getOperand(0).getValueType()));
8183 if (User->getOperand(1) == PromOps[i])
8184 SelectTruncOp[1].insert(std::make_pair(User,
8185 User->getOperand(1).getValueType()));
8190 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8191 bool ReallyNeedsExt = false;
8192 if (N->getOpcode() != ISD::ANY_EXTEND) {
8193 // If all of the inputs are not already sign/zero extended, then
8194 // we'll still need to do that at the end.
8195 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8196 if (isa<ConstantSDNode>(Inputs[i]))
8200 Inputs[i].getOperand(0).getValueSizeInBits();
8201 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8203 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8204 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8205 APInt::getHighBitsSet(OpBits,
8206 OpBits-PromBits))) ||
8207 (N->getOpcode() == ISD::SIGN_EXTEND &&
8208 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8209 (OpBits-(PromBits-1)))) {
8210 ReallyNeedsExt = true;
8216 // Replace all inputs, either with the truncation operand, or a
8217 // truncation or extension to the final output type.
8218 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8219 // Constant inputs need to be replaced with the to-be-promoted nodes that
8220 // use them because they might have users outside of the cluster of
8222 if (isa<ConstantSDNode>(Inputs[i]))
8225 SDValue InSrc = Inputs[i].getOperand(0);
8226 if (Inputs[i].getValueType() == N->getValueType(0))
8227 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8228 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8229 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8230 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8231 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8232 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8233 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8235 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8236 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8239 // Replace all operations (these are all the same, but have a different
8240 // (promoted) return type). DAG.getNode will validate that the types of
8241 // a binary operator match, so go through the list in reverse so that
8242 // we've likely promoted both operands first.
8243 while (!PromOps.empty()) {
8244 SDValue PromOp = PromOps.back();
8248 switch (PromOp.getOpcode()) {
8249 default: C = 0; break;
8250 case ISD::SELECT: C = 1; break;
8251 case ISD::SELECT_CC: C = 2; break;
8254 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8255 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8256 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8257 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8258 // The to-be-promoted operands of this node have not yet been
8259 // promoted (this should be rare because we're going through the
8260 // list backward, but if one of the operands has several users in
8261 // this cluster of to-be-promoted nodes, it is possible).
8262 PromOps.insert(PromOps.begin(), PromOp);
8266 // For SELECT and SELECT_CC nodes, we do a similar check for any
8267 // to-be-promoted comparison inputs.
8268 if (PromOp.getOpcode() == ISD::SELECT ||
8269 PromOp.getOpcode() == ISD::SELECT_CC) {
8270 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
8271 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
8272 (SelectTruncOp[1].count(PromOp.getNode()) &&
8273 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
8274 PromOps.insert(PromOps.begin(), PromOp);
8279 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8280 PromOp.getNode()->op_end());
8282 // If this node has constant inputs, then they'll need to be promoted here.
8283 for (unsigned i = 0; i < 2; ++i) {
8284 if (!isa<ConstantSDNode>(Ops[C+i]))
8286 if (Ops[C+i].getValueType() == N->getValueType(0))
8289 if (N->getOpcode() == ISD::SIGN_EXTEND)
8290 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8291 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8292 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8294 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8297 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
8298 // truncate them again to the original value type.
8299 if (PromOp.getOpcode() == ISD::SELECT ||
8300 PromOp.getOpcode() == ISD::SELECT_CC) {
8301 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
8302 if (SI0 != SelectTruncOp[0].end())
8303 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
8304 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
8305 if (SI1 != SelectTruncOp[1].end())
8306 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
8309 DAG.ReplaceAllUsesOfValueWith(PromOp,
8310 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8313 // Now we're left with the initial extension itself.
8314 if (!ReallyNeedsExt)
8315 return N->getOperand(0);
8317 // To zero extend, just mask off everything except for the first bit (in the
8319 if (N->getOpcode() == ISD::ZERO_EXTEND)
8320 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8321 DAG.getConstant(APInt::getLowBitsSet(
8322 N->getValueSizeInBits(0), PromBits),
8323 N->getValueType(0)));
8325 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8326 "Invalid extension type");
8327 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8329 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8330 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8331 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8332 N->getOperand(0), ShiftCst), ShiftCst);
8335 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
8336 // builtins) into loads with swaps.
8337 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
8338 DAGCombinerInfo &DCI) const {
8339 SelectionDAG &DAG = DCI.DAG;
8343 MachineMemOperand *MMO;
8345 switch (N->getOpcode()) {
8347 llvm_unreachable("Unexpected opcode for little endian VSX load");
8349 LoadSDNode *LD = cast<LoadSDNode>(N);
8350 Chain = LD->getChain();
8351 Base = LD->getBasePtr();
8352 MMO = LD->getMemOperand();
8353 // If the MMO suggests this isn't a load of a full vector, leave
8354 // things alone. For a built-in, we have to make the change for
8355 // correctness, so if there is a size problem that will be a bug.
8356 if (MMO->getSize() < 16)
8360 case ISD::INTRINSIC_W_CHAIN: {
8361 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8362 Chain = Intrin->getChain();
8363 Base = Intrin->getBasePtr();
8364 MMO = Intrin->getMemOperand();
8369 MVT VecTy = N->getValueType(0).getSimpleVT();
8370 SDValue LoadOps[] = { Chain, Base };
8371 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
8372 DAG.getVTList(VecTy, MVT::Other),
8373 LoadOps, VecTy, MMO);
8374 DCI.AddToWorklist(Load.getNode());
8375 Chain = Load.getValue(1);
8376 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8377 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
8378 DCI.AddToWorklist(Swap.getNode());
8382 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
8383 // builtins) into stores with swaps.
8384 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
8385 DAGCombinerInfo &DCI) const {
8386 SelectionDAG &DAG = DCI.DAG;
8391 MachineMemOperand *MMO;
8393 switch (N->getOpcode()) {
8395 llvm_unreachable("Unexpected opcode for little endian VSX store");
8397 StoreSDNode *ST = cast<StoreSDNode>(N);
8398 Chain = ST->getChain();
8399 Base = ST->getBasePtr();
8400 MMO = ST->getMemOperand();
8402 // If the MMO suggests this isn't a store of a full vector, leave
8403 // things alone. For a built-in, we have to make the change for
8404 // correctness, so if there is a size problem that will be a bug.
8405 if (MMO->getSize() < 16)
8409 case ISD::INTRINSIC_VOID: {
8410 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8411 Chain = Intrin->getChain();
8412 // Intrin->getBasePtr() oddly does not get what we want.
8413 Base = Intrin->getOperand(3);
8414 MMO = Intrin->getMemOperand();
8420 SDValue Src = N->getOperand(SrcOpnd);
8421 MVT VecTy = Src.getValueType().getSimpleVT();
8422 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8423 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
8424 DCI.AddToWorklist(Swap.getNode());
8425 Chain = Swap.getValue(1);
8426 SDValue StoreOps[] = { Chain, Swap, Base };
8427 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
8428 DAG.getVTList(MVT::Other),
8429 StoreOps, VecTy, MMO);
8430 DCI.AddToWorklist(Store.getNode());
8434 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8435 DAGCombinerInfo &DCI) const {
8436 const TargetMachine &TM = getTargetMachine();
8437 SelectionDAG &DAG = DCI.DAG;
8439 switch (N->getOpcode()) {
8442 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8443 if (C->isNullValue()) // 0 << V -> 0.
8444 return N->getOperand(0);
8448 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8449 if (C->isNullValue()) // 0 >>u V -> 0.
8450 return N->getOperand(0);
8454 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8455 if (C->isNullValue() || // 0 >>s V -> 0.
8456 C->isAllOnesValue()) // -1 >>s V -> -1.
8457 return N->getOperand(0);
8460 case ISD::SIGN_EXTEND:
8461 case ISD::ZERO_EXTEND:
8462 case ISD::ANY_EXTEND:
8463 return DAGCombineExtBoolTrunc(N, DCI);
8466 case ISD::SELECT_CC:
8467 return DAGCombineTruncBoolExt(N, DCI);
8468 case ISD::SINT_TO_FP:
8469 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
8470 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8471 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8472 // We allow the src/dst to be either f32/f64, but the intermediate
8473 // type must be i64.
8474 if (N->getOperand(0).getValueType() == MVT::i64 &&
8475 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
8476 SDValue Val = N->getOperand(0).getOperand(0);
8477 if (Val.getValueType() == MVT::f32) {
8478 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8479 DCI.AddToWorklist(Val.getNode());
8482 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8483 DCI.AddToWorklist(Val.getNode());
8484 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8485 DCI.AddToWorklist(Val.getNode());
8486 if (N->getValueType(0) == MVT::f32) {
8487 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8488 DAG.getIntPtrConstant(0));
8489 DCI.AddToWorklist(Val.getNode());
8492 } else if (N->getOperand(0).getValueType() == MVT::i32) {
8493 // If the intermediate type is i32, we can avoid the load/store here
8500 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8501 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8502 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8503 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8504 N->getOperand(1).getValueType() == MVT::i32 &&
8505 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8506 SDValue Val = N->getOperand(1).getOperand(0);
8507 if (Val.getValueType() == MVT::f32) {
8508 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8509 DCI.AddToWorklist(Val.getNode());
8511 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8512 DCI.AddToWorklist(Val.getNode());
8515 N->getOperand(0), Val, N->getOperand(2),
8516 DAG.getValueType(N->getOperand(1).getValueType())
8519 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8520 DAG.getVTList(MVT::Other), Ops,
8521 cast<StoreSDNode>(N)->getMemoryVT(),
8522 cast<StoreSDNode>(N)->getMemOperand());
8523 DCI.AddToWorklist(Val.getNode());
8527 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8528 if (cast<StoreSDNode>(N)->isUnindexed() &&
8529 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8530 N->getOperand(1).getNode()->hasOneUse() &&
8531 (N->getOperand(1).getValueType() == MVT::i32 ||
8532 N->getOperand(1).getValueType() == MVT::i16 ||
8533 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8534 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8535 N->getOperand(1).getValueType() == MVT::i64))) {
8536 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8537 // Do an any-extend to 32-bits if this is a half-word input.
8538 if (BSwapOp.getValueType() == MVT::i16)
8539 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8542 N->getOperand(0), BSwapOp, N->getOperand(2),
8543 DAG.getValueType(N->getOperand(1).getValueType())
8546 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8547 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8548 cast<StoreSDNode>(N)->getMemOperand());
8551 // For little endian, VSX stores require generating xxswapd/lxvd2x.
8552 EVT VT = N->getOperand(1).getValueType();
8553 if (VT.isSimple()) {
8554 MVT StoreVT = VT.getSimpleVT();
8555 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8556 TM.getSubtarget<PPCSubtarget>().isLittleEndian() &&
8557 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
8558 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
8559 return expandVSXStoreForLE(N, DCI);
8564 LoadSDNode *LD = cast<LoadSDNode>(N);
8565 EVT VT = LD->getValueType(0);
8567 // For little endian, VSX loads require generating lxvd2x/xxswapd.
8568 if (VT.isSimple()) {
8569 MVT LoadVT = VT.getSimpleVT();
8570 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8571 TM.getSubtarget<PPCSubtarget>().isLittleEndian() &&
8572 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
8573 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
8574 return expandVSXLoadForLE(N, DCI);
8577 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8578 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8579 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8580 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8581 // P8 and later hardware should just use LOAD.
8582 !TM.getSubtarget<PPCSubtarget>().hasP8Vector() &&
8583 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8584 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8585 LD->getAlignment() < ABIAlignment) {
8586 // This is a type-legal unaligned Altivec load.
8587 SDValue Chain = LD->getChain();
8588 SDValue Ptr = LD->getBasePtr();
8589 bool isLittleEndian = Subtarget.isLittleEndian();
8591 // This implements the loading of unaligned vectors as described in
8592 // the venerable Apple Velocity Engine overview. Specifically:
8593 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8594 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8596 // The general idea is to expand a sequence of one or more unaligned
8597 // loads into an alignment-based permutation-control instruction (lvsl
8598 // or lvsr), a series of regular vector loads (which always truncate
8599 // their input address to an aligned address), and a series of
8600 // permutations. The results of these permutations are the requested
8601 // loaded values. The trick is that the last "extra" load is not taken
8602 // from the address you might suspect (sizeof(vector) bytes after the
8603 // last requested load), but rather sizeof(vector) - 1 bytes after the
8604 // last requested vector. The point of this is to avoid a page fault if
8605 // the base address happened to be aligned. This works because if the
8606 // base address is aligned, then adding less than a full vector length
8607 // will cause the last vector in the sequence to be (re)loaded.
8608 // Otherwise, the next vector will be fetched as you might suspect was
8611 // We might be able to reuse the permutation generation from
8612 // a different base address offset from this one by an aligned amount.
8613 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8614 // optimization later.
8615 Intrinsic::ID Intr = (isLittleEndian ?
8616 Intrinsic::ppc_altivec_lvsr :
8617 Intrinsic::ppc_altivec_lvsl);
8618 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8620 // Create the new MMO for the new base load. It is like the original MMO,
8621 // but represents an area in memory almost twice the vector size centered
8622 // on the original address. If the address is unaligned, we might start
8623 // reading up to (sizeof(vector)-1) bytes below the address of the
8624 // original unaligned load.
8625 MachineFunction &MF = DAG.getMachineFunction();
8626 MachineMemOperand *BaseMMO =
8627 MF.getMachineMemOperand(LD->getMemOperand(),
8628 -LD->getMemoryVT().getStoreSize()+1,
8629 2*LD->getMemoryVT().getStoreSize()-1);
8631 // Create the new base load.
8632 SDValue LDXIntID = DAG.getTargetConstant(Intrinsic::ppc_altivec_lvx,
8634 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
8636 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8637 DAG.getVTList(MVT::v4i32, MVT::Other),
8638 BaseLoadOps, MVT::v4i32, BaseMMO);
8640 // Note that the value of IncOffset (which is provided to the next
8641 // load's pointer info offset value, and thus used to calculate the
8642 // alignment), and the value of IncValue (which is actually used to
8643 // increment the pointer value) are different! This is because we
8644 // require the next load to appear to be aligned, even though it
8645 // is actually offset from the base pointer by a lesser amount.
8646 int IncOffset = VT.getSizeInBits() / 8;
8647 int IncValue = IncOffset;
8649 // Walk (both up and down) the chain looking for another load at the real
8650 // (aligned) offset (the alignment of the other load does not matter in
8651 // this case). If found, then do not use the offset reduction trick, as
8652 // that will prevent the loads from being later combined (as they would
8653 // otherwise be duplicates).
8654 if (!findConsecutiveLoad(LD, DAG))
8657 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8658 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8660 MachineMemOperand *ExtraMMO =
8661 MF.getMachineMemOperand(LD->getMemOperand(),
8662 1, 2*LD->getMemoryVT().getStoreSize()-1);
8663 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
8665 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8666 DAG.getVTList(MVT::v4i32, MVT::Other),
8667 ExtraLoadOps, MVT::v4i32, ExtraMMO);
8669 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8670 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8672 // Because vperm has a big-endian bias, we must reverse the order
8673 // of the input vectors and complement the permute control vector
8674 // when generating little endian code. We have already handled the
8675 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8676 // and ExtraLoad here.
8679 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8680 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8682 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8683 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8685 if (VT != MVT::v4i32)
8686 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8688 // The output of the permutation is our loaded result, the TokenFactor is
8690 DCI.CombineTo(N, Perm, TF);
8691 return SDValue(N, 0);
8695 case ISD::INTRINSIC_WO_CHAIN: {
8696 bool isLittleEndian = Subtarget.isLittleEndian();
8697 Intrinsic::ID Intr = (isLittleEndian ?
8698 Intrinsic::ppc_altivec_lvsr :
8699 Intrinsic::ppc_altivec_lvsl);
8700 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8701 N->getOperand(1)->getOpcode() == ISD::ADD) {
8702 SDValue Add = N->getOperand(1);
8704 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8705 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8706 Add.getValueType().getScalarType().getSizeInBits()))) {
8707 SDNode *BasePtr = Add->getOperand(0).getNode();
8708 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8709 UE = BasePtr->use_end(); UI != UE; ++UI) {
8710 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8711 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8713 // We've found another LVSL/LVSR, and this address is an aligned
8714 // multiple of that one. The results will be the same, so use the
8715 // one we've just found instead.
8717 return SDValue(*UI, 0);
8725 case ISD::INTRINSIC_W_CHAIN: {
8726 // For little endian, VSX loads require generating lxvd2x/xxswapd.
8727 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8728 TM.getSubtarget<PPCSubtarget>().isLittleEndian()) {
8729 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8732 case Intrinsic::ppc_vsx_lxvw4x:
8733 case Intrinsic::ppc_vsx_lxvd2x:
8734 return expandVSXLoadForLE(N, DCI);
8739 case ISD::INTRINSIC_VOID: {
8740 // For little endian, VSX stores require generating xxswapd/stxvd2x.
8741 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8742 TM.getSubtarget<PPCSubtarget>().isLittleEndian()) {
8743 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8746 case Intrinsic::ppc_vsx_stxvw4x:
8747 case Intrinsic::ppc_vsx_stxvd2x:
8748 return expandVSXStoreForLE(N, DCI);
8754 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8755 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8756 N->getOperand(0).hasOneUse() &&
8757 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8758 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8759 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8760 N->getValueType(0) == MVT::i64))) {
8761 SDValue Load = N->getOperand(0);
8762 LoadSDNode *LD = cast<LoadSDNode>(Load);
8763 // Create the byte-swapping load.
8765 LD->getChain(), // Chain
8766 LD->getBasePtr(), // Ptr
8767 DAG.getValueType(N->getValueType(0)) // VT
8770 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8771 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8772 MVT::i64 : MVT::i32, MVT::Other),
8773 Ops, LD->getMemoryVT(), LD->getMemOperand());
8775 // If this is an i16 load, insert the truncate.
8776 SDValue ResVal = BSLoad;
8777 if (N->getValueType(0) == MVT::i16)
8778 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8780 // First, combine the bswap away. This makes the value produced by the
8782 DCI.CombineTo(N, ResVal);
8784 // Next, combine the load away, we give it a bogus result value but a real
8785 // chain result. The result value is dead because the bswap is dead.
8786 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8788 // Return N so it doesn't get rechecked!
8789 return SDValue(N, 0);
8793 case PPCISD::VCMP: {
8794 // If a VCMPo node already exists with exactly the same operands as this
8795 // node, use its result instead of this node (VCMPo computes both a CR6 and
8796 // a normal output).
8798 if (!N->getOperand(0).hasOneUse() &&
8799 !N->getOperand(1).hasOneUse() &&
8800 !N->getOperand(2).hasOneUse()) {
8802 // Scan all of the users of the LHS, looking for VCMPo's that match.
8803 SDNode *VCMPoNode = nullptr;
8805 SDNode *LHSN = N->getOperand(0).getNode();
8806 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8808 if (UI->getOpcode() == PPCISD::VCMPo &&
8809 UI->getOperand(1) == N->getOperand(1) &&
8810 UI->getOperand(2) == N->getOperand(2) &&
8811 UI->getOperand(0) == N->getOperand(0)) {
8816 // If there is no VCMPo node, or if the flag value has a single use, don't
8818 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8821 // Look at the (necessarily single) use of the flag value. If it has a
8822 // chain, this transformation is more complex. Note that multiple things
8823 // could use the value result, which we should ignore.
8824 SDNode *FlagUser = nullptr;
8825 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8826 FlagUser == nullptr; ++UI) {
8827 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8829 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8830 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8837 // If the user is a MFOCRF instruction, we know this is safe.
8838 // Otherwise we give up for right now.
8839 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8840 return SDValue(VCMPoNode, 0);
8845 SDValue Cond = N->getOperand(1);
8846 SDValue Target = N->getOperand(2);
8848 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8849 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8850 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8852 // We now need to make the intrinsic dead (it cannot be instruction
8854 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8855 assert(Cond.getNode()->hasOneUse() &&
8856 "Counter decrement has more than one use");
8858 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8859 N->getOperand(0), Target);
8864 // If this is a branch on an altivec predicate comparison, lower this so
8865 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8866 // lowering is done pre-legalize, because the legalizer lowers the predicate
8867 // compare down to code that is difficult to reassemble.
8868 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8869 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8871 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8872 // value. If so, pass-through the AND to get to the intrinsic.
8873 if (LHS.getOpcode() == ISD::AND &&
8874 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8875 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8876 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8877 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8878 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8880 LHS = LHS.getOperand(0);
8882 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8883 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8884 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8885 isa<ConstantSDNode>(RHS)) {
8886 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8887 "Counter decrement comparison is not EQ or NE");
8889 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8890 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8891 (CC == ISD::SETNE && !Val);
8893 // We now need to make the intrinsic dead (it cannot be instruction
8895 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8896 assert(LHS.getNode()->hasOneUse() &&
8897 "Counter decrement has more than one use");
8899 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8900 N->getOperand(0), N->getOperand(4));
8906 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8907 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8908 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8909 assert(isDot && "Can't compare against a vector result!");
8911 // If this is a comparison against something other than 0/1, then we know
8912 // that the condition is never/always true.
8913 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8914 if (Val != 0 && Val != 1) {
8915 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8916 return N->getOperand(0);
8917 // Always !=, turn it into an unconditional branch.
8918 return DAG.getNode(ISD::BR, dl, MVT::Other,
8919 N->getOperand(0), N->getOperand(4));
8922 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8924 // Create the PPCISD altivec 'dot' comparison node.
8926 LHS.getOperand(2), // LHS of compare
8927 LHS.getOperand(3), // RHS of compare
8928 DAG.getConstant(CompareOpc, MVT::i32)
8930 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8931 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8933 // Unpack the result based on how the target uses it.
8934 PPC::Predicate CompOpc;
8935 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8936 default: // Can't happen, don't crash on invalid number though.
8937 case 0: // Branch on the value of the EQ bit of CR6.
8938 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8940 case 1: // Branch on the inverted value of the EQ bit of CR6.
8941 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8943 case 2: // Branch on the value of the LT bit of CR6.
8944 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8946 case 3: // Branch on the inverted value of the LT bit of CR6.
8947 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8951 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8952 DAG.getConstant(CompOpc, MVT::i32),
8953 DAG.getRegister(PPC::CR6, MVT::i32),
8954 N->getOperand(4), CompNode.getValue(1));
8964 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
8966 std::vector<SDNode *> *Created) const {
8967 // fold (sdiv X, pow2)
8968 EVT VT = N->getValueType(0);
8969 if (VT == MVT::i64 && !Subtarget.isPPC64())
8971 if ((VT != MVT::i32 && VT != MVT::i64) ||
8972 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
8976 SDValue N0 = N->getOperand(0);
8978 bool IsNegPow2 = (-Divisor).isPowerOf2();
8979 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
8980 SDValue ShiftAmt = DAG.getConstant(Lg2, VT);
8982 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
8984 Created->push_back(Op.getNode());
8987 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), Op);
8989 Created->push_back(Op.getNode());
8995 //===----------------------------------------------------------------------===//
8996 // Inline Assembly Support
8997 //===----------------------------------------------------------------------===//
8999 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
9002 const SelectionDAG &DAG,
9003 unsigned Depth) const {
9004 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
9005 switch (Op.getOpcode()) {
9007 case PPCISD::LBRX: {
9008 // lhbrx is known to have the top bits cleared out.
9009 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
9010 KnownZero = 0xFFFF0000;
9013 case ISD::INTRINSIC_WO_CHAIN: {
9014 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
9016 case Intrinsic::ppc_altivec_vcmpbfp_p:
9017 case Intrinsic::ppc_altivec_vcmpeqfp_p:
9018 case Intrinsic::ppc_altivec_vcmpequb_p:
9019 case Intrinsic::ppc_altivec_vcmpequh_p:
9020 case Intrinsic::ppc_altivec_vcmpequw_p:
9021 case Intrinsic::ppc_altivec_vcmpgefp_p:
9022 case Intrinsic::ppc_altivec_vcmpgtfp_p:
9023 case Intrinsic::ppc_altivec_vcmpgtsb_p:
9024 case Intrinsic::ppc_altivec_vcmpgtsh_p:
9025 case Intrinsic::ppc_altivec_vcmpgtsw_p:
9026 case Intrinsic::ppc_altivec_vcmpgtub_p:
9027 case Intrinsic::ppc_altivec_vcmpgtuh_p:
9028 case Intrinsic::ppc_altivec_vcmpgtuw_p:
9029 KnownZero = ~1U; // All bits but the low one are known to be zero.
9037 /// getConstraintType - Given a constraint, return the type of
9038 /// constraint it is for this target.
9039 PPCTargetLowering::ConstraintType
9040 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
9041 if (Constraint.size() == 1) {
9042 switch (Constraint[0]) {
9049 return C_RegisterClass;
9051 // FIXME: While Z does indicate a memory constraint, it specifically
9052 // indicates an r+r address (used in conjunction with the 'y' modifier
9053 // in the replacement string). Currently, we're forcing the base
9054 // register to be r0 in the asm printer (which is interpreted as zero)
9055 // and forming the complete address in the second register. This is
9059 } else if (Constraint == "wc") { // individual CR bits.
9060 return C_RegisterClass;
9061 } else if (Constraint == "wa" || Constraint == "wd" ||
9062 Constraint == "wf" || Constraint == "ws") {
9063 return C_RegisterClass; // VSX registers.
9065 return TargetLowering::getConstraintType(Constraint);
9068 /// Examine constraint type and operand type and determine a weight value.
9069 /// This object must already have been set up with the operand type
9070 /// and the current alternative constraint selected.
9071 TargetLowering::ConstraintWeight
9072 PPCTargetLowering::getSingleConstraintMatchWeight(
9073 AsmOperandInfo &info, const char *constraint) const {
9074 ConstraintWeight weight = CW_Invalid;
9075 Value *CallOperandVal = info.CallOperandVal;
9076 // If we don't have a value, we can't do a match,
9077 // but allow it at the lowest weight.
9078 if (!CallOperandVal)
9080 Type *type = CallOperandVal->getType();
9082 // Look at the constraint type.
9083 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
9084 return CW_Register; // an individual CR bit.
9085 else if ((StringRef(constraint) == "wa" ||
9086 StringRef(constraint) == "wd" ||
9087 StringRef(constraint) == "wf") &&
9090 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
9093 switch (*constraint) {
9095 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
9098 if (type->isIntegerTy())
9099 weight = CW_Register;
9102 if (type->isFloatTy())
9103 weight = CW_Register;
9106 if (type->isDoubleTy())
9107 weight = CW_Register;
9110 if (type->isVectorTy())
9111 weight = CW_Register;
9114 weight = CW_Register;
9123 std::pair<unsigned, const TargetRegisterClass*>
9124 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9126 if (Constraint.size() == 1) {
9127 // GCC RS6000 Constraint Letters
9128 switch (Constraint[0]) {
9130 if (VT == MVT::i64 && Subtarget.isPPC64())
9131 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
9132 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
9134 if (VT == MVT::i64 && Subtarget.isPPC64())
9135 return std::make_pair(0U, &PPC::G8RCRegClass);
9136 return std::make_pair(0U, &PPC::GPRCRegClass);
9138 if (VT == MVT::f32 || VT == MVT::i32)
9139 return std::make_pair(0U, &PPC::F4RCRegClass);
9140 if (VT == MVT::f64 || VT == MVT::i64)
9141 return std::make_pair(0U, &PPC::F8RCRegClass);
9144 return std::make_pair(0U, &PPC::VRRCRegClass);
9146 return std::make_pair(0U, &PPC::CRRCRegClass);
9148 } else if (Constraint == "wc") { // an individual CR bit.
9149 return std::make_pair(0U, &PPC::CRBITRCRegClass);
9150 } else if (Constraint == "wa" || Constraint == "wd" ||
9151 Constraint == "wf") {
9152 return std::make_pair(0U, &PPC::VSRCRegClass);
9153 } else if (Constraint == "ws") {
9154 return std::make_pair(0U, &PPC::VSFRCRegClass);
9157 std::pair<unsigned, const TargetRegisterClass*> R =
9158 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9160 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
9161 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
9162 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
9164 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
9165 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
9166 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
9167 PPC::GPRCRegClass.contains(R.first)) {
9168 const TargetRegisterInfo *TRI =
9169 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
9170 return std::make_pair(TRI->getMatchingSuperReg(R.first,
9171 PPC::sub_32, &PPC::G8RCRegClass),
9172 &PPC::G8RCRegClass);
9175 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
9176 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
9178 R.second = &PPC::CRRCRegClass;
9185 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9186 /// vector. If it is invalid, don't add anything to Ops.
9187 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9188 std::string &Constraint,
9189 std::vector<SDValue>&Ops,
9190 SelectionDAG &DAG) const {
9193 // Only support length 1 constraints.
9194 if (Constraint.length() > 1) return;
9196 char Letter = Constraint[0];
9207 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
9208 if (!CST) return; // Must be an immediate to match.
9209 int64_t Value = CST->getSExtValue();
9210 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
9211 // numbers are printed as such.
9213 default: llvm_unreachable("Unknown constraint letter!");
9214 case 'I': // "I" is a signed 16-bit constant.
9215 if (isInt<16>(Value))
9216 Result = DAG.getTargetConstant(Value, TCVT);
9218 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
9219 if (isShiftedUInt<16, 16>(Value))
9220 Result = DAG.getTargetConstant(Value, TCVT);
9222 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
9223 if (isShiftedInt<16, 16>(Value))
9224 Result = DAG.getTargetConstant(Value, TCVT);
9226 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
9227 if (isUInt<16>(Value))
9228 Result = DAG.getTargetConstant(Value, TCVT);
9230 case 'M': // "M" is a constant that is greater than 31.
9232 Result = DAG.getTargetConstant(Value, TCVT);
9234 case 'N': // "N" is a positive constant that is an exact power of two.
9235 if (Value > 0 && isPowerOf2_64(Value))
9236 Result = DAG.getTargetConstant(Value, TCVT);
9238 case 'O': // "O" is the constant zero.
9240 Result = DAG.getTargetConstant(Value, TCVT);
9242 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
9243 if (isInt<16>(-Value))
9244 Result = DAG.getTargetConstant(Value, TCVT);
9251 if (Result.getNode()) {
9252 Ops.push_back(Result);
9256 // Handle standard constraint letters.
9257 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9260 // isLegalAddressingMode - Return true if the addressing mode represented
9261 // by AM is legal for this target, for a load/store of the specified type.
9262 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9264 // FIXME: PPC does not allow r+i addressing modes for vectors!
9266 // PPC allows a sign-extended 16-bit immediate field.
9267 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
9270 // No global is ever allowed as a base.
9274 // PPC only support r+r,
9276 case 0: // "r+i" or just "i", depending on HasBaseReg.
9279 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9281 // Otherwise we have r+r or r+i.
9284 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9286 // Allow 2*r as r+r.
9289 // No other scales are supported.
9296 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
9297 SelectionDAG &DAG) const {
9298 MachineFunction &MF = DAG.getMachineFunction();
9299 MachineFrameInfo *MFI = MF.getFrameInfo();
9300 MFI->setReturnAddressIsTaken(true);
9302 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9306 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9308 // Make sure the function does not optimize away the store of the RA to
9310 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9311 FuncInfo->setLRStoreRequired();
9312 bool isPPC64 = Subtarget.isPPC64();
9313 bool isDarwinABI = Subtarget.isDarwinABI();
9316 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9319 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
9320 isPPC64? MVT::i64 : MVT::i32);
9321 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9322 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9324 MachinePointerInfo(), false, false, false, 0);
9327 // Just load the return address off the stack.
9328 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9329 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9330 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9333 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9334 SelectionDAG &DAG) const {
9336 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9338 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9339 bool isPPC64 = PtrVT == MVT::i64;
9341 MachineFunction &MF = DAG.getMachineFunction();
9342 MachineFrameInfo *MFI = MF.getFrameInfo();
9343 MFI->setFrameAddressIsTaken(true);
9345 // Naked functions never have a frame pointer, and so we use r1. For all
9346 // other functions, this decision must be delayed until during PEI.
9348 if (MF.getFunction()->getAttributes().hasAttribute(
9349 AttributeSet::FunctionIndex, Attribute::Naked))
9350 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9352 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9354 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9357 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9358 FrameAddr, MachinePointerInfo(), false, false,
9363 // FIXME? Maybe this could be a TableGen attribute on some registers and
9364 // this table could be generated automatically from RegInfo.
9365 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9367 bool isPPC64 = Subtarget.isPPC64();
9368 bool isDarwinABI = Subtarget.isDarwinABI();
9370 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9371 (!isPPC64 && VT != MVT::i32))
9372 report_fatal_error("Invalid register global variable type");
9374 bool is64Bit = isPPC64 && VT == MVT::i64;
9375 unsigned Reg = StringSwitch<unsigned>(RegName)
9376 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9377 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
9378 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9379 (is64Bit ? PPC::X13 : PPC::R13))
9384 report_fatal_error("Invalid register name global variable");
9388 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9389 // The PowerPC target isn't yet aware of offsets.
9393 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
9395 unsigned Intrinsic) const {
9397 switch (Intrinsic) {
9398 case Intrinsic::ppc_altivec_lvx:
9399 case Intrinsic::ppc_altivec_lvxl:
9400 case Intrinsic::ppc_altivec_lvebx:
9401 case Intrinsic::ppc_altivec_lvehx:
9402 case Intrinsic::ppc_altivec_lvewx:
9403 case Intrinsic::ppc_vsx_lxvd2x:
9404 case Intrinsic::ppc_vsx_lxvw4x: {
9406 switch (Intrinsic) {
9407 case Intrinsic::ppc_altivec_lvebx:
9410 case Intrinsic::ppc_altivec_lvehx:
9413 case Intrinsic::ppc_altivec_lvewx:
9416 case Intrinsic::ppc_vsx_lxvd2x:
9424 Info.opc = ISD::INTRINSIC_W_CHAIN;
9426 Info.ptrVal = I.getArgOperand(0);
9427 Info.offset = -VT.getStoreSize()+1;
9428 Info.size = 2*VT.getStoreSize()-1;
9431 Info.readMem = true;
9432 Info.writeMem = false;
9435 case Intrinsic::ppc_altivec_stvx:
9436 case Intrinsic::ppc_altivec_stvxl:
9437 case Intrinsic::ppc_altivec_stvebx:
9438 case Intrinsic::ppc_altivec_stvehx:
9439 case Intrinsic::ppc_altivec_stvewx:
9440 case Intrinsic::ppc_vsx_stxvd2x:
9441 case Intrinsic::ppc_vsx_stxvw4x: {
9443 switch (Intrinsic) {
9444 case Intrinsic::ppc_altivec_stvebx:
9447 case Intrinsic::ppc_altivec_stvehx:
9450 case Intrinsic::ppc_altivec_stvewx:
9453 case Intrinsic::ppc_vsx_stxvd2x:
9461 Info.opc = ISD::INTRINSIC_VOID;
9463 Info.ptrVal = I.getArgOperand(1);
9464 Info.offset = -VT.getStoreSize()+1;
9465 Info.size = 2*VT.getStoreSize()-1;
9468 Info.readMem = false;
9469 Info.writeMem = true;
9479 /// getOptimalMemOpType - Returns the target specific optimal type for load
9480 /// and store operations as a result of memset, memcpy, and memmove
9481 /// lowering. If DstAlign is zero that means it's safe to destination
9482 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9483 /// means there isn't a need to check it against alignment requirement,
9484 /// probably because the source does not need to be loaded. If 'IsMemset' is
9485 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9486 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9487 /// source is constant so it does not need to be loaded.
9488 /// It returns EVT::Other if the type should be determined using generic
9489 /// target-independent logic.
9490 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9491 unsigned DstAlign, unsigned SrcAlign,
9492 bool IsMemset, bool ZeroMemset,
9494 MachineFunction &MF) const {
9495 if (Subtarget.isPPC64()) {
9502 /// \brief Returns true if it is beneficial to convert a load of a constant
9503 /// to just the constant itself.
9504 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9506 assert(Ty->isIntegerTy());
9508 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9509 if (BitSize == 0 || BitSize > 64)
9514 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9515 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9517 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9518 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9519 return NumBits1 == 64 && NumBits2 == 32;
9522 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9523 if (!VT1.isInteger() || !VT2.isInteger())
9525 unsigned NumBits1 = VT1.getSizeInBits();
9526 unsigned NumBits2 = VT2.getSizeInBits();
9527 return NumBits1 == 64 && NumBits2 == 32;
9530 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9531 return isInt<16>(Imm) || isUInt<16>(Imm);
9534 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9535 return isInt<16>(Imm) || isUInt<16>(Imm);
9538 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9542 if (DisablePPCUnaligned)
9545 // PowerPC supports unaligned memory access for simple non-vector types.
9546 // Although accessing unaligned addresses is not as efficient as accessing
9547 // aligned addresses, it is generally more efficient than manual expansion,
9548 // and generally only traps for software emulation when crossing page
9554 if (VT.getSimpleVT().isVector()) {
9555 if (Subtarget.hasVSX()) {
9556 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
9557 VT != MVT::v4f32 && VT != MVT::v4i32)
9564 if (VT == MVT::ppcf128)
9573 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9574 VT = VT.getScalarType();
9579 switch (VT.getSimpleVT().SimpleTy) {
9591 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
9592 EVT VT , unsigned DefinedValues) const {
9593 if (VT == MVT::v2i64)
9596 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9599 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9600 if (DisableILPPref || Subtarget.enableMachineScheduler())
9601 return TargetLowering::getSchedulingPreference(N);
9606 // Create a fast isel object.
9608 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9609 const TargetLibraryInfo *LibInfo) const {
9610 return PPC::createFastISel(FuncInfo, LibInfo);