1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
43 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
45 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
46 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
49 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
51 // FIXME: Remove this once the bug has been fixed!
52 extern cl::opt<bool> ANDIGlueBug;
54 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
55 // If it isn't a Mach-O file then it's going to be a linux ELF
58 return new TargetLoweringObjectFileMachO();
60 return new PPC64LinuxTargetObjectFile();
63 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
64 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))),
65 Subtarget(*TM.getSubtargetImpl()) {
68 // Use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(true);
72 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
73 // arguments are at least 4/8 bytes aligned.
74 bool isPPC64 = Subtarget.isPPC64();
75 setMinStackArgumentAlignment(isPPC64 ? 8:4);
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
82 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // PowerPC has pre-inc load and store's.
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
100 if (Subtarget.useCRBits()) {
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
103 if (isPPC64 || Subtarget.hasFPCVT()) {
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
108 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
109 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
115 // PowerPC does not support direct load / store of condition registers
116 setOperationAction(ISD::LOAD, MVT::i1, Custom);
117 setOperationAction(ISD::STORE, MVT::i1, Custom);
119 // FIXME: Remove this once the ANDI glue bug is fixed:
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
125 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
127 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
128 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath &&
180 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget.hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath &&
185 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget.hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget.hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget.hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget.useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget.isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget.isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget.has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget.use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget.hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
405 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
407 // add/sub are legal for all supported vector VT's.
408 setOperationAction(ISD::ADD , VT, Legal);
409 setOperationAction(ISD::SUB , VT, Legal);
411 // We promote all shuffles to v16i8.
412 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
413 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
415 // We promote all non-typed operations to v4i32.
416 setOperationAction(ISD::AND , VT, Promote);
417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
418 setOperationAction(ISD::OR , VT, Promote);
419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
420 setOperationAction(ISD::XOR , VT, Promote);
421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
422 setOperationAction(ISD::LOAD , VT, Promote);
423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
424 setOperationAction(ISD::SELECT, VT, Promote);
425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
426 setOperationAction(ISD::STORE, VT, Promote);
427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
429 // No other operations are legal.
430 setOperationAction(ISD::MUL , VT, Expand);
431 setOperationAction(ISD::SDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UDIV, VT, Expand);
434 setOperationAction(ISD::UREM, VT, Expand);
435 setOperationAction(ISD::FDIV, VT, Expand);
436 setOperationAction(ISD::FREM, VT, Expand);
437 setOperationAction(ISD::FNEG, VT, Expand);
438 setOperationAction(ISD::FSQRT, VT, Expand);
439 setOperationAction(ISD::FLOG, VT, Expand);
440 setOperationAction(ISD::FLOG10, VT, Expand);
441 setOperationAction(ISD::FLOG2, VT, Expand);
442 setOperationAction(ISD::FEXP, VT, Expand);
443 setOperationAction(ISD::FEXP2, VT, Expand);
444 setOperationAction(ISD::FSIN, VT, Expand);
445 setOperationAction(ISD::FCOS, VT, Expand);
446 setOperationAction(ISD::FABS, VT, Expand);
447 setOperationAction(ISD::FPOWI, VT, Expand);
448 setOperationAction(ISD::FFLOOR, VT, Expand);
449 setOperationAction(ISD::FCEIL, VT, Expand);
450 setOperationAction(ISD::FTRUNC, VT, Expand);
451 setOperationAction(ISD::FRINT, VT, Expand);
452 setOperationAction(ISD::FNEARBYINT, VT, Expand);
453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
455 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
456 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
457 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
458 setOperationAction(ISD::UDIVREM, VT, Expand);
459 setOperationAction(ISD::SDIVREM, VT, Expand);
460 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
461 setOperationAction(ISD::FPOW, VT, Expand);
462 setOperationAction(ISD::BSWAP, VT, Expand);
463 setOperationAction(ISD::CTPOP, VT, Expand);
464 setOperationAction(ISD::CTLZ, VT, Expand);
465 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
466 setOperationAction(ISD::CTTZ, VT, Expand);
467 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
468 setOperationAction(ISD::VSELECT, VT, Expand);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
471 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
472 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
473 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
474 setTruncStoreAction(VT, InnerVT, Expand);
476 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
477 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
478 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
481 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
482 // with merges, splats, etc.
483 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
485 setOperationAction(ISD::AND , MVT::v4i32, Legal);
486 setOperationAction(ISD::OR , MVT::v4i32, Legal);
487 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
488 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
489 setOperationAction(ISD::SELECT, MVT::v4i32,
490 Subtarget.useCRBits() ? Legal : Expand);
491 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
492 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
493 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
494 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
495 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
496 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
497 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
498 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
499 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
501 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
502 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
503 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
504 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
506 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
507 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
509 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
510 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
511 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
514 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
515 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
516 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
518 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
519 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
521 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
522 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
524 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
526 // Altivec does not contain unordered floating-point compare instructions
527 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
528 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
529 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
530 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
531 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
532 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
534 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
535 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
537 if (Subtarget.hasVSX()) {
538 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
541 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
542 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
543 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
544 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
545 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
547 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
549 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
550 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
552 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
553 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
559 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
561 // Share the Altivec comparison restrictions.
562 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
563 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
564 setCondCodeAction(ISD::SETUGT, MVT::v2f64, Expand);
565 setCondCodeAction(ISD::SETUGE, MVT::v2f64, Expand);
566 setCondCodeAction(ISD::SETULT, MVT::v2f64, Expand);
567 setCondCodeAction(ISD::SETULE, MVT::v2f64, Expand);
569 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
570 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
572 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
573 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
575 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
577 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
579 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
580 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
582 // VSX v2i64 only supports non-arithmetic operations.
583 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
584 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
586 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
587 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
588 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
590 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
592 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
593 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
594 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
595 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
597 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
599 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
600 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
601 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
602 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
604 // Vector operation legalization checks the result type of
605 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
608 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
611 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
615 if (Subtarget.has64BitSupport()) {
616 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
617 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
620 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
621 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
622 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
623 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
625 setBooleanContents(ZeroOrOneBooleanContent);
626 // Altivec instructions set fields to all zeros or all ones.
627 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
630 setStackPointerRegisterToSaveRestore(PPC::X1);
631 setExceptionPointerRegister(PPC::X3);
632 setExceptionSelectorRegister(PPC::X4);
634 setStackPointerRegisterToSaveRestore(PPC::R1);
635 setExceptionPointerRegister(PPC::R3);
636 setExceptionSelectorRegister(PPC::R4);
639 // We have target-specific dag combine patterns for the following nodes:
640 setTargetDAGCombine(ISD::SINT_TO_FP);
641 setTargetDAGCombine(ISD::LOAD);
642 setTargetDAGCombine(ISD::STORE);
643 setTargetDAGCombine(ISD::BR_CC);
644 if (Subtarget.useCRBits())
645 setTargetDAGCombine(ISD::BRCOND);
646 setTargetDAGCombine(ISD::BSWAP);
647 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
649 setTargetDAGCombine(ISD::SIGN_EXTEND);
650 setTargetDAGCombine(ISD::ZERO_EXTEND);
651 setTargetDAGCombine(ISD::ANY_EXTEND);
653 if (Subtarget.useCRBits()) {
654 setTargetDAGCombine(ISD::TRUNCATE);
655 setTargetDAGCombine(ISD::SETCC);
656 setTargetDAGCombine(ISD::SELECT_CC);
659 // Use reciprocal estimates.
660 if (TM.Options.UnsafeFPMath) {
661 setTargetDAGCombine(ISD::FDIV);
662 setTargetDAGCombine(ISD::FSQRT);
665 // Darwin long double math library functions have $LDBL128 appended.
666 if (Subtarget.isDarwin()) {
667 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
668 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
669 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
670 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
671 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
672 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
673 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
674 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
675 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
676 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
679 // With 32 condition bits, we don't need to sink (and duplicate) compares
680 // aggressively in CodeGenPrep.
681 if (Subtarget.useCRBits())
682 setHasMultipleConditionRegisters();
684 setMinFunctionAlignment(2);
685 if (Subtarget.isDarwin())
686 setPrefFunctionAlignment(4);
688 if (isPPC64 && Subtarget.isJITCodeModel())
689 // Temporary workaround for the inability of PPC64 JIT to handle jump
691 setSupportJumpTables(false);
693 setInsertFencesForAtomic(true);
695 if (Subtarget.enableMachineScheduler())
696 setSchedulingPreference(Sched::Source);
698 setSchedulingPreference(Sched::Hybrid);
700 computeRegisterProperties();
702 // The Freescale cores does better with aggressive inlining of memcpy and
703 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
704 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
705 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
706 MaxStoresPerMemset = 32;
707 MaxStoresPerMemsetOptSize = 16;
708 MaxStoresPerMemcpy = 32;
709 MaxStoresPerMemcpyOptSize = 8;
710 MaxStoresPerMemmove = 32;
711 MaxStoresPerMemmoveOptSize = 8;
713 setPrefFunctionAlignment(4);
717 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
718 /// the desired ByVal argument alignment.
719 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
720 unsigned MaxMaxAlign) {
721 if (MaxAlign == MaxMaxAlign)
723 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
724 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
726 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
728 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
729 unsigned EltAlign = 0;
730 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
731 if (EltAlign > MaxAlign)
733 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
734 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
735 unsigned EltAlign = 0;
736 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
737 if (EltAlign > MaxAlign)
739 if (MaxAlign == MaxMaxAlign)
745 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
746 /// function arguments in the caller parameter area.
747 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
748 // Darwin passes everything on 4 byte boundary.
749 if (Subtarget.isDarwin())
752 // 16byte and wider vectors are passed on 16byte boundary.
753 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
754 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
755 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
756 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
760 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
762 default: return nullptr;
763 case PPCISD::FSEL: return "PPCISD::FSEL";
764 case PPCISD::FCFID: return "PPCISD::FCFID";
765 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
766 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
767 case PPCISD::FRE: return "PPCISD::FRE";
768 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
769 case PPCISD::STFIWX: return "PPCISD::STFIWX";
770 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
771 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
772 case PPCISD::VPERM: return "PPCISD::VPERM";
773 case PPCISD::Hi: return "PPCISD::Hi";
774 case PPCISD::Lo: return "PPCISD::Lo";
775 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
776 case PPCISD::LOAD: return "PPCISD::LOAD";
777 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
778 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
779 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
780 case PPCISD::SRL: return "PPCISD::SRL";
781 case PPCISD::SRA: return "PPCISD::SRA";
782 case PPCISD::SHL: return "PPCISD::SHL";
783 case PPCISD::CALL: return "PPCISD::CALL";
784 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
785 case PPCISD::MTCTR: return "PPCISD::MTCTR";
786 case PPCISD::BCTRL: return "PPCISD::BCTRL";
787 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
788 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
789 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
790 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
791 case PPCISD::VCMP: return "PPCISD::VCMP";
792 case PPCISD::VCMPo: return "PPCISD::VCMPo";
793 case PPCISD::LBRX: return "PPCISD::LBRX";
794 case PPCISD::STBRX: return "PPCISD::STBRX";
795 case PPCISD::LARX: return "PPCISD::LARX";
796 case PPCISD::STCX: return "PPCISD::STCX";
797 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
798 case PPCISD::BDNZ: return "PPCISD::BDNZ";
799 case PPCISD::BDZ: return "PPCISD::BDZ";
800 case PPCISD::MFFS: return "PPCISD::MFFS";
801 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
802 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
803 case PPCISD::CR6SET: return "PPCISD::CR6SET";
804 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
805 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
806 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
807 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
808 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
809 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
810 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
811 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
812 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
813 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
814 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
815 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
816 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
817 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
818 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
819 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
820 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
821 case PPCISD::SC: return "PPCISD::SC";
825 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
827 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
828 return VT.changeVectorElementTypeToInteger();
831 //===----------------------------------------------------------------------===//
832 // Node matching predicates, for use by the tblgen matching code.
833 //===----------------------------------------------------------------------===//
835 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
836 static bool isFloatingPointZero(SDValue Op) {
837 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
838 return CFP->getValueAPF().isZero();
839 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
840 // Maybe this has already been legalized into the constant pool?
841 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
842 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
843 return CFP->getValueAPF().isZero();
848 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
849 /// true if Op is undef or if it matches the specified value.
850 static bool isConstantOrUndef(int Op, int Val) {
851 return Op < 0 || Op == Val;
854 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
855 /// VPKUHUM instruction.
856 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
858 unsigned j = DAG.getTarget().getDataLayout()->isLittleEndian() ? 0 : 1;
860 for (unsigned i = 0; i != 16; ++i)
861 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j))
864 for (unsigned i = 0; i != 8; ++i)
865 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
866 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
872 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
873 /// VPKUWUM instruction.
874 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
877 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
885 for (unsigned i = 0; i != 16; i += 2)
886 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
887 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k))
890 for (unsigned i = 0; i != 8; i += 2)
891 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
892 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k) ||
893 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
894 !isConstantOrUndef(N->getMaskElt(i+9), i*2+k))
900 /// isVMerge - Common function, used to match vmrg* shuffles.
902 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
903 unsigned LHSStart, unsigned RHSStart) {
904 if (N->getValueType(0) != MVT::v16i8)
906 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
907 "Unsupported merge size!");
909 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
910 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
911 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
912 LHSStart+j+i*UnitSize) ||
913 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
914 RHSStart+j+i*UnitSize))
920 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
921 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
922 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
923 bool isUnary, SelectionDAG &DAG) {
924 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
926 return isVMerge(N, UnitSize, 0, 16);
927 return isVMerge(N, UnitSize, 0, 0);
930 return isVMerge(N, UnitSize, 8, 24);
931 return isVMerge(N, UnitSize, 8, 8);
935 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
936 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
937 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
938 bool isUnary, SelectionDAG &DAG) {
939 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
941 return isVMerge(N, UnitSize, 8, 24);
942 return isVMerge(N, UnitSize, 8, 8);
945 return isVMerge(N, UnitSize, 0, 16);
946 return isVMerge(N, UnitSize, 0, 0);
951 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
952 /// amount, otherwise return -1.
953 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG) {
954 if (N->getValueType(0) != MVT::v16i8)
957 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
959 // Find the first non-undef value in the shuffle mask.
961 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
964 if (i == 16) return -1; // all undef.
966 // Otherwise, check to see if the rest of the elements are consecutively
967 // numbered from this value.
968 unsigned ShiftAmt = SVOp->getMaskElt(i);
969 if (ShiftAmt < i) return -1;
971 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
976 // Check the rest of the elements to see if they are consecutive.
977 for (++i; i != 16; ++i)
978 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt - i))
981 // Check the rest of the elements to see if they are consecutive.
982 for (++i; i != 16; ++i)
983 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt - i) & 15))
987 } else { // Big Endian
992 // Check the rest of the elements to see if they are consecutive.
993 for (++i; i != 16; ++i)
994 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
997 // Check the rest of the elements to see if they are consecutive.
998 for (++i; i != 16; ++i)
999 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1006 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1007 /// specifies a splat of a single element that is suitable for input to
1008 /// VSPLTB/VSPLTH/VSPLTW.
1009 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1010 assert(N->getValueType(0) == MVT::v16i8 &&
1011 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1013 // This is a splat operation if each element of the permute is the same, and
1014 // if the value doesn't reference the second vector.
1015 unsigned ElementBase = N->getMaskElt(0);
1017 // FIXME: Handle UNDEF elements too!
1018 if (ElementBase >= 16)
1021 // Check that the indices are consecutive, in the case of a multi-byte element
1022 // splatted with a v16i8 mask.
1023 for (unsigned i = 1; i != EltSize; ++i)
1024 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1027 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1028 if (N->getMaskElt(i) < 0) continue;
1029 for (unsigned j = 0; j != EltSize; ++j)
1030 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1036 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1038 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1039 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1041 APInt APVal, APUndef;
1045 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1046 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1047 return CFP->getValueAPF().isNegZero();
1052 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1053 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1054 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1055 SelectionDAG &DAG) {
1056 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1057 assert(isSplatShuffleMask(SVOp, EltSize));
1058 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1059 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1061 return SVOp->getMaskElt(0) / EltSize;
1064 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1065 /// by using a vspltis[bhw] instruction of the specified element size, return
1066 /// the constant being splatted. The ByteSize field indicates the number of
1067 /// bytes of each element [124] -> [bhw].
1068 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1069 SDValue OpVal(nullptr, 0);
1071 // If ByteSize of the splat is bigger than the element size of the
1072 // build_vector, then we have a case where we are checking for a splat where
1073 // multiple elements of the buildvector are folded together into a single
1074 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1075 unsigned EltSize = 16/N->getNumOperands();
1076 if (EltSize < ByteSize) {
1077 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1078 SDValue UniquedVals[4];
1079 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1081 // See if all of the elements in the buildvector agree across.
1082 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1083 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1084 // If the element isn't a constant, bail fully out.
1085 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1088 if (!UniquedVals[i&(Multiple-1)].getNode())
1089 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1090 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1091 return SDValue(); // no match.
1094 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1095 // either constant or undef values that are identical for each chunk. See
1096 // if these chunks can form into a larger vspltis*.
1098 // Check to see if all of the leading entries are either 0 or -1. If
1099 // neither, then this won't fit into the immediate field.
1100 bool LeadingZero = true;
1101 bool LeadingOnes = true;
1102 for (unsigned i = 0; i != Multiple-1; ++i) {
1103 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1105 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1106 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1108 // Finally, check the least significant entry.
1110 if (!UniquedVals[Multiple-1].getNode())
1111 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1112 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1114 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1117 if (!UniquedVals[Multiple-1].getNode())
1118 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1119 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1120 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1121 return DAG.getTargetConstant(Val, MVT::i32);
1127 // Check to see if this buildvec has a single non-undef value in its elements.
1128 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1129 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1130 if (!OpVal.getNode())
1131 OpVal = N->getOperand(i);
1132 else if (OpVal != N->getOperand(i))
1136 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1138 unsigned ValSizeInBytes = EltSize;
1140 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1141 Value = CN->getZExtValue();
1142 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1143 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1144 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1147 // If the splat value is larger than the element value, then we can never do
1148 // this splat. The only case that we could fit the replicated bits into our
1149 // immediate field for would be zero, and we prefer to use vxor for it.
1150 if (ValSizeInBytes < ByteSize) return SDValue();
1152 // If the element value is larger than the splat value, cut it in half and
1153 // check to see if the two halves are equal. Continue doing this until we
1154 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1155 while (ValSizeInBytes > ByteSize) {
1156 ValSizeInBytes >>= 1;
1158 // If the top half equals the bottom half, we're still ok.
1159 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1160 (Value & ((1 << (8*ValSizeInBytes))-1)))
1164 // Properly sign extend the value.
1165 int MaskVal = SignExtend32(Value, ByteSize * 8);
1167 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1168 if (MaskVal == 0) return SDValue();
1170 // Finally, if this value fits in a 5 bit sext field, return it
1171 if (SignExtend32<5>(MaskVal) == MaskVal)
1172 return DAG.getTargetConstant(MaskVal, MVT::i32);
1176 //===----------------------------------------------------------------------===//
1177 // Addressing Mode Selection
1178 //===----------------------------------------------------------------------===//
1180 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1181 /// or 64-bit immediate, and if the value can be accurately represented as a
1182 /// sign extension from a 16-bit value. If so, this returns true and the
1184 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1185 if (!isa<ConstantSDNode>(N))
1188 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1189 if (N->getValueType(0) == MVT::i32)
1190 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1192 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1194 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1195 return isIntS16Immediate(Op.getNode(), Imm);
1199 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1200 /// can be represented as an indexed [r+r] operation. Returns false if it
1201 /// can be more efficiently represented with [r+imm].
1202 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1204 SelectionDAG &DAG) const {
1206 if (N.getOpcode() == ISD::ADD) {
1207 if (isIntS16Immediate(N.getOperand(1), imm))
1208 return false; // r+i
1209 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1210 return false; // r+i
1212 Base = N.getOperand(0);
1213 Index = N.getOperand(1);
1215 } else if (N.getOpcode() == ISD::OR) {
1216 if (isIntS16Immediate(N.getOperand(1), imm))
1217 return false; // r+i can fold it if we can.
1219 // If this is an or of disjoint bitfields, we can codegen this as an add
1220 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1222 APInt LHSKnownZero, LHSKnownOne;
1223 APInt RHSKnownZero, RHSKnownOne;
1224 DAG.computeKnownBits(N.getOperand(0),
1225 LHSKnownZero, LHSKnownOne);
1227 if (LHSKnownZero.getBoolValue()) {
1228 DAG.computeKnownBits(N.getOperand(1),
1229 RHSKnownZero, RHSKnownOne);
1230 // If all of the bits are known zero on the LHS or RHS, the add won't
1232 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1233 Base = N.getOperand(0);
1234 Index = N.getOperand(1);
1243 // If we happen to be doing an i64 load or store into a stack slot that has
1244 // less than a 4-byte alignment, then the frame-index elimination may need to
1245 // use an indexed load or store instruction (because the offset may not be a
1246 // multiple of 4). The extra register needed to hold the offset comes from the
1247 // register scavenger, and it is possible that the scavenger will need to use
1248 // an emergency spill slot. As a result, we need to make sure that a spill slot
1249 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1251 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1252 // FIXME: This does not handle the LWA case.
1256 // NOTE: We'll exclude negative FIs here, which come from argument
1257 // lowering, because there are no known test cases triggering this problem
1258 // using packed structures (or similar). We can remove this exclusion if
1259 // we find such a test case. The reason why this is so test-case driven is
1260 // because this entire 'fixup' is only to prevent crashes (from the
1261 // register scavenger) on not-really-valid inputs. For example, if we have:
1263 // %b = bitcast i1* %a to i64*
1264 // store i64* a, i64 b
1265 // then the store should really be marked as 'align 1', but is not. If it
1266 // were marked as 'align 1' then the indexed form would have been
1267 // instruction-selected initially, and the problem this 'fixup' is preventing
1268 // won't happen regardless.
1272 MachineFunction &MF = DAG.getMachineFunction();
1273 MachineFrameInfo *MFI = MF.getFrameInfo();
1275 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1279 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1280 FuncInfo->setHasNonRISpills();
1283 /// Returns true if the address N can be represented by a base register plus
1284 /// a signed 16-bit displacement [r+imm], and if it is not better
1285 /// represented as reg+reg. If Aligned is true, only accept displacements
1286 /// suitable for STD and friends, i.e. multiples of 4.
1287 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1290 bool Aligned) const {
1291 // FIXME dl should come from parent load or store, not from address
1293 // If this can be more profitably realized as r+r, fail.
1294 if (SelectAddressRegReg(N, Disp, Base, DAG))
1297 if (N.getOpcode() == ISD::ADD) {
1299 if (isIntS16Immediate(N.getOperand(1), imm) &&
1300 (!Aligned || (imm & 3) == 0)) {
1301 Disp = DAG.getTargetConstant(imm, N.getValueType());
1302 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1303 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1304 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1306 Base = N.getOperand(0);
1308 return true; // [r+i]
1309 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1310 // Match LOAD (ADD (X, Lo(G))).
1311 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1312 && "Cannot handle constant offsets yet!");
1313 Disp = N.getOperand(1).getOperand(0); // The global address.
1314 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1315 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1316 Disp.getOpcode() == ISD::TargetConstantPool ||
1317 Disp.getOpcode() == ISD::TargetJumpTable);
1318 Base = N.getOperand(0);
1319 return true; // [&g+r]
1321 } else if (N.getOpcode() == ISD::OR) {
1323 if (isIntS16Immediate(N.getOperand(1), imm) &&
1324 (!Aligned || (imm & 3) == 0)) {
1325 // If this is an or of disjoint bitfields, we can codegen this as an add
1326 // (for better address arithmetic) if the LHS and RHS of the OR are
1327 // provably disjoint.
1328 APInt LHSKnownZero, LHSKnownOne;
1329 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1331 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1332 // If all of the bits are known zero on the LHS or RHS, the add won't
1334 Base = N.getOperand(0);
1335 Disp = DAG.getTargetConstant(imm, N.getValueType());
1339 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1340 // Loading from a constant address.
1342 // If this address fits entirely in a 16-bit sext immediate field, codegen
1345 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1346 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1347 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1348 CN->getValueType(0));
1352 // Handle 32-bit sext immediates with LIS + addr mode.
1353 if ((CN->getValueType(0) == MVT::i32 ||
1354 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1355 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1356 int Addr = (int)CN->getZExtValue();
1358 // Otherwise, break this down into an LIS + disp.
1359 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1361 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1362 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1363 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1368 Disp = DAG.getTargetConstant(0, getPointerTy());
1369 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1370 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1371 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1374 return true; // [r+0]
1377 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1378 /// represented as an indexed [r+r] operation.
1379 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1381 SelectionDAG &DAG) const {
1382 // Check to see if we can easily represent this as an [r+r] address. This
1383 // will fail if it thinks that the address is more profitably represented as
1384 // reg+imm, e.g. where imm = 0.
1385 if (SelectAddressRegReg(N, Base, Index, DAG))
1388 // If the operand is an addition, always emit this as [r+r], since this is
1389 // better (for code size, and execution, as the memop does the add for free)
1390 // than emitting an explicit add.
1391 if (N.getOpcode() == ISD::ADD) {
1392 Base = N.getOperand(0);
1393 Index = N.getOperand(1);
1397 // Otherwise, do it the hard way, using R0 as the base register.
1398 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1404 /// getPreIndexedAddressParts - returns true by value, base pointer and
1405 /// offset pointer and addressing mode by reference if the node's address
1406 /// can be legally represented as pre-indexed load / store address.
1407 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1409 ISD::MemIndexedMode &AM,
1410 SelectionDAG &DAG) const {
1411 if (DisablePPCPreinc) return false;
1417 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1418 Ptr = LD->getBasePtr();
1419 VT = LD->getMemoryVT();
1420 Alignment = LD->getAlignment();
1421 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1422 Ptr = ST->getBasePtr();
1423 VT = ST->getMemoryVT();
1424 Alignment = ST->getAlignment();
1429 // PowerPC doesn't have preinc load/store instructions for vectors.
1433 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1435 // Common code will reject creating a pre-inc form if the base pointer
1436 // is a frame index, or if N is a store and the base pointer is either
1437 // the same as or a predecessor of the value being stored. Check for
1438 // those situations here, and try with swapped Base/Offset instead.
1441 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1444 SDValue Val = cast<StoreSDNode>(N)->getValue();
1445 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1450 std::swap(Base, Offset);
1456 // LDU/STU can only handle immediates that are a multiple of 4.
1457 if (VT != MVT::i64) {
1458 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1461 // LDU/STU need an address with at least 4-byte alignment.
1465 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1469 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1470 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1471 // sext i32 to i64 when addr mode is r+i.
1472 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1473 LD->getExtensionType() == ISD::SEXTLOAD &&
1474 isa<ConstantSDNode>(Offset))
1482 //===----------------------------------------------------------------------===//
1483 // LowerOperation implementation
1484 //===----------------------------------------------------------------------===//
1486 /// GetLabelAccessInfo - Return true if we should reference labels using a
1487 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1488 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1489 unsigned &LoOpFlags,
1490 const GlobalValue *GV = nullptr) {
1491 HiOpFlags = PPCII::MO_HA;
1492 LoOpFlags = PPCII::MO_LO;
1494 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1495 // non-darwin platform. We don't support PIC on other platforms yet.
1496 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1497 TM.getSubtarget<PPCSubtarget>().isDarwin();
1499 HiOpFlags |= PPCII::MO_PIC_FLAG;
1500 LoOpFlags |= PPCII::MO_PIC_FLAG;
1503 // If this is a reference to a global value that requires a non-lazy-ptr, make
1504 // sure that instruction lowering adds it.
1505 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1506 HiOpFlags |= PPCII::MO_NLP_FLAG;
1507 LoOpFlags |= PPCII::MO_NLP_FLAG;
1509 if (GV->hasHiddenVisibility()) {
1510 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1511 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1518 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1519 SelectionDAG &DAG) {
1520 EVT PtrVT = HiPart.getValueType();
1521 SDValue Zero = DAG.getConstant(0, PtrVT);
1524 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1525 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1527 // With PIC, the first instruction is actually "GR+hi(&G)".
1529 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1530 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1532 // Generate non-pic code that has direct accesses to the constant pool.
1533 // The address of the global is just (hi(&g)+lo(&g)).
1534 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1537 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1538 SelectionDAG &DAG) const {
1539 EVT PtrVT = Op.getValueType();
1540 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1541 const Constant *C = CP->getConstVal();
1543 // 64-bit SVR4 ABI code is always position-independent.
1544 // The actual address of the GlobalValue is stored in the TOC.
1545 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1546 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1547 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1548 DAG.getRegister(PPC::X2, MVT::i64));
1551 unsigned MOHiFlag, MOLoFlag;
1552 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1554 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1556 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1557 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1560 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1561 EVT PtrVT = Op.getValueType();
1562 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1564 // 64-bit SVR4 ABI code is always position-independent.
1565 // The actual address of the GlobalValue is stored in the TOC.
1566 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1567 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1568 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1569 DAG.getRegister(PPC::X2, MVT::i64));
1572 unsigned MOHiFlag, MOLoFlag;
1573 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1574 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1575 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1576 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1579 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1580 SelectionDAG &DAG) const {
1581 EVT PtrVT = Op.getValueType();
1583 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1585 unsigned MOHiFlag, MOLoFlag;
1586 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1587 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1588 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1589 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1592 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1593 SelectionDAG &DAG) const {
1595 // FIXME: TLS addresses currently use medium model code sequences,
1596 // which is the most useful form. Eventually support for small and
1597 // large models could be added if users need it, at the cost of
1598 // additional complexity.
1599 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1601 const GlobalValue *GV = GA->getGlobal();
1602 EVT PtrVT = getPointerTy();
1603 bool is64bit = Subtarget.isPPC64();
1605 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1607 if (Model == TLSModel::LocalExec) {
1608 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1609 PPCII::MO_TPREL_HA);
1610 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1611 PPCII::MO_TPREL_LO);
1612 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1613 is64bit ? MVT::i64 : MVT::i32);
1614 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1615 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1618 if (Model == TLSModel::InitialExec) {
1619 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1620 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1624 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1625 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1626 PtrVT, GOTReg, TGA);
1628 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1629 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1630 PtrVT, TGA, GOTPtr);
1631 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1634 if (Model == TLSModel::GeneralDynamic) {
1635 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1636 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1637 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1639 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1642 // We need a chain node, and don't have one handy. The underlying
1643 // call has no side effects, so using the function entry node
1645 SDValue Chain = DAG.getEntryNode();
1646 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1647 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1648 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1649 PtrVT, ParmReg, TGA);
1650 // The return value from GET_TLS_ADDR really is in X3 already, but
1651 // some hacks are needed here to tie everything together. The extra
1652 // copies dissolve during subsequent transforms.
1653 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1654 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1657 if (Model == TLSModel::LocalDynamic) {
1658 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1659 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1660 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1662 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1665 // We need a chain node, and don't have one handy. The underlying
1666 // call has no side effects, so using the function entry node
1668 SDValue Chain = DAG.getEntryNode();
1669 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1670 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1671 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1672 PtrVT, ParmReg, TGA);
1673 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1674 // some hacks are needed here to tie everything together. The extra
1675 // copies dissolve during subsequent transforms.
1676 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1677 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1678 Chain, ParmReg, TGA);
1679 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1682 llvm_unreachable("Unknown TLS model!");
1685 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1686 SelectionDAG &DAG) const {
1687 EVT PtrVT = Op.getValueType();
1688 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1690 const GlobalValue *GV = GSDN->getGlobal();
1692 // 64-bit SVR4 ABI code is always position-independent.
1693 // The actual address of the GlobalValue is stored in the TOC.
1694 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1695 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1696 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1697 DAG.getRegister(PPC::X2, MVT::i64));
1700 unsigned MOHiFlag, MOLoFlag;
1701 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1704 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1706 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1708 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1710 // If the global reference is actually to a non-lazy-pointer, we have to do an
1711 // extra load to get the address of the global.
1712 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1713 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1714 false, false, false, 0);
1718 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1719 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1722 if (Op.getValueType() == MVT::v2i64) {
1723 // When the operands themselves are v2i64 values, we need to do something
1724 // special because VSX has no underlying comparison operations for these.
1725 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1726 // Equality can be handled by casting to the legal type for Altivec
1727 // comparisons, everything else needs to be expanded.
1728 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1729 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1730 DAG.getSetCC(dl, MVT::v4i32,
1731 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1732 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1739 // We handle most of these in the usual way.
1743 // If we're comparing for equality to zero, expose the fact that this is
1744 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1745 // fold the new nodes.
1746 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1747 if (C->isNullValue() && CC == ISD::SETEQ) {
1748 EVT VT = Op.getOperand(0).getValueType();
1749 SDValue Zext = Op.getOperand(0);
1750 if (VT.bitsLT(MVT::i32)) {
1752 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1754 unsigned Log2b = Log2_32(VT.getSizeInBits());
1755 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1756 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1757 DAG.getConstant(Log2b, MVT::i32));
1758 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1760 // Leave comparisons against 0 and -1 alone for now, since they're usually
1761 // optimized. FIXME: revisit this when we can custom lower all setcc
1763 if (C->isAllOnesValue() || C->isNullValue())
1767 // If we have an integer seteq/setne, turn it into a compare against zero
1768 // by xor'ing the rhs with the lhs, which is faster than setting a
1769 // condition register, reading it back out, and masking the correct bit. The
1770 // normal approach here uses sub to do this instead of xor. Using xor exposes
1771 // the result to other bit-twiddling opportunities.
1772 EVT LHSVT = Op.getOperand(0).getValueType();
1773 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1774 EVT VT = Op.getValueType();
1775 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1777 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1782 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1783 const PPCSubtarget &Subtarget) const {
1784 SDNode *Node = Op.getNode();
1785 EVT VT = Node->getValueType(0);
1786 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1787 SDValue InChain = Node->getOperand(0);
1788 SDValue VAListPtr = Node->getOperand(1);
1789 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1792 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1795 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1796 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1798 InChain = GprIndex.getValue(1);
1800 if (VT == MVT::i64) {
1801 // Check if GprIndex is even
1802 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1803 DAG.getConstant(1, MVT::i32));
1804 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1805 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1806 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1807 DAG.getConstant(1, MVT::i32));
1808 // Align GprIndex to be even if it isn't
1809 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1813 // fpr index is 1 byte after gpr
1814 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1815 DAG.getConstant(1, MVT::i32));
1818 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1819 FprPtr, MachinePointerInfo(SV), MVT::i8,
1821 InChain = FprIndex.getValue(1);
1823 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1824 DAG.getConstant(8, MVT::i32));
1826 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1827 DAG.getConstant(4, MVT::i32));
1830 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1831 MachinePointerInfo(), false, false,
1833 InChain = OverflowArea.getValue(1);
1835 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1836 MachinePointerInfo(), false, false,
1838 InChain = RegSaveArea.getValue(1);
1840 // select overflow_area if index > 8
1841 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1842 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1844 // adjustment constant gpr_index * 4/8
1845 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1846 VT.isInteger() ? GprIndex : FprIndex,
1847 DAG.getConstant(VT.isInteger() ? 4 : 8,
1850 // OurReg = RegSaveArea + RegConstant
1851 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1854 // Floating types are 32 bytes into RegSaveArea
1855 if (VT.isFloatingPoint())
1856 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1857 DAG.getConstant(32, MVT::i32));
1859 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1860 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1861 VT.isInteger() ? GprIndex : FprIndex,
1862 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1865 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1866 VT.isInteger() ? VAListPtr : FprPtr,
1867 MachinePointerInfo(SV),
1868 MVT::i8, false, false, 0);
1870 // determine if we should load from reg_save_area or overflow_area
1871 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1873 // increase overflow_area by 4/8 if gpr/fpr > 8
1874 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1875 DAG.getConstant(VT.isInteger() ? 4 : 8,
1878 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1881 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1883 MachinePointerInfo(),
1884 MVT::i32, false, false, 0);
1886 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1887 false, false, false, 0);
1890 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1891 const PPCSubtarget &Subtarget) const {
1892 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1894 // We have to copy the entire va_list struct:
1895 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1896 return DAG.getMemcpy(Op.getOperand(0), Op,
1897 Op.getOperand(1), Op.getOperand(2),
1898 DAG.getConstant(12, MVT::i32), 8, false, true,
1899 MachinePointerInfo(), MachinePointerInfo());
1902 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1903 SelectionDAG &DAG) const {
1904 return Op.getOperand(0);
1907 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1908 SelectionDAG &DAG) const {
1909 SDValue Chain = Op.getOperand(0);
1910 SDValue Trmp = Op.getOperand(1); // trampoline
1911 SDValue FPtr = Op.getOperand(2); // nested function
1912 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1915 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1916 bool isPPC64 = (PtrVT == MVT::i64);
1918 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1921 TargetLowering::ArgListTy Args;
1922 TargetLowering::ArgListEntry Entry;
1924 Entry.Ty = IntPtrTy;
1925 Entry.Node = Trmp; Args.push_back(Entry);
1927 // TrampSize == (isPPC64 ? 48 : 40);
1928 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1929 isPPC64 ? MVT::i64 : MVT::i32);
1930 Args.push_back(Entry);
1932 Entry.Node = FPtr; Args.push_back(Entry);
1933 Entry.Node = Nest; Args.push_back(Entry);
1935 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1936 TargetLowering::CallLoweringInfo CLI(DAG);
1937 CLI.setDebugLoc(dl).setChain(Chain)
1938 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
1939 DAG.getExternalSymbol("__trampoline_setup", PtrVT), &Args, 0);
1941 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1942 return CallResult.second;
1945 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1946 const PPCSubtarget &Subtarget) const {
1947 MachineFunction &MF = DAG.getMachineFunction();
1948 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1952 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1953 // vastart just stores the address of the VarArgsFrameIndex slot into the
1954 // memory location argument.
1955 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1956 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1957 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1958 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1959 MachinePointerInfo(SV),
1963 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1964 // We suppose the given va_list is already allocated.
1967 // char gpr; /* index into the array of 8 GPRs
1968 // * stored in the register save area
1969 // * gpr=0 corresponds to r3,
1970 // * gpr=1 to r4, etc.
1972 // char fpr; /* index into the array of 8 FPRs
1973 // * stored in the register save area
1974 // * fpr=0 corresponds to f1,
1975 // * fpr=1 to f2, etc.
1977 // char *overflow_arg_area;
1978 // /* location on stack that holds
1979 // * the next overflow argument
1981 // char *reg_save_area;
1982 // /* where r3:r10 and f1:f8 (if saved)
1988 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1989 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1992 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1994 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1996 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1999 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2000 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2002 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2003 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2005 uint64_t FPROffset = 1;
2006 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2008 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2010 // Store first byte : number of int regs
2011 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2013 MachinePointerInfo(SV),
2014 MVT::i8, false, false, 0);
2015 uint64_t nextOffset = FPROffset;
2016 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2019 // Store second byte : number of float regs
2020 SDValue secondStore =
2021 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2022 MachinePointerInfo(SV, nextOffset), MVT::i8,
2024 nextOffset += StackOffset;
2025 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2027 // Store second word : arguments given on stack
2028 SDValue thirdStore =
2029 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2030 MachinePointerInfo(SV, nextOffset),
2032 nextOffset += FrameOffset;
2033 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2035 // Store third word : arguments given in registers
2036 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2037 MachinePointerInfo(SV, nextOffset),
2042 #include "PPCGenCallingConv.inc"
2044 // Function whose sole purpose is to kill compiler warnings
2045 // stemming from unused functions included from PPCGenCallingConv.inc.
2046 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2047 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2050 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2051 CCValAssign::LocInfo &LocInfo,
2052 ISD::ArgFlagsTy &ArgFlags,
2057 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2059 CCValAssign::LocInfo &LocInfo,
2060 ISD::ArgFlagsTy &ArgFlags,
2062 static const MCPhysReg ArgRegs[] = {
2063 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2064 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2066 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2068 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2070 // Skip one register if the first unallocated register has an even register
2071 // number and there are still argument registers available which have not been
2072 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2073 // need to skip a register if RegNum is odd.
2074 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2075 State.AllocateReg(ArgRegs[RegNum]);
2078 // Always return false here, as this function only makes sure that the first
2079 // unallocated register has an odd register number and does not actually
2080 // allocate a register for the current argument.
2084 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2086 CCValAssign::LocInfo &LocInfo,
2087 ISD::ArgFlagsTy &ArgFlags,
2089 static const MCPhysReg ArgRegs[] = {
2090 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2094 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2096 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2098 // If there is only one Floating-point register left we need to put both f64
2099 // values of a split ppc_fp128 value on the stack.
2100 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2101 State.AllocateReg(ArgRegs[RegNum]);
2104 // Always return false here, as this function only makes sure that the two f64
2105 // values a ppc_fp128 value is split into are both passed in registers or both
2106 // passed on the stack and does not actually allocate a register for the
2107 // current argument.
2111 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2113 static const MCPhysReg *GetFPR() {
2114 static const MCPhysReg FPR[] = {
2115 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2116 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2122 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2124 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2125 unsigned PtrByteSize) {
2126 unsigned ArgSize = ArgVT.getStoreSize();
2127 if (Flags.isByVal())
2128 ArgSize = Flags.getByValSize();
2129 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2133 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2134 /// ensure minimum alignment required for target.
2135 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2136 unsigned NumBytes) {
2137 unsigned TargetAlign = Target.getFrameLowering()->getStackAlignment();
2138 unsigned AlignMask = TargetAlign - 1;
2139 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2144 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2145 CallingConv::ID CallConv, bool isVarArg,
2146 const SmallVectorImpl<ISD::InputArg>
2148 SDLoc dl, SelectionDAG &DAG,
2149 SmallVectorImpl<SDValue> &InVals)
2151 if (Subtarget.isSVR4ABI()) {
2152 if (Subtarget.isPPC64())
2153 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2156 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2159 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2165 PPCTargetLowering::LowerFormalArguments_32SVR4(
2167 CallingConv::ID CallConv, bool isVarArg,
2168 const SmallVectorImpl<ISD::InputArg>
2170 SDLoc dl, SelectionDAG &DAG,
2171 SmallVectorImpl<SDValue> &InVals) const {
2173 // 32-bit SVR4 ABI Stack Frame Layout:
2174 // +-----------------------------------+
2175 // +--> | Back chain |
2176 // | +-----------------------------------+
2177 // | | Floating-point register save area |
2178 // | +-----------------------------------+
2179 // | | General register save area |
2180 // | +-----------------------------------+
2181 // | | CR save word |
2182 // | +-----------------------------------+
2183 // | | VRSAVE save word |
2184 // | +-----------------------------------+
2185 // | | Alignment padding |
2186 // | +-----------------------------------+
2187 // | | Vector register save area |
2188 // | +-----------------------------------+
2189 // | | Local variable space |
2190 // | +-----------------------------------+
2191 // | | Parameter list area |
2192 // | +-----------------------------------+
2193 // | | LR save word |
2194 // | +-----------------------------------+
2195 // SP--> +--- | Back chain |
2196 // +-----------------------------------+
2199 // System V Application Binary Interface PowerPC Processor Supplement
2200 // AltiVec Technology Programming Interface Manual
2202 MachineFunction &MF = DAG.getMachineFunction();
2203 MachineFrameInfo *MFI = MF.getFrameInfo();
2204 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2206 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2207 // Potential tail calls could cause overwriting of argument stack slots.
2208 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2209 (CallConv == CallingConv::Fast));
2210 unsigned PtrByteSize = 4;
2212 // Assign locations to all of the incoming arguments.
2213 SmallVector<CCValAssign, 16> ArgLocs;
2214 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2215 getTargetMachine(), ArgLocs, *DAG.getContext());
2217 // Reserve space for the linkage area on the stack.
2218 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2220 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2222 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2223 CCValAssign &VA = ArgLocs[i];
2225 // Arguments stored in registers.
2226 if (VA.isRegLoc()) {
2227 const TargetRegisterClass *RC;
2228 EVT ValVT = VA.getValVT();
2230 switch (ValVT.getSimpleVT().SimpleTy) {
2232 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2235 RC = &PPC::GPRCRegClass;
2238 RC = &PPC::F4RCRegClass;
2241 if (Subtarget.hasVSX())
2242 RC = &PPC::VSFRCRegClass;
2244 RC = &PPC::F8RCRegClass;
2250 RC = &PPC::VRRCRegClass;
2254 RC = &PPC::VSHRCRegClass;
2258 // Transform the arguments stored in physical registers into virtual ones.
2259 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2260 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2261 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2263 if (ValVT == MVT::i1)
2264 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2266 InVals.push_back(ArgValue);
2268 // Argument stored in memory.
2269 assert(VA.isMemLoc());
2271 unsigned ArgSize = VA.getLocVT().getStoreSize();
2272 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2275 // Create load nodes to retrieve arguments from the stack.
2276 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2277 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2278 MachinePointerInfo(),
2279 false, false, false, 0));
2283 // Assign locations to all of the incoming aggregate by value arguments.
2284 // Aggregates passed by value are stored in the local variable space of the
2285 // caller's stack frame, right above the parameter list area.
2286 SmallVector<CCValAssign, 16> ByValArgLocs;
2287 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2288 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2290 // Reserve stack space for the allocations in CCInfo.
2291 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2293 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2295 // Area that is at least reserved in the caller of this function.
2296 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2298 std::max(MinReservedArea,
2299 PPCFrameLowering::getMinCallFrameSize(false, false));
2301 // Set the size that is at least reserved in caller of this function. Tail
2302 // call optimized function's reserved stack space needs to be aligned so that
2303 // taking the difference between two stack areas will result in an aligned
2305 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2306 FuncInfo->setMinReservedArea(MinReservedArea);
2308 SmallVector<SDValue, 8> MemOps;
2310 // If the function takes variable number of arguments, make a frame index for
2311 // the start of the first vararg value... for expansion of llvm.va_start.
2313 static const MCPhysReg GPArgRegs[] = {
2314 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2315 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2317 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2319 static const MCPhysReg FPArgRegs[] = {
2320 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2323 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2325 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2327 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2330 // Make room for NumGPArgRegs and NumFPArgRegs.
2331 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2332 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2334 FuncInfo->setVarArgsStackOffset(
2335 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2336 CCInfo.getNextStackOffset(), true));
2338 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2339 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2341 // The fixed integer arguments of a variadic function are stored to the
2342 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2343 // the result of va_next.
2344 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2345 // Get an existing live-in vreg, or add a new one.
2346 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2348 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2350 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2351 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2352 MachinePointerInfo(), false, false, 0);
2353 MemOps.push_back(Store);
2354 // Increment the address by four for the next argument to store
2355 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2356 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2359 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2361 // The double arguments are stored to the VarArgsFrameIndex
2363 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2364 // Get an existing live-in vreg, or add a new one.
2365 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2367 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2369 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2370 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2371 MachinePointerInfo(), false, false, 0);
2372 MemOps.push_back(Store);
2373 // Increment the address by eight for the next argument to store
2374 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2376 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2380 if (!MemOps.empty())
2381 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2386 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2387 // value to MVT::i64 and then truncate to the correct register size.
2389 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2390 SelectionDAG &DAG, SDValue ArgVal,
2393 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2394 DAG.getValueType(ObjectVT));
2395 else if (Flags.isZExt())
2396 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2397 DAG.getValueType(ObjectVT));
2399 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2403 PPCTargetLowering::LowerFormalArguments_64SVR4(
2405 CallingConv::ID CallConv, bool isVarArg,
2406 const SmallVectorImpl<ISD::InputArg>
2408 SDLoc dl, SelectionDAG &DAG,
2409 SmallVectorImpl<SDValue> &InVals) const {
2410 // TODO: add description of PPC stack frame format, or at least some docs.
2412 bool isLittleEndian = Subtarget.isLittleEndian();
2413 MachineFunction &MF = DAG.getMachineFunction();
2414 MachineFrameInfo *MFI = MF.getFrameInfo();
2415 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2417 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2418 // Potential tail calls could cause overwriting of argument stack slots.
2419 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2420 (CallConv == CallingConv::Fast));
2421 unsigned PtrByteSize = 8;
2423 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, false);
2424 // Area that is at least reserved in caller of this function.
2425 unsigned MinReservedArea = ArgOffset;
2427 static const MCPhysReg GPR[] = {
2428 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2429 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2432 static const MCPhysReg *FPR = GetFPR();
2434 static const MCPhysReg VR[] = {
2435 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2436 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2438 static const MCPhysReg VSRH[] = {
2439 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2440 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2443 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2444 const unsigned Num_FPR_Regs = 13;
2445 const unsigned Num_VR_Regs = array_lengthof(VR);
2447 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2449 // Add DAG nodes to load the arguments or copy them out of registers. On
2450 // entry to a function on PPC, the arguments start after the linkage area,
2451 // although the first ones are often in registers.
2453 SmallVector<SDValue, 8> MemOps;
2454 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2455 unsigned CurArgIdx = 0;
2456 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2458 bool needsLoad = false;
2459 EVT ObjectVT = Ins[ArgNo].VT;
2460 unsigned ObjSize = ObjectVT.getStoreSize();
2461 unsigned ArgSize = ObjSize;
2462 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2463 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2464 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2466 unsigned CurArgOffset = ArgOffset;
2468 // Altivec parameters are padded to a 16 byte boundary.
2469 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2470 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8 ||
2471 ObjectVT==MVT::v2f64 || ObjectVT==MVT::v2i64)
2472 MinReservedArea = ((MinReservedArea+15)/16)*16;
2474 // Calculate min reserved area.
2475 MinReservedArea += CalculateStackSlotSize(ObjectVT, Flags, PtrByteSize);
2477 // FIXME the codegen can be much improved in some cases.
2478 // We do not have to keep everything in memory.
2479 if (Flags.isByVal()) {
2480 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2481 ObjSize = Flags.getByValSize();
2482 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2483 // Empty aggregate parameters do not take up registers. Examples:
2487 // etc. However, we have to provide a place-holder in InVals, so
2488 // pretend we have an 8-byte item at the current address for that
2491 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2492 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2493 InVals.push_back(FIN);
2497 unsigned BVAlign = Flags.getByValAlign();
2499 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
2500 CurArgOffset = ArgOffset;
2503 // All aggregates smaller than 8 bytes must be passed right-justified.
2504 if (ObjSize < PtrByteSize && !isLittleEndian)
2505 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2506 // The value of the object is its address.
2507 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2508 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2509 InVals.push_back(FIN);
2512 if (GPR_idx != Num_GPR_Regs) {
2513 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2514 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2517 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2518 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2519 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2520 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2521 MachinePointerInfo(FuncArg),
2522 ObjType, false, false, 0);
2524 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2525 // store the whole register as-is to the parameter save area
2526 // slot. The address of the parameter was already calculated
2527 // above (InVals.push_back(FIN)) to be the right-justified
2528 // offset within the slot. For this store, we need a new
2529 // frame index that points at the beginning of the slot.
2530 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2531 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2532 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2533 MachinePointerInfo(FuncArg),
2537 MemOps.push_back(Store);
2540 // Whether we copied from a register or not, advance the offset
2541 // into the parameter save area by a full doubleword.
2542 ArgOffset += PtrByteSize;
2546 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2547 // Store whatever pieces of the object are in registers
2548 // to memory. ArgOffset will be the address of the beginning
2550 if (GPR_idx != Num_GPR_Regs) {
2552 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2553 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2554 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2555 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2556 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2557 MachinePointerInfo(FuncArg, j),
2559 MemOps.push_back(Store);
2561 ArgOffset += PtrByteSize;
2563 ArgOffset += ArgSize - j;
2570 switch (ObjectVT.getSimpleVT().SimpleTy) {
2571 default: llvm_unreachable("Unhandled argument type!");
2575 if (GPR_idx != Num_GPR_Regs) {
2576 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2577 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2579 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2580 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2581 // value to MVT::i64 and then truncate to the correct register size.
2582 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2587 ArgSize = PtrByteSize;
2594 // Every 8 bytes of argument space consumes one of the GPRs available for
2595 // argument passing.
2596 if (GPR_idx != Num_GPR_Regs) {
2599 if (FPR_idx != Num_FPR_Regs) {
2602 if (ObjectVT == MVT::f32)
2603 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2605 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2606 &PPC::VSFRCRegClass :
2607 &PPC::F8RCRegClass);
2609 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2613 ArgSize = PtrByteSize;
2624 // Vectors are aligned to a 16-byte boundary in the argument save area.
2625 while ((ArgOffset % 16) != 0) {
2626 ArgOffset += PtrByteSize;
2627 if (GPR_idx != Num_GPR_Regs)
2630 if (VR_idx != Num_VR_Regs) {
2631 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2632 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2633 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2634 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2637 CurArgOffset = ArgOffset;
2641 GPR_idx = std::min(GPR_idx + 2, Num_GPR_Regs);
2645 // We need to load the argument to a virtual register if we determined
2646 // above that we ran out of physical registers of the appropriate type.
2648 if (ObjSize < ArgSize && !isLittleEndian)
2649 CurArgOffset += ArgSize - ObjSize;
2650 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2651 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2652 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2653 false, false, false, 0);
2656 InVals.push_back(ArgVal);
2659 // Area that is at least reserved in the caller of this function.
2661 std::max(MinReservedArea,
2662 PPCFrameLowering::getMinCallFrameSize(true, false));
2664 // Set the size that is at least reserved in caller of this function. Tail
2665 // call optimized functions' reserved stack space needs to be aligned so that
2666 // taking the difference between two stack areas will result in an aligned
2668 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2669 FuncInfo->setMinReservedArea(MinReservedArea);
2671 // If the function takes variable number of arguments, make a frame index for
2672 // the start of the first vararg value... for expansion of llvm.va_start.
2674 int Depth = ArgOffset;
2676 FuncInfo->setVarArgsFrameIndex(
2677 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2678 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2680 // If this function is vararg, store any remaining integer argument regs
2681 // to their spots on the stack so that they may be loaded by deferencing the
2682 // result of va_next.
2683 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2684 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2685 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2686 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2687 MachinePointerInfo(), false, false, 0);
2688 MemOps.push_back(Store);
2689 // Increment the address by four for the next argument to store
2690 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2691 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2695 if (!MemOps.empty())
2696 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2702 PPCTargetLowering::LowerFormalArguments_Darwin(
2704 CallingConv::ID CallConv, bool isVarArg,
2705 const SmallVectorImpl<ISD::InputArg>
2707 SDLoc dl, SelectionDAG &DAG,
2708 SmallVectorImpl<SDValue> &InVals) const {
2709 // TODO: add description of PPC stack frame format, or at least some docs.
2711 MachineFunction &MF = DAG.getMachineFunction();
2712 MachineFrameInfo *MFI = MF.getFrameInfo();
2713 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2715 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2716 bool isPPC64 = PtrVT == MVT::i64;
2717 // Potential tail calls could cause overwriting of argument stack slots.
2718 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2719 (CallConv == CallingConv::Fast));
2720 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2722 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2723 // Area that is at least reserved in caller of this function.
2724 unsigned MinReservedArea = ArgOffset;
2726 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2727 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2728 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2730 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2731 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2732 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2735 static const MCPhysReg *FPR = GetFPR();
2737 static const MCPhysReg VR[] = {
2738 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2739 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2742 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2743 const unsigned Num_FPR_Regs = 13;
2744 const unsigned Num_VR_Regs = array_lengthof( VR);
2746 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2748 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2750 // In 32-bit non-varargs functions, the stack space for vectors is after the
2751 // stack space for non-vectors. We do not use this space unless we have
2752 // too many vectors to fit in registers, something that only occurs in
2753 // constructed examples:), but we have to walk the arglist to figure
2754 // that out...for the pathological case, compute VecArgOffset as the
2755 // start of the vector parameter area. Computing VecArgOffset is the
2756 // entire point of the following loop.
2757 unsigned VecArgOffset = ArgOffset;
2758 if (!isVarArg && !isPPC64) {
2759 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2761 EVT ObjectVT = Ins[ArgNo].VT;
2762 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2764 if (Flags.isByVal()) {
2765 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2766 unsigned ObjSize = Flags.getByValSize();
2768 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2769 VecArgOffset += ArgSize;
2773 switch(ObjectVT.getSimpleVT().SimpleTy) {
2774 default: llvm_unreachable("Unhandled argument type!");
2780 case MVT::i64: // PPC64
2782 // FIXME: We are guaranteed to be !isPPC64 at this point.
2783 // Does MVT::i64 apply?
2790 // Nothing to do, we're only looking at Nonvector args here.
2795 // We've found where the vector parameter area in memory is. Skip the
2796 // first 12 parameters; these don't use that memory.
2797 VecArgOffset = ((VecArgOffset+15)/16)*16;
2798 VecArgOffset += 12*16;
2800 // Add DAG nodes to load the arguments or copy them out of registers. On
2801 // entry to a function on PPC, the arguments start after the linkage area,
2802 // although the first ones are often in registers.
2804 SmallVector<SDValue, 8> MemOps;
2805 unsigned nAltivecParamsAtEnd = 0;
2806 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2807 unsigned CurArgIdx = 0;
2808 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2810 bool needsLoad = false;
2811 EVT ObjectVT = Ins[ArgNo].VT;
2812 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2813 unsigned ArgSize = ObjSize;
2814 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2815 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2816 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2818 unsigned CurArgOffset = ArgOffset;
2820 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2821 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2822 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2823 if (isVarArg || isPPC64) {
2824 MinReservedArea = ((MinReservedArea+15)/16)*16;
2825 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2828 } else nAltivecParamsAtEnd++;
2830 // Calculate min reserved area.
2831 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2835 // FIXME the codegen can be much improved in some cases.
2836 // We do not have to keep everything in memory.
2837 if (Flags.isByVal()) {
2838 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2839 ObjSize = Flags.getByValSize();
2840 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2841 // Objects of size 1 and 2 are right justified, everything else is
2842 // left justified. This means the memory address is adjusted forwards.
2843 if (ObjSize==1 || ObjSize==2) {
2844 CurArgOffset = CurArgOffset + (4 - ObjSize);
2846 // The value of the object is its address.
2847 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2848 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2849 InVals.push_back(FIN);
2850 if (ObjSize==1 || ObjSize==2) {
2851 if (GPR_idx != Num_GPR_Regs) {
2854 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2856 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2857 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2858 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2859 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2860 MachinePointerInfo(FuncArg),
2861 ObjType, false, false, 0);
2862 MemOps.push_back(Store);
2866 ArgOffset += PtrByteSize;
2870 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2871 // Store whatever pieces of the object are in registers
2872 // to memory. ArgOffset will be the address of the beginning
2874 if (GPR_idx != Num_GPR_Regs) {
2877 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2879 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2880 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2881 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2882 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2883 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2884 MachinePointerInfo(FuncArg, j),
2886 MemOps.push_back(Store);
2888 ArgOffset += PtrByteSize;
2890 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2897 switch (ObjectVT.getSimpleVT().SimpleTy) {
2898 default: llvm_unreachable("Unhandled argument type!");
2902 if (GPR_idx != Num_GPR_Regs) {
2903 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2904 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2906 if (ObjectVT == MVT::i1)
2907 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
2912 ArgSize = PtrByteSize;
2914 // All int arguments reserve stack space in the Darwin ABI.
2915 ArgOffset += PtrByteSize;
2919 case MVT::i64: // PPC64
2920 if (GPR_idx != Num_GPR_Regs) {
2921 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2922 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2924 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2925 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2926 // value to MVT::i64 and then truncate to the correct register size.
2927 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2932 ArgSize = PtrByteSize;
2934 // All int arguments reserve stack space in the Darwin ABI.
2940 // Every 4 bytes of argument space consumes one of the GPRs available for
2941 // argument passing.
2942 if (GPR_idx != Num_GPR_Regs) {
2944 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2947 if (FPR_idx != Num_FPR_Regs) {
2950 if (ObjectVT == MVT::f32)
2951 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2953 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2955 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2961 // All FP arguments reserve stack space in the Darwin ABI.
2962 ArgOffset += isPPC64 ? 8 : ObjSize;
2968 // Note that vector arguments in registers don't reserve stack space,
2969 // except in varargs functions.
2970 if (VR_idx != Num_VR_Regs) {
2971 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2972 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2974 while ((ArgOffset % 16) != 0) {
2975 ArgOffset += PtrByteSize;
2976 if (GPR_idx != Num_GPR_Regs)
2980 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2984 if (!isVarArg && !isPPC64) {
2985 // Vectors go after all the nonvectors.
2986 CurArgOffset = VecArgOffset;
2989 // Vectors are aligned.
2990 ArgOffset = ((ArgOffset+15)/16)*16;
2991 CurArgOffset = ArgOffset;
2999 // We need to load the argument to a virtual register if we determined above
3000 // that we ran out of physical registers of the appropriate type.
3002 int FI = MFI->CreateFixedObject(ObjSize,
3003 CurArgOffset + (ArgSize - ObjSize),
3005 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3006 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3007 false, false, false, 0);
3010 InVals.push_back(ArgVal);
3013 // Allow for Altivec parameters at the end, if needed.
3014 if (nAltivecParamsAtEnd) {
3015 MinReservedArea = ((MinReservedArea+15)/16)*16;
3016 MinReservedArea += 16*nAltivecParamsAtEnd;
3019 // Area that is at least reserved in the caller of this function.
3021 std::max(MinReservedArea,
3022 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
3024 // Set the size that is at least reserved in caller of this function. Tail
3025 // call optimized functions' reserved stack space needs to be aligned so that
3026 // taking the difference between two stack areas will result in an aligned
3028 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3029 FuncInfo->setMinReservedArea(MinReservedArea);
3031 // If the function takes variable number of arguments, make a frame index for
3032 // the start of the first vararg value... for expansion of llvm.va_start.
3034 int Depth = ArgOffset;
3036 FuncInfo->setVarArgsFrameIndex(
3037 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3039 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3041 // If this function is vararg, store any remaining integer argument regs
3042 // to their spots on the stack so that they may be loaded by deferencing the
3043 // result of va_next.
3044 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3048 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3050 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3052 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3053 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3054 MachinePointerInfo(), false, false, 0);
3055 MemOps.push_back(Store);
3056 // Increment the address by four for the next argument to store
3057 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3058 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3062 if (!MemOps.empty())
3063 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3068 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3069 /// adjusted to accommodate the arguments for the tailcall.
3070 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3071 unsigned ParamSize) {
3073 if (!isTailCall) return 0;
3075 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3076 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3077 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3078 // Remember only if the new adjustement is bigger.
3079 if (SPDiff < FI->getTailCallSPDelta())
3080 FI->setTailCallSPDelta(SPDiff);
3085 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3086 /// for tail call optimization. Targets which want to do tail call
3087 /// optimization should implement this function.
3089 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3090 CallingConv::ID CalleeCC,
3092 const SmallVectorImpl<ISD::InputArg> &Ins,
3093 SelectionDAG& DAG) const {
3094 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3097 // Variable argument functions are not supported.
3101 MachineFunction &MF = DAG.getMachineFunction();
3102 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3103 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3104 // Functions containing by val parameters are not supported.
3105 for (unsigned i = 0; i != Ins.size(); i++) {
3106 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3107 if (Flags.isByVal()) return false;
3110 // Non-PIC/GOT tail calls are supported.
3111 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3114 // At the moment we can only do local tail calls (in same module, hidden
3115 // or protected) if we are generating PIC.
3116 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3117 return G->getGlobal()->hasHiddenVisibility()
3118 || G->getGlobal()->hasProtectedVisibility();
3124 /// isCallCompatibleAddress - Return the immediate to use if the specified
3125 /// 32-bit value is representable in the immediate field of a BxA instruction.
3126 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3127 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3128 if (!C) return nullptr;
3130 int Addr = C->getZExtValue();
3131 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3132 SignExtend32<26>(Addr) != Addr)
3133 return nullptr; // Top 6 bits have to be sext of immediate.
3135 return DAG.getConstant((int)C->getZExtValue() >> 2,
3136 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3141 struct TailCallArgumentInfo {
3146 TailCallArgumentInfo() : FrameIdx(0) {}
3151 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3153 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3155 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3156 SmallVectorImpl<SDValue> &MemOpChains,
3158 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3159 SDValue Arg = TailCallArgs[i].Arg;
3160 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3161 int FI = TailCallArgs[i].FrameIdx;
3162 // Store relative to framepointer.
3163 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3164 MachinePointerInfo::getFixedStack(FI),
3169 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3170 /// the appropriate stack slot for the tail call optimized function call.
3171 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3172 MachineFunction &MF,
3181 // Calculate the new stack slot for the return address.
3182 int SlotSize = isPPC64 ? 8 : 4;
3183 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3185 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3186 NewRetAddrLoc, true);
3187 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3188 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3189 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3190 MachinePointerInfo::getFixedStack(NewRetAddr),
3193 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3194 // slot as the FP is never overwritten.
3197 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3198 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3200 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3201 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3202 MachinePointerInfo::getFixedStack(NewFPIdx),
3209 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3210 /// the position of the argument.
3212 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3213 SDValue Arg, int SPDiff, unsigned ArgOffset,
3214 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3215 int Offset = ArgOffset + SPDiff;
3216 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3217 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3218 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3219 SDValue FIN = DAG.getFrameIndex(FI, VT);
3220 TailCallArgumentInfo Info;
3222 Info.FrameIdxOp = FIN;
3224 TailCallArguments.push_back(Info);
3227 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3228 /// stack slot. Returns the chain as result and the loaded frame pointers in
3229 /// LROpOut/FPOpout. Used when tail calling.
3230 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3238 // Load the LR and FP stack slot for later adjusting.
3239 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3240 LROpOut = getReturnAddrFrameIndex(DAG);
3241 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3242 false, false, false, 0);
3243 Chain = SDValue(LROpOut.getNode(), 1);
3245 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3246 // slot as the FP is never overwritten.
3248 FPOpOut = getFramePointerFrameIndex(DAG);
3249 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3250 false, false, false, 0);
3251 Chain = SDValue(FPOpOut.getNode(), 1);
3257 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3258 /// by "Src" to address "Dst" of size "Size". Alignment information is
3259 /// specified by the specific parameter attribute. The copy will be passed as
3260 /// a byval function parameter.
3261 /// Sometimes what we are copying is the end of a larger object, the part that
3262 /// does not fit in registers.
3264 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3265 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3267 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3268 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3269 false, false, MachinePointerInfo(),
3270 MachinePointerInfo());
3273 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3276 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3277 SDValue Arg, SDValue PtrOff, int SPDiff,
3278 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3279 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3280 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3282 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3287 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3289 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3290 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3291 DAG.getConstant(ArgOffset, PtrVT));
3293 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3294 MachinePointerInfo(), false, false, 0));
3295 // Calculate and remember argument location.
3296 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3301 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3302 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3303 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3304 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3305 MachineFunction &MF = DAG.getMachineFunction();
3307 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3308 // might overwrite each other in case of tail call optimization.
3309 SmallVector<SDValue, 8> MemOpChains2;
3310 // Do not flag preceding copytoreg stuff together with the following stuff.
3312 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3314 if (!MemOpChains2.empty())
3315 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3317 // Store the return address to the appropriate stack slot.
3318 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3319 isPPC64, isDarwinABI, dl);
3321 // Emit callseq_end just before tailcall node.
3322 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3323 DAG.getIntPtrConstant(0, true), InFlag, dl);
3324 InFlag = Chain.getValue(1);
3328 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3329 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3330 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3331 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3332 const PPCSubtarget &Subtarget) {
3334 bool isPPC64 = Subtarget.isPPC64();
3335 bool isSVR4ABI = Subtarget.isSVR4ABI();
3337 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3338 NodeTys.push_back(MVT::Other); // Returns a chain
3339 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3341 unsigned CallOpc = PPCISD::CALL;
3343 bool needIndirectCall = true;
3344 if (!isSVR4ABI || !isPPC64)
3345 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3346 // If this is an absolute destination address, use the munged value.
3347 Callee = SDValue(Dest, 0);
3348 needIndirectCall = false;
3351 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3352 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3353 // Use indirect calls for ALL functions calls in JIT mode, since the
3354 // far-call stubs may be outside relocation limits for a BL instruction.
3355 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3356 unsigned OpFlags = 0;
3357 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3358 (Subtarget.getTargetTriple().isMacOSX() &&
3359 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3360 (G->getGlobal()->isDeclaration() ||
3361 G->getGlobal()->isWeakForLinker())) {
3362 // PC-relative references to external symbols should go through $stub,
3363 // unless we're building with the leopard linker or later, which
3364 // automatically synthesizes these stubs.
3365 OpFlags = PPCII::MO_DARWIN_STUB;
3368 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3369 // every direct call is) turn it into a TargetGlobalAddress /
3370 // TargetExternalSymbol node so that legalize doesn't hack it.
3371 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3372 Callee.getValueType(),
3374 needIndirectCall = false;
3378 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3379 unsigned char OpFlags = 0;
3381 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3382 (Subtarget.getTargetTriple().isMacOSX() &&
3383 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3384 // PC-relative references to external symbols should go through $stub,
3385 // unless we're building with the leopard linker or later, which
3386 // automatically synthesizes these stubs.
3387 OpFlags = PPCII::MO_DARWIN_STUB;
3390 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3392 needIndirectCall = false;
3395 if (needIndirectCall) {
3396 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3397 // to do the call, we can't use PPCISD::CALL.
3398 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3400 if (isSVR4ABI && isPPC64) {
3401 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3402 // entry point, but to the function descriptor (the function entry point
3403 // address is part of the function descriptor though).
3404 // The function descriptor is a three doubleword structure with the
3405 // following fields: function entry point, TOC base address and
3406 // environment pointer.
3407 // Thus for a call through a function pointer, the following actions need
3409 // 1. Save the TOC of the caller in the TOC save area of its stack
3410 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3411 // 2. Load the address of the function entry point from the function
3413 // 3. Load the TOC of the callee from the function descriptor into r2.
3414 // 4. Load the environment pointer from the function descriptor into
3416 // 5. Branch to the function entry point address.
3417 // 6. On return of the callee, the TOC of the caller needs to be
3418 // restored (this is done in FinishCall()).
3420 // All those operations are flagged together to ensure that no other
3421 // operations can be scheduled in between. E.g. without flagging the
3422 // operations together, a TOC access in the caller could be scheduled
3423 // between the load of the callee TOC and the branch to the callee, which
3424 // results in the TOC access going through the TOC of the callee instead
3425 // of going through the TOC of the caller, which leads to incorrect code.
3427 // Load the address of the function entry point from the function
3429 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3430 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3431 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3432 Chain = LoadFuncPtr.getValue(1);
3433 InFlag = LoadFuncPtr.getValue(2);
3435 // Load environment pointer into r11.
3436 // Offset of the environment pointer within the function descriptor.
3437 SDValue PtrOff = DAG.getIntPtrConstant(16);
3439 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3440 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3442 Chain = LoadEnvPtr.getValue(1);
3443 InFlag = LoadEnvPtr.getValue(2);
3445 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3447 Chain = EnvVal.getValue(0);
3448 InFlag = EnvVal.getValue(1);
3450 // Load TOC of the callee into r2. We are using a target-specific load
3451 // with r2 hard coded, because the result of a target-independent load
3452 // would never go directly into r2, since r2 is a reserved register (which
3453 // prevents the register allocator from allocating it), resulting in an
3454 // additional register being allocated and an unnecessary move instruction
3456 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3457 SDValue TOCOff = DAG.getIntPtrConstant(8);
3458 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3459 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3461 Chain = LoadTOCPtr.getValue(0);
3462 InFlag = LoadTOCPtr.getValue(1);
3464 MTCTROps[0] = Chain;
3465 MTCTROps[1] = LoadFuncPtr;
3466 MTCTROps[2] = InFlag;
3469 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3470 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3471 InFlag = Chain.getValue(1);
3474 NodeTys.push_back(MVT::Other);
3475 NodeTys.push_back(MVT::Glue);
3476 Ops.push_back(Chain);
3477 CallOpc = PPCISD::BCTRL;
3478 Callee.setNode(nullptr);
3479 // Add use of X11 (holding environment pointer)
3480 if (isSVR4ABI && isPPC64)
3481 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3482 // Add CTR register as callee so a bctr can be emitted later.
3484 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3487 // If this is a direct call, pass the chain and the callee.
3488 if (Callee.getNode()) {
3489 Ops.push_back(Chain);
3490 Ops.push_back(Callee);
3492 // If this is a tail call add stack pointer delta.
3494 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3496 // Add argument registers to the end of the list so that they are known live
3498 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3499 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3500 RegsToPass[i].second.getValueType()));
3506 bool isLocalCall(const SDValue &Callee)
3508 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3509 return !G->getGlobal()->isDeclaration() &&
3510 !G->getGlobal()->isWeakForLinker();
3515 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3516 CallingConv::ID CallConv, bool isVarArg,
3517 const SmallVectorImpl<ISD::InputArg> &Ins,
3518 SDLoc dl, SelectionDAG &DAG,
3519 SmallVectorImpl<SDValue> &InVals) const {
3521 SmallVector<CCValAssign, 16> RVLocs;
3522 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3523 getTargetMachine(), RVLocs, *DAG.getContext());
3524 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3526 // Copy all of the result registers out of their specified physreg.
3527 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3528 CCValAssign &VA = RVLocs[i];
3529 assert(VA.isRegLoc() && "Can only return in registers!");
3531 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3532 VA.getLocReg(), VA.getLocVT(), InFlag);
3533 Chain = Val.getValue(1);
3534 InFlag = Val.getValue(2);
3536 switch (VA.getLocInfo()) {
3537 default: llvm_unreachable("Unknown loc info!");
3538 case CCValAssign::Full: break;
3539 case CCValAssign::AExt:
3540 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3542 case CCValAssign::ZExt:
3543 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3544 DAG.getValueType(VA.getValVT()));
3545 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3547 case CCValAssign::SExt:
3548 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3549 DAG.getValueType(VA.getValVT()));
3550 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3554 InVals.push_back(Val);
3561 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3562 bool isTailCall, bool isVarArg,
3564 SmallVector<std::pair<unsigned, SDValue>, 8>
3566 SDValue InFlag, SDValue Chain,
3568 int SPDiff, unsigned NumBytes,
3569 const SmallVectorImpl<ISD::InputArg> &Ins,
3570 SmallVectorImpl<SDValue> &InVals) const {
3571 std::vector<EVT> NodeTys;
3572 SmallVector<SDValue, 8> Ops;
3573 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3574 isTailCall, RegsToPass, Ops, NodeTys,
3577 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3578 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3579 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3581 // When performing tail call optimization the callee pops its arguments off
3582 // the stack. Account for this here so these bytes can be pushed back on in
3583 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3584 int BytesCalleePops =
3585 (CallConv == CallingConv::Fast &&
3586 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3588 // Add a register mask operand representing the call-preserved registers.
3589 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3590 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3591 assert(Mask && "Missing call preserved mask for calling convention");
3592 Ops.push_back(DAG.getRegisterMask(Mask));
3594 if (InFlag.getNode())
3595 Ops.push_back(InFlag);
3599 assert(((Callee.getOpcode() == ISD::Register &&
3600 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3601 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3602 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3603 isa<ConstantSDNode>(Callee)) &&
3604 "Expecting an global address, external symbol, absolute value or register");
3606 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3609 // Add a NOP immediately after the branch instruction when using the 64-bit
3610 // SVR4 ABI. At link time, if caller and callee are in a different module and
3611 // thus have a different TOC, the call will be replaced with a call to a stub
3612 // function which saves the current TOC, loads the TOC of the callee and
3613 // branches to the callee. The NOP will be replaced with a load instruction
3614 // which restores the TOC of the caller from the TOC save slot of the current
3615 // stack frame. If caller and callee belong to the same module (and have the
3616 // same TOC), the NOP will remain unchanged.
3618 bool needsTOCRestore = false;
3619 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3620 if (CallOpc == PPCISD::BCTRL) {
3621 // This is a call through a function pointer.
3622 // Restore the caller TOC from the save area into R2.
3623 // See PrepareCall() for more information about calls through function
3624 // pointers in the 64-bit SVR4 ABI.
3625 // We are using a target-specific load with r2 hard coded, because the
3626 // result of a target-independent load would never go directly into r2,
3627 // since r2 is a reserved register (which prevents the register allocator
3628 // from allocating it), resulting in an additional register being
3629 // allocated and an unnecessary move instruction being generated.
3630 needsTOCRestore = true;
3631 } else if ((CallOpc == PPCISD::CALL) &&
3632 (!isLocalCall(Callee) ||
3633 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3634 // Otherwise insert NOP for non-local calls.
3635 CallOpc = PPCISD::CALL_NOP;
3639 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3640 InFlag = Chain.getValue(1);
3642 if (needsTOCRestore) {
3643 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3644 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3645 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3646 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset();
3647 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3648 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3649 Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag);
3650 InFlag = Chain.getValue(1);
3653 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3654 DAG.getIntPtrConstant(BytesCalleePops, true),
3657 InFlag = Chain.getValue(1);
3659 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3660 Ins, dl, DAG, InVals);
3664 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3665 SmallVectorImpl<SDValue> &InVals) const {
3666 SelectionDAG &DAG = CLI.DAG;
3668 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3669 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3670 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3671 SDValue Chain = CLI.Chain;
3672 SDValue Callee = CLI.Callee;
3673 bool &isTailCall = CLI.IsTailCall;
3674 CallingConv::ID CallConv = CLI.CallConv;
3675 bool isVarArg = CLI.IsVarArg;
3678 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3681 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3682 report_fatal_error("failed to perform tail call elimination on a call "
3683 "site marked musttail");
3685 if (Subtarget.isSVR4ABI()) {
3686 if (Subtarget.isPPC64())
3687 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3688 isTailCall, Outs, OutVals, Ins,
3691 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3692 isTailCall, Outs, OutVals, Ins,
3696 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3697 isTailCall, Outs, OutVals, Ins,
3702 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3703 CallingConv::ID CallConv, bool isVarArg,
3705 const SmallVectorImpl<ISD::OutputArg> &Outs,
3706 const SmallVectorImpl<SDValue> &OutVals,
3707 const SmallVectorImpl<ISD::InputArg> &Ins,
3708 SDLoc dl, SelectionDAG &DAG,
3709 SmallVectorImpl<SDValue> &InVals) const {
3710 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3711 // of the 32-bit SVR4 ABI stack frame layout.
3713 assert((CallConv == CallingConv::C ||
3714 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3716 unsigned PtrByteSize = 4;
3718 MachineFunction &MF = DAG.getMachineFunction();
3720 // Mark this function as potentially containing a function that contains a
3721 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3722 // and restoring the callers stack pointer in this functions epilog. This is
3723 // done because by tail calling the called function might overwrite the value
3724 // in this function's (MF) stack pointer stack slot 0(SP).
3725 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3726 CallConv == CallingConv::Fast)
3727 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3729 // Count how many bytes are to be pushed on the stack, including the linkage
3730 // area, parameter list area and the part of the local variable space which
3731 // contains copies of aggregates which are passed by value.
3733 // Assign locations to all of the outgoing arguments.
3734 SmallVector<CCValAssign, 16> ArgLocs;
3735 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3736 getTargetMachine(), ArgLocs, *DAG.getContext());
3738 // Reserve space for the linkage area on the stack.
3739 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3742 // Handle fixed and variable vector arguments differently.
3743 // Fixed vector arguments go into registers as long as registers are
3744 // available. Variable vector arguments always go into memory.
3745 unsigned NumArgs = Outs.size();
3747 for (unsigned i = 0; i != NumArgs; ++i) {
3748 MVT ArgVT = Outs[i].VT;
3749 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3752 if (Outs[i].IsFixed) {
3753 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3756 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3762 errs() << "Call operand #" << i << " has unhandled type "
3763 << EVT(ArgVT).getEVTString() << "\n";
3765 llvm_unreachable(nullptr);
3769 // All arguments are treated the same.
3770 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3773 // Assign locations to all of the outgoing aggregate by value arguments.
3774 SmallVector<CCValAssign, 16> ByValArgLocs;
3775 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3776 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3778 // Reserve stack space for the allocations in CCInfo.
3779 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3781 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3783 // Size of the linkage area, parameter list area and the part of the local
3784 // space variable where copies of aggregates which are passed by value are
3786 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3788 // Calculate by how many bytes the stack has to be adjusted in case of tail
3789 // call optimization.
3790 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3792 // Adjust the stack pointer for the new arguments...
3793 // These operations are automatically eliminated by the prolog/epilog pass
3794 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3796 SDValue CallSeqStart = Chain;
3798 // Load the return address and frame pointer so it can be moved somewhere else
3801 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3804 // Set up a copy of the stack pointer for use loading and storing any
3805 // arguments that may not fit in the registers available for argument
3807 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3809 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3810 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3811 SmallVector<SDValue, 8> MemOpChains;
3813 bool seenFloatArg = false;
3814 // Walk the register/memloc assignments, inserting copies/loads.
3815 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3818 CCValAssign &VA = ArgLocs[i];
3819 SDValue Arg = OutVals[i];
3820 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3822 if (Flags.isByVal()) {
3823 // Argument is an aggregate which is passed by value, thus we need to
3824 // create a copy of it in the local variable space of the current stack
3825 // frame (which is the stack frame of the caller) and pass the address of
3826 // this copy to the callee.
3827 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3828 CCValAssign &ByValVA = ByValArgLocs[j++];
3829 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3831 // Memory reserved in the local variable space of the callers stack frame.
3832 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3834 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3835 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3837 // Create a copy of the argument in the local area of the current
3839 SDValue MemcpyCall =
3840 CreateCopyOfByValArgument(Arg, PtrOff,
3841 CallSeqStart.getNode()->getOperand(0),
3844 // This must go outside the CALLSEQ_START..END.
3845 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3846 CallSeqStart.getNode()->getOperand(1),
3848 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3849 NewCallSeqStart.getNode());
3850 Chain = CallSeqStart = NewCallSeqStart;
3852 // Pass the address of the aggregate copy on the stack either in a
3853 // physical register or in the parameter list area of the current stack
3854 // frame to the callee.
3858 if (VA.isRegLoc()) {
3859 if (Arg.getValueType() == MVT::i1)
3860 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
3862 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3863 // Put argument in a physical register.
3864 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3866 // Put argument in the parameter list area of the current stack frame.
3867 assert(VA.isMemLoc());
3868 unsigned LocMemOffset = VA.getLocMemOffset();
3871 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3872 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3874 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3875 MachinePointerInfo(),
3878 // Calculate and remember argument location.
3879 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3885 if (!MemOpChains.empty())
3886 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3888 // Build a sequence of copy-to-reg nodes chained together with token chain
3889 // and flag operands which copy the outgoing args into the appropriate regs.
3891 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3892 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3893 RegsToPass[i].second, InFlag);
3894 InFlag = Chain.getValue(1);
3897 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3900 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3901 SDValue Ops[] = { Chain, InFlag };
3903 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3904 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
3906 InFlag = Chain.getValue(1);
3910 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3911 false, TailCallArguments);
3913 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3914 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3918 // Copy an argument into memory, being careful to do this outside the
3919 // call sequence for the call to which the argument belongs.
3921 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3922 SDValue CallSeqStart,
3923 ISD::ArgFlagsTy Flags,
3926 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3927 CallSeqStart.getNode()->getOperand(0),
3929 // The MEMCPY must go outside the CALLSEQ_START..END.
3930 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3931 CallSeqStart.getNode()->getOperand(1),
3933 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3934 NewCallSeqStart.getNode());
3935 return NewCallSeqStart;
3939 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3940 CallingConv::ID CallConv, bool isVarArg,
3942 const SmallVectorImpl<ISD::OutputArg> &Outs,
3943 const SmallVectorImpl<SDValue> &OutVals,
3944 const SmallVectorImpl<ISD::InputArg> &Ins,
3945 SDLoc dl, SelectionDAG &DAG,
3946 SmallVectorImpl<SDValue> &InVals) const {
3948 bool isLittleEndian = Subtarget.isLittleEndian();
3949 unsigned NumOps = Outs.size();
3951 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3952 unsigned PtrByteSize = 8;
3954 MachineFunction &MF = DAG.getMachineFunction();
3956 // Mark this function as potentially containing a function that contains a
3957 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3958 // and restoring the callers stack pointer in this functions epilog. This is
3959 // done because by tail calling the called function might overwrite the value
3960 // in this function's (MF) stack pointer stack slot 0(SP).
3961 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3962 CallConv == CallingConv::Fast)
3963 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3965 // Count how many bytes are to be pushed on the stack, including the linkage
3966 // area, and parameter passing area. We start with at least 48 bytes, which
3967 // is reserved space for [SP][CR][LR][3 x unused].
3968 unsigned NumBytes = PPCFrameLowering::getLinkageSize(true, false);
3970 // Add up all the space actually used.
3971 for (unsigned i = 0; i != NumOps; ++i) {
3972 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3973 EVT ArgVT = Outs[i].VT;
3975 // Altivec parameters are padded to a 16 byte boundary.
3976 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3977 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3978 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
3979 NumBytes = ((NumBytes+15)/16)*16;
3981 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3984 // The prolog code of the callee may store up to 8 GPR argument registers to
3985 // the stack, allowing va_start to index over them in memory if its varargs.
3986 // Because we cannot tell if this is needed on the caller side, we have to
3987 // conservatively assume that it is needed. As such, make sure we have at
3988 // least enough stack space for the caller to store the 8 GPRs.
3989 NumBytes = std::max(NumBytes,
3990 PPCFrameLowering::getMinCallFrameSize(true, false));
3992 // Tail call needs the stack to be aligned.
3993 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3994 CallConv == CallingConv::Fast)
3995 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
3997 // Calculate by how many bytes the stack has to be adjusted in case of tail
3998 // call optimization.
3999 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4001 // To protect arguments on the stack from being clobbered in a tail call,
4002 // force all the loads to happen before doing any other lowering.
4004 Chain = DAG.getStackArgumentTokenFactor(Chain);
4006 // Adjust the stack pointer for the new arguments...
4007 // These operations are automatically eliminated by the prolog/epilog pass
4008 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4010 SDValue CallSeqStart = Chain;
4012 // Load the return address and frame pointer so it can be move somewhere else
4015 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4018 // Set up a copy of the stack pointer for use loading and storing any
4019 // arguments that may not fit in the registers available for argument
4021 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4023 // Figure out which arguments are going to go in registers, and which in
4024 // memory. Also, if this is a vararg function, floating point operations
4025 // must be stored to our stack, and loaded into integer regs as well, if
4026 // any integer regs are available for argument passing.
4027 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, false);
4028 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4030 static const MCPhysReg GPR[] = {
4031 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4032 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4034 static const MCPhysReg *FPR = GetFPR();
4036 static const MCPhysReg VR[] = {
4037 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4038 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4040 static const MCPhysReg VSRH[] = {
4041 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4042 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4045 const unsigned NumGPRs = array_lengthof(GPR);
4046 const unsigned NumFPRs = 13;
4047 const unsigned NumVRs = array_lengthof(VR);
4049 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4050 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4052 SmallVector<SDValue, 8> MemOpChains;
4053 for (unsigned i = 0; i != NumOps; ++i) {
4054 SDValue Arg = OutVals[i];
4055 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4057 // PtrOff will be used to store the current argument to the stack if a
4058 // register cannot be found for it.
4061 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4063 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4065 // Promote integers to 64-bit values.
4066 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4067 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4068 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4069 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4072 // FIXME memcpy is used way more than necessary. Correctness first.
4073 // Note: "by value" is code for passing a structure by value, not
4075 if (Flags.isByVal()) {
4076 // Note: Size includes alignment padding, so
4077 // struct x { short a; char b; }
4078 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4079 // These are the proper values we need for right-justifying the
4080 // aggregate in a parameter register.
4081 unsigned Size = Flags.getByValSize();
4083 // An empty aggregate parameter takes up no storage and no
4088 unsigned BVAlign = Flags.getByValAlign();
4090 if (BVAlign % PtrByteSize != 0)
4092 "ByVal alignment is not a multiple of the pointer size");
4094 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
4097 // All aggregates smaller than 8 bytes must be passed right-justified.
4098 if (Size==1 || Size==2 || Size==4) {
4099 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4100 if (GPR_idx != NumGPRs) {
4101 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4102 MachinePointerInfo(), VT,
4104 MemOpChains.push_back(Load.getValue(1));
4105 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4107 ArgOffset += PtrByteSize;
4112 if (GPR_idx == NumGPRs && Size < 8) {
4113 SDValue AddPtr = PtrOff;
4114 if (!isLittleEndian) {
4115 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4116 PtrOff.getValueType());
4117 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4119 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4122 ArgOffset += PtrByteSize;
4125 // Copy entire object into memory. There are cases where gcc-generated
4126 // code assumes it is there, even if it could be put entirely into
4127 // registers. (This is not what the doc says.)
4129 // FIXME: The above statement is likely due to a misunderstanding of the
4130 // documents. All arguments must be copied into the parameter area BY
4131 // THE CALLEE in the event that the callee takes the address of any
4132 // formal argument. That has not yet been implemented. However, it is
4133 // reasonable to use the stack area as a staging area for the register
4136 // Skip this for small aggregates, as we will use the same slot for a
4137 // right-justified copy, below.
4139 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4143 // When a register is available, pass a small aggregate right-justified.
4144 if (Size < 8 && GPR_idx != NumGPRs) {
4145 // The easiest way to get this right-justified in a register
4146 // is to copy the structure into the rightmost portion of a
4147 // local variable slot, then load the whole slot into the
4149 // FIXME: The memcpy seems to produce pretty awful code for
4150 // small aggregates, particularly for packed ones.
4151 // FIXME: It would be preferable to use the slot in the
4152 // parameter save area instead of a new local variable.
4153 SDValue AddPtr = PtrOff;
4154 if (!isLittleEndian) {
4155 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4156 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4158 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4162 // Load the slot into the register.
4163 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4164 MachinePointerInfo(),
4165 false, false, false, 0);
4166 MemOpChains.push_back(Load.getValue(1));
4167 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4169 // Done with this argument.
4170 ArgOffset += PtrByteSize;
4174 // For aggregates larger than PtrByteSize, copy the pieces of the
4175 // object that fit into registers from the parameter save area.
4176 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4177 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4178 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4179 if (GPR_idx != NumGPRs) {
4180 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4181 MachinePointerInfo(),
4182 false, false, false, 0);
4183 MemOpChains.push_back(Load.getValue(1));
4184 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4185 ArgOffset += PtrByteSize;
4187 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4194 switch (Arg.getSimpleValueType().SimpleTy) {
4195 default: llvm_unreachable("Unexpected ValueType for argument!");
4199 if (GPR_idx != NumGPRs) {
4200 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4202 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4203 true, isTailCall, false, MemOpChains,
4204 TailCallArguments, dl);
4206 ArgOffset += PtrByteSize;
4210 if (FPR_idx != NumFPRs) {
4211 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4214 // A single float or an aggregate containing only a single float
4215 // must be passed right-justified in the stack doubleword, and
4216 // in the GPR, if one is available.
4218 if (Arg.getSimpleValueType().SimpleTy == MVT::f32 &&
4220 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4221 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4225 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
4226 MachinePointerInfo(), false, false, 0);
4227 MemOpChains.push_back(Store);
4229 // Float varargs are always shadowed in available integer registers
4230 if (GPR_idx != NumGPRs) {
4231 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4232 MachinePointerInfo(), false, false,
4234 MemOpChains.push_back(Load.getValue(1));
4235 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4237 } else if (GPR_idx != NumGPRs)
4238 // If we have any FPRs remaining, we may also have GPRs remaining.
4241 // Single-precision floating-point values are mapped to the
4242 // second (rightmost) word of the stack doubleword.
4243 if (Arg.getValueType() == MVT::f32 && !isLittleEndian) {
4244 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4245 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4248 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4249 true, isTailCall, false, MemOpChains,
4250 TailCallArguments, dl);
4260 // Vectors are aligned to a 16-byte boundary in the argument save area.
4261 while (ArgOffset % 16 !=0) {
4262 ArgOffset += PtrByteSize;
4263 if (GPR_idx != NumGPRs)
4267 // For a varargs call, named arguments go into VRs or on the stack as
4268 // usual; unnamed arguments always go to the stack or the corresponding
4269 // GPRs when within range. For now, we always put the value in both
4270 // locations (or even all three).
4272 // We could elide this store in the case where the object fits
4273 // entirely in R registers. Maybe later.
4274 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4275 DAG.getConstant(ArgOffset, PtrVT));
4276 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4277 MachinePointerInfo(), false, false, 0);
4278 MemOpChains.push_back(Store);
4279 if (VR_idx != NumVRs) {
4280 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4281 MachinePointerInfo(),
4282 false, false, false, 0);
4283 MemOpChains.push_back(Load.getValue(1));
4285 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4286 Arg.getSimpleValueType() == MVT::v2i64) ?
4287 VSRH[VR_idx] : VR[VR_idx];
4290 RegsToPass.push_back(std::make_pair(VReg, Load));
4293 for (unsigned i=0; i<16; i+=PtrByteSize) {
4294 if (GPR_idx == NumGPRs)
4296 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4297 DAG.getConstant(i, PtrVT));
4298 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4299 false, false, false, 0);
4300 MemOpChains.push_back(Load.getValue(1));
4301 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4306 // Non-varargs Altivec params go into VRs or on the stack.
4307 if (VR_idx != NumVRs) {
4308 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4309 Arg.getSimpleValueType() == MVT::v2i64) ?
4310 VSRH[VR_idx] : VR[VR_idx];
4313 RegsToPass.push_back(std::make_pair(VReg, Arg));
4315 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4316 true, isTailCall, true, MemOpChains,
4317 TailCallArguments, dl);
4320 GPR_idx = std::min(GPR_idx + 2, NumGPRs);
4325 if (!MemOpChains.empty())
4326 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4328 // Check if this is an indirect call (MTCTR/BCTRL).
4329 // See PrepareCall() for more information about calls through function
4330 // pointers in the 64-bit SVR4 ABI.
4332 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4333 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4334 // Load r2 into a virtual register and store it to the TOC save area.
4335 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4336 // TOC save area offset.
4337 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset();
4338 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4339 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4340 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4344 // Build a sequence of copy-to-reg nodes chained together with token chain
4345 // and flag operands which copy the outgoing args into the appropriate regs.
4347 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4348 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4349 RegsToPass[i].second, InFlag);
4350 InFlag = Chain.getValue(1);
4354 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4355 FPOp, true, TailCallArguments);
4357 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4358 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4363 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4364 CallingConv::ID CallConv, bool isVarArg,
4366 const SmallVectorImpl<ISD::OutputArg> &Outs,
4367 const SmallVectorImpl<SDValue> &OutVals,
4368 const SmallVectorImpl<ISD::InputArg> &Ins,
4369 SDLoc dl, SelectionDAG &DAG,
4370 SmallVectorImpl<SDValue> &InVals) const {
4372 unsigned NumOps = Outs.size();
4374 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4375 bool isPPC64 = PtrVT == MVT::i64;
4376 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4378 MachineFunction &MF = DAG.getMachineFunction();
4380 // Mark this function as potentially containing a function that contains a
4381 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4382 // and restoring the callers stack pointer in this functions epilog. This is
4383 // done because by tail calling the called function might overwrite the value
4384 // in this function's (MF) stack pointer stack slot 0(SP).
4385 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4386 CallConv == CallingConv::Fast)
4387 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4389 // Count how many bytes are to be pushed on the stack, including the linkage
4390 // area, and parameter passing area. We start with 24/48 bytes, which is
4391 // prereserved space for [SP][CR][LR][3 x unused].
4392 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
4394 // Add up all the space actually used.
4395 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4396 // they all go in registers, but we must reserve stack space for them for
4397 // possible use by the caller. In varargs or 64-bit calls, parameters are
4398 // assigned stack space in order, with padding so Altivec parameters are
4400 unsigned nAltivecParamsAtEnd = 0;
4401 for (unsigned i = 0; i != NumOps; ++i) {
4402 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4403 EVT ArgVT = Outs[i].VT;
4404 // Varargs Altivec parameters are padded to a 16 byte boundary.
4405 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4406 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4407 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4408 if (!isVarArg && !isPPC64) {
4409 // Non-varargs Altivec parameters go after all the non-Altivec
4410 // parameters; handle those later so we know how much padding we need.
4411 nAltivecParamsAtEnd++;
4414 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4415 NumBytes = ((NumBytes+15)/16)*16;
4417 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4420 // Allow for Altivec parameters at the end, if needed.
4421 if (nAltivecParamsAtEnd) {
4422 NumBytes = ((NumBytes+15)/16)*16;
4423 NumBytes += 16*nAltivecParamsAtEnd;
4426 // The prolog code of the callee may store up to 8 GPR argument registers to
4427 // the stack, allowing va_start to index over them in memory if its varargs.
4428 // Because we cannot tell if this is needed on the caller side, we have to
4429 // conservatively assume that it is needed. As such, make sure we have at
4430 // least enough stack space for the caller to store the 8 GPRs.
4431 NumBytes = std::max(NumBytes,
4432 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
4434 // Tail call needs the stack to be aligned.
4435 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4436 CallConv == CallingConv::Fast)
4437 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4439 // Calculate by how many bytes the stack has to be adjusted in case of tail
4440 // call optimization.
4441 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4443 // To protect arguments on the stack from being clobbered in a tail call,
4444 // force all the loads to happen before doing any other lowering.
4446 Chain = DAG.getStackArgumentTokenFactor(Chain);
4448 // Adjust the stack pointer for the new arguments...
4449 // These operations are automatically eliminated by the prolog/epilog pass
4450 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4452 SDValue CallSeqStart = Chain;
4454 // Load the return address and frame pointer so it can be move somewhere else
4457 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4460 // Set up a copy of the stack pointer for use loading and storing any
4461 // arguments that may not fit in the registers available for argument
4465 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4467 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4469 // Figure out which arguments are going to go in registers, and which in
4470 // memory. Also, if this is a vararg function, floating point operations
4471 // must be stored to our stack, and loaded into integer regs as well, if
4472 // any integer regs are available for argument passing.
4473 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4474 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4476 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4477 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4478 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4480 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4481 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4482 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4484 static const MCPhysReg *FPR = GetFPR();
4486 static const MCPhysReg VR[] = {
4487 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4488 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4490 const unsigned NumGPRs = array_lengthof(GPR_32);
4491 const unsigned NumFPRs = 13;
4492 const unsigned NumVRs = array_lengthof(VR);
4494 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4496 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4497 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4499 SmallVector<SDValue, 8> MemOpChains;
4500 for (unsigned i = 0; i != NumOps; ++i) {
4501 SDValue Arg = OutVals[i];
4502 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4504 // PtrOff will be used to store the current argument to the stack if a
4505 // register cannot be found for it.
4508 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4510 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4512 // On PPC64, promote integers to 64-bit values.
4513 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4514 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4515 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4516 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4519 // FIXME memcpy is used way more than necessary. Correctness first.
4520 // Note: "by value" is code for passing a structure by value, not
4522 if (Flags.isByVal()) {
4523 unsigned Size = Flags.getByValSize();
4524 // Very small objects are passed right-justified. Everything else is
4525 // passed left-justified.
4526 if (Size==1 || Size==2) {
4527 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4528 if (GPR_idx != NumGPRs) {
4529 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4530 MachinePointerInfo(), VT,
4532 MemOpChains.push_back(Load.getValue(1));
4533 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4535 ArgOffset += PtrByteSize;
4537 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4538 PtrOff.getValueType());
4539 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4540 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4543 ArgOffset += PtrByteSize;
4547 // Copy entire object into memory. There are cases where gcc-generated
4548 // code assumes it is there, even if it could be put entirely into
4549 // registers. (This is not what the doc says.)
4550 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4554 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4555 // copy the pieces of the object that fit into registers from the
4556 // parameter save area.
4557 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4558 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4559 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4560 if (GPR_idx != NumGPRs) {
4561 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4562 MachinePointerInfo(),
4563 false, false, false, 0);
4564 MemOpChains.push_back(Load.getValue(1));
4565 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4566 ArgOffset += PtrByteSize;
4568 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4575 switch (Arg.getSimpleValueType().SimpleTy) {
4576 default: llvm_unreachable("Unexpected ValueType for argument!");
4580 if (GPR_idx != NumGPRs) {
4581 if (Arg.getValueType() == MVT::i1)
4582 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4584 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4586 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4587 isPPC64, isTailCall, false, MemOpChains,
4588 TailCallArguments, dl);
4590 ArgOffset += PtrByteSize;
4594 if (FPR_idx != NumFPRs) {
4595 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4598 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4599 MachinePointerInfo(), false, false, 0);
4600 MemOpChains.push_back(Store);
4602 // Float varargs are always shadowed in available integer registers
4603 if (GPR_idx != NumGPRs) {
4604 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4605 MachinePointerInfo(), false, false,
4607 MemOpChains.push_back(Load.getValue(1));
4608 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4610 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4611 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4612 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4613 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4614 MachinePointerInfo(),
4615 false, false, false, 0);
4616 MemOpChains.push_back(Load.getValue(1));
4617 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4620 // If we have any FPRs remaining, we may also have GPRs remaining.
4621 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4623 if (GPR_idx != NumGPRs)
4625 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4626 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4630 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4631 isPPC64, isTailCall, false, MemOpChains,
4632 TailCallArguments, dl);
4636 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4643 // These go aligned on the stack, or in the corresponding R registers
4644 // when within range. The Darwin PPC ABI doc claims they also go in
4645 // V registers; in fact gcc does this only for arguments that are
4646 // prototyped, not for those that match the ... We do it for all
4647 // arguments, seems to work.
4648 while (ArgOffset % 16 !=0) {
4649 ArgOffset += PtrByteSize;
4650 if (GPR_idx != NumGPRs)
4653 // We could elide this store in the case where the object fits
4654 // entirely in R registers. Maybe later.
4655 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4656 DAG.getConstant(ArgOffset, PtrVT));
4657 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4658 MachinePointerInfo(), false, false, 0);
4659 MemOpChains.push_back(Store);
4660 if (VR_idx != NumVRs) {
4661 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4662 MachinePointerInfo(),
4663 false, false, false, 0);
4664 MemOpChains.push_back(Load.getValue(1));
4665 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4668 for (unsigned i=0; i<16; i+=PtrByteSize) {
4669 if (GPR_idx == NumGPRs)
4671 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4672 DAG.getConstant(i, PtrVT));
4673 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4674 false, false, false, 0);
4675 MemOpChains.push_back(Load.getValue(1));
4676 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4681 // Non-varargs Altivec params generally go in registers, but have
4682 // stack space allocated at the end.
4683 if (VR_idx != NumVRs) {
4684 // Doesn't have GPR space allocated.
4685 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4686 } else if (nAltivecParamsAtEnd==0) {
4687 // We are emitting Altivec params in order.
4688 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4689 isPPC64, isTailCall, true, MemOpChains,
4690 TailCallArguments, dl);
4696 // If all Altivec parameters fit in registers, as they usually do,
4697 // they get stack space following the non-Altivec parameters. We
4698 // don't track this here because nobody below needs it.
4699 // If there are more Altivec parameters than fit in registers emit
4701 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4703 // Offset is aligned; skip 1st 12 params which go in V registers.
4704 ArgOffset = ((ArgOffset+15)/16)*16;
4706 for (unsigned i = 0; i != NumOps; ++i) {
4707 SDValue Arg = OutVals[i];
4708 EVT ArgType = Outs[i].VT;
4709 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4710 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4713 // We are emitting Altivec params in order.
4714 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4715 isPPC64, isTailCall, true, MemOpChains,
4716 TailCallArguments, dl);
4723 if (!MemOpChains.empty())
4724 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4726 // On Darwin, R12 must contain the address of an indirect callee. This does
4727 // not mean the MTCTR instruction must use R12; it's easier to model this as
4728 // an extra parameter, so do that.
4730 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4731 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4732 !isBLACompatibleAddress(Callee, DAG))
4733 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4734 PPC::R12), Callee));
4736 // Build a sequence of copy-to-reg nodes chained together with token chain
4737 // and flag operands which copy the outgoing args into the appropriate regs.
4739 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4740 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4741 RegsToPass[i].second, InFlag);
4742 InFlag = Chain.getValue(1);
4746 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4747 FPOp, true, TailCallArguments);
4749 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4750 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4755 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4756 MachineFunction &MF, bool isVarArg,
4757 const SmallVectorImpl<ISD::OutputArg> &Outs,
4758 LLVMContext &Context) const {
4759 SmallVector<CCValAssign, 16> RVLocs;
4760 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4762 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4766 PPCTargetLowering::LowerReturn(SDValue Chain,
4767 CallingConv::ID CallConv, bool isVarArg,
4768 const SmallVectorImpl<ISD::OutputArg> &Outs,
4769 const SmallVectorImpl<SDValue> &OutVals,
4770 SDLoc dl, SelectionDAG &DAG) const {
4772 SmallVector<CCValAssign, 16> RVLocs;
4773 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4774 getTargetMachine(), RVLocs, *DAG.getContext());
4775 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4778 SmallVector<SDValue, 4> RetOps(1, Chain);
4780 // Copy the result values into the output registers.
4781 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4782 CCValAssign &VA = RVLocs[i];
4783 assert(VA.isRegLoc() && "Can only return in registers!");
4785 SDValue Arg = OutVals[i];
4787 switch (VA.getLocInfo()) {
4788 default: llvm_unreachable("Unknown loc info!");
4789 case CCValAssign::Full: break;
4790 case CCValAssign::AExt:
4791 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4793 case CCValAssign::ZExt:
4794 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4796 case CCValAssign::SExt:
4797 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4801 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4802 Flag = Chain.getValue(1);
4803 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4806 RetOps[0] = Chain; // Update chain.
4808 // Add the flag if we have it.
4810 RetOps.push_back(Flag);
4812 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
4815 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4816 const PPCSubtarget &Subtarget) const {
4817 // When we pop the dynamic allocation we need to restore the SP link.
4820 // Get the corect type for pointers.
4821 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4823 // Construct the stack pointer operand.
4824 bool isPPC64 = Subtarget.isPPC64();
4825 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4826 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4828 // Get the operands for the STACKRESTORE.
4829 SDValue Chain = Op.getOperand(0);
4830 SDValue SaveSP = Op.getOperand(1);
4832 // Load the old link SP.
4833 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4834 MachinePointerInfo(),
4835 false, false, false, 0);
4837 // Restore the stack pointer.
4838 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4840 // Store the old link SP.
4841 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4848 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4849 MachineFunction &MF = DAG.getMachineFunction();
4850 bool isPPC64 = Subtarget.isPPC64();
4851 bool isDarwinABI = Subtarget.isDarwinABI();
4852 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4854 // Get current frame pointer save index. The users of this index will be
4855 // primarily DYNALLOC instructions.
4856 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4857 int RASI = FI->getReturnAddrSaveIndex();
4859 // If the frame pointer save index hasn't been defined yet.
4861 // Find out what the fix offset of the frame pointer save area.
4862 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4863 // Allocate the frame index for frame pointer save area.
4864 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4866 FI->setReturnAddrSaveIndex(RASI);
4868 return DAG.getFrameIndex(RASI, PtrVT);
4872 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4873 MachineFunction &MF = DAG.getMachineFunction();
4874 bool isPPC64 = Subtarget.isPPC64();
4875 bool isDarwinABI = Subtarget.isDarwinABI();
4876 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4878 // Get current frame pointer save index. The users of this index will be
4879 // primarily DYNALLOC instructions.
4880 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4881 int FPSI = FI->getFramePointerSaveIndex();
4883 // If the frame pointer save index hasn't been defined yet.
4885 // Find out what the fix offset of the frame pointer save area.
4886 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4889 // Allocate the frame index for frame pointer save area.
4890 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4892 FI->setFramePointerSaveIndex(FPSI);
4894 return DAG.getFrameIndex(FPSI, PtrVT);
4897 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4899 const PPCSubtarget &Subtarget) const {
4901 SDValue Chain = Op.getOperand(0);
4902 SDValue Size = Op.getOperand(1);
4905 // Get the corect type for pointers.
4906 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4908 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4909 DAG.getConstant(0, PtrVT), Size);
4910 // Construct a node for the frame pointer save index.
4911 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4912 // Build a DYNALLOC node.
4913 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4914 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4915 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
4918 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4919 SelectionDAG &DAG) const {
4921 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4922 DAG.getVTList(MVT::i32, MVT::Other),
4923 Op.getOperand(0), Op.getOperand(1));
4926 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4927 SelectionDAG &DAG) const {
4929 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4930 Op.getOperand(0), Op.getOperand(1));
4933 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
4934 assert(Op.getValueType() == MVT::i1 &&
4935 "Custom lowering only for i1 loads");
4937 // First, load 8 bits into 32 bits, then truncate to 1 bit.
4940 LoadSDNode *LD = cast<LoadSDNode>(Op);
4942 SDValue Chain = LD->getChain();
4943 SDValue BasePtr = LD->getBasePtr();
4944 MachineMemOperand *MMO = LD->getMemOperand();
4946 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
4947 BasePtr, MVT::i8, MMO);
4948 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
4950 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
4951 return DAG.getMergeValues(Ops, dl);
4954 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
4955 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
4956 "Custom lowering only for i1 stores");
4958 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
4961 StoreSDNode *ST = cast<StoreSDNode>(Op);
4963 SDValue Chain = ST->getChain();
4964 SDValue BasePtr = ST->getBasePtr();
4965 SDValue Value = ST->getValue();
4966 MachineMemOperand *MMO = ST->getMemOperand();
4968 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
4969 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
4972 // FIXME: Remove this once the ANDI glue bug is fixed:
4973 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
4974 assert(Op.getValueType() == MVT::i1 &&
4975 "Custom lowering only for i1 results");
4978 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
4982 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4984 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4985 // Not FP? Not a fsel.
4986 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4987 !Op.getOperand(2).getValueType().isFloatingPoint())
4990 // We might be able to do better than this under some circumstances, but in
4991 // general, fsel-based lowering of select is a finite-math-only optimization.
4992 // For more information, see section F.3 of the 2.06 ISA specification.
4993 if (!DAG.getTarget().Options.NoInfsFPMath ||
4994 !DAG.getTarget().Options.NoNaNsFPMath)
4997 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4999 EVT ResVT = Op.getValueType();
5000 EVT CmpVT = Op.getOperand(0).getValueType();
5001 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5002 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5005 // If the RHS of the comparison is a 0.0, we don't need to do the
5006 // subtraction at all.
5008 if (isFloatingPointZero(RHS))
5010 default: break; // SETUO etc aren't handled by fsel.
5014 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5015 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5016 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5017 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5018 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5019 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5020 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5023 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5026 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5027 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5028 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5031 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5034 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5035 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5036 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5037 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5042 default: break; // SETUO etc aren't handled by fsel.
5046 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5047 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5048 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5049 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5050 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5051 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5052 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5053 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5056 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5057 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5058 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5059 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5062 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5063 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5064 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5065 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5068 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5069 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5070 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5071 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5074 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5075 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5076 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5077 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5082 // FIXME: Split this code up when LegalizeDAGTypes lands.
5083 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5085 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5086 SDValue Src = Op.getOperand(0);
5087 if (Src.getValueType() == MVT::f32)
5088 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5091 switch (Op.getSimpleValueType().SimpleTy) {
5092 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5094 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5095 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5100 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5101 "i64 FP_TO_UINT is supported only with FPCVT");
5102 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5108 // Convert the FP value to an int value through memory.
5109 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5110 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5111 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5112 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5113 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5115 // Emit a store to the stack slot.
5118 MachineFunction &MF = DAG.getMachineFunction();
5119 MachineMemOperand *MMO =
5120 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5121 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5122 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5123 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5125 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5126 MPI, false, false, 0);
5128 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5130 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5131 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5132 DAG.getConstant(4, FIPtr.getValueType()));
5133 MPI = MachinePointerInfo();
5136 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5137 false, false, false, 0);
5140 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5141 SelectionDAG &DAG) const {
5143 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5144 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5147 if (Op.getOperand(0).getValueType() == MVT::i1)
5148 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5149 DAG.getConstantFP(1.0, Op.getValueType()),
5150 DAG.getConstantFP(0.0, Op.getValueType()));
5152 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5153 "UINT_TO_FP is supported only with FPCVT");
5155 // If we have FCFIDS, then use it when converting to single-precision.
5156 // Otherwise, convert to double-precision and then round.
5157 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5158 (Op.getOpcode() == ISD::UINT_TO_FP ?
5159 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5160 (Op.getOpcode() == ISD::UINT_TO_FP ?
5161 PPCISD::FCFIDU : PPCISD::FCFID);
5162 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5163 MVT::f32 : MVT::f64;
5165 if (Op.getOperand(0).getValueType() == MVT::i64) {
5166 SDValue SINT = Op.getOperand(0);
5167 // When converting to single-precision, we actually need to convert
5168 // to double-precision first and then round to single-precision.
5169 // To avoid double-rounding effects during that operation, we have
5170 // to prepare the input operand. Bits that might be truncated when
5171 // converting to double-precision are replaced by a bit that won't
5172 // be lost at this stage, but is below the single-precision rounding
5175 // However, if -enable-unsafe-fp-math is in effect, accept double
5176 // rounding to avoid the extra overhead.
5177 if (Op.getValueType() == MVT::f32 &&
5178 !Subtarget.hasFPCVT() &&
5179 !DAG.getTarget().Options.UnsafeFPMath) {
5181 // Twiddle input to make sure the low 11 bits are zero. (If this
5182 // is the case, we are guaranteed the value will fit into the 53 bit
5183 // mantissa of an IEEE double-precision value without rounding.)
5184 // If any of those low 11 bits were not zero originally, make sure
5185 // bit 12 (value 2048) is set instead, so that the final rounding
5186 // to single-precision gets the correct result.
5187 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5188 SINT, DAG.getConstant(2047, MVT::i64));
5189 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5190 Round, DAG.getConstant(2047, MVT::i64));
5191 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5192 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5193 Round, DAG.getConstant(-2048, MVT::i64));
5195 // However, we cannot use that value unconditionally: if the magnitude
5196 // of the input value is small, the bit-twiddling we did above might
5197 // end up visibly changing the output. Fortunately, in that case, we
5198 // don't need to twiddle bits since the original input will convert
5199 // exactly to double-precision floating-point already. Therefore,
5200 // construct a conditional to use the original value if the top 11
5201 // bits are all sign-bit copies, and use the rounded value computed
5203 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5204 SINT, DAG.getConstant(53, MVT::i32));
5205 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5206 Cond, DAG.getConstant(1, MVT::i64));
5207 Cond = DAG.getSetCC(dl, MVT::i32,
5208 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5210 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5213 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5214 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5216 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5217 FP = DAG.getNode(ISD::FP_ROUND, dl,
5218 MVT::f32, FP, DAG.getIntPtrConstant(0));
5222 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5223 "Unhandled INT_TO_FP type in custom expander!");
5224 // Since we only generate this in 64-bit mode, we can take advantage of
5225 // 64-bit registers. In particular, sign extend the input value into the
5226 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5227 // then lfd it and fcfid it.
5228 MachineFunction &MF = DAG.getMachineFunction();
5229 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5230 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5233 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5234 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5235 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5237 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5238 MachinePointerInfo::getFixedStack(FrameIdx),
5241 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5242 "Expected an i32 store");
5243 MachineMemOperand *MMO =
5244 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5245 MachineMemOperand::MOLoad, 4, 4);
5246 SDValue Ops[] = { Store, FIdx };
5247 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5248 PPCISD::LFIWZX : PPCISD::LFIWAX,
5249 dl, DAG.getVTList(MVT::f64, MVT::Other),
5250 Ops, MVT::i32, MMO);
5252 assert(Subtarget.isPPC64() &&
5253 "i32->FP without LFIWAX supported only on PPC64");
5255 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5256 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5258 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5261 // STD the extended value into the stack slot.
5262 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5263 MachinePointerInfo::getFixedStack(FrameIdx),
5266 // Load the value as a double.
5267 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5268 MachinePointerInfo::getFixedStack(FrameIdx),
5269 false, false, false, 0);
5272 // FCFID it and return it.
5273 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5274 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5275 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5279 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5280 SelectionDAG &DAG) const {
5283 The rounding mode is in bits 30:31 of FPSR, and has the following
5290 FLT_ROUNDS, on the other hand, expects the following:
5297 To perform the conversion, we do:
5298 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5301 MachineFunction &MF = DAG.getMachineFunction();
5302 EVT VT = Op.getValueType();
5303 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5305 // Save FP Control Word to register
5307 MVT::f64, // return register
5308 MVT::Glue // unused in this context
5310 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5312 // Save FP register to stack slot
5313 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5314 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5315 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5316 StackSlot, MachinePointerInfo(), false, false,0);
5318 // Load FP Control Word from low 32 bits of stack slot.
5319 SDValue Four = DAG.getConstant(4, PtrVT);
5320 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5321 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5322 false, false, false, 0);
5324 // Transform as necessary
5326 DAG.getNode(ISD::AND, dl, MVT::i32,
5327 CWD, DAG.getConstant(3, MVT::i32));
5329 DAG.getNode(ISD::SRL, dl, MVT::i32,
5330 DAG.getNode(ISD::AND, dl, MVT::i32,
5331 DAG.getNode(ISD::XOR, dl, MVT::i32,
5332 CWD, DAG.getConstant(3, MVT::i32)),
5333 DAG.getConstant(3, MVT::i32)),
5334 DAG.getConstant(1, MVT::i32));
5337 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5339 return DAG.getNode((VT.getSizeInBits() < 16 ?
5340 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5343 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5344 EVT VT = Op.getValueType();
5345 unsigned BitWidth = VT.getSizeInBits();
5347 assert(Op.getNumOperands() == 3 &&
5348 VT == Op.getOperand(1).getValueType() &&
5351 // Expand into a bunch of logical ops. Note that these ops
5352 // depend on the PPC behavior for oversized shift amounts.
5353 SDValue Lo = Op.getOperand(0);
5354 SDValue Hi = Op.getOperand(1);
5355 SDValue Amt = Op.getOperand(2);
5356 EVT AmtVT = Amt.getValueType();
5358 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5359 DAG.getConstant(BitWidth, AmtVT), Amt);
5360 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5361 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5362 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5363 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5364 DAG.getConstant(-BitWidth, AmtVT));
5365 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5366 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5367 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5368 SDValue OutOps[] = { OutLo, OutHi };
5369 return DAG.getMergeValues(OutOps, dl);
5372 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5373 EVT VT = Op.getValueType();
5375 unsigned BitWidth = VT.getSizeInBits();
5376 assert(Op.getNumOperands() == 3 &&
5377 VT == Op.getOperand(1).getValueType() &&
5380 // Expand into a bunch of logical ops. Note that these ops
5381 // depend on the PPC behavior for oversized shift amounts.
5382 SDValue Lo = Op.getOperand(0);
5383 SDValue Hi = Op.getOperand(1);
5384 SDValue Amt = Op.getOperand(2);
5385 EVT AmtVT = Amt.getValueType();
5387 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5388 DAG.getConstant(BitWidth, AmtVT), Amt);
5389 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5390 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5391 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5392 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5393 DAG.getConstant(-BitWidth, AmtVT));
5394 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5395 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5396 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5397 SDValue OutOps[] = { OutLo, OutHi };
5398 return DAG.getMergeValues(OutOps, dl);
5401 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5403 EVT VT = Op.getValueType();
5404 unsigned BitWidth = VT.getSizeInBits();
5405 assert(Op.getNumOperands() == 3 &&
5406 VT == Op.getOperand(1).getValueType() &&
5409 // Expand into a bunch of logical ops, followed by a select_cc.
5410 SDValue Lo = Op.getOperand(0);
5411 SDValue Hi = Op.getOperand(1);
5412 SDValue Amt = Op.getOperand(2);
5413 EVT AmtVT = Amt.getValueType();
5415 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5416 DAG.getConstant(BitWidth, AmtVT), Amt);
5417 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5418 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5419 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5420 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5421 DAG.getConstant(-BitWidth, AmtVT));
5422 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5423 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5424 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5425 Tmp4, Tmp6, ISD::SETLE);
5426 SDValue OutOps[] = { OutLo, OutHi };
5427 return DAG.getMergeValues(OutOps, dl);
5430 //===----------------------------------------------------------------------===//
5431 // Vector related lowering.
5434 /// BuildSplatI - Build a canonical splati of Val with an element size of
5435 /// SplatSize. Cast the result to VT.
5436 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5437 SelectionDAG &DAG, SDLoc dl) {
5438 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5440 static const EVT VTys[] = { // canonical VT to use for each size.
5441 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5444 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5446 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5450 EVT CanonicalVT = VTys[SplatSize-1];
5452 // Build a canonical splat for this value.
5453 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5454 SmallVector<SDValue, 8> Ops;
5455 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5456 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5457 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5460 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5461 /// specified intrinsic ID.
5462 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5463 SelectionDAG &DAG, SDLoc dl,
5464 EVT DestVT = MVT::Other) {
5465 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5466 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5467 DAG.getConstant(IID, MVT::i32), Op);
5470 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5471 /// specified intrinsic ID.
5472 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5473 SelectionDAG &DAG, SDLoc dl,
5474 EVT DestVT = MVT::Other) {
5475 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5476 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5477 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5480 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5481 /// specified intrinsic ID.
5482 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5483 SDValue Op2, SelectionDAG &DAG,
5484 SDLoc dl, EVT DestVT = MVT::Other) {
5485 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5486 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5487 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5491 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5492 /// amount. The result has the specified value type.
5493 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5494 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5495 // Force LHS/RHS to be the right type.
5496 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5497 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5500 for (unsigned i = 0; i != 16; ++i)
5502 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5503 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5506 // If this is a case we can't handle, return null and let the default
5507 // expansion code take care of it. If we CAN select this case, and if it
5508 // selects to a single instruction, return Op. Otherwise, if we can codegen
5509 // this case more efficiently than a constant pool load, lower it to the
5510 // sequence of ops that should be used.
5511 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5512 SelectionDAG &DAG) const {
5514 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5515 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5517 // Check if this is a splat of a constant value.
5518 APInt APSplatBits, APSplatUndef;
5519 unsigned SplatBitSize;
5521 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5522 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5525 unsigned SplatBits = APSplatBits.getZExtValue();
5526 unsigned SplatUndef = APSplatUndef.getZExtValue();
5527 unsigned SplatSize = SplatBitSize / 8;
5529 // First, handle single instruction cases.
5532 if (SplatBits == 0) {
5533 // Canonicalize all zero vectors to be v4i32.
5534 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5535 SDValue Z = DAG.getConstant(0, MVT::i32);
5536 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5537 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5542 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5543 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5545 if (SextVal >= -16 && SextVal <= 15)
5546 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5549 // Two instruction sequences.
5551 // If this value is in the range [-32,30] and is even, use:
5552 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5553 // If this value is in the range [17,31] and is odd, use:
5554 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5555 // If this value is in the range [-31,-17] and is odd, use:
5556 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5557 // Note the last two are three-instruction sequences.
5558 if (SextVal >= -32 && SextVal <= 31) {
5559 // To avoid having these optimizations undone by constant folding,
5560 // we convert to a pseudo that will be expanded later into one of
5562 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5563 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5564 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5565 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5566 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5567 if (VT == Op.getValueType())
5570 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5573 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5574 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5576 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5577 // Make -1 and vspltisw -1:
5578 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5580 // Make the VSLW intrinsic, computing 0x8000_0000.
5581 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5584 // xor by OnesV to invert it.
5585 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5586 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5589 // The remaining cases assume either big endian element order or
5590 // a splat-size that equates to the element size of the vector
5591 // to be built. An example that doesn't work for little endian is
5592 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5593 // and a vector element size of 16 bits. The code below will
5594 // produce the vector in big endian element order, which for little
5595 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5597 // For now, just avoid these optimizations in that case.
5598 // FIXME: Develop correct optimizations for LE with mismatched
5599 // splat and element sizes.
5601 if (Subtarget.isLittleEndian() &&
5602 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5605 // Check to see if this is a wide variety of vsplti*, binop self cases.
5606 static const signed char SplatCsts[] = {
5607 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5608 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5611 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5612 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5613 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5614 int i = SplatCsts[idx];
5616 // Figure out what shift amount will be used by altivec if shifted by i in
5618 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5620 // vsplti + shl self.
5621 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5622 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5623 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5624 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5625 Intrinsic::ppc_altivec_vslw
5627 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5628 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5631 // vsplti + srl self.
5632 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5633 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5634 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5635 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5636 Intrinsic::ppc_altivec_vsrw
5638 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5639 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5642 // vsplti + sra self.
5643 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5644 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5645 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5646 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5647 Intrinsic::ppc_altivec_vsraw
5649 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5650 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5653 // vsplti + rol self.
5654 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5655 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5656 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5657 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5658 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5659 Intrinsic::ppc_altivec_vrlw
5661 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5662 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5665 // t = vsplti c, result = vsldoi t, t, 1
5666 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5667 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5668 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5670 // t = vsplti c, result = vsldoi t, t, 2
5671 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5672 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5673 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5675 // t = vsplti c, result = vsldoi t, t, 3
5676 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5677 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5678 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5685 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5686 /// the specified operations to build the shuffle.
5687 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5688 SDValue RHS, SelectionDAG &DAG,
5690 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5691 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5692 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5695 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5707 if (OpNum == OP_COPY) {
5708 if (LHSID == (1*9+2)*9+3) return LHS;
5709 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5713 SDValue OpLHS, OpRHS;
5714 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5715 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5719 default: llvm_unreachable("Unknown i32 permute!");
5721 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5722 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5723 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5724 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5727 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5728 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5729 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5730 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5733 for (unsigned i = 0; i != 16; ++i)
5734 ShufIdxs[i] = (i&3)+0;
5737 for (unsigned i = 0; i != 16; ++i)
5738 ShufIdxs[i] = (i&3)+4;
5741 for (unsigned i = 0; i != 16; ++i)
5742 ShufIdxs[i] = (i&3)+8;
5745 for (unsigned i = 0; i != 16; ++i)
5746 ShufIdxs[i] = (i&3)+12;
5749 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5751 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5753 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5755 EVT VT = OpLHS.getValueType();
5756 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5757 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5758 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5759 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5762 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5763 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5764 /// return the code it can be lowered into. Worst case, it can always be
5765 /// lowered into a vperm.
5766 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5767 SelectionDAG &DAG) const {
5769 SDValue V1 = Op.getOperand(0);
5770 SDValue V2 = Op.getOperand(1);
5771 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5772 EVT VT = Op.getValueType();
5773 bool isLittleEndian = Subtarget.isLittleEndian();
5775 // Cases that are handled by instructions that take permute immediates
5776 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5777 // selected by the instruction selector.
5778 if (V2.getOpcode() == ISD::UNDEF) {
5779 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5780 PPC::isSplatShuffleMask(SVOp, 2) ||
5781 PPC::isSplatShuffleMask(SVOp, 4) ||
5782 PPC::isVPKUWUMShuffleMask(SVOp, true, DAG) ||
5783 PPC::isVPKUHUMShuffleMask(SVOp, true, DAG) ||
5784 PPC::isVSLDOIShuffleMask(SVOp, true, DAG) != -1 ||
5785 PPC::isVMRGLShuffleMask(SVOp, 1, true, DAG) ||
5786 PPC::isVMRGLShuffleMask(SVOp, 2, true, DAG) ||
5787 PPC::isVMRGLShuffleMask(SVOp, 4, true, DAG) ||
5788 PPC::isVMRGHShuffleMask(SVOp, 1, true, DAG) ||
5789 PPC::isVMRGHShuffleMask(SVOp, 2, true, DAG) ||
5790 PPC::isVMRGHShuffleMask(SVOp, 4, true, DAG)) {
5795 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5796 // and produce a fixed permutation. If any of these match, do not lower to
5798 if (PPC::isVPKUWUMShuffleMask(SVOp, false, DAG) ||
5799 PPC::isVPKUHUMShuffleMask(SVOp, false, DAG) ||
5800 PPC::isVSLDOIShuffleMask(SVOp, false, DAG) != -1 ||
5801 PPC::isVMRGLShuffleMask(SVOp, 1, false, DAG) ||
5802 PPC::isVMRGLShuffleMask(SVOp, 2, false, DAG) ||
5803 PPC::isVMRGLShuffleMask(SVOp, 4, false, DAG) ||
5804 PPC::isVMRGHShuffleMask(SVOp, 1, false, DAG) ||
5805 PPC::isVMRGHShuffleMask(SVOp, 2, false, DAG) ||
5806 PPC::isVMRGHShuffleMask(SVOp, 4, false, DAG))
5809 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5810 // perfect shuffle table to emit an optimal matching sequence.
5811 ArrayRef<int> PermMask = SVOp->getMask();
5813 unsigned PFIndexes[4];
5814 bool isFourElementShuffle = true;
5815 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5816 unsigned EltNo = 8; // Start out undef.
5817 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5818 if (PermMask[i*4+j] < 0)
5819 continue; // Undef, ignore it.
5821 unsigned ByteSource = PermMask[i*4+j];
5822 if ((ByteSource & 3) != j) {
5823 isFourElementShuffle = false;
5828 EltNo = ByteSource/4;
5829 } else if (EltNo != ByteSource/4) {
5830 isFourElementShuffle = false;
5834 PFIndexes[i] = EltNo;
5837 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5838 // perfect shuffle vector to determine if it is cost effective to do this as
5839 // discrete instructions, or whether we should use a vperm.
5840 // For now, we skip this for little endian until such time as we have a
5841 // little-endian perfect shuffle table.
5842 if (isFourElementShuffle && !isLittleEndian) {
5843 // Compute the index in the perfect shuffle table.
5844 unsigned PFTableIndex =
5845 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5847 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5848 unsigned Cost = (PFEntry >> 30);
5850 // Determining when to avoid vperm is tricky. Many things affect the cost
5851 // of vperm, particularly how many times the perm mask needs to be computed.
5852 // For example, if the perm mask can be hoisted out of a loop or is already
5853 // used (perhaps because there are multiple permutes with the same shuffle
5854 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5855 // the loop requires an extra register.
5857 // As a compromise, we only emit discrete instructions if the shuffle can be
5858 // generated in 3 or fewer operations. When we have loop information
5859 // available, if this block is within a loop, we should avoid using vperm
5860 // for 3-operation perms and use a constant pool load instead.
5862 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5865 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5866 // vector that will get spilled to the constant pool.
5867 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5869 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5870 // that it is in input element units, not in bytes. Convert now.
5872 // For little endian, the order of the input vectors is reversed, and
5873 // the permutation mask is complemented with respect to 31. This is
5874 // necessary to produce proper semantics with the big-endian-biased vperm
5876 EVT EltVT = V1.getValueType().getVectorElementType();
5877 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5879 SmallVector<SDValue, 16> ResultMask;
5880 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5881 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5883 for (unsigned j = 0; j != BytesPerElement; ++j)
5885 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
5888 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5892 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5895 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
5898 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
5902 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5903 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5904 /// information about the intrinsic.
5905 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5907 unsigned IntrinsicID =
5908 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5911 switch (IntrinsicID) {
5912 default: return false;
5913 // Comparison predicates.
5914 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5915 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5916 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5917 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5918 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5919 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5920 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5921 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5922 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5923 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5924 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5925 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5926 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5928 // Normal Comparisons.
5929 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5930 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5931 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5932 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5933 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5934 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5935 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5936 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5937 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5938 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5939 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5940 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5941 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5946 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5947 /// lower, do it, otherwise return null.
5948 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5949 SelectionDAG &DAG) const {
5950 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5951 // opcode number of the comparison.
5955 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5956 return SDValue(); // Don't custom lower most intrinsics.
5958 // If this is a non-dot comparison, make the VCMP node and we are done.
5960 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5961 Op.getOperand(1), Op.getOperand(2),
5962 DAG.getConstant(CompareOpc, MVT::i32));
5963 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5966 // Create the PPCISD altivec 'dot' comparison node.
5968 Op.getOperand(2), // LHS
5969 Op.getOperand(3), // RHS
5970 DAG.getConstant(CompareOpc, MVT::i32)
5972 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5973 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
5975 // Now that we have the comparison, emit a copy from the CR to a GPR.
5976 // This is flagged to the above dot comparison.
5977 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5978 DAG.getRegister(PPC::CR6, MVT::i32),
5979 CompNode.getValue(1));
5981 // Unpack the result based on how the target uses it.
5982 unsigned BitNo; // Bit # of CR6.
5983 bool InvertBit; // Invert result?
5984 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5985 default: // Can't happen, don't crash on invalid number though.
5986 case 0: // Return the value of the EQ bit of CR6.
5987 BitNo = 0; InvertBit = false;
5989 case 1: // Return the inverted value of the EQ bit of CR6.
5990 BitNo = 0; InvertBit = true;
5992 case 2: // Return the value of the LT bit of CR6.
5993 BitNo = 2; InvertBit = false;
5995 case 3: // Return the inverted value of the LT bit of CR6.
5996 BitNo = 2; InvertBit = true;
6000 // Shift the bit into the low position.
6001 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6002 DAG.getConstant(8-(3-BitNo), MVT::i32));
6004 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6005 DAG.getConstant(1, MVT::i32));
6007 // If we are supposed to, toggle the bit.
6009 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6010 DAG.getConstant(1, MVT::i32));
6014 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6015 SelectionDAG &DAG) const {
6017 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6018 // instructions), but for smaller types, we need to first extend up to v2i32
6019 // before doing going farther.
6020 if (Op.getValueType() == MVT::v2i64) {
6021 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6022 if (ExtVT != MVT::v2i32) {
6023 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6024 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6025 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6026 ExtVT.getVectorElementType(), 4)));
6027 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6028 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6029 DAG.getValueType(MVT::v2i32));
6038 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6039 SelectionDAG &DAG) const {
6041 // Create a stack slot that is 16-byte aligned.
6042 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6043 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6044 EVT PtrVT = getPointerTy();
6045 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6047 // Store the input value into Value#0 of the stack slot.
6048 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6049 Op.getOperand(0), FIdx, MachinePointerInfo(),
6052 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6053 false, false, false, 0);
6056 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6058 if (Op.getValueType() == MVT::v4i32) {
6059 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6061 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6062 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6064 SDValue RHSSwap = // = vrlw RHS, 16
6065 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6067 // Shrinkify inputs to v8i16.
6068 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6069 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6070 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6072 // Low parts multiplied together, generating 32-bit results (we ignore the
6074 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6075 LHS, RHS, DAG, dl, MVT::v4i32);
6077 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6078 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6079 // Shift the high parts up 16 bits.
6080 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6082 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6083 } else if (Op.getValueType() == MVT::v8i16) {
6084 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6086 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6088 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6089 LHS, RHS, Zero, DAG, dl);
6090 } else if (Op.getValueType() == MVT::v16i8) {
6091 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6092 bool isLittleEndian = Subtarget.isLittleEndian();
6094 // Multiply the even 8-bit parts, producing 16-bit sums.
6095 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6096 LHS, RHS, DAG, dl, MVT::v8i16);
6097 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6099 // Multiply the odd 8-bit parts, producing 16-bit sums.
6100 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6101 LHS, RHS, DAG, dl, MVT::v8i16);
6102 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6104 // Merge the results together. Because vmuleub and vmuloub are
6105 // instructions with a big-endian bias, we must reverse the
6106 // element numbering and reverse the meaning of "odd" and "even"
6107 // when generating little endian code.
6109 for (unsigned i = 0; i != 8; ++i) {
6110 if (isLittleEndian) {
6112 Ops[i*2+1] = 2*i+16;
6115 Ops[i*2+1] = 2*i+1+16;
6119 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6121 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6123 llvm_unreachable("Unknown mul to lower!");
6127 /// LowerOperation - Provide custom lowering hooks for some operations.
6129 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6130 switch (Op.getOpcode()) {
6131 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6132 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6133 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6134 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6135 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6136 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6137 case ISD::SETCC: return LowerSETCC(Op, DAG);
6138 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6139 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6141 return LowerVASTART(Op, DAG, Subtarget);
6144 return LowerVAARG(Op, DAG, Subtarget);
6147 return LowerVACOPY(Op, DAG, Subtarget);
6149 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6150 case ISD::DYNAMIC_STACKALLOC:
6151 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6153 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6154 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6156 case ISD::LOAD: return LowerLOAD(Op, DAG);
6157 case ISD::STORE: return LowerSTORE(Op, DAG);
6158 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6159 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6160 case ISD::FP_TO_UINT:
6161 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6163 case ISD::UINT_TO_FP:
6164 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6165 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6167 // Lower 64-bit shifts.
6168 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6169 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6170 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6172 // Vector-related lowering.
6173 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6174 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6175 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6176 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6177 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6178 case ISD::MUL: return LowerMUL(Op, DAG);
6180 // For counter-based loop handling.
6181 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6183 // Frame & Return address.
6184 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6185 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6189 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6190 SmallVectorImpl<SDValue>&Results,
6191 SelectionDAG &DAG) const {
6192 const TargetMachine &TM = getTargetMachine();
6194 switch (N->getOpcode()) {
6196 llvm_unreachable("Do not know how to custom type legalize this operation!");
6197 case ISD::INTRINSIC_W_CHAIN: {
6198 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6199 Intrinsic::ppc_is_decremented_ctr_nonzero)
6202 assert(N->getValueType(0) == MVT::i1 &&
6203 "Unexpected result type for CTR decrement intrinsic");
6204 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6205 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6206 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6209 Results.push_back(NewInt);
6210 Results.push_back(NewInt.getValue(1));
6214 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6215 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6218 EVT VT = N->getValueType(0);
6220 if (VT == MVT::i64) {
6221 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6223 Results.push_back(NewNode);
6224 Results.push_back(NewNode.getValue(1));
6228 case ISD::FP_ROUND_INREG: {
6229 assert(N->getValueType(0) == MVT::ppcf128);
6230 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6231 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6232 MVT::f64, N->getOperand(0),
6233 DAG.getIntPtrConstant(0));
6234 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6235 MVT::f64, N->getOperand(0),
6236 DAG.getIntPtrConstant(1));
6238 // Add the two halves of the long double in round-to-zero mode.
6239 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6241 // We know the low half is about to be thrown away, so just use something
6243 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6247 case ISD::FP_TO_SINT:
6248 // LowerFP_TO_INT() can only handle f32 and f64.
6249 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6251 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6257 //===----------------------------------------------------------------------===//
6258 // Other Lowering Code
6259 //===----------------------------------------------------------------------===//
6262 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6263 bool is64bit, unsigned BinOpcode) const {
6264 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6265 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6267 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6268 MachineFunction *F = BB->getParent();
6269 MachineFunction::iterator It = BB;
6272 unsigned dest = MI->getOperand(0).getReg();
6273 unsigned ptrA = MI->getOperand(1).getReg();
6274 unsigned ptrB = MI->getOperand(2).getReg();
6275 unsigned incr = MI->getOperand(3).getReg();
6276 DebugLoc dl = MI->getDebugLoc();
6278 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6279 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6280 F->insert(It, loopMBB);
6281 F->insert(It, exitMBB);
6282 exitMBB->splice(exitMBB->begin(), BB,
6283 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6284 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6286 MachineRegisterInfo &RegInfo = F->getRegInfo();
6287 unsigned TmpReg = (!BinOpcode) ? incr :
6288 RegInfo.createVirtualRegister(
6289 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6290 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6294 // fallthrough --> loopMBB
6295 BB->addSuccessor(loopMBB);
6298 // l[wd]arx dest, ptr
6299 // add r0, dest, incr
6300 // st[wd]cx. r0, ptr
6302 // fallthrough --> exitMBB
6304 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6305 .addReg(ptrA).addReg(ptrB);
6307 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6308 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6309 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6310 BuildMI(BB, dl, TII->get(PPC::BCC))
6311 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6312 BB->addSuccessor(loopMBB);
6313 BB->addSuccessor(exitMBB);
6322 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6323 MachineBasicBlock *BB,
6324 bool is8bit, // operation
6325 unsigned BinOpcode) const {
6326 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6327 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6328 // In 64 bit mode we have to use 64 bits for addresses, even though the
6329 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6330 // registers without caring whether they're 32 or 64, but here we're
6331 // doing actual arithmetic on the addresses.
6332 bool is64bit = Subtarget.isPPC64();
6333 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6335 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6336 MachineFunction *F = BB->getParent();
6337 MachineFunction::iterator It = BB;
6340 unsigned dest = MI->getOperand(0).getReg();
6341 unsigned ptrA = MI->getOperand(1).getReg();
6342 unsigned ptrB = MI->getOperand(2).getReg();
6343 unsigned incr = MI->getOperand(3).getReg();
6344 DebugLoc dl = MI->getDebugLoc();
6346 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6347 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6348 F->insert(It, loopMBB);
6349 F->insert(It, exitMBB);
6350 exitMBB->splice(exitMBB->begin(), BB,
6351 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6352 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6354 MachineRegisterInfo &RegInfo = F->getRegInfo();
6355 const TargetRegisterClass *RC =
6356 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6357 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6358 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6359 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6360 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6361 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6362 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6363 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6364 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6365 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6366 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6367 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6368 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6370 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6374 // fallthrough --> loopMBB
6375 BB->addSuccessor(loopMBB);
6377 // The 4-byte load must be aligned, while a char or short may be
6378 // anywhere in the word. Hence all this nasty bookkeeping code.
6379 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6380 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6381 // xori shift, shift1, 24 [16]
6382 // rlwinm ptr, ptr1, 0, 0, 29
6383 // slw incr2, incr, shift
6384 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6385 // slw mask, mask2, shift
6387 // lwarx tmpDest, ptr
6388 // add tmp, tmpDest, incr2
6389 // andc tmp2, tmpDest, mask
6390 // and tmp3, tmp, mask
6391 // or tmp4, tmp3, tmp2
6394 // fallthrough --> exitMBB
6395 // srw dest, tmpDest, shift
6396 if (ptrA != ZeroReg) {
6397 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6398 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6399 .addReg(ptrA).addReg(ptrB);
6403 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6404 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6405 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6406 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6408 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6409 .addReg(Ptr1Reg).addImm(0).addImm(61);
6411 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6412 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6413 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6414 .addReg(incr).addReg(ShiftReg);
6416 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6418 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6419 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6421 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6422 .addReg(Mask2Reg).addReg(ShiftReg);
6425 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6426 .addReg(ZeroReg).addReg(PtrReg);
6428 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6429 .addReg(Incr2Reg).addReg(TmpDestReg);
6430 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6431 .addReg(TmpDestReg).addReg(MaskReg);
6432 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6433 .addReg(TmpReg).addReg(MaskReg);
6434 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6435 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6436 BuildMI(BB, dl, TII->get(PPC::STWCX))
6437 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6438 BuildMI(BB, dl, TII->get(PPC::BCC))
6439 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6440 BB->addSuccessor(loopMBB);
6441 BB->addSuccessor(exitMBB);
6446 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6451 llvm::MachineBasicBlock*
6452 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6453 MachineBasicBlock *MBB) const {
6454 DebugLoc DL = MI->getDebugLoc();
6455 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6457 MachineFunction *MF = MBB->getParent();
6458 MachineRegisterInfo &MRI = MF->getRegInfo();
6460 const BasicBlock *BB = MBB->getBasicBlock();
6461 MachineFunction::iterator I = MBB;
6465 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6466 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6468 unsigned DstReg = MI->getOperand(0).getReg();
6469 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6470 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6471 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6472 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6474 MVT PVT = getPointerTy();
6475 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6476 "Invalid Pointer Size!");
6477 // For v = setjmp(buf), we generate
6480 // SjLjSetup mainMBB
6486 // buf[LabelOffset] = LR
6490 // v = phi(main, restore)
6493 MachineBasicBlock *thisMBB = MBB;
6494 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6495 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6496 MF->insert(I, mainMBB);
6497 MF->insert(I, sinkMBB);
6499 MachineInstrBuilder MIB;
6501 // Transfer the remainder of BB and its successor edges to sinkMBB.
6502 sinkMBB->splice(sinkMBB->begin(), MBB,
6503 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6504 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6506 // Note that the structure of the jmp_buf used here is not compatible
6507 // with that used by libc, and is not designed to be. Specifically, it
6508 // stores only those 'reserved' registers that LLVM does not otherwise
6509 // understand how to spill. Also, by convention, by the time this
6510 // intrinsic is called, Clang has already stored the frame address in the
6511 // first slot of the buffer and stack address in the third. Following the
6512 // X86 target code, we'll store the jump address in the second slot. We also
6513 // need to save the TOC pointer (R2) to handle jumps between shared
6514 // libraries, and that will be stored in the fourth slot. The thread
6515 // identifier (R13) is not affected.
6518 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6519 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6520 const int64_t BPOffset = 4 * PVT.getStoreSize();
6522 // Prepare IP either in reg.
6523 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6524 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6525 unsigned BufReg = MI->getOperand(1).getReg();
6527 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6528 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6532 MIB.setMemRefs(MMOBegin, MMOEnd);
6535 // Naked functions never have a base pointer, and so we use r1. For all
6536 // other functions, this decision must be delayed until during PEI.
6538 if (MF->getFunction()->getAttributes().hasAttribute(
6539 AttributeSet::FunctionIndex, Attribute::Naked))
6540 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6542 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6544 MIB = BuildMI(*thisMBB, MI, DL,
6545 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6549 MIB.setMemRefs(MMOBegin, MMOEnd);
6552 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6553 const PPCRegisterInfo *TRI =
6554 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6555 MIB.addRegMask(TRI->getNoPreservedMask());
6557 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6559 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6561 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6563 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6564 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6568 MIB = BuildMI(mainMBB, DL,
6569 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6572 if (Subtarget.isPPC64()) {
6573 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6575 .addImm(LabelOffset)
6578 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6580 .addImm(LabelOffset)
6584 MIB.setMemRefs(MMOBegin, MMOEnd);
6586 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6587 mainMBB->addSuccessor(sinkMBB);
6590 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6591 TII->get(PPC::PHI), DstReg)
6592 .addReg(mainDstReg).addMBB(mainMBB)
6593 .addReg(restoreDstReg).addMBB(thisMBB);
6595 MI->eraseFromParent();
6600 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6601 MachineBasicBlock *MBB) const {
6602 DebugLoc DL = MI->getDebugLoc();
6603 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6605 MachineFunction *MF = MBB->getParent();
6606 MachineRegisterInfo &MRI = MF->getRegInfo();
6609 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6610 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6612 MVT PVT = getPointerTy();
6613 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6614 "Invalid Pointer Size!");
6616 const TargetRegisterClass *RC =
6617 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6618 unsigned Tmp = MRI.createVirtualRegister(RC);
6619 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6620 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6621 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6622 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6624 MachineInstrBuilder MIB;
6626 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6627 const int64_t SPOffset = 2 * PVT.getStoreSize();
6628 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6629 const int64_t BPOffset = 4 * PVT.getStoreSize();
6631 unsigned BufReg = MI->getOperand(0).getReg();
6633 // Reload FP (the jumped-to function may not have had a
6634 // frame pointer, and if so, then its r31 will be restored
6636 if (PVT == MVT::i64) {
6637 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6641 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6645 MIB.setMemRefs(MMOBegin, MMOEnd);
6648 if (PVT == MVT::i64) {
6649 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6650 .addImm(LabelOffset)
6653 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6654 .addImm(LabelOffset)
6657 MIB.setMemRefs(MMOBegin, MMOEnd);
6660 if (PVT == MVT::i64) {
6661 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6665 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6669 MIB.setMemRefs(MMOBegin, MMOEnd);
6672 if (PVT == MVT::i64) {
6673 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6677 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6681 MIB.setMemRefs(MMOBegin, MMOEnd);
6684 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
6685 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6689 MIB.setMemRefs(MMOBegin, MMOEnd);
6693 BuildMI(*MBB, MI, DL,
6694 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6695 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6697 MI->eraseFromParent();
6702 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6703 MachineBasicBlock *BB) const {
6704 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6705 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6706 return emitEHSjLjSetJmp(MI, BB);
6707 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6708 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6709 return emitEHSjLjLongJmp(MI, BB);
6712 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6714 // To "insert" these instructions we actually have to insert their
6715 // control-flow patterns.
6716 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6717 MachineFunction::iterator It = BB;
6720 MachineFunction *F = BB->getParent();
6722 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6723 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6724 MI->getOpcode() == PPC::SELECT_I4 ||
6725 MI->getOpcode() == PPC::SELECT_I8)) {
6726 SmallVector<MachineOperand, 2> Cond;
6727 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6728 MI->getOpcode() == PPC::SELECT_CC_I8)
6729 Cond.push_back(MI->getOperand(4));
6731 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
6732 Cond.push_back(MI->getOperand(1));
6734 DebugLoc dl = MI->getDebugLoc();
6735 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6736 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6737 Cond, MI->getOperand(2).getReg(),
6738 MI->getOperand(3).getReg());
6739 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6740 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6741 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6742 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6743 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
6744 MI->getOpcode() == PPC::SELECT_I4 ||
6745 MI->getOpcode() == PPC::SELECT_I8 ||
6746 MI->getOpcode() == PPC::SELECT_F4 ||
6747 MI->getOpcode() == PPC::SELECT_F8 ||
6748 MI->getOpcode() == PPC::SELECT_VRRC) {
6749 // The incoming instruction knows the destination vreg to set, the
6750 // condition code register to branch on, the true/false values to
6751 // select between, and a branch opcode to use.
6756 // cmpTY ccX, r1, r2
6758 // fallthrough --> copy0MBB
6759 MachineBasicBlock *thisMBB = BB;
6760 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6761 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6762 DebugLoc dl = MI->getDebugLoc();
6763 F->insert(It, copy0MBB);
6764 F->insert(It, sinkMBB);
6766 // Transfer the remainder of BB and its successor edges to sinkMBB.
6767 sinkMBB->splice(sinkMBB->begin(), BB,
6768 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6769 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6771 // Next, add the true and fallthrough blocks as its successors.
6772 BB->addSuccessor(copy0MBB);
6773 BB->addSuccessor(sinkMBB);
6775 if (MI->getOpcode() == PPC::SELECT_I4 ||
6776 MI->getOpcode() == PPC::SELECT_I8 ||
6777 MI->getOpcode() == PPC::SELECT_F4 ||
6778 MI->getOpcode() == PPC::SELECT_F8 ||
6779 MI->getOpcode() == PPC::SELECT_VRRC) {
6780 BuildMI(BB, dl, TII->get(PPC::BC))
6781 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6783 unsigned SelectPred = MI->getOperand(4).getImm();
6784 BuildMI(BB, dl, TII->get(PPC::BCC))
6785 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6789 // %FalseValue = ...
6790 // # fallthrough to sinkMBB
6793 // Update machine-CFG edges
6794 BB->addSuccessor(sinkMBB);
6797 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6800 BuildMI(*BB, BB->begin(), dl,
6801 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6802 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6803 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6805 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6806 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6807 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6808 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6809 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6810 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6811 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6812 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6814 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6815 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6816 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6817 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6818 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6819 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6820 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6821 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6823 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6824 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6825 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6826 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6827 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6828 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6829 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6830 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6832 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6833 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6834 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6835 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6836 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6837 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6838 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6839 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6841 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6842 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6843 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6844 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6845 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6846 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6847 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6848 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6850 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6851 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6852 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6853 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6854 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6855 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6856 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6857 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6859 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6860 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6861 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6862 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6863 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6864 BB = EmitAtomicBinary(MI, BB, false, 0);
6865 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6866 BB = EmitAtomicBinary(MI, BB, true, 0);
6868 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6869 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6870 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6872 unsigned dest = MI->getOperand(0).getReg();
6873 unsigned ptrA = MI->getOperand(1).getReg();
6874 unsigned ptrB = MI->getOperand(2).getReg();
6875 unsigned oldval = MI->getOperand(3).getReg();
6876 unsigned newval = MI->getOperand(4).getReg();
6877 DebugLoc dl = MI->getDebugLoc();
6879 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6880 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6881 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6882 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6883 F->insert(It, loop1MBB);
6884 F->insert(It, loop2MBB);
6885 F->insert(It, midMBB);
6886 F->insert(It, exitMBB);
6887 exitMBB->splice(exitMBB->begin(), BB,
6888 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6889 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6893 // fallthrough --> loopMBB
6894 BB->addSuccessor(loop1MBB);
6897 // l[wd]arx dest, ptr
6898 // cmp[wd] dest, oldval
6901 // st[wd]cx. newval, ptr
6905 // st[wd]cx. dest, ptr
6908 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6909 .addReg(ptrA).addReg(ptrB);
6910 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6911 .addReg(oldval).addReg(dest);
6912 BuildMI(BB, dl, TII->get(PPC::BCC))
6913 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6914 BB->addSuccessor(loop2MBB);
6915 BB->addSuccessor(midMBB);
6918 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6919 .addReg(newval).addReg(ptrA).addReg(ptrB);
6920 BuildMI(BB, dl, TII->get(PPC::BCC))
6921 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6922 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6923 BB->addSuccessor(loop1MBB);
6924 BB->addSuccessor(exitMBB);
6927 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6928 .addReg(dest).addReg(ptrA).addReg(ptrB);
6929 BB->addSuccessor(exitMBB);
6934 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6935 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6936 // We must use 64-bit registers for addresses when targeting 64-bit,
6937 // since we're actually doing arithmetic on them. Other registers
6939 bool is64bit = Subtarget.isPPC64();
6940 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6942 unsigned dest = MI->getOperand(0).getReg();
6943 unsigned ptrA = MI->getOperand(1).getReg();
6944 unsigned ptrB = MI->getOperand(2).getReg();
6945 unsigned oldval = MI->getOperand(3).getReg();
6946 unsigned newval = MI->getOperand(4).getReg();
6947 DebugLoc dl = MI->getDebugLoc();
6949 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6950 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6951 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6952 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6953 F->insert(It, loop1MBB);
6954 F->insert(It, loop2MBB);
6955 F->insert(It, midMBB);
6956 F->insert(It, exitMBB);
6957 exitMBB->splice(exitMBB->begin(), BB,
6958 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6959 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6961 MachineRegisterInfo &RegInfo = F->getRegInfo();
6962 const TargetRegisterClass *RC =
6963 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6964 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6965 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6966 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6967 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6968 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6969 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6970 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6971 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6972 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6973 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6974 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6975 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6976 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6977 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6979 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6980 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6983 // fallthrough --> loopMBB
6984 BB->addSuccessor(loop1MBB);
6986 // The 4-byte load must be aligned, while a char or short may be
6987 // anywhere in the word. Hence all this nasty bookkeeping code.
6988 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6989 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6990 // xori shift, shift1, 24 [16]
6991 // rlwinm ptr, ptr1, 0, 0, 29
6992 // slw newval2, newval, shift
6993 // slw oldval2, oldval,shift
6994 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6995 // slw mask, mask2, shift
6996 // and newval3, newval2, mask
6997 // and oldval3, oldval2, mask
6999 // lwarx tmpDest, ptr
7000 // and tmp, tmpDest, mask
7001 // cmpw tmp, oldval3
7004 // andc tmp2, tmpDest, mask
7005 // or tmp4, tmp2, newval3
7010 // stwcx. tmpDest, ptr
7012 // srw dest, tmpDest, shift
7013 if (ptrA != ZeroReg) {
7014 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7015 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7016 .addReg(ptrA).addReg(ptrB);
7020 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7021 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7022 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7023 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7025 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7026 .addReg(Ptr1Reg).addImm(0).addImm(61);
7028 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7029 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7030 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7031 .addReg(newval).addReg(ShiftReg);
7032 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7033 .addReg(oldval).addReg(ShiftReg);
7035 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7037 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7038 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7039 .addReg(Mask3Reg).addImm(65535);
7041 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7042 .addReg(Mask2Reg).addReg(ShiftReg);
7043 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7044 .addReg(NewVal2Reg).addReg(MaskReg);
7045 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7046 .addReg(OldVal2Reg).addReg(MaskReg);
7049 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7050 .addReg(ZeroReg).addReg(PtrReg);
7051 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7052 .addReg(TmpDestReg).addReg(MaskReg);
7053 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7054 .addReg(TmpReg).addReg(OldVal3Reg);
7055 BuildMI(BB, dl, TII->get(PPC::BCC))
7056 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7057 BB->addSuccessor(loop2MBB);
7058 BB->addSuccessor(midMBB);
7061 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7062 .addReg(TmpDestReg).addReg(MaskReg);
7063 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7064 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7065 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7066 .addReg(ZeroReg).addReg(PtrReg);
7067 BuildMI(BB, dl, TII->get(PPC::BCC))
7068 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7069 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7070 BB->addSuccessor(loop1MBB);
7071 BB->addSuccessor(exitMBB);
7074 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7075 .addReg(ZeroReg).addReg(PtrReg);
7076 BB->addSuccessor(exitMBB);
7081 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7083 } else if (MI->getOpcode() == PPC::FADDrtz) {
7084 // This pseudo performs an FADD with rounding mode temporarily forced
7085 // to round-to-zero. We emit this via custom inserter since the FPSCR
7086 // is not modeled at the SelectionDAG level.
7087 unsigned Dest = MI->getOperand(0).getReg();
7088 unsigned Src1 = MI->getOperand(1).getReg();
7089 unsigned Src2 = MI->getOperand(2).getReg();
7090 DebugLoc dl = MI->getDebugLoc();
7092 MachineRegisterInfo &RegInfo = F->getRegInfo();
7093 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7095 // Save FPSCR value.
7096 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7098 // Set rounding mode to round-to-zero.
7099 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7100 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7102 // Perform addition.
7103 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7105 // Restore FPSCR value.
7106 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7107 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7108 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7109 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7110 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7111 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7112 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7113 PPC::ANDIo8 : PPC::ANDIo;
7114 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7115 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7117 MachineRegisterInfo &RegInfo = F->getRegInfo();
7118 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7119 &PPC::GPRCRegClass :
7120 &PPC::G8RCRegClass);
7122 DebugLoc dl = MI->getDebugLoc();
7123 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7124 .addReg(MI->getOperand(1).getReg()).addImm(1);
7125 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7126 MI->getOperand(0).getReg())
7127 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7129 llvm_unreachable("Unexpected instr type to insert");
7132 MI->eraseFromParent(); // The pseudo instruction is gone now.
7136 //===----------------------------------------------------------------------===//
7137 // Target Optimization Hooks
7138 //===----------------------------------------------------------------------===//
7140 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
7141 DAGCombinerInfo &DCI) const {
7142 if (DCI.isAfterLegalizeVectorOps())
7145 EVT VT = Op.getValueType();
7147 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7148 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7149 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7150 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7152 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7153 // For the reciprocal, we need to find the zero of the function:
7154 // F(X) = A X - 1 [which has a zero at X = 1/A]
7156 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7157 // does not require additional intermediate precision]
7159 // Convergence is quadratic, so we essentially double the number of digits
7160 // correct after every iteration. The minimum architected relative
7161 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7162 // 23 digits and double has 52 digits.
7163 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7164 if (VT.getScalarType() == MVT::f64)
7167 SelectionDAG &DAG = DCI.DAG;
7171 DAG.getConstantFP(1.0, VT.getScalarType());
7172 if (VT.isVector()) {
7173 assert(VT.getVectorNumElements() == 4 &&
7174 "Unknown vector type");
7175 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7176 FPOne, FPOne, FPOne, FPOne);
7179 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
7180 DCI.AddToWorklist(Est.getNode());
7182 // Newton iterations: Est = Est + Est (1 - Arg * Est)
7183 for (int i = 0; i < Iterations; ++i) {
7184 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
7185 DCI.AddToWorklist(NewEst.getNode());
7187 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
7188 DCI.AddToWorklist(NewEst.getNode());
7190 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7191 DCI.AddToWorklist(NewEst.getNode());
7193 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
7194 DCI.AddToWorklist(Est.getNode());
7203 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
7204 DAGCombinerInfo &DCI) const {
7205 if (DCI.isAfterLegalizeVectorOps())
7208 EVT VT = Op.getValueType();
7210 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7211 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7212 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7213 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7215 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7216 // For the reciprocal sqrt, we need to find the zero of the function:
7217 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7219 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7220 // As a result, we precompute A/2 prior to the iteration loop.
7222 // Convergence is quadratic, so we essentially double the number of digits
7223 // correct after every iteration. The minimum architected relative
7224 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7225 // 23 digits and double has 52 digits.
7226 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7227 if (VT.getScalarType() == MVT::f64)
7230 SelectionDAG &DAG = DCI.DAG;
7233 SDValue FPThreeHalves =
7234 DAG.getConstantFP(1.5, VT.getScalarType());
7235 if (VT.isVector()) {
7236 assert(VT.getVectorNumElements() == 4 &&
7237 "Unknown vector type");
7238 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7239 FPThreeHalves, FPThreeHalves,
7240 FPThreeHalves, FPThreeHalves);
7243 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7244 DCI.AddToWorklist(Est.getNode());
7246 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7247 // this entire sequence requires only one FP constant.
7248 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7249 DCI.AddToWorklist(HalfArg.getNode());
7251 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7252 DCI.AddToWorklist(HalfArg.getNode());
7254 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7255 for (int i = 0; i < Iterations; ++i) {
7256 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7257 DCI.AddToWorklist(NewEst.getNode());
7259 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7260 DCI.AddToWorklist(NewEst.getNode());
7262 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7263 DCI.AddToWorklist(NewEst.getNode());
7265 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7266 DCI.AddToWorklist(Est.getNode());
7275 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7276 // not enforce equality of the chain operands.
7277 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
7278 unsigned Bytes, int Dist,
7279 SelectionDAG &DAG) {
7280 EVT VT = LS->getMemoryVT();
7281 if (VT.getSizeInBits() / 8 != Bytes)
7284 SDValue Loc = LS->getBasePtr();
7285 SDValue BaseLoc = Base->getBasePtr();
7286 if (Loc.getOpcode() == ISD::FrameIndex) {
7287 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7289 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7290 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7291 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7292 int FS = MFI->getObjectSize(FI);
7293 int BFS = MFI->getObjectSize(BFI);
7294 if (FS != BFS || FS != (int)Bytes) return false;
7295 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7299 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7300 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7303 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7304 const GlobalValue *GV1 = nullptr;
7305 const GlobalValue *GV2 = nullptr;
7306 int64_t Offset1 = 0;
7307 int64_t Offset2 = 0;
7308 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7309 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7310 if (isGA1 && isGA2 && GV1 == GV2)
7311 return Offset1 == (Offset2 + Dist*Bytes);
7315 // Return true is there is a nearyby consecutive load to the one provided
7316 // (regardless of alignment). We search up and down the chain, looking though
7317 // token factors and other loads (but nothing else). As a result, a true
7318 // results indicates that it is safe to create a new consecutive load adjacent
7319 // to the load provided.
7320 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7321 SDValue Chain = LD->getChain();
7322 EVT VT = LD->getMemoryVT();
7324 SmallSet<SDNode *, 16> LoadRoots;
7325 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7326 SmallSet<SDNode *, 16> Visited;
7328 // First, search up the chain, branching to follow all token-factor operands.
7329 // If we find a consecutive load, then we're done, otherwise, record all
7330 // nodes just above the top-level loads and token factors.
7331 while (!Queue.empty()) {
7332 SDNode *ChainNext = Queue.pop_back_val();
7333 if (!Visited.insert(ChainNext))
7336 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
7337 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7340 if (!Visited.count(ChainLD->getChain().getNode()))
7341 Queue.push_back(ChainLD->getChain().getNode());
7342 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7343 for (SDNode::op_iterator O = ChainNext->op_begin(),
7344 OE = ChainNext->op_end(); O != OE; ++O)
7345 if (!Visited.count(O->getNode()))
7346 Queue.push_back(O->getNode());
7348 LoadRoots.insert(ChainNext);
7351 // Second, search down the chain, starting from the top-level nodes recorded
7352 // in the first phase. These top-level nodes are the nodes just above all
7353 // loads and token factors. Starting with their uses, recursively look though
7354 // all loads (just the chain uses) and token factors to find a consecutive
7359 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7360 IE = LoadRoots.end(); I != IE; ++I) {
7361 Queue.push_back(*I);
7363 while (!Queue.empty()) {
7364 SDNode *LoadRoot = Queue.pop_back_val();
7365 if (!Visited.insert(LoadRoot))
7368 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
7369 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7372 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7373 UE = LoadRoot->use_end(); UI != UE; ++UI)
7374 if (((isa<LoadSDNode>(*UI) &&
7375 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7376 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7377 Queue.push_back(*UI);
7384 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7385 DAGCombinerInfo &DCI) const {
7386 SelectionDAG &DAG = DCI.DAG;
7389 assert(Subtarget.useCRBits() &&
7390 "Expecting to be tracking CR bits");
7391 // If we're tracking CR bits, we need to be careful that we don't have:
7392 // trunc(binary-ops(zext(x), zext(y)))
7394 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7395 // such that we're unnecessarily moving things into GPRs when it would be
7396 // better to keep them in CR bits.
7398 // Note that trunc here can be an actual i1 trunc, or can be the effective
7399 // truncation that comes from a setcc or select_cc.
7400 if (N->getOpcode() == ISD::TRUNCATE &&
7401 N->getValueType(0) != MVT::i1)
7404 if (N->getOperand(0).getValueType() != MVT::i32 &&
7405 N->getOperand(0).getValueType() != MVT::i64)
7408 if (N->getOpcode() == ISD::SETCC ||
7409 N->getOpcode() == ISD::SELECT_CC) {
7410 // If we're looking at a comparison, then we need to make sure that the
7411 // high bits (all except for the first) don't matter the result.
7413 cast<CondCodeSDNode>(N->getOperand(
7414 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7415 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7417 if (ISD::isSignedIntSetCC(CC)) {
7418 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7419 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7421 } else if (ISD::isUnsignedIntSetCC(CC)) {
7422 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7423 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7424 !DAG.MaskedValueIsZero(N->getOperand(1),
7425 APInt::getHighBitsSet(OpBits, OpBits-1)))
7428 // This is neither a signed nor an unsigned comparison, just make sure
7429 // that the high bits are equal.
7430 APInt Op1Zero, Op1One;
7431 APInt Op2Zero, Op2One;
7432 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7433 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7435 // We don't really care about what is known about the first bit (if
7436 // anything), so clear it in all masks prior to comparing them.
7437 Op1Zero.clearBit(0); Op1One.clearBit(0);
7438 Op2Zero.clearBit(0); Op2One.clearBit(0);
7440 if (Op1Zero != Op2Zero || Op1One != Op2One)
7445 // We now know that the higher-order bits are irrelevant, we just need to
7446 // make sure that all of the intermediate operations are bit operations, and
7447 // all inputs are extensions.
7448 if (N->getOperand(0).getOpcode() != ISD::AND &&
7449 N->getOperand(0).getOpcode() != ISD::OR &&
7450 N->getOperand(0).getOpcode() != ISD::XOR &&
7451 N->getOperand(0).getOpcode() != ISD::SELECT &&
7452 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7453 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7454 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7455 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7456 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7459 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7460 N->getOperand(1).getOpcode() != ISD::AND &&
7461 N->getOperand(1).getOpcode() != ISD::OR &&
7462 N->getOperand(1).getOpcode() != ISD::XOR &&
7463 N->getOperand(1).getOpcode() != ISD::SELECT &&
7464 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7465 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7466 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7467 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7468 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7471 SmallVector<SDValue, 4> Inputs;
7472 SmallVector<SDValue, 8> BinOps, PromOps;
7473 SmallPtrSet<SDNode *, 16> Visited;
7475 for (unsigned i = 0; i < 2; ++i) {
7476 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7477 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7478 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7479 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7480 isa<ConstantSDNode>(N->getOperand(i)))
7481 Inputs.push_back(N->getOperand(i));
7483 BinOps.push_back(N->getOperand(i));
7485 if (N->getOpcode() == ISD::TRUNCATE)
7489 // Visit all inputs, collect all binary operations (and, or, xor and
7490 // select) that are all fed by extensions.
7491 while (!BinOps.empty()) {
7492 SDValue BinOp = BinOps.back();
7495 if (!Visited.insert(BinOp.getNode()))
7498 PromOps.push_back(BinOp);
7500 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7501 // The condition of the select is not promoted.
7502 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7504 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7507 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7508 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7509 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7510 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7511 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7512 Inputs.push_back(BinOp.getOperand(i));
7513 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7514 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7515 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7516 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7517 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7518 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7519 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7520 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7521 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7522 BinOps.push_back(BinOp.getOperand(i));
7524 // We have an input that is not an extension or another binary
7525 // operation; we'll abort this transformation.
7531 // Make sure that this is a self-contained cluster of operations (which
7532 // is not quite the same thing as saying that everything has only one
7534 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7535 if (isa<ConstantSDNode>(Inputs[i]))
7538 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7539 UE = Inputs[i].getNode()->use_end();
7542 if (User != N && !Visited.count(User))
7545 // Make sure that we're not going to promote the non-output-value
7546 // operand(s) or SELECT or SELECT_CC.
7547 // FIXME: Although we could sometimes handle this, and it does occur in
7548 // practice that one of the condition inputs to the select is also one of
7549 // the outputs, we currently can't deal with this.
7550 if (User->getOpcode() == ISD::SELECT) {
7551 if (User->getOperand(0) == Inputs[i])
7553 } else if (User->getOpcode() == ISD::SELECT_CC) {
7554 if (User->getOperand(0) == Inputs[i] ||
7555 User->getOperand(1) == Inputs[i])
7561 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7562 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7563 UE = PromOps[i].getNode()->use_end();
7566 if (User != N && !Visited.count(User))
7569 // Make sure that we're not going to promote the non-output-value
7570 // operand(s) or SELECT or SELECT_CC.
7571 // FIXME: Although we could sometimes handle this, and it does occur in
7572 // practice that one of the condition inputs to the select is also one of
7573 // the outputs, we currently can't deal with this.
7574 if (User->getOpcode() == ISD::SELECT) {
7575 if (User->getOperand(0) == PromOps[i])
7577 } else if (User->getOpcode() == ISD::SELECT_CC) {
7578 if (User->getOperand(0) == PromOps[i] ||
7579 User->getOperand(1) == PromOps[i])
7585 // Replace all inputs with the extension operand.
7586 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7587 // Constants may have users outside the cluster of to-be-promoted nodes,
7588 // and so we need to replace those as we do the promotions.
7589 if (isa<ConstantSDNode>(Inputs[i]))
7592 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7595 // Replace all operations (these are all the same, but have a different
7596 // (i1) return type). DAG.getNode will validate that the types of
7597 // a binary operator match, so go through the list in reverse so that
7598 // we've likely promoted both operands first. Any intermediate truncations or
7599 // extensions disappear.
7600 while (!PromOps.empty()) {
7601 SDValue PromOp = PromOps.back();
7604 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7605 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7606 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7607 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7608 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7609 PromOp.getOperand(0).getValueType() != MVT::i1) {
7610 // The operand is not yet ready (see comment below).
7611 PromOps.insert(PromOps.begin(), PromOp);
7615 SDValue RepValue = PromOp.getOperand(0);
7616 if (isa<ConstantSDNode>(RepValue))
7617 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7619 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7624 switch (PromOp.getOpcode()) {
7625 default: C = 0; break;
7626 case ISD::SELECT: C = 1; break;
7627 case ISD::SELECT_CC: C = 2; break;
7630 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7631 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7632 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7633 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7634 // The to-be-promoted operands of this node have not yet been
7635 // promoted (this should be rare because we're going through the
7636 // list backward, but if one of the operands has several users in
7637 // this cluster of to-be-promoted nodes, it is possible).
7638 PromOps.insert(PromOps.begin(), PromOp);
7642 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7643 PromOp.getNode()->op_end());
7645 // If there are any constant inputs, make sure they're replaced now.
7646 for (unsigned i = 0; i < 2; ++i)
7647 if (isa<ConstantSDNode>(Ops[C+i]))
7648 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7650 DAG.ReplaceAllUsesOfValueWith(PromOp,
7651 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
7654 // Now we're left with the initial truncation itself.
7655 if (N->getOpcode() == ISD::TRUNCATE)
7656 return N->getOperand(0);
7658 // Otherwise, this is a comparison. The operands to be compared have just
7659 // changed type (to i1), but everything else is the same.
7660 return SDValue(N, 0);
7663 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7664 DAGCombinerInfo &DCI) const {
7665 SelectionDAG &DAG = DCI.DAG;
7668 // If we're tracking CR bits, we need to be careful that we don't have:
7669 // zext(binary-ops(trunc(x), trunc(y)))
7671 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
7672 // such that we're unnecessarily moving things into CR bits that can more
7673 // efficiently stay in GPRs. Note that if we're not certain that the high
7674 // bits are set as required by the final extension, we still may need to do
7675 // some masking to get the proper behavior.
7677 // This same functionality is important on PPC64 when dealing with
7678 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
7679 // the return values of functions. Because it is so similar, it is handled
7682 if (N->getValueType(0) != MVT::i32 &&
7683 N->getValueType(0) != MVT::i64)
7686 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
7687 Subtarget.useCRBits()) ||
7688 (N->getOperand(0).getValueType() == MVT::i32 &&
7689 Subtarget.isPPC64())))
7692 if (N->getOperand(0).getOpcode() != ISD::AND &&
7693 N->getOperand(0).getOpcode() != ISD::OR &&
7694 N->getOperand(0).getOpcode() != ISD::XOR &&
7695 N->getOperand(0).getOpcode() != ISD::SELECT &&
7696 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
7699 SmallVector<SDValue, 4> Inputs;
7700 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
7701 SmallPtrSet<SDNode *, 16> Visited;
7703 // Visit all inputs, collect all binary operations (and, or, xor and
7704 // select) that are all fed by truncations.
7705 while (!BinOps.empty()) {
7706 SDValue BinOp = BinOps.back();
7709 if (!Visited.insert(BinOp.getNode()))
7712 PromOps.push_back(BinOp);
7714 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7715 // The condition of the select is not promoted.
7716 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7718 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7721 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7722 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7723 Inputs.push_back(BinOp.getOperand(i));
7724 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7725 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7726 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7727 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7728 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
7729 BinOps.push_back(BinOp.getOperand(i));
7731 // We have an input that is not a truncation or another binary
7732 // operation; we'll abort this transformation.
7738 // Make sure that this is a self-contained cluster of operations (which
7739 // is not quite the same thing as saying that everything has only one
7741 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7742 if (isa<ConstantSDNode>(Inputs[i]))
7745 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7746 UE = Inputs[i].getNode()->use_end();
7749 if (User != N && !Visited.count(User))
7752 // Make sure that we're not going to promote the non-output-value
7753 // operand(s) or SELECT or SELECT_CC.
7754 // FIXME: Although we could sometimes handle this, and it does occur in
7755 // practice that one of the condition inputs to the select is also one of
7756 // the outputs, we currently can't deal with this.
7757 if (User->getOpcode() == ISD::SELECT) {
7758 if (User->getOperand(0) == Inputs[i])
7760 } else if (User->getOpcode() == ISD::SELECT_CC) {
7761 if (User->getOperand(0) == Inputs[i] ||
7762 User->getOperand(1) == Inputs[i])
7768 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7769 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7770 UE = PromOps[i].getNode()->use_end();
7773 if (User != N && !Visited.count(User))
7776 // Make sure that we're not going to promote the non-output-value
7777 // operand(s) or SELECT or SELECT_CC.
7778 // FIXME: Although we could sometimes handle this, and it does occur in
7779 // practice that one of the condition inputs to the select is also one of
7780 // the outputs, we currently can't deal with this.
7781 if (User->getOpcode() == ISD::SELECT) {
7782 if (User->getOperand(0) == PromOps[i])
7784 } else if (User->getOpcode() == ISD::SELECT_CC) {
7785 if (User->getOperand(0) == PromOps[i] ||
7786 User->getOperand(1) == PromOps[i])
7792 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
7793 bool ReallyNeedsExt = false;
7794 if (N->getOpcode() != ISD::ANY_EXTEND) {
7795 // If all of the inputs are not already sign/zero extended, then
7796 // we'll still need to do that at the end.
7797 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7798 if (isa<ConstantSDNode>(Inputs[i]))
7802 Inputs[i].getOperand(0).getValueSizeInBits();
7803 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
7805 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
7806 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
7807 APInt::getHighBitsSet(OpBits,
7808 OpBits-PromBits))) ||
7809 (N->getOpcode() == ISD::SIGN_EXTEND &&
7810 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
7811 (OpBits-(PromBits-1)))) {
7812 ReallyNeedsExt = true;
7818 // Replace all inputs, either with the truncation operand, or a
7819 // truncation or extension to the final output type.
7820 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7821 // Constant inputs need to be replaced with the to-be-promoted nodes that
7822 // use them because they might have users outside of the cluster of
7824 if (isa<ConstantSDNode>(Inputs[i]))
7827 SDValue InSrc = Inputs[i].getOperand(0);
7828 if (Inputs[i].getValueType() == N->getValueType(0))
7829 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
7830 else if (N->getOpcode() == ISD::SIGN_EXTEND)
7831 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7832 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
7833 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7834 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7835 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
7837 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7838 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
7841 // Replace all operations (these are all the same, but have a different
7842 // (promoted) return type). DAG.getNode will validate that the types of
7843 // a binary operator match, so go through the list in reverse so that
7844 // we've likely promoted both operands first.
7845 while (!PromOps.empty()) {
7846 SDValue PromOp = PromOps.back();
7850 switch (PromOp.getOpcode()) {
7851 default: C = 0; break;
7852 case ISD::SELECT: C = 1; break;
7853 case ISD::SELECT_CC: C = 2; break;
7856 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7857 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
7858 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7859 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
7860 // The to-be-promoted operands of this node have not yet been
7861 // promoted (this should be rare because we're going through the
7862 // list backward, but if one of the operands has several users in
7863 // this cluster of to-be-promoted nodes, it is possible).
7864 PromOps.insert(PromOps.begin(), PromOp);
7868 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7869 PromOp.getNode()->op_end());
7871 // If this node has constant inputs, then they'll need to be promoted here.
7872 for (unsigned i = 0; i < 2; ++i) {
7873 if (!isa<ConstantSDNode>(Ops[C+i]))
7875 if (Ops[C+i].getValueType() == N->getValueType(0))
7878 if (N->getOpcode() == ISD::SIGN_EXTEND)
7879 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7880 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7881 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7883 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7886 DAG.ReplaceAllUsesOfValueWith(PromOp,
7887 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
7890 // Now we're left with the initial extension itself.
7891 if (!ReallyNeedsExt)
7892 return N->getOperand(0);
7894 // To zero extend, just mask off everything except for the first bit (in the
7896 if (N->getOpcode() == ISD::ZERO_EXTEND)
7897 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
7898 DAG.getConstant(APInt::getLowBitsSet(
7899 N->getValueSizeInBits(0), PromBits),
7900 N->getValueType(0)));
7902 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
7903 "Invalid extension type");
7904 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
7906 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
7907 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
7908 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
7909 N->getOperand(0), ShiftCst), ShiftCst);
7912 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
7913 DAGCombinerInfo &DCI) const {
7914 const TargetMachine &TM = getTargetMachine();
7915 SelectionDAG &DAG = DCI.DAG;
7917 switch (N->getOpcode()) {
7920 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7921 if (C->isNullValue()) // 0 << V -> 0.
7922 return N->getOperand(0);
7926 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7927 if (C->isNullValue()) // 0 >>u V -> 0.
7928 return N->getOperand(0);
7932 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7933 if (C->isNullValue() || // 0 >>s V -> 0.
7934 C->isAllOnesValue()) // -1 >>s V -> -1.
7935 return N->getOperand(0);
7938 case ISD::SIGN_EXTEND:
7939 case ISD::ZERO_EXTEND:
7940 case ISD::ANY_EXTEND:
7941 return DAGCombineExtBoolTrunc(N, DCI);
7944 case ISD::SELECT_CC:
7945 return DAGCombineTruncBoolExt(N, DCI);
7947 assert(TM.Options.UnsafeFPMath &&
7948 "Reciprocal estimates require UnsafeFPMath");
7950 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
7952 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
7954 DCI.AddToWorklist(RV.getNode());
7955 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7956 N->getOperand(0), RV);
7958 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
7959 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7961 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7964 DCI.AddToWorklist(RV.getNode());
7965 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
7966 N->getValueType(0), RV);
7967 DCI.AddToWorklist(RV.getNode());
7968 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7969 N->getOperand(0), RV);
7971 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
7972 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7974 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7977 DCI.AddToWorklist(RV.getNode());
7978 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
7979 N->getValueType(0), RV,
7980 N->getOperand(1).getOperand(1));
7981 DCI.AddToWorklist(RV.getNode());
7982 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7983 N->getOperand(0), RV);
7987 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
7989 DCI.AddToWorklist(RV.getNode());
7990 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7991 N->getOperand(0), RV);
7997 assert(TM.Options.UnsafeFPMath &&
7998 "Reciprocal estimates require UnsafeFPMath");
8000 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
8002 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
8004 DCI.AddToWorklist(RV.getNode());
8005 RV = DAGCombineFastRecip(RV, DCI);
8007 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
8008 // this case and force the answer to 0.
8010 EVT VT = RV.getValueType();
8012 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
8013 if (VT.isVector()) {
8014 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
8015 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
8019 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
8020 N->getOperand(0), Zero, ISD::SETEQ);
8021 DCI.AddToWorklist(ZeroCmp.getNode());
8022 DCI.AddToWorklist(RV.getNode());
8024 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
8032 case ISD::SINT_TO_FP:
8033 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
8034 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8035 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8036 // We allow the src/dst to be either f32/f64, but the intermediate
8037 // type must be i64.
8038 if (N->getOperand(0).getValueType() == MVT::i64 &&
8039 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
8040 SDValue Val = N->getOperand(0).getOperand(0);
8041 if (Val.getValueType() == MVT::f32) {
8042 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8043 DCI.AddToWorklist(Val.getNode());
8046 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8047 DCI.AddToWorklist(Val.getNode());
8048 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8049 DCI.AddToWorklist(Val.getNode());
8050 if (N->getValueType(0) == MVT::f32) {
8051 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8052 DAG.getIntPtrConstant(0));
8053 DCI.AddToWorklist(Val.getNode());
8056 } else if (N->getOperand(0).getValueType() == MVT::i32) {
8057 // If the intermediate type is i32, we can avoid the load/store here
8064 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8065 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8066 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8067 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8068 N->getOperand(1).getValueType() == MVT::i32 &&
8069 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8070 SDValue Val = N->getOperand(1).getOperand(0);
8071 if (Val.getValueType() == MVT::f32) {
8072 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8073 DCI.AddToWorklist(Val.getNode());
8075 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8076 DCI.AddToWorklist(Val.getNode());
8079 N->getOperand(0), Val, N->getOperand(2),
8080 DAG.getValueType(N->getOperand(1).getValueType())
8083 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8084 DAG.getVTList(MVT::Other), Ops,
8085 cast<StoreSDNode>(N)->getMemoryVT(),
8086 cast<StoreSDNode>(N)->getMemOperand());
8087 DCI.AddToWorklist(Val.getNode());
8091 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8092 if (cast<StoreSDNode>(N)->isUnindexed() &&
8093 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8094 N->getOperand(1).getNode()->hasOneUse() &&
8095 (N->getOperand(1).getValueType() == MVT::i32 ||
8096 N->getOperand(1).getValueType() == MVT::i16 ||
8097 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8098 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8099 N->getOperand(1).getValueType() == MVT::i64))) {
8100 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8101 // Do an any-extend to 32-bits if this is a half-word input.
8102 if (BSwapOp.getValueType() == MVT::i16)
8103 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8106 N->getOperand(0), BSwapOp, N->getOperand(2),
8107 DAG.getValueType(N->getOperand(1).getValueType())
8110 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8111 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8112 cast<StoreSDNode>(N)->getMemOperand());
8116 LoadSDNode *LD = cast<LoadSDNode>(N);
8117 EVT VT = LD->getValueType(0);
8118 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8119 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8120 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8121 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8122 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8123 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8124 LD->getAlignment() < ABIAlignment) {
8125 // This is a type-legal unaligned Altivec load.
8126 SDValue Chain = LD->getChain();
8127 SDValue Ptr = LD->getBasePtr();
8128 bool isLittleEndian = Subtarget.isLittleEndian();
8130 // This implements the loading of unaligned vectors as described in
8131 // the venerable Apple Velocity Engine overview. Specifically:
8132 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8133 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8135 // The general idea is to expand a sequence of one or more unaligned
8136 // loads into an alignment-based permutation-control instruction (lvsl
8137 // or lvsr), a series of regular vector loads (which always truncate
8138 // their input address to an aligned address), and a series of
8139 // permutations. The results of these permutations are the requested
8140 // loaded values. The trick is that the last "extra" load is not taken
8141 // from the address you might suspect (sizeof(vector) bytes after the
8142 // last requested load), but rather sizeof(vector) - 1 bytes after the
8143 // last requested vector. The point of this is to avoid a page fault if
8144 // the base address happened to be aligned. This works because if the
8145 // base address is aligned, then adding less than a full vector length
8146 // will cause the last vector in the sequence to be (re)loaded.
8147 // Otherwise, the next vector will be fetched as you might suspect was
8150 // We might be able to reuse the permutation generation from
8151 // a different base address offset from this one by an aligned amount.
8152 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8153 // optimization later.
8154 Intrinsic::ID Intr = (isLittleEndian ?
8155 Intrinsic::ppc_altivec_lvsr :
8156 Intrinsic::ppc_altivec_lvsl);
8157 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8159 // Refine the alignment of the original load (a "new" load created here
8160 // which was identical to the first except for the alignment would be
8161 // merged with the existing node regardless).
8162 MachineFunction &MF = DAG.getMachineFunction();
8163 MachineMemOperand *MMO =
8164 MF.getMachineMemOperand(LD->getPointerInfo(),
8165 LD->getMemOperand()->getFlags(),
8166 LD->getMemoryVT().getStoreSize(),
8168 LD->refineAlignment(MMO);
8169 SDValue BaseLoad = SDValue(LD, 0);
8171 // Note that the value of IncOffset (which is provided to the next
8172 // load's pointer info offset value, and thus used to calculate the
8173 // alignment), and the value of IncValue (which is actually used to
8174 // increment the pointer value) are different! This is because we
8175 // require the next load to appear to be aligned, even though it
8176 // is actually offset from the base pointer by a lesser amount.
8177 int IncOffset = VT.getSizeInBits() / 8;
8178 int IncValue = IncOffset;
8180 // Walk (both up and down) the chain looking for another load at the real
8181 // (aligned) offset (the alignment of the other load does not matter in
8182 // this case). If found, then do not use the offset reduction trick, as
8183 // that will prevent the loads from being later combined (as they would
8184 // otherwise be duplicates).
8185 if (!findConsecutiveLoad(LD, DAG))
8188 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8189 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8192 DAG.getLoad(VT, dl, Chain, Ptr,
8193 LD->getPointerInfo().getWithOffset(IncOffset),
8194 LD->isVolatile(), LD->isNonTemporal(),
8195 LD->isInvariant(), ABIAlignment);
8197 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8198 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8200 if (BaseLoad.getValueType() != MVT::v4i32)
8201 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
8203 if (ExtraLoad.getValueType() != MVT::v4i32)
8204 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
8206 // Because vperm has a big-endian bias, we must reverse the order
8207 // of the input vectors and complement the permute control vector
8208 // when generating little endian code. We have already handled the
8209 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8210 // and ExtraLoad here.
8213 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8214 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8216 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8217 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8219 if (VT != MVT::v4i32)
8220 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8222 // Now we need to be really careful about how we update the users of the
8223 // original load. We cannot just call DCI.CombineTo (or
8224 // DAG.ReplaceAllUsesWith for that matter), because the load still has
8225 // uses created here (the permutation for example) that need to stay.
8226 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
8228 SDUse &Use = UI.getUse();
8230 // Note: BaseLoad is checked here because it might not be N, but a
8232 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
8233 User == TF.getNode() || Use.getResNo() > 1) {
8238 SDValue To = Use.getResNo() ? TF : Perm;
8241 SmallVector<SDValue, 8> Ops;
8242 for (SDNode::op_iterator O = User->op_begin(),
8243 OE = User->op_end(); O != OE; ++O) {
8250 DAG.UpdateNodeOperands(User, Ops);
8253 return SDValue(N, 0);
8257 case ISD::INTRINSIC_WO_CHAIN: {
8258 bool isLittleEndian = Subtarget.isLittleEndian();
8259 Intrinsic::ID Intr = (isLittleEndian ?
8260 Intrinsic::ppc_altivec_lvsr :
8261 Intrinsic::ppc_altivec_lvsl);
8262 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8263 N->getOperand(1)->getOpcode() == ISD::ADD) {
8264 SDValue Add = N->getOperand(1);
8266 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8267 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8268 Add.getValueType().getScalarType().getSizeInBits()))) {
8269 SDNode *BasePtr = Add->getOperand(0).getNode();
8270 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8271 UE = BasePtr->use_end(); UI != UE; ++UI) {
8272 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8273 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8275 // We've found another LVSL/LVSR, and this address is an aligned
8276 // multiple of that one. The results will be the same, so use the
8277 // one we've just found instead.
8279 return SDValue(*UI, 0);
8288 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8289 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8290 N->getOperand(0).hasOneUse() &&
8291 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8292 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8293 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8294 N->getValueType(0) == MVT::i64))) {
8295 SDValue Load = N->getOperand(0);
8296 LoadSDNode *LD = cast<LoadSDNode>(Load);
8297 // Create the byte-swapping load.
8299 LD->getChain(), // Chain
8300 LD->getBasePtr(), // Ptr
8301 DAG.getValueType(N->getValueType(0)) // VT
8304 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8305 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8306 MVT::i64 : MVT::i32, MVT::Other),
8307 Ops, LD->getMemoryVT(), LD->getMemOperand());
8309 // If this is an i16 load, insert the truncate.
8310 SDValue ResVal = BSLoad;
8311 if (N->getValueType(0) == MVT::i16)
8312 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8314 // First, combine the bswap away. This makes the value produced by the
8316 DCI.CombineTo(N, ResVal);
8318 // Next, combine the load away, we give it a bogus result value but a real
8319 // chain result. The result value is dead because the bswap is dead.
8320 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8322 // Return N so it doesn't get rechecked!
8323 return SDValue(N, 0);
8327 case PPCISD::VCMP: {
8328 // If a VCMPo node already exists with exactly the same operands as this
8329 // node, use its result instead of this node (VCMPo computes both a CR6 and
8330 // a normal output).
8332 if (!N->getOperand(0).hasOneUse() &&
8333 !N->getOperand(1).hasOneUse() &&
8334 !N->getOperand(2).hasOneUse()) {
8336 // Scan all of the users of the LHS, looking for VCMPo's that match.
8337 SDNode *VCMPoNode = nullptr;
8339 SDNode *LHSN = N->getOperand(0).getNode();
8340 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8342 if (UI->getOpcode() == PPCISD::VCMPo &&
8343 UI->getOperand(1) == N->getOperand(1) &&
8344 UI->getOperand(2) == N->getOperand(2) &&
8345 UI->getOperand(0) == N->getOperand(0)) {
8350 // If there is no VCMPo node, or if the flag value has a single use, don't
8352 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8355 // Look at the (necessarily single) use of the flag value. If it has a
8356 // chain, this transformation is more complex. Note that multiple things
8357 // could use the value result, which we should ignore.
8358 SDNode *FlagUser = nullptr;
8359 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8360 FlagUser == nullptr; ++UI) {
8361 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8363 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8364 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8371 // If the user is a MFOCRF instruction, we know this is safe.
8372 // Otherwise we give up for right now.
8373 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8374 return SDValue(VCMPoNode, 0);
8379 SDValue Cond = N->getOperand(1);
8380 SDValue Target = N->getOperand(2);
8382 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8383 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8384 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8386 // We now need to make the intrinsic dead (it cannot be instruction
8388 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8389 assert(Cond.getNode()->hasOneUse() &&
8390 "Counter decrement has more than one use");
8392 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8393 N->getOperand(0), Target);
8398 // If this is a branch on an altivec predicate comparison, lower this so
8399 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8400 // lowering is done pre-legalize, because the legalizer lowers the predicate
8401 // compare down to code that is difficult to reassemble.
8402 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8403 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8405 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8406 // value. If so, pass-through the AND to get to the intrinsic.
8407 if (LHS.getOpcode() == ISD::AND &&
8408 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8409 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8410 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8411 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8412 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8414 LHS = LHS.getOperand(0);
8416 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8417 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8418 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8419 isa<ConstantSDNode>(RHS)) {
8420 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8421 "Counter decrement comparison is not EQ or NE");
8423 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8424 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8425 (CC == ISD::SETNE && !Val);
8427 // We now need to make the intrinsic dead (it cannot be instruction
8429 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8430 assert(LHS.getNode()->hasOneUse() &&
8431 "Counter decrement has more than one use");
8433 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8434 N->getOperand(0), N->getOperand(4));
8440 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8441 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8442 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8443 assert(isDot && "Can't compare against a vector result!");
8445 // If this is a comparison against something other than 0/1, then we know
8446 // that the condition is never/always true.
8447 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8448 if (Val != 0 && Val != 1) {
8449 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8450 return N->getOperand(0);
8451 // Always !=, turn it into an unconditional branch.
8452 return DAG.getNode(ISD::BR, dl, MVT::Other,
8453 N->getOperand(0), N->getOperand(4));
8456 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8458 // Create the PPCISD altivec 'dot' comparison node.
8460 LHS.getOperand(2), // LHS of compare
8461 LHS.getOperand(3), // RHS of compare
8462 DAG.getConstant(CompareOpc, MVT::i32)
8464 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8465 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8467 // Unpack the result based on how the target uses it.
8468 PPC::Predicate CompOpc;
8469 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8470 default: // Can't happen, don't crash on invalid number though.
8471 case 0: // Branch on the value of the EQ bit of CR6.
8472 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8474 case 1: // Branch on the inverted value of the EQ bit of CR6.
8475 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8477 case 2: // Branch on the value of the LT bit of CR6.
8478 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8480 case 3: // Branch on the inverted value of the LT bit of CR6.
8481 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8485 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8486 DAG.getConstant(CompOpc, MVT::i32),
8487 DAG.getRegister(PPC::CR6, MVT::i32),
8488 N->getOperand(4), CompNode.getValue(1));
8497 //===----------------------------------------------------------------------===//
8498 // Inline Assembly Support
8499 //===----------------------------------------------------------------------===//
8501 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8504 const SelectionDAG &DAG,
8505 unsigned Depth) const {
8506 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8507 switch (Op.getOpcode()) {
8509 case PPCISD::LBRX: {
8510 // lhbrx is known to have the top bits cleared out.
8511 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8512 KnownZero = 0xFFFF0000;
8515 case ISD::INTRINSIC_WO_CHAIN: {
8516 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8518 case Intrinsic::ppc_altivec_vcmpbfp_p:
8519 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8520 case Intrinsic::ppc_altivec_vcmpequb_p:
8521 case Intrinsic::ppc_altivec_vcmpequh_p:
8522 case Intrinsic::ppc_altivec_vcmpequw_p:
8523 case Intrinsic::ppc_altivec_vcmpgefp_p:
8524 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8525 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8526 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8527 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8528 case Intrinsic::ppc_altivec_vcmpgtub_p:
8529 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8530 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8531 KnownZero = ~1U; // All bits but the low one are known to be zero.
8539 /// getConstraintType - Given a constraint, return the type of
8540 /// constraint it is for this target.
8541 PPCTargetLowering::ConstraintType
8542 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8543 if (Constraint.size() == 1) {
8544 switch (Constraint[0]) {
8551 return C_RegisterClass;
8553 // FIXME: While Z does indicate a memory constraint, it specifically
8554 // indicates an r+r address (used in conjunction with the 'y' modifier
8555 // in the replacement string). Currently, we're forcing the base
8556 // register to be r0 in the asm printer (which is interpreted as zero)
8557 // and forming the complete address in the second register. This is
8561 } else if (Constraint == "wc") { // individual CR bits.
8562 return C_RegisterClass;
8563 } else if (Constraint == "wa" || Constraint == "wd" ||
8564 Constraint == "wf" || Constraint == "ws") {
8565 return C_RegisterClass; // VSX registers.
8567 return TargetLowering::getConstraintType(Constraint);
8570 /// Examine constraint type and operand type and determine a weight value.
8571 /// This object must already have been set up with the operand type
8572 /// and the current alternative constraint selected.
8573 TargetLowering::ConstraintWeight
8574 PPCTargetLowering::getSingleConstraintMatchWeight(
8575 AsmOperandInfo &info, const char *constraint) const {
8576 ConstraintWeight weight = CW_Invalid;
8577 Value *CallOperandVal = info.CallOperandVal;
8578 // If we don't have a value, we can't do a match,
8579 // but allow it at the lowest weight.
8580 if (!CallOperandVal)
8582 Type *type = CallOperandVal->getType();
8584 // Look at the constraint type.
8585 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8586 return CW_Register; // an individual CR bit.
8587 else if ((StringRef(constraint) == "wa" ||
8588 StringRef(constraint) == "wd" ||
8589 StringRef(constraint) == "wf") &&
8592 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8595 switch (*constraint) {
8597 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8600 if (type->isIntegerTy())
8601 weight = CW_Register;
8604 if (type->isFloatTy())
8605 weight = CW_Register;
8608 if (type->isDoubleTy())
8609 weight = CW_Register;
8612 if (type->isVectorTy())
8613 weight = CW_Register;
8616 weight = CW_Register;
8625 std::pair<unsigned, const TargetRegisterClass*>
8626 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8628 if (Constraint.size() == 1) {
8629 // GCC RS6000 Constraint Letters
8630 switch (Constraint[0]) {
8632 if (VT == MVT::i64 && Subtarget.isPPC64())
8633 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8634 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8636 if (VT == MVT::i64 && Subtarget.isPPC64())
8637 return std::make_pair(0U, &PPC::G8RCRegClass);
8638 return std::make_pair(0U, &PPC::GPRCRegClass);
8640 if (VT == MVT::f32 || VT == MVT::i32)
8641 return std::make_pair(0U, &PPC::F4RCRegClass);
8642 if (VT == MVT::f64 || VT == MVT::i64)
8643 return std::make_pair(0U, &PPC::F8RCRegClass);
8646 return std::make_pair(0U, &PPC::VRRCRegClass);
8648 return std::make_pair(0U, &PPC::CRRCRegClass);
8650 } else if (Constraint == "wc") { // an individual CR bit.
8651 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8652 } else if (Constraint == "wa" || Constraint == "wd" ||
8653 Constraint == "wf") {
8654 return std::make_pair(0U, &PPC::VSRCRegClass);
8655 } else if (Constraint == "ws") {
8656 return std::make_pair(0U, &PPC::VSFRCRegClass);
8659 std::pair<unsigned, const TargetRegisterClass*> R =
8660 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8662 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8663 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8664 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8666 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8667 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8668 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
8669 PPC::GPRCRegClass.contains(R.first)) {
8670 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
8671 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8672 PPC::sub_32, &PPC::G8RCRegClass),
8673 &PPC::G8RCRegClass);
8680 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8681 /// vector. If it is invalid, don't add anything to Ops.
8682 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8683 std::string &Constraint,
8684 std::vector<SDValue>&Ops,
8685 SelectionDAG &DAG) const {
8688 // Only support length 1 constraints.
8689 if (Constraint.length() > 1) return;
8691 char Letter = Constraint[0];
8702 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
8703 if (!CST) return; // Must be an immediate to match.
8704 unsigned Value = CST->getZExtValue();
8706 default: llvm_unreachable("Unknown constraint letter!");
8707 case 'I': // "I" is a signed 16-bit constant.
8708 if ((short)Value == (int)Value)
8709 Result = DAG.getTargetConstant(Value, Op.getValueType());
8711 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
8712 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
8713 if ((short)Value == 0)
8714 Result = DAG.getTargetConstant(Value, Op.getValueType());
8716 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
8717 if ((Value >> 16) == 0)
8718 Result = DAG.getTargetConstant(Value, Op.getValueType());
8720 case 'M': // "M" is a constant that is greater than 31.
8722 Result = DAG.getTargetConstant(Value, Op.getValueType());
8724 case 'N': // "N" is a positive constant that is an exact power of two.
8725 if ((int)Value > 0 && isPowerOf2_32(Value))
8726 Result = DAG.getTargetConstant(Value, Op.getValueType());
8728 case 'O': // "O" is the constant zero.
8730 Result = DAG.getTargetConstant(Value, Op.getValueType());
8732 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
8733 if ((short)-Value == (int)-Value)
8734 Result = DAG.getTargetConstant(Value, Op.getValueType());
8741 if (Result.getNode()) {
8742 Ops.push_back(Result);
8746 // Handle standard constraint letters.
8747 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8750 // isLegalAddressingMode - Return true if the addressing mode represented
8751 // by AM is legal for this target, for a load/store of the specified type.
8752 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
8754 // FIXME: PPC does not allow r+i addressing modes for vectors!
8756 // PPC allows a sign-extended 16-bit immediate field.
8757 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
8760 // No global is ever allowed as a base.
8764 // PPC only support r+r,
8766 case 0: // "r+i" or just "i", depending on HasBaseReg.
8769 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
8771 // Otherwise we have r+r or r+i.
8774 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
8776 // Allow 2*r as r+r.
8779 // No other scales are supported.
8786 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
8787 SelectionDAG &DAG) const {
8788 MachineFunction &MF = DAG.getMachineFunction();
8789 MachineFrameInfo *MFI = MF.getFrameInfo();
8790 MFI->setReturnAddressIsTaken(true);
8792 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
8796 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8798 // Make sure the function does not optimize away the store of the RA to
8800 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
8801 FuncInfo->setLRStoreRequired();
8802 bool isPPC64 = Subtarget.isPPC64();
8803 bool isDarwinABI = Subtarget.isDarwinABI();
8806 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
8809 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
8810 isPPC64? MVT::i64 : MVT::i32);
8811 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8812 DAG.getNode(ISD::ADD, dl, getPointerTy(),
8814 MachinePointerInfo(), false, false, false, 0);
8817 // Just load the return address off the stack.
8818 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
8819 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8820 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
8823 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
8824 SelectionDAG &DAG) const {
8826 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8828 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
8829 bool isPPC64 = PtrVT == MVT::i64;
8831 MachineFunction &MF = DAG.getMachineFunction();
8832 MachineFrameInfo *MFI = MF.getFrameInfo();
8833 MFI->setFrameAddressIsTaken(true);
8835 // Naked functions never have a frame pointer, and so we use r1. For all
8836 // other functions, this decision must be delayed until during PEI.
8838 if (MF.getFunction()->getAttributes().hasAttribute(
8839 AttributeSet::FunctionIndex, Attribute::Naked))
8840 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
8842 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
8844 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
8847 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
8848 FrameAddr, MachinePointerInfo(), false, false,
8853 // FIXME? Maybe this could be a TableGen attribute on some registers and
8854 // this table could be generated automatically from RegInfo.
8855 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
8857 bool isPPC64 = Subtarget.isPPC64();
8858 bool isDarwinABI = Subtarget.isDarwinABI();
8860 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
8861 (!isPPC64 && VT != MVT::i32))
8862 report_fatal_error("Invalid register global variable type");
8864 bool is64Bit = isPPC64 && VT == MVT::i64;
8865 unsigned Reg = StringSwitch<unsigned>(RegName)
8866 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
8867 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
8868 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
8869 (is64Bit ? PPC::X13 : PPC::R13))
8874 report_fatal_error("Invalid register name global variable");
8878 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
8879 // The PowerPC target isn't yet aware of offsets.
8883 /// getOptimalMemOpType - Returns the target specific optimal type for load
8884 /// and store operations as a result of memset, memcpy, and memmove
8885 /// lowering. If DstAlign is zero that means it's safe to destination
8886 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
8887 /// means there isn't a need to check it against alignment requirement,
8888 /// probably because the source does not need to be loaded. If 'IsMemset' is
8889 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
8890 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
8891 /// source is constant so it does not need to be loaded.
8892 /// It returns EVT::Other if the type should be determined using generic
8893 /// target-independent logic.
8894 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
8895 unsigned DstAlign, unsigned SrcAlign,
8896 bool IsMemset, bool ZeroMemset,
8898 MachineFunction &MF) const {
8899 if (Subtarget.isPPC64()) {
8906 /// \brief Returns true if it is beneficial to convert a load of a constant
8907 /// to just the constant itself.
8908 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
8910 assert(Ty->isIntegerTy());
8912 unsigned BitSize = Ty->getPrimitiveSizeInBits();
8913 if (BitSize == 0 || BitSize > 64)
8918 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
8919 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
8921 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
8922 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
8923 return NumBits1 == 64 && NumBits2 == 32;
8926 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
8927 if (!VT1.isInteger() || !VT2.isInteger())
8929 unsigned NumBits1 = VT1.getSizeInBits();
8930 unsigned NumBits2 = VT2.getSizeInBits();
8931 return NumBits1 == 64 && NumBits2 == 32;
8934 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
8935 return isInt<16>(Imm) || isUInt<16>(Imm);
8938 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
8939 return isInt<16>(Imm) || isUInt<16>(Imm);
8942 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
8945 if (DisablePPCUnaligned)
8948 // PowerPC supports unaligned memory access for simple non-vector types.
8949 // Although accessing unaligned addresses is not as efficient as accessing
8950 // aligned addresses, it is generally more efficient than manual expansion,
8951 // and generally only traps for software emulation when crossing page
8957 if (VT.getSimpleVT().isVector()) {
8958 if (Subtarget.hasVSX()) {
8959 if (VT != MVT::v2f64 && VT != MVT::v2i64)
8966 if (VT == MVT::ppcf128)
8975 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
8976 VT = VT.getScalarType();
8981 switch (VT.getSimpleVT().SimpleTy) {
8993 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
8994 EVT VT , unsigned DefinedValues) const {
8995 if (VT == MVT::v2i64)
8998 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9001 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9002 if (DisableILPPref || Subtarget.enableMachineScheduler())
9003 return TargetLowering::getSchedulingPreference(N);
9008 // Create a fast isel object.
9010 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9011 const TargetLibraryInfo *LibInfo) const {
9012 return PPC::createFastISel(FuncInfo, LibInfo);