1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCTargetMachine.h"
16 #include "PPCPerfectShuffle.h"
17 #include "llvm/ADT/VectorExtras.h"
18 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Function.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Target/TargetOptions.h"
31 PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
32 : TargetLowering(TM) {
34 // Fold away setcc operations if possible.
35 setSetCCIsExpensive();
38 // Use _setjmp/_longjmp instead of setjmp/longjmp.
39 setUseUnderscoreSetJmpLongJmp(true);
41 // Set up the register classes.
42 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
43 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
44 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
46 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
47 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
49 // PowerPC has no intrinsics for these particular operations
50 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
51 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
52 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
54 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
55 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
56 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
58 // PowerPC has no SREM/UREM instructions
59 setOperationAction(ISD::SREM, MVT::i32, Expand);
60 setOperationAction(ISD::UREM, MVT::i32, Expand);
62 // We don't support sin/cos/sqrt/fmod
63 setOperationAction(ISD::FSIN , MVT::f64, Expand);
64 setOperationAction(ISD::FCOS , MVT::f64, Expand);
65 setOperationAction(ISD::FREM , MVT::f64, Expand);
66 setOperationAction(ISD::FSIN , MVT::f32, Expand);
67 setOperationAction(ISD::FCOS , MVT::f32, Expand);
68 setOperationAction(ISD::FREM , MVT::f32, Expand);
70 // If we're enabling GP optimizations, use hardware square root
71 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
72 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
73 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
76 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
77 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
79 // PowerPC does not have BSWAP, CTPOP or CTTZ
80 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
81 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
82 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
84 // PowerPC does not have ROTR
85 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
87 // PowerPC does not have Select
88 setOperationAction(ISD::SELECT, MVT::i32, Expand);
89 setOperationAction(ISD::SELECT, MVT::f32, Expand);
90 setOperationAction(ISD::SELECT, MVT::f64, Expand);
92 // PowerPC wants to turn select_cc of FP into fsel when possible.
93 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
94 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
96 // PowerPC wants to optimize integer setcc a bit
97 setOperationAction(ISD::SETCC, MVT::i32, Custom);
99 // PowerPC does not have BRCOND which requires SetCC
100 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
102 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
103 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
105 // PowerPC does not have [U|S]INT_TO_FP
106 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
109 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
110 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
112 // PowerPC does not have truncstore for i1.
113 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
115 // We cannot sextinreg(i1). Expand to shifts.
116 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
119 // Support label based line numbers.
120 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
121 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
122 // FIXME - use subtarget debug flags
123 if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
124 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
126 // We want to legalize GlobalAddress and ConstantPool nodes into the
127 // appropriate instructions to materialize the address.
128 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
129 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
130 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
132 // RET must be custom lowered, to meet ABI requirements
133 setOperationAction(ISD::RET , MVT::Other, Custom);
135 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
136 setOperationAction(ISD::VASTART , MVT::Other, Custom);
138 // Use the default implementation.
139 setOperationAction(ISD::VAARG , MVT::Other, Expand);
140 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
141 setOperationAction(ISD::VAEND , MVT::Other, Expand);
142 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
143 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
144 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
146 // We want to custom lower some of our intrinsics.
147 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
149 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
150 // They also have instructions for converting between i64 and fp.
151 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
152 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
154 // FIXME: disable this lowered code. This generates 64-bit register values,
155 // and we don't model the fact that the top part is clobbered by calls. We
156 // need to flag these together so that the value isn't live across a call.
157 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
159 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
160 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
162 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
163 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
166 if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) {
167 // 64 bit PowerPC implementations can support i64 types directly
168 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
169 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
170 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
172 // 32 bit PowerPC wants to expand i64 shifts itself.
173 setOperationAction(ISD::SHL, MVT::i64, Custom);
174 setOperationAction(ISD::SRL, MVT::i64, Custom);
175 setOperationAction(ISD::SRA, MVT::i64, Custom);
178 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
179 // First set operation action for all vector types to expand. Then we
180 // will selectively turn on ones that can be effectively codegen'd.
181 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
182 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
183 // add/sub are legal for all supported vector VT's.
184 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
185 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
187 // We promote all shuffles to v16i8.
188 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
189 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
191 // We promote all non-typed operations to v4i32.
192 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
193 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
194 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
195 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
196 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
197 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
198 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
199 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
200 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
201 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
202 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
203 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
205 // No other operations are legal.
206 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
207 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
208 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
209 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
210 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
211 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
212 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
213 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
214 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
216 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
219 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
220 // with merges, splats, etc.
221 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
223 setOperationAction(ISD::AND , MVT::v4i32, Legal);
224 setOperationAction(ISD::OR , MVT::v4i32, Legal);
225 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
226 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
227 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
228 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
230 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
231 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
232 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
233 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
235 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
236 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
237 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
238 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
240 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
241 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
243 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
244 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
245 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
246 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
249 setSetCCResultContents(ZeroOrOneSetCCResult);
250 setStackPointerRegisterToSaveRestore(PPC::R1);
252 // We have target-specific dag combine patterns for the following nodes:
253 setTargetDAGCombine(ISD::SINT_TO_FP);
254 setTargetDAGCombine(ISD::STORE);
255 setTargetDAGCombine(ISD::BR_CC);
257 computeRegisterProperties();
260 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
263 case PPCISD::FSEL: return "PPCISD::FSEL";
264 case PPCISD::FCFID: return "PPCISD::FCFID";
265 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
266 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
267 case PPCISD::STFIWX: return "PPCISD::STFIWX";
268 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
269 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
270 case PPCISD::VPERM: return "PPCISD::VPERM";
271 case PPCISD::Hi: return "PPCISD::Hi";
272 case PPCISD::Lo: return "PPCISD::Lo";
273 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
274 case PPCISD::SRL: return "PPCISD::SRL";
275 case PPCISD::SRA: return "PPCISD::SRA";
276 case PPCISD::SHL: return "PPCISD::SHL";
277 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
278 case PPCISD::STD_32: return "PPCISD::STD_32";
279 case PPCISD::CALL: return "PPCISD::CALL";
280 case PPCISD::MTCTR: return "PPCISD::MTCTR";
281 case PPCISD::BCTRL: return "PPCISD::BCTRL";
282 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
283 case PPCISD::MFCR: return "PPCISD::MFCR";
284 case PPCISD::VCMP: return "PPCISD::VCMP";
285 case PPCISD::VCMPo: return "PPCISD::VCMPo";
286 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
290 //===----------------------------------------------------------------------===//
291 // Node matching predicates, for use by the tblgen matching code.
292 //===----------------------------------------------------------------------===//
294 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
295 static bool isFloatingPointZero(SDOperand Op) {
296 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
297 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
298 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
299 // Maybe this has already been legalized into the constant pool?
300 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
301 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
302 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
307 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
308 /// true if Op is undef or if it matches the specified value.
309 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
310 return Op.getOpcode() == ISD::UNDEF ||
311 cast<ConstantSDNode>(Op)->getValue() == Val;
314 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
315 /// VPKUHUM instruction.
316 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
318 for (unsigned i = 0; i != 16; ++i)
319 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
322 for (unsigned i = 0; i != 8; ++i)
323 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
324 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
330 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
331 /// VPKUWUM instruction.
332 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
334 for (unsigned i = 0; i != 16; i += 2)
335 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
336 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
339 for (unsigned i = 0; i != 8; i += 2)
340 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
341 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
342 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
343 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
349 /// isVMerge - Common function, used to match vmrg* shuffles.
351 static bool isVMerge(SDNode *N, unsigned UnitSize,
352 unsigned LHSStart, unsigned RHSStart) {
353 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
354 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
355 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
356 "Unsupported merge size!");
358 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
359 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
360 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
361 LHSStart+j+i*UnitSize) ||
362 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
363 RHSStart+j+i*UnitSize))
369 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
370 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
371 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
373 return isVMerge(N, UnitSize, 8, 24);
374 return isVMerge(N, UnitSize, 8, 8);
377 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
378 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
379 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
381 return isVMerge(N, UnitSize, 0, 16);
382 return isVMerge(N, UnitSize, 0, 0);
386 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
387 /// amount, otherwise return -1.
388 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
389 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
390 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
391 // Find the first non-undef value in the shuffle mask.
393 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
396 if (i == 16) return -1; // all undef.
398 // Otherwise, check to see if the rest of the elements are consequtively
399 // numbered from this value.
400 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
401 if (ShiftAmt < i) return -1;
405 // Check the rest of the elements to see if they are consequtive.
406 for (++i; i != 16; ++i)
407 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
410 // Check the rest of the elements to see if they are consequtive.
411 for (++i; i != 16; ++i)
412 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
419 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
420 /// specifies a splat of a single element that is suitable for input to
421 /// VSPLTB/VSPLTH/VSPLTW.
422 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
423 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
424 N->getNumOperands() == 16 &&
425 (EltSize == 1 || EltSize == 2 || EltSize == 4));
427 // This is a splat operation if each element of the permute is the same, and
428 // if the value doesn't reference the second vector.
429 unsigned ElementBase = 0;
430 SDOperand Elt = N->getOperand(0);
431 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
432 ElementBase = EltV->getValue();
434 return false; // FIXME: Handle UNDEF elements too!
436 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
439 // Check that they are consequtive.
440 for (unsigned i = 1; i != EltSize; ++i) {
441 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
442 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
446 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
447 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
448 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
449 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
450 "Invalid VECTOR_SHUFFLE mask!");
451 for (unsigned j = 0; j != EltSize; ++j)
452 if (N->getOperand(i+j) != N->getOperand(j))
459 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
460 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
461 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
462 assert(isSplatShuffleMask(N, EltSize));
463 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
466 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
467 /// by using a vspltis[bhw] instruction of the specified element size, return
468 /// the constant being splatted. The ByteSize field indicates the number of
469 /// bytes of each element [124] -> [bhw].
470 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
471 SDOperand OpVal(0, 0);
473 // If ByteSize of the splat is bigger than the element size of the
474 // build_vector, then we have a case where we are checking for a splat where
475 // multiple elements of the buildvector are folded together into a single
476 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
477 unsigned EltSize = 16/N->getNumOperands();
478 if (EltSize < ByteSize) {
479 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
480 SDOperand UniquedVals[4];
481 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
483 // See if all of the elements in the buildvector agree across.
484 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
485 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
486 // If the element isn't a constant, bail fully out.
487 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
490 if (UniquedVals[i&(Multiple-1)].Val == 0)
491 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
492 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
493 return SDOperand(); // no match.
496 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
497 // either constant or undef values that are identical for each chunk. See
498 // if these chunks can form into a larger vspltis*.
500 // Check to see if all of the leading entries are either 0 or -1. If
501 // neither, then this won't fit into the immediate field.
502 bool LeadingZero = true;
503 bool LeadingOnes = true;
504 for (unsigned i = 0; i != Multiple-1; ++i) {
505 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
507 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
508 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
510 // Finally, check the least significant entry.
512 if (UniquedVals[Multiple-1].Val == 0)
513 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
514 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
516 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
519 if (UniquedVals[Multiple-1].Val == 0)
520 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
521 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
522 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
523 return DAG.getTargetConstant(Val, MVT::i32);
529 // Check to see if this buildvec has a single non-undef value in its elements.
530 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
531 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
533 OpVal = N->getOperand(i);
534 else if (OpVal != N->getOperand(i))
538 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
540 unsigned ValSizeInBytes = 0;
542 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
543 Value = CN->getValue();
544 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
545 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
546 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
547 Value = FloatToBits(CN->getValue());
551 // If the splat value is larger than the element value, then we can never do
552 // this splat. The only case that we could fit the replicated bits into our
553 // immediate field for would be zero, and we prefer to use vxor for it.
554 if (ValSizeInBytes < ByteSize) return SDOperand();
556 // If the element value is larger than the splat value, cut it in half and
557 // check to see if the two halves are equal. Continue doing this until we
558 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
559 while (ValSizeInBytes > ByteSize) {
560 ValSizeInBytes >>= 1;
562 // If the top half equals the bottom half, we're still ok.
563 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
564 (Value & ((1 << (8*ValSizeInBytes))-1)))
568 // Properly sign extend the value.
569 int ShAmt = (4-ByteSize)*8;
570 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
572 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
573 if (MaskVal == 0) return SDOperand();
575 // Finally, if this value fits in a 5 bit sext field, return it
576 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
577 return DAG.getTargetConstant(MaskVal, MVT::i32);
581 //===----------------------------------------------------------------------===//
582 // LowerOperation implementation
583 //===----------------------------------------------------------------------===//
585 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
586 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
587 Constant *C = CP->get();
588 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32, CP->getAlignment());
589 SDOperand Zero = DAG.getConstant(0, MVT::i32);
591 const TargetMachine &TM = DAG.getTarget();
593 // If this is a non-darwin platform, we don't support non-static relo models
595 if (TM.getRelocationModel() == Reloc::Static ||
596 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
597 // Generate non-pic code that has direct accesses to the constant pool.
598 // The address of the global is just (hi(&g)+lo(&g)).
599 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
600 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
601 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
604 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
605 if (TM.getRelocationModel() == Reloc::PIC) {
606 // With PIC, the first instruction is actually "GR+hi(&G)".
607 Hi = DAG.getNode(ISD::ADD, MVT::i32,
608 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
611 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
612 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
616 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
617 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
618 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
619 SDOperand Zero = DAG.getConstant(0, MVT::i32);
621 const TargetMachine &TM = DAG.getTarget();
623 // If this is a non-darwin platform, we don't support non-static relo models
625 if (TM.getRelocationModel() == Reloc::Static ||
626 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
627 // Generate non-pic code that has direct accesses to the constant pool.
628 // The address of the global is just (hi(&g)+lo(&g)).
629 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, JTI, Zero);
630 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, JTI, Zero);
631 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
634 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, JTI, Zero);
635 if (TM.getRelocationModel() == Reloc::PIC) {
636 // With PIC, the first instruction is actually "GR+hi(&G)".
637 Hi = DAG.getNode(ISD::ADD, MVT::i32,
638 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
641 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, JTI, Zero);
642 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
646 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
647 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
648 GlobalValue *GV = GSDN->getGlobal();
649 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset());
650 SDOperand Zero = DAG.getConstant(0, MVT::i32);
652 const TargetMachine &TM = DAG.getTarget();
654 // If this is a non-darwin platform, we don't support non-static relo models
656 if (TM.getRelocationModel() == Reloc::Static ||
657 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
658 // Generate non-pic code that has direct accesses to globals.
659 // The address of the global is just (hi(&g)+lo(&g)).
660 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
661 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
662 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
665 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
666 if (TM.getRelocationModel() == Reloc::PIC) {
667 // With PIC, the first instruction is actually "GR+hi(&G)".
668 Hi = DAG.getNode(ISD::ADD, MVT::i32,
669 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
672 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
673 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
675 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() &&
676 (!GV->isExternal() || GV->hasNotBeenReadFromBytecode()))
679 // If the global is weak or external, we have to go through the lazy
681 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
684 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
685 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
687 // If we're comparing for equality to zero, expose the fact that this is
688 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
689 // fold the new nodes.
690 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
691 if (C->isNullValue() && CC == ISD::SETEQ) {
692 MVT::ValueType VT = Op.getOperand(0).getValueType();
693 SDOperand Zext = Op.getOperand(0);
696 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
698 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
699 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
700 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
701 DAG.getConstant(Log2b, MVT::i32));
702 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
704 // Leave comparisons against 0 and -1 alone for now, since they're usually
705 // optimized. FIXME: revisit this when we can custom lower all setcc
707 if (C->isAllOnesValue() || C->isNullValue())
711 // If we have an integer seteq/setne, turn it into a compare against zero
712 // by subtracting the rhs from the lhs, which is faster than setting a
713 // condition register, reading it back out, and masking the correct bit.
714 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
715 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
716 MVT::ValueType VT = Op.getValueType();
717 SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0),
719 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
724 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
725 unsigned VarArgsFrameIndex) {
726 // vastart just stores the address of the VarArgsFrameIndex slot into the
727 // memory location argument.
728 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
729 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
730 Op.getOperand(1), Op.getOperand(2));
733 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
734 int &VarArgsFrameIndex) {
735 // TODO: add description of PPC stack frame format, or at least some docs.
737 MachineFunction &MF = DAG.getMachineFunction();
738 MachineFrameInfo *MFI = MF.getFrameInfo();
739 SSARegMap *RegMap = MF.getSSARegMap();
740 std::vector<SDOperand> ArgValues;
741 SDOperand Root = Op.getOperand(0);
743 unsigned ArgOffset = 24;
744 const unsigned Num_GPR_Regs = 8;
745 const unsigned Num_FPR_Regs = 13;
746 const unsigned Num_VR_Regs = 12;
747 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
748 static const unsigned GPR[] = {
749 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
750 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
752 static const unsigned FPR[] = {
753 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
754 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
756 static const unsigned VR[] = {
757 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
758 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
761 // Add DAG nodes to load the arguments or copy them out of registers. On
762 // entry to a function on PPC, the arguments start at offset 24, although the
763 // first ones are often in registers.
764 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
766 bool needsLoad = false;
767 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
768 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
770 unsigned CurArgOffset = ArgOffset;
773 default: assert(0 && "Unhandled argument type!");
775 // All int arguments reserve stack space.
778 if (GPR_idx != Num_GPR_Regs) {
779 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
780 MF.addLiveIn(GPR[GPR_idx], VReg);
781 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
789 // All FP arguments reserve stack space.
790 ArgOffset += ObjSize;
792 // Every 4 bytes of argument space consumes one of the GPRs available for
794 if (GPR_idx != Num_GPR_Regs) {
796 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs)
799 if (FPR_idx != Num_FPR_Regs) {
801 if (ObjectVT == MVT::f32)
802 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
804 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
805 MF.addLiveIn(FPR[FPR_idx], VReg);
806 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
816 // Note that vector arguments in registers don't reserve stack space.
817 if (VR_idx != Num_VR_Regs) {
818 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass);
819 MF.addLiveIn(VR[VR_idx], VReg);
820 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
823 // This should be simple, but requires getting 16-byte aligned stack
825 assert(0 && "Loading VR argument not implemented yet!");
831 // We need to load the argument to a virtual register if we determined above
832 // that we ran out of physical registers of the appropriate type
834 // If the argument is actually used, emit a load from the right stack
836 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
837 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
838 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
839 ArgVal = DAG.getLoad(ObjectVT, Root, FIN,
840 DAG.getSrcValue(NULL));
842 // Don't emit a dead load.
843 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
847 ArgValues.push_back(ArgVal);
850 // If the function takes variable number of arguments, make a frame index for
851 // the start of the first vararg value... for expansion of llvm.va_start.
852 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
854 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
855 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
856 // If this function is vararg, store any remaining integer argument regs
857 // to their spots on the stack so that they may be loaded by deferencing the
858 // result of va_next.
859 std::vector<SDOperand> MemOps;
860 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
861 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
862 MF.addLiveIn(GPR[GPR_idx], VReg);
863 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::i32);
864 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
865 Val, FIN, DAG.getSrcValue(NULL));
866 MemOps.push_back(Store);
867 // Increment the address by four for the next argument to store
868 SDOperand PtrOff = DAG.getConstant(4, MVT::i32);
869 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
872 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
875 ArgValues.push_back(Root);
877 // Return the new list of results.
878 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
879 Op.Val->value_end());
880 return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
883 /// isCallCompatibleAddress - Return the immediate to use if the specified
884 /// 32-bit value is representable in the immediate field of a BxA instruction.
885 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
886 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
889 int Addr = C->getValue();
890 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
891 (Addr << 6 >> 6) != Addr)
892 return 0; // Top 6 bits have to be sext of immediate.
894 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
898 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
899 SDOperand Chain = Op.getOperand(0);
900 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
901 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
902 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
903 SDOperand Callee = Op.getOperand(4);
904 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
906 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
907 // SelectExpr to use to put the arguments in the appropriate registers.
908 std::vector<SDOperand> args_to_use;
910 // Count how many bytes are to be pushed on the stack, including the linkage
911 // area, and parameter passing area. We start with 24 bytes, which is
912 // prereserved space for [SP][CR][LR][3 x unused].
913 unsigned NumBytes = 24;
915 // Add up all the space actually used.
916 for (unsigned i = 0; i != NumOps; ++i)
917 NumBytes += MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
919 // The prolog code of the callee may store up to 8 GPR argument registers to
920 // the stack, allowing va_start to index over them in memory if its varargs.
921 // Because we cannot tell if this is needed on the caller side, we have to
922 // conservatively assume that it is needed. As such, make sure we have at
923 // least enough stack space for the caller to store the 8 GPRs.
924 if (NumBytes < 24+8*4)
927 // Adjust the stack pointer for the new arguments...
928 // These operations are automatically eliminated by the prolog/epilog pass
929 Chain = DAG.getCALLSEQ_START(Chain,
930 DAG.getConstant(NumBytes, MVT::i32));
932 // Set up a copy of the stack pointer for use loading and storing any
933 // arguments that may not fit in the registers available for argument
935 SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
937 // Figure out which arguments are going to go in registers, and which in
938 // memory. Also, if this is a vararg function, floating point operations
939 // must be stored to our stack, and loaded into integer regs as well, if
940 // any integer regs are available for argument passing.
941 unsigned ArgOffset = 24;
942 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
943 static const unsigned GPR[] = {
944 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
945 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
947 static const unsigned FPR[] = {
948 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
949 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
951 static const unsigned VR[] = {
952 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
953 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
955 const unsigned NumGPRs = sizeof(GPR)/sizeof(GPR[0]);
956 const unsigned NumFPRs = sizeof(FPR)/sizeof(FPR[0]);
957 const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]);
959 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
960 std::vector<SDOperand> MemOpChains;
961 for (unsigned i = 0; i != NumOps; ++i) {
962 SDOperand Arg = Op.getOperand(5+2*i);
964 // PtrOff will be used to store the current argument to the stack if a
965 // register cannot be found for it.
966 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
967 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
968 switch (Arg.getValueType()) {
969 default: assert(0 && "Unexpected ValueType for argument!");
971 if (GPR_idx != NumGPRs) {
972 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
974 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
975 Arg, PtrOff, DAG.getSrcValue(NULL)));
981 if (FPR_idx != NumFPRs) {
982 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
985 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
987 DAG.getSrcValue(NULL));
988 MemOpChains.push_back(Store);
990 // Float varargs are always shadowed in available integer registers
991 if (GPR_idx != NumGPRs) {
992 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
993 DAG.getSrcValue(NULL));
994 MemOpChains.push_back(Load.getValue(1));
995 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
997 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) {
998 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
999 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
1000 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
1001 DAG.getSrcValue(NULL));
1002 MemOpChains.push_back(Load.getValue(1));
1003 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1006 // If we have any FPRs remaining, we may also have GPRs remaining.
1007 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1009 if (GPR_idx != NumGPRs)
1011 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64)
1015 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1016 Arg, PtrOff, DAG.getSrcValue(NULL)));
1018 ArgOffset += (Arg.getValueType() == MVT::f32) ? 4 : 8;
1024 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1025 assert(VR_idx != NumVRs &&
1026 "Don't support passing more than 12 vector args yet!");
1027 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1031 if (!MemOpChains.empty())
1032 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOpChains);
1034 // Build a sequence of copy-to-reg nodes chained together with token chain
1035 // and flag operands which copy the outgoing args into the appropriate regs.
1037 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1038 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1040 InFlag = Chain.getValue(1);
1043 std::vector<MVT::ValueType> NodeTys;
1045 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1046 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1047 // node so that legalize doesn't hack it.
1048 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1049 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1050 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1051 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1052 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1053 // If this is an absolute destination address, use the munged value.
1054 Callee = SDOperand(Dest, 0);
1056 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1057 // to do the call, we can't use PPCISD::CALL.
1058 std::vector<SDOperand> Ops;
1059 Ops.push_back(Chain);
1060 Ops.push_back(Callee);
1061 NodeTys.push_back(MVT::Other);
1062 NodeTys.push_back(MVT::Flag);
1065 Ops.push_back(InFlag);
1066 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, Ops);
1067 InFlag = Chain.getValue(1);
1069 // Copy the callee address into R12 on darwin.
1070 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1071 InFlag = Chain.getValue(1);
1074 NodeTys.push_back(MVT::Other);
1075 NodeTys.push_back(MVT::Flag);
1077 Ops.push_back(Chain);
1078 Ops.push_back(InFlag);
1079 Chain = DAG.getNode(PPCISD::BCTRL, NodeTys, Ops);
1080 InFlag = Chain.getValue(1);
1084 // Create the PPCISD::CALL node itself.
1086 NodeTys.push_back(MVT::Other); // Returns a chain
1087 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1088 std::vector<SDOperand> Ops;
1089 Ops.push_back(Chain);
1090 Ops.push_back(Callee);
1092 Ops.push_back(InFlag);
1093 Chain = DAG.getNode(PPCISD::CALL, NodeTys, Ops);
1094 InFlag = Chain.getValue(1);
1097 std::vector<SDOperand> ResultVals;
1100 // If the call has results, copy the values out of the ret val registers.
1101 switch (Op.Val->getValueType(0)) {
1102 default: assert(0 && "Unexpected ret value!");
1103 case MVT::Other: break;
1105 if (Op.Val->getValueType(1) == MVT::i32) {
1106 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1);
1107 ResultVals.push_back(Chain.getValue(0));
1108 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32,
1109 Chain.getValue(2)).getValue(1);
1110 ResultVals.push_back(Chain.getValue(0));
1111 NodeTys.push_back(MVT::i32);
1113 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1114 ResultVals.push_back(Chain.getValue(0));
1116 NodeTys.push_back(MVT::i32);
1120 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1121 InFlag).getValue(1);
1122 ResultVals.push_back(Chain.getValue(0));
1123 NodeTys.push_back(Op.Val->getValueType(0));
1129 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1130 InFlag).getValue(1);
1131 ResultVals.push_back(Chain.getValue(0));
1132 NodeTys.push_back(Op.Val->getValueType(0));
1136 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1137 DAG.getConstant(NumBytes, MVT::i32));
1138 NodeTys.push_back(MVT::Other);
1140 // If the function returns void, just return the chain.
1141 if (ResultVals.empty())
1144 // Otherwise, merge everything together with a MERGE_VALUES node.
1145 ResultVals.push_back(Chain);
1146 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, ResultVals);
1147 return Res.getValue(Op.ResNo);
1150 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
1152 switch(Op.getNumOperands()) {
1154 assert(0 && "Do not know how to return this many arguments!");
1157 return SDOperand(); // ret void is legal
1159 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
1161 if (MVT::isVector(ArgVT))
1163 else if (MVT::isInteger(ArgVT))
1166 assert(MVT::isFloatingPoint(ArgVT));
1170 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
1173 // If we haven't noted the R3/F1 are live out, do so now.
1174 if (DAG.getMachineFunction().liveout_empty())
1175 DAG.getMachineFunction().addLiveOut(ArgReg);
1179 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3),
1181 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
1182 // If we haven't noted the R3+R4 are live out, do so now.
1183 if (DAG.getMachineFunction().liveout_empty()) {
1184 DAG.getMachineFunction().addLiveOut(PPC::R3);
1185 DAG.getMachineFunction().addLiveOut(PPC::R4);
1189 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
1192 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
1194 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
1195 // Not FP? Not a fsel.
1196 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
1197 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
1200 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1202 // Cannot handle SETEQ/SETNE.
1203 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
1205 MVT::ValueType ResVT = Op.getValueType();
1206 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
1207 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1208 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
1210 // If the RHS of the comparison is a 0.0, we don't need to do the
1211 // subtraction at all.
1212 if (isFloatingPointZero(RHS))
1214 default: break; // SETUO etc aren't handled by fsel.
1218 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1222 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1223 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1224 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
1228 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1232 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1233 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1234 return DAG.getNode(PPCISD::FSEL, ResVT,
1235 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
1240 default: break; // SETUO etc aren't handled by fsel.
1244 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1245 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1246 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1247 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1251 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1252 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1253 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1254 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1258 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1259 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1260 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1261 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1265 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1266 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1267 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1268 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1273 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
1274 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
1275 SDOperand Src = Op.getOperand(0);
1276 if (Src.getValueType() == MVT::f32)
1277 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
1280 switch (Op.getValueType()) {
1281 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
1283 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
1286 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
1290 // Convert the FP value to an int value through memory.
1291 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
1292 if (Op.getValueType() == MVT::i32)
1293 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
1297 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1298 if (Op.getOperand(0).getValueType() == MVT::i64) {
1299 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
1300 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
1301 if (Op.getValueType() == MVT::f32)
1302 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1306 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
1307 "Unhandled SINT_TO_FP type in custom expander!");
1308 // Since we only generate this in 64-bit mode, we can take advantage of
1309 // 64-bit registers. In particular, sign extend the input value into the
1310 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
1311 // then lfd it and fcfid it.
1312 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
1313 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
1314 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
1316 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
1319 // STD the extended value into the stack slot.
1320 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
1321 DAG.getEntryNode(), Ext64, FIdx,
1322 DAG.getSrcValue(NULL));
1323 // Load the value as a double.
1324 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL));
1326 // FCFID it and return it.
1327 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
1328 if (Op.getValueType() == MVT::f32)
1329 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1333 static SDOperand LowerSHL(SDOperand Op, SelectionDAG &DAG) {
1334 assert(Op.getValueType() == MVT::i64 &&
1335 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
1336 // The generic code does a fine job expanding shift by a constant.
1337 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
1339 // Otherwise, expand into a bunch of logical ops. Note that these ops
1340 // depend on the PPC behavior for oversized shift amounts.
1341 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1342 DAG.getConstant(0, MVT::i32));
1343 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1344 DAG.getConstant(1, MVT::i32));
1345 SDOperand Amt = Op.getOperand(1);
1347 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1348 DAG.getConstant(32, MVT::i32), Amt);
1349 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
1350 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
1351 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1352 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1353 DAG.getConstant(-32U, MVT::i32));
1354 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
1355 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1356 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
1357 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
1360 static SDOperand LowerSRL(SDOperand Op, SelectionDAG &DAG) {
1361 assert(Op.getValueType() == MVT::i64 &&
1362 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
1363 // The generic code does a fine job expanding shift by a constant.
1364 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
1366 // Otherwise, expand into a bunch of logical ops. Note that these ops
1367 // depend on the PPC behavior for oversized shift amounts.
1368 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1369 DAG.getConstant(0, MVT::i32));
1370 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1371 DAG.getConstant(1, MVT::i32));
1372 SDOperand Amt = Op.getOperand(1);
1374 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1375 DAG.getConstant(32, MVT::i32), Amt);
1376 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1377 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1378 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1379 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1380 DAG.getConstant(-32U, MVT::i32));
1381 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
1382 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1383 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
1384 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
1387 static SDOperand LowerSRA(SDOperand Op, SelectionDAG &DAG) {
1388 assert(Op.getValueType() == MVT::i64 &&
1389 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
1390 // The generic code does a fine job expanding shift by a constant.
1391 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
1393 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
1394 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1395 DAG.getConstant(0, MVT::i32));
1396 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1397 DAG.getConstant(1, MVT::i32));
1398 SDOperand Amt = Op.getOperand(1);
1400 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1401 DAG.getConstant(32, MVT::i32), Amt);
1402 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1403 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1404 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1405 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1406 DAG.getConstant(-32U, MVT::i32));
1407 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
1408 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
1409 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
1410 Tmp4, Tmp6, ISD::SETLE);
1411 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
1414 //===----------------------------------------------------------------------===//
1415 // Vector related lowering.
1418 // If this is a vector of constants or undefs, get the bits. A bit in
1419 // UndefBits is set if the corresponding element of the vector is an
1420 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1421 // zero. Return true if this is not an array of constants, false if it is.
1423 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
1424 uint64_t UndefBits[2]) {
1425 // Start with zero'd results.
1426 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
1428 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
1429 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
1430 SDOperand OpVal = BV->getOperand(i);
1432 unsigned PartNo = i >= e/2; // In the upper 128 bits?
1433 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
1435 uint64_t EltBits = 0;
1436 if (OpVal.getOpcode() == ISD::UNDEF) {
1437 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
1438 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
1440 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1441 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
1442 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1443 assert(CN->getValueType(0) == MVT::f32 &&
1444 "Only one legal FP vector type!");
1445 EltBits = FloatToBits(CN->getValue());
1447 // Nonconstant element.
1451 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
1454 //printf("%llx %llx %llx %llx\n",
1455 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
1459 // If this is a splat (repetition) of a value across the whole vector, return
1460 // the smallest size that splats it. For example, "0x01010101010101..." is a
1461 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1462 // SplatSize = 1 byte.
1463 static bool isConstantSplat(const uint64_t Bits128[2],
1464 const uint64_t Undef128[2],
1465 unsigned &SplatBits, unsigned &SplatUndef,
1466 unsigned &SplatSize) {
1468 // Don't let undefs prevent splats from matching. See if the top 64-bits are
1469 // the same as the lower 64-bits, ignoring undefs.
1470 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
1471 return false; // Can't be a splat if two pieces don't match.
1473 uint64_t Bits64 = Bits128[0] | Bits128[1];
1474 uint64_t Undef64 = Undef128[0] & Undef128[1];
1476 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
1478 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
1479 return false; // Can't be a splat if two pieces don't match.
1481 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
1482 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
1484 // If the top 16-bits are different than the lower 16-bits, ignoring
1485 // undefs, we have an i32 splat.
1486 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
1488 SplatUndef = Undef32;
1493 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
1494 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
1496 // If the top 8-bits are different than the lower 8-bits, ignoring
1497 // undefs, we have an i16 splat.
1498 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
1500 SplatUndef = Undef16;
1505 // Otherwise, we have an 8-bit splat.
1506 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
1507 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
1512 /// BuildSplatI - Build a canonical splati of Val with an element size of
1513 /// SplatSize. Cast the result to VT.
1514 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
1515 SelectionDAG &DAG) {
1516 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
1518 // Force vspltis[hw] -1 to vspltisb -1.
1519 if (Val == -1) SplatSize = 1;
1521 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
1522 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
1524 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
1526 // Build a canonical splat for this value.
1527 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT));
1528 std::vector<SDOperand> Ops(MVT::getVectorNumElements(CanonicalVT), Elt);
1529 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops);
1530 return DAG.getNode(ISD::BIT_CONVERT, VT, Res);
1533 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
1534 /// specified intrinsic ID.
1535 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
1537 MVT::ValueType DestVT = MVT::Other) {
1538 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
1539 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1540 DAG.getConstant(IID, MVT::i32), LHS, RHS);
1543 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
1544 /// specified intrinsic ID.
1545 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
1546 SDOperand Op2, SelectionDAG &DAG,
1547 MVT::ValueType DestVT = MVT::Other) {
1548 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
1549 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1550 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
1554 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
1555 /// amount. The result has the specified value type.
1556 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
1557 MVT::ValueType VT, SelectionDAG &DAG) {
1558 // Force LHS/RHS to be the right type.
1559 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
1560 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
1562 std::vector<SDOperand> Ops;
1563 for (unsigned i = 0; i != 16; ++i)
1564 Ops.push_back(DAG.getConstant(i+Amt, MVT::i32));
1565 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
1566 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
1567 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
1570 // If this is a case we can't handle, return null and let the default
1571 // expansion code take care of it. If we CAN select this case, and if it
1572 // selects to a single instruction, return Op. Otherwise, if we can codegen
1573 // this case more efficiently than a constant pool load, lower it to the
1574 // sequence of ops that should be used.
1575 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
1576 // If this is a vector of constants or undefs, get the bits. A bit in
1577 // UndefBits is set if the corresponding element of the vector is an
1578 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1580 uint64_t VectorBits[2];
1581 uint64_t UndefBits[2];
1582 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
1583 return SDOperand(); // Not a constant vector.
1585 // If this is a splat (repetition) of a value across the whole vector, return
1586 // the smallest size that splats it. For example, "0x01010101010101..." is a
1587 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1588 // SplatSize = 1 byte.
1589 unsigned SplatBits, SplatUndef, SplatSize;
1590 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
1591 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
1593 // First, handle single instruction cases.
1596 if (SplatBits == 0) {
1597 // Canonicalize all zero vectors to be v4i32.
1598 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
1599 SDOperand Z = DAG.getConstant(0, MVT::i32);
1600 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
1601 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
1606 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
1607 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
1608 if (SextVal >= -16 && SextVal <= 15)
1609 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
1612 // Two instruction sequences.
1614 // If this value is in the range [-32,30] and is even, use:
1615 // tmp = VSPLTI[bhw], result = add tmp, tmp
1616 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
1617 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
1618 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
1621 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
1622 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
1624 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
1625 // Make -1 and vspltisw -1:
1626 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
1628 // Make the VSLW intrinsic, computing 0x8000_0000.
1629 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
1632 // xor by OnesV to invert it.
1633 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
1634 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
1637 // Check to see if this is a wide variety of vsplti*, binop self cases.
1638 unsigned SplatBitSize = SplatSize*8;
1639 static const char SplatCsts[] = {
1640 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
1641 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
1643 for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){
1644 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
1645 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
1646 int i = SplatCsts[idx];
1648 // Figure out what shift amount will be used by altivec if shifted by i in
1650 unsigned TypeShiftAmt = i & (SplatBitSize-1);
1652 // vsplti + shl self.
1653 if (SextVal == (i << (int)TypeShiftAmt)) {
1654 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1655 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1656 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
1657 Intrinsic::ppc_altivec_vslw
1659 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1662 // vsplti + srl self.
1663 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
1664 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1665 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1666 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
1667 Intrinsic::ppc_altivec_vsrw
1669 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1672 // vsplti + sra self.
1673 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
1674 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1675 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1676 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
1677 Intrinsic::ppc_altivec_vsraw
1679 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1682 // vsplti + rol self.
1683 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
1684 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
1685 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1686 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1687 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
1688 Intrinsic::ppc_altivec_vrlw
1690 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1693 // t = vsplti c, result = vsldoi t, t, 1
1694 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
1695 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1696 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
1698 // t = vsplti c, result = vsldoi t, t, 2
1699 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
1700 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1701 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
1703 // t = vsplti c, result = vsldoi t, t, 3
1704 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
1705 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1706 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
1710 // Three instruction sequences.
1712 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
1713 if (SextVal >= 0 && SextVal <= 31) {
1714 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, Op.getValueType(),DAG);
1715 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
1716 return DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
1718 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
1719 if (SextVal >= -31 && SextVal <= 0) {
1720 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, Op.getValueType(),DAG);
1721 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
1722 return DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
1729 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
1730 /// the specified operations to build the shuffle.
1731 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
1732 SDOperand RHS, SelectionDAG &DAG) {
1733 unsigned OpNum = (PFEntry >> 26) & 0x0F;
1734 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
1735 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
1738 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
1750 if (OpNum == OP_COPY) {
1751 if (LHSID == (1*9+2)*9+3) return LHS;
1752 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
1756 SDOperand OpLHS, OpRHS;
1757 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
1758 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
1760 unsigned ShufIdxs[16];
1762 default: assert(0 && "Unknown i32 permute!");
1764 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
1765 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
1766 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
1767 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
1770 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
1771 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
1772 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
1773 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
1776 for (unsigned i = 0; i != 16; ++i)
1777 ShufIdxs[i] = (i&3)+0;
1780 for (unsigned i = 0; i != 16; ++i)
1781 ShufIdxs[i] = (i&3)+4;
1784 for (unsigned i = 0; i != 16; ++i)
1785 ShufIdxs[i] = (i&3)+8;
1788 for (unsigned i = 0; i != 16; ++i)
1789 ShufIdxs[i] = (i&3)+12;
1792 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
1794 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
1796 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
1798 std::vector<SDOperand> Ops;
1799 for (unsigned i = 0; i != 16; ++i)
1800 Ops.push_back(DAG.getConstant(ShufIdxs[i], MVT::i32));
1802 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
1803 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
1806 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
1807 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
1808 /// return the code it can be lowered into. Worst case, it can always be
1809 /// lowered into a vperm.
1810 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
1811 SDOperand V1 = Op.getOperand(0);
1812 SDOperand V2 = Op.getOperand(1);
1813 SDOperand PermMask = Op.getOperand(2);
1815 // Cases that are handled by instructions that take permute immediates
1816 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
1817 // selected by the instruction selector.
1818 if (V2.getOpcode() == ISD::UNDEF) {
1819 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
1820 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
1821 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
1822 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
1823 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
1824 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
1825 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
1826 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
1827 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
1828 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
1829 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
1830 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
1835 // Altivec has a variety of "shuffle immediates" that take two vector inputs
1836 // and produce a fixed permutation. If any of these match, do not lower to
1838 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
1839 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
1840 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
1841 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
1842 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
1843 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
1844 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
1845 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
1846 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
1849 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
1850 // perfect shuffle table to emit an optimal matching sequence.
1851 unsigned PFIndexes[4];
1852 bool isFourElementShuffle = true;
1853 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
1854 unsigned EltNo = 8; // Start out undef.
1855 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
1856 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
1857 continue; // Undef, ignore it.
1859 unsigned ByteSource =
1860 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
1861 if ((ByteSource & 3) != j) {
1862 isFourElementShuffle = false;
1867 EltNo = ByteSource/4;
1868 } else if (EltNo != ByteSource/4) {
1869 isFourElementShuffle = false;
1873 PFIndexes[i] = EltNo;
1876 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
1877 // perfect shuffle vector to determine if it is cost effective to do this as
1878 // discrete instructions, or whether we should use a vperm.
1879 if (isFourElementShuffle) {
1880 // Compute the index in the perfect shuffle table.
1881 unsigned PFTableIndex =
1882 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
1884 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
1885 unsigned Cost = (PFEntry >> 30);
1887 // Determining when to avoid vperm is tricky. Many things affect the cost
1888 // of vperm, particularly how many times the perm mask needs to be computed.
1889 // For example, if the perm mask can be hoisted out of a loop or is already
1890 // used (perhaps because there are multiple permutes with the same shuffle
1891 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
1892 // the loop requires an extra register.
1894 // As a compromise, we only emit discrete instructions if the shuffle can be
1895 // generated in 3 or fewer operations. When we have loop information
1896 // available, if this block is within a loop, we should avoid using vperm
1897 // for 3-operation perms and use a constant pool load instead.
1899 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
1902 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
1903 // vector that will get spilled to the constant pool.
1904 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
1906 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
1907 // that it is in input element units, not in bytes. Convert now.
1908 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
1909 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
1911 std::vector<SDOperand> ResultMask;
1912 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
1914 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
1917 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
1919 for (unsigned j = 0; j != BytesPerElement; ++j)
1920 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
1924 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask);
1925 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
1928 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
1929 /// altivec comparison. If it is, return true and fill in Opc/isDot with
1930 /// information about the intrinsic.
1931 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
1933 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
1936 switch (IntrinsicID) {
1937 default: return false;
1938 // Comparison predicates.
1939 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
1940 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
1941 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
1942 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
1943 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
1944 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
1945 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
1946 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
1947 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
1948 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
1949 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
1950 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
1951 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
1953 // Normal Comparisons.
1954 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
1955 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
1956 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
1957 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
1958 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
1959 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
1960 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
1961 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
1962 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
1963 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
1964 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
1965 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
1966 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
1971 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
1972 /// lower, do it, otherwise return null.
1973 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
1974 // If this is a lowered altivec predicate compare, CompareOpc is set to the
1975 // opcode number of the comparison.
1978 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
1979 return SDOperand(); // Don't custom lower most intrinsics.
1981 // If this is a non-dot comparison, make the VCMP node and we are done.
1983 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
1984 Op.getOperand(1), Op.getOperand(2),
1985 DAG.getConstant(CompareOpc, MVT::i32));
1986 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
1989 // Create the PPCISD altivec 'dot' comparison node.
1990 std::vector<SDOperand> Ops;
1991 std::vector<MVT::ValueType> VTs;
1992 Ops.push_back(Op.getOperand(2)); // LHS
1993 Ops.push_back(Op.getOperand(3)); // RHS
1994 Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32));
1995 VTs.push_back(Op.getOperand(2).getValueType());
1996 VTs.push_back(MVT::Flag);
1997 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops);
1999 // Now that we have the comparison, emit a copy from the CR to a GPR.
2000 // This is flagged to the above dot comparison.
2001 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
2002 DAG.getRegister(PPC::CR6, MVT::i32),
2003 CompNode.getValue(1));
2005 // Unpack the result based on how the target uses it.
2006 unsigned BitNo; // Bit # of CR6.
2007 bool InvertBit; // Invert result?
2008 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
2009 default: // Can't happen, don't crash on invalid number though.
2010 case 0: // Return the value of the EQ bit of CR6.
2011 BitNo = 0; InvertBit = false;
2013 case 1: // Return the inverted value of the EQ bit of CR6.
2014 BitNo = 0; InvertBit = true;
2016 case 2: // Return the value of the LT bit of CR6.
2017 BitNo = 2; InvertBit = false;
2019 case 3: // Return the inverted value of the LT bit of CR6.
2020 BitNo = 2; InvertBit = true;
2024 // Shift the bit into the low position.
2025 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
2026 DAG.getConstant(8-(3-BitNo), MVT::i32));
2028 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
2029 DAG.getConstant(1, MVT::i32));
2031 // If we are supposed to, toggle the bit.
2033 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
2034 DAG.getConstant(1, MVT::i32));
2038 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2039 // Create a stack slot that is 16-byte aligned.
2040 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2041 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
2042 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
2044 // Store the input value into Value#0 of the stack slot.
2045 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
2046 Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
2048 return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL));
2051 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
2052 if (Op.getValueType() == MVT::v4i32) {
2053 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2055 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
2056 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
2058 SDOperand RHSSwap = // = vrlw RHS, 16
2059 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
2061 // Shrinkify inputs to v8i16.
2062 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
2063 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
2064 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
2066 // Low parts multiplied together, generating 32-bit results (we ignore the
2068 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
2069 LHS, RHS, DAG, MVT::v4i32);
2071 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
2072 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
2073 // Shift the high parts up 16 bits.
2074 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
2075 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
2076 } else if (Op.getValueType() == MVT::v8i16) {
2077 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2079 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
2081 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
2082 LHS, RHS, Zero, DAG);
2083 } else if (Op.getValueType() == MVT::v16i8) {
2084 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2086 // Multiply the even 8-bit parts, producing 16-bit sums.
2087 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
2088 LHS, RHS, DAG, MVT::v8i16);
2089 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
2091 // Multiply the odd 8-bit parts, producing 16-bit sums.
2092 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
2093 LHS, RHS, DAG, MVT::v8i16);
2094 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
2096 // Merge the results together.
2097 std::vector<SDOperand> Ops;
2098 for (unsigned i = 0; i != 8; ++i) {
2099 Ops.push_back(DAG.getConstant(2*i+1, MVT::i8));
2100 Ops.push_back(DAG.getConstant(2*i+1+16, MVT::i8));
2103 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
2104 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
2106 assert(0 && "Unknown mul to lower!");
2111 /// LowerOperation - Provide custom lowering hooks for some operations.
2113 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2114 switch (Op.getOpcode()) {
2115 default: assert(0 && "Wasn't expecting to be able to lower this!");
2116 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2117 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2118 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2119 case ISD::SETCC: return LowerSETCC(Op, DAG);
2120 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2121 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
2123 case ISD::CALL: return LowerCALL(Op, DAG);
2124 case ISD::RET: return LowerRET(Op, DAG);
2126 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2127 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
2128 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
2130 // Lower 64-bit shifts.
2131 case ISD::SHL: return LowerSHL(Op, DAG);
2132 case ISD::SRL: return LowerSRL(Op, DAG);
2133 case ISD::SRA: return LowerSRA(Op, DAG);
2135 // Vector-related lowering.
2136 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2137 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2138 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2139 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2140 case ISD::MUL: return LowerMUL(Op, DAG);
2145 //===----------------------------------------------------------------------===//
2146 // Other Lowering Code
2147 //===----------------------------------------------------------------------===//
2150 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2151 MachineBasicBlock *BB) {
2152 assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
2153 MI->getOpcode() == PPC::SELECT_CC_F4 ||
2154 MI->getOpcode() == PPC::SELECT_CC_F8 ||
2155 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
2156 "Unexpected instr type to insert");
2158 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2159 // control-flow pattern. The incoming instruction knows the destination vreg
2160 // to set, the condition code register to branch on, the true/false values to
2161 // select between, and a branch opcode to use.
2162 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2163 ilist<MachineBasicBlock>::iterator It = BB;
2169 // cmpTY ccX, r1, r2
2171 // fallthrough --> copy0MBB
2172 MachineBasicBlock *thisMBB = BB;
2173 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2174 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2175 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
2176 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
2177 MachineFunction *F = BB->getParent();
2178 F->getBasicBlockList().insert(It, copy0MBB);
2179 F->getBasicBlockList().insert(It, sinkMBB);
2180 // Update machine-CFG edges by first adding all successors of the current
2181 // block to the new block which will contain the Phi node for the select.
2182 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2183 e = BB->succ_end(); i != e; ++i)
2184 sinkMBB->addSuccessor(*i);
2185 // Next, remove all successors of the current block, and add the true
2186 // and fallthrough blocks as its successors.
2187 while(!BB->succ_empty())
2188 BB->removeSuccessor(BB->succ_begin());
2189 BB->addSuccessor(copy0MBB);
2190 BB->addSuccessor(sinkMBB);
2193 // %FalseValue = ...
2194 // # fallthrough to sinkMBB
2197 // Update machine-CFG edges
2198 BB->addSuccessor(sinkMBB);
2201 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2204 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
2205 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
2206 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2208 delete MI; // The pseudo instruction is gone now.
2212 //===----------------------------------------------------------------------===//
2213 // Target Optimization Hooks
2214 //===----------------------------------------------------------------------===//
2216 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
2217 DAGCombinerInfo &DCI) const {
2218 TargetMachine &TM = getTargetMachine();
2219 SelectionDAG &DAG = DCI.DAG;
2220 switch (N->getOpcode()) {
2222 case ISD::SINT_TO_FP:
2223 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
2224 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
2225 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
2226 // We allow the src/dst to be either f32/f64, but the intermediate
2227 // type must be i64.
2228 if (N->getOperand(0).getValueType() == MVT::i64) {
2229 SDOperand Val = N->getOperand(0).getOperand(0);
2230 if (Val.getValueType() == MVT::f32) {
2231 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2232 DCI.AddToWorklist(Val.Val);
2235 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
2236 DCI.AddToWorklist(Val.Val);
2237 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
2238 DCI.AddToWorklist(Val.Val);
2239 if (N->getValueType(0) == MVT::f32) {
2240 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
2241 DCI.AddToWorklist(Val.Val);
2244 } else if (N->getOperand(0).getValueType() == MVT::i32) {
2245 // If the intermediate type is i32, we can avoid the load/store here
2252 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
2253 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
2254 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
2255 N->getOperand(1).getValueType() == MVT::i32) {
2256 SDOperand Val = N->getOperand(1).getOperand(0);
2257 if (Val.getValueType() == MVT::f32) {
2258 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2259 DCI.AddToWorklist(Val.Val);
2261 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
2262 DCI.AddToWorklist(Val.Val);
2264 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
2265 N->getOperand(2), N->getOperand(3));
2266 DCI.AddToWorklist(Val.Val);
2270 case PPCISD::VCMP: {
2271 // If a VCMPo node already exists with exactly the same operands as this
2272 // node, use its result instead of this node (VCMPo computes both a CR6 and
2273 // a normal output).
2275 if (!N->getOperand(0).hasOneUse() &&
2276 !N->getOperand(1).hasOneUse() &&
2277 !N->getOperand(2).hasOneUse()) {
2279 // Scan all of the users of the LHS, looking for VCMPo's that match.
2280 SDNode *VCMPoNode = 0;
2282 SDNode *LHSN = N->getOperand(0).Val;
2283 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
2285 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
2286 (*UI)->getOperand(1) == N->getOperand(1) &&
2287 (*UI)->getOperand(2) == N->getOperand(2) &&
2288 (*UI)->getOperand(0) == N->getOperand(0)) {
2293 // If there is no VCMPo node, or if the flag value has a single use, don't
2295 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
2298 // Look at the (necessarily single) use of the flag value. If it has a
2299 // chain, this transformation is more complex. Note that multiple things
2300 // could use the value result, which we should ignore.
2301 SDNode *FlagUser = 0;
2302 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
2303 FlagUser == 0; ++UI) {
2304 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
2306 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2307 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
2314 // If the user is a MFCR instruction, we know this is safe. Otherwise we
2315 // give up for right now.
2316 if (FlagUser->getOpcode() == PPCISD::MFCR)
2317 return SDOperand(VCMPoNode, 0);
2322 // If this is a branch on an altivec predicate comparison, lower this so
2323 // that we don't have to do a MFCR: instead, branch directly on CR6. This
2324 // lowering is done pre-legalize, because the legalizer lowers the predicate
2325 // compare down to code that is difficult to reassemble.
2326 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
2327 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
2331 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2332 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
2333 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
2334 assert(isDot && "Can't compare against a vector result!");
2336 // If this is a comparison against something other than 0/1, then we know
2337 // that the condition is never/always true.
2338 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
2339 if (Val != 0 && Val != 1) {
2340 if (CC == ISD::SETEQ) // Cond never true, remove branch.
2341 return N->getOperand(0);
2342 // Always !=, turn it into an unconditional branch.
2343 return DAG.getNode(ISD::BR, MVT::Other,
2344 N->getOperand(0), N->getOperand(4));
2347 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
2349 // Create the PPCISD altivec 'dot' comparison node.
2350 std::vector<SDOperand> Ops;
2351 std::vector<MVT::ValueType> VTs;
2352 Ops.push_back(LHS.getOperand(2)); // LHS of compare
2353 Ops.push_back(LHS.getOperand(3)); // RHS of compare
2354 Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32));
2355 VTs.push_back(LHS.getOperand(2).getValueType());
2356 VTs.push_back(MVT::Flag);
2357 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops);
2359 // Unpack the result based on how the target uses it.
2361 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
2362 default: // Can't happen, don't crash on invalid number though.
2363 case 0: // Branch on the value of the EQ bit of CR6.
2364 CompOpc = BranchOnWhenPredTrue ? PPC::BEQ : PPC::BNE;
2366 case 1: // Branch on the inverted value of the EQ bit of CR6.
2367 CompOpc = BranchOnWhenPredTrue ? PPC::BNE : PPC::BEQ;
2369 case 2: // Branch on the value of the LT bit of CR6.
2370 CompOpc = BranchOnWhenPredTrue ? PPC::BLT : PPC::BGE;
2372 case 3: // Branch on the inverted value of the LT bit of CR6.
2373 CompOpc = BranchOnWhenPredTrue ? PPC::BGE : PPC::BLT;
2377 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
2378 DAG.getRegister(PPC::CR6, MVT::i32),
2379 DAG.getConstant(CompOpc, MVT::i32),
2380 N->getOperand(4), CompNode.getValue(1));
2389 //===----------------------------------------------------------------------===//
2390 // Inline Assembly Support
2391 //===----------------------------------------------------------------------===//
2393 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
2395 uint64_t &KnownZero,
2397 unsigned Depth) const {
2400 switch (Op.getOpcode()) {
2402 case ISD::INTRINSIC_WO_CHAIN: {
2403 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
2405 case Intrinsic::ppc_altivec_vcmpbfp_p:
2406 case Intrinsic::ppc_altivec_vcmpeqfp_p:
2407 case Intrinsic::ppc_altivec_vcmpequb_p:
2408 case Intrinsic::ppc_altivec_vcmpequh_p:
2409 case Intrinsic::ppc_altivec_vcmpequw_p:
2410 case Intrinsic::ppc_altivec_vcmpgefp_p:
2411 case Intrinsic::ppc_altivec_vcmpgtfp_p:
2412 case Intrinsic::ppc_altivec_vcmpgtsb_p:
2413 case Intrinsic::ppc_altivec_vcmpgtsh_p:
2414 case Intrinsic::ppc_altivec_vcmpgtsw_p:
2415 case Intrinsic::ppc_altivec_vcmpgtub_p:
2416 case Intrinsic::ppc_altivec_vcmpgtuh_p:
2417 case Intrinsic::ppc_altivec_vcmpgtuw_p:
2418 KnownZero = ~1U; // All bits but the low one are known to be zero.
2426 /// getConstraintType - Given a constraint letter, return the type of
2427 /// constraint it is for this target.
2428 PPCTargetLowering::ConstraintType
2429 PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
2430 switch (ConstraintLetter) {
2437 return C_RegisterClass;
2439 return TargetLowering::getConstraintType(ConstraintLetter);
2443 std::vector<unsigned> PPCTargetLowering::
2444 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2445 MVT::ValueType VT) const {
2446 if (Constraint.size() == 1) {
2447 switch (Constraint[0]) { // GCC RS6000 Constraint Letters
2448 default: break; // Unknown constriant letter
2450 return make_vector<unsigned>(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 ,
2451 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
2452 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
2453 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
2454 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
2455 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
2456 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
2457 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
2460 return make_vector<unsigned>(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 ,
2461 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
2462 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
2463 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
2464 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
2465 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
2466 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
2467 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
2470 return make_vector<unsigned>(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 ,
2471 PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 ,
2472 PPC::F8 , PPC::F9 , PPC::F10, PPC::F11,
2473 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
2474 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
2475 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
2476 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
2477 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
2480 return make_vector<unsigned>(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 ,
2481 PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
2482 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11,
2483 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
2484 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
2485 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
2486 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
2487 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
2490 return make_vector<unsigned>(PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
2491 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7,
2496 return std::vector<unsigned>();
2499 // isOperandValidForConstraint
2500 bool PPCTargetLowering::
2501 isOperandValidForConstraint(SDOperand Op, char Letter) {
2512 if (!isa<ConstantSDNode>(Op)) return false; // Must be an immediate.
2513 unsigned Value = cast<ConstantSDNode>(Op)->getValue();
2515 default: assert(0 && "Unknown constraint letter!");
2516 case 'I': // "I" is a signed 16-bit constant.
2517 return (short)Value == (int)Value;
2518 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
2519 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
2520 return (short)Value == 0;
2521 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
2522 return (Value >> 16) == 0;
2523 case 'M': // "M" is a constant that is greater than 31.
2525 case 'N': // "N" is a positive constant that is an exact power of two.
2526 return (int)Value > 0 && isPowerOf2_32(Value);
2527 case 'O': // "O" is the constant zero.
2529 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
2530 return (short)-Value == (int)-Value;
2536 // Handle standard constraint letters.
2537 return TargetLowering::isOperandValidForConstraint(Op, Letter);
2540 /// isLegalAddressImmediate - Return true if the integer value can be used
2541 /// as the offset of the target addressing mode.
2542 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const {
2543 // PPC allows a sign-extended 16-bit immediate field.
2544 return (V > -(1 << 16) && V < (1 << 16)-1);