1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCTargetMachine.h"
16 #include "PPCPerfectShuffle.h"
17 #include "llvm/ADT/VectorExtras.h"
18 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Function.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Target/TargetOptions.h"
31 PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
32 : TargetLowering(TM) {
34 // Fold away setcc operations if possible.
35 setSetCCIsExpensive();
38 // Use _setjmp/_longjmp instead of setjmp/longjmp.
39 setUseUnderscoreSetJmpLongJmp(true);
41 // Set up the register classes.
42 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
43 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
44 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
46 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
47 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
48 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
50 // PowerPC does not have truncstore for i1.
51 setStoreXAction(MVT::i1, Promote);
53 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
54 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
56 // PowerPC has no intrinsics for these particular operations
57 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
58 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
59 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
61 // PowerPC has no SREM/UREM instructions
62 setOperationAction(ISD::SREM, MVT::i32, Expand);
63 setOperationAction(ISD::UREM, MVT::i32, Expand);
64 setOperationAction(ISD::SREM, MVT::i64, Expand);
65 setOperationAction(ISD::UREM, MVT::i64, Expand);
67 // We don't support sin/cos/sqrt/fmod
68 setOperationAction(ISD::FSIN , MVT::f64, Expand);
69 setOperationAction(ISD::FCOS , MVT::f64, Expand);
70 setOperationAction(ISD::FREM , MVT::f64, Expand);
71 setOperationAction(ISD::FSIN , MVT::f32, Expand);
72 setOperationAction(ISD::FCOS , MVT::f32, Expand);
73 setOperationAction(ISD::FREM , MVT::f32, Expand);
75 // If we're enabling GP optimizations, use hardware square root
76 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
77 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
78 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
81 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
82 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
84 // PowerPC does not have BSWAP, CTPOP or CTTZ
85 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
86 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
87 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
88 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
89 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
90 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
92 // PowerPC does not have ROTR
93 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
95 // PowerPC does not have Select
96 setOperationAction(ISD::SELECT, MVT::i32, Expand);
97 setOperationAction(ISD::SELECT, MVT::i64, Expand);
98 setOperationAction(ISD::SELECT, MVT::f32, Expand);
99 setOperationAction(ISD::SELECT, MVT::f64, Expand);
101 // PowerPC wants to turn select_cc of FP into fsel when possible.
102 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
103 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
105 // PowerPC wants to optimize integer setcc a bit
106 setOperationAction(ISD::SETCC, MVT::i32, Custom);
108 // PowerPC does not have BRCOND which requires SetCC
109 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
111 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
112 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
114 // PowerPC does not have [U|S]INT_TO_FP
115 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
116 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
118 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
119 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
120 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
121 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
123 // We cannot sextinreg(i1). Expand to shifts.
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
127 // Support label based line numbers.
128 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
129 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
130 // FIXME - use subtarget debug flags
131 if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
132 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
134 // We want to legalize GlobalAddress and ConstantPool nodes into the
135 // appropriate instructions to materialize the address.
136 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
137 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
138 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
139 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
140 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
141 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
143 // RET must be custom lowered, to meet ABI requirements
144 setOperationAction(ISD::RET , MVT::Other, Custom);
146 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
147 setOperationAction(ISD::VASTART , MVT::Other, Custom);
149 // Use the default implementation.
150 setOperationAction(ISD::VAARG , MVT::Other, Expand);
151 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
152 setOperationAction(ISD::VAEND , MVT::Other, Expand);
153 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
154 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
155 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
156 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Expand);
158 // We want to custom lower some of our intrinsics.
159 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
161 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
162 // They also have instructions for converting between i64 and fp.
163 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
164 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
166 // FIXME: disable this lowered code. This generates 64-bit register values,
167 // and we don't model the fact that the top part is clobbered by calls. We
168 // need to flag these together so that the value isn't live across a call.
169 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
171 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
172 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
174 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
175 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
178 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
179 // 64 bit PowerPC implementations can support i64 types directly
180 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
181 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
182 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
184 // 32 bit PowerPC wants to expand i64 shifts itself.
185 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
186 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
187 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
190 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
191 // First set operation action for all vector types to expand. Then we
192 // will selectively turn on ones that can be effectively codegen'd.
193 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
194 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
195 // add/sub are legal for all supported vector VT's.
196 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
197 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
199 // We promote all shuffles to v16i8.
200 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
201 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
203 // We promote all non-typed operations to v4i32.
204 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
205 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
206 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
207 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
208 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
209 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
210 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
211 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
212 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
213 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
214 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
215 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
217 // No other operations are legal.
218 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
219 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
220 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
221 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
222 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
223 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
224 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
225 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
226 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
228 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
231 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
232 // with merges, splats, etc.
233 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
235 setOperationAction(ISD::AND , MVT::v4i32, Legal);
236 setOperationAction(ISD::OR , MVT::v4i32, Legal);
237 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
238 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
239 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
240 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
242 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
243 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
244 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
245 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
247 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
248 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
249 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
250 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
252 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
253 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
255 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
256 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
257 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
258 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
261 setSetCCResultType(MVT::i32);
262 setShiftAmountType(MVT::i32);
263 setSetCCResultContents(ZeroOrOneSetCCResult);
264 setStackPointerRegisterToSaveRestore(PPC::R1);
266 // We have target-specific dag combine patterns for the following nodes:
267 setTargetDAGCombine(ISD::SINT_TO_FP);
268 setTargetDAGCombine(ISD::STORE);
269 setTargetDAGCombine(ISD::BR_CC);
270 setTargetDAGCombine(ISD::BSWAP);
272 computeRegisterProperties();
275 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
278 case PPCISD::FSEL: return "PPCISD::FSEL";
279 case PPCISD::FCFID: return "PPCISD::FCFID";
280 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
281 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
282 case PPCISD::STFIWX: return "PPCISD::STFIWX";
283 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
284 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
285 case PPCISD::VPERM: return "PPCISD::VPERM";
286 case PPCISD::Hi: return "PPCISD::Hi";
287 case PPCISD::Lo: return "PPCISD::Lo";
288 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
289 case PPCISD::SRL: return "PPCISD::SRL";
290 case PPCISD::SRA: return "PPCISD::SRA";
291 case PPCISD::SHL: return "PPCISD::SHL";
292 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
293 case PPCISD::STD_32: return "PPCISD::STD_32";
294 case PPCISD::CALL: return "PPCISD::CALL";
295 case PPCISD::MTCTR: return "PPCISD::MTCTR";
296 case PPCISD::BCTRL: return "PPCISD::BCTRL";
297 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
298 case PPCISD::MFCR: return "PPCISD::MFCR";
299 case PPCISD::VCMP: return "PPCISD::VCMP";
300 case PPCISD::VCMPo: return "PPCISD::VCMPo";
301 case PPCISD::LBRX: return "PPCISD::LBRX";
302 case PPCISD::STBRX: return "PPCISD::STBRX";
303 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
307 //===----------------------------------------------------------------------===//
308 // Node matching predicates, for use by the tblgen matching code.
309 //===----------------------------------------------------------------------===//
311 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
312 static bool isFloatingPointZero(SDOperand Op) {
313 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
314 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
315 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
316 // Maybe this has already been legalized into the constant pool?
317 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
318 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
319 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
324 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
325 /// true if Op is undef or if it matches the specified value.
326 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
327 return Op.getOpcode() == ISD::UNDEF ||
328 cast<ConstantSDNode>(Op)->getValue() == Val;
331 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
332 /// VPKUHUM instruction.
333 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
335 for (unsigned i = 0; i != 16; ++i)
336 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
339 for (unsigned i = 0; i != 8; ++i)
340 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
341 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
347 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
348 /// VPKUWUM instruction.
349 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
351 for (unsigned i = 0; i != 16; i += 2)
352 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
353 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
356 for (unsigned i = 0; i != 8; i += 2)
357 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
358 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
359 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
360 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
366 /// isVMerge - Common function, used to match vmrg* shuffles.
368 static bool isVMerge(SDNode *N, unsigned UnitSize,
369 unsigned LHSStart, unsigned RHSStart) {
370 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
371 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
372 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
373 "Unsupported merge size!");
375 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
376 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
377 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
378 LHSStart+j+i*UnitSize) ||
379 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
380 RHSStart+j+i*UnitSize))
386 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
387 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
388 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
390 return isVMerge(N, UnitSize, 8, 24);
391 return isVMerge(N, UnitSize, 8, 8);
394 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
395 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
396 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
398 return isVMerge(N, UnitSize, 0, 16);
399 return isVMerge(N, UnitSize, 0, 0);
403 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
404 /// amount, otherwise return -1.
405 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
406 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
407 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
408 // Find the first non-undef value in the shuffle mask.
410 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
413 if (i == 16) return -1; // all undef.
415 // Otherwise, check to see if the rest of the elements are consequtively
416 // numbered from this value.
417 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
418 if (ShiftAmt < i) return -1;
422 // Check the rest of the elements to see if they are consequtive.
423 for (++i; i != 16; ++i)
424 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
427 // Check the rest of the elements to see if they are consequtive.
428 for (++i; i != 16; ++i)
429 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
436 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
437 /// specifies a splat of a single element that is suitable for input to
438 /// VSPLTB/VSPLTH/VSPLTW.
439 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
440 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
441 N->getNumOperands() == 16 &&
442 (EltSize == 1 || EltSize == 2 || EltSize == 4));
444 // This is a splat operation if each element of the permute is the same, and
445 // if the value doesn't reference the second vector.
446 unsigned ElementBase = 0;
447 SDOperand Elt = N->getOperand(0);
448 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
449 ElementBase = EltV->getValue();
451 return false; // FIXME: Handle UNDEF elements too!
453 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
456 // Check that they are consequtive.
457 for (unsigned i = 1; i != EltSize; ++i) {
458 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
459 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
463 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
464 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
465 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
466 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
467 "Invalid VECTOR_SHUFFLE mask!");
468 for (unsigned j = 0; j != EltSize; ++j)
469 if (N->getOperand(i+j) != N->getOperand(j))
476 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
477 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
478 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
479 assert(isSplatShuffleMask(N, EltSize));
480 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
483 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
484 /// by using a vspltis[bhw] instruction of the specified element size, return
485 /// the constant being splatted. The ByteSize field indicates the number of
486 /// bytes of each element [124] -> [bhw].
487 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
488 SDOperand OpVal(0, 0);
490 // If ByteSize of the splat is bigger than the element size of the
491 // build_vector, then we have a case where we are checking for a splat where
492 // multiple elements of the buildvector are folded together into a single
493 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
494 unsigned EltSize = 16/N->getNumOperands();
495 if (EltSize < ByteSize) {
496 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
497 SDOperand UniquedVals[4];
498 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
500 // See if all of the elements in the buildvector agree across.
501 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
502 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
503 // If the element isn't a constant, bail fully out.
504 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
507 if (UniquedVals[i&(Multiple-1)].Val == 0)
508 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
509 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
510 return SDOperand(); // no match.
513 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
514 // either constant or undef values that are identical for each chunk. See
515 // if these chunks can form into a larger vspltis*.
517 // Check to see if all of the leading entries are either 0 or -1. If
518 // neither, then this won't fit into the immediate field.
519 bool LeadingZero = true;
520 bool LeadingOnes = true;
521 for (unsigned i = 0; i != Multiple-1; ++i) {
522 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
524 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
525 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
527 // Finally, check the least significant entry.
529 if (UniquedVals[Multiple-1].Val == 0)
530 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
531 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
533 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
536 if (UniquedVals[Multiple-1].Val == 0)
537 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
538 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
539 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
540 return DAG.getTargetConstant(Val, MVT::i32);
546 // Check to see if this buildvec has a single non-undef value in its elements.
547 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
548 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
550 OpVal = N->getOperand(i);
551 else if (OpVal != N->getOperand(i))
555 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
557 unsigned ValSizeInBytes = 0;
559 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
560 Value = CN->getValue();
561 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
562 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
563 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
564 Value = FloatToBits(CN->getValue());
568 // If the splat value is larger than the element value, then we can never do
569 // this splat. The only case that we could fit the replicated bits into our
570 // immediate field for would be zero, and we prefer to use vxor for it.
571 if (ValSizeInBytes < ByteSize) return SDOperand();
573 // If the element value is larger than the splat value, cut it in half and
574 // check to see if the two halves are equal. Continue doing this until we
575 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
576 while (ValSizeInBytes > ByteSize) {
577 ValSizeInBytes >>= 1;
579 // If the top half equals the bottom half, we're still ok.
580 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
581 (Value & ((1 << (8*ValSizeInBytes))-1)))
585 // Properly sign extend the value.
586 int ShAmt = (4-ByteSize)*8;
587 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
589 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
590 if (MaskVal == 0) return SDOperand();
592 // Finally, if this value fits in a 5 bit sext field, return it
593 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
594 return DAG.getTargetConstant(MaskVal, MVT::i32);
598 //===----------------------------------------------------------------------===//
599 // LowerOperation implementation
600 //===----------------------------------------------------------------------===//
602 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
603 MVT::ValueType PtrVT = Op.getValueType();
604 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
605 Constant *C = CP->getConstVal();
606 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
607 SDOperand Zero = DAG.getConstant(0, PtrVT);
609 const TargetMachine &TM = DAG.getTarget();
611 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
612 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
614 // If this is a non-darwin platform, we don't support non-static relo models
616 if (TM.getRelocationModel() == Reloc::Static ||
617 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
618 // Generate non-pic code that has direct accesses to the constant pool.
619 // The address of the global is just (hi(&g)+lo(&g)).
620 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
623 if (TM.getRelocationModel() == Reloc::PIC_) {
624 // With PIC, the first instruction is actually "GR+hi(&G)".
625 Hi = DAG.getNode(ISD::ADD, PtrVT,
626 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
629 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
633 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
634 MVT::ValueType PtrVT = Op.getValueType();
635 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
636 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
637 SDOperand Zero = DAG.getConstant(0, PtrVT);
639 const TargetMachine &TM = DAG.getTarget();
641 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
642 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
644 // If this is a non-darwin platform, we don't support non-static relo models
646 if (TM.getRelocationModel() == Reloc::Static ||
647 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
648 // Generate non-pic code that has direct accesses to the constant pool.
649 // The address of the global is just (hi(&g)+lo(&g)).
650 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
653 if (TM.getRelocationModel() == Reloc::PIC_) {
654 // With PIC, the first instruction is actually "GR+hi(&G)".
655 Hi = DAG.getNode(ISD::ADD, PtrVT,
656 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
659 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
663 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
664 MVT::ValueType PtrVT = Op.getValueType();
665 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
666 GlobalValue *GV = GSDN->getGlobal();
667 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
668 SDOperand Zero = DAG.getConstant(0, PtrVT);
670 const TargetMachine &TM = DAG.getTarget();
672 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
673 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
675 // If this is a non-darwin platform, we don't support non-static relo models
677 if (TM.getRelocationModel() == Reloc::Static ||
678 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
679 // Generate non-pic code that has direct accesses to globals.
680 // The address of the global is just (hi(&g)+lo(&g)).
681 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
684 if (TM.getRelocationModel() == Reloc::PIC_) {
685 // With PIC, the first instruction is actually "GR+hi(&G)".
686 Hi = DAG.getNode(ISD::ADD, PtrVT,
687 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
690 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
692 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() &&
693 (!GV->isExternal() || GV->hasNotBeenReadFromBytecode()))
696 // If the global is weak or external, we have to go through the lazy
698 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
701 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
702 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
704 // If we're comparing for equality to zero, expose the fact that this is
705 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
706 // fold the new nodes.
707 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
708 if (C->isNullValue() && CC == ISD::SETEQ) {
709 MVT::ValueType VT = Op.getOperand(0).getValueType();
710 SDOperand Zext = Op.getOperand(0);
713 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
715 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
716 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
717 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
718 DAG.getConstant(Log2b, MVT::i32));
719 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
721 // Leave comparisons against 0 and -1 alone for now, since they're usually
722 // optimized. FIXME: revisit this when we can custom lower all setcc
724 if (C->isAllOnesValue() || C->isNullValue())
728 // If we have an integer seteq/setne, turn it into a compare against zero
729 // by subtracting the rhs from the lhs, which is faster than setting a
730 // condition register, reading it back out, and masking the correct bit.
731 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
732 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
733 MVT::ValueType VT = Op.getValueType();
734 SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0),
736 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
741 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
742 unsigned VarArgsFrameIndex) {
743 // vastart just stores the address of the VarArgsFrameIndex slot into the
744 // memory location argument.
745 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
746 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
747 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
748 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
752 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
753 int &VarArgsFrameIndex) {
754 // TODO: add description of PPC stack frame format, or at least some docs.
756 MachineFunction &MF = DAG.getMachineFunction();
757 MachineFrameInfo *MFI = MF.getFrameInfo();
758 SSARegMap *RegMap = MF.getSSARegMap();
759 SmallVector<SDOperand, 8> ArgValues;
760 SDOperand Root = Op.getOperand(0);
762 unsigned ArgOffset = 24;
763 const unsigned Num_GPR_Regs = 8;
764 const unsigned Num_FPR_Regs = 13;
765 const unsigned Num_VR_Regs = 12;
766 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
768 static const unsigned GPR_32[] = { // 32-bit registers.
769 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
770 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
772 static const unsigned GPR_64[] = { // 64-bit registers.
773 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
774 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
776 static const unsigned FPR[] = {
777 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
778 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
780 static const unsigned VR[] = {
781 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
782 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
785 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
786 bool isPPC64 = PtrVT == MVT::i64;
787 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
789 // Add DAG nodes to load the arguments or copy them out of registers. On
790 // entry to a function on PPC, the arguments start at offset 24, although the
791 // first ones are often in registers.
792 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
794 bool needsLoad = false;
795 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
796 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
798 unsigned CurArgOffset = ArgOffset;
800 default: assert(0 && "Unhandled argument type!");
802 // All int arguments reserve stack space.
803 ArgOffset += isPPC64 ? 8 : 4;
805 if (GPR_idx != Num_GPR_Regs) {
806 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
807 MF.addLiveIn(GPR[GPR_idx], VReg);
808 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
814 case MVT::i64: // PPC64
815 // All int arguments reserve stack space.
818 if (GPR_idx != Num_GPR_Regs) {
819 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
820 MF.addLiveIn(GPR[GPR_idx], VReg);
821 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
829 // All FP arguments reserve stack space.
830 ArgOffset += ObjSize;
832 // Every 4 bytes of argument space consumes one of the GPRs available for
834 if (GPR_idx != Num_GPR_Regs) {
836 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs)
839 if (FPR_idx != Num_FPR_Regs) {
841 if (ObjectVT == MVT::f32)
842 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
844 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
845 MF.addLiveIn(FPR[FPR_idx], VReg);
846 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
856 // Note that vector arguments in registers don't reserve stack space.
857 if (VR_idx != Num_VR_Regs) {
858 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass);
859 MF.addLiveIn(VR[VR_idx], VReg);
860 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
863 // This should be simple, but requires getting 16-byte aligned stack
865 assert(0 && "Loading VR argument not implemented yet!");
871 // We need to load the argument to a virtual register if we determined above
872 // that we ran out of physical registers of the appropriate type
874 // If the argument is actually used, emit a load from the right stack
876 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
877 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
878 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
879 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
881 // Don't emit a dead load.
882 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
886 ArgValues.push_back(ArgVal);
889 // If the function takes variable number of arguments, make a frame index for
890 // the start of the first vararg value... for expansion of llvm.va_start.
891 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
893 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
895 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
896 // If this function is vararg, store any remaining integer argument regs
897 // to their spots on the stack so that they may be loaded by deferencing the
898 // result of va_next.
899 SmallVector<SDOperand, 8> MemOps;
900 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
901 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
902 MF.addLiveIn(GPR[GPR_idx], VReg);
903 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
904 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
905 MemOps.push_back(Store);
906 // Increment the address by four for the next argument to store
907 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
908 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
911 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
914 ArgValues.push_back(Root);
916 // Return the new list of results.
917 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
918 Op.Val->value_end());
919 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
922 /// isCallCompatibleAddress - Return the immediate to use if the specified
923 /// 32-bit value is representable in the immediate field of a BxA instruction.
924 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
925 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
928 int Addr = C->getValue();
929 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
930 (Addr << 6 >> 6) != Addr)
931 return 0; // Top 6 bits have to be sext of immediate.
933 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
937 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
938 SDOperand Chain = Op.getOperand(0);
939 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
940 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
941 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
942 SDOperand Callee = Op.getOperand(4);
943 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
945 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
946 bool isPPC64 = PtrVT == MVT::i64;
947 unsigned PtrByteSize = isPPC64 ? 8 : 4;
950 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
951 // SelectExpr to use to put the arguments in the appropriate registers.
952 std::vector<SDOperand> args_to_use;
954 // Count how many bytes are to be pushed on the stack, including the linkage
955 // area, and parameter passing area. We start with 24/48 bytes, which is
956 // prereserved space for [SP][CR][LR][3 x unused].
957 unsigned NumBytes = 6*PtrByteSize;
959 // Add up all the space actually used.
960 for (unsigned i = 0; i != NumOps; ++i)
961 NumBytes += MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
963 // The prolog code of the callee may store up to 8 GPR argument registers to
964 // the stack, allowing va_start to index over them in memory if its varargs.
965 // Because we cannot tell if this is needed on the caller side, we have to
966 // conservatively assume that it is needed. As such, make sure we have at
967 // least enough stack space for the caller to store the 8 GPRs.
968 if (NumBytes < 6*PtrByteSize+8*PtrByteSize)
969 NumBytes = 6*PtrByteSize+8*PtrByteSize;
971 // Adjust the stack pointer for the new arguments...
972 // These operations are automatically eliminated by the prolog/epilog pass
973 Chain = DAG.getCALLSEQ_START(Chain,
974 DAG.getConstant(NumBytes, PtrVT));
976 // Set up a copy of the stack pointer for use loading and storing any
977 // arguments that may not fit in the registers available for argument
981 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
983 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
985 // Figure out which arguments are going to go in registers, and which in
986 // memory. Also, if this is a vararg function, floating point operations
987 // must be stored to our stack, and loaded into integer regs as well, if
988 // any integer regs are available for argument passing.
989 unsigned ArgOffset = 6*PtrByteSize;
990 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
991 static const unsigned GPR_32[] = { // 32-bit registers.
992 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
993 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
995 static const unsigned GPR_64[] = { // 64-bit registers.
996 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
997 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
999 static const unsigned FPR[] = {
1000 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1001 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1003 static const unsigned VR[] = {
1004 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1005 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1007 const unsigned NumGPRs = sizeof(GPR_32)/sizeof(GPR_32[0]);
1008 const unsigned NumFPRs = sizeof(FPR)/sizeof(FPR[0]);
1009 const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]);
1011 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1013 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1014 SmallVector<SDOperand, 8> MemOpChains;
1015 for (unsigned i = 0; i != NumOps; ++i) {
1016 SDOperand Arg = Op.getOperand(5+2*i);
1018 // PtrOff will be used to store the current argument to the stack if a
1019 // register cannot be found for it.
1020 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1021 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1023 // On PPC64, promote integers to 64-bit values.
1024 if (isPPC64 && Arg.getValueType() == MVT::i32) {
1025 unsigned ExtOp = ISD::ZERO_EXTEND;
1026 if (cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue())
1027 ExtOp = ISD::SIGN_EXTEND;
1028 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1031 switch (Arg.getValueType()) {
1032 default: assert(0 && "Unexpected ValueType for argument!");
1035 if (GPR_idx != NumGPRs) {
1036 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
1038 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1040 ArgOffset += PtrByteSize;
1044 if (FPR_idx != NumFPRs) {
1045 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1048 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1049 MemOpChains.push_back(Store);
1051 // Float varargs are always shadowed in available integer registers
1052 if (GPR_idx != NumGPRs) {
1053 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1054 MemOpChains.push_back(Load.getValue(1));
1055 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1057 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) {
1058 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1059 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
1060 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1061 MemOpChains.push_back(Load.getValue(1));
1062 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1065 // If we have any FPRs remaining, we may also have GPRs remaining.
1066 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1068 if (GPR_idx != NumGPRs)
1070 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64)
1074 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1079 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1085 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1086 assert(VR_idx != NumVRs &&
1087 "Don't support passing more than 12 vector args yet!");
1088 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1092 if (!MemOpChains.empty())
1093 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1094 &MemOpChains[0], MemOpChains.size());
1096 // Build a sequence of copy-to-reg nodes chained together with token chain
1097 // and flag operands which copy the outgoing args into the appropriate regs.
1099 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1100 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1102 InFlag = Chain.getValue(1);
1105 std::vector<MVT::ValueType> NodeTys;
1106 NodeTys.push_back(MVT::Other); // Returns a chain
1107 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1109 SmallVector<SDOperand, 8> Ops;
1110 unsigned CallOpc = PPCISD::CALL;
1112 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1113 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1114 // node so that legalize doesn't hack it.
1115 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1116 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1117 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1118 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1119 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1120 // If this is an absolute destination address, use the munged value.
1121 Callee = SDOperand(Dest, 0);
1123 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1124 // to do the call, we can't use PPCISD::CALL.
1125 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
1126 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
1127 InFlag = Chain.getValue(1);
1129 // Copy the callee address into R12 on darwin.
1130 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1131 InFlag = Chain.getValue(1);
1134 NodeTys.push_back(MVT::Other);
1135 NodeTys.push_back(MVT::Flag);
1136 Ops.push_back(Chain);
1137 CallOpc = PPCISD::BCTRL;
1141 // If this is a direct call, pass the chain and the callee.
1143 Ops.push_back(Chain);
1144 Ops.push_back(Callee);
1147 // Add argument registers to the end of the list so that they are known live
1149 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1150 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1151 RegsToPass[i].second.getValueType()));
1154 Ops.push_back(InFlag);
1155 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
1156 InFlag = Chain.getValue(1);
1158 SDOperand ResultVals[3];
1159 unsigned NumResults = 0;
1162 // If the call has results, copy the values out of the ret val registers.
1163 switch (Op.Val->getValueType(0)) {
1164 default: assert(0 && "Unexpected ret value!");
1165 case MVT::Other: break;
1167 if (Op.Val->getValueType(1) == MVT::i32) {
1168 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1);
1169 ResultVals[0] = Chain.getValue(0);
1170 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32,
1171 Chain.getValue(2)).getValue(1);
1172 ResultVals[1] = Chain.getValue(0);
1174 NodeTys.push_back(MVT::i32);
1176 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1177 ResultVals[0] = Chain.getValue(0);
1180 NodeTys.push_back(MVT::i32);
1183 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
1184 ResultVals[0] = Chain.getValue(0);
1186 NodeTys.push_back(MVT::i64);
1190 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1191 InFlag).getValue(1);
1192 ResultVals[0] = Chain.getValue(0);
1194 NodeTys.push_back(Op.Val->getValueType(0));
1200 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1201 InFlag).getValue(1);
1202 ResultVals[0] = Chain.getValue(0);
1204 NodeTys.push_back(Op.Val->getValueType(0));
1208 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1209 DAG.getConstant(NumBytes, PtrVT));
1210 NodeTys.push_back(MVT::Other);
1212 // If the function returns void, just return the chain.
1213 if (NumResults == 0)
1216 // Otherwise, merge everything together with a MERGE_VALUES node.
1217 ResultVals[NumResults++] = Chain;
1218 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1219 ResultVals, NumResults);
1220 return Res.getValue(Op.ResNo);
1223 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
1225 switch(Op.getNumOperands()) {
1227 assert(0 && "Do not know how to return this many arguments!");
1230 return SDOperand(); // ret void is legal
1232 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
1234 if (ArgVT == MVT::i32) {
1236 } else if (ArgVT == MVT::i64) {
1238 } else if (MVT::isVector(ArgVT)) {
1241 assert(MVT::isFloatingPoint(ArgVT));
1245 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
1248 // If we haven't noted the R3/F1 are live out, do so now.
1249 if (DAG.getMachineFunction().liveout_empty())
1250 DAG.getMachineFunction().addLiveOut(ArgReg);
1254 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3),
1256 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
1257 // If we haven't noted the R3+R4 are live out, do so now.
1258 if (DAG.getMachineFunction().liveout_empty()) {
1259 DAG.getMachineFunction().addLiveOut(PPC::R3);
1260 DAG.getMachineFunction().addLiveOut(PPC::R4);
1264 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
1267 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
1269 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
1270 // Not FP? Not a fsel.
1271 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
1272 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
1275 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1277 // Cannot handle SETEQ/SETNE.
1278 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
1280 MVT::ValueType ResVT = Op.getValueType();
1281 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
1282 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1283 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
1285 // If the RHS of the comparison is a 0.0, we don't need to do the
1286 // subtraction at all.
1287 if (isFloatingPointZero(RHS))
1289 default: break; // SETUO etc aren't handled by fsel.
1293 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1297 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1298 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1299 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
1303 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1307 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1308 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1309 return DAG.getNode(PPCISD::FSEL, ResVT,
1310 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
1315 default: break; // SETUO etc aren't handled by fsel.
1319 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1320 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1321 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1322 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1326 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1327 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1328 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1329 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1333 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1334 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1335 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1336 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1340 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1341 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1342 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1343 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1348 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
1349 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
1350 SDOperand Src = Op.getOperand(0);
1351 if (Src.getValueType() == MVT::f32)
1352 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
1355 switch (Op.getValueType()) {
1356 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
1358 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
1361 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
1365 // Convert the FP value to an int value through memory.
1366 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
1367 if (Op.getValueType() == MVT::i32)
1368 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
1372 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1373 if (Op.getOperand(0).getValueType() == MVT::i64) {
1374 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
1375 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
1376 if (Op.getValueType() == MVT::f32)
1377 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1381 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
1382 "Unhandled SINT_TO_FP type in custom expander!");
1383 // Since we only generate this in 64-bit mode, we can take advantage of
1384 // 64-bit registers. In particular, sign extend the input value into the
1385 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
1386 // then lfd it and fcfid it.
1387 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
1388 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
1389 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1390 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
1392 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
1395 // STD the extended value into the stack slot.
1396 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
1397 DAG.getEntryNode(), Ext64, FIdx,
1398 DAG.getSrcValue(NULL));
1399 // Load the value as a double.
1400 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
1402 // FCFID it and return it.
1403 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
1404 if (Op.getValueType() == MVT::f32)
1405 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1409 static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
1410 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1411 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
1413 // Expand into a bunch of logical ops. Note that these ops
1414 // depend on the PPC behavior for oversized shift amounts.
1415 SDOperand Lo = Op.getOperand(0);
1416 SDOperand Hi = Op.getOperand(1);
1417 SDOperand Amt = Op.getOperand(2);
1419 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1420 DAG.getConstant(32, MVT::i32), Amt);
1421 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
1422 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
1423 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1424 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1425 DAG.getConstant(-32U, MVT::i32));
1426 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
1427 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1428 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
1429 SDOperand OutOps[] = { OutLo, OutHi };
1430 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
1434 static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
1435 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1436 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!");
1438 // Otherwise, expand into a bunch of logical ops. Note that these ops
1439 // depend on the PPC behavior for oversized shift amounts.
1440 SDOperand Lo = Op.getOperand(0);
1441 SDOperand Hi = Op.getOperand(1);
1442 SDOperand Amt = Op.getOperand(2);
1444 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1445 DAG.getConstant(32, MVT::i32), Amt);
1446 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1447 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1448 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1449 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1450 DAG.getConstant(-32U, MVT::i32));
1451 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
1452 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1453 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
1454 SDOperand OutOps[] = { OutLo, OutHi };
1455 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
1459 static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
1460 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
1461 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
1463 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
1464 SDOperand Lo = Op.getOperand(0);
1465 SDOperand Hi = Op.getOperand(1);
1466 SDOperand Amt = Op.getOperand(2);
1468 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1469 DAG.getConstant(32, MVT::i32), Amt);
1470 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1471 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1472 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1473 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1474 DAG.getConstant(-32U, MVT::i32));
1475 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
1476 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
1477 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
1478 Tmp4, Tmp6, ISD::SETLE);
1479 SDOperand OutOps[] = { OutLo, OutHi };
1480 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
1484 //===----------------------------------------------------------------------===//
1485 // Vector related lowering.
1488 // If this is a vector of constants or undefs, get the bits. A bit in
1489 // UndefBits is set if the corresponding element of the vector is an
1490 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1491 // zero. Return true if this is not an array of constants, false if it is.
1493 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
1494 uint64_t UndefBits[2]) {
1495 // Start with zero'd results.
1496 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
1498 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
1499 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
1500 SDOperand OpVal = BV->getOperand(i);
1502 unsigned PartNo = i >= e/2; // In the upper 128 bits?
1503 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
1505 uint64_t EltBits = 0;
1506 if (OpVal.getOpcode() == ISD::UNDEF) {
1507 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
1508 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
1510 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1511 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
1512 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1513 assert(CN->getValueType(0) == MVT::f32 &&
1514 "Only one legal FP vector type!");
1515 EltBits = FloatToBits(CN->getValue());
1517 // Nonconstant element.
1521 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
1524 //printf("%llx %llx %llx %llx\n",
1525 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
1529 // If this is a splat (repetition) of a value across the whole vector, return
1530 // the smallest size that splats it. For example, "0x01010101010101..." is a
1531 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1532 // SplatSize = 1 byte.
1533 static bool isConstantSplat(const uint64_t Bits128[2],
1534 const uint64_t Undef128[2],
1535 unsigned &SplatBits, unsigned &SplatUndef,
1536 unsigned &SplatSize) {
1538 // Don't let undefs prevent splats from matching. See if the top 64-bits are
1539 // the same as the lower 64-bits, ignoring undefs.
1540 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
1541 return false; // Can't be a splat if two pieces don't match.
1543 uint64_t Bits64 = Bits128[0] | Bits128[1];
1544 uint64_t Undef64 = Undef128[0] & Undef128[1];
1546 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
1548 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
1549 return false; // Can't be a splat if two pieces don't match.
1551 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
1552 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
1554 // If the top 16-bits are different than the lower 16-bits, ignoring
1555 // undefs, we have an i32 splat.
1556 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
1558 SplatUndef = Undef32;
1563 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
1564 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
1566 // If the top 8-bits are different than the lower 8-bits, ignoring
1567 // undefs, we have an i16 splat.
1568 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
1570 SplatUndef = Undef16;
1575 // Otherwise, we have an 8-bit splat.
1576 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
1577 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
1582 /// BuildSplatI - Build a canonical splati of Val with an element size of
1583 /// SplatSize. Cast the result to VT.
1584 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
1585 SelectionDAG &DAG) {
1586 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
1588 // Force vspltis[hw] -1 to vspltisb -1.
1589 if (Val == -1) SplatSize = 1;
1591 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
1592 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
1594 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
1596 // Build a canonical splat for this value.
1597 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT));
1598 SmallVector<SDOperand, 8> Ops;
1599 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
1600 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
1601 &Ops[0], Ops.size());
1602 return DAG.getNode(ISD::BIT_CONVERT, VT, Res);
1605 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
1606 /// specified intrinsic ID.
1607 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
1609 MVT::ValueType DestVT = MVT::Other) {
1610 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
1611 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1612 DAG.getConstant(IID, MVT::i32), LHS, RHS);
1615 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
1616 /// specified intrinsic ID.
1617 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
1618 SDOperand Op2, SelectionDAG &DAG,
1619 MVT::ValueType DestVT = MVT::Other) {
1620 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
1621 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1622 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
1626 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
1627 /// amount. The result has the specified value type.
1628 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
1629 MVT::ValueType VT, SelectionDAG &DAG) {
1630 // Force LHS/RHS to be the right type.
1631 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
1632 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
1635 for (unsigned i = 0; i != 16; ++i)
1636 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
1637 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
1638 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
1639 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
1642 // If this is a case we can't handle, return null and let the default
1643 // expansion code take care of it. If we CAN select this case, and if it
1644 // selects to a single instruction, return Op. Otherwise, if we can codegen
1645 // this case more efficiently than a constant pool load, lower it to the
1646 // sequence of ops that should be used.
1647 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
1648 // If this is a vector of constants or undefs, get the bits. A bit in
1649 // UndefBits is set if the corresponding element of the vector is an
1650 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1652 uint64_t VectorBits[2];
1653 uint64_t UndefBits[2];
1654 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
1655 return SDOperand(); // Not a constant vector.
1657 // If this is a splat (repetition) of a value across the whole vector, return
1658 // the smallest size that splats it. For example, "0x01010101010101..." is a
1659 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1660 // SplatSize = 1 byte.
1661 unsigned SplatBits, SplatUndef, SplatSize;
1662 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
1663 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
1665 // First, handle single instruction cases.
1668 if (SplatBits == 0) {
1669 // Canonicalize all zero vectors to be v4i32.
1670 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
1671 SDOperand Z = DAG.getConstant(0, MVT::i32);
1672 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
1673 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
1678 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
1679 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
1680 if (SextVal >= -16 && SextVal <= 15)
1681 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
1684 // Two instruction sequences.
1686 // If this value is in the range [-32,30] and is even, use:
1687 // tmp = VSPLTI[bhw], result = add tmp, tmp
1688 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
1689 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
1690 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
1693 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
1694 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
1696 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
1697 // Make -1 and vspltisw -1:
1698 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
1700 // Make the VSLW intrinsic, computing 0x8000_0000.
1701 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
1704 // xor by OnesV to invert it.
1705 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
1706 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
1709 // Check to see if this is a wide variety of vsplti*, binop self cases.
1710 unsigned SplatBitSize = SplatSize*8;
1711 static const char SplatCsts[] = {
1712 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
1713 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
1715 for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){
1716 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
1717 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
1718 int i = SplatCsts[idx];
1720 // Figure out what shift amount will be used by altivec if shifted by i in
1722 unsigned TypeShiftAmt = i & (SplatBitSize-1);
1724 // vsplti + shl self.
1725 if (SextVal == (i << (int)TypeShiftAmt)) {
1726 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1727 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1728 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
1729 Intrinsic::ppc_altivec_vslw
1731 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1734 // vsplti + srl self.
1735 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
1736 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1737 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1738 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
1739 Intrinsic::ppc_altivec_vsrw
1741 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1744 // vsplti + sra self.
1745 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
1746 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1747 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1748 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
1749 Intrinsic::ppc_altivec_vsraw
1751 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1754 // vsplti + rol self.
1755 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
1756 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
1757 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1758 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1759 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
1760 Intrinsic::ppc_altivec_vrlw
1762 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1765 // t = vsplti c, result = vsldoi t, t, 1
1766 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
1767 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1768 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
1770 // t = vsplti c, result = vsldoi t, t, 2
1771 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
1772 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1773 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
1775 // t = vsplti c, result = vsldoi t, t, 3
1776 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
1777 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1778 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
1782 // Three instruction sequences.
1784 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
1785 if (SextVal >= 0 && SextVal <= 31) {
1786 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, Op.getValueType(),DAG);
1787 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
1788 return DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
1790 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
1791 if (SextVal >= -31 && SextVal <= 0) {
1792 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, Op.getValueType(),DAG);
1793 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
1794 return DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
1801 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
1802 /// the specified operations to build the shuffle.
1803 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
1804 SDOperand RHS, SelectionDAG &DAG) {
1805 unsigned OpNum = (PFEntry >> 26) & 0x0F;
1806 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
1807 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
1810 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
1822 if (OpNum == OP_COPY) {
1823 if (LHSID == (1*9+2)*9+3) return LHS;
1824 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
1828 SDOperand OpLHS, OpRHS;
1829 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
1830 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
1832 unsigned ShufIdxs[16];
1834 default: assert(0 && "Unknown i32 permute!");
1836 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
1837 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
1838 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
1839 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
1842 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
1843 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
1844 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
1845 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
1848 for (unsigned i = 0; i != 16; ++i)
1849 ShufIdxs[i] = (i&3)+0;
1852 for (unsigned i = 0; i != 16; ++i)
1853 ShufIdxs[i] = (i&3)+4;
1856 for (unsigned i = 0; i != 16; ++i)
1857 ShufIdxs[i] = (i&3)+8;
1860 for (unsigned i = 0; i != 16; ++i)
1861 ShufIdxs[i] = (i&3)+12;
1864 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
1866 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
1868 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
1871 for (unsigned i = 0; i != 16; ++i)
1872 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
1874 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
1875 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
1878 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
1879 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
1880 /// return the code it can be lowered into. Worst case, it can always be
1881 /// lowered into a vperm.
1882 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
1883 SDOperand V1 = Op.getOperand(0);
1884 SDOperand V2 = Op.getOperand(1);
1885 SDOperand PermMask = Op.getOperand(2);
1887 // Cases that are handled by instructions that take permute immediates
1888 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
1889 // selected by the instruction selector.
1890 if (V2.getOpcode() == ISD::UNDEF) {
1891 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
1892 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
1893 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
1894 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
1895 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
1896 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
1897 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
1898 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
1899 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
1900 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
1901 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
1902 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
1907 // Altivec has a variety of "shuffle immediates" that take two vector inputs
1908 // and produce a fixed permutation. If any of these match, do not lower to
1910 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
1911 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
1912 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
1913 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
1914 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
1915 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
1916 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
1917 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
1918 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
1921 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
1922 // perfect shuffle table to emit an optimal matching sequence.
1923 unsigned PFIndexes[4];
1924 bool isFourElementShuffle = true;
1925 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
1926 unsigned EltNo = 8; // Start out undef.
1927 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
1928 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
1929 continue; // Undef, ignore it.
1931 unsigned ByteSource =
1932 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
1933 if ((ByteSource & 3) != j) {
1934 isFourElementShuffle = false;
1939 EltNo = ByteSource/4;
1940 } else if (EltNo != ByteSource/4) {
1941 isFourElementShuffle = false;
1945 PFIndexes[i] = EltNo;
1948 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
1949 // perfect shuffle vector to determine if it is cost effective to do this as
1950 // discrete instructions, or whether we should use a vperm.
1951 if (isFourElementShuffle) {
1952 // Compute the index in the perfect shuffle table.
1953 unsigned PFTableIndex =
1954 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
1956 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
1957 unsigned Cost = (PFEntry >> 30);
1959 // Determining when to avoid vperm is tricky. Many things affect the cost
1960 // of vperm, particularly how many times the perm mask needs to be computed.
1961 // For example, if the perm mask can be hoisted out of a loop or is already
1962 // used (perhaps because there are multiple permutes with the same shuffle
1963 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
1964 // the loop requires an extra register.
1966 // As a compromise, we only emit discrete instructions if the shuffle can be
1967 // generated in 3 or fewer operations. When we have loop information
1968 // available, if this block is within a loop, we should avoid using vperm
1969 // for 3-operation perms and use a constant pool load instead.
1971 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
1974 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
1975 // vector that will get spilled to the constant pool.
1976 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
1978 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
1979 // that it is in input element units, not in bytes. Convert now.
1980 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
1981 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
1983 SmallVector<SDOperand, 16> ResultMask;
1984 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
1986 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
1989 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
1991 for (unsigned j = 0; j != BytesPerElement; ++j)
1992 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
1996 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
1997 &ResultMask[0], ResultMask.size());
1998 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
2001 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
2002 /// altivec comparison. If it is, return true and fill in Opc/isDot with
2003 /// information about the intrinsic.
2004 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
2006 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
2009 switch (IntrinsicID) {
2010 default: return false;
2011 // Comparison predicates.
2012 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
2013 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
2014 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
2015 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
2016 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
2017 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
2018 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
2019 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
2020 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
2021 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
2022 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
2023 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
2024 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
2026 // Normal Comparisons.
2027 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
2028 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
2029 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
2030 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
2031 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
2032 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
2033 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
2034 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
2035 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
2036 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
2037 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
2038 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
2039 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
2044 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
2045 /// lower, do it, otherwise return null.
2046 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
2047 // If this is a lowered altivec predicate compare, CompareOpc is set to the
2048 // opcode number of the comparison.
2051 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
2052 return SDOperand(); // Don't custom lower most intrinsics.
2054 // If this is a non-dot comparison, make the VCMP node and we are done.
2056 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
2057 Op.getOperand(1), Op.getOperand(2),
2058 DAG.getConstant(CompareOpc, MVT::i32));
2059 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
2062 // Create the PPCISD altivec 'dot' comparison node.
2064 Op.getOperand(2), // LHS
2065 Op.getOperand(3), // RHS
2066 DAG.getConstant(CompareOpc, MVT::i32)
2068 std::vector<MVT::ValueType> VTs;
2069 VTs.push_back(Op.getOperand(2).getValueType());
2070 VTs.push_back(MVT::Flag);
2071 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2073 // Now that we have the comparison, emit a copy from the CR to a GPR.
2074 // This is flagged to the above dot comparison.
2075 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
2076 DAG.getRegister(PPC::CR6, MVT::i32),
2077 CompNode.getValue(1));
2079 // Unpack the result based on how the target uses it.
2080 unsigned BitNo; // Bit # of CR6.
2081 bool InvertBit; // Invert result?
2082 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
2083 default: // Can't happen, don't crash on invalid number though.
2084 case 0: // Return the value of the EQ bit of CR6.
2085 BitNo = 0; InvertBit = false;
2087 case 1: // Return the inverted value of the EQ bit of CR6.
2088 BitNo = 0; InvertBit = true;
2090 case 2: // Return the value of the LT bit of CR6.
2091 BitNo = 2; InvertBit = false;
2093 case 3: // Return the inverted value of the LT bit of CR6.
2094 BitNo = 2; InvertBit = true;
2098 // Shift the bit into the low position.
2099 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
2100 DAG.getConstant(8-(3-BitNo), MVT::i32));
2102 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
2103 DAG.getConstant(1, MVT::i32));
2105 // If we are supposed to, toggle the bit.
2107 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
2108 DAG.getConstant(1, MVT::i32));
2112 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2113 // Create a stack slot that is 16-byte aligned.
2114 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2115 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
2116 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2117 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2119 // Store the input value into Value#0 of the stack slot.
2120 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
2121 Op.getOperand(0), FIdx, NULL, 0);
2123 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
2126 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
2127 if (Op.getValueType() == MVT::v4i32) {
2128 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2130 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
2131 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
2133 SDOperand RHSSwap = // = vrlw RHS, 16
2134 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
2136 // Shrinkify inputs to v8i16.
2137 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
2138 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
2139 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
2141 // Low parts multiplied together, generating 32-bit results (we ignore the
2143 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
2144 LHS, RHS, DAG, MVT::v4i32);
2146 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
2147 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
2148 // Shift the high parts up 16 bits.
2149 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
2150 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
2151 } else if (Op.getValueType() == MVT::v8i16) {
2152 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2154 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
2156 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
2157 LHS, RHS, Zero, DAG);
2158 } else if (Op.getValueType() == MVT::v16i8) {
2159 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2161 // Multiply the even 8-bit parts, producing 16-bit sums.
2162 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
2163 LHS, RHS, DAG, MVT::v8i16);
2164 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
2166 // Multiply the odd 8-bit parts, producing 16-bit sums.
2167 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
2168 LHS, RHS, DAG, MVT::v8i16);
2169 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
2171 // Merge the results together.
2173 for (unsigned i = 0; i != 8; ++i) {
2174 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
2175 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
2177 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
2178 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2180 assert(0 && "Unknown mul to lower!");
2185 /// LowerOperation - Provide custom lowering hooks for some operations.
2187 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2188 switch (Op.getOpcode()) {
2189 default: assert(0 && "Wasn't expecting to be able to lower this!");
2190 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2191 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2192 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2193 case ISD::SETCC: return LowerSETCC(Op, DAG);
2194 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2195 case ISD::FORMAL_ARGUMENTS:
2196 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex);
2197 case ISD::CALL: return LowerCALL(Op, DAG);
2198 case ISD::RET: return LowerRET(Op, DAG);
2200 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2201 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
2202 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
2204 // Lower 64-bit shifts.
2205 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
2206 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
2207 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
2209 // Vector-related lowering.
2210 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2211 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2212 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2213 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2214 case ISD::MUL: return LowerMUL(Op, DAG);
2219 //===----------------------------------------------------------------------===//
2220 // Other Lowering Code
2221 //===----------------------------------------------------------------------===//
2224 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2225 MachineBasicBlock *BB) {
2226 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
2227 MI->getOpcode() == PPC::SELECT_CC_I8 ||
2228 MI->getOpcode() == PPC::SELECT_CC_F4 ||
2229 MI->getOpcode() == PPC::SELECT_CC_F8 ||
2230 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
2231 "Unexpected instr type to insert");
2233 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2234 // control-flow pattern. The incoming instruction knows the destination vreg
2235 // to set, the condition code register to branch on, the true/false values to
2236 // select between, and a branch opcode to use.
2237 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2238 ilist<MachineBasicBlock>::iterator It = BB;
2244 // cmpTY ccX, r1, r2
2246 // fallthrough --> copy0MBB
2247 MachineBasicBlock *thisMBB = BB;
2248 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2249 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2250 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
2251 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
2252 MachineFunction *F = BB->getParent();
2253 F->getBasicBlockList().insert(It, copy0MBB);
2254 F->getBasicBlockList().insert(It, sinkMBB);
2255 // Update machine-CFG edges by first adding all successors of the current
2256 // block to the new block which will contain the Phi node for the select.
2257 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2258 e = BB->succ_end(); i != e; ++i)
2259 sinkMBB->addSuccessor(*i);
2260 // Next, remove all successors of the current block, and add the true
2261 // and fallthrough blocks as its successors.
2262 while(!BB->succ_empty())
2263 BB->removeSuccessor(BB->succ_begin());
2264 BB->addSuccessor(copy0MBB);
2265 BB->addSuccessor(sinkMBB);
2268 // %FalseValue = ...
2269 // # fallthrough to sinkMBB
2272 // Update machine-CFG edges
2273 BB->addSuccessor(sinkMBB);
2276 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2279 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
2280 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
2281 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2283 delete MI; // The pseudo instruction is gone now.
2287 //===----------------------------------------------------------------------===//
2288 // Target Optimization Hooks
2289 //===----------------------------------------------------------------------===//
2291 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
2292 DAGCombinerInfo &DCI) const {
2293 TargetMachine &TM = getTargetMachine();
2294 SelectionDAG &DAG = DCI.DAG;
2295 switch (N->getOpcode()) {
2298 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2299 if (C->getValue() == 0) // 0 << V -> 0.
2300 return N->getOperand(0);
2304 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2305 if (C->getValue() == 0) // 0 >>u V -> 0.
2306 return N->getOperand(0);
2310 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
2311 if (C->getValue() == 0 || // 0 >>s V -> 0.
2312 C->isAllOnesValue()) // -1 >>s V -> -1.
2313 return N->getOperand(0);
2317 case ISD::SINT_TO_FP:
2318 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
2319 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
2320 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
2321 // We allow the src/dst to be either f32/f64, but the intermediate
2322 // type must be i64.
2323 if (N->getOperand(0).getValueType() == MVT::i64) {
2324 SDOperand Val = N->getOperand(0).getOperand(0);
2325 if (Val.getValueType() == MVT::f32) {
2326 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2327 DCI.AddToWorklist(Val.Val);
2330 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
2331 DCI.AddToWorklist(Val.Val);
2332 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
2333 DCI.AddToWorklist(Val.Val);
2334 if (N->getValueType(0) == MVT::f32) {
2335 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
2336 DCI.AddToWorklist(Val.Val);
2339 } else if (N->getOperand(0).getValueType() == MVT::i32) {
2340 // If the intermediate type is i32, we can avoid the load/store here
2347 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
2348 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
2349 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
2350 N->getOperand(1).getValueType() == MVT::i32) {
2351 SDOperand Val = N->getOperand(1).getOperand(0);
2352 if (Val.getValueType() == MVT::f32) {
2353 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2354 DCI.AddToWorklist(Val.Val);
2356 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
2357 DCI.AddToWorklist(Val.Val);
2359 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
2360 N->getOperand(2), N->getOperand(3));
2361 DCI.AddToWorklist(Val.Val);
2365 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
2366 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
2367 N->getOperand(1).Val->hasOneUse() &&
2368 (N->getOperand(1).getValueType() == MVT::i32 ||
2369 N->getOperand(1).getValueType() == MVT::i16)) {
2370 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
2371 // Do an any-extend to 32-bits if this is a half-word input.
2372 if (BSwapOp.getValueType() == MVT::i16)
2373 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
2375 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
2376 N->getOperand(2), N->getOperand(3),
2377 DAG.getValueType(N->getOperand(1).getValueType()));
2381 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
2382 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
2383 N->getOperand(0).hasOneUse() &&
2384 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
2385 SDOperand Load = N->getOperand(0);
2386 LoadSDNode *LD = cast<LoadSDNode>(Load);
2387 // Create the byte-swapping load.
2388 std::vector<MVT::ValueType> VTs;
2389 VTs.push_back(MVT::i32);
2390 VTs.push_back(MVT::Other);
2391 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset());
2393 LD->getChain(), // Chain
2394 LD->getBasePtr(), // Ptr
2396 DAG.getValueType(N->getValueType(0)) // VT
2398 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
2400 // If this is an i16 load, insert the truncate.
2401 SDOperand ResVal = BSLoad;
2402 if (N->getValueType(0) == MVT::i16)
2403 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
2405 // First, combine the bswap away. This makes the value produced by the
2407 DCI.CombineTo(N, ResVal);
2409 // Next, combine the load away, we give it a bogus result value but a real
2410 // chain result. The result value is dead because the bswap is dead.
2411 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
2413 // Return N so it doesn't get rechecked!
2414 return SDOperand(N, 0);
2418 case PPCISD::VCMP: {
2419 // If a VCMPo node already exists with exactly the same operands as this
2420 // node, use its result instead of this node (VCMPo computes both a CR6 and
2421 // a normal output).
2423 if (!N->getOperand(0).hasOneUse() &&
2424 !N->getOperand(1).hasOneUse() &&
2425 !N->getOperand(2).hasOneUse()) {
2427 // Scan all of the users of the LHS, looking for VCMPo's that match.
2428 SDNode *VCMPoNode = 0;
2430 SDNode *LHSN = N->getOperand(0).Val;
2431 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
2433 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
2434 (*UI)->getOperand(1) == N->getOperand(1) &&
2435 (*UI)->getOperand(2) == N->getOperand(2) &&
2436 (*UI)->getOperand(0) == N->getOperand(0)) {
2441 // If there is no VCMPo node, or if the flag value has a single use, don't
2443 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
2446 // Look at the (necessarily single) use of the flag value. If it has a
2447 // chain, this transformation is more complex. Note that multiple things
2448 // could use the value result, which we should ignore.
2449 SDNode *FlagUser = 0;
2450 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
2451 FlagUser == 0; ++UI) {
2452 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
2454 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2455 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
2462 // If the user is a MFCR instruction, we know this is safe. Otherwise we
2463 // give up for right now.
2464 if (FlagUser->getOpcode() == PPCISD::MFCR)
2465 return SDOperand(VCMPoNode, 0);
2470 // If this is a branch on an altivec predicate comparison, lower this so
2471 // that we don't have to do a MFCR: instead, branch directly on CR6. This
2472 // lowering is done pre-legalize, because the legalizer lowers the predicate
2473 // compare down to code that is difficult to reassemble.
2474 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
2475 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
2479 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2480 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
2481 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
2482 assert(isDot && "Can't compare against a vector result!");
2484 // If this is a comparison against something other than 0/1, then we know
2485 // that the condition is never/always true.
2486 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
2487 if (Val != 0 && Val != 1) {
2488 if (CC == ISD::SETEQ) // Cond never true, remove branch.
2489 return N->getOperand(0);
2490 // Always !=, turn it into an unconditional branch.
2491 return DAG.getNode(ISD::BR, MVT::Other,
2492 N->getOperand(0), N->getOperand(4));
2495 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
2497 // Create the PPCISD altivec 'dot' comparison node.
2498 std::vector<MVT::ValueType> VTs;
2500 LHS.getOperand(2), // LHS of compare
2501 LHS.getOperand(3), // RHS of compare
2502 DAG.getConstant(CompareOpc, MVT::i32)
2504 VTs.push_back(LHS.getOperand(2).getValueType());
2505 VTs.push_back(MVT::Flag);
2506 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2508 // Unpack the result based on how the target uses it.
2510 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
2511 default: // Can't happen, don't crash on invalid number though.
2512 case 0: // Branch on the value of the EQ bit of CR6.
2513 CompOpc = BranchOnWhenPredTrue ? PPC::BEQ : PPC::BNE;
2515 case 1: // Branch on the inverted value of the EQ bit of CR6.
2516 CompOpc = BranchOnWhenPredTrue ? PPC::BNE : PPC::BEQ;
2518 case 2: // Branch on the value of the LT bit of CR6.
2519 CompOpc = BranchOnWhenPredTrue ? PPC::BLT : PPC::BGE;
2521 case 3: // Branch on the inverted value of the LT bit of CR6.
2522 CompOpc = BranchOnWhenPredTrue ? PPC::BGE : PPC::BLT;
2526 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
2527 DAG.getRegister(PPC::CR6, MVT::i32),
2528 DAG.getConstant(CompOpc, MVT::i32),
2529 N->getOperand(4), CompNode.getValue(1));
2538 //===----------------------------------------------------------------------===//
2539 // Inline Assembly Support
2540 //===----------------------------------------------------------------------===//
2542 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
2544 uint64_t &KnownZero,
2546 unsigned Depth) const {
2549 switch (Op.getOpcode()) {
2551 case PPCISD::LBRX: {
2552 // lhbrx is known to have the top bits cleared out.
2553 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
2554 KnownZero = 0xFFFF0000;
2557 case ISD::INTRINSIC_WO_CHAIN: {
2558 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
2560 case Intrinsic::ppc_altivec_vcmpbfp_p:
2561 case Intrinsic::ppc_altivec_vcmpeqfp_p:
2562 case Intrinsic::ppc_altivec_vcmpequb_p:
2563 case Intrinsic::ppc_altivec_vcmpequh_p:
2564 case Intrinsic::ppc_altivec_vcmpequw_p:
2565 case Intrinsic::ppc_altivec_vcmpgefp_p:
2566 case Intrinsic::ppc_altivec_vcmpgtfp_p:
2567 case Intrinsic::ppc_altivec_vcmpgtsb_p:
2568 case Intrinsic::ppc_altivec_vcmpgtsh_p:
2569 case Intrinsic::ppc_altivec_vcmpgtsw_p:
2570 case Intrinsic::ppc_altivec_vcmpgtub_p:
2571 case Intrinsic::ppc_altivec_vcmpgtuh_p:
2572 case Intrinsic::ppc_altivec_vcmpgtuw_p:
2573 KnownZero = ~1U; // All bits but the low one are known to be zero.
2581 /// getConstraintType - Given a constraint letter, return the type of
2582 /// constraint it is for this target.
2583 PPCTargetLowering::ConstraintType
2584 PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
2585 switch (ConstraintLetter) {
2592 return C_RegisterClass;
2594 return TargetLowering::getConstraintType(ConstraintLetter);
2598 std::vector<unsigned> PPCTargetLowering::
2599 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2600 MVT::ValueType VT) const {
2601 if (Constraint.size() == 1) {
2602 switch (Constraint[0]) { // GCC RS6000 Constraint Letters
2603 default: break; // Unknown constriant letter
2605 return make_vector<unsigned>(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 ,
2606 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
2607 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
2608 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
2609 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
2610 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
2611 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
2612 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
2615 return make_vector<unsigned>(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 ,
2616 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
2617 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
2618 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
2619 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
2620 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
2621 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
2622 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
2625 return make_vector<unsigned>(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 ,
2626 PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 ,
2627 PPC::F8 , PPC::F9 , PPC::F10, PPC::F11,
2628 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
2629 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
2630 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
2631 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
2632 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
2635 return make_vector<unsigned>(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 ,
2636 PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
2637 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11,
2638 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
2639 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
2640 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
2641 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
2642 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
2645 return make_vector<unsigned>(PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
2646 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7,
2651 return std::vector<unsigned>();
2654 // isOperandValidForConstraint
2655 bool PPCTargetLowering::
2656 isOperandValidForConstraint(SDOperand Op, char Letter) {
2667 if (!isa<ConstantSDNode>(Op)) return false; // Must be an immediate.
2668 unsigned Value = cast<ConstantSDNode>(Op)->getValue();
2670 default: assert(0 && "Unknown constraint letter!");
2671 case 'I': // "I" is a signed 16-bit constant.
2672 return (short)Value == (int)Value;
2673 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
2674 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
2675 return (short)Value == 0;
2676 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
2677 return (Value >> 16) == 0;
2678 case 'M': // "M" is a constant that is greater than 31.
2680 case 'N': // "N" is a positive constant that is an exact power of two.
2681 return (int)Value > 0 && isPowerOf2_32(Value);
2682 case 'O': // "O" is the constant zero.
2684 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
2685 return (short)-Value == (int)-Value;
2691 // Handle standard constraint letters.
2692 return TargetLowering::isOperandValidForConstraint(Op, Letter);
2695 /// isLegalAddressImmediate - Return true if the integer value can be used
2696 /// as the offset of the target addressing mode.
2697 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const {
2698 // PPC allows a sign-extended 16-bit immediate field.
2699 return (V > -(1 << 16) && V < (1 << 16)-1);
2702 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
2703 return TargetLowering::isLegalAddressImmediate(GV);