1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
43 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
45 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
46 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
49 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
51 // FIXME: Remove this once the bug has been fixed!
52 extern cl::opt<bool> ANDIGlueBug;
54 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
55 // If it isn't a Mach-O file then it's going to be a linux ELF
58 return new TargetLoweringObjectFileMachO();
60 return new PPC64LinuxTargetObjectFile();
63 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
64 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))),
65 Subtarget(*TM.getSubtargetImpl()) {
68 // Use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(true);
72 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
73 // arguments are at least 4/8 bytes aligned.
74 bool isPPC64 = Subtarget.isPPC64();
75 setMinStackArgumentAlignment(isPPC64 ? 8:4);
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
82 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // PowerPC has pre-inc load and store's.
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
100 if (Subtarget.useCRBits()) {
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
103 if (isPPC64 || Subtarget.hasFPCVT()) {
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
108 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
109 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
115 // PowerPC does not support direct load / store of condition registers
116 setOperationAction(ISD::LOAD, MVT::i1, Custom);
117 setOperationAction(ISD::STORE, MVT::i1, Custom);
119 // FIXME: Remove this once the ANDI glue bug is fixed:
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
125 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
127 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
128 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath &&
180 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget.hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath &&
185 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget.hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget.hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget.hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget.useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget.isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget.isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget.has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget.use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget.hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
405 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
407 // add/sub are legal for all supported vector VT's.
408 setOperationAction(ISD::ADD , VT, Legal);
409 setOperationAction(ISD::SUB , VT, Legal);
411 // We promote all shuffles to v16i8.
412 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
413 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
415 // We promote all non-typed operations to v4i32.
416 setOperationAction(ISD::AND , VT, Promote);
417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
418 setOperationAction(ISD::OR , VT, Promote);
419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
420 setOperationAction(ISD::XOR , VT, Promote);
421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
422 setOperationAction(ISD::LOAD , VT, Promote);
423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
424 setOperationAction(ISD::SELECT, VT, Promote);
425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
426 setOperationAction(ISD::STORE, VT, Promote);
427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
429 // No other operations are legal.
430 setOperationAction(ISD::MUL , VT, Expand);
431 setOperationAction(ISD::SDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UDIV, VT, Expand);
434 setOperationAction(ISD::UREM, VT, Expand);
435 setOperationAction(ISD::FDIV, VT, Expand);
436 setOperationAction(ISD::FREM, VT, Expand);
437 setOperationAction(ISD::FNEG, VT, Expand);
438 setOperationAction(ISD::FSQRT, VT, Expand);
439 setOperationAction(ISD::FLOG, VT, Expand);
440 setOperationAction(ISD::FLOG10, VT, Expand);
441 setOperationAction(ISD::FLOG2, VT, Expand);
442 setOperationAction(ISD::FEXP, VT, Expand);
443 setOperationAction(ISD::FEXP2, VT, Expand);
444 setOperationAction(ISD::FSIN, VT, Expand);
445 setOperationAction(ISD::FCOS, VT, Expand);
446 setOperationAction(ISD::FABS, VT, Expand);
447 setOperationAction(ISD::FPOWI, VT, Expand);
448 setOperationAction(ISD::FFLOOR, VT, Expand);
449 setOperationAction(ISD::FCEIL, VT, Expand);
450 setOperationAction(ISD::FTRUNC, VT, Expand);
451 setOperationAction(ISD::FRINT, VT, Expand);
452 setOperationAction(ISD::FNEARBYINT, VT, Expand);
453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
455 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
456 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
457 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
458 setOperationAction(ISD::UDIVREM, VT, Expand);
459 setOperationAction(ISD::SDIVREM, VT, Expand);
460 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
461 setOperationAction(ISD::FPOW, VT, Expand);
462 setOperationAction(ISD::BSWAP, VT, Expand);
463 setOperationAction(ISD::CTPOP, VT, Expand);
464 setOperationAction(ISD::CTLZ, VT, Expand);
465 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
466 setOperationAction(ISD::CTTZ, VT, Expand);
467 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
468 setOperationAction(ISD::VSELECT, VT, Expand);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
471 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
472 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
473 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
474 setTruncStoreAction(VT, InnerVT, Expand);
476 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
477 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
478 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
481 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
482 // with merges, splats, etc.
483 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
485 setOperationAction(ISD::AND , MVT::v4i32, Legal);
486 setOperationAction(ISD::OR , MVT::v4i32, Legal);
487 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
488 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
489 setOperationAction(ISD::SELECT, MVT::v4i32,
490 Subtarget.useCRBits() ? Legal : Expand);
491 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
492 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
493 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
494 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
495 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
496 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
497 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
498 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
499 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
501 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
502 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
503 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
504 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
506 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
507 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
509 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
510 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
511 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
514 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
515 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
516 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
518 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
519 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
521 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
522 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
524 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
526 // Altivec does not contain unordered floating-point compare instructions
527 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
528 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
529 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
530 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
531 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
532 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
534 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
535 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
537 if (Subtarget.hasVSX()) {
538 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
541 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
542 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
543 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
544 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
545 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
547 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
549 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
550 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
552 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
553 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
559 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
561 // Share the Altivec comparison restrictions.
562 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
563 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
564 setCondCodeAction(ISD::SETUGT, MVT::v2f64, Expand);
565 setCondCodeAction(ISD::SETUGE, MVT::v2f64, Expand);
566 setCondCodeAction(ISD::SETULT, MVT::v2f64, Expand);
567 setCondCodeAction(ISD::SETULE, MVT::v2f64, Expand);
569 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
570 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
572 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
573 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
575 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
577 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
579 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
580 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
582 // VSX v2i64 only supports non-arithmetic operations.
583 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
584 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
586 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
587 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
588 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
590 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
592 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
593 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
594 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
595 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
597 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
599 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
600 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
601 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
602 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
604 // Vector operation legalization checks the result type of
605 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
608 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
611 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
615 if (Subtarget.has64BitSupport()) {
616 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
617 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
620 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
621 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
622 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
623 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
625 setBooleanContents(ZeroOrOneBooleanContent);
626 // Altivec instructions set fields to all zeros or all ones.
627 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
630 setStackPointerRegisterToSaveRestore(PPC::X1);
631 setExceptionPointerRegister(PPC::X3);
632 setExceptionSelectorRegister(PPC::X4);
634 setStackPointerRegisterToSaveRestore(PPC::R1);
635 setExceptionPointerRegister(PPC::R3);
636 setExceptionSelectorRegister(PPC::R4);
639 // We have target-specific dag combine patterns for the following nodes:
640 setTargetDAGCombine(ISD::SINT_TO_FP);
641 setTargetDAGCombine(ISD::LOAD);
642 setTargetDAGCombine(ISD::STORE);
643 setTargetDAGCombine(ISD::BR_CC);
644 if (Subtarget.useCRBits())
645 setTargetDAGCombine(ISD::BRCOND);
646 setTargetDAGCombine(ISD::BSWAP);
647 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
649 setTargetDAGCombine(ISD::SIGN_EXTEND);
650 setTargetDAGCombine(ISD::ZERO_EXTEND);
651 setTargetDAGCombine(ISD::ANY_EXTEND);
653 if (Subtarget.useCRBits()) {
654 setTargetDAGCombine(ISD::TRUNCATE);
655 setTargetDAGCombine(ISD::SETCC);
656 setTargetDAGCombine(ISD::SELECT_CC);
659 // Use reciprocal estimates.
660 if (TM.Options.UnsafeFPMath) {
661 setTargetDAGCombine(ISD::FDIV);
662 setTargetDAGCombine(ISD::FSQRT);
665 // Darwin long double math library functions have $LDBL128 appended.
666 if (Subtarget.isDarwin()) {
667 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
668 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
669 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
670 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
671 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
672 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
673 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
674 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
675 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
676 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
679 // With 32 condition bits, we don't need to sink (and duplicate) compares
680 // aggressively in CodeGenPrep.
681 if (Subtarget.useCRBits())
682 setHasMultipleConditionRegisters();
684 setMinFunctionAlignment(2);
685 if (Subtarget.isDarwin())
686 setPrefFunctionAlignment(4);
688 if (isPPC64 && Subtarget.isJITCodeModel())
689 // Temporary workaround for the inability of PPC64 JIT to handle jump
691 setSupportJumpTables(false);
693 setInsertFencesForAtomic(true);
695 if (Subtarget.enableMachineScheduler())
696 setSchedulingPreference(Sched::Source);
698 setSchedulingPreference(Sched::Hybrid);
700 computeRegisterProperties();
702 // The Freescale cores does better with aggressive inlining of memcpy and
703 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
704 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
705 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
706 MaxStoresPerMemset = 32;
707 MaxStoresPerMemsetOptSize = 16;
708 MaxStoresPerMemcpy = 32;
709 MaxStoresPerMemcpyOptSize = 8;
710 MaxStoresPerMemmove = 32;
711 MaxStoresPerMemmoveOptSize = 8;
713 setPrefFunctionAlignment(4);
717 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
718 /// the desired ByVal argument alignment.
719 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
720 unsigned MaxMaxAlign) {
721 if (MaxAlign == MaxMaxAlign)
723 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
724 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
726 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
728 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
729 unsigned EltAlign = 0;
730 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
731 if (EltAlign > MaxAlign)
733 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
734 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
735 unsigned EltAlign = 0;
736 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
737 if (EltAlign > MaxAlign)
739 if (MaxAlign == MaxMaxAlign)
745 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
746 /// function arguments in the caller parameter area.
747 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
748 // Darwin passes everything on 4 byte boundary.
749 if (Subtarget.isDarwin())
752 // 16byte and wider vectors are passed on 16byte boundary.
753 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
754 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
755 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
756 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
760 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
762 default: return nullptr;
763 case PPCISD::FSEL: return "PPCISD::FSEL";
764 case PPCISD::FCFID: return "PPCISD::FCFID";
765 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
766 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
767 case PPCISD::FRE: return "PPCISD::FRE";
768 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
769 case PPCISD::STFIWX: return "PPCISD::STFIWX";
770 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
771 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
772 case PPCISD::VPERM: return "PPCISD::VPERM";
773 case PPCISD::Hi: return "PPCISD::Hi";
774 case PPCISD::Lo: return "PPCISD::Lo";
775 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
776 case PPCISD::LOAD: return "PPCISD::LOAD";
777 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
778 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
779 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
780 case PPCISD::SRL: return "PPCISD::SRL";
781 case PPCISD::SRA: return "PPCISD::SRA";
782 case PPCISD::SHL: return "PPCISD::SHL";
783 case PPCISD::CALL: return "PPCISD::CALL";
784 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
785 case PPCISD::MTCTR: return "PPCISD::MTCTR";
786 case PPCISD::BCTRL: return "PPCISD::BCTRL";
787 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
788 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
789 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
790 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
791 case PPCISD::VCMP: return "PPCISD::VCMP";
792 case PPCISD::VCMPo: return "PPCISD::VCMPo";
793 case PPCISD::LBRX: return "PPCISD::LBRX";
794 case PPCISD::STBRX: return "PPCISD::STBRX";
795 case PPCISD::LARX: return "PPCISD::LARX";
796 case PPCISD::STCX: return "PPCISD::STCX";
797 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
798 case PPCISD::BDNZ: return "PPCISD::BDNZ";
799 case PPCISD::BDZ: return "PPCISD::BDZ";
800 case PPCISD::MFFS: return "PPCISD::MFFS";
801 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
802 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
803 case PPCISD::CR6SET: return "PPCISD::CR6SET";
804 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
805 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
806 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
807 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
808 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
809 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
810 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
811 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
812 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
813 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
814 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
815 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
816 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
817 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
818 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
819 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
820 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
821 case PPCISD::SC: return "PPCISD::SC";
825 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
827 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
828 return VT.changeVectorElementTypeToInteger();
831 //===----------------------------------------------------------------------===//
832 // Node matching predicates, for use by the tblgen matching code.
833 //===----------------------------------------------------------------------===//
835 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
836 static bool isFloatingPointZero(SDValue Op) {
837 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
838 return CFP->getValueAPF().isZero();
839 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
840 // Maybe this has already been legalized into the constant pool?
841 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
842 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
843 return CFP->getValueAPF().isZero();
848 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
849 /// true if Op is undef or if it matches the specified value.
850 static bool isConstantOrUndef(int Op, int Val) {
851 return Op < 0 || Op == Val;
854 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
855 /// VPKUHUM instruction.
856 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
858 unsigned j = DAG.getTarget().getDataLayout()->isLittleEndian() ? 0 : 1;
860 for (unsigned i = 0; i != 16; ++i)
861 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j))
864 for (unsigned i = 0; i != 8; ++i)
865 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
866 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
872 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
873 /// VPKUWUM instruction.
874 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
877 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
885 for (unsigned i = 0; i != 16; i += 2)
886 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
887 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k))
890 for (unsigned i = 0; i != 8; i += 2)
891 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
892 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k) ||
893 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
894 !isConstantOrUndef(N->getMaskElt(i+9), i*2+k))
900 /// isVMerge - Common function, used to match vmrg* shuffles.
902 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
903 unsigned LHSStart, unsigned RHSStart) {
904 if (N->getValueType(0) != MVT::v16i8)
906 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
907 "Unsupported merge size!");
909 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
910 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
911 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
912 LHSStart+j+i*UnitSize) ||
913 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
914 RHSStart+j+i*UnitSize))
920 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
921 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
922 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
923 bool isUnary, SelectionDAG &DAG) {
924 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
926 return isVMerge(N, UnitSize, 0, 16);
927 return isVMerge(N, UnitSize, 0, 0);
930 return isVMerge(N, UnitSize, 8, 24);
931 return isVMerge(N, UnitSize, 8, 8);
935 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
936 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
937 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
938 bool isUnary, SelectionDAG &DAG) {
939 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
941 return isVMerge(N, UnitSize, 8, 24);
942 return isVMerge(N, UnitSize, 8, 8);
945 return isVMerge(N, UnitSize, 0, 16);
946 return isVMerge(N, UnitSize, 0, 0);
951 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
952 /// amount, otherwise return -1.
953 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG) {
954 if (N->getValueType(0) != MVT::v16i8)
957 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
959 // Find the first non-undef value in the shuffle mask.
961 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
964 if (i == 16) return -1; // all undef.
966 // Otherwise, check to see if the rest of the elements are consecutively
967 // numbered from this value.
968 unsigned ShiftAmt = SVOp->getMaskElt(i);
969 if (ShiftAmt < i) return -1;
971 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
976 // Check the rest of the elements to see if they are consecutive.
977 for (++i; i != 16; ++i)
978 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt - i))
981 // Check the rest of the elements to see if they are consecutive.
982 for (++i; i != 16; ++i)
983 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt - i) & 15))
987 } else { // Big Endian
992 // Check the rest of the elements to see if they are consecutive.
993 for (++i; i != 16; ++i)
994 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
997 // Check the rest of the elements to see if they are consecutive.
998 for (++i; i != 16; ++i)
999 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1006 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1007 /// specifies a splat of a single element that is suitable for input to
1008 /// VSPLTB/VSPLTH/VSPLTW.
1009 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1010 assert(N->getValueType(0) == MVT::v16i8 &&
1011 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1013 // This is a splat operation if each element of the permute is the same, and
1014 // if the value doesn't reference the second vector.
1015 unsigned ElementBase = N->getMaskElt(0);
1017 // FIXME: Handle UNDEF elements too!
1018 if (ElementBase >= 16)
1021 // Check that the indices are consecutive, in the case of a multi-byte element
1022 // splatted with a v16i8 mask.
1023 for (unsigned i = 1; i != EltSize; ++i)
1024 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1027 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1028 if (N->getMaskElt(i) < 0) continue;
1029 for (unsigned j = 0; j != EltSize; ++j)
1030 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1036 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1038 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1039 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1041 APInt APVal, APUndef;
1045 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1046 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1047 return CFP->getValueAPF().isNegZero();
1052 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1053 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1054 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1055 SelectionDAG &DAG) {
1056 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1057 assert(isSplatShuffleMask(SVOp, EltSize));
1058 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1059 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1061 return SVOp->getMaskElt(0) / EltSize;
1064 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1065 /// by using a vspltis[bhw] instruction of the specified element size, return
1066 /// the constant being splatted. The ByteSize field indicates the number of
1067 /// bytes of each element [124] -> [bhw].
1068 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1069 SDValue OpVal(nullptr, 0);
1071 // If ByteSize of the splat is bigger than the element size of the
1072 // build_vector, then we have a case where we are checking for a splat where
1073 // multiple elements of the buildvector are folded together into a single
1074 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1075 unsigned EltSize = 16/N->getNumOperands();
1076 if (EltSize < ByteSize) {
1077 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1078 SDValue UniquedVals[4];
1079 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1081 // See if all of the elements in the buildvector agree across.
1082 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1083 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1084 // If the element isn't a constant, bail fully out.
1085 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1088 if (!UniquedVals[i&(Multiple-1)].getNode())
1089 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1090 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1091 return SDValue(); // no match.
1094 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1095 // either constant or undef values that are identical for each chunk. See
1096 // if these chunks can form into a larger vspltis*.
1098 // Check to see if all of the leading entries are either 0 or -1. If
1099 // neither, then this won't fit into the immediate field.
1100 bool LeadingZero = true;
1101 bool LeadingOnes = true;
1102 for (unsigned i = 0; i != Multiple-1; ++i) {
1103 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1105 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1106 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1108 // Finally, check the least significant entry.
1110 if (!UniquedVals[Multiple-1].getNode())
1111 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1112 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1114 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1117 if (!UniquedVals[Multiple-1].getNode())
1118 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1119 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1120 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1121 return DAG.getTargetConstant(Val, MVT::i32);
1127 // Check to see if this buildvec has a single non-undef value in its elements.
1128 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1129 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1130 if (!OpVal.getNode())
1131 OpVal = N->getOperand(i);
1132 else if (OpVal != N->getOperand(i))
1136 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1138 unsigned ValSizeInBytes = EltSize;
1140 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1141 Value = CN->getZExtValue();
1142 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1143 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1144 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1147 // If the splat value is larger than the element value, then we can never do
1148 // this splat. The only case that we could fit the replicated bits into our
1149 // immediate field for would be zero, and we prefer to use vxor for it.
1150 if (ValSizeInBytes < ByteSize) return SDValue();
1152 // If the element value is larger than the splat value, cut it in half and
1153 // check to see if the two halves are equal. Continue doing this until we
1154 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1155 while (ValSizeInBytes > ByteSize) {
1156 ValSizeInBytes >>= 1;
1158 // If the top half equals the bottom half, we're still ok.
1159 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1160 (Value & ((1 << (8*ValSizeInBytes))-1)))
1164 // Properly sign extend the value.
1165 int MaskVal = SignExtend32(Value, ByteSize * 8);
1167 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1168 if (MaskVal == 0) return SDValue();
1170 // Finally, if this value fits in a 5 bit sext field, return it
1171 if (SignExtend32<5>(MaskVal) == MaskVal)
1172 return DAG.getTargetConstant(MaskVal, MVT::i32);
1176 //===----------------------------------------------------------------------===//
1177 // Addressing Mode Selection
1178 //===----------------------------------------------------------------------===//
1180 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1181 /// or 64-bit immediate, and if the value can be accurately represented as a
1182 /// sign extension from a 16-bit value. If so, this returns true and the
1184 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1185 if (!isa<ConstantSDNode>(N))
1188 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1189 if (N->getValueType(0) == MVT::i32)
1190 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1192 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1194 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1195 return isIntS16Immediate(Op.getNode(), Imm);
1199 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1200 /// can be represented as an indexed [r+r] operation. Returns false if it
1201 /// can be more efficiently represented with [r+imm].
1202 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1204 SelectionDAG &DAG) const {
1206 if (N.getOpcode() == ISD::ADD) {
1207 if (isIntS16Immediate(N.getOperand(1), imm))
1208 return false; // r+i
1209 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1210 return false; // r+i
1212 Base = N.getOperand(0);
1213 Index = N.getOperand(1);
1215 } else if (N.getOpcode() == ISD::OR) {
1216 if (isIntS16Immediate(N.getOperand(1), imm))
1217 return false; // r+i can fold it if we can.
1219 // If this is an or of disjoint bitfields, we can codegen this as an add
1220 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1222 APInt LHSKnownZero, LHSKnownOne;
1223 APInt RHSKnownZero, RHSKnownOne;
1224 DAG.computeKnownBits(N.getOperand(0),
1225 LHSKnownZero, LHSKnownOne);
1227 if (LHSKnownZero.getBoolValue()) {
1228 DAG.computeKnownBits(N.getOperand(1),
1229 RHSKnownZero, RHSKnownOne);
1230 // If all of the bits are known zero on the LHS or RHS, the add won't
1232 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1233 Base = N.getOperand(0);
1234 Index = N.getOperand(1);
1243 // If we happen to be doing an i64 load or store into a stack slot that has
1244 // less than a 4-byte alignment, then the frame-index elimination may need to
1245 // use an indexed load or store instruction (because the offset may not be a
1246 // multiple of 4). The extra register needed to hold the offset comes from the
1247 // register scavenger, and it is possible that the scavenger will need to use
1248 // an emergency spill slot. As a result, we need to make sure that a spill slot
1249 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1251 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1252 // FIXME: This does not handle the LWA case.
1256 // NOTE: We'll exclude negative FIs here, which come from argument
1257 // lowering, because there are no known test cases triggering this problem
1258 // using packed structures (or similar). We can remove this exclusion if
1259 // we find such a test case. The reason why this is so test-case driven is
1260 // because this entire 'fixup' is only to prevent crashes (from the
1261 // register scavenger) on not-really-valid inputs. For example, if we have:
1263 // %b = bitcast i1* %a to i64*
1264 // store i64* a, i64 b
1265 // then the store should really be marked as 'align 1', but is not. If it
1266 // were marked as 'align 1' then the indexed form would have been
1267 // instruction-selected initially, and the problem this 'fixup' is preventing
1268 // won't happen regardless.
1272 MachineFunction &MF = DAG.getMachineFunction();
1273 MachineFrameInfo *MFI = MF.getFrameInfo();
1275 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1279 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1280 FuncInfo->setHasNonRISpills();
1283 /// Returns true if the address N can be represented by a base register plus
1284 /// a signed 16-bit displacement [r+imm], and if it is not better
1285 /// represented as reg+reg. If Aligned is true, only accept displacements
1286 /// suitable for STD and friends, i.e. multiples of 4.
1287 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1290 bool Aligned) const {
1291 // FIXME dl should come from parent load or store, not from address
1293 // If this can be more profitably realized as r+r, fail.
1294 if (SelectAddressRegReg(N, Disp, Base, DAG))
1297 if (N.getOpcode() == ISD::ADD) {
1299 if (isIntS16Immediate(N.getOperand(1), imm) &&
1300 (!Aligned || (imm & 3) == 0)) {
1301 Disp = DAG.getTargetConstant(imm, N.getValueType());
1302 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1303 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1304 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1306 Base = N.getOperand(0);
1308 return true; // [r+i]
1309 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1310 // Match LOAD (ADD (X, Lo(G))).
1311 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1312 && "Cannot handle constant offsets yet!");
1313 Disp = N.getOperand(1).getOperand(0); // The global address.
1314 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1315 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1316 Disp.getOpcode() == ISD::TargetConstantPool ||
1317 Disp.getOpcode() == ISD::TargetJumpTable);
1318 Base = N.getOperand(0);
1319 return true; // [&g+r]
1321 } else if (N.getOpcode() == ISD::OR) {
1323 if (isIntS16Immediate(N.getOperand(1), imm) &&
1324 (!Aligned || (imm & 3) == 0)) {
1325 // If this is an or of disjoint bitfields, we can codegen this as an add
1326 // (for better address arithmetic) if the LHS and RHS of the OR are
1327 // provably disjoint.
1328 APInt LHSKnownZero, LHSKnownOne;
1329 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1331 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1332 // If all of the bits are known zero on the LHS or RHS, the add won't
1334 Base = N.getOperand(0);
1335 Disp = DAG.getTargetConstant(imm, N.getValueType());
1339 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1340 // Loading from a constant address.
1342 // If this address fits entirely in a 16-bit sext immediate field, codegen
1345 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1346 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1347 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1348 CN->getValueType(0));
1352 // Handle 32-bit sext immediates with LIS + addr mode.
1353 if ((CN->getValueType(0) == MVT::i32 ||
1354 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1355 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1356 int Addr = (int)CN->getZExtValue();
1358 // Otherwise, break this down into an LIS + disp.
1359 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1361 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1362 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1363 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1368 Disp = DAG.getTargetConstant(0, getPointerTy());
1369 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1370 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1371 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1374 return true; // [r+0]
1377 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1378 /// represented as an indexed [r+r] operation.
1379 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1381 SelectionDAG &DAG) const {
1382 // Check to see if we can easily represent this as an [r+r] address. This
1383 // will fail if it thinks that the address is more profitably represented as
1384 // reg+imm, e.g. where imm = 0.
1385 if (SelectAddressRegReg(N, Base, Index, DAG))
1388 // If the operand is an addition, always emit this as [r+r], since this is
1389 // better (for code size, and execution, as the memop does the add for free)
1390 // than emitting an explicit add.
1391 if (N.getOpcode() == ISD::ADD) {
1392 Base = N.getOperand(0);
1393 Index = N.getOperand(1);
1397 // Otherwise, do it the hard way, using R0 as the base register.
1398 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1404 /// getPreIndexedAddressParts - returns true by value, base pointer and
1405 /// offset pointer and addressing mode by reference if the node's address
1406 /// can be legally represented as pre-indexed load / store address.
1407 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1409 ISD::MemIndexedMode &AM,
1410 SelectionDAG &DAG) const {
1411 if (DisablePPCPreinc) return false;
1417 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1418 Ptr = LD->getBasePtr();
1419 VT = LD->getMemoryVT();
1420 Alignment = LD->getAlignment();
1421 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1422 Ptr = ST->getBasePtr();
1423 VT = ST->getMemoryVT();
1424 Alignment = ST->getAlignment();
1429 // PowerPC doesn't have preinc load/store instructions for vectors.
1433 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1435 // Common code will reject creating a pre-inc form if the base pointer
1436 // is a frame index, or if N is a store and the base pointer is either
1437 // the same as or a predecessor of the value being stored. Check for
1438 // those situations here, and try with swapped Base/Offset instead.
1441 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1444 SDValue Val = cast<StoreSDNode>(N)->getValue();
1445 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1450 std::swap(Base, Offset);
1456 // LDU/STU can only handle immediates that are a multiple of 4.
1457 if (VT != MVT::i64) {
1458 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1461 // LDU/STU need an address with at least 4-byte alignment.
1465 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1469 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1470 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1471 // sext i32 to i64 when addr mode is r+i.
1472 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1473 LD->getExtensionType() == ISD::SEXTLOAD &&
1474 isa<ConstantSDNode>(Offset))
1482 //===----------------------------------------------------------------------===//
1483 // LowerOperation implementation
1484 //===----------------------------------------------------------------------===//
1486 /// GetLabelAccessInfo - Return true if we should reference labels using a
1487 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1488 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1489 unsigned &LoOpFlags,
1490 const GlobalValue *GV = nullptr) {
1491 HiOpFlags = PPCII::MO_HA;
1492 LoOpFlags = PPCII::MO_LO;
1494 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1495 // non-darwin platform. We don't support PIC on other platforms yet.
1496 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1497 TM.getSubtarget<PPCSubtarget>().isDarwin();
1499 HiOpFlags |= PPCII::MO_PIC_FLAG;
1500 LoOpFlags |= PPCII::MO_PIC_FLAG;
1503 // If this is a reference to a global value that requires a non-lazy-ptr, make
1504 // sure that instruction lowering adds it.
1505 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1506 HiOpFlags |= PPCII::MO_NLP_FLAG;
1507 LoOpFlags |= PPCII::MO_NLP_FLAG;
1509 if (GV->hasHiddenVisibility()) {
1510 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1511 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1518 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1519 SelectionDAG &DAG) {
1520 EVT PtrVT = HiPart.getValueType();
1521 SDValue Zero = DAG.getConstant(0, PtrVT);
1524 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1525 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1527 // With PIC, the first instruction is actually "GR+hi(&G)".
1529 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1530 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1532 // Generate non-pic code that has direct accesses to the constant pool.
1533 // The address of the global is just (hi(&g)+lo(&g)).
1534 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1537 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1538 SelectionDAG &DAG) const {
1539 EVT PtrVT = Op.getValueType();
1540 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1541 const Constant *C = CP->getConstVal();
1543 // 64-bit SVR4 ABI code is always position-independent.
1544 // The actual address of the GlobalValue is stored in the TOC.
1545 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1546 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1547 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1548 DAG.getRegister(PPC::X2, MVT::i64));
1551 unsigned MOHiFlag, MOLoFlag;
1552 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1554 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1556 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1557 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1560 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1561 EVT PtrVT = Op.getValueType();
1562 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1564 // 64-bit SVR4 ABI code is always position-independent.
1565 // The actual address of the GlobalValue is stored in the TOC.
1566 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1567 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1568 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1569 DAG.getRegister(PPC::X2, MVT::i64));
1572 unsigned MOHiFlag, MOLoFlag;
1573 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1574 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1575 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1576 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1579 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1580 SelectionDAG &DAG) const {
1581 EVT PtrVT = Op.getValueType();
1583 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1585 unsigned MOHiFlag, MOLoFlag;
1586 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1587 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1588 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1589 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1592 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1593 SelectionDAG &DAG) const {
1595 // FIXME: TLS addresses currently use medium model code sequences,
1596 // which is the most useful form. Eventually support for small and
1597 // large models could be added if users need it, at the cost of
1598 // additional complexity.
1599 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1601 const GlobalValue *GV = GA->getGlobal();
1602 EVT PtrVT = getPointerTy();
1603 bool is64bit = Subtarget.isPPC64();
1605 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1607 if (Model == TLSModel::LocalExec) {
1608 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1609 PPCII::MO_TPREL_HA);
1610 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1611 PPCII::MO_TPREL_LO);
1612 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1613 is64bit ? MVT::i64 : MVT::i32);
1614 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1615 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1618 if (Model == TLSModel::InitialExec) {
1619 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1620 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1624 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1625 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1626 PtrVT, GOTReg, TGA);
1628 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1629 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1630 PtrVT, TGA, GOTPtr);
1631 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1634 if (Model == TLSModel::GeneralDynamic) {
1635 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1636 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1637 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1639 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1642 // We need a chain node, and don't have one handy. The underlying
1643 // call has no side effects, so using the function entry node
1645 SDValue Chain = DAG.getEntryNode();
1646 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1647 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1648 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1649 PtrVT, ParmReg, TGA);
1650 // The return value from GET_TLS_ADDR really is in X3 already, but
1651 // some hacks are needed here to tie everything together. The extra
1652 // copies dissolve during subsequent transforms.
1653 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1654 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1657 if (Model == TLSModel::LocalDynamic) {
1658 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1659 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1660 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1662 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1665 // We need a chain node, and don't have one handy. The underlying
1666 // call has no side effects, so using the function entry node
1668 SDValue Chain = DAG.getEntryNode();
1669 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1670 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1671 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1672 PtrVT, ParmReg, TGA);
1673 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1674 // some hacks are needed here to tie everything together. The extra
1675 // copies dissolve during subsequent transforms.
1676 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1677 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1678 Chain, ParmReg, TGA);
1679 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1682 llvm_unreachable("Unknown TLS model!");
1685 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1686 SelectionDAG &DAG) const {
1687 EVT PtrVT = Op.getValueType();
1688 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1690 const GlobalValue *GV = GSDN->getGlobal();
1692 // 64-bit SVR4 ABI code is always position-independent.
1693 // The actual address of the GlobalValue is stored in the TOC.
1694 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1695 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1696 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1697 DAG.getRegister(PPC::X2, MVT::i64));
1700 unsigned MOHiFlag, MOLoFlag;
1701 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1704 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1706 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1708 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1710 // If the global reference is actually to a non-lazy-pointer, we have to do an
1711 // extra load to get the address of the global.
1712 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1713 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1714 false, false, false, 0);
1718 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1719 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1722 if (Op.getValueType() == MVT::v2i64) {
1723 // When the operands themselves are v2i64 values, we need to do something
1724 // special because VSX has no underlying comparison operations for these.
1725 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1726 // Equality can be handled by casting to the legal type for Altivec
1727 // comparisons, everything else needs to be expanded.
1728 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1729 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1730 DAG.getSetCC(dl, MVT::v4i32,
1731 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1732 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1739 // We handle most of these in the usual way.
1743 // If we're comparing for equality to zero, expose the fact that this is
1744 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1745 // fold the new nodes.
1746 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1747 if (C->isNullValue() && CC == ISD::SETEQ) {
1748 EVT VT = Op.getOperand(0).getValueType();
1749 SDValue Zext = Op.getOperand(0);
1750 if (VT.bitsLT(MVT::i32)) {
1752 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1754 unsigned Log2b = Log2_32(VT.getSizeInBits());
1755 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1756 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1757 DAG.getConstant(Log2b, MVT::i32));
1758 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1760 // Leave comparisons against 0 and -1 alone for now, since they're usually
1761 // optimized. FIXME: revisit this when we can custom lower all setcc
1763 if (C->isAllOnesValue() || C->isNullValue())
1767 // If we have an integer seteq/setne, turn it into a compare against zero
1768 // by xor'ing the rhs with the lhs, which is faster than setting a
1769 // condition register, reading it back out, and masking the correct bit. The
1770 // normal approach here uses sub to do this instead of xor. Using xor exposes
1771 // the result to other bit-twiddling opportunities.
1772 EVT LHSVT = Op.getOperand(0).getValueType();
1773 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1774 EVT VT = Op.getValueType();
1775 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1777 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1782 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1783 const PPCSubtarget &Subtarget) const {
1784 SDNode *Node = Op.getNode();
1785 EVT VT = Node->getValueType(0);
1786 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1787 SDValue InChain = Node->getOperand(0);
1788 SDValue VAListPtr = Node->getOperand(1);
1789 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1792 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1795 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1796 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1798 InChain = GprIndex.getValue(1);
1800 if (VT == MVT::i64) {
1801 // Check if GprIndex is even
1802 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1803 DAG.getConstant(1, MVT::i32));
1804 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1805 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1806 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1807 DAG.getConstant(1, MVT::i32));
1808 // Align GprIndex to be even if it isn't
1809 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1813 // fpr index is 1 byte after gpr
1814 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1815 DAG.getConstant(1, MVT::i32));
1818 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1819 FprPtr, MachinePointerInfo(SV), MVT::i8,
1821 InChain = FprIndex.getValue(1);
1823 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1824 DAG.getConstant(8, MVT::i32));
1826 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1827 DAG.getConstant(4, MVT::i32));
1830 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1831 MachinePointerInfo(), false, false,
1833 InChain = OverflowArea.getValue(1);
1835 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1836 MachinePointerInfo(), false, false,
1838 InChain = RegSaveArea.getValue(1);
1840 // select overflow_area if index > 8
1841 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1842 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1844 // adjustment constant gpr_index * 4/8
1845 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1846 VT.isInteger() ? GprIndex : FprIndex,
1847 DAG.getConstant(VT.isInteger() ? 4 : 8,
1850 // OurReg = RegSaveArea + RegConstant
1851 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1854 // Floating types are 32 bytes into RegSaveArea
1855 if (VT.isFloatingPoint())
1856 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1857 DAG.getConstant(32, MVT::i32));
1859 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1860 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1861 VT.isInteger() ? GprIndex : FprIndex,
1862 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1865 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1866 VT.isInteger() ? VAListPtr : FprPtr,
1867 MachinePointerInfo(SV),
1868 MVT::i8, false, false, 0);
1870 // determine if we should load from reg_save_area or overflow_area
1871 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1873 // increase overflow_area by 4/8 if gpr/fpr > 8
1874 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1875 DAG.getConstant(VT.isInteger() ? 4 : 8,
1878 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1881 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1883 MachinePointerInfo(),
1884 MVT::i32, false, false, 0);
1886 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1887 false, false, false, 0);
1890 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1891 const PPCSubtarget &Subtarget) const {
1892 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1894 // We have to copy the entire va_list struct:
1895 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1896 return DAG.getMemcpy(Op.getOperand(0), Op,
1897 Op.getOperand(1), Op.getOperand(2),
1898 DAG.getConstant(12, MVT::i32), 8, false, true,
1899 MachinePointerInfo(), MachinePointerInfo());
1902 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1903 SelectionDAG &DAG) const {
1904 return Op.getOperand(0);
1907 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1908 SelectionDAG &DAG) const {
1909 SDValue Chain = Op.getOperand(0);
1910 SDValue Trmp = Op.getOperand(1); // trampoline
1911 SDValue FPtr = Op.getOperand(2); // nested function
1912 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1915 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1916 bool isPPC64 = (PtrVT == MVT::i64);
1918 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1921 TargetLowering::ArgListTy Args;
1922 TargetLowering::ArgListEntry Entry;
1924 Entry.Ty = IntPtrTy;
1925 Entry.Node = Trmp; Args.push_back(Entry);
1927 // TrampSize == (isPPC64 ? 48 : 40);
1928 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1929 isPPC64 ? MVT::i64 : MVT::i32);
1930 Args.push_back(Entry);
1932 Entry.Node = FPtr; Args.push_back(Entry);
1933 Entry.Node = Nest; Args.push_back(Entry);
1935 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1936 TargetLowering::CallLoweringInfo CLI(DAG);
1937 CLI.setDebugLoc(dl).setChain(Chain)
1938 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
1939 DAG.getExternalSymbol("__trampoline_setup", PtrVT), &Args, 0);
1941 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1942 return CallResult.second;
1945 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1946 const PPCSubtarget &Subtarget) const {
1947 MachineFunction &MF = DAG.getMachineFunction();
1948 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1952 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1953 // vastart just stores the address of the VarArgsFrameIndex slot into the
1954 // memory location argument.
1955 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1956 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1957 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1958 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1959 MachinePointerInfo(SV),
1963 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1964 // We suppose the given va_list is already allocated.
1967 // char gpr; /* index into the array of 8 GPRs
1968 // * stored in the register save area
1969 // * gpr=0 corresponds to r3,
1970 // * gpr=1 to r4, etc.
1972 // char fpr; /* index into the array of 8 FPRs
1973 // * stored in the register save area
1974 // * fpr=0 corresponds to f1,
1975 // * fpr=1 to f2, etc.
1977 // char *overflow_arg_area;
1978 // /* location on stack that holds
1979 // * the next overflow argument
1981 // char *reg_save_area;
1982 // /* where r3:r10 and f1:f8 (if saved)
1988 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1989 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1992 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1994 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1996 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1999 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2000 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2002 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2003 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2005 uint64_t FPROffset = 1;
2006 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2008 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2010 // Store first byte : number of int regs
2011 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2013 MachinePointerInfo(SV),
2014 MVT::i8, false, false, 0);
2015 uint64_t nextOffset = FPROffset;
2016 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2019 // Store second byte : number of float regs
2020 SDValue secondStore =
2021 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2022 MachinePointerInfo(SV, nextOffset), MVT::i8,
2024 nextOffset += StackOffset;
2025 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2027 // Store second word : arguments given on stack
2028 SDValue thirdStore =
2029 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2030 MachinePointerInfo(SV, nextOffset),
2032 nextOffset += FrameOffset;
2033 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2035 // Store third word : arguments given in registers
2036 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2037 MachinePointerInfo(SV, nextOffset),
2042 #include "PPCGenCallingConv.inc"
2044 // Function whose sole purpose is to kill compiler warnings
2045 // stemming from unused functions included from PPCGenCallingConv.inc.
2046 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2047 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2050 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2051 CCValAssign::LocInfo &LocInfo,
2052 ISD::ArgFlagsTy &ArgFlags,
2057 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2059 CCValAssign::LocInfo &LocInfo,
2060 ISD::ArgFlagsTy &ArgFlags,
2062 static const MCPhysReg ArgRegs[] = {
2063 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2064 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2066 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2068 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2070 // Skip one register if the first unallocated register has an even register
2071 // number and there are still argument registers available which have not been
2072 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2073 // need to skip a register if RegNum is odd.
2074 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2075 State.AllocateReg(ArgRegs[RegNum]);
2078 // Always return false here, as this function only makes sure that the first
2079 // unallocated register has an odd register number and does not actually
2080 // allocate a register for the current argument.
2084 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2086 CCValAssign::LocInfo &LocInfo,
2087 ISD::ArgFlagsTy &ArgFlags,
2089 static const MCPhysReg ArgRegs[] = {
2090 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2094 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2096 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2098 // If there is only one Floating-point register left we need to put both f64
2099 // values of a split ppc_fp128 value on the stack.
2100 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2101 State.AllocateReg(ArgRegs[RegNum]);
2104 // Always return false here, as this function only makes sure that the two f64
2105 // values a ppc_fp128 value is split into are both passed in registers or both
2106 // passed on the stack and does not actually allocate a register for the
2107 // current argument.
2111 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2113 static const MCPhysReg *GetFPR() {
2114 static const MCPhysReg FPR[] = {
2115 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2116 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2122 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2124 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2125 unsigned PtrByteSize) {
2126 unsigned ArgSize = ArgVT.getStoreSize();
2127 if (Flags.isByVal())
2128 ArgSize = Flags.getByValSize();
2129 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2133 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2134 /// ensure minimum alignment required for target.
2135 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2136 unsigned NumBytes) {
2137 unsigned TargetAlign = Target.getFrameLowering()->getStackAlignment();
2138 unsigned AlignMask = TargetAlign - 1;
2139 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2144 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2145 CallingConv::ID CallConv, bool isVarArg,
2146 const SmallVectorImpl<ISD::InputArg>
2148 SDLoc dl, SelectionDAG &DAG,
2149 SmallVectorImpl<SDValue> &InVals)
2151 if (Subtarget.isSVR4ABI()) {
2152 if (Subtarget.isPPC64())
2153 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2156 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2159 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2165 PPCTargetLowering::LowerFormalArguments_32SVR4(
2167 CallingConv::ID CallConv, bool isVarArg,
2168 const SmallVectorImpl<ISD::InputArg>
2170 SDLoc dl, SelectionDAG &DAG,
2171 SmallVectorImpl<SDValue> &InVals) const {
2173 // 32-bit SVR4 ABI Stack Frame Layout:
2174 // +-----------------------------------+
2175 // +--> | Back chain |
2176 // | +-----------------------------------+
2177 // | | Floating-point register save area |
2178 // | +-----------------------------------+
2179 // | | General register save area |
2180 // | +-----------------------------------+
2181 // | | CR save word |
2182 // | +-----------------------------------+
2183 // | | VRSAVE save word |
2184 // | +-----------------------------------+
2185 // | | Alignment padding |
2186 // | +-----------------------------------+
2187 // | | Vector register save area |
2188 // | +-----------------------------------+
2189 // | | Local variable space |
2190 // | +-----------------------------------+
2191 // | | Parameter list area |
2192 // | +-----------------------------------+
2193 // | | LR save word |
2194 // | +-----------------------------------+
2195 // SP--> +--- | Back chain |
2196 // +-----------------------------------+
2199 // System V Application Binary Interface PowerPC Processor Supplement
2200 // AltiVec Technology Programming Interface Manual
2202 MachineFunction &MF = DAG.getMachineFunction();
2203 MachineFrameInfo *MFI = MF.getFrameInfo();
2204 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2206 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2207 // Potential tail calls could cause overwriting of argument stack slots.
2208 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2209 (CallConv == CallingConv::Fast));
2210 unsigned PtrByteSize = 4;
2212 // Assign locations to all of the incoming arguments.
2213 SmallVector<CCValAssign, 16> ArgLocs;
2214 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2215 getTargetMachine(), ArgLocs, *DAG.getContext());
2217 // Reserve space for the linkage area on the stack.
2218 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false);
2219 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2221 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2223 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2224 CCValAssign &VA = ArgLocs[i];
2226 // Arguments stored in registers.
2227 if (VA.isRegLoc()) {
2228 const TargetRegisterClass *RC;
2229 EVT ValVT = VA.getValVT();
2231 switch (ValVT.getSimpleVT().SimpleTy) {
2233 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2236 RC = &PPC::GPRCRegClass;
2239 RC = &PPC::F4RCRegClass;
2242 if (Subtarget.hasVSX())
2243 RC = &PPC::VSFRCRegClass;
2245 RC = &PPC::F8RCRegClass;
2251 RC = &PPC::VRRCRegClass;
2255 RC = &PPC::VSHRCRegClass;
2259 // Transform the arguments stored in physical registers into virtual ones.
2260 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2261 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2262 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2264 if (ValVT == MVT::i1)
2265 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2267 InVals.push_back(ArgValue);
2269 // Argument stored in memory.
2270 assert(VA.isMemLoc());
2272 unsigned ArgSize = VA.getLocVT().getStoreSize();
2273 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2276 // Create load nodes to retrieve arguments from the stack.
2277 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2278 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2279 MachinePointerInfo(),
2280 false, false, false, 0));
2284 // Assign locations to all of the incoming aggregate by value arguments.
2285 // Aggregates passed by value are stored in the local variable space of the
2286 // caller's stack frame, right above the parameter list area.
2287 SmallVector<CCValAssign, 16> ByValArgLocs;
2288 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2289 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2291 // Reserve stack space for the allocations in CCInfo.
2292 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2294 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2296 // Area that is at least reserved in the caller of this function.
2297 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2298 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2300 // Set the size that is at least reserved in caller of this function. Tail
2301 // call optimized function's reserved stack space needs to be aligned so that
2302 // taking the difference between two stack areas will result in an aligned
2304 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2305 FuncInfo->setMinReservedArea(MinReservedArea);
2307 SmallVector<SDValue, 8> MemOps;
2309 // If the function takes variable number of arguments, make a frame index for
2310 // the start of the first vararg value... for expansion of llvm.va_start.
2312 static const MCPhysReg GPArgRegs[] = {
2313 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2314 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2316 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2318 static const MCPhysReg FPArgRegs[] = {
2319 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2322 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2324 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2326 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2329 // Make room for NumGPArgRegs and NumFPArgRegs.
2330 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2331 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2333 FuncInfo->setVarArgsStackOffset(
2334 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2335 CCInfo.getNextStackOffset(), true));
2337 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2338 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2340 // The fixed integer arguments of a variadic function are stored to the
2341 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2342 // the result of va_next.
2343 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2344 // Get an existing live-in vreg, or add a new one.
2345 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2347 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2349 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2350 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2351 MachinePointerInfo(), false, false, 0);
2352 MemOps.push_back(Store);
2353 // Increment the address by four for the next argument to store
2354 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2355 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2358 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2360 // The double arguments are stored to the VarArgsFrameIndex
2362 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2363 // Get an existing live-in vreg, or add a new one.
2364 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2366 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2368 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2369 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2370 MachinePointerInfo(), false, false, 0);
2371 MemOps.push_back(Store);
2372 // Increment the address by eight for the next argument to store
2373 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2375 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2379 if (!MemOps.empty())
2380 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2385 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2386 // value to MVT::i64 and then truncate to the correct register size.
2388 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2389 SelectionDAG &DAG, SDValue ArgVal,
2392 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2393 DAG.getValueType(ObjectVT));
2394 else if (Flags.isZExt())
2395 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2396 DAG.getValueType(ObjectVT));
2398 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2402 PPCTargetLowering::LowerFormalArguments_64SVR4(
2404 CallingConv::ID CallConv, bool isVarArg,
2405 const SmallVectorImpl<ISD::InputArg>
2407 SDLoc dl, SelectionDAG &DAG,
2408 SmallVectorImpl<SDValue> &InVals) const {
2409 // TODO: add description of PPC stack frame format, or at least some docs.
2411 bool isLittleEndian = Subtarget.isLittleEndian();
2412 MachineFunction &MF = DAG.getMachineFunction();
2413 MachineFrameInfo *MFI = MF.getFrameInfo();
2414 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2416 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2417 // Potential tail calls could cause overwriting of argument stack slots.
2418 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2419 (CallConv == CallingConv::Fast));
2420 unsigned PtrByteSize = 8;
2422 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false);
2423 unsigned ArgOffset = LinkageSize;
2424 // Area that is at least reserved in caller of this function.
2425 unsigned MinReservedArea = ArgOffset;
2427 static const MCPhysReg GPR[] = {
2428 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2429 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2432 static const MCPhysReg *FPR = GetFPR();
2434 static const MCPhysReg VR[] = {
2435 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2436 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2438 static const MCPhysReg VSRH[] = {
2439 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2440 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2443 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2444 const unsigned Num_FPR_Regs = 13;
2445 const unsigned Num_VR_Regs = array_lengthof(VR);
2447 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2449 // Add DAG nodes to load the arguments or copy them out of registers. On
2450 // entry to a function on PPC, the arguments start after the linkage area,
2451 // although the first ones are often in registers.
2453 SmallVector<SDValue, 8> MemOps;
2454 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2455 unsigned CurArgIdx = 0;
2456 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2458 bool needsLoad = false;
2459 EVT ObjectVT = Ins[ArgNo].VT;
2460 unsigned ObjSize = ObjectVT.getStoreSize();
2461 unsigned ArgSize = ObjSize;
2462 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2463 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2464 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2466 unsigned CurArgOffset = ArgOffset;
2468 // Altivec parameters are padded to a 16 byte boundary.
2469 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2470 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8 ||
2471 ObjectVT==MVT::v2f64 || ObjectVT==MVT::v2i64)
2472 MinReservedArea = ((MinReservedArea+15)/16)*16;
2474 // Calculate min reserved area.
2475 MinReservedArea += CalculateStackSlotSize(ObjectVT, Flags, PtrByteSize);
2477 // FIXME the codegen can be much improved in some cases.
2478 // We do not have to keep everything in memory.
2479 if (Flags.isByVal()) {
2480 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2481 ObjSize = Flags.getByValSize();
2482 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2483 // Empty aggregate parameters do not take up registers. Examples:
2487 // etc. However, we have to provide a place-holder in InVals, so
2488 // pretend we have an 8-byte item at the current address for that
2491 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2492 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2493 InVals.push_back(FIN);
2497 unsigned BVAlign = Flags.getByValAlign();
2499 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
2500 CurArgOffset = ArgOffset;
2503 // All aggregates smaller than 8 bytes must be passed right-justified.
2504 if (ObjSize < PtrByteSize && !isLittleEndian)
2505 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2506 // The value of the object is its address.
2507 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2508 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2509 InVals.push_back(FIN);
2512 if (GPR_idx != Num_GPR_Regs) {
2513 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2514 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2517 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2518 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2519 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2520 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2521 MachinePointerInfo(FuncArg),
2522 ObjType, false, false, 0);
2524 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2525 // store the whole register as-is to the parameter save area
2526 // slot. The address of the parameter was already calculated
2527 // above (InVals.push_back(FIN)) to be the right-justified
2528 // offset within the slot. For this store, we need a new
2529 // frame index that points at the beginning of the slot.
2530 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2531 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2532 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2533 MachinePointerInfo(FuncArg),
2537 MemOps.push_back(Store);
2540 // Whether we copied from a register or not, advance the offset
2541 // into the parameter save area by a full doubleword.
2542 ArgOffset += PtrByteSize;
2546 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2547 // Store whatever pieces of the object are in registers
2548 // to memory. ArgOffset will be the address of the beginning
2550 if (GPR_idx != Num_GPR_Regs) {
2552 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2553 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2554 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2555 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2556 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2557 MachinePointerInfo(FuncArg, j),
2559 MemOps.push_back(Store);
2561 ArgOffset += PtrByteSize;
2563 ArgOffset += ArgSize - j;
2570 switch (ObjectVT.getSimpleVT().SimpleTy) {
2571 default: llvm_unreachable("Unhandled argument type!");
2575 if (GPR_idx != Num_GPR_Regs) {
2576 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2577 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2579 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2580 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2581 // value to MVT::i64 and then truncate to the correct register size.
2582 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2587 ArgSize = PtrByteSize;
2594 // Every 8 bytes of argument space consumes one of the GPRs available for
2595 // argument passing.
2596 if (GPR_idx != Num_GPR_Regs) {
2599 if (FPR_idx != Num_FPR_Regs) {
2602 if (ObjectVT == MVT::f32)
2603 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2605 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2606 &PPC::VSFRCRegClass :
2607 &PPC::F8RCRegClass);
2609 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2613 ArgSize = PtrByteSize;
2624 // Vectors are aligned to a 16-byte boundary in the argument save area.
2625 while ((ArgOffset % 16) != 0) {
2626 ArgOffset += PtrByteSize;
2627 if (GPR_idx != Num_GPR_Regs)
2630 if (VR_idx != Num_VR_Regs) {
2631 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2632 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2633 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2634 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2637 CurArgOffset = ArgOffset;
2641 GPR_idx = std::min(GPR_idx + 2, Num_GPR_Regs);
2645 // We need to load the argument to a virtual register if we determined
2646 // above that we ran out of physical registers of the appropriate type.
2648 if (ObjSize < ArgSize && !isLittleEndian)
2649 CurArgOffset += ArgSize - ObjSize;
2650 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2651 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2652 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2653 false, false, false, 0);
2656 InVals.push_back(ArgVal);
2659 // Area that is at least reserved in the caller of this function.
2660 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
2662 // Set the size that is at least reserved in caller of this function. Tail
2663 // call optimized functions' reserved stack space needs to be aligned so that
2664 // taking the difference between two stack areas will result in an aligned
2666 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2667 FuncInfo->setMinReservedArea(MinReservedArea);
2669 // If the function takes variable number of arguments, make a frame index for
2670 // the start of the first vararg value... for expansion of llvm.va_start.
2672 int Depth = ArgOffset;
2674 FuncInfo->setVarArgsFrameIndex(
2675 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2676 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2678 // If this function is vararg, store any remaining integer argument regs
2679 // to their spots on the stack so that they may be loaded by deferencing the
2680 // result of va_next.
2681 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2682 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2683 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2684 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2685 MachinePointerInfo(), false, false, 0);
2686 MemOps.push_back(Store);
2687 // Increment the address by four for the next argument to store
2688 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2689 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2693 if (!MemOps.empty())
2694 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2700 PPCTargetLowering::LowerFormalArguments_Darwin(
2702 CallingConv::ID CallConv, bool isVarArg,
2703 const SmallVectorImpl<ISD::InputArg>
2705 SDLoc dl, SelectionDAG &DAG,
2706 SmallVectorImpl<SDValue> &InVals) const {
2707 // TODO: add description of PPC stack frame format, or at least some docs.
2709 MachineFunction &MF = DAG.getMachineFunction();
2710 MachineFrameInfo *MFI = MF.getFrameInfo();
2711 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2713 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2714 bool isPPC64 = PtrVT == MVT::i64;
2715 // Potential tail calls could cause overwriting of argument stack slots.
2716 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2717 (CallConv == CallingConv::Fast));
2718 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2720 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true);
2721 unsigned ArgOffset = LinkageSize;
2722 // Area that is at least reserved in caller of this function.
2723 unsigned MinReservedArea = ArgOffset;
2725 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2726 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2727 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2729 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2730 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2731 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2734 static const MCPhysReg *FPR = GetFPR();
2736 static const MCPhysReg VR[] = {
2737 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2738 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2741 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2742 const unsigned Num_FPR_Regs = 13;
2743 const unsigned Num_VR_Regs = array_lengthof( VR);
2745 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2747 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2749 // In 32-bit non-varargs functions, the stack space for vectors is after the
2750 // stack space for non-vectors. We do not use this space unless we have
2751 // too many vectors to fit in registers, something that only occurs in
2752 // constructed examples:), but we have to walk the arglist to figure
2753 // that out...for the pathological case, compute VecArgOffset as the
2754 // start of the vector parameter area. Computing VecArgOffset is the
2755 // entire point of the following loop.
2756 unsigned VecArgOffset = ArgOffset;
2757 if (!isVarArg && !isPPC64) {
2758 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2760 EVT ObjectVT = Ins[ArgNo].VT;
2761 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2763 if (Flags.isByVal()) {
2764 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2765 unsigned ObjSize = Flags.getByValSize();
2767 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2768 VecArgOffset += ArgSize;
2772 switch(ObjectVT.getSimpleVT().SimpleTy) {
2773 default: llvm_unreachable("Unhandled argument type!");
2779 case MVT::i64: // PPC64
2781 // FIXME: We are guaranteed to be !isPPC64 at this point.
2782 // Does MVT::i64 apply?
2789 // Nothing to do, we're only looking at Nonvector args here.
2794 // We've found where the vector parameter area in memory is. Skip the
2795 // first 12 parameters; these don't use that memory.
2796 VecArgOffset = ((VecArgOffset+15)/16)*16;
2797 VecArgOffset += 12*16;
2799 // Add DAG nodes to load the arguments or copy them out of registers. On
2800 // entry to a function on PPC, the arguments start after the linkage area,
2801 // although the first ones are often in registers.
2803 SmallVector<SDValue, 8> MemOps;
2804 unsigned nAltivecParamsAtEnd = 0;
2805 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2806 unsigned CurArgIdx = 0;
2807 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2809 bool needsLoad = false;
2810 EVT ObjectVT = Ins[ArgNo].VT;
2811 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2812 unsigned ArgSize = ObjSize;
2813 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2814 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2815 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2817 unsigned CurArgOffset = ArgOffset;
2819 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2820 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2821 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2822 if (isVarArg || isPPC64) {
2823 MinReservedArea = ((MinReservedArea+15)/16)*16;
2824 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2827 } else nAltivecParamsAtEnd++;
2829 // Calculate min reserved area.
2830 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2834 // FIXME the codegen can be much improved in some cases.
2835 // We do not have to keep everything in memory.
2836 if (Flags.isByVal()) {
2837 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2838 ObjSize = Flags.getByValSize();
2839 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2840 // Objects of size 1 and 2 are right justified, everything else is
2841 // left justified. This means the memory address is adjusted forwards.
2842 if (ObjSize==1 || ObjSize==2) {
2843 CurArgOffset = CurArgOffset + (4 - ObjSize);
2845 // The value of the object is its address.
2846 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2847 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2848 InVals.push_back(FIN);
2849 if (ObjSize==1 || ObjSize==2) {
2850 if (GPR_idx != Num_GPR_Regs) {
2853 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2855 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2856 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2857 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2858 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2859 MachinePointerInfo(FuncArg),
2860 ObjType, false, false, 0);
2861 MemOps.push_back(Store);
2865 ArgOffset += PtrByteSize;
2869 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2870 // Store whatever pieces of the object are in registers
2871 // to memory. ArgOffset will be the address of the beginning
2873 if (GPR_idx != Num_GPR_Regs) {
2876 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2878 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2879 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2880 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2881 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2882 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2883 MachinePointerInfo(FuncArg, j),
2885 MemOps.push_back(Store);
2887 ArgOffset += PtrByteSize;
2889 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2896 switch (ObjectVT.getSimpleVT().SimpleTy) {
2897 default: llvm_unreachable("Unhandled argument type!");
2901 if (GPR_idx != Num_GPR_Regs) {
2902 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2903 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2905 if (ObjectVT == MVT::i1)
2906 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
2911 ArgSize = PtrByteSize;
2913 // All int arguments reserve stack space in the Darwin ABI.
2914 ArgOffset += PtrByteSize;
2918 case MVT::i64: // PPC64
2919 if (GPR_idx != Num_GPR_Regs) {
2920 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2921 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2923 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2924 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2925 // value to MVT::i64 and then truncate to the correct register size.
2926 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2931 ArgSize = PtrByteSize;
2933 // All int arguments reserve stack space in the Darwin ABI.
2939 // Every 4 bytes of argument space consumes one of the GPRs available for
2940 // argument passing.
2941 if (GPR_idx != Num_GPR_Regs) {
2943 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2946 if (FPR_idx != Num_FPR_Regs) {
2949 if (ObjectVT == MVT::f32)
2950 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2952 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2954 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2960 // All FP arguments reserve stack space in the Darwin ABI.
2961 ArgOffset += isPPC64 ? 8 : ObjSize;
2967 // Note that vector arguments in registers don't reserve stack space,
2968 // except in varargs functions.
2969 if (VR_idx != Num_VR_Regs) {
2970 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2971 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2973 while ((ArgOffset % 16) != 0) {
2974 ArgOffset += PtrByteSize;
2975 if (GPR_idx != Num_GPR_Regs)
2979 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2983 if (!isVarArg && !isPPC64) {
2984 // Vectors go after all the nonvectors.
2985 CurArgOffset = VecArgOffset;
2988 // Vectors are aligned.
2989 ArgOffset = ((ArgOffset+15)/16)*16;
2990 CurArgOffset = ArgOffset;
2998 // We need to load the argument to a virtual register if we determined above
2999 // that we ran out of physical registers of the appropriate type.
3001 int FI = MFI->CreateFixedObject(ObjSize,
3002 CurArgOffset + (ArgSize - ObjSize),
3004 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3005 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3006 false, false, false, 0);
3009 InVals.push_back(ArgVal);
3012 // Allow for Altivec parameters at the end, if needed.
3013 if (nAltivecParamsAtEnd) {
3014 MinReservedArea = ((MinReservedArea+15)/16)*16;
3015 MinReservedArea += 16*nAltivecParamsAtEnd;
3018 // Area that is at least reserved in the caller of this function.
3019 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3021 // Set the size that is at least reserved in caller of this function. Tail
3022 // call optimized functions' reserved stack space needs to be aligned so that
3023 // taking the difference between two stack areas will result in an aligned
3025 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3026 FuncInfo->setMinReservedArea(MinReservedArea);
3028 // If the function takes variable number of arguments, make a frame index for
3029 // the start of the first vararg value... for expansion of llvm.va_start.
3031 int Depth = ArgOffset;
3033 FuncInfo->setVarArgsFrameIndex(
3034 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3036 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3038 // If this function is vararg, store any remaining integer argument regs
3039 // to their spots on the stack so that they may be loaded by deferencing the
3040 // result of va_next.
3041 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3045 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3047 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3049 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3050 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3051 MachinePointerInfo(), false, false, 0);
3052 MemOps.push_back(Store);
3053 // Increment the address by four for the next argument to store
3054 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3055 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3059 if (!MemOps.empty())
3060 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3065 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3066 /// adjusted to accommodate the arguments for the tailcall.
3067 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3068 unsigned ParamSize) {
3070 if (!isTailCall) return 0;
3072 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3073 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3074 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3075 // Remember only if the new adjustement is bigger.
3076 if (SPDiff < FI->getTailCallSPDelta())
3077 FI->setTailCallSPDelta(SPDiff);
3082 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3083 /// for tail call optimization. Targets which want to do tail call
3084 /// optimization should implement this function.
3086 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3087 CallingConv::ID CalleeCC,
3089 const SmallVectorImpl<ISD::InputArg> &Ins,
3090 SelectionDAG& DAG) const {
3091 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3094 // Variable argument functions are not supported.
3098 MachineFunction &MF = DAG.getMachineFunction();
3099 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3100 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3101 // Functions containing by val parameters are not supported.
3102 for (unsigned i = 0; i != Ins.size(); i++) {
3103 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3104 if (Flags.isByVal()) return false;
3107 // Non-PIC/GOT tail calls are supported.
3108 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3111 // At the moment we can only do local tail calls (in same module, hidden
3112 // or protected) if we are generating PIC.
3113 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3114 return G->getGlobal()->hasHiddenVisibility()
3115 || G->getGlobal()->hasProtectedVisibility();
3121 /// isCallCompatibleAddress - Return the immediate to use if the specified
3122 /// 32-bit value is representable in the immediate field of a BxA instruction.
3123 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3124 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3125 if (!C) return nullptr;
3127 int Addr = C->getZExtValue();
3128 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3129 SignExtend32<26>(Addr) != Addr)
3130 return nullptr; // Top 6 bits have to be sext of immediate.
3132 return DAG.getConstant((int)C->getZExtValue() >> 2,
3133 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3138 struct TailCallArgumentInfo {
3143 TailCallArgumentInfo() : FrameIdx(0) {}
3148 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3150 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3152 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3153 SmallVectorImpl<SDValue> &MemOpChains,
3155 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3156 SDValue Arg = TailCallArgs[i].Arg;
3157 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3158 int FI = TailCallArgs[i].FrameIdx;
3159 // Store relative to framepointer.
3160 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3161 MachinePointerInfo::getFixedStack(FI),
3166 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3167 /// the appropriate stack slot for the tail call optimized function call.
3168 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3169 MachineFunction &MF,
3178 // Calculate the new stack slot for the return address.
3179 int SlotSize = isPPC64 ? 8 : 4;
3180 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3182 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3183 NewRetAddrLoc, true);
3184 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3185 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3186 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3187 MachinePointerInfo::getFixedStack(NewRetAddr),
3190 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3191 // slot as the FP is never overwritten.
3194 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3195 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3197 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3198 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3199 MachinePointerInfo::getFixedStack(NewFPIdx),
3206 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3207 /// the position of the argument.
3209 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3210 SDValue Arg, int SPDiff, unsigned ArgOffset,
3211 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3212 int Offset = ArgOffset + SPDiff;
3213 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3214 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3215 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3216 SDValue FIN = DAG.getFrameIndex(FI, VT);
3217 TailCallArgumentInfo Info;
3219 Info.FrameIdxOp = FIN;
3221 TailCallArguments.push_back(Info);
3224 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3225 /// stack slot. Returns the chain as result and the loaded frame pointers in
3226 /// LROpOut/FPOpout. Used when tail calling.
3227 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3235 // Load the LR and FP stack slot for later adjusting.
3236 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3237 LROpOut = getReturnAddrFrameIndex(DAG);
3238 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3239 false, false, false, 0);
3240 Chain = SDValue(LROpOut.getNode(), 1);
3242 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3243 // slot as the FP is never overwritten.
3245 FPOpOut = getFramePointerFrameIndex(DAG);
3246 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3247 false, false, false, 0);
3248 Chain = SDValue(FPOpOut.getNode(), 1);
3254 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3255 /// by "Src" to address "Dst" of size "Size". Alignment information is
3256 /// specified by the specific parameter attribute. The copy will be passed as
3257 /// a byval function parameter.
3258 /// Sometimes what we are copying is the end of a larger object, the part that
3259 /// does not fit in registers.
3261 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3262 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3264 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3265 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3266 false, false, MachinePointerInfo(),
3267 MachinePointerInfo());
3270 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3273 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3274 SDValue Arg, SDValue PtrOff, int SPDiff,
3275 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3276 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3277 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3279 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3284 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3286 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3287 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3288 DAG.getConstant(ArgOffset, PtrVT));
3290 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3291 MachinePointerInfo(), false, false, 0));
3292 // Calculate and remember argument location.
3293 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3298 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3299 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3300 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3301 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3302 MachineFunction &MF = DAG.getMachineFunction();
3304 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3305 // might overwrite each other in case of tail call optimization.
3306 SmallVector<SDValue, 8> MemOpChains2;
3307 // Do not flag preceding copytoreg stuff together with the following stuff.
3309 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3311 if (!MemOpChains2.empty())
3312 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3314 // Store the return address to the appropriate stack slot.
3315 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3316 isPPC64, isDarwinABI, dl);
3318 // Emit callseq_end just before tailcall node.
3319 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3320 DAG.getIntPtrConstant(0, true), InFlag, dl);
3321 InFlag = Chain.getValue(1);
3325 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3326 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3327 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3328 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3329 const PPCSubtarget &Subtarget) {
3331 bool isPPC64 = Subtarget.isPPC64();
3332 bool isSVR4ABI = Subtarget.isSVR4ABI();
3334 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3335 NodeTys.push_back(MVT::Other); // Returns a chain
3336 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3338 unsigned CallOpc = PPCISD::CALL;
3340 bool needIndirectCall = true;
3341 if (!isSVR4ABI || !isPPC64)
3342 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3343 // If this is an absolute destination address, use the munged value.
3344 Callee = SDValue(Dest, 0);
3345 needIndirectCall = false;
3348 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3349 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3350 // Use indirect calls for ALL functions calls in JIT mode, since the
3351 // far-call stubs may be outside relocation limits for a BL instruction.
3352 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3353 unsigned OpFlags = 0;
3354 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3355 (Subtarget.getTargetTriple().isMacOSX() &&
3356 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3357 (G->getGlobal()->isDeclaration() ||
3358 G->getGlobal()->isWeakForLinker())) {
3359 // PC-relative references to external symbols should go through $stub,
3360 // unless we're building with the leopard linker or later, which
3361 // automatically synthesizes these stubs.
3362 OpFlags = PPCII::MO_DARWIN_STUB;
3365 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3366 // every direct call is) turn it into a TargetGlobalAddress /
3367 // TargetExternalSymbol node so that legalize doesn't hack it.
3368 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3369 Callee.getValueType(),
3371 needIndirectCall = false;
3375 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3376 unsigned char OpFlags = 0;
3378 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3379 (Subtarget.getTargetTriple().isMacOSX() &&
3380 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3381 // PC-relative references to external symbols should go through $stub,
3382 // unless we're building with the leopard linker or later, which
3383 // automatically synthesizes these stubs.
3384 OpFlags = PPCII::MO_DARWIN_STUB;
3387 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3389 needIndirectCall = false;
3392 if (needIndirectCall) {
3393 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3394 // to do the call, we can't use PPCISD::CALL.
3395 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3397 if (isSVR4ABI && isPPC64) {
3398 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3399 // entry point, but to the function descriptor (the function entry point
3400 // address is part of the function descriptor though).
3401 // The function descriptor is a three doubleword structure with the
3402 // following fields: function entry point, TOC base address and
3403 // environment pointer.
3404 // Thus for a call through a function pointer, the following actions need
3406 // 1. Save the TOC of the caller in the TOC save area of its stack
3407 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3408 // 2. Load the address of the function entry point from the function
3410 // 3. Load the TOC of the callee from the function descriptor into r2.
3411 // 4. Load the environment pointer from the function descriptor into
3413 // 5. Branch to the function entry point address.
3414 // 6. On return of the callee, the TOC of the caller needs to be
3415 // restored (this is done in FinishCall()).
3417 // All those operations are flagged together to ensure that no other
3418 // operations can be scheduled in between. E.g. without flagging the
3419 // operations together, a TOC access in the caller could be scheduled
3420 // between the load of the callee TOC and the branch to the callee, which
3421 // results in the TOC access going through the TOC of the callee instead
3422 // of going through the TOC of the caller, which leads to incorrect code.
3424 // Load the address of the function entry point from the function
3426 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3427 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3428 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3429 Chain = LoadFuncPtr.getValue(1);
3430 InFlag = LoadFuncPtr.getValue(2);
3432 // Load environment pointer into r11.
3433 // Offset of the environment pointer within the function descriptor.
3434 SDValue PtrOff = DAG.getIntPtrConstant(16);
3436 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3437 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3439 Chain = LoadEnvPtr.getValue(1);
3440 InFlag = LoadEnvPtr.getValue(2);
3442 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3444 Chain = EnvVal.getValue(0);
3445 InFlag = EnvVal.getValue(1);
3447 // Load TOC of the callee into r2. We are using a target-specific load
3448 // with r2 hard coded, because the result of a target-independent load
3449 // would never go directly into r2, since r2 is a reserved register (which
3450 // prevents the register allocator from allocating it), resulting in an
3451 // additional register being allocated and an unnecessary move instruction
3453 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3454 SDValue TOCOff = DAG.getIntPtrConstant(8);
3455 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3456 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3458 Chain = LoadTOCPtr.getValue(0);
3459 InFlag = LoadTOCPtr.getValue(1);
3461 MTCTROps[0] = Chain;
3462 MTCTROps[1] = LoadFuncPtr;
3463 MTCTROps[2] = InFlag;
3466 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3467 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3468 InFlag = Chain.getValue(1);
3471 NodeTys.push_back(MVT::Other);
3472 NodeTys.push_back(MVT::Glue);
3473 Ops.push_back(Chain);
3474 CallOpc = PPCISD::BCTRL;
3475 Callee.setNode(nullptr);
3476 // Add use of X11 (holding environment pointer)
3477 if (isSVR4ABI && isPPC64)
3478 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3479 // Add CTR register as callee so a bctr can be emitted later.
3481 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3484 // If this is a direct call, pass the chain and the callee.
3485 if (Callee.getNode()) {
3486 Ops.push_back(Chain);
3487 Ops.push_back(Callee);
3489 // If this is a tail call add stack pointer delta.
3491 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3493 // Add argument registers to the end of the list so that they are known live
3495 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3496 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3497 RegsToPass[i].second.getValueType()));
3503 bool isLocalCall(const SDValue &Callee)
3505 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3506 return !G->getGlobal()->isDeclaration() &&
3507 !G->getGlobal()->isWeakForLinker();
3512 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3513 CallingConv::ID CallConv, bool isVarArg,
3514 const SmallVectorImpl<ISD::InputArg> &Ins,
3515 SDLoc dl, SelectionDAG &DAG,
3516 SmallVectorImpl<SDValue> &InVals) const {
3518 SmallVector<CCValAssign, 16> RVLocs;
3519 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3520 getTargetMachine(), RVLocs, *DAG.getContext());
3521 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3523 // Copy all of the result registers out of their specified physreg.
3524 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3525 CCValAssign &VA = RVLocs[i];
3526 assert(VA.isRegLoc() && "Can only return in registers!");
3528 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3529 VA.getLocReg(), VA.getLocVT(), InFlag);
3530 Chain = Val.getValue(1);
3531 InFlag = Val.getValue(2);
3533 switch (VA.getLocInfo()) {
3534 default: llvm_unreachable("Unknown loc info!");
3535 case CCValAssign::Full: break;
3536 case CCValAssign::AExt:
3537 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3539 case CCValAssign::ZExt:
3540 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3541 DAG.getValueType(VA.getValVT()));
3542 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3544 case CCValAssign::SExt:
3545 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3546 DAG.getValueType(VA.getValVT()));
3547 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3551 InVals.push_back(Val);
3558 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3559 bool isTailCall, bool isVarArg,
3561 SmallVector<std::pair<unsigned, SDValue>, 8>
3563 SDValue InFlag, SDValue Chain,
3565 int SPDiff, unsigned NumBytes,
3566 const SmallVectorImpl<ISD::InputArg> &Ins,
3567 SmallVectorImpl<SDValue> &InVals) const {
3568 std::vector<EVT> NodeTys;
3569 SmallVector<SDValue, 8> Ops;
3570 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3571 isTailCall, RegsToPass, Ops, NodeTys,
3574 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3575 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3576 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3578 // When performing tail call optimization the callee pops its arguments off
3579 // the stack. Account for this here so these bytes can be pushed back on in
3580 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3581 int BytesCalleePops =
3582 (CallConv == CallingConv::Fast &&
3583 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3585 // Add a register mask operand representing the call-preserved registers.
3586 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3587 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3588 assert(Mask && "Missing call preserved mask for calling convention");
3589 Ops.push_back(DAG.getRegisterMask(Mask));
3591 if (InFlag.getNode())
3592 Ops.push_back(InFlag);
3596 assert(((Callee.getOpcode() == ISD::Register &&
3597 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3598 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3599 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3600 isa<ConstantSDNode>(Callee)) &&
3601 "Expecting an global address, external symbol, absolute value or register");
3603 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3606 // Add a NOP immediately after the branch instruction when using the 64-bit
3607 // SVR4 ABI. At link time, if caller and callee are in a different module and
3608 // thus have a different TOC, the call will be replaced with a call to a stub
3609 // function which saves the current TOC, loads the TOC of the callee and
3610 // branches to the callee. The NOP will be replaced with a load instruction
3611 // which restores the TOC of the caller from the TOC save slot of the current
3612 // stack frame. If caller and callee belong to the same module (and have the
3613 // same TOC), the NOP will remain unchanged.
3615 bool needsTOCRestore = false;
3616 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3617 if (CallOpc == PPCISD::BCTRL) {
3618 // This is a call through a function pointer.
3619 // Restore the caller TOC from the save area into R2.
3620 // See PrepareCall() for more information about calls through function
3621 // pointers in the 64-bit SVR4 ABI.
3622 // We are using a target-specific load with r2 hard coded, because the
3623 // result of a target-independent load would never go directly into r2,
3624 // since r2 is a reserved register (which prevents the register allocator
3625 // from allocating it), resulting in an additional register being
3626 // allocated and an unnecessary move instruction being generated.
3627 needsTOCRestore = true;
3628 } else if ((CallOpc == PPCISD::CALL) &&
3629 (!isLocalCall(Callee) ||
3630 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3631 // Otherwise insert NOP for non-local calls.
3632 CallOpc = PPCISD::CALL_NOP;
3636 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3637 InFlag = Chain.getValue(1);
3639 if (needsTOCRestore) {
3640 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3641 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3642 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3643 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset();
3644 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3645 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3646 Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag);
3647 InFlag = Chain.getValue(1);
3650 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3651 DAG.getIntPtrConstant(BytesCalleePops, true),
3654 InFlag = Chain.getValue(1);
3656 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3657 Ins, dl, DAG, InVals);
3661 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3662 SmallVectorImpl<SDValue> &InVals) const {
3663 SelectionDAG &DAG = CLI.DAG;
3665 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3666 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3667 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3668 SDValue Chain = CLI.Chain;
3669 SDValue Callee = CLI.Callee;
3670 bool &isTailCall = CLI.IsTailCall;
3671 CallingConv::ID CallConv = CLI.CallConv;
3672 bool isVarArg = CLI.IsVarArg;
3675 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3678 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3679 report_fatal_error("failed to perform tail call elimination on a call "
3680 "site marked musttail");
3682 if (Subtarget.isSVR4ABI()) {
3683 if (Subtarget.isPPC64())
3684 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3685 isTailCall, Outs, OutVals, Ins,
3688 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3689 isTailCall, Outs, OutVals, Ins,
3693 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3694 isTailCall, Outs, OutVals, Ins,
3699 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3700 CallingConv::ID CallConv, bool isVarArg,
3702 const SmallVectorImpl<ISD::OutputArg> &Outs,
3703 const SmallVectorImpl<SDValue> &OutVals,
3704 const SmallVectorImpl<ISD::InputArg> &Ins,
3705 SDLoc dl, SelectionDAG &DAG,
3706 SmallVectorImpl<SDValue> &InVals) const {
3707 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3708 // of the 32-bit SVR4 ABI stack frame layout.
3710 assert((CallConv == CallingConv::C ||
3711 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3713 unsigned PtrByteSize = 4;
3715 MachineFunction &MF = DAG.getMachineFunction();
3717 // Mark this function as potentially containing a function that contains a
3718 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3719 // and restoring the callers stack pointer in this functions epilog. This is
3720 // done because by tail calling the called function might overwrite the value
3721 // in this function's (MF) stack pointer stack slot 0(SP).
3722 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3723 CallConv == CallingConv::Fast)
3724 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3726 // Count how many bytes are to be pushed on the stack, including the linkage
3727 // area, parameter list area and the part of the local variable space which
3728 // contains copies of aggregates which are passed by value.
3730 // Assign locations to all of the outgoing arguments.
3731 SmallVector<CCValAssign, 16> ArgLocs;
3732 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3733 getTargetMachine(), ArgLocs, *DAG.getContext());
3735 // Reserve space for the linkage area on the stack.
3736 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3739 // Handle fixed and variable vector arguments differently.
3740 // Fixed vector arguments go into registers as long as registers are
3741 // available. Variable vector arguments always go into memory.
3742 unsigned NumArgs = Outs.size();
3744 for (unsigned i = 0; i != NumArgs; ++i) {
3745 MVT ArgVT = Outs[i].VT;
3746 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3749 if (Outs[i].IsFixed) {
3750 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3753 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3759 errs() << "Call operand #" << i << " has unhandled type "
3760 << EVT(ArgVT).getEVTString() << "\n";
3762 llvm_unreachable(nullptr);
3766 // All arguments are treated the same.
3767 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3770 // Assign locations to all of the outgoing aggregate by value arguments.
3771 SmallVector<CCValAssign, 16> ByValArgLocs;
3772 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3773 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3775 // Reserve stack space for the allocations in CCInfo.
3776 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3778 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3780 // Size of the linkage area, parameter list area and the part of the local
3781 // space variable where copies of aggregates which are passed by value are
3783 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3785 // Calculate by how many bytes the stack has to be adjusted in case of tail
3786 // call optimization.
3787 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3789 // Adjust the stack pointer for the new arguments...
3790 // These operations are automatically eliminated by the prolog/epilog pass
3791 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3793 SDValue CallSeqStart = Chain;
3795 // Load the return address and frame pointer so it can be moved somewhere else
3798 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3801 // Set up a copy of the stack pointer for use loading and storing any
3802 // arguments that may not fit in the registers available for argument
3804 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3806 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3807 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3808 SmallVector<SDValue, 8> MemOpChains;
3810 bool seenFloatArg = false;
3811 // Walk the register/memloc assignments, inserting copies/loads.
3812 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3815 CCValAssign &VA = ArgLocs[i];
3816 SDValue Arg = OutVals[i];
3817 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3819 if (Flags.isByVal()) {
3820 // Argument is an aggregate which is passed by value, thus we need to
3821 // create a copy of it in the local variable space of the current stack
3822 // frame (which is the stack frame of the caller) and pass the address of
3823 // this copy to the callee.
3824 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3825 CCValAssign &ByValVA = ByValArgLocs[j++];
3826 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3828 // Memory reserved in the local variable space of the callers stack frame.
3829 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3831 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3832 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3834 // Create a copy of the argument in the local area of the current
3836 SDValue MemcpyCall =
3837 CreateCopyOfByValArgument(Arg, PtrOff,
3838 CallSeqStart.getNode()->getOperand(0),
3841 // This must go outside the CALLSEQ_START..END.
3842 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3843 CallSeqStart.getNode()->getOperand(1),
3845 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3846 NewCallSeqStart.getNode());
3847 Chain = CallSeqStart = NewCallSeqStart;
3849 // Pass the address of the aggregate copy on the stack either in a
3850 // physical register or in the parameter list area of the current stack
3851 // frame to the callee.
3855 if (VA.isRegLoc()) {
3856 if (Arg.getValueType() == MVT::i1)
3857 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
3859 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3860 // Put argument in a physical register.
3861 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3863 // Put argument in the parameter list area of the current stack frame.
3864 assert(VA.isMemLoc());
3865 unsigned LocMemOffset = VA.getLocMemOffset();
3868 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3869 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3871 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3872 MachinePointerInfo(),
3875 // Calculate and remember argument location.
3876 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3882 if (!MemOpChains.empty())
3883 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3885 // Build a sequence of copy-to-reg nodes chained together with token chain
3886 // and flag operands which copy the outgoing args into the appropriate regs.
3888 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3889 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3890 RegsToPass[i].second, InFlag);
3891 InFlag = Chain.getValue(1);
3894 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3897 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3898 SDValue Ops[] = { Chain, InFlag };
3900 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3901 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
3903 InFlag = Chain.getValue(1);
3907 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3908 false, TailCallArguments);
3910 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3911 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3915 // Copy an argument into memory, being careful to do this outside the
3916 // call sequence for the call to which the argument belongs.
3918 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3919 SDValue CallSeqStart,
3920 ISD::ArgFlagsTy Flags,
3923 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3924 CallSeqStart.getNode()->getOperand(0),
3926 // The MEMCPY must go outside the CALLSEQ_START..END.
3927 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3928 CallSeqStart.getNode()->getOperand(1),
3930 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3931 NewCallSeqStart.getNode());
3932 return NewCallSeqStart;
3936 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3937 CallingConv::ID CallConv, bool isVarArg,
3939 const SmallVectorImpl<ISD::OutputArg> &Outs,
3940 const SmallVectorImpl<SDValue> &OutVals,
3941 const SmallVectorImpl<ISD::InputArg> &Ins,
3942 SDLoc dl, SelectionDAG &DAG,
3943 SmallVectorImpl<SDValue> &InVals) const {
3945 bool isLittleEndian = Subtarget.isLittleEndian();
3946 unsigned NumOps = Outs.size();
3948 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3949 unsigned PtrByteSize = 8;
3951 MachineFunction &MF = DAG.getMachineFunction();
3953 // Mark this function as potentially containing a function that contains a
3954 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3955 // and restoring the callers stack pointer in this functions epilog. This is
3956 // done because by tail calling the called function might overwrite the value
3957 // in this function's (MF) stack pointer stack slot 0(SP).
3958 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3959 CallConv == CallingConv::Fast)
3960 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3962 // Count how many bytes are to be pushed on the stack, including the linkage
3963 // area, and parameter passing area. We start with at least 48 bytes, which
3964 // is reserved space for [SP][CR][LR][3 x unused].
3965 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false);
3966 unsigned NumBytes = LinkageSize;
3968 // Add up all the space actually used.
3969 for (unsigned i = 0; i != NumOps; ++i) {
3970 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3971 EVT ArgVT = Outs[i].VT;
3973 // Altivec parameters are padded to a 16 byte boundary.
3974 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
3975 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
3976 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
3977 NumBytes = ((NumBytes+15)/16)*16;
3979 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3982 // The prolog code of the callee may store up to 8 GPR argument registers to
3983 // the stack, allowing va_start to index over them in memory if its varargs.
3984 // Because we cannot tell if this is needed on the caller side, we have to
3985 // conservatively assume that it is needed. As such, make sure we have at
3986 // least enough stack space for the caller to store the 8 GPRs.
3987 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
3989 // Tail call needs the stack to be aligned.
3990 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3991 CallConv == CallingConv::Fast)
3992 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
3994 // Calculate by how many bytes the stack has to be adjusted in case of tail
3995 // call optimization.
3996 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3998 // To protect arguments on the stack from being clobbered in a tail call,
3999 // force all the loads to happen before doing any other lowering.
4001 Chain = DAG.getStackArgumentTokenFactor(Chain);
4003 // Adjust the stack pointer for the new arguments...
4004 // These operations are automatically eliminated by the prolog/epilog pass
4005 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4007 SDValue CallSeqStart = Chain;
4009 // Load the return address and frame pointer so it can be move somewhere else
4012 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4015 // Set up a copy of the stack pointer for use loading and storing any
4016 // arguments that may not fit in the registers available for argument
4018 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4020 // Figure out which arguments are going to go in registers, and which in
4021 // memory. Also, if this is a vararg function, floating point operations
4022 // must be stored to our stack, and loaded into integer regs as well, if
4023 // any integer regs are available for argument passing.
4024 unsigned ArgOffset = LinkageSize;
4025 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4027 static const MCPhysReg GPR[] = {
4028 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4029 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4031 static const MCPhysReg *FPR = GetFPR();
4033 static const MCPhysReg VR[] = {
4034 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4035 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4037 static const MCPhysReg VSRH[] = {
4038 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4039 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4042 const unsigned NumGPRs = array_lengthof(GPR);
4043 const unsigned NumFPRs = 13;
4044 const unsigned NumVRs = array_lengthof(VR);
4046 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4047 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4049 SmallVector<SDValue, 8> MemOpChains;
4050 for (unsigned i = 0; i != NumOps; ++i) {
4051 SDValue Arg = OutVals[i];
4052 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4054 // PtrOff will be used to store the current argument to the stack if a
4055 // register cannot be found for it.
4058 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4060 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4062 // Promote integers to 64-bit values.
4063 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4064 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4065 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4066 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4069 // FIXME memcpy is used way more than necessary. Correctness first.
4070 // Note: "by value" is code for passing a structure by value, not
4072 if (Flags.isByVal()) {
4073 // Note: Size includes alignment padding, so
4074 // struct x { short a; char b; }
4075 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4076 // These are the proper values we need for right-justifying the
4077 // aggregate in a parameter register.
4078 unsigned Size = Flags.getByValSize();
4080 // An empty aggregate parameter takes up no storage and no
4085 unsigned BVAlign = Flags.getByValAlign();
4087 if (BVAlign % PtrByteSize != 0)
4089 "ByVal alignment is not a multiple of the pointer size");
4091 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
4094 // All aggregates smaller than 8 bytes must be passed right-justified.
4095 if (Size==1 || Size==2 || Size==4) {
4096 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4097 if (GPR_idx != NumGPRs) {
4098 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4099 MachinePointerInfo(), VT,
4101 MemOpChains.push_back(Load.getValue(1));
4102 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4104 ArgOffset += PtrByteSize;
4109 if (GPR_idx == NumGPRs && Size < 8) {
4110 SDValue AddPtr = PtrOff;
4111 if (!isLittleEndian) {
4112 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4113 PtrOff.getValueType());
4114 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4116 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4119 ArgOffset += PtrByteSize;
4122 // Copy entire object into memory. There are cases where gcc-generated
4123 // code assumes it is there, even if it could be put entirely into
4124 // registers. (This is not what the doc says.)
4126 // FIXME: The above statement is likely due to a misunderstanding of the
4127 // documents. All arguments must be copied into the parameter area BY
4128 // THE CALLEE in the event that the callee takes the address of any
4129 // formal argument. That has not yet been implemented. However, it is
4130 // reasonable to use the stack area as a staging area for the register
4133 // Skip this for small aggregates, as we will use the same slot for a
4134 // right-justified copy, below.
4136 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4140 // When a register is available, pass a small aggregate right-justified.
4141 if (Size < 8 && GPR_idx != NumGPRs) {
4142 // The easiest way to get this right-justified in a register
4143 // is to copy the structure into the rightmost portion of a
4144 // local variable slot, then load the whole slot into the
4146 // FIXME: The memcpy seems to produce pretty awful code for
4147 // small aggregates, particularly for packed ones.
4148 // FIXME: It would be preferable to use the slot in the
4149 // parameter save area instead of a new local variable.
4150 SDValue AddPtr = PtrOff;
4151 if (!isLittleEndian) {
4152 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4153 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4155 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4159 // Load the slot into the register.
4160 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4161 MachinePointerInfo(),
4162 false, false, false, 0);
4163 MemOpChains.push_back(Load.getValue(1));
4164 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4166 // Done with this argument.
4167 ArgOffset += PtrByteSize;
4171 // For aggregates larger than PtrByteSize, copy the pieces of the
4172 // object that fit into registers from the parameter save area.
4173 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4174 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4175 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4176 if (GPR_idx != NumGPRs) {
4177 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4178 MachinePointerInfo(),
4179 false, false, false, 0);
4180 MemOpChains.push_back(Load.getValue(1));
4181 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4182 ArgOffset += PtrByteSize;
4184 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4191 switch (Arg.getSimpleValueType().SimpleTy) {
4192 default: llvm_unreachable("Unexpected ValueType for argument!");
4196 if (GPR_idx != NumGPRs) {
4197 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4199 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4200 true, isTailCall, false, MemOpChains,
4201 TailCallArguments, dl);
4203 ArgOffset += PtrByteSize;
4207 if (FPR_idx != NumFPRs) {
4208 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4211 // A single float or an aggregate containing only a single float
4212 // must be passed right-justified in the stack doubleword, and
4213 // in the GPR, if one is available.
4215 if (Arg.getSimpleValueType().SimpleTy == MVT::f32 &&
4217 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4218 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4222 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
4223 MachinePointerInfo(), false, false, 0);
4224 MemOpChains.push_back(Store);
4226 // Float varargs are always shadowed in available integer registers
4227 if (GPR_idx != NumGPRs) {
4228 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4229 MachinePointerInfo(), false, false,
4231 MemOpChains.push_back(Load.getValue(1));
4232 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4234 } else if (GPR_idx != NumGPRs)
4235 // If we have any FPRs remaining, we may also have GPRs remaining.
4238 // Single-precision floating-point values are mapped to the
4239 // second (rightmost) word of the stack doubleword.
4240 if (Arg.getValueType() == MVT::f32 && !isLittleEndian) {
4241 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4242 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4245 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4246 true, isTailCall, false, MemOpChains,
4247 TailCallArguments, dl);
4257 // Vectors are aligned to a 16-byte boundary in the argument save area.
4258 while (ArgOffset % 16 !=0) {
4259 ArgOffset += PtrByteSize;
4260 if (GPR_idx != NumGPRs)
4264 // For a varargs call, named arguments go into VRs or on the stack as
4265 // usual; unnamed arguments always go to the stack or the corresponding
4266 // GPRs when within range. For now, we always put the value in both
4267 // locations (or even all three).
4269 // We could elide this store in the case where the object fits
4270 // entirely in R registers. Maybe later.
4271 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4272 DAG.getConstant(ArgOffset, PtrVT));
4273 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4274 MachinePointerInfo(), false, false, 0);
4275 MemOpChains.push_back(Store);
4276 if (VR_idx != NumVRs) {
4277 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4278 MachinePointerInfo(),
4279 false, false, false, 0);
4280 MemOpChains.push_back(Load.getValue(1));
4282 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4283 Arg.getSimpleValueType() == MVT::v2i64) ?
4284 VSRH[VR_idx] : VR[VR_idx];
4287 RegsToPass.push_back(std::make_pair(VReg, Load));
4290 for (unsigned i=0; i<16; i+=PtrByteSize) {
4291 if (GPR_idx == NumGPRs)
4293 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4294 DAG.getConstant(i, PtrVT));
4295 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4296 false, false, false, 0);
4297 MemOpChains.push_back(Load.getValue(1));
4298 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4303 // Non-varargs Altivec params go into VRs or on the stack.
4304 if (VR_idx != NumVRs) {
4305 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4306 Arg.getSimpleValueType() == MVT::v2i64) ?
4307 VSRH[VR_idx] : VR[VR_idx];
4310 RegsToPass.push_back(std::make_pair(VReg, Arg));
4312 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4313 true, isTailCall, true, MemOpChains,
4314 TailCallArguments, dl);
4317 GPR_idx = std::min(GPR_idx + 2, NumGPRs);
4322 if (!MemOpChains.empty())
4323 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4325 // Check if this is an indirect call (MTCTR/BCTRL).
4326 // See PrepareCall() for more information about calls through function
4327 // pointers in the 64-bit SVR4 ABI.
4329 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4330 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4331 // Load r2 into a virtual register and store it to the TOC save area.
4332 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4333 // TOC save area offset.
4334 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset();
4335 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4336 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4337 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4341 // Build a sequence of copy-to-reg nodes chained together with token chain
4342 // and flag operands which copy the outgoing args into the appropriate regs.
4344 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4345 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4346 RegsToPass[i].second, InFlag);
4347 InFlag = Chain.getValue(1);
4351 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4352 FPOp, true, TailCallArguments);
4354 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4355 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4360 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4361 CallingConv::ID CallConv, bool isVarArg,
4363 const SmallVectorImpl<ISD::OutputArg> &Outs,
4364 const SmallVectorImpl<SDValue> &OutVals,
4365 const SmallVectorImpl<ISD::InputArg> &Ins,
4366 SDLoc dl, SelectionDAG &DAG,
4367 SmallVectorImpl<SDValue> &InVals) const {
4369 unsigned NumOps = Outs.size();
4371 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4372 bool isPPC64 = PtrVT == MVT::i64;
4373 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4375 MachineFunction &MF = DAG.getMachineFunction();
4377 // Mark this function as potentially containing a function that contains a
4378 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4379 // and restoring the callers stack pointer in this functions epilog. This is
4380 // done because by tail calling the called function might overwrite the value
4381 // in this function's (MF) stack pointer stack slot 0(SP).
4382 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4383 CallConv == CallingConv::Fast)
4384 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4386 // Count how many bytes are to be pushed on the stack, including the linkage
4387 // area, and parameter passing area. We start with 24/48 bytes, which is
4388 // prereserved space for [SP][CR][LR][3 x unused].
4389 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true);
4390 unsigned NumBytes = LinkageSize;
4392 // Add up all the space actually used.
4393 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4394 // they all go in registers, but we must reserve stack space for them for
4395 // possible use by the caller. In varargs or 64-bit calls, parameters are
4396 // assigned stack space in order, with padding so Altivec parameters are
4398 unsigned nAltivecParamsAtEnd = 0;
4399 for (unsigned i = 0; i != NumOps; ++i) {
4400 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4401 EVT ArgVT = Outs[i].VT;
4402 // Varargs Altivec parameters are padded to a 16 byte boundary.
4403 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4404 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4405 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4406 if (!isVarArg && !isPPC64) {
4407 // Non-varargs Altivec parameters go after all the non-Altivec
4408 // parameters; handle those later so we know how much padding we need.
4409 nAltivecParamsAtEnd++;
4412 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4413 NumBytes = ((NumBytes+15)/16)*16;
4415 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4418 // Allow for Altivec parameters at the end, if needed.
4419 if (nAltivecParamsAtEnd) {
4420 NumBytes = ((NumBytes+15)/16)*16;
4421 NumBytes += 16*nAltivecParamsAtEnd;
4424 // The prolog code of the callee may store up to 8 GPR argument registers to
4425 // the stack, allowing va_start to index over them in memory if its varargs.
4426 // Because we cannot tell if this is needed on the caller side, we have to
4427 // conservatively assume that it is needed. As such, make sure we have at
4428 // least enough stack space for the caller to store the 8 GPRs.
4429 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4431 // Tail call needs the stack to be aligned.
4432 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4433 CallConv == CallingConv::Fast)
4434 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4436 // Calculate by how many bytes the stack has to be adjusted in case of tail
4437 // call optimization.
4438 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4440 // To protect arguments on the stack from being clobbered in a tail call,
4441 // force all the loads to happen before doing any other lowering.
4443 Chain = DAG.getStackArgumentTokenFactor(Chain);
4445 // Adjust the stack pointer for the new arguments...
4446 // These operations are automatically eliminated by the prolog/epilog pass
4447 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4449 SDValue CallSeqStart = Chain;
4451 // Load the return address and frame pointer so it can be move somewhere else
4454 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4457 // Set up a copy of the stack pointer for use loading and storing any
4458 // arguments that may not fit in the registers available for argument
4462 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4464 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4466 // Figure out which arguments are going to go in registers, and which in
4467 // memory. Also, if this is a vararg function, floating point operations
4468 // must be stored to our stack, and loaded into integer regs as well, if
4469 // any integer regs are available for argument passing.
4470 unsigned ArgOffset = LinkageSize;
4471 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4473 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4474 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4475 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4477 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4478 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4479 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4481 static const MCPhysReg *FPR = GetFPR();
4483 static const MCPhysReg VR[] = {
4484 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4485 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4487 const unsigned NumGPRs = array_lengthof(GPR_32);
4488 const unsigned NumFPRs = 13;
4489 const unsigned NumVRs = array_lengthof(VR);
4491 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4493 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4494 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4496 SmallVector<SDValue, 8> MemOpChains;
4497 for (unsigned i = 0; i != NumOps; ++i) {
4498 SDValue Arg = OutVals[i];
4499 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4501 // PtrOff will be used to store the current argument to the stack if a
4502 // register cannot be found for it.
4505 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4507 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4509 // On PPC64, promote integers to 64-bit values.
4510 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4511 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4512 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4513 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4516 // FIXME memcpy is used way more than necessary. Correctness first.
4517 // Note: "by value" is code for passing a structure by value, not
4519 if (Flags.isByVal()) {
4520 unsigned Size = Flags.getByValSize();
4521 // Very small objects are passed right-justified. Everything else is
4522 // passed left-justified.
4523 if (Size==1 || Size==2) {
4524 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4525 if (GPR_idx != NumGPRs) {
4526 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4527 MachinePointerInfo(), VT,
4529 MemOpChains.push_back(Load.getValue(1));
4530 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4532 ArgOffset += PtrByteSize;
4534 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4535 PtrOff.getValueType());
4536 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4537 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4540 ArgOffset += PtrByteSize;
4544 // Copy entire object into memory. There are cases where gcc-generated
4545 // code assumes it is there, even if it could be put entirely into
4546 // registers. (This is not what the doc says.)
4547 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4551 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4552 // copy the pieces of the object that fit into registers from the
4553 // parameter save area.
4554 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4555 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4556 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4557 if (GPR_idx != NumGPRs) {
4558 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4559 MachinePointerInfo(),
4560 false, false, false, 0);
4561 MemOpChains.push_back(Load.getValue(1));
4562 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4563 ArgOffset += PtrByteSize;
4565 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4572 switch (Arg.getSimpleValueType().SimpleTy) {
4573 default: llvm_unreachable("Unexpected ValueType for argument!");
4577 if (GPR_idx != NumGPRs) {
4578 if (Arg.getValueType() == MVT::i1)
4579 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4581 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4583 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4584 isPPC64, isTailCall, false, MemOpChains,
4585 TailCallArguments, dl);
4587 ArgOffset += PtrByteSize;
4591 if (FPR_idx != NumFPRs) {
4592 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4595 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4596 MachinePointerInfo(), false, false, 0);
4597 MemOpChains.push_back(Store);
4599 // Float varargs are always shadowed in available integer registers
4600 if (GPR_idx != NumGPRs) {
4601 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4602 MachinePointerInfo(), false, false,
4604 MemOpChains.push_back(Load.getValue(1));
4605 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4607 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4608 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4609 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4610 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4611 MachinePointerInfo(),
4612 false, false, false, 0);
4613 MemOpChains.push_back(Load.getValue(1));
4614 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4617 // If we have any FPRs remaining, we may also have GPRs remaining.
4618 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4620 if (GPR_idx != NumGPRs)
4622 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4623 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4627 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4628 isPPC64, isTailCall, false, MemOpChains,
4629 TailCallArguments, dl);
4633 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4640 // These go aligned on the stack, or in the corresponding R registers
4641 // when within range. The Darwin PPC ABI doc claims they also go in
4642 // V registers; in fact gcc does this only for arguments that are
4643 // prototyped, not for those that match the ... We do it for all
4644 // arguments, seems to work.
4645 while (ArgOffset % 16 !=0) {
4646 ArgOffset += PtrByteSize;
4647 if (GPR_idx != NumGPRs)
4650 // We could elide this store in the case where the object fits
4651 // entirely in R registers. Maybe later.
4652 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4653 DAG.getConstant(ArgOffset, PtrVT));
4654 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4655 MachinePointerInfo(), false, false, 0);
4656 MemOpChains.push_back(Store);
4657 if (VR_idx != NumVRs) {
4658 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4659 MachinePointerInfo(),
4660 false, false, false, 0);
4661 MemOpChains.push_back(Load.getValue(1));
4662 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4665 for (unsigned i=0; i<16; i+=PtrByteSize) {
4666 if (GPR_idx == NumGPRs)
4668 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4669 DAG.getConstant(i, PtrVT));
4670 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4671 false, false, false, 0);
4672 MemOpChains.push_back(Load.getValue(1));
4673 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4678 // Non-varargs Altivec params generally go in registers, but have
4679 // stack space allocated at the end.
4680 if (VR_idx != NumVRs) {
4681 // Doesn't have GPR space allocated.
4682 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4683 } else if (nAltivecParamsAtEnd==0) {
4684 // We are emitting Altivec params in order.
4685 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4686 isPPC64, isTailCall, true, MemOpChains,
4687 TailCallArguments, dl);
4693 // If all Altivec parameters fit in registers, as they usually do,
4694 // they get stack space following the non-Altivec parameters. We
4695 // don't track this here because nobody below needs it.
4696 // If there are more Altivec parameters than fit in registers emit
4698 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4700 // Offset is aligned; skip 1st 12 params which go in V registers.
4701 ArgOffset = ((ArgOffset+15)/16)*16;
4703 for (unsigned i = 0; i != NumOps; ++i) {
4704 SDValue Arg = OutVals[i];
4705 EVT ArgType = Outs[i].VT;
4706 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4707 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4710 // We are emitting Altivec params in order.
4711 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4712 isPPC64, isTailCall, true, MemOpChains,
4713 TailCallArguments, dl);
4720 if (!MemOpChains.empty())
4721 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4723 // On Darwin, R12 must contain the address of an indirect callee. This does
4724 // not mean the MTCTR instruction must use R12; it's easier to model this as
4725 // an extra parameter, so do that.
4727 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4728 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4729 !isBLACompatibleAddress(Callee, DAG))
4730 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4731 PPC::R12), Callee));
4733 // Build a sequence of copy-to-reg nodes chained together with token chain
4734 // and flag operands which copy the outgoing args into the appropriate regs.
4736 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4737 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4738 RegsToPass[i].second, InFlag);
4739 InFlag = Chain.getValue(1);
4743 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4744 FPOp, true, TailCallArguments);
4746 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4747 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4752 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4753 MachineFunction &MF, bool isVarArg,
4754 const SmallVectorImpl<ISD::OutputArg> &Outs,
4755 LLVMContext &Context) const {
4756 SmallVector<CCValAssign, 16> RVLocs;
4757 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4759 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4763 PPCTargetLowering::LowerReturn(SDValue Chain,
4764 CallingConv::ID CallConv, bool isVarArg,
4765 const SmallVectorImpl<ISD::OutputArg> &Outs,
4766 const SmallVectorImpl<SDValue> &OutVals,
4767 SDLoc dl, SelectionDAG &DAG) const {
4769 SmallVector<CCValAssign, 16> RVLocs;
4770 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4771 getTargetMachine(), RVLocs, *DAG.getContext());
4772 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4775 SmallVector<SDValue, 4> RetOps(1, Chain);
4777 // Copy the result values into the output registers.
4778 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4779 CCValAssign &VA = RVLocs[i];
4780 assert(VA.isRegLoc() && "Can only return in registers!");
4782 SDValue Arg = OutVals[i];
4784 switch (VA.getLocInfo()) {
4785 default: llvm_unreachable("Unknown loc info!");
4786 case CCValAssign::Full: break;
4787 case CCValAssign::AExt:
4788 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4790 case CCValAssign::ZExt:
4791 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4793 case CCValAssign::SExt:
4794 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4798 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4799 Flag = Chain.getValue(1);
4800 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4803 RetOps[0] = Chain; // Update chain.
4805 // Add the flag if we have it.
4807 RetOps.push_back(Flag);
4809 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
4812 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4813 const PPCSubtarget &Subtarget) const {
4814 // When we pop the dynamic allocation we need to restore the SP link.
4817 // Get the corect type for pointers.
4818 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4820 // Construct the stack pointer operand.
4821 bool isPPC64 = Subtarget.isPPC64();
4822 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4823 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4825 // Get the operands for the STACKRESTORE.
4826 SDValue Chain = Op.getOperand(0);
4827 SDValue SaveSP = Op.getOperand(1);
4829 // Load the old link SP.
4830 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4831 MachinePointerInfo(),
4832 false, false, false, 0);
4834 // Restore the stack pointer.
4835 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4837 // Store the old link SP.
4838 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4845 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4846 MachineFunction &MF = DAG.getMachineFunction();
4847 bool isPPC64 = Subtarget.isPPC64();
4848 bool isDarwinABI = Subtarget.isDarwinABI();
4849 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4851 // Get current frame pointer save index. The users of this index will be
4852 // primarily DYNALLOC instructions.
4853 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4854 int RASI = FI->getReturnAddrSaveIndex();
4856 // If the frame pointer save index hasn't been defined yet.
4858 // Find out what the fix offset of the frame pointer save area.
4859 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4860 // Allocate the frame index for frame pointer save area.
4861 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4863 FI->setReturnAddrSaveIndex(RASI);
4865 return DAG.getFrameIndex(RASI, PtrVT);
4869 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4870 MachineFunction &MF = DAG.getMachineFunction();
4871 bool isPPC64 = Subtarget.isPPC64();
4872 bool isDarwinABI = Subtarget.isDarwinABI();
4873 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4875 // Get current frame pointer save index. The users of this index will be
4876 // primarily DYNALLOC instructions.
4877 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4878 int FPSI = FI->getFramePointerSaveIndex();
4880 // If the frame pointer save index hasn't been defined yet.
4882 // Find out what the fix offset of the frame pointer save area.
4883 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4886 // Allocate the frame index for frame pointer save area.
4887 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4889 FI->setFramePointerSaveIndex(FPSI);
4891 return DAG.getFrameIndex(FPSI, PtrVT);
4894 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4896 const PPCSubtarget &Subtarget) const {
4898 SDValue Chain = Op.getOperand(0);
4899 SDValue Size = Op.getOperand(1);
4902 // Get the corect type for pointers.
4903 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4905 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4906 DAG.getConstant(0, PtrVT), Size);
4907 // Construct a node for the frame pointer save index.
4908 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4909 // Build a DYNALLOC node.
4910 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4911 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4912 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
4915 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4916 SelectionDAG &DAG) const {
4918 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4919 DAG.getVTList(MVT::i32, MVT::Other),
4920 Op.getOperand(0), Op.getOperand(1));
4923 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4924 SelectionDAG &DAG) const {
4926 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4927 Op.getOperand(0), Op.getOperand(1));
4930 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
4931 assert(Op.getValueType() == MVT::i1 &&
4932 "Custom lowering only for i1 loads");
4934 // First, load 8 bits into 32 bits, then truncate to 1 bit.
4937 LoadSDNode *LD = cast<LoadSDNode>(Op);
4939 SDValue Chain = LD->getChain();
4940 SDValue BasePtr = LD->getBasePtr();
4941 MachineMemOperand *MMO = LD->getMemOperand();
4943 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
4944 BasePtr, MVT::i8, MMO);
4945 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
4947 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
4948 return DAG.getMergeValues(Ops, dl);
4951 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
4952 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
4953 "Custom lowering only for i1 stores");
4955 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
4958 StoreSDNode *ST = cast<StoreSDNode>(Op);
4960 SDValue Chain = ST->getChain();
4961 SDValue BasePtr = ST->getBasePtr();
4962 SDValue Value = ST->getValue();
4963 MachineMemOperand *MMO = ST->getMemOperand();
4965 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
4966 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
4969 // FIXME: Remove this once the ANDI glue bug is fixed:
4970 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
4971 assert(Op.getValueType() == MVT::i1 &&
4972 "Custom lowering only for i1 results");
4975 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
4979 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4981 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4982 // Not FP? Not a fsel.
4983 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4984 !Op.getOperand(2).getValueType().isFloatingPoint())
4987 // We might be able to do better than this under some circumstances, but in
4988 // general, fsel-based lowering of select is a finite-math-only optimization.
4989 // For more information, see section F.3 of the 2.06 ISA specification.
4990 if (!DAG.getTarget().Options.NoInfsFPMath ||
4991 !DAG.getTarget().Options.NoNaNsFPMath)
4994 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4996 EVT ResVT = Op.getValueType();
4997 EVT CmpVT = Op.getOperand(0).getValueType();
4998 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4999 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5002 // If the RHS of the comparison is a 0.0, we don't need to do the
5003 // subtraction at all.
5005 if (isFloatingPointZero(RHS))
5007 default: break; // SETUO etc aren't handled by fsel.
5011 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5012 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5013 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5014 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5015 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5016 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5017 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5020 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5023 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5024 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5025 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5028 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5031 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5032 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5033 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5034 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5039 default: break; // SETUO etc aren't handled by fsel.
5043 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5044 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5045 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5046 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5047 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5048 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5049 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5050 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5053 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5054 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5055 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5056 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5059 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5060 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5061 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5062 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5065 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5066 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5067 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5068 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5071 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5072 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5073 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5074 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5079 // FIXME: Split this code up when LegalizeDAGTypes lands.
5080 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5082 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5083 SDValue Src = Op.getOperand(0);
5084 if (Src.getValueType() == MVT::f32)
5085 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5088 switch (Op.getSimpleValueType().SimpleTy) {
5089 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5091 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5092 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5097 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5098 "i64 FP_TO_UINT is supported only with FPCVT");
5099 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5105 // Convert the FP value to an int value through memory.
5106 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5107 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5108 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5109 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5110 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5112 // Emit a store to the stack slot.
5115 MachineFunction &MF = DAG.getMachineFunction();
5116 MachineMemOperand *MMO =
5117 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5118 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5119 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5120 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5122 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5123 MPI, false, false, 0);
5125 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5127 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5128 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5129 DAG.getConstant(4, FIPtr.getValueType()));
5130 MPI = MachinePointerInfo();
5133 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5134 false, false, false, 0);
5137 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5138 SelectionDAG &DAG) const {
5140 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5141 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5144 if (Op.getOperand(0).getValueType() == MVT::i1)
5145 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5146 DAG.getConstantFP(1.0, Op.getValueType()),
5147 DAG.getConstantFP(0.0, Op.getValueType()));
5149 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5150 "UINT_TO_FP is supported only with FPCVT");
5152 // If we have FCFIDS, then use it when converting to single-precision.
5153 // Otherwise, convert to double-precision and then round.
5154 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5155 (Op.getOpcode() == ISD::UINT_TO_FP ?
5156 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5157 (Op.getOpcode() == ISD::UINT_TO_FP ?
5158 PPCISD::FCFIDU : PPCISD::FCFID);
5159 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5160 MVT::f32 : MVT::f64;
5162 if (Op.getOperand(0).getValueType() == MVT::i64) {
5163 SDValue SINT = Op.getOperand(0);
5164 // When converting to single-precision, we actually need to convert
5165 // to double-precision first and then round to single-precision.
5166 // To avoid double-rounding effects during that operation, we have
5167 // to prepare the input operand. Bits that might be truncated when
5168 // converting to double-precision are replaced by a bit that won't
5169 // be lost at this stage, but is below the single-precision rounding
5172 // However, if -enable-unsafe-fp-math is in effect, accept double
5173 // rounding to avoid the extra overhead.
5174 if (Op.getValueType() == MVT::f32 &&
5175 !Subtarget.hasFPCVT() &&
5176 !DAG.getTarget().Options.UnsafeFPMath) {
5178 // Twiddle input to make sure the low 11 bits are zero. (If this
5179 // is the case, we are guaranteed the value will fit into the 53 bit
5180 // mantissa of an IEEE double-precision value without rounding.)
5181 // If any of those low 11 bits were not zero originally, make sure
5182 // bit 12 (value 2048) is set instead, so that the final rounding
5183 // to single-precision gets the correct result.
5184 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5185 SINT, DAG.getConstant(2047, MVT::i64));
5186 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5187 Round, DAG.getConstant(2047, MVT::i64));
5188 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5189 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5190 Round, DAG.getConstant(-2048, MVT::i64));
5192 // However, we cannot use that value unconditionally: if the magnitude
5193 // of the input value is small, the bit-twiddling we did above might
5194 // end up visibly changing the output. Fortunately, in that case, we
5195 // don't need to twiddle bits since the original input will convert
5196 // exactly to double-precision floating-point already. Therefore,
5197 // construct a conditional to use the original value if the top 11
5198 // bits are all sign-bit copies, and use the rounded value computed
5200 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5201 SINT, DAG.getConstant(53, MVT::i32));
5202 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5203 Cond, DAG.getConstant(1, MVT::i64));
5204 Cond = DAG.getSetCC(dl, MVT::i32,
5205 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5207 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5210 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5211 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5213 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5214 FP = DAG.getNode(ISD::FP_ROUND, dl,
5215 MVT::f32, FP, DAG.getIntPtrConstant(0));
5219 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5220 "Unhandled INT_TO_FP type in custom expander!");
5221 // Since we only generate this in 64-bit mode, we can take advantage of
5222 // 64-bit registers. In particular, sign extend the input value into the
5223 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5224 // then lfd it and fcfid it.
5225 MachineFunction &MF = DAG.getMachineFunction();
5226 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5227 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5230 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5231 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5232 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5234 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5235 MachinePointerInfo::getFixedStack(FrameIdx),
5238 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5239 "Expected an i32 store");
5240 MachineMemOperand *MMO =
5241 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5242 MachineMemOperand::MOLoad, 4, 4);
5243 SDValue Ops[] = { Store, FIdx };
5244 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5245 PPCISD::LFIWZX : PPCISD::LFIWAX,
5246 dl, DAG.getVTList(MVT::f64, MVT::Other),
5247 Ops, MVT::i32, MMO);
5249 assert(Subtarget.isPPC64() &&
5250 "i32->FP without LFIWAX supported only on PPC64");
5252 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5253 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5255 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5258 // STD the extended value into the stack slot.
5259 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5260 MachinePointerInfo::getFixedStack(FrameIdx),
5263 // Load the value as a double.
5264 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5265 MachinePointerInfo::getFixedStack(FrameIdx),
5266 false, false, false, 0);
5269 // FCFID it and return it.
5270 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5271 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5272 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5276 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5277 SelectionDAG &DAG) const {
5280 The rounding mode is in bits 30:31 of FPSR, and has the following
5287 FLT_ROUNDS, on the other hand, expects the following:
5294 To perform the conversion, we do:
5295 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5298 MachineFunction &MF = DAG.getMachineFunction();
5299 EVT VT = Op.getValueType();
5300 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5302 // Save FP Control Word to register
5304 MVT::f64, // return register
5305 MVT::Glue // unused in this context
5307 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5309 // Save FP register to stack slot
5310 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5311 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5312 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5313 StackSlot, MachinePointerInfo(), false, false,0);
5315 // Load FP Control Word from low 32 bits of stack slot.
5316 SDValue Four = DAG.getConstant(4, PtrVT);
5317 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5318 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5319 false, false, false, 0);
5321 // Transform as necessary
5323 DAG.getNode(ISD::AND, dl, MVT::i32,
5324 CWD, DAG.getConstant(3, MVT::i32));
5326 DAG.getNode(ISD::SRL, dl, MVT::i32,
5327 DAG.getNode(ISD::AND, dl, MVT::i32,
5328 DAG.getNode(ISD::XOR, dl, MVT::i32,
5329 CWD, DAG.getConstant(3, MVT::i32)),
5330 DAG.getConstant(3, MVT::i32)),
5331 DAG.getConstant(1, MVT::i32));
5334 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5336 return DAG.getNode((VT.getSizeInBits() < 16 ?
5337 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5340 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5341 EVT VT = Op.getValueType();
5342 unsigned BitWidth = VT.getSizeInBits();
5344 assert(Op.getNumOperands() == 3 &&
5345 VT == Op.getOperand(1).getValueType() &&
5348 // Expand into a bunch of logical ops. Note that these ops
5349 // depend on the PPC behavior for oversized shift amounts.
5350 SDValue Lo = Op.getOperand(0);
5351 SDValue Hi = Op.getOperand(1);
5352 SDValue Amt = Op.getOperand(2);
5353 EVT AmtVT = Amt.getValueType();
5355 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5356 DAG.getConstant(BitWidth, AmtVT), Amt);
5357 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5358 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5359 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5360 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5361 DAG.getConstant(-BitWidth, AmtVT));
5362 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5363 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5364 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5365 SDValue OutOps[] = { OutLo, OutHi };
5366 return DAG.getMergeValues(OutOps, dl);
5369 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5370 EVT VT = Op.getValueType();
5372 unsigned BitWidth = VT.getSizeInBits();
5373 assert(Op.getNumOperands() == 3 &&
5374 VT == Op.getOperand(1).getValueType() &&
5377 // Expand into a bunch of logical ops. Note that these ops
5378 // depend on the PPC behavior for oversized shift amounts.
5379 SDValue Lo = Op.getOperand(0);
5380 SDValue Hi = Op.getOperand(1);
5381 SDValue Amt = Op.getOperand(2);
5382 EVT AmtVT = Amt.getValueType();
5384 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5385 DAG.getConstant(BitWidth, AmtVT), Amt);
5386 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5387 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5388 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5389 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5390 DAG.getConstant(-BitWidth, AmtVT));
5391 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5392 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5393 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5394 SDValue OutOps[] = { OutLo, OutHi };
5395 return DAG.getMergeValues(OutOps, dl);
5398 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5400 EVT VT = Op.getValueType();
5401 unsigned BitWidth = VT.getSizeInBits();
5402 assert(Op.getNumOperands() == 3 &&
5403 VT == Op.getOperand(1).getValueType() &&
5406 // Expand into a bunch of logical ops, followed by a select_cc.
5407 SDValue Lo = Op.getOperand(0);
5408 SDValue Hi = Op.getOperand(1);
5409 SDValue Amt = Op.getOperand(2);
5410 EVT AmtVT = Amt.getValueType();
5412 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5413 DAG.getConstant(BitWidth, AmtVT), Amt);
5414 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5415 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5416 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5417 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5418 DAG.getConstant(-BitWidth, AmtVT));
5419 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5420 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5421 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5422 Tmp4, Tmp6, ISD::SETLE);
5423 SDValue OutOps[] = { OutLo, OutHi };
5424 return DAG.getMergeValues(OutOps, dl);
5427 //===----------------------------------------------------------------------===//
5428 // Vector related lowering.
5431 /// BuildSplatI - Build a canonical splati of Val with an element size of
5432 /// SplatSize. Cast the result to VT.
5433 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5434 SelectionDAG &DAG, SDLoc dl) {
5435 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5437 static const EVT VTys[] = { // canonical VT to use for each size.
5438 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5441 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5443 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5447 EVT CanonicalVT = VTys[SplatSize-1];
5449 // Build a canonical splat for this value.
5450 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5451 SmallVector<SDValue, 8> Ops;
5452 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5453 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5454 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5457 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5458 /// specified intrinsic ID.
5459 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5460 SelectionDAG &DAG, SDLoc dl,
5461 EVT DestVT = MVT::Other) {
5462 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5463 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5464 DAG.getConstant(IID, MVT::i32), Op);
5467 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5468 /// specified intrinsic ID.
5469 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5470 SelectionDAG &DAG, SDLoc dl,
5471 EVT DestVT = MVT::Other) {
5472 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5473 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5474 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5477 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5478 /// specified intrinsic ID.
5479 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5480 SDValue Op2, SelectionDAG &DAG,
5481 SDLoc dl, EVT DestVT = MVT::Other) {
5482 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5483 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5484 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5488 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5489 /// amount. The result has the specified value type.
5490 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5491 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5492 // Force LHS/RHS to be the right type.
5493 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5494 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5497 for (unsigned i = 0; i != 16; ++i)
5499 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5500 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5503 // If this is a case we can't handle, return null and let the default
5504 // expansion code take care of it. If we CAN select this case, and if it
5505 // selects to a single instruction, return Op. Otherwise, if we can codegen
5506 // this case more efficiently than a constant pool load, lower it to the
5507 // sequence of ops that should be used.
5508 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5509 SelectionDAG &DAG) const {
5511 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5512 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5514 // Check if this is a splat of a constant value.
5515 APInt APSplatBits, APSplatUndef;
5516 unsigned SplatBitSize;
5518 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5519 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5522 unsigned SplatBits = APSplatBits.getZExtValue();
5523 unsigned SplatUndef = APSplatUndef.getZExtValue();
5524 unsigned SplatSize = SplatBitSize / 8;
5526 // First, handle single instruction cases.
5529 if (SplatBits == 0) {
5530 // Canonicalize all zero vectors to be v4i32.
5531 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5532 SDValue Z = DAG.getConstant(0, MVT::i32);
5533 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5534 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5539 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5540 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5542 if (SextVal >= -16 && SextVal <= 15)
5543 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5546 // Two instruction sequences.
5548 // If this value is in the range [-32,30] and is even, use:
5549 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5550 // If this value is in the range [17,31] and is odd, use:
5551 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5552 // If this value is in the range [-31,-17] and is odd, use:
5553 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5554 // Note the last two are three-instruction sequences.
5555 if (SextVal >= -32 && SextVal <= 31) {
5556 // To avoid having these optimizations undone by constant folding,
5557 // we convert to a pseudo that will be expanded later into one of
5559 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5560 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5561 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5562 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5563 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5564 if (VT == Op.getValueType())
5567 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5570 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5571 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5573 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5574 // Make -1 and vspltisw -1:
5575 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5577 // Make the VSLW intrinsic, computing 0x8000_0000.
5578 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5581 // xor by OnesV to invert it.
5582 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5583 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5586 // The remaining cases assume either big endian element order or
5587 // a splat-size that equates to the element size of the vector
5588 // to be built. An example that doesn't work for little endian is
5589 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5590 // and a vector element size of 16 bits. The code below will
5591 // produce the vector in big endian element order, which for little
5592 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5594 // For now, just avoid these optimizations in that case.
5595 // FIXME: Develop correct optimizations for LE with mismatched
5596 // splat and element sizes.
5598 if (Subtarget.isLittleEndian() &&
5599 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5602 // Check to see if this is a wide variety of vsplti*, binop self cases.
5603 static const signed char SplatCsts[] = {
5604 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5605 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5608 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5609 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5610 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5611 int i = SplatCsts[idx];
5613 // Figure out what shift amount will be used by altivec if shifted by i in
5615 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5617 // vsplti + shl self.
5618 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5619 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5620 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5621 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5622 Intrinsic::ppc_altivec_vslw
5624 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5625 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5628 // vsplti + srl self.
5629 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5630 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5631 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5632 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5633 Intrinsic::ppc_altivec_vsrw
5635 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5636 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5639 // vsplti + sra self.
5640 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5641 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5642 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5643 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5644 Intrinsic::ppc_altivec_vsraw
5646 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5647 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5650 // vsplti + rol self.
5651 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5652 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5653 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5654 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5655 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5656 Intrinsic::ppc_altivec_vrlw
5658 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5659 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5662 // t = vsplti c, result = vsldoi t, t, 1
5663 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5664 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5665 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5667 // t = vsplti c, result = vsldoi t, t, 2
5668 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5669 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5670 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5672 // t = vsplti c, result = vsldoi t, t, 3
5673 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5674 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5675 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5682 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5683 /// the specified operations to build the shuffle.
5684 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5685 SDValue RHS, SelectionDAG &DAG,
5687 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5688 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5689 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5692 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5704 if (OpNum == OP_COPY) {
5705 if (LHSID == (1*9+2)*9+3) return LHS;
5706 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5710 SDValue OpLHS, OpRHS;
5711 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5712 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5716 default: llvm_unreachable("Unknown i32 permute!");
5718 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5719 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5720 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5721 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5724 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5725 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5726 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5727 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5730 for (unsigned i = 0; i != 16; ++i)
5731 ShufIdxs[i] = (i&3)+0;
5734 for (unsigned i = 0; i != 16; ++i)
5735 ShufIdxs[i] = (i&3)+4;
5738 for (unsigned i = 0; i != 16; ++i)
5739 ShufIdxs[i] = (i&3)+8;
5742 for (unsigned i = 0; i != 16; ++i)
5743 ShufIdxs[i] = (i&3)+12;
5746 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5748 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5750 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5752 EVT VT = OpLHS.getValueType();
5753 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5754 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5755 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5756 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5759 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5760 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5761 /// return the code it can be lowered into. Worst case, it can always be
5762 /// lowered into a vperm.
5763 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5764 SelectionDAG &DAG) const {
5766 SDValue V1 = Op.getOperand(0);
5767 SDValue V2 = Op.getOperand(1);
5768 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5769 EVT VT = Op.getValueType();
5770 bool isLittleEndian = Subtarget.isLittleEndian();
5772 // Cases that are handled by instructions that take permute immediates
5773 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5774 // selected by the instruction selector.
5775 if (V2.getOpcode() == ISD::UNDEF) {
5776 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5777 PPC::isSplatShuffleMask(SVOp, 2) ||
5778 PPC::isSplatShuffleMask(SVOp, 4) ||
5779 PPC::isVPKUWUMShuffleMask(SVOp, true, DAG) ||
5780 PPC::isVPKUHUMShuffleMask(SVOp, true, DAG) ||
5781 PPC::isVSLDOIShuffleMask(SVOp, true, DAG) != -1 ||
5782 PPC::isVMRGLShuffleMask(SVOp, 1, true, DAG) ||
5783 PPC::isVMRGLShuffleMask(SVOp, 2, true, DAG) ||
5784 PPC::isVMRGLShuffleMask(SVOp, 4, true, DAG) ||
5785 PPC::isVMRGHShuffleMask(SVOp, 1, true, DAG) ||
5786 PPC::isVMRGHShuffleMask(SVOp, 2, true, DAG) ||
5787 PPC::isVMRGHShuffleMask(SVOp, 4, true, DAG)) {
5792 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5793 // and produce a fixed permutation. If any of these match, do not lower to
5795 if (PPC::isVPKUWUMShuffleMask(SVOp, false, DAG) ||
5796 PPC::isVPKUHUMShuffleMask(SVOp, false, DAG) ||
5797 PPC::isVSLDOIShuffleMask(SVOp, false, DAG) != -1 ||
5798 PPC::isVMRGLShuffleMask(SVOp, 1, false, DAG) ||
5799 PPC::isVMRGLShuffleMask(SVOp, 2, false, DAG) ||
5800 PPC::isVMRGLShuffleMask(SVOp, 4, false, DAG) ||
5801 PPC::isVMRGHShuffleMask(SVOp, 1, false, DAG) ||
5802 PPC::isVMRGHShuffleMask(SVOp, 2, false, DAG) ||
5803 PPC::isVMRGHShuffleMask(SVOp, 4, false, DAG))
5806 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5807 // perfect shuffle table to emit an optimal matching sequence.
5808 ArrayRef<int> PermMask = SVOp->getMask();
5810 unsigned PFIndexes[4];
5811 bool isFourElementShuffle = true;
5812 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5813 unsigned EltNo = 8; // Start out undef.
5814 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5815 if (PermMask[i*4+j] < 0)
5816 continue; // Undef, ignore it.
5818 unsigned ByteSource = PermMask[i*4+j];
5819 if ((ByteSource & 3) != j) {
5820 isFourElementShuffle = false;
5825 EltNo = ByteSource/4;
5826 } else if (EltNo != ByteSource/4) {
5827 isFourElementShuffle = false;
5831 PFIndexes[i] = EltNo;
5834 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5835 // perfect shuffle vector to determine if it is cost effective to do this as
5836 // discrete instructions, or whether we should use a vperm.
5837 // For now, we skip this for little endian until such time as we have a
5838 // little-endian perfect shuffle table.
5839 if (isFourElementShuffle && !isLittleEndian) {
5840 // Compute the index in the perfect shuffle table.
5841 unsigned PFTableIndex =
5842 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5844 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5845 unsigned Cost = (PFEntry >> 30);
5847 // Determining when to avoid vperm is tricky. Many things affect the cost
5848 // of vperm, particularly how many times the perm mask needs to be computed.
5849 // For example, if the perm mask can be hoisted out of a loop or is already
5850 // used (perhaps because there are multiple permutes with the same shuffle
5851 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5852 // the loop requires an extra register.
5854 // As a compromise, we only emit discrete instructions if the shuffle can be
5855 // generated in 3 or fewer operations. When we have loop information
5856 // available, if this block is within a loop, we should avoid using vperm
5857 // for 3-operation perms and use a constant pool load instead.
5859 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5862 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5863 // vector that will get spilled to the constant pool.
5864 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5866 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5867 // that it is in input element units, not in bytes. Convert now.
5869 // For little endian, the order of the input vectors is reversed, and
5870 // the permutation mask is complemented with respect to 31. This is
5871 // necessary to produce proper semantics with the big-endian-biased vperm
5873 EVT EltVT = V1.getValueType().getVectorElementType();
5874 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5876 SmallVector<SDValue, 16> ResultMask;
5877 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5878 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5880 for (unsigned j = 0; j != BytesPerElement; ++j)
5882 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
5885 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5889 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5892 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
5895 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
5899 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5900 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5901 /// information about the intrinsic.
5902 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5904 unsigned IntrinsicID =
5905 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5908 switch (IntrinsicID) {
5909 default: return false;
5910 // Comparison predicates.
5911 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5912 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5913 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5914 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5915 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5916 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5917 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5918 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5919 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5920 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5921 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5922 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5923 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5925 // Normal Comparisons.
5926 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5927 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5928 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5929 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5930 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5931 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5932 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5933 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5934 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5935 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5936 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5937 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5938 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5943 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5944 /// lower, do it, otherwise return null.
5945 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5946 SelectionDAG &DAG) const {
5947 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5948 // opcode number of the comparison.
5952 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5953 return SDValue(); // Don't custom lower most intrinsics.
5955 // If this is a non-dot comparison, make the VCMP node and we are done.
5957 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5958 Op.getOperand(1), Op.getOperand(2),
5959 DAG.getConstant(CompareOpc, MVT::i32));
5960 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5963 // Create the PPCISD altivec 'dot' comparison node.
5965 Op.getOperand(2), // LHS
5966 Op.getOperand(3), // RHS
5967 DAG.getConstant(CompareOpc, MVT::i32)
5969 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5970 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
5972 // Now that we have the comparison, emit a copy from the CR to a GPR.
5973 // This is flagged to the above dot comparison.
5974 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5975 DAG.getRegister(PPC::CR6, MVT::i32),
5976 CompNode.getValue(1));
5978 // Unpack the result based on how the target uses it.
5979 unsigned BitNo; // Bit # of CR6.
5980 bool InvertBit; // Invert result?
5981 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5982 default: // Can't happen, don't crash on invalid number though.
5983 case 0: // Return the value of the EQ bit of CR6.
5984 BitNo = 0; InvertBit = false;
5986 case 1: // Return the inverted value of the EQ bit of CR6.
5987 BitNo = 0; InvertBit = true;
5989 case 2: // Return the value of the LT bit of CR6.
5990 BitNo = 2; InvertBit = false;
5992 case 3: // Return the inverted value of the LT bit of CR6.
5993 BitNo = 2; InvertBit = true;
5997 // Shift the bit into the low position.
5998 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5999 DAG.getConstant(8-(3-BitNo), MVT::i32));
6001 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6002 DAG.getConstant(1, MVT::i32));
6004 // If we are supposed to, toggle the bit.
6006 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6007 DAG.getConstant(1, MVT::i32));
6011 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6012 SelectionDAG &DAG) const {
6014 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6015 // instructions), but for smaller types, we need to first extend up to v2i32
6016 // before doing going farther.
6017 if (Op.getValueType() == MVT::v2i64) {
6018 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6019 if (ExtVT != MVT::v2i32) {
6020 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6021 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6022 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6023 ExtVT.getVectorElementType(), 4)));
6024 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6025 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6026 DAG.getValueType(MVT::v2i32));
6035 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6036 SelectionDAG &DAG) const {
6038 // Create a stack slot that is 16-byte aligned.
6039 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6040 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6041 EVT PtrVT = getPointerTy();
6042 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6044 // Store the input value into Value#0 of the stack slot.
6045 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6046 Op.getOperand(0), FIdx, MachinePointerInfo(),
6049 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6050 false, false, false, 0);
6053 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6055 if (Op.getValueType() == MVT::v4i32) {
6056 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6058 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6059 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6061 SDValue RHSSwap = // = vrlw RHS, 16
6062 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6064 // Shrinkify inputs to v8i16.
6065 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6066 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6067 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6069 // Low parts multiplied together, generating 32-bit results (we ignore the
6071 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6072 LHS, RHS, DAG, dl, MVT::v4i32);
6074 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6075 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6076 // Shift the high parts up 16 bits.
6077 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6079 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6080 } else if (Op.getValueType() == MVT::v8i16) {
6081 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6083 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6085 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6086 LHS, RHS, Zero, DAG, dl);
6087 } else if (Op.getValueType() == MVT::v16i8) {
6088 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6089 bool isLittleEndian = Subtarget.isLittleEndian();
6091 // Multiply the even 8-bit parts, producing 16-bit sums.
6092 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6093 LHS, RHS, DAG, dl, MVT::v8i16);
6094 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6096 // Multiply the odd 8-bit parts, producing 16-bit sums.
6097 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6098 LHS, RHS, DAG, dl, MVT::v8i16);
6099 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6101 // Merge the results together. Because vmuleub and vmuloub are
6102 // instructions with a big-endian bias, we must reverse the
6103 // element numbering and reverse the meaning of "odd" and "even"
6104 // when generating little endian code.
6106 for (unsigned i = 0; i != 8; ++i) {
6107 if (isLittleEndian) {
6109 Ops[i*2+1] = 2*i+16;
6112 Ops[i*2+1] = 2*i+1+16;
6116 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6118 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6120 llvm_unreachable("Unknown mul to lower!");
6124 /// LowerOperation - Provide custom lowering hooks for some operations.
6126 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6127 switch (Op.getOpcode()) {
6128 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6129 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6130 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6131 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6132 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6133 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6134 case ISD::SETCC: return LowerSETCC(Op, DAG);
6135 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6136 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6138 return LowerVASTART(Op, DAG, Subtarget);
6141 return LowerVAARG(Op, DAG, Subtarget);
6144 return LowerVACOPY(Op, DAG, Subtarget);
6146 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6147 case ISD::DYNAMIC_STACKALLOC:
6148 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6150 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6151 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6153 case ISD::LOAD: return LowerLOAD(Op, DAG);
6154 case ISD::STORE: return LowerSTORE(Op, DAG);
6155 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6156 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6157 case ISD::FP_TO_UINT:
6158 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6160 case ISD::UINT_TO_FP:
6161 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6162 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6164 // Lower 64-bit shifts.
6165 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6166 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6167 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6169 // Vector-related lowering.
6170 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6171 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6172 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6173 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6174 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6175 case ISD::MUL: return LowerMUL(Op, DAG);
6177 // For counter-based loop handling.
6178 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6180 // Frame & Return address.
6181 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6182 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6186 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6187 SmallVectorImpl<SDValue>&Results,
6188 SelectionDAG &DAG) const {
6189 const TargetMachine &TM = getTargetMachine();
6191 switch (N->getOpcode()) {
6193 llvm_unreachable("Do not know how to custom type legalize this operation!");
6194 case ISD::INTRINSIC_W_CHAIN: {
6195 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6196 Intrinsic::ppc_is_decremented_ctr_nonzero)
6199 assert(N->getValueType(0) == MVT::i1 &&
6200 "Unexpected result type for CTR decrement intrinsic");
6201 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6202 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6203 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6206 Results.push_back(NewInt);
6207 Results.push_back(NewInt.getValue(1));
6211 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6212 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6215 EVT VT = N->getValueType(0);
6217 if (VT == MVT::i64) {
6218 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6220 Results.push_back(NewNode);
6221 Results.push_back(NewNode.getValue(1));
6225 case ISD::FP_ROUND_INREG: {
6226 assert(N->getValueType(0) == MVT::ppcf128);
6227 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6228 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6229 MVT::f64, N->getOperand(0),
6230 DAG.getIntPtrConstant(0));
6231 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6232 MVT::f64, N->getOperand(0),
6233 DAG.getIntPtrConstant(1));
6235 // Add the two halves of the long double in round-to-zero mode.
6236 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6238 // We know the low half is about to be thrown away, so just use something
6240 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6244 case ISD::FP_TO_SINT:
6245 // LowerFP_TO_INT() can only handle f32 and f64.
6246 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6248 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6254 //===----------------------------------------------------------------------===//
6255 // Other Lowering Code
6256 //===----------------------------------------------------------------------===//
6259 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6260 bool is64bit, unsigned BinOpcode) const {
6261 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6262 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6264 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6265 MachineFunction *F = BB->getParent();
6266 MachineFunction::iterator It = BB;
6269 unsigned dest = MI->getOperand(0).getReg();
6270 unsigned ptrA = MI->getOperand(1).getReg();
6271 unsigned ptrB = MI->getOperand(2).getReg();
6272 unsigned incr = MI->getOperand(3).getReg();
6273 DebugLoc dl = MI->getDebugLoc();
6275 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6276 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6277 F->insert(It, loopMBB);
6278 F->insert(It, exitMBB);
6279 exitMBB->splice(exitMBB->begin(), BB,
6280 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6281 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6283 MachineRegisterInfo &RegInfo = F->getRegInfo();
6284 unsigned TmpReg = (!BinOpcode) ? incr :
6285 RegInfo.createVirtualRegister(
6286 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6287 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6291 // fallthrough --> loopMBB
6292 BB->addSuccessor(loopMBB);
6295 // l[wd]arx dest, ptr
6296 // add r0, dest, incr
6297 // st[wd]cx. r0, ptr
6299 // fallthrough --> exitMBB
6301 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6302 .addReg(ptrA).addReg(ptrB);
6304 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6305 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6306 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6307 BuildMI(BB, dl, TII->get(PPC::BCC))
6308 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6309 BB->addSuccessor(loopMBB);
6310 BB->addSuccessor(exitMBB);
6319 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6320 MachineBasicBlock *BB,
6321 bool is8bit, // operation
6322 unsigned BinOpcode) const {
6323 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6324 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6325 // In 64 bit mode we have to use 64 bits for addresses, even though the
6326 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6327 // registers without caring whether they're 32 or 64, but here we're
6328 // doing actual arithmetic on the addresses.
6329 bool is64bit = Subtarget.isPPC64();
6330 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6332 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6333 MachineFunction *F = BB->getParent();
6334 MachineFunction::iterator It = BB;
6337 unsigned dest = MI->getOperand(0).getReg();
6338 unsigned ptrA = MI->getOperand(1).getReg();
6339 unsigned ptrB = MI->getOperand(2).getReg();
6340 unsigned incr = MI->getOperand(3).getReg();
6341 DebugLoc dl = MI->getDebugLoc();
6343 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6344 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6345 F->insert(It, loopMBB);
6346 F->insert(It, exitMBB);
6347 exitMBB->splice(exitMBB->begin(), BB,
6348 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6349 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6351 MachineRegisterInfo &RegInfo = F->getRegInfo();
6352 const TargetRegisterClass *RC =
6353 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6354 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6355 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6356 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6357 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6358 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6359 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6360 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6361 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6362 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6363 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6364 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6365 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6367 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6371 // fallthrough --> loopMBB
6372 BB->addSuccessor(loopMBB);
6374 // The 4-byte load must be aligned, while a char or short may be
6375 // anywhere in the word. Hence all this nasty bookkeeping code.
6376 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6377 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6378 // xori shift, shift1, 24 [16]
6379 // rlwinm ptr, ptr1, 0, 0, 29
6380 // slw incr2, incr, shift
6381 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6382 // slw mask, mask2, shift
6384 // lwarx tmpDest, ptr
6385 // add tmp, tmpDest, incr2
6386 // andc tmp2, tmpDest, mask
6387 // and tmp3, tmp, mask
6388 // or tmp4, tmp3, tmp2
6391 // fallthrough --> exitMBB
6392 // srw dest, tmpDest, shift
6393 if (ptrA != ZeroReg) {
6394 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6395 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6396 .addReg(ptrA).addReg(ptrB);
6400 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6401 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6402 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6403 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6405 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6406 .addReg(Ptr1Reg).addImm(0).addImm(61);
6408 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6409 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6410 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6411 .addReg(incr).addReg(ShiftReg);
6413 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6415 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6416 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6418 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6419 .addReg(Mask2Reg).addReg(ShiftReg);
6422 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6423 .addReg(ZeroReg).addReg(PtrReg);
6425 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6426 .addReg(Incr2Reg).addReg(TmpDestReg);
6427 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6428 .addReg(TmpDestReg).addReg(MaskReg);
6429 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6430 .addReg(TmpReg).addReg(MaskReg);
6431 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6432 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6433 BuildMI(BB, dl, TII->get(PPC::STWCX))
6434 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6435 BuildMI(BB, dl, TII->get(PPC::BCC))
6436 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6437 BB->addSuccessor(loopMBB);
6438 BB->addSuccessor(exitMBB);
6443 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6448 llvm::MachineBasicBlock*
6449 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6450 MachineBasicBlock *MBB) const {
6451 DebugLoc DL = MI->getDebugLoc();
6452 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6454 MachineFunction *MF = MBB->getParent();
6455 MachineRegisterInfo &MRI = MF->getRegInfo();
6457 const BasicBlock *BB = MBB->getBasicBlock();
6458 MachineFunction::iterator I = MBB;
6462 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6463 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6465 unsigned DstReg = MI->getOperand(0).getReg();
6466 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6467 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6468 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6469 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6471 MVT PVT = getPointerTy();
6472 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6473 "Invalid Pointer Size!");
6474 // For v = setjmp(buf), we generate
6477 // SjLjSetup mainMBB
6483 // buf[LabelOffset] = LR
6487 // v = phi(main, restore)
6490 MachineBasicBlock *thisMBB = MBB;
6491 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6492 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6493 MF->insert(I, mainMBB);
6494 MF->insert(I, sinkMBB);
6496 MachineInstrBuilder MIB;
6498 // Transfer the remainder of BB and its successor edges to sinkMBB.
6499 sinkMBB->splice(sinkMBB->begin(), MBB,
6500 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6501 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6503 // Note that the structure of the jmp_buf used here is not compatible
6504 // with that used by libc, and is not designed to be. Specifically, it
6505 // stores only those 'reserved' registers that LLVM does not otherwise
6506 // understand how to spill. Also, by convention, by the time this
6507 // intrinsic is called, Clang has already stored the frame address in the
6508 // first slot of the buffer and stack address in the third. Following the
6509 // X86 target code, we'll store the jump address in the second slot. We also
6510 // need to save the TOC pointer (R2) to handle jumps between shared
6511 // libraries, and that will be stored in the fourth slot. The thread
6512 // identifier (R13) is not affected.
6515 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6516 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6517 const int64_t BPOffset = 4 * PVT.getStoreSize();
6519 // Prepare IP either in reg.
6520 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6521 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6522 unsigned BufReg = MI->getOperand(1).getReg();
6524 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6525 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6529 MIB.setMemRefs(MMOBegin, MMOEnd);
6532 // Naked functions never have a base pointer, and so we use r1. For all
6533 // other functions, this decision must be delayed until during PEI.
6535 if (MF->getFunction()->getAttributes().hasAttribute(
6536 AttributeSet::FunctionIndex, Attribute::Naked))
6537 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6539 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6541 MIB = BuildMI(*thisMBB, MI, DL,
6542 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6546 MIB.setMemRefs(MMOBegin, MMOEnd);
6549 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6550 const PPCRegisterInfo *TRI =
6551 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6552 MIB.addRegMask(TRI->getNoPreservedMask());
6554 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6556 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6558 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6560 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6561 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6565 MIB = BuildMI(mainMBB, DL,
6566 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6569 if (Subtarget.isPPC64()) {
6570 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6572 .addImm(LabelOffset)
6575 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6577 .addImm(LabelOffset)
6581 MIB.setMemRefs(MMOBegin, MMOEnd);
6583 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6584 mainMBB->addSuccessor(sinkMBB);
6587 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6588 TII->get(PPC::PHI), DstReg)
6589 .addReg(mainDstReg).addMBB(mainMBB)
6590 .addReg(restoreDstReg).addMBB(thisMBB);
6592 MI->eraseFromParent();
6597 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6598 MachineBasicBlock *MBB) const {
6599 DebugLoc DL = MI->getDebugLoc();
6600 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6602 MachineFunction *MF = MBB->getParent();
6603 MachineRegisterInfo &MRI = MF->getRegInfo();
6606 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6607 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6609 MVT PVT = getPointerTy();
6610 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6611 "Invalid Pointer Size!");
6613 const TargetRegisterClass *RC =
6614 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6615 unsigned Tmp = MRI.createVirtualRegister(RC);
6616 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6617 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6618 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6619 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6621 MachineInstrBuilder MIB;
6623 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6624 const int64_t SPOffset = 2 * PVT.getStoreSize();
6625 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6626 const int64_t BPOffset = 4 * PVT.getStoreSize();
6628 unsigned BufReg = MI->getOperand(0).getReg();
6630 // Reload FP (the jumped-to function may not have had a
6631 // frame pointer, and if so, then its r31 will be restored
6633 if (PVT == MVT::i64) {
6634 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6638 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6642 MIB.setMemRefs(MMOBegin, MMOEnd);
6645 if (PVT == MVT::i64) {
6646 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6647 .addImm(LabelOffset)
6650 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6651 .addImm(LabelOffset)
6654 MIB.setMemRefs(MMOBegin, MMOEnd);
6657 if (PVT == MVT::i64) {
6658 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6662 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6666 MIB.setMemRefs(MMOBegin, MMOEnd);
6669 if (PVT == MVT::i64) {
6670 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6674 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6678 MIB.setMemRefs(MMOBegin, MMOEnd);
6681 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
6682 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6686 MIB.setMemRefs(MMOBegin, MMOEnd);
6690 BuildMI(*MBB, MI, DL,
6691 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6692 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6694 MI->eraseFromParent();
6699 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6700 MachineBasicBlock *BB) const {
6701 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6702 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6703 return emitEHSjLjSetJmp(MI, BB);
6704 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6705 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6706 return emitEHSjLjLongJmp(MI, BB);
6709 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6711 // To "insert" these instructions we actually have to insert their
6712 // control-flow patterns.
6713 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6714 MachineFunction::iterator It = BB;
6717 MachineFunction *F = BB->getParent();
6719 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6720 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6721 MI->getOpcode() == PPC::SELECT_I4 ||
6722 MI->getOpcode() == PPC::SELECT_I8)) {
6723 SmallVector<MachineOperand, 2> Cond;
6724 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6725 MI->getOpcode() == PPC::SELECT_CC_I8)
6726 Cond.push_back(MI->getOperand(4));
6728 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
6729 Cond.push_back(MI->getOperand(1));
6731 DebugLoc dl = MI->getDebugLoc();
6732 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6733 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6734 Cond, MI->getOperand(2).getReg(),
6735 MI->getOperand(3).getReg());
6736 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6737 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6738 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6739 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6740 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
6741 MI->getOpcode() == PPC::SELECT_I4 ||
6742 MI->getOpcode() == PPC::SELECT_I8 ||
6743 MI->getOpcode() == PPC::SELECT_F4 ||
6744 MI->getOpcode() == PPC::SELECT_F8 ||
6745 MI->getOpcode() == PPC::SELECT_VRRC) {
6746 // The incoming instruction knows the destination vreg to set, the
6747 // condition code register to branch on, the true/false values to
6748 // select between, and a branch opcode to use.
6753 // cmpTY ccX, r1, r2
6755 // fallthrough --> copy0MBB
6756 MachineBasicBlock *thisMBB = BB;
6757 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6758 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6759 DebugLoc dl = MI->getDebugLoc();
6760 F->insert(It, copy0MBB);
6761 F->insert(It, sinkMBB);
6763 // Transfer the remainder of BB and its successor edges to sinkMBB.
6764 sinkMBB->splice(sinkMBB->begin(), BB,
6765 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6766 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6768 // Next, add the true and fallthrough blocks as its successors.
6769 BB->addSuccessor(copy0MBB);
6770 BB->addSuccessor(sinkMBB);
6772 if (MI->getOpcode() == PPC::SELECT_I4 ||
6773 MI->getOpcode() == PPC::SELECT_I8 ||
6774 MI->getOpcode() == PPC::SELECT_F4 ||
6775 MI->getOpcode() == PPC::SELECT_F8 ||
6776 MI->getOpcode() == PPC::SELECT_VRRC) {
6777 BuildMI(BB, dl, TII->get(PPC::BC))
6778 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6780 unsigned SelectPred = MI->getOperand(4).getImm();
6781 BuildMI(BB, dl, TII->get(PPC::BCC))
6782 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6786 // %FalseValue = ...
6787 // # fallthrough to sinkMBB
6790 // Update machine-CFG edges
6791 BB->addSuccessor(sinkMBB);
6794 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6797 BuildMI(*BB, BB->begin(), dl,
6798 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6799 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6800 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6802 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6803 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6804 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6805 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6806 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6807 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6808 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6809 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6811 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6812 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6813 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6814 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6815 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6816 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6817 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6818 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6820 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6821 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6822 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6823 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6824 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6825 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6826 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6827 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6829 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6830 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6831 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6832 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6833 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6834 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6835 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6836 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6838 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6839 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6840 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6841 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6842 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6843 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6844 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6845 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6847 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6848 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6849 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6850 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6851 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6852 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6853 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6854 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6856 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6857 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6858 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6859 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6860 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6861 BB = EmitAtomicBinary(MI, BB, false, 0);
6862 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6863 BB = EmitAtomicBinary(MI, BB, true, 0);
6865 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6866 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6867 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6869 unsigned dest = MI->getOperand(0).getReg();
6870 unsigned ptrA = MI->getOperand(1).getReg();
6871 unsigned ptrB = MI->getOperand(2).getReg();
6872 unsigned oldval = MI->getOperand(3).getReg();
6873 unsigned newval = MI->getOperand(4).getReg();
6874 DebugLoc dl = MI->getDebugLoc();
6876 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6877 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6878 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6879 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6880 F->insert(It, loop1MBB);
6881 F->insert(It, loop2MBB);
6882 F->insert(It, midMBB);
6883 F->insert(It, exitMBB);
6884 exitMBB->splice(exitMBB->begin(), BB,
6885 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6886 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6890 // fallthrough --> loopMBB
6891 BB->addSuccessor(loop1MBB);
6894 // l[wd]arx dest, ptr
6895 // cmp[wd] dest, oldval
6898 // st[wd]cx. newval, ptr
6902 // st[wd]cx. dest, ptr
6905 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6906 .addReg(ptrA).addReg(ptrB);
6907 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6908 .addReg(oldval).addReg(dest);
6909 BuildMI(BB, dl, TII->get(PPC::BCC))
6910 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6911 BB->addSuccessor(loop2MBB);
6912 BB->addSuccessor(midMBB);
6915 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6916 .addReg(newval).addReg(ptrA).addReg(ptrB);
6917 BuildMI(BB, dl, TII->get(PPC::BCC))
6918 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6919 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6920 BB->addSuccessor(loop1MBB);
6921 BB->addSuccessor(exitMBB);
6924 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6925 .addReg(dest).addReg(ptrA).addReg(ptrB);
6926 BB->addSuccessor(exitMBB);
6931 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6932 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6933 // We must use 64-bit registers for addresses when targeting 64-bit,
6934 // since we're actually doing arithmetic on them. Other registers
6936 bool is64bit = Subtarget.isPPC64();
6937 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6939 unsigned dest = MI->getOperand(0).getReg();
6940 unsigned ptrA = MI->getOperand(1).getReg();
6941 unsigned ptrB = MI->getOperand(2).getReg();
6942 unsigned oldval = MI->getOperand(3).getReg();
6943 unsigned newval = MI->getOperand(4).getReg();
6944 DebugLoc dl = MI->getDebugLoc();
6946 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6947 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6948 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6949 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6950 F->insert(It, loop1MBB);
6951 F->insert(It, loop2MBB);
6952 F->insert(It, midMBB);
6953 F->insert(It, exitMBB);
6954 exitMBB->splice(exitMBB->begin(), BB,
6955 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6956 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6958 MachineRegisterInfo &RegInfo = F->getRegInfo();
6959 const TargetRegisterClass *RC =
6960 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6961 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6962 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6963 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6964 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6965 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6966 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6967 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6968 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6969 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6970 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6971 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6972 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6973 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6974 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6976 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6977 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6980 // fallthrough --> loopMBB
6981 BB->addSuccessor(loop1MBB);
6983 // The 4-byte load must be aligned, while a char or short may be
6984 // anywhere in the word. Hence all this nasty bookkeeping code.
6985 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6986 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6987 // xori shift, shift1, 24 [16]
6988 // rlwinm ptr, ptr1, 0, 0, 29
6989 // slw newval2, newval, shift
6990 // slw oldval2, oldval,shift
6991 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6992 // slw mask, mask2, shift
6993 // and newval3, newval2, mask
6994 // and oldval3, oldval2, mask
6996 // lwarx tmpDest, ptr
6997 // and tmp, tmpDest, mask
6998 // cmpw tmp, oldval3
7001 // andc tmp2, tmpDest, mask
7002 // or tmp4, tmp2, newval3
7007 // stwcx. tmpDest, ptr
7009 // srw dest, tmpDest, shift
7010 if (ptrA != ZeroReg) {
7011 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7012 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7013 .addReg(ptrA).addReg(ptrB);
7017 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7018 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7019 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7020 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7022 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7023 .addReg(Ptr1Reg).addImm(0).addImm(61);
7025 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7026 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7027 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7028 .addReg(newval).addReg(ShiftReg);
7029 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7030 .addReg(oldval).addReg(ShiftReg);
7032 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7034 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7035 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7036 .addReg(Mask3Reg).addImm(65535);
7038 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7039 .addReg(Mask2Reg).addReg(ShiftReg);
7040 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7041 .addReg(NewVal2Reg).addReg(MaskReg);
7042 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7043 .addReg(OldVal2Reg).addReg(MaskReg);
7046 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7047 .addReg(ZeroReg).addReg(PtrReg);
7048 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7049 .addReg(TmpDestReg).addReg(MaskReg);
7050 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7051 .addReg(TmpReg).addReg(OldVal3Reg);
7052 BuildMI(BB, dl, TII->get(PPC::BCC))
7053 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7054 BB->addSuccessor(loop2MBB);
7055 BB->addSuccessor(midMBB);
7058 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7059 .addReg(TmpDestReg).addReg(MaskReg);
7060 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7061 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7062 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7063 .addReg(ZeroReg).addReg(PtrReg);
7064 BuildMI(BB, dl, TII->get(PPC::BCC))
7065 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7066 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7067 BB->addSuccessor(loop1MBB);
7068 BB->addSuccessor(exitMBB);
7071 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7072 .addReg(ZeroReg).addReg(PtrReg);
7073 BB->addSuccessor(exitMBB);
7078 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7080 } else if (MI->getOpcode() == PPC::FADDrtz) {
7081 // This pseudo performs an FADD with rounding mode temporarily forced
7082 // to round-to-zero. We emit this via custom inserter since the FPSCR
7083 // is not modeled at the SelectionDAG level.
7084 unsigned Dest = MI->getOperand(0).getReg();
7085 unsigned Src1 = MI->getOperand(1).getReg();
7086 unsigned Src2 = MI->getOperand(2).getReg();
7087 DebugLoc dl = MI->getDebugLoc();
7089 MachineRegisterInfo &RegInfo = F->getRegInfo();
7090 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7092 // Save FPSCR value.
7093 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7095 // Set rounding mode to round-to-zero.
7096 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7097 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7099 // Perform addition.
7100 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7102 // Restore FPSCR value.
7103 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7104 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7105 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7106 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7107 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7108 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7109 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7110 PPC::ANDIo8 : PPC::ANDIo;
7111 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7112 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7114 MachineRegisterInfo &RegInfo = F->getRegInfo();
7115 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7116 &PPC::GPRCRegClass :
7117 &PPC::G8RCRegClass);
7119 DebugLoc dl = MI->getDebugLoc();
7120 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7121 .addReg(MI->getOperand(1).getReg()).addImm(1);
7122 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7123 MI->getOperand(0).getReg())
7124 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7126 llvm_unreachable("Unexpected instr type to insert");
7129 MI->eraseFromParent(); // The pseudo instruction is gone now.
7133 //===----------------------------------------------------------------------===//
7134 // Target Optimization Hooks
7135 //===----------------------------------------------------------------------===//
7137 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
7138 DAGCombinerInfo &DCI) const {
7139 if (DCI.isAfterLegalizeVectorOps())
7142 EVT VT = Op.getValueType();
7144 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7145 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7146 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7147 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7149 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7150 // For the reciprocal, we need to find the zero of the function:
7151 // F(X) = A X - 1 [which has a zero at X = 1/A]
7153 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7154 // does not require additional intermediate precision]
7156 // Convergence is quadratic, so we essentially double the number of digits
7157 // correct after every iteration. The minimum architected relative
7158 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7159 // 23 digits and double has 52 digits.
7160 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7161 if (VT.getScalarType() == MVT::f64)
7164 SelectionDAG &DAG = DCI.DAG;
7168 DAG.getConstantFP(1.0, VT.getScalarType());
7169 if (VT.isVector()) {
7170 assert(VT.getVectorNumElements() == 4 &&
7171 "Unknown vector type");
7172 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7173 FPOne, FPOne, FPOne, FPOne);
7176 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
7177 DCI.AddToWorklist(Est.getNode());
7179 // Newton iterations: Est = Est + Est (1 - Arg * Est)
7180 for (int i = 0; i < Iterations; ++i) {
7181 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
7182 DCI.AddToWorklist(NewEst.getNode());
7184 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
7185 DCI.AddToWorklist(NewEst.getNode());
7187 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7188 DCI.AddToWorklist(NewEst.getNode());
7190 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
7191 DCI.AddToWorklist(Est.getNode());
7200 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
7201 DAGCombinerInfo &DCI) const {
7202 if (DCI.isAfterLegalizeVectorOps())
7205 EVT VT = Op.getValueType();
7207 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7208 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7209 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7210 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7212 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7213 // For the reciprocal sqrt, we need to find the zero of the function:
7214 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7216 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7217 // As a result, we precompute A/2 prior to the iteration loop.
7219 // Convergence is quadratic, so we essentially double the number of digits
7220 // correct after every iteration. The minimum architected relative
7221 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7222 // 23 digits and double has 52 digits.
7223 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7224 if (VT.getScalarType() == MVT::f64)
7227 SelectionDAG &DAG = DCI.DAG;
7230 SDValue FPThreeHalves =
7231 DAG.getConstantFP(1.5, VT.getScalarType());
7232 if (VT.isVector()) {
7233 assert(VT.getVectorNumElements() == 4 &&
7234 "Unknown vector type");
7235 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7236 FPThreeHalves, FPThreeHalves,
7237 FPThreeHalves, FPThreeHalves);
7240 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7241 DCI.AddToWorklist(Est.getNode());
7243 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7244 // this entire sequence requires only one FP constant.
7245 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7246 DCI.AddToWorklist(HalfArg.getNode());
7248 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7249 DCI.AddToWorklist(HalfArg.getNode());
7251 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7252 for (int i = 0; i < Iterations; ++i) {
7253 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7254 DCI.AddToWorklist(NewEst.getNode());
7256 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7257 DCI.AddToWorklist(NewEst.getNode());
7259 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7260 DCI.AddToWorklist(NewEst.getNode());
7262 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7263 DCI.AddToWorklist(Est.getNode());
7272 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7273 // not enforce equality of the chain operands.
7274 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
7275 unsigned Bytes, int Dist,
7276 SelectionDAG &DAG) {
7277 EVT VT = LS->getMemoryVT();
7278 if (VT.getSizeInBits() / 8 != Bytes)
7281 SDValue Loc = LS->getBasePtr();
7282 SDValue BaseLoc = Base->getBasePtr();
7283 if (Loc.getOpcode() == ISD::FrameIndex) {
7284 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7286 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7287 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7288 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7289 int FS = MFI->getObjectSize(FI);
7290 int BFS = MFI->getObjectSize(BFI);
7291 if (FS != BFS || FS != (int)Bytes) return false;
7292 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7296 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7297 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7300 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7301 const GlobalValue *GV1 = nullptr;
7302 const GlobalValue *GV2 = nullptr;
7303 int64_t Offset1 = 0;
7304 int64_t Offset2 = 0;
7305 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7306 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7307 if (isGA1 && isGA2 && GV1 == GV2)
7308 return Offset1 == (Offset2 + Dist*Bytes);
7312 // Return true is there is a nearyby consecutive load to the one provided
7313 // (regardless of alignment). We search up and down the chain, looking though
7314 // token factors and other loads (but nothing else). As a result, a true
7315 // results indicates that it is safe to create a new consecutive load adjacent
7316 // to the load provided.
7317 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7318 SDValue Chain = LD->getChain();
7319 EVT VT = LD->getMemoryVT();
7321 SmallSet<SDNode *, 16> LoadRoots;
7322 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7323 SmallSet<SDNode *, 16> Visited;
7325 // First, search up the chain, branching to follow all token-factor operands.
7326 // If we find a consecutive load, then we're done, otherwise, record all
7327 // nodes just above the top-level loads and token factors.
7328 while (!Queue.empty()) {
7329 SDNode *ChainNext = Queue.pop_back_val();
7330 if (!Visited.insert(ChainNext))
7333 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
7334 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7337 if (!Visited.count(ChainLD->getChain().getNode()))
7338 Queue.push_back(ChainLD->getChain().getNode());
7339 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7340 for (const SDUse &O : ChainNext->ops())
7341 if (!Visited.count(O.getNode()))
7342 Queue.push_back(O.getNode());
7344 LoadRoots.insert(ChainNext);
7347 // Second, search down the chain, starting from the top-level nodes recorded
7348 // in the first phase. These top-level nodes are the nodes just above all
7349 // loads and token factors. Starting with their uses, recursively look though
7350 // all loads (just the chain uses) and token factors to find a consecutive
7355 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7356 IE = LoadRoots.end(); I != IE; ++I) {
7357 Queue.push_back(*I);
7359 while (!Queue.empty()) {
7360 SDNode *LoadRoot = Queue.pop_back_val();
7361 if (!Visited.insert(LoadRoot))
7364 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
7365 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7368 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7369 UE = LoadRoot->use_end(); UI != UE; ++UI)
7370 if (((isa<LoadSDNode>(*UI) &&
7371 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7372 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7373 Queue.push_back(*UI);
7380 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7381 DAGCombinerInfo &DCI) const {
7382 SelectionDAG &DAG = DCI.DAG;
7385 assert(Subtarget.useCRBits() &&
7386 "Expecting to be tracking CR bits");
7387 // If we're tracking CR bits, we need to be careful that we don't have:
7388 // trunc(binary-ops(zext(x), zext(y)))
7390 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7391 // such that we're unnecessarily moving things into GPRs when it would be
7392 // better to keep them in CR bits.
7394 // Note that trunc here can be an actual i1 trunc, or can be the effective
7395 // truncation that comes from a setcc or select_cc.
7396 if (N->getOpcode() == ISD::TRUNCATE &&
7397 N->getValueType(0) != MVT::i1)
7400 if (N->getOperand(0).getValueType() != MVT::i32 &&
7401 N->getOperand(0).getValueType() != MVT::i64)
7404 if (N->getOpcode() == ISD::SETCC ||
7405 N->getOpcode() == ISD::SELECT_CC) {
7406 // If we're looking at a comparison, then we need to make sure that the
7407 // high bits (all except for the first) don't matter the result.
7409 cast<CondCodeSDNode>(N->getOperand(
7410 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7411 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7413 if (ISD::isSignedIntSetCC(CC)) {
7414 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7415 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7417 } else if (ISD::isUnsignedIntSetCC(CC)) {
7418 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7419 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7420 !DAG.MaskedValueIsZero(N->getOperand(1),
7421 APInt::getHighBitsSet(OpBits, OpBits-1)))
7424 // This is neither a signed nor an unsigned comparison, just make sure
7425 // that the high bits are equal.
7426 APInt Op1Zero, Op1One;
7427 APInt Op2Zero, Op2One;
7428 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7429 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7431 // We don't really care about what is known about the first bit (if
7432 // anything), so clear it in all masks prior to comparing them.
7433 Op1Zero.clearBit(0); Op1One.clearBit(0);
7434 Op2Zero.clearBit(0); Op2One.clearBit(0);
7436 if (Op1Zero != Op2Zero || Op1One != Op2One)
7441 // We now know that the higher-order bits are irrelevant, we just need to
7442 // make sure that all of the intermediate operations are bit operations, and
7443 // all inputs are extensions.
7444 if (N->getOperand(0).getOpcode() != ISD::AND &&
7445 N->getOperand(0).getOpcode() != ISD::OR &&
7446 N->getOperand(0).getOpcode() != ISD::XOR &&
7447 N->getOperand(0).getOpcode() != ISD::SELECT &&
7448 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7449 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7450 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7451 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7452 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7455 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7456 N->getOperand(1).getOpcode() != ISD::AND &&
7457 N->getOperand(1).getOpcode() != ISD::OR &&
7458 N->getOperand(1).getOpcode() != ISD::XOR &&
7459 N->getOperand(1).getOpcode() != ISD::SELECT &&
7460 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7461 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7462 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7463 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7464 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7467 SmallVector<SDValue, 4> Inputs;
7468 SmallVector<SDValue, 8> BinOps, PromOps;
7469 SmallPtrSet<SDNode *, 16> Visited;
7471 for (unsigned i = 0; i < 2; ++i) {
7472 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7473 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7474 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7475 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7476 isa<ConstantSDNode>(N->getOperand(i)))
7477 Inputs.push_back(N->getOperand(i));
7479 BinOps.push_back(N->getOperand(i));
7481 if (N->getOpcode() == ISD::TRUNCATE)
7485 // Visit all inputs, collect all binary operations (and, or, xor and
7486 // select) that are all fed by extensions.
7487 while (!BinOps.empty()) {
7488 SDValue BinOp = BinOps.back();
7491 if (!Visited.insert(BinOp.getNode()))
7494 PromOps.push_back(BinOp);
7496 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7497 // The condition of the select is not promoted.
7498 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7500 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7503 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7504 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7505 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7506 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7507 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7508 Inputs.push_back(BinOp.getOperand(i));
7509 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7510 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7511 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7512 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7513 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7514 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7515 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7516 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7517 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7518 BinOps.push_back(BinOp.getOperand(i));
7520 // We have an input that is not an extension or another binary
7521 // operation; we'll abort this transformation.
7527 // Make sure that this is a self-contained cluster of operations (which
7528 // is not quite the same thing as saying that everything has only one
7530 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7531 if (isa<ConstantSDNode>(Inputs[i]))
7534 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7535 UE = Inputs[i].getNode()->use_end();
7538 if (User != N && !Visited.count(User))
7541 // Make sure that we're not going to promote the non-output-value
7542 // operand(s) or SELECT or SELECT_CC.
7543 // FIXME: Although we could sometimes handle this, and it does occur in
7544 // practice that one of the condition inputs to the select is also one of
7545 // the outputs, we currently can't deal with this.
7546 if (User->getOpcode() == ISD::SELECT) {
7547 if (User->getOperand(0) == Inputs[i])
7549 } else if (User->getOpcode() == ISD::SELECT_CC) {
7550 if (User->getOperand(0) == Inputs[i] ||
7551 User->getOperand(1) == Inputs[i])
7557 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7558 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7559 UE = PromOps[i].getNode()->use_end();
7562 if (User != N && !Visited.count(User))
7565 // Make sure that we're not going to promote the non-output-value
7566 // operand(s) or SELECT or SELECT_CC.
7567 // FIXME: Although we could sometimes handle this, and it does occur in
7568 // practice that one of the condition inputs to the select is also one of
7569 // the outputs, we currently can't deal with this.
7570 if (User->getOpcode() == ISD::SELECT) {
7571 if (User->getOperand(0) == PromOps[i])
7573 } else if (User->getOpcode() == ISD::SELECT_CC) {
7574 if (User->getOperand(0) == PromOps[i] ||
7575 User->getOperand(1) == PromOps[i])
7581 // Replace all inputs with the extension operand.
7582 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7583 // Constants may have users outside the cluster of to-be-promoted nodes,
7584 // and so we need to replace those as we do the promotions.
7585 if (isa<ConstantSDNode>(Inputs[i]))
7588 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7591 // Replace all operations (these are all the same, but have a different
7592 // (i1) return type). DAG.getNode will validate that the types of
7593 // a binary operator match, so go through the list in reverse so that
7594 // we've likely promoted both operands first. Any intermediate truncations or
7595 // extensions disappear.
7596 while (!PromOps.empty()) {
7597 SDValue PromOp = PromOps.back();
7600 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7601 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7602 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7603 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7604 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7605 PromOp.getOperand(0).getValueType() != MVT::i1) {
7606 // The operand is not yet ready (see comment below).
7607 PromOps.insert(PromOps.begin(), PromOp);
7611 SDValue RepValue = PromOp.getOperand(0);
7612 if (isa<ConstantSDNode>(RepValue))
7613 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7615 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7620 switch (PromOp.getOpcode()) {
7621 default: C = 0; break;
7622 case ISD::SELECT: C = 1; break;
7623 case ISD::SELECT_CC: C = 2; break;
7626 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7627 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7628 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7629 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7630 // The to-be-promoted operands of this node have not yet been
7631 // promoted (this should be rare because we're going through the
7632 // list backward, but if one of the operands has several users in
7633 // this cluster of to-be-promoted nodes, it is possible).
7634 PromOps.insert(PromOps.begin(), PromOp);
7638 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7639 PromOp.getNode()->op_end());
7641 // If there are any constant inputs, make sure they're replaced now.
7642 for (unsigned i = 0; i < 2; ++i)
7643 if (isa<ConstantSDNode>(Ops[C+i]))
7644 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7646 DAG.ReplaceAllUsesOfValueWith(PromOp,
7647 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
7650 // Now we're left with the initial truncation itself.
7651 if (N->getOpcode() == ISD::TRUNCATE)
7652 return N->getOperand(0);
7654 // Otherwise, this is a comparison. The operands to be compared have just
7655 // changed type (to i1), but everything else is the same.
7656 return SDValue(N, 0);
7659 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7660 DAGCombinerInfo &DCI) const {
7661 SelectionDAG &DAG = DCI.DAG;
7664 // If we're tracking CR bits, we need to be careful that we don't have:
7665 // zext(binary-ops(trunc(x), trunc(y)))
7667 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
7668 // such that we're unnecessarily moving things into CR bits that can more
7669 // efficiently stay in GPRs. Note that if we're not certain that the high
7670 // bits are set as required by the final extension, we still may need to do
7671 // some masking to get the proper behavior.
7673 // This same functionality is important on PPC64 when dealing with
7674 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
7675 // the return values of functions. Because it is so similar, it is handled
7678 if (N->getValueType(0) != MVT::i32 &&
7679 N->getValueType(0) != MVT::i64)
7682 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
7683 Subtarget.useCRBits()) ||
7684 (N->getOperand(0).getValueType() == MVT::i32 &&
7685 Subtarget.isPPC64())))
7688 if (N->getOperand(0).getOpcode() != ISD::AND &&
7689 N->getOperand(0).getOpcode() != ISD::OR &&
7690 N->getOperand(0).getOpcode() != ISD::XOR &&
7691 N->getOperand(0).getOpcode() != ISD::SELECT &&
7692 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
7695 SmallVector<SDValue, 4> Inputs;
7696 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
7697 SmallPtrSet<SDNode *, 16> Visited;
7699 // Visit all inputs, collect all binary operations (and, or, xor and
7700 // select) that are all fed by truncations.
7701 while (!BinOps.empty()) {
7702 SDValue BinOp = BinOps.back();
7705 if (!Visited.insert(BinOp.getNode()))
7708 PromOps.push_back(BinOp);
7710 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7711 // The condition of the select is not promoted.
7712 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7714 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7717 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7718 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7719 Inputs.push_back(BinOp.getOperand(i));
7720 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7721 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7722 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7723 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7724 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
7725 BinOps.push_back(BinOp.getOperand(i));
7727 // We have an input that is not a truncation or another binary
7728 // operation; we'll abort this transformation.
7734 // Make sure that this is a self-contained cluster of operations (which
7735 // is not quite the same thing as saying that everything has only one
7737 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7738 if (isa<ConstantSDNode>(Inputs[i]))
7741 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7742 UE = Inputs[i].getNode()->use_end();
7745 if (User != N && !Visited.count(User))
7748 // Make sure that we're not going to promote the non-output-value
7749 // operand(s) or SELECT or SELECT_CC.
7750 // FIXME: Although we could sometimes handle this, and it does occur in
7751 // practice that one of the condition inputs to the select is also one of
7752 // the outputs, we currently can't deal with this.
7753 if (User->getOpcode() == ISD::SELECT) {
7754 if (User->getOperand(0) == Inputs[i])
7756 } else if (User->getOpcode() == ISD::SELECT_CC) {
7757 if (User->getOperand(0) == Inputs[i] ||
7758 User->getOperand(1) == Inputs[i])
7764 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7765 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7766 UE = PromOps[i].getNode()->use_end();
7769 if (User != N && !Visited.count(User))
7772 // Make sure that we're not going to promote the non-output-value
7773 // operand(s) or SELECT or SELECT_CC.
7774 // FIXME: Although we could sometimes handle this, and it does occur in
7775 // practice that one of the condition inputs to the select is also one of
7776 // the outputs, we currently can't deal with this.
7777 if (User->getOpcode() == ISD::SELECT) {
7778 if (User->getOperand(0) == PromOps[i])
7780 } else if (User->getOpcode() == ISD::SELECT_CC) {
7781 if (User->getOperand(0) == PromOps[i] ||
7782 User->getOperand(1) == PromOps[i])
7788 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
7789 bool ReallyNeedsExt = false;
7790 if (N->getOpcode() != ISD::ANY_EXTEND) {
7791 // If all of the inputs are not already sign/zero extended, then
7792 // we'll still need to do that at the end.
7793 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7794 if (isa<ConstantSDNode>(Inputs[i]))
7798 Inputs[i].getOperand(0).getValueSizeInBits();
7799 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
7801 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
7802 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
7803 APInt::getHighBitsSet(OpBits,
7804 OpBits-PromBits))) ||
7805 (N->getOpcode() == ISD::SIGN_EXTEND &&
7806 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
7807 (OpBits-(PromBits-1)))) {
7808 ReallyNeedsExt = true;
7814 // Replace all inputs, either with the truncation operand, or a
7815 // truncation or extension to the final output type.
7816 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7817 // Constant inputs need to be replaced with the to-be-promoted nodes that
7818 // use them because they might have users outside of the cluster of
7820 if (isa<ConstantSDNode>(Inputs[i]))
7823 SDValue InSrc = Inputs[i].getOperand(0);
7824 if (Inputs[i].getValueType() == N->getValueType(0))
7825 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
7826 else if (N->getOpcode() == ISD::SIGN_EXTEND)
7827 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7828 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
7829 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7830 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7831 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
7833 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7834 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
7837 // Replace all operations (these are all the same, but have a different
7838 // (promoted) return type). DAG.getNode will validate that the types of
7839 // a binary operator match, so go through the list in reverse so that
7840 // we've likely promoted both operands first.
7841 while (!PromOps.empty()) {
7842 SDValue PromOp = PromOps.back();
7846 switch (PromOp.getOpcode()) {
7847 default: C = 0; break;
7848 case ISD::SELECT: C = 1; break;
7849 case ISD::SELECT_CC: C = 2; break;
7852 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7853 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
7854 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7855 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
7856 // The to-be-promoted operands of this node have not yet been
7857 // promoted (this should be rare because we're going through the
7858 // list backward, but if one of the operands has several users in
7859 // this cluster of to-be-promoted nodes, it is possible).
7860 PromOps.insert(PromOps.begin(), PromOp);
7864 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7865 PromOp.getNode()->op_end());
7867 // If this node has constant inputs, then they'll need to be promoted here.
7868 for (unsigned i = 0; i < 2; ++i) {
7869 if (!isa<ConstantSDNode>(Ops[C+i]))
7871 if (Ops[C+i].getValueType() == N->getValueType(0))
7874 if (N->getOpcode() == ISD::SIGN_EXTEND)
7875 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7876 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7877 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7879 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7882 DAG.ReplaceAllUsesOfValueWith(PromOp,
7883 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
7886 // Now we're left with the initial extension itself.
7887 if (!ReallyNeedsExt)
7888 return N->getOperand(0);
7890 // To zero extend, just mask off everything except for the first bit (in the
7892 if (N->getOpcode() == ISD::ZERO_EXTEND)
7893 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
7894 DAG.getConstant(APInt::getLowBitsSet(
7895 N->getValueSizeInBits(0), PromBits),
7896 N->getValueType(0)));
7898 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
7899 "Invalid extension type");
7900 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
7902 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
7903 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
7904 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
7905 N->getOperand(0), ShiftCst), ShiftCst);
7908 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
7909 DAGCombinerInfo &DCI) const {
7910 const TargetMachine &TM = getTargetMachine();
7911 SelectionDAG &DAG = DCI.DAG;
7913 switch (N->getOpcode()) {
7916 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7917 if (C->isNullValue()) // 0 << V -> 0.
7918 return N->getOperand(0);
7922 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7923 if (C->isNullValue()) // 0 >>u V -> 0.
7924 return N->getOperand(0);
7928 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7929 if (C->isNullValue() || // 0 >>s V -> 0.
7930 C->isAllOnesValue()) // -1 >>s V -> -1.
7931 return N->getOperand(0);
7934 case ISD::SIGN_EXTEND:
7935 case ISD::ZERO_EXTEND:
7936 case ISD::ANY_EXTEND:
7937 return DAGCombineExtBoolTrunc(N, DCI);
7940 case ISD::SELECT_CC:
7941 return DAGCombineTruncBoolExt(N, DCI);
7943 assert(TM.Options.UnsafeFPMath &&
7944 "Reciprocal estimates require UnsafeFPMath");
7946 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
7948 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
7950 DCI.AddToWorklist(RV.getNode());
7951 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7952 N->getOperand(0), RV);
7954 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
7955 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7957 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7960 DCI.AddToWorklist(RV.getNode());
7961 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
7962 N->getValueType(0), RV);
7963 DCI.AddToWorklist(RV.getNode());
7964 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7965 N->getOperand(0), RV);
7967 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
7968 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7970 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7973 DCI.AddToWorklist(RV.getNode());
7974 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
7975 N->getValueType(0), RV,
7976 N->getOperand(1).getOperand(1));
7977 DCI.AddToWorklist(RV.getNode());
7978 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7979 N->getOperand(0), RV);
7983 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
7985 DCI.AddToWorklist(RV.getNode());
7986 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7987 N->getOperand(0), RV);
7993 assert(TM.Options.UnsafeFPMath &&
7994 "Reciprocal estimates require UnsafeFPMath");
7996 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
7998 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
8000 DCI.AddToWorklist(RV.getNode());
8001 RV = DAGCombineFastRecip(RV, DCI);
8003 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
8004 // this case and force the answer to 0.
8006 EVT VT = RV.getValueType();
8008 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
8009 if (VT.isVector()) {
8010 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
8011 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
8015 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
8016 N->getOperand(0), Zero, ISD::SETEQ);
8017 DCI.AddToWorklist(ZeroCmp.getNode());
8018 DCI.AddToWorklist(RV.getNode());
8020 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
8028 case ISD::SINT_TO_FP:
8029 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
8030 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8031 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8032 // We allow the src/dst to be either f32/f64, but the intermediate
8033 // type must be i64.
8034 if (N->getOperand(0).getValueType() == MVT::i64 &&
8035 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
8036 SDValue Val = N->getOperand(0).getOperand(0);
8037 if (Val.getValueType() == MVT::f32) {
8038 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8039 DCI.AddToWorklist(Val.getNode());
8042 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8043 DCI.AddToWorklist(Val.getNode());
8044 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8045 DCI.AddToWorklist(Val.getNode());
8046 if (N->getValueType(0) == MVT::f32) {
8047 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8048 DAG.getIntPtrConstant(0));
8049 DCI.AddToWorklist(Val.getNode());
8052 } else if (N->getOperand(0).getValueType() == MVT::i32) {
8053 // If the intermediate type is i32, we can avoid the load/store here
8060 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8061 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8062 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8063 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8064 N->getOperand(1).getValueType() == MVT::i32 &&
8065 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8066 SDValue Val = N->getOperand(1).getOperand(0);
8067 if (Val.getValueType() == MVT::f32) {
8068 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8069 DCI.AddToWorklist(Val.getNode());
8071 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8072 DCI.AddToWorklist(Val.getNode());
8075 N->getOperand(0), Val, N->getOperand(2),
8076 DAG.getValueType(N->getOperand(1).getValueType())
8079 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8080 DAG.getVTList(MVT::Other), Ops,
8081 cast<StoreSDNode>(N)->getMemoryVT(),
8082 cast<StoreSDNode>(N)->getMemOperand());
8083 DCI.AddToWorklist(Val.getNode());
8087 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8088 if (cast<StoreSDNode>(N)->isUnindexed() &&
8089 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8090 N->getOperand(1).getNode()->hasOneUse() &&
8091 (N->getOperand(1).getValueType() == MVT::i32 ||
8092 N->getOperand(1).getValueType() == MVT::i16 ||
8093 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8094 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8095 N->getOperand(1).getValueType() == MVT::i64))) {
8096 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8097 // Do an any-extend to 32-bits if this is a half-word input.
8098 if (BSwapOp.getValueType() == MVT::i16)
8099 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8102 N->getOperand(0), BSwapOp, N->getOperand(2),
8103 DAG.getValueType(N->getOperand(1).getValueType())
8106 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8107 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8108 cast<StoreSDNode>(N)->getMemOperand());
8112 LoadSDNode *LD = cast<LoadSDNode>(N);
8113 EVT VT = LD->getValueType(0);
8114 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8115 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8116 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8117 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8118 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8119 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8120 LD->getAlignment() < ABIAlignment) {
8121 // This is a type-legal unaligned Altivec load.
8122 SDValue Chain = LD->getChain();
8123 SDValue Ptr = LD->getBasePtr();
8124 bool isLittleEndian = Subtarget.isLittleEndian();
8126 // This implements the loading of unaligned vectors as described in
8127 // the venerable Apple Velocity Engine overview. Specifically:
8128 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8129 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8131 // The general idea is to expand a sequence of one or more unaligned
8132 // loads into an alignment-based permutation-control instruction (lvsl
8133 // or lvsr), a series of regular vector loads (which always truncate
8134 // their input address to an aligned address), and a series of
8135 // permutations. The results of these permutations are the requested
8136 // loaded values. The trick is that the last "extra" load is not taken
8137 // from the address you might suspect (sizeof(vector) bytes after the
8138 // last requested load), but rather sizeof(vector) - 1 bytes after the
8139 // last requested vector. The point of this is to avoid a page fault if
8140 // the base address happened to be aligned. This works because if the
8141 // base address is aligned, then adding less than a full vector length
8142 // will cause the last vector in the sequence to be (re)loaded.
8143 // Otherwise, the next vector will be fetched as you might suspect was
8146 // We might be able to reuse the permutation generation from
8147 // a different base address offset from this one by an aligned amount.
8148 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8149 // optimization later.
8150 Intrinsic::ID Intr = (isLittleEndian ?
8151 Intrinsic::ppc_altivec_lvsr :
8152 Intrinsic::ppc_altivec_lvsl);
8153 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8155 // Refine the alignment of the original load (a "new" load created here
8156 // which was identical to the first except for the alignment would be
8157 // merged with the existing node regardless).
8158 MachineFunction &MF = DAG.getMachineFunction();
8159 MachineMemOperand *MMO =
8160 MF.getMachineMemOperand(LD->getPointerInfo(),
8161 LD->getMemOperand()->getFlags(),
8162 LD->getMemoryVT().getStoreSize(),
8164 LD->refineAlignment(MMO);
8165 SDValue BaseLoad = SDValue(LD, 0);
8167 // Note that the value of IncOffset (which is provided to the next
8168 // load's pointer info offset value, and thus used to calculate the
8169 // alignment), and the value of IncValue (which is actually used to
8170 // increment the pointer value) are different! This is because we
8171 // require the next load to appear to be aligned, even though it
8172 // is actually offset from the base pointer by a lesser amount.
8173 int IncOffset = VT.getSizeInBits() / 8;
8174 int IncValue = IncOffset;
8176 // Walk (both up and down) the chain looking for another load at the real
8177 // (aligned) offset (the alignment of the other load does not matter in
8178 // this case). If found, then do not use the offset reduction trick, as
8179 // that will prevent the loads from being later combined (as they would
8180 // otherwise be duplicates).
8181 if (!findConsecutiveLoad(LD, DAG))
8184 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8185 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8188 DAG.getLoad(VT, dl, Chain, Ptr,
8189 LD->getPointerInfo().getWithOffset(IncOffset),
8190 LD->isVolatile(), LD->isNonTemporal(),
8191 LD->isInvariant(), ABIAlignment);
8193 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8194 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8196 if (BaseLoad.getValueType() != MVT::v4i32)
8197 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
8199 if (ExtraLoad.getValueType() != MVT::v4i32)
8200 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
8202 // Because vperm has a big-endian bias, we must reverse the order
8203 // of the input vectors and complement the permute control vector
8204 // when generating little endian code. We have already handled the
8205 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8206 // and ExtraLoad here.
8209 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8210 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8212 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8213 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8215 if (VT != MVT::v4i32)
8216 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8218 // Now we need to be really careful about how we update the users of the
8219 // original load. We cannot just call DCI.CombineTo (or
8220 // DAG.ReplaceAllUsesWith for that matter), because the load still has
8221 // uses created here (the permutation for example) that need to stay.
8222 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
8224 SDUse &Use = UI.getUse();
8226 // Note: BaseLoad is checked here because it might not be N, but a
8228 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
8229 User == TF.getNode() || Use.getResNo() > 1) {
8234 SDValue To = Use.getResNo() ? TF : Perm;
8237 SmallVector<SDValue, 8> Ops;
8238 for (const SDUse &O : User->ops()) {
8245 DAG.UpdateNodeOperands(User, Ops);
8248 return SDValue(N, 0);
8252 case ISD::INTRINSIC_WO_CHAIN: {
8253 bool isLittleEndian = Subtarget.isLittleEndian();
8254 Intrinsic::ID Intr = (isLittleEndian ?
8255 Intrinsic::ppc_altivec_lvsr :
8256 Intrinsic::ppc_altivec_lvsl);
8257 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8258 N->getOperand(1)->getOpcode() == ISD::ADD) {
8259 SDValue Add = N->getOperand(1);
8261 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8262 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8263 Add.getValueType().getScalarType().getSizeInBits()))) {
8264 SDNode *BasePtr = Add->getOperand(0).getNode();
8265 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8266 UE = BasePtr->use_end(); UI != UE; ++UI) {
8267 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8268 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8270 // We've found another LVSL/LVSR, and this address is an aligned
8271 // multiple of that one. The results will be the same, so use the
8272 // one we've just found instead.
8274 return SDValue(*UI, 0);
8283 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8284 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8285 N->getOperand(0).hasOneUse() &&
8286 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8287 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8288 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8289 N->getValueType(0) == MVT::i64))) {
8290 SDValue Load = N->getOperand(0);
8291 LoadSDNode *LD = cast<LoadSDNode>(Load);
8292 // Create the byte-swapping load.
8294 LD->getChain(), // Chain
8295 LD->getBasePtr(), // Ptr
8296 DAG.getValueType(N->getValueType(0)) // VT
8299 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8300 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8301 MVT::i64 : MVT::i32, MVT::Other),
8302 Ops, LD->getMemoryVT(), LD->getMemOperand());
8304 // If this is an i16 load, insert the truncate.
8305 SDValue ResVal = BSLoad;
8306 if (N->getValueType(0) == MVT::i16)
8307 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8309 // First, combine the bswap away. This makes the value produced by the
8311 DCI.CombineTo(N, ResVal);
8313 // Next, combine the load away, we give it a bogus result value but a real
8314 // chain result. The result value is dead because the bswap is dead.
8315 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8317 // Return N so it doesn't get rechecked!
8318 return SDValue(N, 0);
8322 case PPCISD::VCMP: {
8323 // If a VCMPo node already exists with exactly the same operands as this
8324 // node, use its result instead of this node (VCMPo computes both a CR6 and
8325 // a normal output).
8327 if (!N->getOperand(0).hasOneUse() &&
8328 !N->getOperand(1).hasOneUse() &&
8329 !N->getOperand(2).hasOneUse()) {
8331 // Scan all of the users of the LHS, looking for VCMPo's that match.
8332 SDNode *VCMPoNode = nullptr;
8334 SDNode *LHSN = N->getOperand(0).getNode();
8335 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8337 if (UI->getOpcode() == PPCISD::VCMPo &&
8338 UI->getOperand(1) == N->getOperand(1) &&
8339 UI->getOperand(2) == N->getOperand(2) &&
8340 UI->getOperand(0) == N->getOperand(0)) {
8345 // If there is no VCMPo node, or if the flag value has a single use, don't
8347 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8350 // Look at the (necessarily single) use of the flag value. If it has a
8351 // chain, this transformation is more complex. Note that multiple things
8352 // could use the value result, which we should ignore.
8353 SDNode *FlagUser = nullptr;
8354 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8355 FlagUser == nullptr; ++UI) {
8356 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8358 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8359 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8366 // If the user is a MFOCRF instruction, we know this is safe.
8367 // Otherwise we give up for right now.
8368 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8369 return SDValue(VCMPoNode, 0);
8374 SDValue Cond = N->getOperand(1);
8375 SDValue Target = N->getOperand(2);
8377 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8378 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8379 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8381 // We now need to make the intrinsic dead (it cannot be instruction
8383 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8384 assert(Cond.getNode()->hasOneUse() &&
8385 "Counter decrement has more than one use");
8387 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8388 N->getOperand(0), Target);
8393 // If this is a branch on an altivec predicate comparison, lower this so
8394 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8395 // lowering is done pre-legalize, because the legalizer lowers the predicate
8396 // compare down to code that is difficult to reassemble.
8397 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8398 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8400 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8401 // value. If so, pass-through the AND to get to the intrinsic.
8402 if (LHS.getOpcode() == ISD::AND &&
8403 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8404 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8405 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8406 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8407 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8409 LHS = LHS.getOperand(0);
8411 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8412 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8413 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8414 isa<ConstantSDNode>(RHS)) {
8415 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8416 "Counter decrement comparison is not EQ or NE");
8418 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8419 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8420 (CC == ISD::SETNE && !Val);
8422 // We now need to make the intrinsic dead (it cannot be instruction
8424 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8425 assert(LHS.getNode()->hasOneUse() &&
8426 "Counter decrement has more than one use");
8428 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8429 N->getOperand(0), N->getOperand(4));
8435 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8436 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8437 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8438 assert(isDot && "Can't compare against a vector result!");
8440 // If this is a comparison against something other than 0/1, then we know
8441 // that the condition is never/always true.
8442 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8443 if (Val != 0 && Val != 1) {
8444 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8445 return N->getOperand(0);
8446 // Always !=, turn it into an unconditional branch.
8447 return DAG.getNode(ISD::BR, dl, MVT::Other,
8448 N->getOperand(0), N->getOperand(4));
8451 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8453 // Create the PPCISD altivec 'dot' comparison node.
8455 LHS.getOperand(2), // LHS of compare
8456 LHS.getOperand(3), // RHS of compare
8457 DAG.getConstant(CompareOpc, MVT::i32)
8459 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8460 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8462 // Unpack the result based on how the target uses it.
8463 PPC::Predicate CompOpc;
8464 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8465 default: // Can't happen, don't crash on invalid number though.
8466 case 0: // Branch on the value of the EQ bit of CR6.
8467 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8469 case 1: // Branch on the inverted value of the EQ bit of CR6.
8470 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8472 case 2: // Branch on the value of the LT bit of CR6.
8473 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8475 case 3: // Branch on the inverted value of the LT bit of CR6.
8476 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8480 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8481 DAG.getConstant(CompOpc, MVT::i32),
8482 DAG.getRegister(PPC::CR6, MVT::i32),
8483 N->getOperand(4), CompNode.getValue(1));
8492 //===----------------------------------------------------------------------===//
8493 // Inline Assembly Support
8494 //===----------------------------------------------------------------------===//
8496 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8499 const SelectionDAG &DAG,
8500 unsigned Depth) const {
8501 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8502 switch (Op.getOpcode()) {
8504 case PPCISD::LBRX: {
8505 // lhbrx is known to have the top bits cleared out.
8506 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8507 KnownZero = 0xFFFF0000;
8510 case ISD::INTRINSIC_WO_CHAIN: {
8511 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8513 case Intrinsic::ppc_altivec_vcmpbfp_p:
8514 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8515 case Intrinsic::ppc_altivec_vcmpequb_p:
8516 case Intrinsic::ppc_altivec_vcmpequh_p:
8517 case Intrinsic::ppc_altivec_vcmpequw_p:
8518 case Intrinsic::ppc_altivec_vcmpgefp_p:
8519 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8520 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8521 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8522 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8523 case Intrinsic::ppc_altivec_vcmpgtub_p:
8524 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8525 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8526 KnownZero = ~1U; // All bits but the low one are known to be zero.
8534 /// getConstraintType - Given a constraint, return the type of
8535 /// constraint it is for this target.
8536 PPCTargetLowering::ConstraintType
8537 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8538 if (Constraint.size() == 1) {
8539 switch (Constraint[0]) {
8546 return C_RegisterClass;
8548 // FIXME: While Z does indicate a memory constraint, it specifically
8549 // indicates an r+r address (used in conjunction with the 'y' modifier
8550 // in the replacement string). Currently, we're forcing the base
8551 // register to be r0 in the asm printer (which is interpreted as zero)
8552 // and forming the complete address in the second register. This is
8556 } else if (Constraint == "wc") { // individual CR bits.
8557 return C_RegisterClass;
8558 } else if (Constraint == "wa" || Constraint == "wd" ||
8559 Constraint == "wf" || Constraint == "ws") {
8560 return C_RegisterClass; // VSX registers.
8562 return TargetLowering::getConstraintType(Constraint);
8565 /// Examine constraint type and operand type and determine a weight value.
8566 /// This object must already have been set up with the operand type
8567 /// and the current alternative constraint selected.
8568 TargetLowering::ConstraintWeight
8569 PPCTargetLowering::getSingleConstraintMatchWeight(
8570 AsmOperandInfo &info, const char *constraint) const {
8571 ConstraintWeight weight = CW_Invalid;
8572 Value *CallOperandVal = info.CallOperandVal;
8573 // If we don't have a value, we can't do a match,
8574 // but allow it at the lowest weight.
8575 if (!CallOperandVal)
8577 Type *type = CallOperandVal->getType();
8579 // Look at the constraint type.
8580 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8581 return CW_Register; // an individual CR bit.
8582 else if ((StringRef(constraint) == "wa" ||
8583 StringRef(constraint) == "wd" ||
8584 StringRef(constraint) == "wf") &&
8587 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8590 switch (*constraint) {
8592 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8595 if (type->isIntegerTy())
8596 weight = CW_Register;
8599 if (type->isFloatTy())
8600 weight = CW_Register;
8603 if (type->isDoubleTy())
8604 weight = CW_Register;
8607 if (type->isVectorTy())
8608 weight = CW_Register;
8611 weight = CW_Register;
8620 std::pair<unsigned, const TargetRegisterClass*>
8621 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8623 if (Constraint.size() == 1) {
8624 // GCC RS6000 Constraint Letters
8625 switch (Constraint[0]) {
8627 if (VT == MVT::i64 && Subtarget.isPPC64())
8628 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8629 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8631 if (VT == MVT::i64 && Subtarget.isPPC64())
8632 return std::make_pair(0U, &PPC::G8RCRegClass);
8633 return std::make_pair(0U, &PPC::GPRCRegClass);
8635 if (VT == MVT::f32 || VT == MVT::i32)
8636 return std::make_pair(0U, &PPC::F4RCRegClass);
8637 if (VT == MVT::f64 || VT == MVT::i64)
8638 return std::make_pair(0U, &PPC::F8RCRegClass);
8641 return std::make_pair(0U, &PPC::VRRCRegClass);
8643 return std::make_pair(0U, &PPC::CRRCRegClass);
8645 } else if (Constraint == "wc") { // an individual CR bit.
8646 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8647 } else if (Constraint == "wa" || Constraint == "wd" ||
8648 Constraint == "wf") {
8649 return std::make_pair(0U, &PPC::VSRCRegClass);
8650 } else if (Constraint == "ws") {
8651 return std::make_pair(0U, &PPC::VSFRCRegClass);
8654 std::pair<unsigned, const TargetRegisterClass*> R =
8655 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8657 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8658 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8659 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8661 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8662 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8663 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
8664 PPC::GPRCRegClass.contains(R.first)) {
8665 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
8666 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8667 PPC::sub_32, &PPC::G8RCRegClass),
8668 &PPC::G8RCRegClass);
8675 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8676 /// vector. If it is invalid, don't add anything to Ops.
8677 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8678 std::string &Constraint,
8679 std::vector<SDValue>&Ops,
8680 SelectionDAG &DAG) const {
8683 // Only support length 1 constraints.
8684 if (Constraint.length() > 1) return;
8686 char Letter = Constraint[0];
8697 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
8698 if (!CST) return; // Must be an immediate to match.
8699 unsigned Value = CST->getZExtValue();
8701 default: llvm_unreachable("Unknown constraint letter!");
8702 case 'I': // "I" is a signed 16-bit constant.
8703 if ((short)Value == (int)Value)
8704 Result = DAG.getTargetConstant(Value, Op.getValueType());
8706 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
8707 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
8708 if ((short)Value == 0)
8709 Result = DAG.getTargetConstant(Value, Op.getValueType());
8711 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
8712 if ((Value >> 16) == 0)
8713 Result = DAG.getTargetConstant(Value, Op.getValueType());
8715 case 'M': // "M" is a constant that is greater than 31.
8717 Result = DAG.getTargetConstant(Value, Op.getValueType());
8719 case 'N': // "N" is a positive constant that is an exact power of two.
8720 if ((int)Value > 0 && isPowerOf2_32(Value))
8721 Result = DAG.getTargetConstant(Value, Op.getValueType());
8723 case 'O': // "O" is the constant zero.
8725 Result = DAG.getTargetConstant(Value, Op.getValueType());
8727 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
8728 if ((short)-Value == (int)-Value)
8729 Result = DAG.getTargetConstant(Value, Op.getValueType());
8736 if (Result.getNode()) {
8737 Ops.push_back(Result);
8741 // Handle standard constraint letters.
8742 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8745 // isLegalAddressingMode - Return true if the addressing mode represented
8746 // by AM is legal for this target, for a load/store of the specified type.
8747 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
8749 // FIXME: PPC does not allow r+i addressing modes for vectors!
8751 // PPC allows a sign-extended 16-bit immediate field.
8752 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
8755 // No global is ever allowed as a base.
8759 // PPC only support r+r,
8761 case 0: // "r+i" or just "i", depending on HasBaseReg.
8764 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
8766 // Otherwise we have r+r or r+i.
8769 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
8771 // Allow 2*r as r+r.
8774 // No other scales are supported.
8781 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
8782 SelectionDAG &DAG) const {
8783 MachineFunction &MF = DAG.getMachineFunction();
8784 MachineFrameInfo *MFI = MF.getFrameInfo();
8785 MFI->setReturnAddressIsTaken(true);
8787 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
8791 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8793 // Make sure the function does not optimize away the store of the RA to
8795 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
8796 FuncInfo->setLRStoreRequired();
8797 bool isPPC64 = Subtarget.isPPC64();
8798 bool isDarwinABI = Subtarget.isDarwinABI();
8801 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
8804 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
8805 isPPC64? MVT::i64 : MVT::i32);
8806 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8807 DAG.getNode(ISD::ADD, dl, getPointerTy(),
8809 MachinePointerInfo(), false, false, false, 0);
8812 // Just load the return address off the stack.
8813 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
8814 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8815 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
8818 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
8819 SelectionDAG &DAG) const {
8821 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8823 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
8824 bool isPPC64 = PtrVT == MVT::i64;
8826 MachineFunction &MF = DAG.getMachineFunction();
8827 MachineFrameInfo *MFI = MF.getFrameInfo();
8828 MFI->setFrameAddressIsTaken(true);
8830 // Naked functions never have a frame pointer, and so we use r1. For all
8831 // other functions, this decision must be delayed until during PEI.
8833 if (MF.getFunction()->getAttributes().hasAttribute(
8834 AttributeSet::FunctionIndex, Attribute::Naked))
8835 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
8837 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
8839 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
8842 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
8843 FrameAddr, MachinePointerInfo(), false, false,
8848 // FIXME? Maybe this could be a TableGen attribute on some registers and
8849 // this table could be generated automatically from RegInfo.
8850 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
8852 bool isPPC64 = Subtarget.isPPC64();
8853 bool isDarwinABI = Subtarget.isDarwinABI();
8855 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
8856 (!isPPC64 && VT != MVT::i32))
8857 report_fatal_error("Invalid register global variable type");
8859 bool is64Bit = isPPC64 && VT == MVT::i64;
8860 unsigned Reg = StringSwitch<unsigned>(RegName)
8861 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
8862 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
8863 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
8864 (is64Bit ? PPC::X13 : PPC::R13))
8869 report_fatal_error("Invalid register name global variable");
8873 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
8874 // The PowerPC target isn't yet aware of offsets.
8878 /// getOptimalMemOpType - Returns the target specific optimal type for load
8879 /// and store operations as a result of memset, memcpy, and memmove
8880 /// lowering. If DstAlign is zero that means it's safe to destination
8881 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
8882 /// means there isn't a need to check it against alignment requirement,
8883 /// probably because the source does not need to be loaded. If 'IsMemset' is
8884 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
8885 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
8886 /// source is constant so it does not need to be loaded.
8887 /// It returns EVT::Other if the type should be determined using generic
8888 /// target-independent logic.
8889 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
8890 unsigned DstAlign, unsigned SrcAlign,
8891 bool IsMemset, bool ZeroMemset,
8893 MachineFunction &MF) const {
8894 if (Subtarget.isPPC64()) {
8901 /// \brief Returns true if it is beneficial to convert a load of a constant
8902 /// to just the constant itself.
8903 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
8905 assert(Ty->isIntegerTy());
8907 unsigned BitSize = Ty->getPrimitiveSizeInBits();
8908 if (BitSize == 0 || BitSize > 64)
8913 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
8914 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
8916 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
8917 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
8918 return NumBits1 == 64 && NumBits2 == 32;
8921 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
8922 if (!VT1.isInteger() || !VT2.isInteger())
8924 unsigned NumBits1 = VT1.getSizeInBits();
8925 unsigned NumBits2 = VT2.getSizeInBits();
8926 return NumBits1 == 64 && NumBits2 == 32;
8929 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
8930 return isInt<16>(Imm) || isUInt<16>(Imm);
8933 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
8934 return isInt<16>(Imm) || isUInt<16>(Imm);
8937 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
8940 if (DisablePPCUnaligned)
8943 // PowerPC supports unaligned memory access for simple non-vector types.
8944 // Although accessing unaligned addresses is not as efficient as accessing
8945 // aligned addresses, it is generally more efficient than manual expansion,
8946 // and generally only traps for software emulation when crossing page
8952 if (VT.getSimpleVT().isVector()) {
8953 if (Subtarget.hasVSX()) {
8954 if (VT != MVT::v2f64 && VT != MVT::v2i64)
8961 if (VT == MVT::ppcf128)
8970 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
8971 VT = VT.getScalarType();
8976 switch (VT.getSimpleVT().SimpleTy) {
8988 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
8989 EVT VT , unsigned DefinedValues) const {
8990 if (VT == MVT::v2i64)
8993 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
8996 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
8997 if (DisableILPPref || Subtarget.enableMachineScheduler())
8998 return TargetLowering::getSchedulingPreference(N);
9003 // Create a fast isel object.
9005 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9006 const TargetLibraryInfo *LibInfo) const {
9007 return PPC::createFastISel(FuncInfo, LibInfo);