1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCTargetMachine.h"
16 #include "llvm/ADT/VectorExtras.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/Constants.h"
23 #include "llvm/Function.h"
24 #include "llvm/Support/MathExtras.h"
25 #include "llvm/Target/TargetOptions.h"
28 PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
29 : TargetLowering(TM) {
31 // Fold away setcc operations if possible.
32 setSetCCIsExpensive();
35 // Use _setjmp/_longjmp instead of setjmp/longjmp.
36 setUseUnderscoreSetJmpLongJmp(true);
38 // Set up the register classes.
39 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
40 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
41 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
43 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
44 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
46 // PowerPC has no intrinsics for these particular operations
47 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
48 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
49 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
51 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
52 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
53 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
55 // PowerPC has no SREM/UREM instructions
56 setOperationAction(ISD::SREM, MVT::i32, Expand);
57 setOperationAction(ISD::UREM, MVT::i32, Expand);
59 // We don't support sin/cos/sqrt/fmod
60 setOperationAction(ISD::FSIN , MVT::f64, Expand);
61 setOperationAction(ISD::FCOS , MVT::f64, Expand);
62 setOperationAction(ISD::FREM , MVT::f64, Expand);
63 setOperationAction(ISD::FSIN , MVT::f32, Expand);
64 setOperationAction(ISD::FCOS , MVT::f32, Expand);
65 setOperationAction(ISD::FREM , MVT::f32, Expand);
67 // If we're enabling GP optimizations, use hardware square root
68 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
69 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
70 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
73 // PowerPC does not have BSWAP, CTPOP or CTTZ
74 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
75 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
76 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
78 // PowerPC does not have ROTR
79 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
81 // PowerPC does not have Select
82 setOperationAction(ISD::SELECT, MVT::i32, Expand);
83 setOperationAction(ISD::SELECT, MVT::f32, Expand);
84 setOperationAction(ISD::SELECT, MVT::f64, Expand);
86 // PowerPC wants to turn select_cc of FP into fsel when possible.
87 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
88 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
90 // PowerPC wants to optimize integer setcc a bit
91 setOperationAction(ISD::SETCC, MVT::i32, Custom);
93 // PowerPC does not have BRCOND* which requires SetCC
94 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
95 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
97 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
98 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
100 // PowerPC does not have [U|S]INT_TO_FP
101 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
102 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
104 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
105 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
107 // PowerPC does not have truncstore for i1.
108 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
110 // Support label based line numbers.
111 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
112 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
113 // FIXME - use subtarget debug flags
114 if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
115 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
117 // We want to legalize GlobalAddress and ConstantPool nodes into the
118 // appropriate instructions to materialize the address.
119 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
120 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
122 // RET must be custom lowered, to meet ABI requirements
123 setOperationAction(ISD::RET , MVT::Other, Custom);
125 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
126 setOperationAction(ISD::VASTART , MVT::Other, Custom);
128 // Use the default implementation.
129 setOperationAction(ISD::VAARG , MVT::Other, Expand);
130 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
131 setOperationAction(ISD::VAEND , MVT::Other, Expand);
132 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
133 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
134 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
136 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
137 // They also have instructions for converting between i64 and fp.
138 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
139 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
140 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
141 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
143 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
144 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
147 if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) {
148 // 64 bit PowerPC implementations can support i64 types directly
149 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
150 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
151 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
153 // 32 bit PowerPC wants to expand i64 shifts itself.
154 setOperationAction(ISD::SHL, MVT::i64, Custom);
155 setOperationAction(ISD::SRL, MVT::i64, Custom);
156 setOperationAction(ISD::SRA, MVT::i64, Custom);
159 // First set operation action for all vector types to expand. Then we
160 // will selectively turn on ones that can be effectively codegen'd.
161 for (unsigned VT = (unsigned)MVT::Vector + 1;
162 VT != (unsigned)MVT::LAST_VALUETYPE; VT++) {
163 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Expand);
164 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Expand);
165 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
166 setOperationAction(ISD::LOAD, (MVT::ValueType)VT, Expand);
169 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
170 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
171 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
173 setOperationAction(ISD::ADD , MVT::v4f32, Legal);
174 setOperationAction(ISD::SUB , MVT::v4f32, Legal);
175 setOperationAction(ISD::MUL , MVT::v4f32, Legal);
176 setOperationAction(ISD::LOAD , MVT::v4f32, Legal);
177 setOperationAction(ISD::ADD , MVT::v4i32, Legal);
178 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
179 // FIXME: We don't support any ConstantVec's yet. We should custom expand
181 setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand);
182 setOperationAction(ISD::ConstantVec, MVT::v4i32, Expand);
185 setSetCCResultContents(ZeroOrOneSetCCResult);
186 setStackPointerRegisterToSaveRestore(PPC::R1);
188 // We have target-specific dag combine patterns for the following nodes:
189 setTargetDAGCombine(ISD::SINT_TO_FP);
190 setTargetDAGCombine(ISD::STORE);
192 computeRegisterProperties();
195 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
198 case PPCISD::FSEL: return "PPCISD::FSEL";
199 case PPCISD::FCFID: return "PPCISD::FCFID";
200 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
201 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
202 case PPCISD::STFIWX: return "PPCISD::STFIWX";
203 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
204 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
205 case PPCISD::Hi: return "PPCISD::Hi";
206 case PPCISD::Lo: return "PPCISD::Lo";
207 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
208 case PPCISD::SRL: return "PPCISD::SRL";
209 case PPCISD::SRA: return "PPCISD::SRA";
210 case PPCISD::SHL: return "PPCISD::SHL";
211 case PPCISD::CALL: return "PPCISD::CALL";
212 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
216 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
217 static bool isFloatingPointZero(SDOperand Op) {
218 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
219 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
220 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
221 // Maybe this has already been legalized into the constant pool?
222 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
223 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
224 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
229 /// LowerOperation - Provide custom lowering hooks for some operations.
231 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
232 switch (Op.getOpcode()) {
233 default: assert(0 && "Wasn't expecting to be able to lower this!");
234 case ISD::FP_TO_SINT: {
235 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
236 SDOperand Src = Op.getOperand(0);
237 if (Src.getValueType() == MVT::f32)
238 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
241 switch (Op.getValueType()) {
242 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
244 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
247 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
251 // Convert the FP value to an int value through memory.
252 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
253 if (Op.getValueType() == MVT::i32)
254 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
257 case ISD::SINT_TO_FP: {
258 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
259 "Unhandled SINT_TO_FP type in custom expander!");
260 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
261 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
262 if (MVT::f32 == Op.getValueType())
263 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
266 case ISD::SELECT_CC: {
267 // Turn FP only select_cc's into fsel instructions.
268 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
269 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
272 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
274 // Cannot handle SETEQ/SETNE.
275 if (CC == ISD::SETEQ || CC == ISD::SETNE) break;
277 MVT::ValueType ResVT = Op.getValueType();
278 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
279 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
280 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
282 // If the RHS of the comparison is a 0.0, we don't need to do the
283 // subtraction at all.
284 if (isFloatingPointZero(RHS))
286 default: break; // SETUO etc aren't handled by fsel.
289 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
292 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
293 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
294 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
297 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
300 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
301 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
302 return DAG.getNode(PPCISD::FSEL, ResVT,
303 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
308 default: break; // SETUO etc aren't handled by fsel.
311 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
312 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
313 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
314 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
317 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
318 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
319 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
320 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
323 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
324 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
325 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
326 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
329 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
330 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
331 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
332 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
337 assert(Op.getValueType() == MVT::i64 &&
338 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
339 // The generic code does a fine job expanding shift by a constant.
340 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
342 // Otherwise, expand into a bunch of logical ops. Note that these ops
343 // depend on the PPC behavior for oversized shift amounts.
344 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
345 DAG.getConstant(0, MVT::i32));
346 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
347 DAG.getConstant(1, MVT::i32));
348 SDOperand Amt = Op.getOperand(1);
350 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
351 DAG.getConstant(32, MVT::i32), Amt);
352 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
353 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
354 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
355 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
356 DAG.getConstant(-32U, MVT::i32));
357 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
358 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
359 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
360 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
363 assert(Op.getValueType() == MVT::i64 &&
364 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
365 // The generic code does a fine job expanding shift by a constant.
366 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
368 // Otherwise, expand into a bunch of logical ops. Note that these ops
369 // depend on the PPC behavior for oversized shift amounts.
370 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
371 DAG.getConstant(0, MVT::i32));
372 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
373 DAG.getConstant(1, MVT::i32));
374 SDOperand Amt = Op.getOperand(1);
376 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
377 DAG.getConstant(32, MVT::i32), Amt);
378 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
379 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
380 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
381 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
382 DAG.getConstant(-32U, MVT::i32));
383 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
384 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
385 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
386 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
389 assert(Op.getValueType() == MVT::i64 &&
390 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
391 // The generic code does a fine job expanding shift by a constant.
392 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
394 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
395 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
396 DAG.getConstant(0, MVT::i32));
397 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
398 DAG.getConstant(1, MVT::i32));
399 SDOperand Amt = Op.getOperand(1);
401 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
402 DAG.getConstant(32, MVT::i32), Amt);
403 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
404 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
405 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
406 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
407 DAG.getConstant(-32U, MVT::i32));
408 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
409 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
410 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
411 Tmp4, Tmp6, ISD::SETLE);
412 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
414 case ISD::ConstantPool: {
415 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
416 Constant *C = CP->get();
417 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32, CP->getAlignment());
418 SDOperand Zero = DAG.getConstant(0, MVT::i32);
420 if (getTargetMachine().getRelocationModel() == Reloc::Static) {
421 // Generate non-pic code that has direct accesses to the constant pool.
422 // The address of the global is just (hi(&g)+lo(&g)).
423 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
424 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
425 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
428 // Only lower ConstantPool on Darwin.
429 if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break;
430 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
431 if (getTargetMachine().getRelocationModel() == Reloc::PIC) {
432 // With PIC, the first instruction is actually "GR+hi(&G)".
433 Hi = DAG.getNode(ISD::ADD, MVT::i32,
434 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
437 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
438 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
441 case ISD::GlobalAddress: {
442 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
443 GlobalValue *GV = GSDN->getGlobal();
444 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset());
445 SDOperand Zero = DAG.getConstant(0, MVT::i32);
447 if (getTargetMachine().getRelocationModel() == Reloc::Static) {
448 // Generate non-pic code that has direct accesses to globals.
449 // The address of the global is just (hi(&g)+lo(&g)).
450 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
451 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
452 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
455 // Only lower GlobalAddress on Darwin.
456 if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break;
458 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
459 if (getTargetMachine().getRelocationModel() == Reloc::PIC) {
460 // With PIC, the first instruction is actually "GR+hi(&G)".
461 Hi = DAG.getNode(ISD::ADD, MVT::i32,
462 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
465 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
466 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
468 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() &&
469 (!GV->isExternal() || GV->hasNotBeenReadFromBytecode()))
472 // If the global is weak or external, we have to go through the lazy
474 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
477 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
479 // If we're comparing for equality to zero, expose the fact that this is
480 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
481 // fold the new nodes.
482 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
483 if (C->isNullValue() && CC == ISD::SETEQ) {
484 MVT::ValueType VT = Op.getOperand(0).getValueType();
485 SDOperand Zext = Op.getOperand(0);
488 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
490 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
491 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
492 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
493 DAG.getConstant(Log2b, getShiftAmountTy()));
494 return DAG.getNode(ISD::TRUNCATE, getSetCCResultTy(), Scc);
496 // Leave comparisons against 0 and -1 alone for now, since they're usually
497 // optimized. FIXME: revisit this when we can custom lower all setcc
499 if (C->isAllOnesValue() || C->isNullValue())
503 // If we have an integer seteq/setne, turn it into a compare against zero
504 // by subtracting the rhs from the lhs, which is faster than setting a
505 // condition register, reading it back out, and masking the correct bit.
506 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
507 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
508 MVT::ValueType VT = Op.getValueType();
509 SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0),
511 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
516 // vastart just stores the address of the VarArgsFrameIndex slot into the
517 // memory location argument.
518 // FIXME: Replace MVT::i32 with PointerTy
519 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
520 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
521 Op.getOperand(1), Op.getOperand(2));
526 switch(Op.getNumOperands()) {
528 assert(0 && "Do not know how to return this many arguments!");
531 return SDOperand(); // ret void is legal
533 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
534 unsigned ArgReg = MVT::isInteger(ArgVT) ? PPC::R3 : PPC::F1;
535 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
540 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2),
542 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
545 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
551 std::vector<SDOperand>
552 PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
554 // add beautiful description of PPC stack frame format, or at least some docs
556 MachineFunction &MF = DAG.getMachineFunction();
557 MachineFrameInfo *MFI = MF.getFrameInfo();
558 MachineBasicBlock& BB = MF.front();
559 SSARegMap *RegMap = MF.getSSARegMap();
560 std::vector<SDOperand> ArgValues;
562 unsigned ArgOffset = 24;
563 unsigned GPR_remaining = 8;
564 unsigned FPR_remaining = 13;
565 unsigned GPR_idx = 0, FPR_idx = 0;
566 static const unsigned GPR[] = {
567 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
568 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
570 static const unsigned FPR[] = {
571 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
572 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
575 // Add DAG nodes to load the arguments... On entry to a function on PPC,
576 // the arguments start at offset 24, although they are likely to be passed
578 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
579 SDOperand newroot, argt;
581 bool needsLoad = false;
582 bool ArgLive = !I->use_empty();
583 MVT::ValueType ObjectVT = getValueType(I->getType());
586 default: assert(0 && "Unhandled argument type!");
593 if (GPR_remaining > 0) {
594 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
595 MF.addLiveIn(GPR[GPR_idx], VReg);
596 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
597 if (ObjectVT != MVT::i32) {
598 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
600 argt = DAG.getNode(AssertOp, MVT::i32, argt,
601 DAG.getValueType(ObjectVT));
602 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
611 if (GPR_remaining > 0) {
612 SDOperand argHi, argLo;
613 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
614 MF.addLiveIn(GPR[GPR_idx], VReg);
615 argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
616 // If we have two or more remaining argument registers, then both halves
617 // of the i64 can be sourced from there. Otherwise, the lower half will
618 // have to come off the stack. This can happen when an i64 is preceded
619 // by 28 bytes of arguments.
620 if (GPR_remaining > 1) {
621 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
622 MF.addLiveIn(GPR[GPR_idx+1], VReg);
623 argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32);
625 int FI = MFI->CreateFixedObject(4, ArgOffset+4);
626 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
627 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
628 DAG.getSrcValue(NULL));
630 // Build the outgoing arg thingy
631 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
639 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
641 if (FPR_remaining > 0) {
647 if (FPR_remaining > 0) {
649 if (ObjectVT == MVT::f32)
650 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
652 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
653 MF.addLiveIn(FPR[FPR_idx], VReg);
654 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT);
663 // We need to load the argument to a virtual register if we determined above
664 // that we ran out of physical registers of the appropriate type
666 unsigned SubregOffset = 0;
667 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
668 if (ObjectVT == MVT::i16) SubregOffset = 2;
669 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
670 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
671 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
672 DAG.getConstant(SubregOffset, MVT::i32));
673 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
674 DAG.getSrcValue(NULL));
677 // Every 4 bytes of argument space consumes one of the GPRs available for
679 if (GPR_remaining > 0) {
680 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
681 GPR_remaining -= delta;
684 ArgOffset += ObjSize;
686 DAG.setRoot(newroot.getValue(1));
688 ArgValues.push_back(argt);
691 // If the function takes variable number of arguments, make a frame index for
692 // the start of the first vararg value... for expansion of llvm.va_start.
694 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
695 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
696 // If this function is vararg, store any remaining integer argument regs
697 // to their spots on the stack so that they may be loaded by deferencing the
698 // result of va_next.
699 std::vector<SDOperand> MemOps;
700 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
701 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
702 MF.addLiveIn(GPR[GPR_idx], VReg);
703 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
704 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
705 Val, FIN, DAG.getSrcValue(NULL));
706 MemOps.push_back(Store);
707 // Increment the address by four for the next argument to store
708 SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
709 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
711 if (!MemOps.empty()) {
712 MemOps.push_back(DAG.getRoot());
713 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
717 // Finally, inform the code generator which regs we return values in.
718 switch (getValueType(F.getReturnType())) {
719 default: assert(0 && "Unknown type!");
720 case MVT::isVoid: break;
725 MF.addLiveOut(PPC::R3);
728 MF.addLiveOut(PPC::R3);
729 MF.addLiveOut(PPC::R4);
733 MF.addLiveOut(PPC::F1);
740 std::pair<SDOperand, SDOperand>
741 PPCTargetLowering::LowerCallTo(SDOperand Chain,
742 const Type *RetTy, bool isVarArg,
743 unsigned CallingConv, bool isTailCall,
744 SDOperand Callee, ArgListTy &Args,
746 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
747 // SelectExpr to use to put the arguments in the appropriate registers.
748 std::vector<SDOperand> args_to_use;
750 // Count how many bytes are to be pushed on the stack, including the linkage
751 // area, and parameter passing area.
752 unsigned NumBytes = 24;
755 Chain = DAG.getCALLSEQ_START(Chain,
756 DAG.getConstant(NumBytes, getPointerTy()));
758 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
759 switch (getValueType(Args[i].second)) {
760 default: assert(0 && "Unknown value type!");
775 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
776 // plus 32 bytes of argument space in case any called code gets funky on us.
777 // (Required by ABI to support var arg)
778 if (NumBytes < 56) NumBytes = 56;
780 // Adjust the stack pointer for the new arguments...
781 // These operations are automatically eliminated by the prolog/epilog pass
782 Chain = DAG.getCALLSEQ_START(Chain,
783 DAG.getConstant(NumBytes, getPointerTy()));
785 // Set up a copy of the stack pointer for use loading and storing any
786 // arguments that may not fit in the registers available for argument
788 SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
790 // Figure out which arguments are going to go in registers, and which in
791 // memory. Also, if this is a vararg function, floating point operations
792 // must be stored to our stack, and loaded into integer regs as well, if
793 // any integer regs are available for argument passing.
794 unsigned ArgOffset = 24;
795 unsigned GPR_remaining = 8;
796 unsigned FPR_remaining = 13;
798 std::vector<SDOperand> MemOps;
799 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
800 // PtrOff will be used to store the current argument to the stack if a
801 // register cannot be found for it.
802 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
803 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
804 MVT::ValueType ArgVT = getValueType(Args[i].second);
807 default: assert(0 && "Unexpected ValueType for argument!");
811 // Promote the integer to 32 bits. If the input type is signed use a
812 // sign extend, otherwise use a zero extend.
813 if (Args[i].second->isSigned())
814 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
816 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
819 if (GPR_remaining > 0) {
820 args_to_use.push_back(Args[i].first);
823 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
824 Args[i].first, PtrOff,
825 DAG.getSrcValue(NULL)));
830 // If we have one free GPR left, we can place the upper half of the i64
831 // in it, and store the other half to the stack. If we have two or more
832 // free GPRs, then we can pass both halves of the i64 in registers.
833 if (GPR_remaining > 0) {
834 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
835 Args[i].first, DAG.getConstant(1, MVT::i32));
836 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
837 Args[i].first, DAG.getConstant(0, MVT::i32));
838 args_to_use.push_back(Hi);
840 if (GPR_remaining > 0) {
841 args_to_use.push_back(Lo);
844 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
845 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
846 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
847 Lo, PtrOff, DAG.getSrcValue(NULL)));
850 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
851 Args[i].first, PtrOff,
852 DAG.getSrcValue(NULL)));
858 if (FPR_remaining > 0) {
859 args_to_use.push_back(Args[i].first);
862 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
863 Args[i].first, PtrOff,
864 DAG.getSrcValue(NULL));
865 MemOps.push_back(Store);
866 // Float varargs are always shadowed in available integer registers
867 if (GPR_remaining > 0) {
868 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
869 DAG.getSrcValue(NULL));
870 MemOps.push_back(Load.getValue(1));
871 args_to_use.push_back(Load);
874 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
875 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
876 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
877 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
878 DAG.getSrcValue(NULL));
879 MemOps.push_back(Load.getValue(1));
880 args_to_use.push_back(Load);
884 // If we have any FPRs remaining, we may also have GPRs remaining.
885 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
887 if (GPR_remaining > 0) {
888 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
891 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
892 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
897 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
898 Args[i].first, PtrOff,
899 DAG.getSrcValue(NULL)));
901 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
906 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
909 std::vector<MVT::ValueType> RetVals;
910 MVT::ValueType RetTyVT = getValueType(RetTy);
911 MVT::ValueType ActualRetTyVT = RetTyVT;
912 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16)
913 ActualRetTyVT = MVT::i32; // Promote result to i32.
915 if (RetTyVT == MVT::i64) {
916 RetVals.push_back(MVT::i32);
917 RetVals.push_back(MVT::i32);
918 } else if (RetTyVT != MVT::isVoid) {
919 RetVals.push_back(ActualRetTyVT);
921 RetVals.push_back(MVT::Other);
923 // If the callee is a GlobalAddress node (quite common, every direct call is)
924 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
925 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
926 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
928 std::vector<SDOperand> Ops;
929 Ops.push_back(Chain);
930 Ops.push_back(Callee);
931 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
932 SDOperand TheCall = DAG.getNode(PPCISD::CALL, RetVals, Ops);
933 Chain = TheCall.getValue(TheCall.Val->getNumValues()-1);
934 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
935 DAG.getConstant(NumBytes, getPointerTy()));
936 SDOperand RetVal = TheCall;
938 // If the result is a small value, add a note so that we keep track of the
939 // information about whether it is sign or zero extended.
940 if (RetTyVT != ActualRetTyVT) {
941 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
942 MVT::i32, RetVal, DAG.getValueType(RetTyVT));
943 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
944 } else if (RetTyVT == MVT::i64) {
945 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, RetVal, RetVal.getValue(1));
948 return std::make_pair(RetVal, Chain);
952 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
953 MachineBasicBlock *BB) {
954 assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
955 MI->getOpcode() == PPC::SELECT_CC_F4 ||
956 MI->getOpcode() == PPC::SELECT_CC_F8) &&
957 "Unexpected instr type to insert");
959 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
960 // control-flow pattern. The incoming instruction knows the destination vreg
961 // to set, the condition code register to branch on, the true/false values to
962 // select between, and a branch opcode to use.
963 const BasicBlock *LLVM_BB = BB->getBasicBlock();
964 ilist<MachineBasicBlock>::iterator It = BB;
972 // fallthrough --> copy0MBB
973 MachineBasicBlock *thisMBB = BB;
974 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
975 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
976 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
977 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
978 MachineFunction *F = BB->getParent();
979 F->getBasicBlockList().insert(It, copy0MBB);
980 F->getBasicBlockList().insert(It, sinkMBB);
981 // Update machine-CFG edges
982 BB->addSuccessor(copy0MBB);
983 BB->addSuccessor(sinkMBB);
987 // # fallthrough to sinkMBB
990 // Update machine-CFG edges
991 BB->addSuccessor(sinkMBB);
994 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
997 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
998 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
999 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1001 delete MI; // The pseudo instruction is gone now.
1005 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
1006 DAGCombinerInfo &DCI) const {
1007 TargetMachine &TM = getTargetMachine();
1008 SelectionDAG &DAG = DCI.DAG;
1009 switch (N->getOpcode()) {
1011 case ISD::SINT_TO_FP:
1012 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
1013 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
1014 // We allow the src/dst to be either f32/f64, but force the intermediate
1016 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT &&
1017 N->getOperand(0).getValueType() == MVT::i64) {
1019 SDOperand Val = N->getOperand(0).getOperand(0);
1020 if (Val.getValueType() == MVT::f32) {
1021 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
1022 DCI.AddToWorklist(Val.Val);
1025 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
1026 DCI.AddToWorklist(Val.Val);
1027 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
1028 DCI.AddToWorklist(Val.Val);
1029 if (N->getValueType(0) == MVT::f32) {
1030 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
1031 DCI.AddToWorklist(Val.Val);
1038 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
1039 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
1040 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
1041 N->getOperand(1).getValueType() == MVT::i32) {
1042 SDOperand Val = N->getOperand(1).getOperand(0);
1043 if (Val.getValueType() == MVT::f32) {
1044 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
1045 DCI.AddToWorklist(Val.Val);
1047 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
1048 DCI.AddToWorklist(Val.Val);
1050 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
1051 N->getOperand(2), N->getOperand(3));
1052 DCI.AddToWorklist(Val.Val);
1061 /// getConstraintType - Given a constraint letter, return the type of
1062 /// constraint it is for this target.
1063 PPCTargetLowering::ConstraintType
1064 PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
1065 switch (ConstraintLetter) {
1072 return C_RegisterClass;
1074 return TargetLowering::getConstraintType(ConstraintLetter);
1078 std::vector<unsigned> PPCTargetLowering::
1079 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1080 MVT::ValueType VT) const {
1081 if (Constraint.size() == 1) {
1082 switch (Constraint[0]) { // GCC RS6000 Constraint Letters
1083 default: break; // Unknown constriant letter
1085 return make_vector<unsigned>(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 ,
1086 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
1087 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
1088 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
1089 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
1090 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
1091 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
1092 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
1095 return make_vector<unsigned>(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 ,
1096 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
1097 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
1098 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
1099 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
1100 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
1101 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
1102 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
1105 return make_vector<unsigned>(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 ,
1106 PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 ,
1107 PPC::F8 , PPC::F9 , PPC::F10, PPC::F11,
1108 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
1109 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
1110 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
1111 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
1112 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
1115 return make_vector<unsigned>(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 ,
1116 PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
1117 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11,
1118 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
1119 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
1120 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
1121 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
1122 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
1125 return make_vector<unsigned>(PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
1126 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7,
1131 return std::vector<unsigned>();
1134 // isOperandValidForConstraint
1135 bool PPCTargetLowering::
1136 isOperandValidForConstraint(SDOperand Op, char Letter) {
1147 if (!isa<ConstantSDNode>(Op)) return false; // Must be an immediate.
1148 unsigned Value = cast<ConstantSDNode>(Op)->getValue();
1150 default: assert(0 && "Unknown constraint letter!");
1151 case 'I': // "I" is a signed 16-bit constant.
1152 return (short)Value == (int)Value;
1153 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
1154 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
1155 return (short)Value == 0;
1156 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
1157 return (Value >> 16) == 0;
1158 case 'M': // "M" is a constant that is greater than 31.
1160 case 'N': // "N" is a positive constant that is an exact power of two.
1161 return (int)Value > 0 && isPowerOf2_32(Value);
1162 case 'O': // "O" is the constant zero.
1164 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
1165 return (short)-Value == (int)-Value;
1171 // Handle standard constraint letters.
1172 return TargetLowering::isOperandValidForConstraint(Op, Letter);