1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetOptions.h"
40 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
41 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
43 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
44 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
46 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
47 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
49 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
50 if (TM.getSubtargetImpl()->isDarwin())
51 return new TargetLoweringObjectFileMachO();
53 if (TM.getSubtargetImpl()->isSVR4ABI())
54 return new PPC64LinuxTargetObjectFile();
56 return new TargetLoweringObjectFileELF();
59 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
60 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
61 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
65 // Use _setjmp/_longjmp instead of setjmp/longjmp.
66 setUseUnderscoreSetJmp(true);
67 setUseUnderscoreLongJmp(true);
69 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
70 // arguments are at least 4/8 bytes aligned.
71 bool isPPC64 = Subtarget->isPPC64();
72 setMinStackArgumentAlignment(isPPC64 ? 8:4);
74 // Set up the register classes.
75 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
76 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
77 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
79 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
80 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
85 // PowerPC has pre-inc load and store's.
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
97 // This is used in the ppcf128->int sequence. Note it has different semantics
98 // from FP_ROUND: that rounds to nearest, this rounds to zero.
99 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
101 // We do not currently implement these libm ops for PowerPC.
102 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
103 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
104 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
105 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
106 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
107 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
109 // PowerPC has no SREM/UREM instructions
110 setOperationAction(ISD::SREM, MVT::i32, Expand);
111 setOperationAction(ISD::UREM, MVT::i32, Expand);
112 setOperationAction(ISD::SREM, MVT::i64, Expand);
113 setOperationAction(ISD::UREM, MVT::i64, Expand);
115 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
116 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
117 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
118 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
119 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
121 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
122 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
123 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
125 // We don't support sin/cos/sqrt/fmod/pow
126 setOperationAction(ISD::FSIN , MVT::f64, Expand);
127 setOperationAction(ISD::FCOS , MVT::f64, Expand);
128 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
129 setOperationAction(ISD::FREM , MVT::f64, Expand);
130 setOperationAction(ISD::FPOW , MVT::f64, Expand);
131 setOperationAction(ISD::FMA , MVT::f64, Legal);
132 setOperationAction(ISD::FSIN , MVT::f32, Expand);
133 setOperationAction(ISD::FCOS , MVT::f32, Expand);
134 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
135 setOperationAction(ISD::FREM , MVT::f32, Expand);
136 setOperationAction(ISD::FPOW , MVT::f32, Expand);
137 setOperationAction(ISD::FMA , MVT::f32, Legal);
139 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
141 // If we're enabling GP optimizations, use hardware square root
142 if (!Subtarget->hasFSQRT() &&
143 !(TM.Options.UnsafeFPMath &&
144 Subtarget->hasFRSQRTE() && Subtarget->hasFRE()))
145 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
147 if (!Subtarget->hasFSQRT() &&
148 !(TM.Options.UnsafeFPMath &&
149 Subtarget->hasFRSQRTES() && Subtarget->hasFRES()))
150 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
152 if (Subtarget->hasFCPSGN()) {
153 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
154 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
156 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
157 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
160 if (Subtarget->hasFPRND()) {
161 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
162 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
163 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
164 setOperationAction(ISD::FROUND, MVT::f64, Legal);
166 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
167 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
168 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
169 setOperationAction(ISD::FROUND, MVT::f32, Legal);
172 // PowerPC does not have BSWAP, CTPOP or CTTZ
173 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
174 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
175 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
176 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
177 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
178 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
179 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
180 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
182 if (Subtarget->hasPOPCNTD()) {
183 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
184 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
186 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
187 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
190 // PowerPC does not have ROTR
191 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
192 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
194 // PowerPC does not have Select
195 setOperationAction(ISD::SELECT, MVT::i32, Expand);
196 setOperationAction(ISD::SELECT, MVT::i64, Expand);
197 setOperationAction(ISD::SELECT, MVT::f32, Expand);
198 setOperationAction(ISD::SELECT, MVT::f64, Expand);
200 // PowerPC wants to turn select_cc of FP into fsel when possible.
201 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
202 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
204 // PowerPC wants to optimize integer setcc a bit
205 setOperationAction(ISD::SETCC, MVT::i32, Custom);
207 // PowerPC does not have BRCOND which requires SetCC
208 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
210 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
212 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
213 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
215 // PowerPC does not have [U|S]INT_TO_FP
216 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
217 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
219 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
220 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
221 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
222 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
224 // We cannot sextinreg(i1). Expand to shifts.
225 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
227 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
228 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
229 // support continuation, user-level threading, and etc.. As a result, no
230 // other SjLj exception interfaces are implemented and please don't build
231 // your own exception handling based on them.
232 // LLVM/Clang supports zero-cost DWARF exception handling.
233 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
234 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
236 // We want to legalize GlobalAddress and ConstantPool nodes into the
237 // appropriate instructions to materialize the address.
238 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
239 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
240 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
241 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
242 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
243 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
244 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
245 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
246 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
247 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
250 setOperationAction(ISD::TRAP, MVT::Other, Legal);
252 // TRAMPOLINE is custom lowered.
253 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
254 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
256 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
257 setOperationAction(ISD::VASTART , MVT::Other, Custom);
259 if (Subtarget->isSVR4ABI()) {
261 // VAARG always uses double-word chunks, so promote anything smaller.
262 setOperationAction(ISD::VAARG, MVT::i1, Promote);
263 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
264 setOperationAction(ISD::VAARG, MVT::i8, Promote);
265 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
266 setOperationAction(ISD::VAARG, MVT::i16, Promote);
267 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
268 setOperationAction(ISD::VAARG, MVT::i32, Promote);
269 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
270 setOperationAction(ISD::VAARG, MVT::Other, Expand);
272 // VAARG is custom lowered with the 32-bit SVR4 ABI.
273 setOperationAction(ISD::VAARG, MVT::Other, Custom);
274 setOperationAction(ISD::VAARG, MVT::i64, Custom);
277 setOperationAction(ISD::VAARG, MVT::Other, Expand);
279 if (Subtarget->isSVR4ABI() && !isPPC64)
280 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
281 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
283 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
285 // Use the default implementation.
286 setOperationAction(ISD::VAEND , MVT::Other, Expand);
287 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
288 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
289 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
290 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
292 // We want to custom lower some of our intrinsics.
293 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
295 // To handle counter-based loop conditions.
296 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
298 // Comparisons that require checking two conditions.
299 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
300 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
301 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
302 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
303 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
304 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
305 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
306 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
307 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
308 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
309 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
310 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
312 if (Subtarget->has64BitSupport()) {
313 // They also have instructions for converting between i64 and fp.
314 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
315 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
316 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
317 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
318 // This is just the low 32 bits of a (signed) fp->i64 conversion.
319 // We cannot do this with Promote because i64 is not a legal type.
320 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
322 if (PPCSubTarget.hasLFIWAX() || Subtarget->isPPC64())
323 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
325 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
326 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
329 // With the instructions enabled under FPCVT, we can do everything.
330 if (PPCSubTarget.hasFPCVT()) {
331 if (Subtarget->has64BitSupport()) {
332 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
333 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
334 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
335 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
338 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
339 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
340 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
341 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
344 if (Subtarget->use64BitRegs()) {
345 // 64-bit PowerPC implementations can support i64 types directly
346 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
347 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
348 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
349 // 64-bit PowerPC wants to expand i128 shifts itself.
350 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
351 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
352 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
354 // 32-bit PowerPC wants to expand i64 shifts itself.
355 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
356 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
357 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
360 if (Subtarget->hasAltivec()) {
361 // First set operation action for all vector types to expand. Then we
362 // will selectively turn on ones that can be effectively codegen'd.
363 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
364 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
365 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
367 // add/sub are legal for all supported vector VT's.
368 setOperationAction(ISD::ADD , VT, Legal);
369 setOperationAction(ISD::SUB , VT, Legal);
371 // We promote all shuffles to v16i8.
372 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
373 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
375 // We promote all non-typed operations to v4i32.
376 setOperationAction(ISD::AND , VT, Promote);
377 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
378 setOperationAction(ISD::OR , VT, Promote);
379 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
380 setOperationAction(ISD::XOR , VT, Promote);
381 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
382 setOperationAction(ISD::LOAD , VT, Promote);
383 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
384 setOperationAction(ISD::SELECT, VT, Promote);
385 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
386 setOperationAction(ISD::STORE, VT, Promote);
387 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
389 // No other operations are legal.
390 setOperationAction(ISD::MUL , VT, Expand);
391 setOperationAction(ISD::SDIV, VT, Expand);
392 setOperationAction(ISD::SREM, VT, Expand);
393 setOperationAction(ISD::UDIV, VT, Expand);
394 setOperationAction(ISD::UREM, VT, Expand);
395 setOperationAction(ISD::FDIV, VT, Expand);
396 setOperationAction(ISD::FREM, VT, Expand);
397 setOperationAction(ISD::FNEG, VT, Expand);
398 setOperationAction(ISD::FSQRT, VT, Expand);
399 setOperationAction(ISD::FLOG, VT, Expand);
400 setOperationAction(ISD::FLOG10, VT, Expand);
401 setOperationAction(ISD::FLOG2, VT, Expand);
402 setOperationAction(ISD::FEXP, VT, Expand);
403 setOperationAction(ISD::FEXP2, VT, Expand);
404 setOperationAction(ISD::FSIN, VT, Expand);
405 setOperationAction(ISD::FCOS, VT, Expand);
406 setOperationAction(ISD::FABS, VT, Expand);
407 setOperationAction(ISD::FPOWI, VT, Expand);
408 setOperationAction(ISD::FFLOOR, VT, Expand);
409 setOperationAction(ISD::FCEIL, VT, Expand);
410 setOperationAction(ISD::FTRUNC, VT, Expand);
411 setOperationAction(ISD::FRINT, VT, Expand);
412 setOperationAction(ISD::FNEARBYINT, VT, Expand);
413 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
414 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
415 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
416 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
417 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
418 setOperationAction(ISD::UDIVREM, VT, Expand);
419 setOperationAction(ISD::SDIVREM, VT, Expand);
420 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
421 setOperationAction(ISD::FPOW, VT, Expand);
422 setOperationAction(ISD::CTPOP, VT, Expand);
423 setOperationAction(ISD::CTLZ, VT, Expand);
424 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
425 setOperationAction(ISD::CTTZ, VT, Expand);
426 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
427 setOperationAction(ISD::VSELECT, VT, Expand);
428 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
430 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
431 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
432 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
433 setTruncStoreAction(VT, InnerVT, Expand);
435 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
436 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
437 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
440 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
441 // with merges, splats, etc.
442 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
444 setOperationAction(ISD::AND , MVT::v4i32, Legal);
445 setOperationAction(ISD::OR , MVT::v4i32, Legal);
446 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
447 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
448 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
449 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
450 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
451 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
452 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
453 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
454 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
455 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
456 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
457 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
459 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
460 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
461 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
462 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
464 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
465 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
467 if (TM.Options.UnsafeFPMath) {
468 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
469 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
472 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
473 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
474 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
476 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
477 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
479 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
480 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
481 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
482 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
484 // Altivec does not contain unordered floating-point compare instructions
485 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
486 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
487 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
488 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
489 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
490 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
492 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
493 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
496 if (Subtarget->has64BitSupport()) {
497 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
498 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
501 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
502 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
503 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
504 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
506 setBooleanContents(ZeroOrOneBooleanContent);
507 // Altivec instructions set fields to all zeros or all ones.
508 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
511 setStackPointerRegisterToSaveRestore(PPC::X1);
512 setExceptionPointerRegister(PPC::X3);
513 setExceptionSelectorRegister(PPC::X4);
515 setStackPointerRegisterToSaveRestore(PPC::R1);
516 setExceptionPointerRegister(PPC::R3);
517 setExceptionSelectorRegister(PPC::R4);
520 // We have target-specific dag combine patterns for the following nodes:
521 setTargetDAGCombine(ISD::SINT_TO_FP);
522 setTargetDAGCombine(ISD::LOAD);
523 setTargetDAGCombine(ISD::STORE);
524 setTargetDAGCombine(ISD::BR_CC);
525 setTargetDAGCombine(ISD::BSWAP);
526 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
528 // Use reciprocal estimates.
529 if (TM.Options.UnsafeFPMath) {
530 setTargetDAGCombine(ISD::FDIV);
531 setTargetDAGCombine(ISD::FSQRT);
534 // Darwin long double math library functions have $LDBL128 appended.
535 if (Subtarget->isDarwin()) {
536 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
537 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
538 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
539 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
540 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
541 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
542 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
543 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
544 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
545 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
548 setMinFunctionAlignment(2);
549 if (PPCSubTarget.isDarwin())
550 setPrefFunctionAlignment(4);
552 if (isPPC64 && Subtarget->isJITCodeModel())
553 // Temporary workaround for the inability of PPC64 JIT to handle jump
555 setSupportJumpTables(false);
557 setInsertFencesForAtomic(true);
559 if (Subtarget->enableMachineScheduler())
560 setSchedulingPreference(Sched::Source);
562 setSchedulingPreference(Sched::Hybrid);
564 computeRegisterProperties();
566 // The Freescale cores does better with aggressive inlining of memcpy and
567 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
568 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
569 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
570 MaxStoresPerMemset = 32;
571 MaxStoresPerMemsetOptSize = 16;
572 MaxStoresPerMemcpy = 32;
573 MaxStoresPerMemcpyOptSize = 8;
574 MaxStoresPerMemmove = 32;
575 MaxStoresPerMemmoveOptSize = 8;
577 setPrefFunctionAlignment(4);
581 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
582 /// function arguments in the caller parameter area.
583 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
584 const TargetMachine &TM = getTargetMachine();
585 // Darwin passes everything on 4 byte boundary.
586 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
589 // 16byte and wider vectors are passed on 16byte boundary.
590 if (VectorType *VTy = dyn_cast<VectorType>(Ty))
591 if (VTy->getBitWidth() >= 128)
594 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
595 if (PPCSubTarget.isPPC64())
601 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
604 case PPCISD::FSEL: return "PPCISD::FSEL";
605 case PPCISD::FCFID: return "PPCISD::FCFID";
606 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
607 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
608 case PPCISD::FRE: return "PPCISD::FRE";
609 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
610 case PPCISD::STFIWX: return "PPCISD::STFIWX";
611 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
612 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
613 case PPCISD::VPERM: return "PPCISD::VPERM";
614 case PPCISD::Hi: return "PPCISD::Hi";
615 case PPCISD::Lo: return "PPCISD::Lo";
616 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
617 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
618 case PPCISD::LOAD: return "PPCISD::LOAD";
619 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
620 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
621 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
622 case PPCISD::SRL: return "PPCISD::SRL";
623 case PPCISD::SRA: return "PPCISD::SRA";
624 case PPCISD::SHL: return "PPCISD::SHL";
625 case PPCISD::CALL: return "PPCISD::CALL";
626 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
627 case PPCISD::MTCTR: return "PPCISD::MTCTR";
628 case PPCISD::BCTRL: return "PPCISD::BCTRL";
629 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
630 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
631 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
632 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
633 case PPCISD::VCMP: return "PPCISD::VCMP";
634 case PPCISD::VCMPo: return "PPCISD::VCMPo";
635 case PPCISD::LBRX: return "PPCISD::LBRX";
636 case PPCISD::STBRX: return "PPCISD::STBRX";
637 case PPCISD::LARX: return "PPCISD::LARX";
638 case PPCISD::STCX: return "PPCISD::STCX";
639 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
640 case PPCISD::BDNZ: return "PPCISD::BDNZ";
641 case PPCISD::BDZ: return "PPCISD::BDZ";
642 case PPCISD::MFFS: return "PPCISD::MFFS";
643 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
644 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
645 case PPCISD::CR6SET: return "PPCISD::CR6SET";
646 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
647 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
648 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
649 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
650 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
651 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
652 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
653 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
654 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
655 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
656 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
657 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
658 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
659 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
660 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
661 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
662 case PPCISD::SC: return "PPCISD::SC";
666 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
669 return VT.changeVectorElementTypeToInteger();
672 //===----------------------------------------------------------------------===//
673 // Node matching predicates, for use by the tblgen matching code.
674 //===----------------------------------------------------------------------===//
676 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
677 static bool isFloatingPointZero(SDValue Op) {
678 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
679 return CFP->getValueAPF().isZero();
680 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
681 // Maybe this has already been legalized into the constant pool?
682 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
683 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
684 return CFP->getValueAPF().isZero();
689 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
690 /// true if Op is undef or if it matches the specified value.
691 static bool isConstantOrUndef(int Op, int Val) {
692 return Op < 0 || Op == Val;
695 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
696 /// VPKUHUM instruction.
697 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
699 for (unsigned i = 0; i != 16; ++i)
700 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
703 for (unsigned i = 0; i != 8; ++i)
704 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
705 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
711 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
712 /// VPKUWUM instruction.
713 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
715 for (unsigned i = 0; i != 16; i += 2)
716 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
717 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
720 for (unsigned i = 0; i != 8; i += 2)
721 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
722 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
723 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
724 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
730 /// isVMerge - Common function, used to match vmrg* shuffles.
732 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
733 unsigned LHSStart, unsigned RHSStart) {
734 assert(N->getValueType(0) == MVT::v16i8 &&
735 "PPC only supports shuffles by bytes!");
736 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
737 "Unsupported merge size!");
739 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
740 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
741 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
742 LHSStart+j+i*UnitSize) ||
743 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
744 RHSStart+j+i*UnitSize))
750 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
751 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
752 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
755 return isVMerge(N, UnitSize, 8, 24);
756 return isVMerge(N, UnitSize, 8, 8);
759 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
760 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
761 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
764 return isVMerge(N, UnitSize, 0, 16);
765 return isVMerge(N, UnitSize, 0, 0);
769 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
770 /// amount, otherwise return -1.
771 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
772 assert(N->getValueType(0) == MVT::v16i8 &&
773 "PPC only supports shuffles by bytes!");
775 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
777 // Find the first non-undef value in the shuffle mask.
779 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
782 if (i == 16) return -1; // all undef.
784 // Otherwise, check to see if the rest of the elements are consecutively
785 // numbered from this value.
786 unsigned ShiftAmt = SVOp->getMaskElt(i);
787 if (ShiftAmt < i) return -1;
791 // Check the rest of the elements to see if they are consecutive.
792 for (++i; i != 16; ++i)
793 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
796 // Check the rest of the elements to see if they are consecutive.
797 for (++i; i != 16; ++i)
798 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
804 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
805 /// specifies a splat of a single element that is suitable for input to
806 /// VSPLTB/VSPLTH/VSPLTW.
807 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
808 assert(N->getValueType(0) == MVT::v16i8 &&
809 (EltSize == 1 || EltSize == 2 || EltSize == 4));
811 // This is a splat operation if each element of the permute is the same, and
812 // if the value doesn't reference the second vector.
813 unsigned ElementBase = N->getMaskElt(0);
815 // FIXME: Handle UNDEF elements too!
816 if (ElementBase >= 16)
819 // Check that the indices are consecutive, in the case of a multi-byte element
820 // splatted with a v16i8 mask.
821 for (unsigned i = 1; i != EltSize; ++i)
822 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
825 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
826 if (N->getMaskElt(i) < 0) continue;
827 for (unsigned j = 0; j != EltSize; ++j)
828 if (N->getMaskElt(i+j) != N->getMaskElt(j))
834 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
836 bool PPC::isAllNegativeZeroVector(SDNode *N) {
837 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
839 APInt APVal, APUndef;
843 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
844 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
845 return CFP->getValueAPF().isNegZero();
850 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
851 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
852 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
853 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
854 assert(isSplatShuffleMask(SVOp, EltSize));
855 return SVOp->getMaskElt(0) / EltSize;
858 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
859 /// by using a vspltis[bhw] instruction of the specified element size, return
860 /// the constant being splatted. The ByteSize field indicates the number of
861 /// bytes of each element [124] -> [bhw].
862 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
865 // If ByteSize of the splat is bigger than the element size of the
866 // build_vector, then we have a case where we are checking for a splat where
867 // multiple elements of the buildvector are folded together into a single
868 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
869 unsigned EltSize = 16/N->getNumOperands();
870 if (EltSize < ByteSize) {
871 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
872 SDValue UniquedVals[4];
873 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
875 // See if all of the elements in the buildvector agree across.
876 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
877 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
878 // If the element isn't a constant, bail fully out.
879 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
882 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
883 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
884 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
885 return SDValue(); // no match.
888 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
889 // either constant or undef values that are identical for each chunk. See
890 // if these chunks can form into a larger vspltis*.
892 // Check to see if all of the leading entries are either 0 or -1. If
893 // neither, then this won't fit into the immediate field.
894 bool LeadingZero = true;
895 bool LeadingOnes = true;
896 for (unsigned i = 0; i != Multiple-1; ++i) {
897 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
899 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
900 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
902 // Finally, check the least significant entry.
904 if (UniquedVals[Multiple-1].getNode() == 0)
905 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
906 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
908 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
911 if (UniquedVals[Multiple-1].getNode() == 0)
912 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
913 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
914 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
915 return DAG.getTargetConstant(Val, MVT::i32);
921 // Check to see if this buildvec has a single non-undef value in its elements.
922 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
923 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
924 if (OpVal.getNode() == 0)
925 OpVal = N->getOperand(i);
926 else if (OpVal != N->getOperand(i))
930 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
932 unsigned ValSizeInBytes = EltSize;
934 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
935 Value = CN->getZExtValue();
936 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
937 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
938 Value = FloatToBits(CN->getValueAPF().convertToFloat());
941 // If the splat value is larger than the element value, then we can never do
942 // this splat. The only case that we could fit the replicated bits into our
943 // immediate field for would be zero, and we prefer to use vxor for it.
944 if (ValSizeInBytes < ByteSize) return SDValue();
946 // If the element value is larger than the splat value, cut it in half and
947 // check to see if the two halves are equal. Continue doing this until we
948 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
949 while (ValSizeInBytes > ByteSize) {
950 ValSizeInBytes >>= 1;
952 // If the top half equals the bottom half, we're still ok.
953 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
954 (Value & ((1 << (8*ValSizeInBytes))-1)))
958 // Properly sign extend the value.
959 int MaskVal = SignExtend32(Value, ByteSize * 8);
961 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
962 if (MaskVal == 0) return SDValue();
964 // Finally, if this value fits in a 5 bit sext field, return it
965 if (SignExtend32<5>(MaskVal) == MaskVal)
966 return DAG.getTargetConstant(MaskVal, MVT::i32);
970 //===----------------------------------------------------------------------===//
971 // Addressing Mode Selection
972 //===----------------------------------------------------------------------===//
974 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
975 /// or 64-bit immediate, and if the value can be accurately represented as a
976 /// sign extension from a 16-bit value. If so, this returns true and the
978 static bool isIntS16Immediate(SDNode *N, short &Imm) {
979 if (N->getOpcode() != ISD::Constant)
982 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
983 if (N->getValueType(0) == MVT::i32)
984 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
986 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
988 static bool isIntS16Immediate(SDValue Op, short &Imm) {
989 return isIntS16Immediate(Op.getNode(), Imm);
993 /// SelectAddressRegReg - Given the specified addressed, check to see if it
994 /// can be represented as an indexed [r+r] operation. Returns false if it
995 /// can be more efficiently represented with [r+imm].
996 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
998 SelectionDAG &DAG) const {
1000 if (N.getOpcode() == ISD::ADD) {
1001 if (isIntS16Immediate(N.getOperand(1), imm))
1002 return false; // r+i
1003 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1004 return false; // r+i
1006 Base = N.getOperand(0);
1007 Index = N.getOperand(1);
1009 } else if (N.getOpcode() == ISD::OR) {
1010 if (isIntS16Immediate(N.getOperand(1), imm))
1011 return false; // r+i can fold it if we can.
1013 // If this is an or of disjoint bitfields, we can codegen this as an add
1014 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1016 APInt LHSKnownZero, LHSKnownOne;
1017 APInt RHSKnownZero, RHSKnownOne;
1018 DAG.ComputeMaskedBits(N.getOperand(0),
1019 LHSKnownZero, LHSKnownOne);
1021 if (LHSKnownZero.getBoolValue()) {
1022 DAG.ComputeMaskedBits(N.getOperand(1),
1023 RHSKnownZero, RHSKnownOne);
1024 // If all of the bits are known zero on the LHS or RHS, the add won't
1026 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1027 Base = N.getOperand(0);
1028 Index = N.getOperand(1);
1037 // If we happen to be doing an i64 load or store into a stack slot that has
1038 // less than a 4-byte alignment, then the frame-index elimination may need to
1039 // use an indexed load or store instruction (because the offset may not be a
1040 // multiple of 4). The extra register needed to hold the offset comes from the
1041 // register scavenger, and it is possible that the scavenger will need to use
1042 // an emergency spill slot. As a result, we need to make sure that a spill slot
1043 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1045 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1046 // FIXME: This does not handle the LWA case.
1050 // NOTE: We'll exclude negative FIs here, which come from argument
1051 // lowering, because there are no known test cases triggering this problem
1052 // using packed structures (or similar). We can remove this exclusion if
1053 // we find such a test case. The reason why this is so test-case driven is
1054 // because this entire 'fixup' is only to prevent crashes (from the
1055 // register scavenger) on not-really-valid inputs. For example, if we have:
1057 // %b = bitcast i1* %a to i64*
1058 // store i64* a, i64 b
1059 // then the store should really be marked as 'align 1', but is not. If it
1060 // were marked as 'align 1' then the indexed form would have been
1061 // instruction-selected initially, and the problem this 'fixup' is preventing
1062 // won't happen regardless.
1066 MachineFunction &MF = DAG.getMachineFunction();
1067 MachineFrameInfo *MFI = MF.getFrameInfo();
1069 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1073 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1074 FuncInfo->setHasNonRISpills();
1077 /// Returns true if the address N can be represented by a base register plus
1078 /// a signed 16-bit displacement [r+imm], and if it is not better
1079 /// represented as reg+reg. If Aligned is true, only accept displacements
1080 /// suitable for STD and friends, i.e. multiples of 4.
1081 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1084 bool Aligned) const {
1085 // FIXME dl should come from parent load or store, not from address
1087 // If this can be more profitably realized as r+r, fail.
1088 if (SelectAddressRegReg(N, Disp, Base, DAG))
1091 if (N.getOpcode() == ISD::ADD) {
1093 if (isIntS16Immediate(N.getOperand(1), imm) &&
1094 (!Aligned || (imm & 3) == 0)) {
1095 Disp = DAG.getTargetConstant(imm, N.getValueType());
1096 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1097 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1098 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1100 Base = N.getOperand(0);
1102 return true; // [r+i]
1103 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1104 // Match LOAD (ADD (X, Lo(G))).
1105 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1106 && "Cannot handle constant offsets yet!");
1107 Disp = N.getOperand(1).getOperand(0); // The global address.
1108 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1109 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1110 Disp.getOpcode() == ISD::TargetConstantPool ||
1111 Disp.getOpcode() == ISD::TargetJumpTable);
1112 Base = N.getOperand(0);
1113 return true; // [&g+r]
1115 } else if (N.getOpcode() == ISD::OR) {
1117 if (isIntS16Immediate(N.getOperand(1), imm) &&
1118 (!Aligned || (imm & 3) == 0)) {
1119 // If this is an or of disjoint bitfields, we can codegen this as an add
1120 // (for better address arithmetic) if the LHS and RHS of the OR are
1121 // provably disjoint.
1122 APInt LHSKnownZero, LHSKnownOne;
1123 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1125 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1126 // If all of the bits are known zero on the LHS or RHS, the add won't
1128 Base = N.getOperand(0);
1129 Disp = DAG.getTargetConstant(imm, N.getValueType());
1133 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1134 // Loading from a constant address.
1136 // If this address fits entirely in a 16-bit sext immediate field, codegen
1139 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1140 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1141 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1142 CN->getValueType(0));
1146 // Handle 32-bit sext immediates with LIS + addr mode.
1147 if ((CN->getValueType(0) == MVT::i32 ||
1148 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1149 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1150 int Addr = (int)CN->getZExtValue();
1152 // Otherwise, break this down into an LIS + disp.
1153 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1155 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1156 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1157 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1162 Disp = DAG.getTargetConstant(0, getPointerTy());
1163 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1164 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1165 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1168 return true; // [r+0]
1171 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1172 /// represented as an indexed [r+r] operation.
1173 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1175 SelectionDAG &DAG) const {
1176 // Check to see if we can easily represent this as an [r+r] address. This
1177 // will fail if it thinks that the address is more profitably represented as
1178 // reg+imm, e.g. where imm = 0.
1179 if (SelectAddressRegReg(N, Base, Index, DAG))
1182 // If the operand is an addition, always emit this as [r+r], since this is
1183 // better (for code size, and execution, as the memop does the add for free)
1184 // than emitting an explicit add.
1185 if (N.getOpcode() == ISD::ADD) {
1186 Base = N.getOperand(0);
1187 Index = N.getOperand(1);
1191 // Otherwise, do it the hard way, using R0 as the base register.
1192 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1198 /// getPreIndexedAddressParts - returns true by value, base pointer and
1199 /// offset pointer and addressing mode by reference if the node's address
1200 /// can be legally represented as pre-indexed load / store address.
1201 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1203 ISD::MemIndexedMode &AM,
1204 SelectionDAG &DAG) const {
1205 if (DisablePPCPreinc) return false;
1211 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1212 Ptr = LD->getBasePtr();
1213 VT = LD->getMemoryVT();
1214 Alignment = LD->getAlignment();
1215 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1216 Ptr = ST->getBasePtr();
1217 VT = ST->getMemoryVT();
1218 Alignment = ST->getAlignment();
1223 // PowerPC doesn't have preinc load/store instructions for vectors.
1227 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1229 // Common code will reject creating a pre-inc form if the base pointer
1230 // is a frame index, or if N is a store and the base pointer is either
1231 // the same as or a predecessor of the value being stored. Check for
1232 // those situations here, and try with swapped Base/Offset instead.
1235 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1238 SDValue Val = cast<StoreSDNode>(N)->getValue();
1239 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1244 std::swap(Base, Offset);
1250 // LDU/STU can only handle immediates that are a multiple of 4.
1251 if (VT != MVT::i64) {
1252 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1255 // LDU/STU need an address with at least 4-byte alignment.
1259 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1263 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1264 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1265 // sext i32 to i64 when addr mode is r+i.
1266 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1267 LD->getExtensionType() == ISD::SEXTLOAD &&
1268 isa<ConstantSDNode>(Offset))
1276 //===----------------------------------------------------------------------===//
1277 // LowerOperation implementation
1278 //===----------------------------------------------------------------------===//
1280 /// GetLabelAccessInfo - Return true if we should reference labels using a
1281 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1282 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1283 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1284 HiOpFlags = PPCII::MO_HA;
1285 LoOpFlags = PPCII::MO_LO;
1287 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1288 // non-darwin platform. We don't support PIC on other platforms yet.
1289 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1290 TM.getSubtarget<PPCSubtarget>().isDarwin();
1292 HiOpFlags |= PPCII::MO_PIC_FLAG;
1293 LoOpFlags |= PPCII::MO_PIC_FLAG;
1296 // If this is a reference to a global value that requires a non-lazy-ptr, make
1297 // sure that instruction lowering adds it.
1298 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1299 HiOpFlags |= PPCII::MO_NLP_FLAG;
1300 LoOpFlags |= PPCII::MO_NLP_FLAG;
1302 if (GV->hasHiddenVisibility()) {
1303 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1304 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1311 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1312 SelectionDAG &DAG) {
1313 EVT PtrVT = HiPart.getValueType();
1314 SDValue Zero = DAG.getConstant(0, PtrVT);
1317 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1318 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1320 // With PIC, the first instruction is actually "GR+hi(&G)".
1322 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1323 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1325 // Generate non-pic code that has direct accesses to the constant pool.
1326 // The address of the global is just (hi(&g)+lo(&g)).
1327 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1330 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1331 SelectionDAG &DAG) const {
1332 EVT PtrVT = Op.getValueType();
1333 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1334 const Constant *C = CP->getConstVal();
1336 // 64-bit SVR4 ABI code is always position-independent.
1337 // The actual address of the GlobalValue is stored in the TOC.
1338 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1339 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1340 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1341 DAG.getRegister(PPC::X2, MVT::i64));
1344 unsigned MOHiFlag, MOLoFlag;
1345 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1347 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1349 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1350 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1353 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1354 EVT PtrVT = Op.getValueType();
1355 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1357 // 64-bit SVR4 ABI code is always position-independent.
1358 // The actual address of the GlobalValue is stored in the TOC.
1359 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1360 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1361 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1362 DAG.getRegister(PPC::X2, MVT::i64));
1365 unsigned MOHiFlag, MOLoFlag;
1366 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1367 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1368 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1369 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1372 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1373 SelectionDAG &DAG) const {
1374 EVT PtrVT = Op.getValueType();
1376 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1378 unsigned MOHiFlag, MOLoFlag;
1379 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1380 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1381 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1382 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1385 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1386 SelectionDAG &DAG) const {
1388 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1390 const GlobalValue *GV = GA->getGlobal();
1391 EVT PtrVT = getPointerTy();
1392 bool is64bit = PPCSubTarget.isPPC64();
1394 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1396 if (Model == TLSModel::LocalExec) {
1397 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1398 PPCII::MO_TPREL_HA);
1399 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1400 PPCII::MO_TPREL_LO);
1401 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1402 is64bit ? MVT::i64 : MVT::i32);
1403 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1404 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1408 llvm_unreachable("only local-exec is currently supported for ppc32");
1410 if (Model == TLSModel::InitialExec) {
1411 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1412 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1414 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1415 SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1416 PtrVT, GOTReg, TGA);
1417 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1418 PtrVT, TGA, TPOffsetHi);
1419 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1422 if (Model == TLSModel::GeneralDynamic) {
1423 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1424 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1425 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1427 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1430 // We need a chain node, and don't have one handy. The underlying
1431 // call has no side effects, so using the function entry node
1433 SDValue Chain = DAG.getEntryNode();
1434 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1435 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1436 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1437 PtrVT, ParmReg, TGA);
1438 // The return value from GET_TLS_ADDR really is in X3 already, but
1439 // some hacks are needed here to tie everything together. The extra
1440 // copies dissolve during subsequent transforms.
1441 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1442 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1445 if (Model == TLSModel::LocalDynamic) {
1446 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1447 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1448 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1450 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1453 // We need a chain node, and don't have one handy. The underlying
1454 // call has no side effects, so using the function entry node
1456 SDValue Chain = DAG.getEntryNode();
1457 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1458 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1459 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1460 PtrVT, ParmReg, TGA);
1461 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1462 // some hacks are needed here to tie everything together. The extra
1463 // copies dissolve during subsequent transforms.
1464 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1465 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1466 Chain, ParmReg, TGA);
1467 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1470 llvm_unreachable("Unknown TLS model!");
1473 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1474 SelectionDAG &DAG) const {
1475 EVT PtrVT = Op.getValueType();
1476 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1478 const GlobalValue *GV = GSDN->getGlobal();
1480 // 64-bit SVR4 ABI code is always position-independent.
1481 // The actual address of the GlobalValue is stored in the TOC.
1482 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1483 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1484 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1485 DAG.getRegister(PPC::X2, MVT::i64));
1488 unsigned MOHiFlag, MOLoFlag;
1489 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1492 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1494 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1496 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1498 // If the global reference is actually to a non-lazy-pointer, we have to do an
1499 // extra load to get the address of the global.
1500 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1501 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1502 false, false, false, 0);
1506 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1507 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1510 // If we're comparing for equality to zero, expose the fact that this is
1511 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1512 // fold the new nodes.
1513 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1514 if (C->isNullValue() && CC == ISD::SETEQ) {
1515 EVT VT = Op.getOperand(0).getValueType();
1516 SDValue Zext = Op.getOperand(0);
1517 if (VT.bitsLT(MVT::i32)) {
1519 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1521 unsigned Log2b = Log2_32(VT.getSizeInBits());
1522 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1523 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1524 DAG.getConstant(Log2b, MVT::i32));
1525 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1527 // Leave comparisons against 0 and -1 alone for now, since they're usually
1528 // optimized. FIXME: revisit this when we can custom lower all setcc
1530 if (C->isAllOnesValue() || C->isNullValue())
1534 // If we have an integer seteq/setne, turn it into a compare against zero
1535 // by xor'ing the rhs with the lhs, which is faster than setting a
1536 // condition register, reading it back out, and masking the correct bit. The
1537 // normal approach here uses sub to do this instead of xor. Using xor exposes
1538 // the result to other bit-twiddling opportunities.
1539 EVT LHSVT = Op.getOperand(0).getValueType();
1540 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1541 EVT VT = Op.getValueType();
1542 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1544 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1549 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1550 const PPCSubtarget &Subtarget) const {
1551 SDNode *Node = Op.getNode();
1552 EVT VT = Node->getValueType(0);
1553 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1554 SDValue InChain = Node->getOperand(0);
1555 SDValue VAListPtr = Node->getOperand(1);
1556 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1559 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1562 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1563 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1565 InChain = GprIndex.getValue(1);
1567 if (VT == MVT::i64) {
1568 // Check if GprIndex is even
1569 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1570 DAG.getConstant(1, MVT::i32));
1571 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1572 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1573 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1574 DAG.getConstant(1, MVT::i32));
1575 // Align GprIndex to be even if it isn't
1576 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1580 // fpr index is 1 byte after gpr
1581 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1582 DAG.getConstant(1, MVT::i32));
1585 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1586 FprPtr, MachinePointerInfo(SV), MVT::i8,
1588 InChain = FprIndex.getValue(1);
1590 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1591 DAG.getConstant(8, MVT::i32));
1593 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1594 DAG.getConstant(4, MVT::i32));
1597 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1598 MachinePointerInfo(), false, false,
1600 InChain = OverflowArea.getValue(1);
1602 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1603 MachinePointerInfo(), false, false,
1605 InChain = RegSaveArea.getValue(1);
1607 // select overflow_area if index > 8
1608 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1609 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1611 // adjustment constant gpr_index * 4/8
1612 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1613 VT.isInteger() ? GprIndex : FprIndex,
1614 DAG.getConstant(VT.isInteger() ? 4 : 8,
1617 // OurReg = RegSaveArea + RegConstant
1618 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1621 // Floating types are 32 bytes into RegSaveArea
1622 if (VT.isFloatingPoint())
1623 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1624 DAG.getConstant(32, MVT::i32));
1626 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1627 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1628 VT.isInteger() ? GprIndex : FprIndex,
1629 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1632 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1633 VT.isInteger() ? VAListPtr : FprPtr,
1634 MachinePointerInfo(SV),
1635 MVT::i8, false, false, 0);
1637 // determine if we should load from reg_save_area or overflow_area
1638 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1640 // increase overflow_area by 4/8 if gpr/fpr > 8
1641 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1642 DAG.getConstant(VT.isInteger() ? 4 : 8,
1645 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1648 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1650 MachinePointerInfo(),
1651 MVT::i32, false, false, 0);
1653 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1654 false, false, false, 0);
1657 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1658 const PPCSubtarget &Subtarget) const {
1659 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1661 // We have to copy the entire va_list struct:
1662 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1663 return DAG.getMemcpy(Op.getOperand(0), Op,
1664 Op.getOperand(1), Op.getOperand(2),
1665 DAG.getConstant(12, MVT::i32), 8, false, true,
1666 MachinePointerInfo(), MachinePointerInfo());
1669 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1670 SelectionDAG &DAG) const {
1671 return Op.getOperand(0);
1674 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1675 SelectionDAG &DAG) const {
1676 SDValue Chain = Op.getOperand(0);
1677 SDValue Trmp = Op.getOperand(1); // trampoline
1678 SDValue FPtr = Op.getOperand(2); // nested function
1679 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1682 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1683 bool isPPC64 = (PtrVT == MVT::i64);
1685 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1688 TargetLowering::ArgListTy Args;
1689 TargetLowering::ArgListEntry Entry;
1691 Entry.Ty = IntPtrTy;
1692 Entry.Node = Trmp; Args.push_back(Entry);
1694 // TrampSize == (isPPC64 ? 48 : 40);
1695 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1696 isPPC64 ? MVT::i64 : MVT::i32);
1697 Args.push_back(Entry);
1699 Entry.Node = FPtr; Args.push_back(Entry);
1700 Entry.Node = Nest; Args.push_back(Entry);
1702 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1703 TargetLowering::CallLoweringInfo CLI(Chain,
1704 Type::getVoidTy(*DAG.getContext()),
1705 false, false, false, false, 0,
1707 /*isTailCall=*/false,
1708 /*doesNotRet=*/false,
1709 /*isReturnValueUsed=*/true,
1710 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1712 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1714 return CallResult.second;
1717 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1718 const PPCSubtarget &Subtarget) const {
1719 MachineFunction &MF = DAG.getMachineFunction();
1720 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1724 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1725 // vastart just stores the address of the VarArgsFrameIndex slot into the
1726 // memory location argument.
1727 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1728 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1729 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1730 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1731 MachinePointerInfo(SV),
1735 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1736 // We suppose the given va_list is already allocated.
1739 // char gpr; /* index into the array of 8 GPRs
1740 // * stored in the register save area
1741 // * gpr=0 corresponds to r3,
1742 // * gpr=1 to r4, etc.
1744 // char fpr; /* index into the array of 8 FPRs
1745 // * stored in the register save area
1746 // * fpr=0 corresponds to f1,
1747 // * fpr=1 to f2, etc.
1749 // char *overflow_arg_area;
1750 // /* location on stack that holds
1751 // * the next overflow argument
1753 // char *reg_save_area;
1754 // /* where r3:r10 and f1:f8 (if saved)
1760 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1761 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1764 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1766 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1768 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1771 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1772 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1774 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1775 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1777 uint64_t FPROffset = 1;
1778 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1780 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1782 // Store first byte : number of int regs
1783 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1785 MachinePointerInfo(SV),
1786 MVT::i8, false, false, 0);
1787 uint64_t nextOffset = FPROffset;
1788 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1791 // Store second byte : number of float regs
1792 SDValue secondStore =
1793 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1794 MachinePointerInfo(SV, nextOffset), MVT::i8,
1796 nextOffset += StackOffset;
1797 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1799 // Store second word : arguments given on stack
1800 SDValue thirdStore =
1801 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1802 MachinePointerInfo(SV, nextOffset),
1804 nextOffset += FrameOffset;
1805 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1807 // Store third word : arguments given in registers
1808 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1809 MachinePointerInfo(SV, nextOffset),
1814 #include "PPCGenCallingConv.inc"
1816 // Function whose sole purpose is to kill compiler warnings
1817 // stemming from unused functions included from PPCGenCallingConv.inc.
1818 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
1819 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
1822 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1823 CCValAssign::LocInfo &LocInfo,
1824 ISD::ArgFlagsTy &ArgFlags,
1829 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1831 CCValAssign::LocInfo &LocInfo,
1832 ISD::ArgFlagsTy &ArgFlags,
1834 static const uint16_t ArgRegs[] = {
1835 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1836 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1838 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1840 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1842 // Skip one register if the first unallocated register has an even register
1843 // number and there are still argument registers available which have not been
1844 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1845 // need to skip a register if RegNum is odd.
1846 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1847 State.AllocateReg(ArgRegs[RegNum]);
1850 // Always return false here, as this function only makes sure that the first
1851 // unallocated register has an odd register number and does not actually
1852 // allocate a register for the current argument.
1856 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1858 CCValAssign::LocInfo &LocInfo,
1859 ISD::ArgFlagsTy &ArgFlags,
1861 static const uint16_t ArgRegs[] = {
1862 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1866 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1868 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1870 // If there is only one Floating-point register left we need to put both f64
1871 // values of a split ppc_fp128 value on the stack.
1872 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1873 State.AllocateReg(ArgRegs[RegNum]);
1876 // Always return false here, as this function only makes sure that the two f64
1877 // values a ppc_fp128 value is split into are both passed in registers or both
1878 // passed on the stack and does not actually allocate a register for the
1879 // current argument.
1883 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1885 static const uint16_t *GetFPR() {
1886 static const uint16_t FPR[] = {
1887 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1888 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1894 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1896 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1897 unsigned PtrByteSize) {
1898 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1899 if (Flags.isByVal())
1900 ArgSize = Flags.getByValSize();
1901 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1907 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1908 CallingConv::ID CallConv, bool isVarArg,
1909 const SmallVectorImpl<ISD::InputArg>
1911 SDLoc dl, SelectionDAG &DAG,
1912 SmallVectorImpl<SDValue> &InVals)
1914 if (PPCSubTarget.isSVR4ABI()) {
1915 if (PPCSubTarget.isPPC64())
1916 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
1919 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
1922 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1928 PPCTargetLowering::LowerFormalArguments_32SVR4(
1930 CallingConv::ID CallConv, bool isVarArg,
1931 const SmallVectorImpl<ISD::InputArg>
1933 SDLoc dl, SelectionDAG &DAG,
1934 SmallVectorImpl<SDValue> &InVals) const {
1936 // 32-bit SVR4 ABI Stack Frame Layout:
1937 // +-----------------------------------+
1938 // +--> | Back chain |
1939 // | +-----------------------------------+
1940 // | | Floating-point register save area |
1941 // | +-----------------------------------+
1942 // | | General register save area |
1943 // | +-----------------------------------+
1944 // | | CR save word |
1945 // | +-----------------------------------+
1946 // | | VRSAVE save word |
1947 // | +-----------------------------------+
1948 // | | Alignment padding |
1949 // | +-----------------------------------+
1950 // | | Vector register save area |
1951 // | +-----------------------------------+
1952 // | | Local variable space |
1953 // | +-----------------------------------+
1954 // | | Parameter list area |
1955 // | +-----------------------------------+
1956 // | | LR save word |
1957 // | +-----------------------------------+
1958 // SP--> +--- | Back chain |
1959 // +-----------------------------------+
1962 // System V Application Binary Interface PowerPC Processor Supplement
1963 // AltiVec Technology Programming Interface Manual
1965 MachineFunction &MF = DAG.getMachineFunction();
1966 MachineFrameInfo *MFI = MF.getFrameInfo();
1967 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1969 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1970 // Potential tail calls could cause overwriting of argument stack slots.
1971 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1972 (CallConv == CallingConv::Fast));
1973 unsigned PtrByteSize = 4;
1975 // Assign locations to all of the incoming arguments.
1976 SmallVector<CCValAssign, 16> ArgLocs;
1977 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1978 getTargetMachine(), ArgLocs, *DAG.getContext());
1980 // Reserve space for the linkage area on the stack.
1981 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
1983 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
1985 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1986 CCValAssign &VA = ArgLocs[i];
1988 // Arguments stored in registers.
1989 if (VA.isRegLoc()) {
1990 const TargetRegisterClass *RC;
1991 EVT ValVT = VA.getValVT();
1993 switch (ValVT.getSimpleVT().SimpleTy) {
1995 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1997 RC = &PPC::GPRCRegClass;
2000 RC = &PPC::F4RCRegClass;
2003 RC = &PPC::F8RCRegClass;
2009 RC = &PPC::VRRCRegClass;
2013 // Transform the arguments stored in physical registers into virtual ones.
2014 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2015 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
2017 InVals.push_back(ArgValue);
2019 // Argument stored in memory.
2020 assert(VA.isMemLoc());
2022 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
2023 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2026 // Create load nodes to retrieve arguments from the stack.
2027 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2028 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2029 MachinePointerInfo(),
2030 false, false, false, 0));
2034 // Assign locations to all of the incoming aggregate by value arguments.
2035 // Aggregates passed by value are stored in the local variable space of the
2036 // caller's stack frame, right above the parameter list area.
2037 SmallVector<CCValAssign, 16> ByValArgLocs;
2038 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2039 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2041 // Reserve stack space for the allocations in CCInfo.
2042 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2044 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2046 // Area that is at least reserved in the caller of this function.
2047 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2049 // Set the size that is at least reserved in caller of this function. Tail
2050 // call optimized function's reserved stack space needs to be aligned so that
2051 // taking the difference between two stack areas will result in an aligned
2053 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2056 std::max(MinReservedArea,
2057 PPCFrameLowering::getMinCallFrameSize(false, false));
2059 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2060 getStackAlignment();
2061 unsigned AlignMask = TargetAlign-1;
2062 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2064 FI->setMinReservedArea(MinReservedArea);
2066 SmallVector<SDValue, 8> MemOps;
2068 // If the function takes variable number of arguments, make a frame index for
2069 // the start of the first vararg value... for expansion of llvm.va_start.
2071 static const uint16_t GPArgRegs[] = {
2072 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2073 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2075 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2077 static const uint16_t FPArgRegs[] = {
2078 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2081 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2083 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2085 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2088 // Make room for NumGPArgRegs and NumFPArgRegs.
2089 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2090 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2092 FuncInfo->setVarArgsStackOffset(
2093 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2094 CCInfo.getNextStackOffset(), true));
2096 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2097 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2099 // The fixed integer arguments of a variadic function are stored to the
2100 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2101 // the result of va_next.
2102 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2103 // Get an existing live-in vreg, or add a new one.
2104 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2106 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2108 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2109 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2110 MachinePointerInfo(), false, false, 0);
2111 MemOps.push_back(Store);
2112 // Increment the address by four for the next argument to store
2113 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2114 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2117 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2119 // The double arguments are stored to the VarArgsFrameIndex
2121 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2122 // Get an existing live-in vreg, or add a new one.
2123 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2125 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2127 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2128 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2129 MachinePointerInfo(), false, false, 0);
2130 MemOps.push_back(Store);
2131 // Increment the address by eight for the next argument to store
2132 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2134 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2138 if (!MemOps.empty())
2139 Chain = DAG.getNode(ISD::TokenFactor, dl,
2140 MVT::Other, &MemOps[0], MemOps.size());
2145 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2146 // value to MVT::i64 and then truncate to the correct register size.
2148 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2149 SelectionDAG &DAG, SDValue ArgVal,
2152 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2153 DAG.getValueType(ObjectVT));
2154 else if (Flags.isZExt())
2155 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2156 DAG.getValueType(ObjectVT));
2158 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2161 // Set the size that is at least reserved in caller of this function. Tail
2162 // call optimized functions' reserved stack space needs to be aligned so that
2163 // taking the difference between two stack areas will result in an aligned
2166 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2167 unsigned nAltivecParamsAtEnd,
2168 unsigned MinReservedArea,
2169 bool isPPC64) const {
2170 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2171 // Add the Altivec parameters at the end, if needed.
2172 if (nAltivecParamsAtEnd) {
2173 MinReservedArea = ((MinReservedArea+15)/16)*16;
2174 MinReservedArea += 16*nAltivecParamsAtEnd;
2177 std::max(MinReservedArea,
2178 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2179 unsigned TargetAlign
2180 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2181 getStackAlignment();
2182 unsigned AlignMask = TargetAlign-1;
2183 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2184 FI->setMinReservedArea(MinReservedArea);
2188 PPCTargetLowering::LowerFormalArguments_64SVR4(
2190 CallingConv::ID CallConv, bool isVarArg,
2191 const SmallVectorImpl<ISD::InputArg>
2193 SDLoc dl, SelectionDAG &DAG,
2194 SmallVectorImpl<SDValue> &InVals) const {
2195 // TODO: add description of PPC stack frame format, or at least some docs.
2197 MachineFunction &MF = DAG.getMachineFunction();
2198 MachineFrameInfo *MFI = MF.getFrameInfo();
2199 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2201 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2202 // Potential tail calls could cause overwriting of argument stack slots.
2203 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2204 (CallConv == CallingConv::Fast));
2205 unsigned PtrByteSize = 8;
2207 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2208 // Area that is at least reserved in caller of this function.
2209 unsigned MinReservedArea = ArgOffset;
2211 static const uint16_t GPR[] = {
2212 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2213 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2216 static const uint16_t *FPR = GetFPR();
2218 static const uint16_t VR[] = {
2219 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2220 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2223 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2224 const unsigned Num_FPR_Regs = 13;
2225 const unsigned Num_VR_Regs = array_lengthof(VR);
2227 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2229 // Add DAG nodes to load the arguments or copy them out of registers. On
2230 // entry to a function on PPC, the arguments start after the linkage area,
2231 // although the first ones are often in registers.
2233 SmallVector<SDValue, 8> MemOps;
2234 unsigned nAltivecParamsAtEnd = 0;
2235 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2236 unsigned CurArgIdx = 0;
2237 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2239 bool needsLoad = false;
2240 EVT ObjectVT = Ins[ArgNo].VT;
2241 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2242 unsigned ArgSize = ObjSize;
2243 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2244 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2245 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2247 unsigned CurArgOffset = ArgOffset;
2249 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2250 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2251 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2253 MinReservedArea = ((MinReservedArea+15)/16)*16;
2254 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2258 nAltivecParamsAtEnd++;
2260 // Calculate min reserved area.
2261 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2265 // FIXME the codegen can be much improved in some cases.
2266 // We do not have to keep everything in memory.
2267 if (Flags.isByVal()) {
2268 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2269 ObjSize = Flags.getByValSize();
2270 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2271 // Empty aggregate parameters do not take up registers. Examples:
2275 // etc. However, we have to provide a place-holder in InVals, so
2276 // pretend we have an 8-byte item at the current address for that
2279 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2280 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2281 InVals.push_back(FIN);
2284 // All aggregates smaller than 8 bytes must be passed right-justified.
2285 if (ObjSize < PtrByteSize)
2286 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2287 // The value of the object is its address.
2288 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2289 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2290 InVals.push_back(FIN);
2293 if (GPR_idx != Num_GPR_Regs) {
2294 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2295 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2298 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2299 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2300 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2301 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2302 MachinePointerInfo(FuncArg, CurArgOffset),
2303 ObjType, false, false, 0);
2305 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2306 // store the whole register as-is to the parameter save area
2307 // slot. The address of the parameter was already calculated
2308 // above (InVals.push_back(FIN)) to be the right-justified
2309 // offset within the slot. For this store, we need a new
2310 // frame index that points at the beginning of the slot.
2311 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2312 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2313 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2314 MachinePointerInfo(FuncArg, ArgOffset),
2318 MemOps.push_back(Store);
2321 // Whether we copied from a register or not, advance the offset
2322 // into the parameter save area by a full doubleword.
2323 ArgOffset += PtrByteSize;
2327 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2328 // Store whatever pieces of the object are in registers
2329 // to memory. ArgOffset will be the address of the beginning
2331 if (GPR_idx != Num_GPR_Regs) {
2333 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2334 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2335 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2336 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2337 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2338 MachinePointerInfo(FuncArg, ArgOffset),
2340 MemOps.push_back(Store);
2342 ArgOffset += PtrByteSize;
2344 ArgOffset += ArgSize - j;
2351 switch (ObjectVT.getSimpleVT().SimpleTy) {
2352 default: llvm_unreachable("Unhandled argument type!");
2355 if (GPR_idx != Num_GPR_Regs) {
2356 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2357 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2359 if (ObjectVT == MVT::i32)
2360 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2361 // value to MVT::i64 and then truncate to the correct register size.
2362 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2367 ArgSize = PtrByteSize;
2374 // Every 8 bytes of argument space consumes one of the GPRs available for
2375 // argument passing.
2376 if (GPR_idx != Num_GPR_Regs) {
2379 if (FPR_idx != Num_FPR_Regs) {
2382 if (ObjectVT == MVT::f32)
2383 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2385 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2387 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2391 ArgSize = PtrByteSize;
2400 // Note that vector arguments in registers don't reserve stack space,
2401 // except in varargs functions.
2402 if (VR_idx != Num_VR_Regs) {
2403 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2404 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2406 while ((ArgOffset % 16) != 0) {
2407 ArgOffset += PtrByteSize;
2408 if (GPR_idx != Num_GPR_Regs)
2412 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2416 // Vectors are aligned.
2417 ArgOffset = ((ArgOffset+15)/16)*16;
2418 CurArgOffset = ArgOffset;
2425 // We need to load the argument to a virtual register if we determined
2426 // above that we ran out of physical registers of the appropriate type.
2428 int FI = MFI->CreateFixedObject(ObjSize,
2429 CurArgOffset + (ArgSize - ObjSize),
2431 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2432 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2433 false, false, false, 0);
2436 InVals.push_back(ArgVal);
2439 // Set the size that is at least reserved in caller of this function. Tail
2440 // call optimized functions' reserved stack space needs to be aligned so that
2441 // taking the difference between two stack areas will result in an aligned
2443 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2445 // If the function takes variable number of arguments, make a frame index for
2446 // the start of the first vararg value... for expansion of llvm.va_start.
2448 int Depth = ArgOffset;
2450 FuncInfo->setVarArgsFrameIndex(
2451 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2452 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2454 // If this function is vararg, store any remaining integer argument regs
2455 // to their spots on the stack so that they may be loaded by deferencing the
2456 // result of va_next.
2457 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2458 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2459 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2460 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2461 MachinePointerInfo(), false, false, 0);
2462 MemOps.push_back(Store);
2463 // Increment the address by four for the next argument to store
2464 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2465 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2469 if (!MemOps.empty())
2470 Chain = DAG.getNode(ISD::TokenFactor, dl,
2471 MVT::Other, &MemOps[0], MemOps.size());
2477 PPCTargetLowering::LowerFormalArguments_Darwin(
2479 CallingConv::ID CallConv, bool isVarArg,
2480 const SmallVectorImpl<ISD::InputArg>
2482 SDLoc dl, SelectionDAG &DAG,
2483 SmallVectorImpl<SDValue> &InVals) const {
2484 // TODO: add description of PPC stack frame format, or at least some docs.
2486 MachineFunction &MF = DAG.getMachineFunction();
2487 MachineFrameInfo *MFI = MF.getFrameInfo();
2488 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2490 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2491 bool isPPC64 = PtrVT == MVT::i64;
2492 // Potential tail calls could cause overwriting of argument stack slots.
2493 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2494 (CallConv == CallingConv::Fast));
2495 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2497 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2498 // Area that is at least reserved in caller of this function.
2499 unsigned MinReservedArea = ArgOffset;
2501 static const uint16_t GPR_32[] = { // 32-bit registers.
2502 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2503 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2505 static const uint16_t GPR_64[] = { // 64-bit registers.
2506 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2507 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2510 static const uint16_t *FPR = GetFPR();
2512 static const uint16_t VR[] = {
2513 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2514 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2517 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2518 const unsigned Num_FPR_Regs = 13;
2519 const unsigned Num_VR_Regs = array_lengthof( VR);
2521 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2523 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2525 // In 32-bit non-varargs functions, the stack space for vectors is after the
2526 // stack space for non-vectors. We do not use this space unless we have
2527 // too many vectors to fit in registers, something that only occurs in
2528 // constructed examples:), but we have to walk the arglist to figure
2529 // that out...for the pathological case, compute VecArgOffset as the
2530 // start of the vector parameter area. Computing VecArgOffset is the
2531 // entire point of the following loop.
2532 unsigned VecArgOffset = ArgOffset;
2533 if (!isVarArg && !isPPC64) {
2534 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2536 EVT ObjectVT = Ins[ArgNo].VT;
2537 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2539 if (Flags.isByVal()) {
2540 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2541 unsigned ObjSize = Flags.getByValSize();
2543 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2544 VecArgOffset += ArgSize;
2548 switch(ObjectVT.getSimpleVT().SimpleTy) {
2549 default: llvm_unreachable("Unhandled argument type!");
2554 case MVT::i64: // PPC64
2556 // FIXME: We are guaranteed to be !isPPC64 at this point.
2557 // Does MVT::i64 apply?
2564 // Nothing to do, we're only looking at Nonvector args here.
2569 // We've found where the vector parameter area in memory is. Skip the
2570 // first 12 parameters; these don't use that memory.
2571 VecArgOffset = ((VecArgOffset+15)/16)*16;
2572 VecArgOffset += 12*16;
2574 // Add DAG nodes to load the arguments or copy them out of registers. On
2575 // entry to a function on PPC, the arguments start after the linkage area,
2576 // although the first ones are often in registers.
2578 SmallVector<SDValue, 8> MemOps;
2579 unsigned nAltivecParamsAtEnd = 0;
2580 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2581 unsigned CurArgIdx = 0;
2582 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2584 bool needsLoad = false;
2585 EVT ObjectVT = Ins[ArgNo].VT;
2586 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2587 unsigned ArgSize = ObjSize;
2588 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2589 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2590 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2592 unsigned CurArgOffset = ArgOffset;
2594 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2595 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2596 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2597 if (isVarArg || isPPC64) {
2598 MinReservedArea = ((MinReservedArea+15)/16)*16;
2599 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2602 } else nAltivecParamsAtEnd++;
2604 // Calculate min reserved area.
2605 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2609 // FIXME the codegen can be much improved in some cases.
2610 // We do not have to keep everything in memory.
2611 if (Flags.isByVal()) {
2612 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2613 ObjSize = Flags.getByValSize();
2614 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2615 // Objects of size 1 and 2 are right justified, everything else is
2616 // left justified. This means the memory address is adjusted forwards.
2617 if (ObjSize==1 || ObjSize==2) {
2618 CurArgOffset = CurArgOffset + (4 - ObjSize);
2620 // The value of the object is its address.
2621 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2622 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2623 InVals.push_back(FIN);
2624 if (ObjSize==1 || ObjSize==2) {
2625 if (GPR_idx != Num_GPR_Regs) {
2628 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2630 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2631 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2632 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2633 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2634 MachinePointerInfo(FuncArg,
2636 ObjType, false, false, 0);
2637 MemOps.push_back(Store);
2641 ArgOffset += PtrByteSize;
2645 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2646 // Store whatever pieces of the object are in registers
2647 // to memory. ArgOffset will be the address of the beginning
2649 if (GPR_idx != Num_GPR_Regs) {
2652 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2654 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2655 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2656 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2657 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2658 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2659 MachinePointerInfo(FuncArg, ArgOffset),
2661 MemOps.push_back(Store);
2663 ArgOffset += PtrByteSize;
2665 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2672 switch (ObjectVT.getSimpleVT().SimpleTy) {
2673 default: llvm_unreachable("Unhandled argument type!");
2676 if (GPR_idx != Num_GPR_Regs) {
2677 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2678 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2682 ArgSize = PtrByteSize;
2684 // All int arguments reserve stack space in the Darwin ABI.
2685 ArgOffset += PtrByteSize;
2689 case MVT::i64: // PPC64
2690 if (GPR_idx != Num_GPR_Regs) {
2691 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2692 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2694 if (ObjectVT == MVT::i32)
2695 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2696 // value to MVT::i64 and then truncate to the correct register size.
2697 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2702 ArgSize = PtrByteSize;
2704 // All int arguments reserve stack space in the Darwin ABI.
2710 // Every 4 bytes of argument space consumes one of the GPRs available for
2711 // argument passing.
2712 if (GPR_idx != Num_GPR_Regs) {
2714 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2717 if (FPR_idx != Num_FPR_Regs) {
2720 if (ObjectVT == MVT::f32)
2721 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2723 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2725 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2731 // All FP arguments reserve stack space in the Darwin ABI.
2732 ArgOffset += isPPC64 ? 8 : ObjSize;
2738 // Note that vector arguments in registers don't reserve stack space,
2739 // except in varargs functions.
2740 if (VR_idx != Num_VR_Regs) {
2741 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2742 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2744 while ((ArgOffset % 16) != 0) {
2745 ArgOffset += PtrByteSize;
2746 if (GPR_idx != Num_GPR_Regs)
2750 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2754 if (!isVarArg && !isPPC64) {
2755 // Vectors go after all the nonvectors.
2756 CurArgOffset = VecArgOffset;
2759 // Vectors are aligned.
2760 ArgOffset = ((ArgOffset+15)/16)*16;
2761 CurArgOffset = ArgOffset;
2769 // We need to load the argument to a virtual register if we determined above
2770 // that we ran out of physical registers of the appropriate type.
2772 int FI = MFI->CreateFixedObject(ObjSize,
2773 CurArgOffset + (ArgSize - ObjSize),
2775 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2776 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2777 false, false, false, 0);
2780 InVals.push_back(ArgVal);
2783 // Set the size that is at least reserved in caller of this function. Tail
2784 // call optimized functions' reserved stack space needs to be aligned so that
2785 // taking the difference between two stack areas will result in an aligned
2787 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
2789 // If the function takes variable number of arguments, make a frame index for
2790 // the start of the first vararg value... for expansion of llvm.va_start.
2792 int Depth = ArgOffset;
2794 FuncInfo->setVarArgsFrameIndex(
2795 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2797 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2799 // If this function is vararg, store any remaining integer argument regs
2800 // to their spots on the stack so that they may be loaded by deferencing the
2801 // result of va_next.
2802 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2806 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2808 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2810 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2811 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2812 MachinePointerInfo(), false, false, 0);
2813 MemOps.push_back(Store);
2814 // Increment the address by four for the next argument to store
2815 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2816 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2820 if (!MemOps.empty())
2821 Chain = DAG.getNode(ISD::TokenFactor, dl,
2822 MVT::Other, &MemOps[0], MemOps.size());
2827 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
2828 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
2830 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2834 const SmallVectorImpl<ISD::OutputArg>
2836 const SmallVectorImpl<SDValue> &OutVals,
2837 unsigned &nAltivecParamsAtEnd) {
2838 // Count how many bytes are to be pushed on the stack, including the linkage
2839 // area, and parameter passing area. We start with 24/48 bytes, which is
2840 // prereserved space for [SP][CR][LR][3 x unused].
2841 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2842 unsigned NumOps = Outs.size();
2843 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2845 // Add up all the space actually used.
2846 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2847 // they all go in registers, but we must reserve stack space for them for
2848 // possible use by the caller. In varargs or 64-bit calls, parameters are
2849 // assigned stack space in order, with padding so Altivec parameters are
2851 nAltivecParamsAtEnd = 0;
2852 for (unsigned i = 0; i != NumOps; ++i) {
2853 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2854 EVT ArgVT = Outs[i].VT;
2855 // Varargs Altivec parameters are padded to a 16 byte boundary.
2856 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2857 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2858 if (!isVarArg && !isPPC64) {
2859 // Non-varargs Altivec parameters go after all the non-Altivec
2860 // parameters; handle those later so we know how much padding we need.
2861 nAltivecParamsAtEnd++;
2864 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2865 NumBytes = ((NumBytes+15)/16)*16;
2867 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2870 // Allow for Altivec parameters at the end, if needed.
2871 if (nAltivecParamsAtEnd) {
2872 NumBytes = ((NumBytes+15)/16)*16;
2873 NumBytes += 16*nAltivecParamsAtEnd;
2876 // The prolog code of the callee may store up to 8 GPR argument registers to
2877 // the stack, allowing va_start to index over them in memory if its varargs.
2878 // Because we cannot tell if this is needed on the caller side, we have to
2879 // conservatively assume that it is needed. As such, make sure we have at
2880 // least enough stack space for the caller to store the 8 GPRs.
2881 NumBytes = std::max(NumBytes,
2882 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2884 // Tail call needs the stack to be aligned.
2885 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2886 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2887 getFrameLowering()->getStackAlignment();
2888 unsigned AlignMask = TargetAlign-1;
2889 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2895 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2896 /// adjusted to accommodate the arguments for the tailcall.
2897 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2898 unsigned ParamSize) {
2900 if (!isTailCall) return 0;
2902 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2903 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2904 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2905 // Remember only if the new adjustement is bigger.
2906 if (SPDiff < FI->getTailCallSPDelta())
2907 FI->setTailCallSPDelta(SPDiff);
2912 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2913 /// for tail call optimization. Targets which want to do tail call
2914 /// optimization should implement this function.
2916 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2917 CallingConv::ID CalleeCC,
2919 const SmallVectorImpl<ISD::InputArg> &Ins,
2920 SelectionDAG& DAG) const {
2921 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2924 // Variable argument functions are not supported.
2928 MachineFunction &MF = DAG.getMachineFunction();
2929 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2930 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2931 // Functions containing by val parameters are not supported.
2932 for (unsigned i = 0; i != Ins.size(); i++) {
2933 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2934 if (Flags.isByVal()) return false;
2937 // Non PIC/GOT tail calls are supported.
2938 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2941 // At the moment we can only do local tail calls (in same module, hidden
2942 // or protected) if we are generating PIC.
2943 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2944 return G->getGlobal()->hasHiddenVisibility()
2945 || G->getGlobal()->hasProtectedVisibility();
2951 /// isCallCompatibleAddress - Return the immediate to use if the specified
2952 /// 32-bit value is representable in the immediate field of a BxA instruction.
2953 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2954 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2957 int Addr = C->getZExtValue();
2958 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2959 SignExtend32<26>(Addr) != Addr)
2960 return 0; // Top 6 bits have to be sext of immediate.
2962 return DAG.getConstant((int)C->getZExtValue() >> 2,
2963 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2968 struct TailCallArgumentInfo {
2973 TailCallArgumentInfo() : FrameIdx(0) {}
2978 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2980 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2982 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
2983 SmallVectorImpl<SDValue> &MemOpChains,
2985 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2986 SDValue Arg = TailCallArgs[i].Arg;
2987 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2988 int FI = TailCallArgs[i].FrameIdx;
2989 // Store relative to framepointer.
2990 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2991 MachinePointerInfo::getFixedStack(FI),
2996 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2997 /// the appropriate stack slot for the tail call optimized function call.
2998 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2999 MachineFunction &MF,
3008 // Calculate the new stack slot for the return address.
3009 int SlotSize = isPPC64 ? 8 : 4;
3010 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3012 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3013 NewRetAddrLoc, true);
3014 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3015 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3016 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3017 MachinePointerInfo::getFixedStack(NewRetAddr),
3020 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3021 // slot as the FP is never overwritten.
3024 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3025 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3027 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3028 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3029 MachinePointerInfo::getFixedStack(NewFPIdx),
3036 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3037 /// the position of the argument.
3039 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3040 SDValue Arg, int SPDiff, unsigned ArgOffset,
3041 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3042 int Offset = ArgOffset + SPDiff;
3043 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3044 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3045 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3046 SDValue FIN = DAG.getFrameIndex(FI, VT);
3047 TailCallArgumentInfo Info;
3049 Info.FrameIdxOp = FIN;
3051 TailCallArguments.push_back(Info);
3054 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3055 /// stack slot. Returns the chain as result and the loaded frame pointers in
3056 /// LROpOut/FPOpout. Used when tail calling.
3057 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3065 // Load the LR and FP stack slot for later adjusting.
3066 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3067 LROpOut = getReturnAddrFrameIndex(DAG);
3068 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3069 false, false, false, 0);
3070 Chain = SDValue(LROpOut.getNode(), 1);
3072 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3073 // slot as the FP is never overwritten.
3075 FPOpOut = getFramePointerFrameIndex(DAG);
3076 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3077 false, false, false, 0);
3078 Chain = SDValue(FPOpOut.getNode(), 1);
3084 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3085 /// by "Src" to address "Dst" of size "Size". Alignment information is
3086 /// specified by the specific parameter attribute. The copy will be passed as
3087 /// a byval function parameter.
3088 /// Sometimes what we are copying is the end of a larger object, the part that
3089 /// does not fit in registers.
3091 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3092 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3094 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3095 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3096 false, false, MachinePointerInfo(0),
3097 MachinePointerInfo(0));
3100 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3103 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3104 SDValue Arg, SDValue PtrOff, int SPDiff,
3105 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3106 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3107 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3109 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3114 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3116 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3117 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3118 DAG.getConstant(ArgOffset, PtrVT));
3120 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3121 MachinePointerInfo(), false, false, 0));
3122 // Calculate and remember argument location.
3123 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3128 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3129 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3130 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3131 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3132 MachineFunction &MF = DAG.getMachineFunction();
3134 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3135 // might overwrite each other in case of tail call optimization.
3136 SmallVector<SDValue, 8> MemOpChains2;
3137 // Do not flag preceding copytoreg stuff together with the following stuff.
3139 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3141 if (!MemOpChains2.empty())
3142 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3143 &MemOpChains2[0], MemOpChains2.size());
3145 // Store the return address to the appropriate stack slot.
3146 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3147 isPPC64, isDarwinABI, dl);
3149 // Emit callseq_end just before tailcall node.
3150 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3151 DAG.getIntPtrConstant(0, true), InFlag, dl);
3152 InFlag = Chain.getValue(1);
3156 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3157 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3158 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3159 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3160 const PPCSubtarget &PPCSubTarget) {
3162 bool isPPC64 = PPCSubTarget.isPPC64();
3163 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3165 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3166 NodeTys.push_back(MVT::Other); // Returns a chain
3167 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3169 unsigned CallOpc = PPCISD::CALL;
3171 bool needIndirectCall = true;
3172 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3173 // If this is an absolute destination address, use the munged value.
3174 Callee = SDValue(Dest, 0);
3175 needIndirectCall = false;
3178 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3179 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3180 // Use indirect calls for ALL functions calls in JIT mode, since the
3181 // far-call stubs may be outside relocation limits for a BL instruction.
3182 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3183 unsigned OpFlags = 0;
3184 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3185 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3186 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3187 (G->getGlobal()->isDeclaration() ||
3188 G->getGlobal()->isWeakForLinker())) {
3189 // PC-relative references to external symbols should go through $stub,
3190 // unless we're building with the leopard linker or later, which
3191 // automatically synthesizes these stubs.
3192 OpFlags = PPCII::MO_DARWIN_STUB;
3195 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3196 // every direct call is) turn it into a TargetGlobalAddress /
3197 // TargetExternalSymbol node so that legalize doesn't hack it.
3198 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3199 Callee.getValueType(),
3201 needIndirectCall = false;
3205 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3206 unsigned char OpFlags = 0;
3208 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3209 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3210 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3211 // PC-relative references to external symbols should go through $stub,
3212 // unless we're building with the leopard linker or later, which
3213 // automatically synthesizes these stubs.
3214 OpFlags = PPCII::MO_DARWIN_STUB;
3217 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3219 needIndirectCall = false;
3222 if (needIndirectCall) {
3223 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3224 // to do the call, we can't use PPCISD::CALL.
3225 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3227 if (isSVR4ABI && isPPC64) {
3228 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3229 // entry point, but to the function descriptor (the function entry point
3230 // address is part of the function descriptor though).
3231 // The function descriptor is a three doubleword structure with the
3232 // following fields: function entry point, TOC base address and
3233 // environment pointer.
3234 // Thus for a call through a function pointer, the following actions need
3236 // 1. Save the TOC of the caller in the TOC save area of its stack
3237 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3238 // 2. Load the address of the function entry point from the function
3240 // 3. Load the TOC of the callee from the function descriptor into r2.
3241 // 4. Load the environment pointer from the function descriptor into
3243 // 5. Branch to the function entry point address.
3244 // 6. On return of the callee, the TOC of the caller needs to be
3245 // restored (this is done in FinishCall()).
3247 // All those operations are flagged together to ensure that no other
3248 // operations can be scheduled in between. E.g. without flagging the
3249 // operations together, a TOC access in the caller could be scheduled
3250 // between the load of the callee TOC and the branch to the callee, which
3251 // results in the TOC access going through the TOC of the callee instead
3252 // of going through the TOC of the caller, which leads to incorrect code.
3254 // Load the address of the function entry point from the function
3256 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3257 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
3258 InFlag.getNode() ? 3 : 2);
3259 Chain = LoadFuncPtr.getValue(1);
3260 InFlag = LoadFuncPtr.getValue(2);
3262 // Load environment pointer into r11.
3263 // Offset of the environment pointer within the function descriptor.
3264 SDValue PtrOff = DAG.getIntPtrConstant(16);
3266 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3267 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3269 Chain = LoadEnvPtr.getValue(1);
3270 InFlag = LoadEnvPtr.getValue(2);
3272 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3274 Chain = EnvVal.getValue(0);
3275 InFlag = EnvVal.getValue(1);
3277 // Load TOC of the callee into r2. We are using a target-specific load
3278 // with r2 hard coded, because the result of a target-independent load
3279 // would never go directly into r2, since r2 is a reserved register (which
3280 // prevents the register allocator from allocating it), resulting in an
3281 // additional register being allocated and an unnecessary move instruction
3283 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3284 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3286 Chain = LoadTOCPtr.getValue(0);
3287 InFlag = LoadTOCPtr.getValue(1);
3289 MTCTROps[0] = Chain;
3290 MTCTROps[1] = LoadFuncPtr;
3291 MTCTROps[2] = InFlag;
3294 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
3295 2 + (InFlag.getNode() != 0));
3296 InFlag = Chain.getValue(1);
3299 NodeTys.push_back(MVT::Other);
3300 NodeTys.push_back(MVT::Glue);
3301 Ops.push_back(Chain);
3302 CallOpc = PPCISD::BCTRL;
3304 // Add use of X11 (holding environment pointer)
3305 if (isSVR4ABI && isPPC64)
3306 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3307 // Add CTR register as callee so a bctr can be emitted later.
3309 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3312 // If this is a direct call, pass the chain and the callee.
3313 if (Callee.getNode()) {
3314 Ops.push_back(Chain);
3315 Ops.push_back(Callee);
3317 // If this is a tail call add stack pointer delta.
3319 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3321 // Add argument registers to the end of the list so that they are known live
3323 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3324 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3325 RegsToPass[i].second.getValueType()));
3331 bool isLocalCall(const SDValue &Callee)
3333 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3334 return !G->getGlobal()->isDeclaration() &&
3335 !G->getGlobal()->isWeakForLinker();
3340 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3341 CallingConv::ID CallConv, bool isVarArg,
3342 const SmallVectorImpl<ISD::InputArg> &Ins,
3343 SDLoc dl, SelectionDAG &DAG,
3344 SmallVectorImpl<SDValue> &InVals) const {
3346 SmallVector<CCValAssign, 16> RVLocs;
3347 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3348 getTargetMachine(), RVLocs, *DAG.getContext());
3349 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3351 // Copy all of the result registers out of their specified physreg.
3352 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3353 CCValAssign &VA = RVLocs[i];
3354 assert(VA.isRegLoc() && "Can only return in registers!");
3356 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3357 VA.getLocReg(), VA.getLocVT(), InFlag);
3358 Chain = Val.getValue(1);
3359 InFlag = Val.getValue(2);
3361 switch (VA.getLocInfo()) {
3362 default: llvm_unreachable("Unknown loc info!");
3363 case CCValAssign::Full: break;
3364 case CCValAssign::AExt:
3365 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3367 case CCValAssign::ZExt:
3368 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3369 DAG.getValueType(VA.getValVT()));
3370 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3372 case CCValAssign::SExt:
3373 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3374 DAG.getValueType(VA.getValVT()));
3375 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3379 InVals.push_back(Val);
3386 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3387 bool isTailCall, bool isVarArg,
3389 SmallVector<std::pair<unsigned, SDValue>, 8>
3391 SDValue InFlag, SDValue Chain,
3393 int SPDiff, unsigned NumBytes,
3394 const SmallVectorImpl<ISD::InputArg> &Ins,
3395 SmallVectorImpl<SDValue> &InVals) const {
3396 std::vector<EVT> NodeTys;
3397 SmallVector<SDValue, 8> Ops;
3398 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3399 isTailCall, RegsToPass, Ops, NodeTys,
3402 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3403 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3404 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3406 // When performing tail call optimization the callee pops its arguments off
3407 // the stack. Account for this here so these bytes can be pushed back on in
3408 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3409 int BytesCalleePops =
3410 (CallConv == CallingConv::Fast &&
3411 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3413 // Add a register mask operand representing the call-preserved registers.
3414 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3415 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3416 assert(Mask && "Missing call preserved mask for calling convention");
3417 Ops.push_back(DAG.getRegisterMask(Mask));
3419 if (InFlag.getNode())
3420 Ops.push_back(InFlag);
3424 assert(((Callee.getOpcode() == ISD::Register &&
3425 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3426 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3427 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3428 isa<ConstantSDNode>(Callee)) &&
3429 "Expecting an global address, external symbol, absolute value or register");
3431 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3434 // Add a NOP immediately after the branch instruction when using the 64-bit
3435 // SVR4 ABI. At link time, if caller and callee are in a different module and
3436 // thus have a different TOC, the call will be replaced with a call to a stub
3437 // function which saves the current TOC, loads the TOC of the callee and
3438 // branches to the callee. The NOP will be replaced with a load instruction
3439 // which restores the TOC of the caller from the TOC save slot of the current
3440 // stack frame. If caller and callee belong to the same module (and have the
3441 // same TOC), the NOP will remain unchanged.
3443 bool needsTOCRestore = false;
3444 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3445 if (CallOpc == PPCISD::BCTRL) {
3446 // This is a call through a function pointer.
3447 // Restore the caller TOC from the save area into R2.
3448 // See PrepareCall() for more information about calls through function
3449 // pointers in the 64-bit SVR4 ABI.
3450 // We are using a target-specific load with r2 hard coded, because the
3451 // result of a target-independent load would never go directly into r2,
3452 // since r2 is a reserved register (which prevents the register allocator
3453 // from allocating it), resulting in an additional register being
3454 // allocated and an unnecessary move instruction being generated.
3455 needsTOCRestore = true;
3456 } else if ((CallOpc == PPCISD::CALL) && !isLocalCall(Callee)) {
3457 // Otherwise insert NOP for non-local calls.
3458 CallOpc = PPCISD::CALL_NOP;
3462 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
3463 InFlag = Chain.getValue(1);
3465 if (needsTOCRestore) {
3466 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3467 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3468 InFlag = Chain.getValue(1);
3471 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3472 DAG.getIntPtrConstant(BytesCalleePops, true),
3475 InFlag = Chain.getValue(1);
3477 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3478 Ins, dl, DAG, InVals);
3482 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3483 SmallVectorImpl<SDValue> &InVals) const {
3484 SelectionDAG &DAG = CLI.DAG;
3486 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3487 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3488 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3489 SDValue Chain = CLI.Chain;
3490 SDValue Callee = CLI.Callee;
3491 bool &isTailCall = CLI.IsTailCall;
3492 CallingConv::ID CallConv = CLI.CallConv;
3493 bool isVarArg = CLI.IsVarArg;
3496 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3499 if (PPCSubTarget.isSVR4ABI()) {
3500 if (PPCSubTarget.isPPC64())
3501 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3502 isTailCall, Outs, OutVals, Ins,
3505 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3506 isTailCall, Outs, OutVals, Ins,
3510 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3511 isTailCall, Outs, OutVals, Ins,
3516 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3517 CallingConv::ID CallConv, bool isVarArg,
3519 const SmallVectorImpl<ISD::OutputArg> &Outs,
3520 const SmallVectorImpl<SDValue> &OutVals,
3521 const SmallVectorImpl<ISD::InputArg> &Ins,
3522 SDLoc dl, SelectionDAG &DAG,
3523 SmallVectorImpl<SDValue> &InVals) const {
3524 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3525 // of the 32-bit SVR4 ABI stack frame layout.
3527 assert((CallConv == CallingConv::C ||
3528 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3530 unsigned PtrByteSize = 4;
3532 MachineFunction &MF = DAG.getMachineFunction();
3534 // Mark this function as potentially containing a function that contains a
3535 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3536 // and restoring the callers stack pointer in this functions epilog. This is
3537 // done because by tail calling the called function might overwrite the value
3538 // in this function's (MF) stack pointer stack slot 0(SP).
3539 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3540 CallConv == CallingConv::Fast)
3541 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3543 // Count how many bytes are to be pushed on the stack, including the linkage
3544 // area, parameter list area and the part of the local variable space which
3545 // contains copies of aggregates which are passed by value.
3547 // Assign locations to all of the outgoing arguments.
3548 SmallVector<CCValAssign, 16> ArgLocs;
3549 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3550 getTargetMachine(), ArgLocs, *DAG.getContext());
3552 // Reserve space for the linkage area on the stack.
3553 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3556 // Handle fixed and variable vector arguments differently.
3557 // Fixed vector arguments go into registers as long as registers are
3558 // available. Variable vector arguments always go into memory.
3559 unsigned NumArgs = Outs.size();
3561 for (unsigned i = 0; i != NumArgs; ++i) {
3562 MVT ArgVT = Outs[i].VT;
3563 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3566 if (Outs[i].IsFixed) {
3567 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3570 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3576 errs() << "Call operand #" << i << " has unhandled type "
3577 << EVT(ArgVT).getEVTString() << "\n";
3579 llvm_unreachable(0);
3583 // All arguments are treated the same.
3584 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3587 // Assign locations to all of the outgoing aggregate by value arguments.
3588 SmallVector<CCValAssign, 16> ByValArgLocs;
3589 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3590 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3592 // Reserve stack space for the allocations in CCInfo.
3593 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3595 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3597 // Size of the linkage area, parameter list area and the part of the local
3598 // space variable where copies of aggregates which are passed by value are
3600 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3602 // Calculate by how many bytes the stack has to be adjusted in case of tail
3603 // call optimization.
3604 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3606 // Adjust the stack pointer for the new arguments...
3607 // These operations are automatically eliminated by the prolog/epilog pass
3608 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3610 SDValue CallSeqStart = Chain;
3612 // Load the return address and frame pointer so it can be moved somewhere else
3615 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3618 // Set up a copy of the stack pointer for use loading and storing any
3619 // arguments that may not fit in the registers available for argument
3621 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3623 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3624 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3625 SmallVector<SDValue, 8> MemOpChains;
3627 bool seenFloatArg = false;
3628 // Walk the register/memloc assignments, inserting copies/loads.
3629 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3632 CCValAssign &VA = ArgLocs[i];
3633 SDValue Arg = OutVals[i];
3634 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3636 if (Flags.isByVal()) {
3637 // Argument is an aggregate which is passed by value, thus we need to
3638 // create a copy of it in the local variable space of the current stack
3639 // frame (which is the stack frame of the caller) and pass the address of
3640 // this copy to the callee.
3641 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3642 CCValAssign &ByValVA = ByValArgLocs[j++];
3643 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3645 // Memory reserved in the local variable space of the callers stack frame.
3646 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3648 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3649 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3651 // Create a copy of the argument in the local area of the current
3653 SDValue MemcpyCall =
3654 CreateCopyOfByValArgument(Arg, PtrOff,
3655 CallSeqStart.getNode()->getOperand(0),
3658 // This must go outside the CALLSEQ_START..END.
3659 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3660 CallSeqStart.getNode()->getOperand(1),
3662 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3663 NewCallSeqStart.getNode());
3664 Chain = CallSeqStart = NewCallSeqStart;
3666 // Pass the address of the aggregate copy on the stack either in a
3667 // physical register or in the parameter list area of the current stack
3668 // frame to the callee.
3672 if (VA.isRegLoc()) {
3673 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3674 // Put argument in a physical register.
3675 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3677 // Put argument in the parameter list area of the current stack frame.
3678 assert(VA.isMemLoc());
3679 unsigned LocMemOffset = VA.getLocMemOffset();
3682 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3683 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3685 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3686 MachinePointerInfo(),
3689 // Calculate and remember argument location.
3690 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3696 if (!MemOpChains.empty())
3697 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3698 &MemOpChains[0], MemOpChains.size());
3700 // Build a sequence of copy-to-reg nodes chained together with token chain
3701 // and flag operands which copy the outgoing args into the appropriate regs.
3703 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3704 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3705 RegsToPass[i].second, InFlag);
3706 InFlag = Chain.getValue(1);
3709 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3712 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3713 SDValue Ops[] = { Chain, InFlag };
3715 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3716 dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
3718 InFlag = Chain.getValue(1);
3722 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3723 false, TailCallArguments);
3725 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3726 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3730 // Copy an argument into memory, being careful to do this outside the
3731 // call sequence for the call to which the argument belongs.
3733 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3734 SDValue CallSeqStart,
3735 ISD::ArgFlagsTy Flags,
3738 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3739 CallSeqStart.getNode()->getOperand(0),
3741 // The MEMCPY must go outside the CALLSEQ_START..END.
3742 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3743 CallSeqStart.getNode()->getOperand(1),
3745 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3746 NewCallSeqStart.getNode());
3747 return NewCallSeqStart;
3751 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3752 CallingConv::ID CallConv, bool isVarArg,
3754 const SmallVectorImpl<ISD::OutputArg> &Outs,
3755 const SmallVectorImpl<SDValue> &OutVals,
3756 const SmallVectorImpl<ISD::InputArg> &Ins,
3757 SDLoc dl, SelectionDAG &DAG,
3758 SmallVectorImpl<SDValue> &InVals) const {
3760 unsigned NumOps = Outs.size();
3762 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3763 unsigned PtrByteSize = 8;
3765 MachineFunction &MF = DAG.getMachineFunction();
3767 // Mark this function as potentially containing a function that contains a
3768 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3769 // and restoring the callers stack pointer in this functions epilog. This is
3770 // done because by tail calling the called function might overwrite the value
3771 // in this function's (MF) stack pointer stack slot 0(SP).
3772 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3773 CallConv == CallingConv::Fast)
3774 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3776 unsigned nAltivecParamsAtEnd = 0;
3778 // Count how many bytes are to be pushed on the stack, including the linkage
3779 // area, and parameter passing area. We start with at least 48 bytes, which
3780 // is reserved space for [SP][CR][LR][3 x unused].
3781 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
3784 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
3785 Outs, OutVals, nAltivecParamsAtEnd);
3787 // Calculate by how many bytes the stack has to be adjusted in case of tail
3788 // call optimization.
3789 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3791 // To protect arguments on the stack from being clobbered in a tail call,
3792 // force all the loads to happen before doing any other lowering.
3794 Chain = DAG.getStackArgumentTokenFactor(Chain);
3796 // Adjust the stack pointer for the new arguments...
3797 // These operations are automatically eliminated by the prolog/epilog pass
3798 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3800 SDValue CallSeqStart = Chain;
3802 // Load the return address and frame pointer so it can be move somewhere else
3805 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3808 // Set up a copy of the stack pointer for use loading and storing any
3809 // arguments that may not fit in the registers available for argument
3811 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3813 // Figure out which arguments are going to go in registers, and which in
3814 // memory. Also, if this is a vararg function, floating point operations
3815 // must be stored to our stack, and loaded into integer regs as well, if
3816 // any integer regs are available for argument passing.
3817 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
3818 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3820 static const uint16_t GPR[] = {
3821 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3822 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3824 static const uint16_t *FPR = GetFPR();
3826 static const uint16_t VR[] = {
3827 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3828 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3830 const unsigned NumGPRs = array_lengthof(GPR);
3831 const unsigned NumFPRs = 13;
3832 const unsigned NumVRs = array_lengthof(VR);
3834 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3835 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3837 SmallVector<SDValue, 8> MemOpChains;
3838 for (unsigned i = 0; i != NumOps; ++i) {
3839 SDValue Arg = OutVals[i];
3840 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3842 // PtrOff will be used to store the current argument to the stack if a
3843 // register cannot be found for it.
3846 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3848 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3850 // Promote integers to 64-bit values.
3851 if (Arg.getValueType() == MVT::i32) {
3852 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3853 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3854 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3857 // FIXME memcpy is used way more than necessary. Correctness first.
3858 // Note: "by value" is code for passing a structure by value, not
3860 if (Flags.isByVal()) {
3861 // Note: Size includes alignment padding, so
3862 // struct x { short a; char b; }
3863 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
3864 // These are the proper values we need for right-justifying the
3865 // aggregate in a parameter register.
3866 unsigned Size = Flags.getByValSize();
3868 // An empty aggregate parameter takes up no storage and no
3873 // All aggregates smaller than 8 bytes must be passed right-justified.
3874 if (Size==1 || Size==2 || Size==4) {
3875 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
3876 if (GPR_idx != NumGPRs) {
3877 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3878 MachinePointerInfo(), VT,
3880 MemOpChains.push_back(Load.getValue(1));
3881 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3883 ArgOffset += PtrByteSize;
3888 if (GPR_idx == NumGPRs && Size < 8) {
3889 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3890 PtrOff.getValueType());
3891 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3892 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3895 ArgOffset += PtrByteSize;
3898 // Copy entire object into memory. There are cases where gcc-generated
3899 // code assumes it is there, even if it could be put entirely into
3900 // registers. (This is not what the doc says.)
3902 // FIXME: The above statement is likely due to a misunderstanding of the
3903 // documents. All arguments must be copied into the parameter area BY
3904 // THE CALLEE in the event that the callee takes the address of any
3905 // formal argument. That has not yet been implemented. However, it is
3906 // reasonable to use the stack area as a staging area for the register
3909 // Skip this for small aggregates, as we will use the same slot for a
3910 // right-justified copy, below.
3912 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
3916 // When a register is available, pass a small aggregate right-justified.
3917 if (Size < 8 && GPR_idx != NumGPRs) {
3918 // The easiest way to get this right-justified in a register
3919 // is to copy the structure into the rightmost portion of a
3920 // local variable slot, then load the whole slot into the
3922 // FIXME: The memcpy seems to produce pretty awful code for
3923 // small aggregates, particularly for packed ones.
3924 // FIXME: It would be preferable to use the slot in the
3925 // parameter save area instead of a new local variable.
3926 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
3927 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3928 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3932 // Load the slot into the register.
3933 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
3934 MachinePointerInfo(),
3935 false, false, false, 0);
3936 MemOpChains.push_back(Load.getValue(1));
3937 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3939 // Done with this argument.
3940 ArgOffset += PtrByteSize;
3944 // For aggregates larger than PtrByteSize, copy the pieces of the
3945 // object that fit into registers from the parameter save area.
3946 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3947 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3948 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3949 if (GPR_idx != NumGPRs) {
3950 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3951 MachinePointerInfo(),
3952 false, false, false, 0);
3953 MemOpChains.push_back(Load.getValue(1));
3954 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3955 ArgOffset += PtrByteSize;
3957 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3964 switch (Arg.getSimpleValueType().SimpleTy) {
3965 default: llvm_unreachable("Unexpected ValueType for argument!");
3968 if (GPR_idx != NumGPRs) {
3969 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3971 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3972 true, isTailCall, false, MemOpChains,
3973 TailCallArguments, dl);
3975 ArgOffset += PtrByteSize;
3979 if (FPR_idx != NumFPRs) {
3980 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3983 // A single float or an aggregate containing only a single float
3984 // must be passed right-justified in the stack doubleword, and
3985 // in the GPR, if one is available.
3987 if (Arg.getSimpleValueType().SimpleTy == MVT::f32) {
3988 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3989 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3993 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
3994 MachinePointerInfo(), false, false, 0);
3995 MemOpChains.push_back(Store);
3997 // Float varargs are always shadowed in available integer registers
3998 if (GPR_idx != NumGPRs) {
3999 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4000 MachinePointerInfo(), false, false,
4002 MemOpChains.push_back(Load.getValue(1));
4003 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4005 } else if (GPR_idx != NumGPRs)
4006 // If we have any FPRs remaining, we may also have GPRs remaining.
4009 // Single-precision floating-point values are mapped to the
4010 // second (rightmost) word of the stack doubleword.
4011 if (Arg.getValueType() == MVT::f32) {
4012 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4013 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4016 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4017 true, isTailCall, false, MemOpChains,
4018 TailCallArguments, dl);
4027 // These go aligned on the stack, or in the corresponding R registers
4028 // when within range. The Darwin PPC ABI doc claims they also go in
4029 // V registers; in fact gcc does this only for arguments that are
4030 // prototyped, not for those that match the ... We do it for all
4031 // arguments, seems to work.
4032 while (ArgOffset % 16 !=0) {
4033 ArgOffset += PtrByteSize;
4034 if (GPR_idx != NumGPRs)
4037 // We could elide this store in the case where the object fits
4038 // entirely in R registers. Maybe later.
4039 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4040 DAG.getConstant(ArgOffset, PtrVT));
4041 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4042 MachinePointerInfo(), false, false, 0);
4043 MemOpChains.push_back(Store);
4044 if (VR_idx != NumVRs) {
4045 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4046 MachinePointerInfo(),
4047 false, false, false, 0);
4048 MemOpChains.push_back(Load.getValue(1));
4049 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4052 for (unsigned i=0; i<16; i+=PtrByteSize) {
4053 if (GPR_idx == NumGPRs)
4055 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4056 DAG.getConstant(i, PtrVT));
4057 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4058 false, false, false, 0);
4059 MemOpChains.push_back(Load.getValue(1));
4060 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4065 // Non-varargs Altivec params generally go in registers, but have
4066 // stack space allocated at the end.
4067 if (VR_idx != NumVRs) {
4068 // Doesn't have GPR space allocated.
4069 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4071 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4072 true, isTailCall, true, MemOpChains,
4073 TailCallArguments, dl);
4080 if (!MemOpChains.empty())
4081 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4082 &MemOpChains[0], MemOpChains.size());
4084 // Check if this is an indirect call (MTCTR/BCTRL).
4085 // See PrepareCall() for more information about calls through function
4086 // pointers in the 64-bit SVR4 ABI.
4088 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4089 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4090 !isBLACompatibleAddress(Callee, DAG)) {
4091 // Load r2 into a virtual register and store it to the TOC save area.
4092 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4093 // TOC save area offset.
4094 SDValue PtrOff = DAG.getIntPtrConstant(40);
4095 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4096 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4098 // R12 must contain the address of an indirect callee. This does not
4099 // mean the MTCTR instruction must use R12; it's easier to model this
4100 // as an extra parameter, so do that.
4101 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4104 // Build a sequence of copy-to-reg nodes chained together with token chain
4105 // and flag operands which copy the outgoing args into the appropriate regs.
4107 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4108 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4109 RegsToPass[i].second, InFlag);
4110 InFlag = Chain.getValue(1);
4114 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4115 FPOp, true, TailCallArguments);
4117 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4118 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4123 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4124 CallingConv::ID CallConv, bool isVarArg,
4126 const SmallVectorImpl<ISD::OutputArg> &Outs,
4127 const SmallVectorImpl<SDValue> &OutVals,
4128 const SmallVectorImpl<ISD::InputArg> &Ins,
4129 SDLoc dl, SelectionDAG &DAG,
4130 SmallVectorImpl<SDValue> &InVals) const {
4132 unsigned NumOps = Outs.size();
4134 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4135 bool isPPC64 = PtrVT == MVT::i64;
4136 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4138 MachineFunction &MF = DAG.getMachineFunction();
4140 // Mark this function as potentially containing a function that contains a
4141 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4142 // and restoring the callers stack pointer in this functions epilog. This is
4143 // done because by tail calling the called function might overwrite the value
4144 // in this function's (MF) stack pointer stack slot 0(SP).
4145 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4146 CallConv == CallingConv::Fast)
4147 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4149 unsigned nAltivecParamsAtEnd = 0;
4151 // Count how many bytes are to be pushed on the stack, including the linkage
4152 // area, and parameter passing area. We start with 24/48 bytes, which is
4153 // prereserved space for [SP][CR][LR][3 x unused].
4155 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4157 nAltivecParamsAtEnd);
4159 // Calculate by how many bytes the stack has to be adjusted in case of tail
4160 // call optimization.
4161 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4163 // To protect arguments on the stack from being clobbered in a tail call,
4164 // force all the loads to happen before doing any other lowering.
4166 Chain = DAG.getStackArgumentTokenFactor(Chain);
4168 // Adjust the stack pointer for the new arguments...
4169 // These operations are automatically eliminated by the prolog/epilog pass
4170 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4172 SDValue CallSeqStart = Chain;
4174 // Load the return address and frame pointer so it can be move somewhere else
4177 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4180 // Set up a copy of the stack pointer for use loading and storing any
4181 // arguments that may not fit in the registers available for argument
4185 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4187 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4189 // Figure out which arguments are going to go in registers, and which in
4190 // memory. Also, if this is a vararg function, floating point operations
4191 // must be stored to our stack, and loaded into integer regs as well, if
4192 // any integer regs are available for argument passing.
4193 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4194 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4196 static const uint16_t GPR_32[] = { // 32-bit registers.
4197 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4198 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4200 static const uint16_t GPR_64[] = { // 64-bit registers.
4201 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4202 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4204 static const uint16_t *FPR = GetFPR();
4206 static const uint16_t VR[] = {
4207 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4208 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4210 const unsigned NumGPRs = array_lengthof(GPR_32);
4211 const unsigned NumFPRs = 13;
4212 const unsigned NumVRs = array_lengthof(VR);
4214 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4216 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4217 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4219 SmallVector<SDValue, 8> MemOpChains;
4220 for (unsigned i = 0; i != NumOps; ++i) {
4221 SDValue Arg = OutVals[i];
4222 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4224 // PtrOff will be used to store the current argument to the stack if a
4225 // register cannot be found for it.
4228 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4230 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4232 // On PPC64, promote integers to 64-bit values.
4233 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4234 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4235 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4236 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4239 // FIXME memcpy is used way more than necessary. Correctness first.
4240 // Note: "by value" is code for passing a structure by value, not
4242 if (Flags.isByVal()) {
4243 unsigned Size = Flags.getByValSize();
4244 // Very small objects are passed right-justified. Everything else is
4245 // passed left-justified.
4246 if (Size==1 || Size==2) {
4247 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4248 if (GPR_idx != NumGPRs) {
4249 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4250 MachinePointerInfo(), VT,
4252 MemOpChains.push_back(Load.getValue(1));
4253 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4255 ArgOffset += PtrByteSize;
4257 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4258 PtrOff.getValueType());
4259 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4260 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4263 ArgOffset += PtrByteSize;
4267 // Copy entire object into memory. There are cases where gcc-generated
4268 // code assumes it is there, even if it could be put entirely into
4269 // registers. (This is not what the doc says.)
4270 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4274 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4275 // copy the pieces of the object that fit into registers from the
4276 // parameter save area.
4277 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4278 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4279 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4280 if (GPR_idx != NumGPRs) {
4281 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4282 MachinePointerInfo(),
4283 false, false, false, 0);
4284 MemOpChains.push_back(Load.getValue(1));
4285 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4286 ArgOffset += PtrByteSize;
4288 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4295 switch (Arg.getSimpleValueType().SimpleTy) {
4296 default: llvm_unreachable("Unexpected ValueType for argument!");
4299 if (GPR_idx != NumGPRs) {
4300 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4302 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4303 isPPC64, isTailCall, false, MemOpChains,
4304 TailCallArguments, dl);
4306 ArgOffset += PtrByteSize;
4310 if (FPR_idx != NumFPRs) {
4311 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4314 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4315 MachinePointerInfo(), false, false, 0);
4316 MemOpChains.push_back(Store);
4318 // Float varargs are always shadowed in available integer registers
4319 if (GPR_idx != NumGPRs) {
4320 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4321 MachinePointerInfo(), false, false,
4323 MemOpChains.push_back(Load.getValue(1));
4324 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4326 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4327 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4328 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4329 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4330 MachinePointerInfo(),
4331 false, false, false, 0);
4332 MemOpChains.push_back(Load.getValue(1));
4333 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4336 // If we have any FPRs remaining, we may also have GPRs remaining.
4337 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4339 if (GPR_idx != NumGPRs)
4341 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4342 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4346 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4347 isPPC64, isTailCall, false, MemOpChains,
4348 TailCallArguments, dl);
4352 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4359 // These go aligned on the stack, or in the corresponding R registers
4360 // when within range. The Darwin PPC ABI doc claims they also go in
4361 // V registers; in fact gcc does this only for arguments that are
4362 // prototyped, not for those that match the ... We do it for all
4363 // arguments, seems to work.
4364 while (ArgOffset % 16 !=0) {
4365 ArgOffset += PtrByteSize;
4366 if (GPR_idx != NumGPRs)
4369 // We could elide this store in the case where the object fits
4370 // entirely in R registers. Maybe later.
4371 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4372 DAG.getConstant(ArgOffset, PtrVT));
4373 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4374 MachinePointerInfo(), false, false, 0);
4375 MemOpChains.push_back(Store);
4376 if (VR_idx != NumVRs) {
4377 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4378 MachinePointerInfo(),
4379 false, false, false, 0);
4380 MemOpChains.push_back(Load.getValue(1));
4381 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4384 for (unsigned i=0; i<16; i+=PtrByteSize) {
4385 if (GPR_idx == NumGPRs)
4387 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4388 DAG.getConstant(i, PtrVT));
4389 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4390 false, false, false, 0);
4391 MemOpChains.push_back(Load.getValue(1));
4392 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4397 // Non-varargs Altivec params generally go in registers, but have
4398 // stack space allocated at the end.
4399 if (VR_idx != NumVRs) {
4400 // Doesn't have GPR space allocated.
4401 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4402 } else if (nAltivecParamsAtEnd==0) {
4403 // We are emitting Altivec params in order.
4404 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4405 isPPC64, isTailCall, true, MemOpChains,
4406 TailCallArguments, dl);
4412 // If all Altivec parameters fit in registers, as they usually do,
4413 // they get stack space following the non-Altivec parameters. We
4414 // don't track this here because nobody below needs it.
4415 // If there are more Altivec parameters than fit in registers emit
4417 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4419 // Offset is aligned; skip 1st 12 params which go in V registers.
4420 ArgOffset = ((ArgOffset+15)/16)*16;
4422 for (unsigned i = 0; i != NumOps; ++i) {
4423 SDValue Arg = OutVals[i];
4424 EVT ArgType = Outs[i].VT;
4425 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4426 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4429 // We are emitting Altivec params in order.
4430 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4431 isPPC64, isTailCall, true, MemOpChains,
4432 TailCallArguments, dl);
4439 if (!MemOpChains.empty())
4440 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4441 &MemOpChains[0], MemOpChains.size());
4443 // On Darwin, R12 must contain the address of an indirect callee. This does
4444 // not mean the MTCTR instruction must use R12; it's easier to model this as
4445 // an extra parameter, so do that.
4447 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4448 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4449 !isBLACompatibleAddress(Callee, DAG))
4450 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4451 PPC::R12), Callee));
4453 // Build a sequence of copy-to-reg nodes chained together with token chain
4454 // and flag operands which copy the outgoing args into the appropriate regs.
4456 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4457 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4458 RegsToPass[i].second, InFlag);
4459 InFlag = Chain.getValue(1);
4463 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4464 FPOp, true, TailCallArguments);
4466 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4467 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4472 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4473 MachineFunction &MF, bool isVarArg,
4474 const SmallVectorImpl<ISD::OutputArg> &Outs,
4475 LLVMContext &Context) const {
4476 SmallVector<CCValAssign, 16> RVLocs;
4477 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4479 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4483 PPCTargetLowering::LowerReturn(SDValue Chain,
4484 CallingConv::ID CallConv, bool isVarArg,
4485 const SmallVectorImpl<ISD::OutputArg> &Outs,
4486 const SmallVectorImpl<SDValue> &OutVals,
4487 SDLoc dl, SelectionDAG &DAG) const {
4489 SmallVector<CCValAssign, 16> RVLocs;
4490 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4491 getTargetMachine(), RVLocs, *DAG.getContext());
4492 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4495 SmallVector<SDValue, 4> RetOps(1, Chain);
4497 // Copy the result values into the output registers.
4498 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4499 CCValAssign &VA = RVLocs[i];
4500 assert(VA.isRegLoc() && "Can only return in registers!");
4502 SDValue Arg = OutVals[i];
4504 switch (VA.getLocInfo()) {
4505 default: llvm_unreachable("Unknown loc info!");
4506 case CCValAssign::Full: break;
4507 case CCValAssign::AExt:
4508 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4510 case CCValAssign::ZExt:
4511 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4513 case CCValAssign::SExt:
4514 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4518 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4519 Flag = Chain.getValue(1);
4520 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4523 RetOps[0] = Chain; // Update chain.
4525 // Add the flag if we have it.
4527 RetOps.push_back(Flag);
4529 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4530 &RetOps[0], RetOps.size());
4533 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4534 const PPCSubtarget &Subtarget) const {
4535 // When we pop the dynamic allocation we need to restore the SP link.
4538 // Get the corect type for pointers.
4539 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4541 // Construct the stack pointer operand.
4542 bool isPPC64 = Subtarget.isPPC64();
4543 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4544 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4546 // Get the operands for the STACKRESTORE.
4547 SDValue Chain = Op.getOperand(0);
4548 SDValue SaveSP = Op.getOperand(1);
4550 // Load the old link SP.
4551 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4552 MachinePointerInfo(),
4553 false, false, false, 0);
4555 // Restore the stack pointer.
4556 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4558 // Store the old link SP.
4559 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4566 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4567 MachineFunction &MF = DAG.getMachineFunction();
4568 bool isPPC64 = PPCSubTarget.isPPC64();
4569 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4570 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4572 // Get current frame pointer save index. The users of this index will be
4573 // primarily DYNALLOC instructions.
4574 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4575 int RASI = FI->getReturnAddrSaveIndex();
4577 // If the frame pointer save index hasn't been defined yet.
4579 // Find out what the fix offset of the frame pointer save area.
4580 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4581 // Allocate the frame index for frame pointer save area.
4582 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4584 FI->setReturnAddrSaveIndex(RASI);
4586 return DAG.getFrameIndex(RASI, PtrVT);
4590 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4591 MachineFunction &MF = DAG.getMachineFunction();
4592 bool isPPC64 = PPCSubTarget.isPPC64();
4593 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4594 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4596 // Get current frame pointer save index. The users of this index will be
4597 // primarily DYNALLOC instructions.
4598 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4599 int FPSI = FI->getFramePointerSaveIndex();
4601 // If the frame pointer save index hasn't been defined yet.
4603 // Find out what the fix offset of the frame pointer save area.
4604 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4607 // Allocate the frame index for frame pointer save area.
4608 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4610 FI->setFramePointerSaveIndex(FPSI);
4612 return DAG.getFrameIndex(FPSI, PtrVT);
4615 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4617 const PPCSubtarget &Subtarget) const {
4619 SDValue Chain = Op.getOperand(0);
4620 SDValue Size = Op.getOperand(1);
4623 // Get the corect type for pointers.
4624 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4626 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4627 DAG.getConstant(0, PtrVT), Size);
4628 // Construct a node for the frame pointer save index.
4629 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4630 // Build a DYNALLOC node.
4631 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4632 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4633 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
4636 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4637 SelectionDAG &DAG) const {
4639 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4640 DAG.getVTList(MVT::i32, MVT::Other),
4641 Op.getOperand(0), Op.getOperand(1));
4644 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4645 SelectionDAG &DAG) const {
4647 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4648 Op.getOperand(0), Op.getOperand(1));
4651 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4653 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4654 // Not FP? Not a fsel.
4655 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4656 !Op.getOperand(2).getValueType().isFloatingPoint())
4659 // We might be able to do better than this under some circumstances, but in
4660 // general, fsel-based lowering of select is a finite-math-only optimization.
4661 // For more information, see section F.3 of the 2.06 ISA specification.
4662 if (!DAG.getTarget().Options.NoInfsFPMath ||
4663 !DAG.getTarget().Options.NoNaNsFPMath)
4666 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4668 EVT ResVT = Op.getValueType();
4669 EVT CmpVT = Op.getOperand(0).getValueType();
4670 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4671 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4674 // If the RHS of the comparison is a 0.0, we don't need to do the
4675 // subtraction at all.
4677 if (isFloatingPointZero(RHS))
4679 default: break; // SETUO etc aren't handled by fsel.
4683 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4684 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4685 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4686 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4687 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4688 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4689 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
4692 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4695 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4696 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4697 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4700 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4703 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4704 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4705 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4706 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4711 default: break; // SETUO etc aren't handled by fsel.
4715 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4716 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4717 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4718 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4719 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4720 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4721 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4722 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
4725 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4726 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4727 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4728 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4731 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4732 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4733 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4734 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4737 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4738 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4739 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4740 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4743 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4744 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4745 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4746 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4751 // FIXME: Split this code up when LegalizeDAGTypes lands.
4752 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
4754 assert(Op.getOperand(0).getValueType().isFloatingPoint());
4755 SDValue Src = Op.getOperand(0);
4756 if (Src.getValueType() == MVT::f32)
4757 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4760 switch (Op.getSimpleValueType().SimpleTy) {
4761 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
4763 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4764 (PPCSubTarget.hasFPCVT() ? PPCISD::FCTIWUZ :
4769 assert((Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT()) &&
4770 "i64 FP_TO_UINT is supported only with FPCVT");
4771 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
4777 // Convert the FP value to an int value through memory.
4778 bool i32Stack = Op.getValueType() == MVT::i32 && PPCSubTarget.hasSTFIWX() &&
4779 (Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT());
4780 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
4781 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
4782 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
4784 // Emit a store to the stack slot.
4787 MachineFunction &MF = DAG.getMachineFunction();
4788 MachineMemOperand *MMO =
4789 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
4790 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
4791 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
4792 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
4795 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
4796 MPI, false, false, 0);
4798 // Result is a load from the stack slot. If loading 4 bytes, make sure to
4800 if (Op.getValueType() == MVT::i32 && !i32Stack) {
4801 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
4802 DAG.getConstant(4, FIPtr.getValueType()));
4803 MPI = MachinePointerInfo();
4806 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
4807 false, false, false, 0);
4810 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
4811 SelectionDAG &DAG) const {
4813 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
4814 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4817 assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) &&
4818 "UINT_TO_FP is supported only with FPCVT");
4820 // If we have FCFIDS, then use it when converting to single-precision.
4821 // Otherwise, convert to double-precision and then round.
4822 unsigned FCFOp = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4823 (Op.getOpcode() == ISD::UINT_TO_FP ?
4824 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
4825 (Op.getOpcode() == ISD::UINT_TO_FP ?
4826 PPCISD::FCFIDU : PPCISD::FCFID);
4827 MVT FCFTy = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4828 MVT::f32 : MVT::f64;
4830 if (Op.getOperand(0).getValueType() == MVT::i64) {
4831 SDValue SINT = Op.getOperand(0);
4832 // When converting to single-precision, we actually need to convert
4833 // to double-precision first and then round to single-precision.
4834 // To avoid double-rounding effects during that operation, we have
4835 // to prepare the input operand. Bits that might be truncated when
4836 // converting to double-precision are replaced by a bit that won't
4837 // be lost at this stage, but is below the single-precision rounding
4840 // However, if -enable-unsafe-fp-math is in effect, accept double
4841 // rounding to avoid the extra overhead.
4842 if (Op.getValueType() == MVT::f32 &&
4843 !PPCSubTarget.hasFPCVT() &&
4844 !DAG.getTarget().Options.UnsafeFPMath) {
4846 // Twiddle input to make sure the low 11 bits are zero. (If this
4847 // is the case, we are guaranteed the value will fit into the 53 bit
4848 // mantissa of an IEEE double-precision value without rounding.)
4849 // If any of those low 11 bits were not zero originally, make sure
4850 // bit 12 (value 2048) is set instead, so that the final rounding
4851 // to single-precision gets the correct result.
4852 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4853 SINT, DAG.getConstant(2047, MVT::i64));
4854 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4855 Round, DAG.getConstant(2047, MVT::i64));
4856 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4857 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4858 Round, DAG.getConstant(-2048, MVT::i64));
4860 // However, we cannot use that value unconditionally: if the magnitude
4861 // of the input value is small, the bit-twiddling we did above might
4862 // end up visibly changing the output. Fortunately, in that case, we
4863 // don't need to twiddle bits since the original input will convert
4864 // exactly to double-precision floating-point already. Therefore,
4865 // construct a conditional to use the original value if the top 11
4866 // bits are all sign-bit copies, and use the rounded value computed
4868 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4869 SINT, DAG.getConstant(53, MVT::i32));
4870 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4871 Cond, DAG.getConstant(1, MVT::i64));
4872 Cond = DAG.getSetCC(dl, MVT::i32,
4873 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4875 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4878 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4879 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
4881 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4882 FP = DAG.getNode(ISD::FP_ROUND, dl,
4883 MVT::f32, FP, DAG.getIntPtrConstant(0));
4887 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
4888 "Unhandled INT_TO_FP type in custom expander!");
4889 // Since we only generate this in 64-bit mode, we can take advantage of
4890 // 64-bit registers. In particular, sign extend the input value into the
4891 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
4892 // then lfd it and fcfid it.
4893 MachineFunction &MF = DAG.getMachineFunction();
4894 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
4895 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4898 if (PPCSubTarget.hasLFIWAX() || PPCSubTarget.hasFPCVT()) {
4899 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
4900 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4902 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
4903 MachinePointerInfo::getFixedStack(FrameIdx),
4906 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
4907 "Expected an i32 store");
4908 MachineMemOperand *MMO =
4909 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
4910 MachineMemOperand::MOLoad, 4, 4);
4911 SDValue Ops[] = { Store, FIdx };
4912 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
4913 PPCISD::LFIWZX : PPCISD::LFIWAX,
4914 dl, DAG.getVTList(MVT::f64, MVT::Other),
4915 Ops, 2, MVT::i32, MMO);
4917 assert(PPCSubTarget.isPPC64() &&
4918 "i32->FP without LFIWAX supported only on PPC64");
4920 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
4921 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4923 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
4926 // STD the extended value into the stack slot.
4927 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
4928 MachinePointerInfo::getFixedStack(FrameIdx),
4931 // Load the value as a double.
4932 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
4933 MachinePointerInfo::getFixedStack(FrameIdx),
4934 false, false, false, 0);
4937 // FCFID it and return it.
4938 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
4939 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4940 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
4944 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4945 SelectionDAG &DAG) const {
4948 The rounding mode is in bits 30:31 of FPSR, and has the following
4955 FLT_ROUNDS, on the other hand, expects the following:
4962 To perform the conversion, we do:
4963 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
4966 MachineFunction &MF = DAG.getMachineFunction();
4967 EVT VT = Op.getValueType();
4968 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4969 SDValue MFFSreg, InFlag;
4971 // Save FP Control Word to register
4973 MVT::f64, // return register
4974 MVT::Glue // unused in this context
4976 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4978 // Save FP register to stack slot
4979 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
4980 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
4981 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
4982 StackSlot, MachinePointerInfo(), false, false,0);
4984 // Load FP Control Word from low 32 bits of stack slot.
4985 SDValue Four = DAG.getConstant(4, PtrVT);
4986 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
4987 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
4988 false, false, false, 0);
4990 // Transform as necessary
4992 DAG.getNode(ISD::AND, dl, MVT::i32,
4993 CWD, DAG.getConstant(3, MVT::i32));
4995 DAG.getNode(ISD::SRL, dl, MVT::i32,
4996 DAG.getNode(ISD::AND, dl, MVT::i32,
4997 DAG.getNode(ISD::XOR, dl, MVT::i32,
4998 CWD, DAG.getConstant(3, MVT::i32)),
4999 DAG.getConstant(3, MVT::i32)),
5000 DAG.getConstant(1, MVT::i32));
5003 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5005 return DAG.getNode((VT.getSizeInBits() < 16 ?
5006 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5009 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5010 EVT VT = Op.getValueType();
5011 unsigned BitWidth = VT.getSizeInBits();
5013 assert(Op.getNumOperands() == 3 &&
5014 VT == Op.getOperand(1).getValueType() &&
5017 // Expand into a bunch of logical ops. Note that these ops
5018 // depend on the PPC behavior for oversized shift amounts.
5019 SDValue Lo = Op.getOperand(0);
5020 SDValue Hi = Op.getOperand(1);
5021 SDValue Amt = Op.getOperand(2);
5022 EVT AmtVT = Amt.getValueType();
5024 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5025 DAG.getConstant(BitWidth, AmtVT), Amt);
5026 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5027 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5028 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5029 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5030 DAG.getConstant(-BitWidth, AmtVT));
5031 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5032 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5033 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5034 SDValue OutOps[] = { OutLo, OutHi };
5035 return DAG.getMergeValues(OutOps, 2, dl);
5038 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5039 EVT VT = Op.getValueType();
5041 unsigned BitWidth = VT.getSizeInBits();
5042 assert(Op.getNumOperands() == 3 &&
5043 VT == Op.getOperand(1).getValueType() &&
5046 // Expand into a bunch of logical ops. Note that these ops
5047 // depend on the PPC behavior for oversized shift amounts.
5048 SDValue Lo = Op.getOperand(0);
5049 SDValue Hi = Op.getOperand(1);
5050 SDValue Amt = Op.getOperand(2);
5051 EVT AmtVT = Amt.getValueType();
5053 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5054 DAG.getConstant(BitWidth, AmtVT), Amt);
5055 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5056 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5057 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5058 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5059 DAG.getConstant(-BitWidth, AmtVT));
5060 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5061 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5062 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5063 SDValue OutOps[] = { OutLo, OutHi };
5064 return DAG.getMergeValues(OutOps, 2, dl);
5067 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5069 EVT VT = Op.getValueType();
5070 unsigned BitWidth = VT.getSizeInBits();
5071 assert(Op.getNumOperands() == 3 &&
5072 VT == Op.getOperand(1).getValueType() &&
5075 // Expand into a bunch of logical ops, followed by a select_cc.
5076 SDValue Lo = Op.getOperand(0);
5077 SDValue Hi = Op.getOperand(1);
5078 SDValue Amt = Op.getOperand(2);
5079 EVT AmtVT = Amt.getValueType();
5081 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5082 DAG.getConstant(BitWidth, AmtVT), Amt);
5083 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5084 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5085 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5086 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5087 DAG.getConstant(-BitWidth, AmtVT));
5088 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5089 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5090 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5091 Tmp4, Tmp6, ISD::SETLE);
5092 SDValue OutOps[] = { OutLo, OutHi };
5093 return DAG.getMergeValues(OutOps, 2, dl);
5096 //===----------------------------------------------------------------------===//
5097 // Vector related lowering.
5100 /// BuildSplatI - Build a canonical splati of Val with an element size of
5101 /// SplatSize. Cast the result to VT.
5102 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5103 SelectionDAG &DAG, SDLoc dl) {
5104 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5106 static const EVT VTys[] = { // canonical VT to use for each size.
5107 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5110 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5112 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5116 EVT CanonicalVT = VTys[SplatSize-1];
5118 // Build a canonical splat for this value.
5119 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5120 SmallVector<SDValue, 8> Ops;
5121 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5122 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
5123 &Ops[0], Ops.size());
5124 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5127 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5128 /// specified intrinsic ID.
5129 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5130 SelectionDAG &DAG, SDLoc dl,
5131 EVT DestVT = MVT::Other) {
5132 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5133 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5134 DAG.getConstant(IID, MVT::i32), Op);
5137 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5138 /// specified intrinsic ID.
5139 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5140 SelectionDAG &DAG, SDLoc dl,
5141 EVT DestVT = MVT::Other) {
5142 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5143 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5144 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5147 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5148 /// specified intrinsic ID.
5149 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5150 SDValue Op2, SelectionDAG &DAG,
5151 SDLoc dl, EVT DestVT = MVT::Other) {
5152 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5153 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5154 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5158 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5159 /// amount. The result has the specified value type.
5160 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5161 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5162 // Force LHS/RHS to be the right type.
5163 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5164 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5167 for (unsigned i = 0; i != 16; ++i)
5169 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5170 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5173 // If this is a case we can't handle, return null and let the default
5174 // expansion code take care of it. If we CAN select this case, and if it
5175 // selects to a single instruction, return Op. Otherwise, if we can codegen
5176 // this case more efficiently than a constant pool load, lower it to the
5177 // sequence of ops that should be used.
5178 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5179 SelectionDAG &DAG) const {
5181 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5182 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5184 // Check if this is a splat of a constant value.
5185 APInt APSplatBits, APSplatUndef;
5186 unsigned SplatBitSize;
5188 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5189 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5192 unsigned SplatBits = APSplatBits.getZExtValue();
5193 unsigned SplatUndef = APSplatUndef.getZExtValue();
5194 unsigned SplatSize = SplatBitSize / 8;
5196 // First, handle single instruction cases.
5199 if (SplatBits == 0) {
5200 // Canonicalize all zero vectors to be v4i32.
5201 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5202 SDValue Z = DAG.getConstant(0, MVT::i32);
5203 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5204 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5209 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5210 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5212 if (SextVal >= -16 && SextVal <= 15)
5213 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5216 // Two instruction sequences.
5218 // If this value is in the range [-32,30] and is even, use:
5219 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5220 // If this value is in the range [17,31] and is odd, use:
5221 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5222 // If this value is in the range [-31,-17] and is odd, use:
5223 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5224 // Note the last two are three-instruction sequences.
5225 if (SextVal >= -32 && SextVal <= 31) {
5226 // To avoid having these optimizations undone by constant folding,
5227 // we convert to a pseudo that will be expanded later into one of
5229 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5230 EVT VT = Op.getValueType();
5231 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5232 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5233 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5236 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5237 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5239 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5240 // Make -1 and vspltisw -1:
5241 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5243 // Make the VSLW intrinsic, computing 0x8000_0000.
5244 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5247 // xor by OnesV to invert it.
5248 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5249 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5252 // Check to see if this is a wide variety of vsplti*, binop self cases.
5253 static const signed char SplatCsts[] = {
5254 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5255 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5258 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5259 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5260 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5261 int i = SplatCsts[idx];
5263 // Figure out what shift amount will be used by altivec if shifted by i in
5265 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5267 // vsplti + shl self.
5268 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5269 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5270 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5271 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5272 Intrinsic::ppc_altivec_vslw
5274 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5275 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5278 // vsplti + srl self.
5279 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5280 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5281 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5282 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5283 Intrinsic::ppc_altivec_vsrw
5285 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5286 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5289 // vsplti + sra self.
5290 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5291 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5292 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5293 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5294 Intrinsic::ppc_altivec_vsraw
5296 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5297 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5300 // vsplti + rol self.
5301 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5302 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5303 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5304 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5305 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5306 Intrinsic::ppc_altivec_vrlw
5308 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5309 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5312 // t = vsplti c, result = vsldoi t, t, 1
5313 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5314 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5315 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5317 // t = vsplti c, result = vsldoi t, t, 2
5318 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5319 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5320 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5322 // t = vsplti c, result = vsldoi t, t, 3
5323 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5324 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5325 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5332 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5333 /// the specified operations to build the shuffle.
5334 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5335 SDValue RHS, SelectionDAG &DAG,
5337 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5338 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5339 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5342 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5354 if (OpNum == OP_COPY) {
5355 if (LHSID == (1*9+2)*9+3) return LHS;
5356 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5360 SDValue OpLHS, OpRHS;
5361 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5362 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5366 default: llvm_unreachable("Unknown i32 permute!");
5368 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5369 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5370 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5371 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5374 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5375 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5376 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5377 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5380 for (unsigned i = 0; i != 16; ++i)
5381 ShufIdxs[i] = (i&3)+0;
5384 for (unsigned i = 0; i != 16; ++i)
5385 ShufIdxs[i] = (i&3)+4;
5388 for (unsigned i = 0; i != 16; ++i)
5389 ShufIdxs[i] = (i&3)+8;
5392 for (unsigned i = 0; i != 16; ++i)
5393 ShufIdxs[i] = (i&3)+12;
5396 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5398 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5400 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5402 EVT VT = OpLHS.getValueType();
5403 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5404 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5405 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5406 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5409 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5410 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5411 /// return the code it can be lowered into. Worst case, it can always be
5412 /// lowered into a vperm.
5413 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5414 SelectionDAG &DAG) const {
5416 SDValue V1 = Op.getOperand(0);
5417 SDValue V2 = Op.getOperand(1);
5418 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5419 EVT VT = Op.getValueType();
5421 // Cases that are handled by instructions that take permute immediates
5422 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5423 // selected by the instruction selector.
5424 if (V2.getOpcode() == ISD::UNDEF) {
5425 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5426 PPC::isSplatShuffleMask(SVOp, 2) ||
5427 PPC::isSplatShuffleMask(SVOp, 4) ||
5428 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5429 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5430 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5431 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5432 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5433 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5434 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5435 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5436 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5441 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5442 // and produce a fixed permutation. If any of these match, do not lower to
5444 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5445 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5446 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5447 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5448 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5449 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5450 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5451 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5452 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5455 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5456 // perfect shuffle table to emit an optimal matching sequence.
5457 ArrayRef<int> PermMask = SVOp->getMask();
5459 unsigned PFIndexes[4];
5460 bool isFourElementShuffle = true;
5461 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5462 unsigned EltNo = 8; // Start out undef.
5463 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5464 if (PermMask[i*4+j] < 0)
5465 continue; // Undef, ignore it.
5467 unsigned ByteSource = PermMask[i*4+j];
5468 if ((ByteSource & 3) != j) {
5469 isFourElementShuffle = false;
5474 EltNo = ByteSource/4;
5475 } else if (EltNo != ByteSource/4) {
5476 isFourElementShuffle = false;
5480 PFIndexes[i] = EltNo;
5483 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5484 // perfect shuffle vector to determine if it is cost effective to do this as
5485 // discrete instructions, or whether we should use a vperm.
5486 if (isFourElementShuffle) {
5487 // Compute the index in the perfect shuffle table.
5488 unsigned PFTableIndex =
5489 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5491 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5492 unsigned Cost = (PFEntry >> 30);
5494 // Determining when to avoid vperm is tricky. Many things affect the cost
5495 // of vperm, particularly how many times the perm mask needs to be computed.
5496 // For example, if the perm mask can be hoisted out of a loop or is already
5497 // used (perhaps because there are multiple permutes with the same shuffle
5498 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5499 // the loop requires an extra register.
5501 // As a compromise, we only emit discrete instructions if the shuffle can be
5502 // generated in 3 or fewer operations. When we have loop information
5503 // available, if this block is within a loop, we should avoid using vperm
5504 // for 3-operation perms and use a constant pool load instead.
5506 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5509 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5510 // vector that will get spilled to the constant pool.
5511 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5513 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5514 // that it is in input element units, not in bytes. Convert now.
5515 EVT EltVT = V1.getValueType().getVectorElementType();
5516 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5518 SmallVector<SDValue, 16> ResultMask;
5519 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5520 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5522 for (unsigned j = 0; j != BytesPerElement; ++j)
5523 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5527 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5528 &ResultMask[0], ResultMask.size());
5529 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5532 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5533 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5534 /// information about the intrinsic.
5535 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5537 unsigned IntrinsicID =
5538 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5541 switch (IntrinsicID) {
5542 default: return false;
5543 // Comparison predicates.
5544 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5545 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5546 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5547 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5548 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5549 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5550 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5551 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5552 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5553 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5554 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5555 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5556 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5558 // Normal Comparisons.
5559 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5560 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5561 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5562 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5563 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5564 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5565 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5566 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5567 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5568 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5569 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5570 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5571 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5576 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5577 /// lower, do it, otherwise return null.
5578 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5579 SelectionDAG &DAG) const {
5580 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5581 // opcode number of the comparison.
5585 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5586 return SDValue(); // Don't custom lower most intrinsics.
5588 // If this is a non-dot comparison, make the VCMP node and we are done.
5590 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5591 Op.getOperand(1), Op.getOperand(2),
5592 DAG.getConstant(CompareOpc, MVT::i32));
5593 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5596 // Create the PPCISD altivec 'dot' comparison node.
5598 Op.getOperand(2), // LHS
5599 Op.getOperand(3), // RHS
5600 DAG.getConstant(CompareOpc, MVT::i32)
5602 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5603 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5605 // Now that we have the comparison, emit a copy from the CR to a GPR.
5606 // This is flagged to the above dot comparison.
5607 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5608 DAG.getRegister(PPC::CR6, MVT::i32),
5609 CompNode.getValue(1));
5611 // Unpack the result based on how the target uses it.
5612 unsigned BitNo; // Bit # of CR6.
5613 bool InvertBit; // Invert result?
5614 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5615 default: // Can't happen, don't crash on invalid number though.
5616 case 0: // Return the value of the EQ bit of CR6.
5617 BitNo = 0; InvertBit = false;
5619 case 1: // Return the inverted value of the EQ bit of CR6.
5620 BitNo = 0; InvertBit = true;
5622 case 2: // Return the value of the LT bit of CR6.
5623 BitNo = 2; InvertBit = false;
5625 case 3: // Return the inverted value of the LT bit of CR6.
5626 BitNo = 2; InvertBit = true;
5630 // Shift the bit into the low position.
5631 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5632 DAG.getConstant(8-(3-BitNo), MVT::i32));
5634 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5635 DAG.getConstant(1, MVT::i32));
5637 // If we are supposed to, toggle the bit.
5639 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5640 DAG.getConstant(1, MVT::i32));
5644 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5645 SelectionDAG &DAG) const {
5647 // Create a stack slot that is 16-byte aligned.
5648 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5649 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5650 EVT PtrVT = getPointerTy();
5651 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5653 // Store the input value into Value#0 of the stack slot.
5654 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5655 Op.getOperand(0), FIdx, MachinePointerInfo(),
5658 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5659 false, false, false, 0);
5662 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5664 if (Op.getValueType() == MVT::v4i32) {
5665 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5667 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5668 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5670 SDValue RHSSwap = // = vrlw RHS, 16
5671 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
5673 // Shrinkify inputs to v8i16.
5674 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5675 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5676 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5678 // Low parts multiplied together, generating 32-bit results (we ignore the
5680 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
5681 LHS, RHS, DAG, dl, MVT::v4i32);
5683 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
5684 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5685 // Shift the high parts up 16 bits.
5686 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
5688 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5689 } else if (Op.getValueType() == MVT::v8i16) {
5690 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5692 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5694 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
5695 LHS, RHS, Zero, DAG, dl);
5696 } else if (Op.getValueType() == MVT::v16i8) {
5697 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5699 // Multiply the even 8-bit parts, producing 16-bit sums.
5700 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
5701 LHS, RHS, DAG, dl, MVT::v8i16);
5702 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5704 // Multiply the odd 8-bit parts, producing 16-bit sums.
5705 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
5706 LHS, RHS, DAG, dl, MVT::v8i16);
5707 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5709 // Merge the results together.
5711 for (unsigned i = 0; i != 8; ++i) {
5713 Ops[i*2+1] = 2*i+1+16;
5715 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5717 llvm_unreachable("Unknown mul to lower!");
5721 /// LowerOperation - Provide custom lowering hooks for some operations.
5723 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5724 switch (Op.getOpcode()) {
5725 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
5726 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5727 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5728 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5729 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5730 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5731 case ISD::SETCC: return LowerSETCC(Op, DAG);
5732 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
5733 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
5735 return LowerVASTART(Op, DAG, PPCSubTarget);
5738 return LowerVAARG(Op, DAG, PPCSubTarget);
5741 return LowerVACOPY(Op, DAG, PPCSubTarget);
5743 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
5744 case ISD::DYNAMIC_STACKALLOC:
5745 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
5747 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
5748 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
5750 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5751 case ISD::FP_TO_UINT:
5752 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
5754 case ISD::UINT_TO_FP:
5755 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
5756 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5758 // Lower 64-bit shifts.
5759 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
5760 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
5761 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
5763 // Vector-related lowering.
5764 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5765 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5766 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5767 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5768 case ISD::MUL: return LowerMUL(Op, DAG);
5770 // For counter-based loop handling.
5771 case ISD::INTRINSIC_W_CHAIN: return SDValue();
5773 // Frame & Return address.
5774 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5775 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5779 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
5780 SmallVectorImpl<SDValue>&Results,
5781 SelectionDAG &DAG) const {
5782 const TargetMachine &TM = getTargetMachine();
5784 switch (N->getOpcode()) {
5786 llvm_unreachable("Do not know how to custom type legalize this operation!");
5787 case ISD::INTRINSIC_W_CHAIN: {
5788 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
5789 Intrinsic::ppc_is_decremented_ctr_nonzero)
5792 assert(N->getValueType(0) == MVT::i1 &&
5793 "Unexpected result type for CTR decrement intrinsic");
5794 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
5795 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
5796 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
5799 Results.push_back(NewInt);
5800 Results.push_back(NewInt.getValue(1));
5804 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
5805 || TM.getSubtarget<PPCSubtarget>().isPPC64())
5808 EVT VT = N->getValueType(0);
5810 if (VT == MVT::i64) {
5811 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
5813 Results.push_back(NewNode);
5814 Results.push_back(NewNode.getValue(1));
5818 case ISD::FP_ROUND_INREG: {
5819 assert(N->getValueType(0) == MVT::ppcf128);
5820 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5821 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5822 MVT::f64, N->getOperand(0),
5823 DAG.getIntPtrConstant(0));
5824 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5825 MVT::f64, N->getOperand(0),
5826 DAG.getIntPtrConstant(1));
5828 // Add the two halves of the long double in round-to-zero mode.
5829 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
5831 // We know the low half is about to be thrown away, so just use something
5833 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5837 case ISD::FP_TO_SINT:
5838 // LowerFP_TO_INT() can only handle f32 and f64.
5839 if (N->getOperand(0).getValueType() == MVT::ppcf128)
5841 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
5847 //===----------------------------------------------------------------------===//
5848 // Other Lowering Code
5849 //===----------------------------------------------------------------------===//
5852 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5853 bool is64bit, unsigned BinOpcode) const {
5854 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5855 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5857 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5858 MachineFunction *F = BB->getParent();
5859 MachineFunction::iterator It = BB;
5862 unsigned dest = MI->getOperand(0).getReg();
5863 unsigned ptrA = MI->getOperand(1).getReg();
5864 unsigned ptrB = MI->getOperand(2).getReg();
5865 unsigned incr = MI->getOperand(3).getReg();
5866 DebugLoc dl = MI->getDebugLoc();
5868 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5869 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5870 F->insert(It, loopMBB);
5871 F->insert(It, exitMBB);
5872 exitMBB->splice(exitMBB->begin(), BB,
5873 llvm::next(MachineBasicBlock::iterator(MI)),
5875 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5877 MachineRegisterInfo &RegInfo = F->getRegInfo();
5878 unsigned TmpReg = (!BinOpcode) ? incr :
5879 RegInfo.createVirtualRegister(
5880 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5881 (const TargetRegisterClass *) &PPC::GPRCRegClass);
5885 // fallthrough --> loopMBB
5886 BB->addSuccessor(loopMBB);
5889 // l[wd]arx dest, ptr
5890 // add r0, dest, incr
5891 // st[wd]cx. r0, ptr
5893 // fallthrough --> exitMBB
5895 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5896 .addReg(ptrA).addReg(ptrB);
5898 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
5899 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5900 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
5901 BuildMI(BB, dl, TII->get(PPC::BCC))
5902 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5903 BB->addSuccessor(loopMBB);
5904 BB->addSuccessor(exitMBB);
5913 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
5914 MachineBasicBlock *BB,
5915 bool is8bit, // operation
5916 unsigned BinOpcode) const {
5917 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5918 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5919 // In 64 bit mode we have to use 64 bits for addresses, even though the
5920 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
5921 // registers without caring whether they're 32 or 64, but here we're
5922 // doing actual arithmetic on the addresses.
5923 bool is64bit = PPCSubTarget.isPPC64();
5924 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
5926 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5927 MachineFunction *F = BB->getParent();
5928 MachineFunction::iterator It = BB;
5931 unsigned dest = MI->getOperand(0).getReg();
5932 unsigned ptrA = MI->getOperand(1).getReg();
5933 unsigned ptrB = MI->getOperand(2).getReg();
5934 unsigned incr = MI->getOperand(3).getReg();
5935 DebugLoc dl = MI->getDebugLoc();
5937 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5938 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5939 F->insert(It, loopMBB);
5940 F->insert(It, exitMBB);
5941 exitMBB->splice(exitMBB->begin(), BB,
5942 llvm::next(MachineBasicBlock::iterator(MI)),
5944 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5946 MachineRegisterInfo &RegInfo = F->getRegInfo();
5947 const TargetRegisterClass *RC =
5948 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5949 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5950 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5951 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5952 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5953 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
5954 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
5955 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
5956 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
5957 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
5958 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
5959 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
5960 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
5962 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
5966 // fallthrough --> loopMBB
5967 BB->addSuccessor(loopMBB);
5969 // The 4-byte load must be aligned, while a char or short may be
5970 // anywhere in the word. Hence all this nasty bookkeeping code.
5971 // add ptr1, ptrA, ptrB [copy if ptrA==0]
5972 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
5973 // xori shift, shift1, 24 [16]
5974 // rlwinm ptr, ptr1, 0, 0, 29
5975 // slw incr2, incr, shift
5976 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
5977 // slw mask, mask2, shift
5979 // lwarx tmpDest, ptr
5980 // add tmp, tmpDest, incr2
5981 // andc tmp2, tmpDest, mask
5982 // and tmp3, tmp, mask
5983 // or tmp4, tmp3, tmp2
5986 // fallthrough --> exitMBB
5987 // srw dest, tmpDest, shift
5988 if (ptrA != ZeroReg) {
5989 Ptr1Reg = RegInfo.createVirtualRegister(RC);
5990 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
5991 .addReg(ptrA).addReg(ptrB);
5995 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5996 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
5997 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5998 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6000 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6001 .addReg(Ptr1Reg).addImm(0).addImm(61);
6003 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6004 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6005 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6006 .addReg(incr).addReg(ShiftReg);
6008 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6010 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6011 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6013 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6014 .addReg(Mask2Reg).addReg(ShiftReg);
6017 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6018 .addReg(ZeroReg).addReg(PtrReg);
6020 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6021 .addReg(Incr2Reg).addReg(TmpDestReg);
6022 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6023 .addReg(TmpDestReg).addReg(MaskReg);
6024 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6025 .addReg(TmpReg).addReg(MaskReg);
6026 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6027 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6028 BuildMI(BB, dl, TII->get(PPC::STWCX))
6029 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6030 BuildMI(BB, dl, TII->get(PPC::BCC))
6031 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6032 BB->addSuccessor(loopMBB);
6033 BB->addSuccessor(exitMBB);
6038 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6043 llvm::MachineBasicBlock*
6044 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6045 MachineBasicBlock *MBB) const {
6046 DebugLoc DL = MI->getDebugLoc();
6047 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6049 MachineFunction *MF = MBB->getParent();
6050 MachineRegisterInfo &MRI = MF->getRegInfo();
6052 const BasicBlock *BB = MBB->getBasicBlock();
6053 MachineFunction::iterator I = MBB;
6057 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6058 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6060 unsigned DstReg = MI->getOperand(0).getReg();
6061 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6062 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6063 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6064 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6066 MVT PVT = getPointerTy();
6067 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6068 "Invalid Pointer Size!");
6069 // For v = setjmp(buf), we generate
6072 // SjLjSetup mainMBB
6078 // buf[LabelOffset] = LR
6082 // v = phi(main, restore)
6085 MachineBasicBlock *thisMBB = MBB;
6086 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6087 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6088 MF->insert(I, mainMBB);
6089 MF->insert(I, sinkMBB);
6091 MachineInstrBuilder MIB;
6093 // Transfer the remainder of BB and its successor edges to sinkMBB.
6094 sinkMBB->splice(sinkMBB->begin(), MBB,
6095 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
6096 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6098 // Note that the structure of the jmp_buf used here is not compatible
6099 // with that used by libc, and is not designed to be. Specifically, it
6100 // stores only those 'reserved' registers that LLVM does not otherwise
6101 // understand how to spill. Also, by convention, by the time this
6102 // intrinsic is called, Clang has already stored the frame address in the
6103 // first slot of the buffer and stack address in the third. Following the
6104 // X86 target code, we'll store the jump address in the second slot. We also
6105 // need to save the TOC pointer (R2) to handle jumps between shared
6106 // libraries, and that will be stored in the fourth slot. The thread
6107 // identifier (R13) is not affected.
6110 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6111 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6112 const int64_t BPOffset = 4 * PVT.getStoreSize();
6114 // Prepare IP either in reg.
6115 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6116 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6117 unsigned BufReg = MI->getOperand(1).getReg();
6119 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) {
6120 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6124 MIB.setMemRefs(MMOBegin, MMOEnd);
6127 // Naked functions never have a base pointer, and so we use r1. For all
6128 // other functions, this decision must be delayed until during PEI.
6130 if (MF->getFunction()->getAttributes().hasAttribute(
6131 AttributeSet::FunctionIndex, Attribute::Naked))
6132 BaseReg = PPCSubTarget.isPPC64() ? PPC::X1 : PPC::R1;
6134 BaseReg = PPCSubTarget.isPPC64() ? PPC::BP8 : PPC::BP;
6136 MIB = BuildMI(*thisMBB, MI, DL,
6137 TII->get(PPCSubTarget.isPPC64() ? PPC::STD : PPC::STW))
6141 MIB.setMemRefs(MMOBegin, MMOEnd);
6144 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6145 const PPCRegisterInfo *TRI =
6146 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6147 MIB.addRegMask(TRI->getNoPreservedMask());
6149 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6151 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6153 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6155 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6156 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6160 MIB = BuildMI(mainMBB, DL,
6161 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6164 if (PPCSubTarget.isPPC64()) {
6165 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6167 .addImm(LabelOffset)
6170 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6172 .addImm(LabelOffset)
6176 MIB.setMemRefs(MMOBegin, MMOEnd);
6178 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6179 mainMBB->addSuccessor(sinkMBB);
6182 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6183 TII->get(PPC::PHI), DstReg)
6184 .addReg(mainDstReg).addMBB(mainMBB)
6185 .addReg(restoreDstReg).addMBB(thisMBB);
6187 MI->eraseFromParent();
6192 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6193 MachineBasicBlock *MBB) const {
6194 DebugLoc DL = MI->getDebugLoc();
6195 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6197 MachineFunction *MF = MBB->getParent();
6198 MachineRegisterInfo &MRI = MF->getRegInfo();
6201 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6202 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6204 MVT PVT = getPointerTy();
6205 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6206 "Invalid Pointer Size!");
6208 const TargetRegisterClass *RC =
6209 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6210 unsigned Tmp = MRI.createVirtualRegister(RC);
6211 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6212 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6213 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6214 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6216 MachineInstrBuilder MIB;
6218 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6219 const int64_t SPOffset = 2 * PVT.getStoreSize();
6220 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6221 const int64_t BPOffset = 4 * PVT.getStoreSize();
6223 unsigned BufReg = MI->getOperand(0).getReg();
6225 // Reload FP (the jumped-to function may not have had a
6226 // frame pointer, and if so, then its r31 will be restored
6228 if (PVT == MVT::i64) {
6229 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6233 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6237 MIB.setMemRefs(MMOBegin, MMOEnd);
6240 if (PVT == MVT::i64) {
6241 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6242 .addImm(LabelOffset)
6245 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6246 .addImm(LabelOffset)
6249 MIB.setMemRefs(MMOBegin, MMOEnd);
6252 if (PVT == MVT::i64) {
6253 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6257 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6261 MIB.setMemRefs(MMOBegin, MMOEnd);
6264 if (PVT == MVT::i64) {
6265 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6269 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6273 MIB.setMemRefs(MMOBegin, MMOEnd);
6276 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6277 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6281 MIB.setMemRefs(MMOBegin, MMOEnd);
6285 BuildMI(*MBB, MI, DL,
6286 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6287 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6289 MI->eraseFromParent();
6294 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6295 MachineBasicBlock *BB) const {
6296 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6297 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6298 return emitEHSjLjSetJmp(MI, BB);
6299 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6300 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6301 return emitEHSjLjLongJmp(MI, BB);
6304 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6306 // To "insert" these instructions we actually have to insert their
6307 // control-flow patterns.
6308 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6309 MachineFunction::iterator It = BB;
6312 MachineFunction *F = BB->getParent();
6314 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6315 MI->getOpcode() == PPC::SELECT_CC_I8)) {
6316 SmallVector<MachineOperand, 2> Cond;
6317 Cond.push_back(MI->getOperand(4));
6318 Cond.push_back(MI->getOperand(1));
6320 DebugLoc dl = MI->getDebugLoc();
6321 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6322 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6323 Cond, MI->getOperand(2).getReg(),
6324 MI->getOperand(3).getReg());
6325 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6326 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6327 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6328 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6329 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
6332 // The incoming instruction knows the destination vreg to set, the
6333 // condition code register to branch on, the true/false values to
6334 // select between, and a branch opcode to use.
6339 // cmpTY ccX, r1, r2
6341 // fallthrough --> copy0MBB
6342 MachineBasicBlock *thisMBB = BB;
6343 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6344 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6345 unsigned SelectPred = MI->getOperand(4).getImm();
6346 DebugLoc dl = MI->getDebugLoc();
6347 F->insert(It, copy0MBB);
6348 F->insert(It, sinkMBB);
6350 // Transfer the remainder of BB and its successor edges to sinkMBB.
6351 sinkMBB->splice(sinkMBB->begin(), BB,
6352 llvm::next(MachineBasicBlock::iterator(MI)),
6354 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6356 // Next, add the true and fallthrough blocks as its successors.
6357 BB->addSuccessor(copy0MBB);
6358 BB->addSuccessor(sinkMBB);
6360 BuildMI(BB, dl, TII->get(PPC::BCC))
6361 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6364 // %FalseValue = ...
6365 // # fallthrough to sinkMBB
6368 // Update machine-CFG edges
6369 BB->addSuccessor(sinkMBB);
6372 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6375 BuildMI(*BB, BB->begin(), dl,
6376 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6377 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6378 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6380 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6381 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6382 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6383 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6384 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6385 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6386 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6387 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6389 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6390 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6391 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6392 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6393 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6394 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6395 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6396 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6398 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6399 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6400 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6401 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6402 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6403 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6404 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6405 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6407 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6408 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6409 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6410 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6411 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6412 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6413 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6414 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6416 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6417 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6418 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6419 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6420 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6421 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6422 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6423 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6425 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6426 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6427 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6428 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6429 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6430 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6431 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6432 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6434 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6435 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6436 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6437 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6438 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6439 BB = EmitAtomicBinary(MI, BB, false, 0);
6440 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6441 BB = EmitAtomicBinary(MI, BB, true, 0);
6443 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6444 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6445 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6447 unsigned dest = MI->getOperand(0).getReg();
6448 unsigned ptrA = MI->getOperand(1).getReg();
6449 unsigned ptrB = MI->getOperand(2).getReg();
6450 unsigned oldval = MI->getOperand(3).getReg();
6451 unsigned newval = MI->getOperand(4).getReg();
6452 DebugLoc dl = MI->getDebugLoc();
6454 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6455 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6456 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6457 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6458 F->insert(It, loop1MBB);
6459 F->insert(It, loop2MBB);
6460 F->insert(It, midMBB);
6461 F->insert(It, exitMBB);
6462 exitMBB->splice(exitMBB->begin(), BB,
6463 llvm::next(MachineBasicBlock::iterator(MI)),
6465 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6469 // fallthrough --> loopMBB
6470 BB->addSuccessor(loop1MBB);
6473 // l[wd]arx dest, ptr
6474 // cmp[wd] dest, oldval
6477 // st[wd]cx. newval, ptr
6481 // st[wd]cx. dest, ptr
6484 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6485 .addReg(ptrA).addReg(ptrB);
6486 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6487 .addReg(oldval).addReg(dest);
6488 BuildMI(BB, dl, TII->get(PPC::BCC))
6489 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6490 BB->addSuccessor(loop2MBB);
6491 BB->addSuccessor(midMBB);
6494 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6495 .addReg(newval).addReg(ptrA).addReg(ptrB);
6496 BuildMI(BB, dl, TII->get(PPC::BCC))
6497 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6498 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6499 BB->addSuccessor(loop1MBB);
6500 BB->addSuccessor(exitMBB);
6503 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6504 .addReg(dest).addReg(ptrA).addReg(ptrB);
6505 BB->addSuccessor(exitMBB);
6510 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6511 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6512 // We must use 64-bit registers for addresses when targeting 64-bit,
6513 // since we're actually doing arithmetic on them. Other registers
6515 bool is64bit = PPCSubTarget.isPPC64();
6516 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6518 unsigned dest = MI->getOperand(0).getReg();
6519 unsigned ptrA = MI->getOperand(1).getReg();
6520 unsigned ptrB = MI->getOperand(2).getReg();
6521 unsigned oldval = MI->getOperand(3).getReg();
6522 unsigned newval = MI->getOperand(4).getReg();
6523 DebugLoc dl = MI->getDebugLoc();
6525 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6526 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6527 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6528 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6529 F->insert(It, loop1MBB);
6530 F->insert(It, loop2MBB);
6531 F->insert(It, midMBB);
6532 F->insert(It, exitMBB);
6533 exitMBB->splice(exitMBB->begin(), BB,
6534 llvm::next(MachineBasicBlock::iterator(MI)),
6536 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6538 MachineRegisterInfo &RegInfo = F->getRegInfo();
6539 const TargetRegisterClass *RC =
6540 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6541 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6542 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6543 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6544 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6545 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6546 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6547 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6548 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6549 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6550 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6551 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6552 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6553 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6554 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6556 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6557 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6560 // fallthrough --> loopMBB
6561 BB->addSuccessor(loop1MBB);
6563 // The 4-byte load must be aligned, while a char or short may be
6564 // anywhere in the word. Hence all this nasty bookkeeping code.
6565 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6566 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6567 // xori shift, shift1, 24 [16]
6568 // rlwinm ptr, ptr1, 0, 0, 29
6569 // slw newval2, newval, shift
6570 // slw oldval2, oldval,shift
6571 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6572 // slw mask, mask2, shift
6573 // and newval3, newval2, mask
6574 // and oldval3, oldval2, mask
6576 // lwarx tmpDest, ptr
6577 // and tmp, tmpDest, mask
6578 // cmpw tmp, oldval3
6581 // andc tmp2, tmpDest, mask
6582 // or tmp4, tmp2, newval3
6587 // stwcx. tmpDest, ptr
6589 // srw dest, tmpDest, shift
6590 if (ptrA != ZeroReg) {
6591 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6592 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6593 .addReg(ptrA).addReg(ptrB);
6597 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6598 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6599 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6600 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6602 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6603 .addReg(Ptr1Reg).addImm(0).addImm(61);
6605 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6606 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6607 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6608 .addReg(newval).addReg(ShiftReg);
6609 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6610 .addReg(oldval).addReg(ShiftReg);
6612 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6614 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6615 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6616 .addReg(Mask3Reg).addImm(65535);
6618 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6619 .addReg(Mask2Reg).addReg(ShiftReg);
6620 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6621 .addReg(NewVal2Reg).addReg(MaskReg);
6622 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6623 .addReg(OldVal2Reg).addReg(MaskReg);
6626 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6627 .addReg(ZeroReg).addReg(PtrReg);
6628 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6629 .addReg(TmpDestReg).addReg(MaskReg);
6630 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6631 .addReg(TmpReg).addReg(OldVal3Reg);
6632 BuildMI(BB, dl, TII->get(PPC::BCC))
6633 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6634 BB->addSuccessor(loop2MBB);
6635 BB->addSuccessor(midMBB);
6638 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6639 .addReg(TmpDestReg).addReg(MaskReg);
6640 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6641 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6642 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6643 .addReg(ZeroReg).addReg(PtrReg);
6644 BuildMI(BB, dl, TII->get(PPC::BCC))
6645 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6646 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6647 BB->addSuccessor(loop1MBB);
6648 BB->addSuccessor(exitMBB);
6651 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
6652 .addReg(ZeroReg).addReg(PtrReg);
6653 BB->addSuccessor(exitMBB);
6658 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
6660 } else if (MI->getOpcode() == PPC::FADDrtz) {
6661 // This pseudo performs an FADD with rounding mode temporarily forced
6662 // to round-to-zero. We emit this via custom inserter since the FPSCR
6663 // is not modeled at the SelectionDAG level.
6664 unsigned Dest = MI->getOperand(0).getReg();
6665 unsigned Src1 = MI->getOperand(1).getReg();
6666 unsigned Src2 = MI->getOperand(2).getReg();
6667 DebugLoc dl = MI->getDebugLoc();
6669 MachineRegisterInfo &RegInfo = F->getRegInfo();
6670 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
6672 // Save FPSCR value.
6673 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
6675 // Set rounding mode to round-to-zero.
6676 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
6677 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
6679 // Perform addition.
6680 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
6682 // Restore FPSCR value.
6683 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
6685 llvm_unreachable("Unexpected instr type to insert");
6688 MI->eraseFromParent(); // The pseudo instruction is gone now.
6692 //===----------------------------------------------------------------------===//
6693 // Target Optimization Hooks
6694 //===----------------------------------------------------------------------===//
6696 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
6697 DAGCombinerInfo &DCI) const {
6698 if (DCI.isAfterLegalizeVectorOps())
6701 EVT VT = Op.getValueType();
6703 if ((VT == MVT::f32 && PPCSubTarget.hasFRES()) ||
6704 (VT == MVT::f64 && PPCSubTarget.hasFRE()) ||
6705 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6707 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6708 // For the reciprocal, we need to find the zero of the function:
6709 // F(X) = A X - 1 [which has a zero at X = 1/A]
6711 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
6712 // does not require additional intermediate precision]
6714 // Convergence is quadratic, so we essentially double the number of digits
6715 // correct after every iteration. The minimum architected relative
6716 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6717 // 23 digits and double has 52 digits.
6718 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6719 if (VT.getScalarType() == MVT::f64)
6722 SelectionDAG &DAG = DCI.DAG;
6726 DAG.getConstantFP(1.0, VT.getScalarType());
6727 if (VT.isVector()) {
6728 assert(VT.getVectorNumElements() == 4 &&
6729 "Unknown vector type");
6730 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6731 FPOne, FPOne, FPOne, FPOne);
6734 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
6735 DCI.AddToWorklist(Est.getNode());
6737 // Newton iterations: Est = Est + Est (1 - Arg * Est)
6738 for (int i = 0; i < Iterations; ++i) {
6739 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
6740 DCI.AddToWorklist(NewEst.getNode());
6742 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
6743 DCI.AddToWorklist(NewEst.getNode());
6745 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6746 DCI.AddToWorklist(NewEst.getNode());
6748 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
6749 DCI.AddToWorklist(Est.getNode());
6758 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
6759 DAGCombinerInfo &DCI) const {
6760 if (DCI.isAfterLegalizeVectorOps())
6763 EVT VT = Op.getValueType();
6765 if ((VT == MVT::f32 && PPCSubTarget.hasFRSQRTES()) ||
6766 (VT == MVT::f64 && PPCSubTarget.hasFRSQRTE()) ||
6767 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6769 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6770 // For the reciprocal sqrt, we need to find the zero of the function:
6771 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
6773 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
6774 // As a result, we precompute A/2 prior to the iteration loop.
6776 // Convergence is quadratic, so we essentially double the number of digits
6777 // correct after every iteration. The minimum architected relative
6778 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6779 // 23 digits and double has 52 digits.
6780 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6781 if (VT.getScalarType() == MVT::f64)
6784 SelectionDAG &DAG = DCI.DAG;
6787 SDValue FPThreeHalves =
6788 DAG.getConstantFP(1.5, VT.getScalarType());
6789 if (VT.isVector()) {
6790 assert(VT.getVectorNumElements() == 4 &&
6791 "Unknown vector type");
6792 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6793 FPThreeHalves, FPThreeHalves,
6794 FPThreeHalves, FPThreeHalves);
6797 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
6798 DCI.AddToWorklist(Est.getNode());
6800 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
6801 // this entire sequence requires only one FP constant.
6802 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
6803 DCI.AddToWorklist(HalfArg.getNode());
6805 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
6806 DCI.AddToWorklist(HalfArg.getNode());
6808 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
6809 for (int i = 0; i < Iterations; ++i) {
6810 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
6811 DCI.AddToWorklist(NewEst.getNode());
6813 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
6814 DCI.AddToWorklist(NewEst.getNode());
6816 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
6817 DCI.AddToWorklist(NewEst.getNode());
6819 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6820 DCI.AddToWorklist(Est.getNode());
6829 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
6830 // not enforce equality of the chain operands.
6831 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
6832 unsigned Bytes, int Dist,
6833 SelectionDAG &DAG) {
6834 EVT VT = LS->getMemoryVT();
6835 if (VT.getSizeInBits() / 8 != Bytes)
6838 SDValue Loc = LS->getBasePtr();
6839 SDValue BaseLoc = Base->getBasePtr();
6840 if (Loc.getOpcode() == ISD::FrameIndex) {
6841 if (BaseLoc.getOpcode() != ISD::FrameIndex)
6843 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6844 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
6845 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
6846 int FS = MFI->getObjectSize(FI);
6847 int BFS = MFI->getObjectSize(BFI);
6848 if (FS != BFS || FS != (int)Bytes) return false;
6849 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
6853 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
6854 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
6857 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6858 const GlobalValue *GV1 = NULL;
6859 const GlobalValue *GV2 = NULL;
6860 int64_t Offset1 = 0;
6861 int64_t Offset2 = 0;
6862 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
6863 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
6864 if (isGA1 && isGA2 && GV1 == GV2)
6865 return Offset1 == (Offset2 + Dist*Bytes);
6869 // Return true is there is a nearyby consecutive load to the one provided
6870 // (regardless of alignment). We search up and down the chain, looking though
6871 // token factors and other loads (but nothing else). As a result, a true
6872 // results indicates that it is safe to create a new consecutive load adjacent
6873 // to the load provided.
6874 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
6875 SDValue Chain = LD->getChain();
6876 EVT VT = LD->getMemoryVT();
6878 SmallSet<SDNode *, 16> LoadRoots;
6879 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
6880 SmallSet<SDNode *, 16> Visited;
6882 // First, search up the chain, branching to follow all token-factor operands.
6883 // If we find a consecutive load, then we're done, otherwise, record all
6884 // nodes just above the top-level loads and token factors.
6885 while (!Queue.empty()) {
6886 SDNode *ChainNext = Queue.pop_back_val();
6887 if (!Visited.insert(ChainNext))
6890 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
6891 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
6894 if (!Visited.count(ChainLD->getChain().getNode()))
6895 Queue.push_back(ChainLD->getChain().getNode());
6896 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
6897 for (SDNode::op_iterator O = ChainNext->op_begin(),
6898 OE = ChainNext->op_end(); O != OE; ++O)
6899 if (!Visited.count(O->getNode()))
6900 Queue.push_back(O->getNode());
6902 LoadRoots.insert(ChainNext);
6905 // Second, search down the chain, starting from the top-level nodes recorded
6906 // in the first phase. These top-level nodes are the nodes just above all
6907 // loads and token factors. Starting with their uses, recursively look though
6908 // all loads (just the chain uses) and token factors to find a consecutive
6913 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
6914 IE = LoadRoots.end(); I != IE; ++I) {
6915 Queue.push_back(*I);
6917 while (!Queue.empty()) {
6918 SDNode *LoadRoot = Queue.pop_back_val();
6919 if (!Visited.insert(LoadRoot))
6922 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
6923 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
6926 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
6927 UE = LoadRoot->use_end(); UI != UE; ++UI)
6928 if (((isa<LoadSDNode>(*UI) &&
6929 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
6930 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
6931 Queue.push_back(*UI);
6938 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
6939 DAGCombinerInfo &DCI) const {
6940 const TargetMachine &TM = getTargetMachine();
6941 SelectionDAG &DAG = DCI.DAG;
6943 switch (N->getOpcode()) {
6946 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6947 if (C->isNullValue()) // 0 << V -> 0.
6948 return N->getOperand(0);
6952 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6953 if (C->isNullValue()) // 0 >>u V -> 0.
6954 return N->getOperand(0);
6958 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6959 if (C->isNullValue() || // 0 >>s V -> 0.
6960 C->isAllOnesValue()) // -1 >>s V -> -1.
6961 return N->getOperand(0);
6965 assert(TM.Options.UnsafeFPMath &&
6966 "Reciprocal estimates require UnsafeFPMath");
6968 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
6970 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
6971 if (RV.getNode() != 0) {
6972 DCI.AddToWorklist(RV.getNode());
6973 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6974 N->getOperand(0), RV);
6976 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
6977 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
6979 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
6981 if (RV.getNode() != 0) {
6982 DCI.AddToWorklist(RV.getNode());
6983 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
6984 N->getValueType(0), RV);
6985 DCI.AddToWorklist(RV.getNode());
6986 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6987 N->getOperand(0), RV);
6989 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
6990 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
6992 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
6994 if (RV.getNode() != 0) {
6995 DCI.AddToWorklist(RV.getNode());
6996 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
6997 N->getValueType(0), RV,
6998 N->getOperand(1).getOperand(1));
6999 DCI.AddToWorklist(RV.getNode());
7000 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7001 N->getOperand(0), RV);
7005 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
7006 if (RV.getNode() != 0) {
7007 DCI.AddToWorklist(RV.getNode());
7008 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7009 N->getOperand(0), RV);
7015 assert(TM.Options.UnsafeFPMath &&
7016 "Reciprocal estimates require UnsafeFPMath");
7018 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
7020 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
7021 if (RV.getNode() != 0) {
7022 DCI.AddToWorklist(RV.getNode());
7023 RV = DAGCombineFastRecip(RV, DCI);
7024 if (RV.getNode() != 0) {
7025 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
7026 // this case and force the answer to 0.
7028 EVT VT = RV.getValueType();
7030 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
7031 if (VT.isVector()) {
7032 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
7033 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
7037 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
7038 N->getOperand(0), Zero, ISD::SETEQ);
7039 DCI.AddToWorklist(ZeroCmp.getNode());
7040 DCI.AddToWorklist(RV.getNode());
7042 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
7050 case ISD::SINT_TO_FP:
7051 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
7052 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
7053 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
7054 // We allow the src/dst to be either f32/f64, but the intermediate
7055 // type must be i64.
7056 if (N->getOperand(0).getValueType() == MVT::i64 &&
7057 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
7058 SDValue Val = N->getOperand(0).getOperand(0);
7059 if (Val.getValueType() == MVT::f32) {
7060 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7061 DCI.AddToWorklist(Val.getNode());
7064 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
7065 DCI.AddToWorklist(Val.getNode());
7066 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
7067 DCI.AddToWorklist(Val.getNode());
7068 if (N->getValueType(0) == MVT::f32) {
7069 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
7070 DAG.getIntPtrConstant(0));
7071 DCI.AddToWorklist(Val.getNode());
7074 } else if (N->getOperand(0).getValueType() == MVT::i32) {
7075 // If the intermediate type is i32, we can avoid the load/store here
7082 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
7083 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
7084 !cast<StoreSDNode>(N)->isTruncatingStore() &&
7085 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
7086 N->getOperand(1).getValueType() == MVT::i32 &&
7087 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
7088 SDValue Val = N->getOperand(1).getOperand(0);
7089 if (Val.getValueType() == MVT::f32) {
7090 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7091 DCI.AddToWorklist(Val.getNode());
7093 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
7094 DCI.AddToWorklist(Val.getNode());
7097 N->getOperand(0), Val, N->getOperand(2),
7098 DAG.getValueType(N->getOperand(1).getValueType())
7101 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
7102 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
7103 cast<StoreSDNode>(N)->getMemoryVT(),
7104 cast<StoreSDNode>(N)->getMemOperand());
7105 DCI.AddToWorklist(Val.getNode());
7109 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
7110 if (cast<StoreSDNode>(N)->isUnindexed() &&
7111 N->getOperand(1).getOpcode() == ISD::BSWAP &&
7112 N->getOperand(1).getNode()->hasOneUse() &&
7113 (N->getOperand(1).getValueType() == MVT::i32 ||
7114 N->getOperand(1).getValueType() == MVT::i16 ||
7115 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7116 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7117 N->getOperand(1).getValueType() == MVT::i64))) {
7118 SDValue BSwapOp = N->getOperand(1).getOperand(0);
7119 // Do an any-extend to 32-bits if this is a half-word input.
7120 if (BSwapOp.getValueType() == MVT::i16)
7121 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
7124 N->getOperand(0), BSwapOp, N->getOperand(2),
7125 DAG.getValueType(N->getOperand(1).getValueType())
7128 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
7129 Ops, array_lengthof(Ops),
7130 cast<StoreSDNode>(N)->getMemoryVT(),
7131 cast<StoreSDNode>(N)->getMemOperand());
7135 LoadSDNode *LD = cast<LoadSDNode>(N);
7136 EVT VT = LD->getValueType(0);
7137 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
7138 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
7139 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
7140 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
7141 DCI.getDAGCombineLevel() == AfterLegalizeTypes &&
7142 LD->getAlignment() < ABIAlignment) {
7143 // This is a type-legal unaligned Altivec load.
7144 SDValue Chain = LD->getChain();
7145 SDValue Ptr = LD->getBasePtr();
7147 // This implements the loading of unaligned vectors as described in
7148 // the venerable Apple Velocity Engine overview. Specifically:
7149 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
7150 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
7152 // The general idea is to expand a sequence of one or more unaligned
7153 // loads into a alignment-based permutation-control instruction (lvsl),
7154 // a series of regular vector loads (which always truncate their
7155 // input address to an aligned address), and a series of permutations.
7156 // The results of these permutations are the requested loaded values.
7157 // The trick is that the last "extra" load is not taken from the address
7158 // you might suspect (sizeof(vector) bytes after the last requested
7159 // load), but rather sizeof(vector) - 1 bytes after the last
7160 // requested vector. The point of this is to avoid a page fault if the
7161 // base address happend to be aligned. This works because if the base
7162 // address is aligned, then adding less than a full vector length will
7163 // cause the last vector in the sequence to be (re)loaded. Otherwise,
7164 // the next vector will be fetched as you might suspect was necessary.
7166 // We might be able to reuse the permutation generation from
7167 // a different base address offset from this one by an aligned amount.
7168 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
7169 // optimization later.
7170 SDValue PermCntl = BuildIntrinsicOp(Intrinsic::ppc_altivec_lvsl, Ptr,
7171 DAG, dl, MVT::v16i8);
7173 // Refine the alignment of the original load (a "new" load created here
7174 // which was identical to the first except for the alignment would be
7175 // merged with the existing node regardless).
7176 MachineFunction &MF = DAG.getMachineFunction();
7177 MachineMemOperand *MMO =
7178 MF.getMachineMemOperand(LD->getPointerInfo(),
7179 LD->getMemOperand()->getFlags(),
7180 LD->getMemoryVT().getStoreSize(),
7182 LD->refineAlignment(MMO);
7183 SDValue BaseLoad = SDValue(LD, 0);
7185 // Note that the value of IncOffset (which is provided to the next
7186 // load's pointer info offset value, and thus used to calculate the
7187 // alignment), and the value of IncValue (which is actually used to
7188 // increment the pointer value) are different! This is because we
7189 // require the next load to appear to be aligned, even though it
7190 // is actually offset from the base pointer by a lesser amount.
7191 int IncOffset = VT.getSizeInBits() / 8;
7192 int IncValue = IncOffset;
7194 // Walk (both up and down) the chain looking for another load at the real
7195 // (aligned) offset (the alignment of the other load does not matter in
7196 // this case). If found, then do not use the offset reduction trick, as
7197 // that will prevent the loads from being later combined (as they would
7198 // otherwise be duplicates).
7199 if (!findConsecutiveLoad(LD, DAG))
7202 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
7203 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
7206 DAG.getLoad(VT, dl, Chain, Ptr,
7207 LD->getPointerInfo().getWithOffset(IncOffset),
7208 LD->isVolatile(), LD->isNonTemporal(),
7209 LD->isInvariant(), ABIAlignment);
7211 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
7212 BaseLoad.getValue(1), ExtraLoad.getValue(1));
7214 if (BaseLoad.getValueType() != MVT::v4i32)
7215 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
7217 if (ExtraLoad.getValueType() != MVT::v4i32)
7218 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
7220 SDValue Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
7221 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
7223 if (VT != MVT::v4i32)
7224 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
7226 // Now we need to be really careful about how we update the users of the
7227 // original load. We cannot just call DCI.CombineTo (or
7228 // DAG.ReplaceAllUsesWith for that matter), because the load still has
7229 // uses created here (the permutation for example) that need to stay.
7230 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
7232 SDUse &Use = UI.getUse();
7234 // Note: BaseLoad is checked here because it might not be N, but a
7236 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
7237 User == TF.getNode() || Use.getResNo() > 1) {
7242 SDValue To = Use.getResNo() ? TF : Perm;
7245 SmallVector<SDValue, 8> Ops;
7246 for (SDNode::op_iterator O = User->op_begin(),
7247 OE = User->op_end(); O != OE; ++O) {
7254 DAG.UpdateNodeOperands(User, Ops.data(), Ops.size());
7257 return SDValue(N, 0);
7261 case ISD::INTRINSIC_WO_CHAIN:
7262 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() ==
7263 Intrinsic::ppc_altivec_lvsl &&
7264 N->getOperand(1)->getOpcode() == ISD::ADD) {
7265 SDValue Add = N->getOperand(1);
7267 if (DAG.MaskedValueIsZero(Add->getOperand(1),
7268 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
7269 Add.getValueType().getScalarType().getSizeInBits()))) {
7270 SDNode *BasePtr = Add->getOperand(0).getNode();
7271 for (SDNode::use_iterator UI = BasePtr->use_begin(),
7272 UE = BasePtr->use_end(); UI != UE; ++UI) {
7273 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7274 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
7275 Intrinsic::ppc_altivec_lvsl) {
7276 // We've found another LVSL, and this address if an aligned
7277 // multiple of that one. The results will be the same, so use the
7278 // one we've just found instead.
7280 return SDValue(*UI, 0);
7286 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
7287 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
7288 N->getOperand(0).hasOneUse() &&
7289 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
7290 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7291 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7292 N->getValueType(0) == MVT::i64))) {
7293 SDValue Load = N->getOperand(0);
7294 LoadSDNode *LD = cast<LoadSDNode>(Load);
7295 // Create the byte-swapping load.
7297 LD->getChain(), // Chain
7298 LD->getBasePtr(), // Ptr
7299 DAG.getValueType(N->getValueType(0)) // VT
7302 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
7303 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
7304 MVT::i64 : MVT::i32, MVT::Other),
7305 Ops, 3, LD->getMemoryVT(), LD->getMemOperand());
7307 // If this is an i16 load, insert the truncate.
7308 SDValue ResVal = BSLoad;
7309 if (N->getValueType(0) == MVT::i16)
7310 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
7312 // First, combine the bswap away. This makes the value produced by the
7314 DCI.CombineTo(N, ResVal);
7316 // Next, combine the load away, we give it a bogus result value but a real
7317 // chain result. The result value is dead because the bswap is dead.
7318 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
7320 // Return N so it doesn't get rechecked!
7321 return SDValue(N, 0);
7325 case PPCISD::VCMP: {
7326 // If a VCMPo node already exists with exactly the same operands as this
7327 // node, use its result instead of this node (VCMPo computes both a CR6 and
7328 // a normal output).
7330 if (!N->getOperand(0).hasOneUse() &&
7331 !N->getOperand(1).hasOneUse() &&
7332 !N->getOperand(2).hasOneUse()) {
7334 // Scan all of the users of the LHS, looking for VCMPo's that match.
7335 SDNode *VCMPoNode = 0;
7337 SDNode *LHSN = N->getOperand(0).getNode();
7338 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
7340 if (UI->getOpcode() == PPCISD::VCMPo &&
7341 UI->getOperand(1) == N->getOperand(1) &&
7342 UI->getOperand(2) == N->getOperand(2) &&
7343 UI->getOperand(0) == N->getOperand(0)) {
7348 // If there is no VCMPo node, or if the flag value has a single use, don't
7350 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
7353 // Look at the (necessarily single) use of the flag value. If it has a
7354 // chain, this transformation is more complex. Note that multiple things
7355 // could use the value result, which we should ignore.
7356 SDNode *FlagUser = 0;
7357 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
7358 FlagUser == 0; ++UI) {
7359 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
7361 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
7362 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
7369 // If the user is a MFOCRF instruction, we know this is safe.
7370 // Otherwise we give up for right now.
7371 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
7372 return SDValue(VCMPoNode, 0);
7377 // If this is a branch on an altivec predicate comparison, lower this so
7378 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
7379 // lowering is done pre-legalize, because the legalizer lowers the predicate
7380 // compare down to code that is difficult to reassemble.
7381 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
7382 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
7384 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
7385 // value. If so, pass-through the AND to get to the intrinsic.
7386 if (LHS.getOpcode() == ISD::AND &&
7387 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7388 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
7389 Intrinsic::ppc_is_decremented_ctr_nonzero &&
7390 isa<ConstantSDNode>(LHS.getOperand(1)) &&
7391 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
7393 LHS = LHS.getOperand(0);
7395 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7396 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
7397 Intrinsic::ppc_is_decremented_ctr_nonzero &&
7398 isa<ConstantSDNode>(RHS)) {
7399 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
7400 "Counter decrement comparison is not EQ or NE");
7402 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7403 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
7404 (CC == ISD::SETNE && !Val);
7406 // We now need to make the intrinsic dead (it cannot be instruction
7408 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
7409 assert(LHS.getNode()->hasOneUse() &&
7410 "Counter decrement has more than one use");
7412 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
7413 N->getOperand(0), N->getOperand(4));
7419 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7420 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
7421 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
7422 assert(isDot && "Can't compare against a vector result!");
7424 // If this is a comparison against something other than 0/1, then we know
7425 // that the condition is never/always true.
7426 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7427 if (Val != 0 && Val != 1) {
7428 if (CC == ISD::SETEQ) // Cond never true, remove branch.
7429 return N->getOperand(0);
7430 // Always !=, turn it into an unconditional branch.
7431 return DAG.getNode(ISD::BR, dl, MVT::Other,
7432 N->getOperand(0), N->getOperand(4));
7435 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
7437 // Create the PPCISD altivec 'dot' comparison node.
7439 LHS.getOperand(2), // LHS of compare
7440 LHS.getOperand(3), // RHS of compare
7441 DAG.getConstant(CompareOpc, MVT::i32)
7443 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
7444 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
7446 // Unpack the result based on how the target uses it.
7447 PPC::Predicate CompOpc;
7448 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
7449 default: // Can't happen, don't crash on invalid number though.
7450 case 0: // Branch on the value of the EQ bit of CR6.
7451 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
7453 case 1: // Branch on the inverted value of the EQ bit of CR6.
7454 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
7456 case 2: // Branch on the value of the LT bit of CR6.
7457 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
7459 case 3: // Branch on the inverted value of the LT bit of CR6.
7460 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
7464 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
7465 DAG.getConstant(CompOpc, MVT::i32),
7466 DAG.getRegister(PPC::CR6, MVT::i32),
7467 N->getOperand(4), CompNode.getValue(1));
7476 //===----------------------------------------------------------------------===//
7477 // Inline Assembly Support
7478 //===----------------------------------------------------------------------===//
7480 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7483 const SelectionDAG &DAG,
7484 unsigned Depth) const {
7485 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
7486 switch (Op.getOpcode()) {
7488 case PPCISD::LBRX: {
7489 // lhbrx is known to have the top bits cleared out.
7490 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
7491 KnownZero = 0xFFFF0000;
7494 case ISD::INTRINSIC_WO_CHAIN: {
7495 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
7497 case Intrinsic::ppc_altivec_vcmpbfp_p:
7498 case Intrinsic::ppc_altivec_vcmpeqfp_p:
7499 case Intrinsic::ppc_altivec_vcmpequb_p:
7500 case Intrinsic::ppc_altivec_vcmpequh_p:
7501 case Intrinsic::ppc_altivec_vcmpequw_p:
7502 case Intrinsic::ppc_altivec_vcmpgefp_p:
7503 case Intrinsic::ppc_altivec_vcmpgtfp_p:
7504 case Intrinsic::ppc_altivec_vcmpgtsb_p:
7505 case Intrinsic::ppc_altivec_vcmpgtsh_p:
7506 case Intrinsic::ppc_altivec_vcmpgtsw_p:
7507 case Intrinsic::ppc_altivec_vcmpgtub_p:
7508 case Intrinsic::ppc_altivec_vcmpgtuh_p:
7509 case Intrinsic::ppc_altivec_vcmpgtuw_p:
7510 KnownZero = ~1U; // All bits but the low one are known to be zero.
7518 /// getConstraintType - Given a constraint, return the type of
7519 /// constraint it is for this target.
7520 PPCTargetLowering::ConstraintType
7521 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
7522 if (Constraint.size() == 1) {
7523 switch (Constraint[0]) {
7530 return C_RegisterClass;
7532 // FIXME: While Z does indicate a memory constraint, it specifically
7533 // indicates an r+r address (used in conjunction with the 'y' modifier
7534 // in the replacement string). Currently, we're forcing the base
7535 // register to be r0 in the asm printer (which is interpreted as zero)
7536 // and forming the complete address in the second register. This is
7541 return TargetLowering::getConstraintType(Constraint);
7544 /// Examine constraint type and operand type and determine a weight value.
7545 /// This object must already have been set up with the operand type
7546 /// and the current alternative constraint selected.
7547 TargetLowering::ConstraintWeight
7548 PPCTargetLowering::getSingleConstraintMatchWeight(
7549 AsmOperandInfo &info, const char *constraint) const {
7550 ConstraintWeight weight = CW_Invalid;
7551 Value *CallOperandVal = info.CallOperandVal;
7552 // If we don't have a value, we can't do a match,
7553 // but allow it at the lowest weight.
7554 if (CallOperandVal == NULL)
7556 Type *type = CallOperandVal->getType();
7557 // Look at the constraint type.
7558 switch (*constraint) {
7560 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
7563 if (type->isIntegerTy())
7564 weight = CW_Register;
7567 if (type->isFloatTy())
7568 weight = CW_Register;
7571 if (type->isDoubleTy())
7572 weight = CW_Register;
7575 if (type->isVectorTy())
7576 weight = CW_Register;
7579 weight = CW_Register;
7588 std::pair<unsigned, const TargetRegisterClass*>
7589 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7591 if (Constraint.size() == 1) {
7592 // GCC RS6000 Constraint Letters
7593 switch (Constraint[0]) {
7595 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7596 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
7597 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
7599 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7600 return std::make_pair(0U, &PPC::G8RCRegClass);
7601 return std::make_pair(0U, &PPC::GPRCRegClass);
7603 if (VT == MVT::f32 || VT == MVT::i32)
7604 return std::make_pair(0U, &PPC::F4RCRegClass);
7605 if (VT == MVT::f64 || VT == MVT::i64)
7606 return std::make_pair(0U, &PPC::F8RCRegClass);
7609 return std::make_pair(0U, &PPC::VRRCRegClass);
7611 return std::make_pair(0U, &PPC::CRRCRegClass);
7615 std::pair<unsigned, const TargetRegisterClass*> R =
7616 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7618 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
7619 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
7620 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
7622 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
7623 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
7624 if (R.first && VT == MVT::i64 && PPCSubTarget.isPPC64() &&
7625 PPC::GPRCRegClass.contains(R.first)) {
7626 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
7627 return std::make_pair(TRI->getMatchingSuperReg(R.first,
7628 PPC::sub_32, &PPC::G8RCRegClass),
7629 &PPC::G8RCRegClass);
7636 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7637 /// vector. If it is invalid, don't add anything to Ops.
7638 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7639 std::string &Constraint,
7640 std::vector<SDValue>&Ops,
7641 SelectionDAG &DAG) const {
7642 SDValue Result(0,0);
7644 // Only support length 1 constraints.
7645 if (Constraint.length() > 1) return;
7647 char Letter = Constraint[0];
7658 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
7659 if (!CST) return; // Must be an immediate to match.
7660 unsigned Value = CST->getZExtValue();
7662 default: llvm_unreachable("Unknown constraint letter!");
7663 case 'I': // "I" is a signed 16-bit constant.
7664 if ((short)Value == (int)Value)
7665 Result = DAG.getTargetConstant(Value, Op.getValueType());
7667 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
7668 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
7669 if ((short)Value == 0)
7670 Result = DAG.getTargetConstant(Value, Op.getValueType());
7672 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
7673 if ((Value >> 16) == 0)
7674 Result = DAG.getTargetConstant(Value, Op.getValueType());
7676 case 'M': // "M" is a constant that is greater than 31.
7678 Result = DAG.getTargetConstant(Value, Op.getValueType());
7680 case 'N': // "N" is a positive constant that is an exact power of two.
7681 if ((int)Value > 0 && isPowerOf2_32(Value))
7682 Result = DAG.getTargetConstant(Value, Op.getValueType());
7684 case 'O': // "O" is the constant zero.
7686 Result = DAG.getTargetConstant(Value, Op.getValueType());
7688 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
7689 if ((short)-Value == (int)-Value)
7690 Result = DAG.getTargetConstant(Value, Op.getValueType());
7697 if (Result.getNode()) {
7698 Ops.push_back(Result);
7702 // Handle standard constraint letters.
7703 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7706 // isLegalAddressingMode - Return true if the addressing mode represented
7707 // by AM is legal for this target, for a load/store of the specified type.
7708 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
7710 // FIXME: PPC does not allow r+i addressing modes for vectors!
7712 // PPC allows a sign-extended 16-bit immediate field.
7713 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
7716 // No global is ever allowed as a base.
7720 // PPC only support r+r,
7722 case 0: // "r+i" or just "i", depending on HasBaseReg.
7725 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
7727 // Otherwise we have r+r or r+i.
7730 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
7732 // Allow 2*r as r+r.
7735 // No other scales are supported.
7742 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
7743 SelectionDAG &DAG) const {
7744 MachineFunction &MF = DAG.getMachineFunction();
7745 MachineFrameInfo *MFI = MF.getFrameInfo();
7746 MFI->setReturnAddressIsTaken(true);
7749 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7751 // Make sure the function does not optimize away the store of the RA to
7753 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
7754 FuncInfo->setLRStoreRequired();
7755 bool isPPC64 = PPCSubTarget.isPPC64();
7756 bool isDarwinABI = PPCSubTarget.isDarwinABI();
7759 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7762 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
7763 isPPC64? MVT::i64 : MVT::i32);
7764 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7765 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7767 MachinePointerInfo(), false, false, false, 0);
7770 // Just load the return address off the stack.
7771 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
7772 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7773 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
7776 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
7777 SelectionDAG &DAG) const {
7779 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7781 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
7782 bool isPPC64 = PtrVT == MVT::i64;
7784 MachineFunction &MF = DAG.getMachineFunction();
7785 MachineFrameInfo *MFI = MF.getFrameInfo();
7786 MFI->setFrameAddressIsTaken(true);
7788 // Naked functions never have a frame pointer, and so we use r1. For all
7789 // other functions, this decision must be delayed until during PEI.
7791 if (MF.getFunction()->getAttributes().hasAttribute(
7792 AttributeSet::FunctionIndex, Attribute::Naked))
7793 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
7795 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
7797 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
7800 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
7801 FrameAddr, MachinePointerInfo(), false, false,
7807 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7808 // The PowerPC target isn't yet aware of offsets.
7812 /// getOptimalMemOpType - Returns the target specific optimal type for load
7813 /// and store operations as a result of memset, memcpy, and memmove
7814 /// lowering. If DstAlign is zero that means it's safe to destination
7815 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
7816 /// means there isn't a need to check it against alignment requirement,
7817 /// probably because the source does not need to be loaded. If 'IsMemset' is
7818 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
7819 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
7820 /// source is constant so it does not need to be loaded.
7821 /// It returns EVT::Other if the type should be determined using generic
7822 /// target-independent logic.
7823 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
7824 unsigned DstAlign, unsigned SrcAlign,
7825 bool IsMemset, bool ZeroMemset,
7827 MachineFunction &MF) const {
7828 if (this->PPCSubTarget.isPPC64()) {
7835 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
7837 if (DisablePPCUnaligned)
7840 // PowerPC supports unaligned memory access for simple non-vector types.
7841 // Although accessing unaligned addresses is not as efficient as accessing
7842 // aligned addresses, it is generally more efficient than manual expansion,
7843 // and generally only traps for software emulation when crossing page
7849 if (VT.getSimpleVT().isVector())
7852 if (VT == MVT::ppcf128)
7861 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
7862 VT = VT.getScalarType();
7867 switch (VT.getSimpleVT().SimpleTy) {
7878 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
7879 if (DisableILPPref || PPCSubTarget.enableMachineScheduler())
7880 return TargetLowering::getSchedulingPreference(N);
7885 // Create a fast isel object.
7887 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
7888 const TargetLibraryInfo *LibInfo) const {
7889 return PPC::createFastISel(FuncInfo, LibInfo);