1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCTargetMachine.h"
16 #include "PPCPerfectShuffle.h"
17 #include "llvm/ADT/VectorExtras.h"
18 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Function.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Target/TargetOptions.h"
31 PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
32 : TargetLowering(TM) {
34 // Fold away setcc operations if possible.
35 setSetCCIsExpensive();
38 // Use _setjmp/_longjmp instead of setjmp/longjmp.
39 setUseUnderscoreSetJmpLongJmp(true);
41 // Set up the register classes.
42 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
43 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
44 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
46 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
47 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
49 // PowerPC has no intrinsics for these particular operations
50 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
51 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
52 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
54 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
55 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
56 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
58 // PowerPC has no SREM/UREM instructions
59 setOperationAction(ISD::SREM, MVT::i32, Expand);
60 setOperationAction(ISD::UREM, MVT::i32, Expand);
62 // We don't support sin/cos/sqrt/fmod
63 setOperationAction(ISD::FSIN , MVT::f64, Expand);
64 setOperationAction(ISD::FCOS , MVT::f64, Expand);
65 setOperationAction(ISD::FREM , MVT::f64, Expand);
66 setOperationAction(ISD::FSIN , MVT::f32, Expand);
67 setOperationAction(ISD::FCOS , MVT::f32, Expand);
68 setOperationAction(ISD::FREM , MVT::f32, Expand);
70 // If we're enabling GP optimizations, use hardware square root
71 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
72 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
73 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
76 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
77 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
79 // PowerPC does not have BSWAP, CTPOP or CTTZ
80 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
81 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
82 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
84 // PowerPC does not have ROTR
85 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
87 // PowerPC does not have Select
88 setOperationAction(ISD::SELECT, MVT::i32, Expand);
89 setOperationAction(ISD::SELECT, MVT::f32, Expand);
90 setOperationAction(ISD::SELECT, MVT::f64, Expand);
92 // PowerPC wants to turn select_cc of FP into fsel when possible.
93 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
94 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
96 // PowerPC wants to optimize integer setcc a bit
97 setOperationAction(ISD::SETCC, MVT::i32, Custom);
99 // PowerPC does not have BRCOND which requires SetCC
100 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
102 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
103 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
105 // PowerPC does not have [U|S]INT_TO_FP
106 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
109 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
110 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
112 // PowerPC does not have truncstore for i1.
113 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
115 // Support label based line numbers.
116 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
117 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
118 // FIXME - use subtarget debug flags
119 if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
120 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
122 // We want to legalize GlobalAddress and ConstantPool nodes into the
123 // appropriate instructions to materialize the address.
124 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
125 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
126 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
128 // RET must be custom lowered, to meet ABI requirements
129 setOperationAction(ISD::RET , MVT::Other, Custom);
131 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
132 setOperationAction(ISD::VASTART , MVT::Other, Custom);
134 // Use the default implementation.
135 setOperationAction(ISD::VAARG , MVT::Other, Expand);
136 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
137 setOperationAction(ISD::VAEND , MVT::Other, Expand);
138 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
139 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
140 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
142 // We want to custom lower some of our intrinsics.
143 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
145 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
146 // They also have instructions for converting between i64 and fp.
147 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
148 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
150 // FIXME: disable this lowered code. This generates 64-bit register values,
151 // and we don't model the fact that the top part is clobbered by calls. We
152 // need to flag these together so that the value isn't live across a call.
153 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
155 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
156 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
158 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
159 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
162 if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) {
163 // 64 bit PowerPC implementations can support i64 types directly
164 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
165 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
166 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
168 // 32 bit PowerPC wants to expand i64 shifts itself.
169 setOperationAction(ISD::SHL, MVT::i64, Custom);
170 setOperationAction(ISD::SRL, MVT::i64, Custom);
171 setOperationAction(ISD::SRA, MVT::i64, Custom);
174 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
175 // First set operation action for all vector types to expand. Then we
176 // will selectively turn on ones that can be effectively codegen'd.
177 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
178 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
179 // add/sub are legal for all supported vector VT's.
180 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
181 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
183 // We promote all shuffles to v16i8.
184 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
185 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
187 // We promote all non-typed operations to v4i32.
188 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
189 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
190 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
191 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
192 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
193 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
194 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
195 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
196 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
197 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
198 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
199 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
201 // No other operations are legal.
202 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
203 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
204 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
205 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
206 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
207 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
208 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
209 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
211 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
214 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
215 // with merges, splats, etc.
216 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
218 setOperationAction(ISD::AND , MVT::v4i32, Legal);
219 setOperationAction(ISD::OR , MVT::v4i32, Legal);
220 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
221 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
222 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
223 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
225 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
226 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
227 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
228 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
230 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
231 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
232 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
233 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
235 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
236 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
238 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
239 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
240 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
241 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
244 setSetCCResultContents(ZeroOrOneSetCCResult);
245 setStackPointerRegisterToSaveRestore(PPC::R1);
247 // We have target-specific dag combine patterns for the following nodes:
248 setTargetDAGCombine(ISD::SINT_TO_FP);
249 setTargetDAGCombine(ISD::STORE);
250 setTargetDAGCombine(ISD::BR_CC);
252 computeRegisterProperties();
255 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
258 case PPCISD::FSEL: return "PPCISD::FSEL";
259 case PPCISD::FCFID: return "PPCISD::FCFID";
260 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
261 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
262 case PPCISD::STFIWX: return "PPCISD::STFIWX";
263 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
264 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
265 case PPCISD::VPERM: return "PPCISD::VPERM";
266 case PPCISD::Hi: return "PPCISD::Hi";
267 case PPCISD::Lo: return "PPCISD::Lo";
268 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
269 case PPCISD::SRL: return "PPCISD::SRL";
270 case PPCISD::SRA: return "PPCISD::SRA";
271 case PPCISD::SHL: return "PPCISD::SHL";
272 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
273 case PPCISD::STD_32: return "PPCISD::STD_32";
274 case PPCISD::CALL: return "PPCISD::CALL";
275 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
276 case PPCISD::MFCR: return "PPCISD::MFCR";
277 case PPCISD::VCMP: return "PPCISD::VCMP";
278 case PPCISD::VCMPo: return "PPCISD::VCMPo";
279 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
283 //===----------------------------------------------------------------------===//
284 // Node matching predicates, for use by the tblgen matching code.
285 //===----------------------------------------------------------------------===//
287 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
288 static bool isFloatingPointZero(SDOperand Op) {
289 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
290 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
291 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
292 // Maybe this has already been legalized into the constant pool?
293 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
294 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
295 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
300 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
301 /// true if Op is undef or if it matches the specified value.
302 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
303 return Op.getOpcode() == ISD::UNDEF ||
304 cast<ConstantSDNode>(Op)->getValue() == Val;
307 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
308 /// VPKUHUM instruction.
309 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
311 for (unsigned i = 0; i != 16; ++i)
312 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
315 for (unsigned i = 0; i != 8; ++i)
316 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
317 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
323 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
324 /// VPKUWUM instruction.
325 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
327 for (unsigned i = 0; i != 16; i += 2)
328 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
329 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
332 for (unsigned i = 0; i != 8; i += 2)
333 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
334 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
335 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
336 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
342 /// isVMerge - Common function, used to match vmrg* shuffles.
344 static bool isVMerge(SDNode *N, unsigned UnitSize,
345 unsigned LHSStart, unsigned RHSStart) {
346 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
347 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
348 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
349 "Unsupported merge size!");
351 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
352 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
353 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
354 LHSStart+j+i*UnitSize) ||
355 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
356 RHSStart+j+i*UnitSize))
362 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
363 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
364 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
366 return isVMerge(N, UnitSize, 8, 24);
367 return isVMerge(N, UnitSize, 8, 8);
370 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
371 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
372 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
374 return isVMerge(N, UnitSize, 0, 16);
375 return isVMerge(N, UnitSize, 0, 0);
379 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
380 /// amount, otherwise return -1.
381 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
382 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
383 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
384 // Find the first non-undef value in the shuffle mask.
386 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
389 if (i == 16) return -1; // all undef.
391 // Otherwise, check to see if the rest of the elements are consequtively
392 // numbered from this value.
393 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
394 if (ShiftAmt < i) return -1;
398 // Check the rest of the elements to see if they are consequtive.
399 for (++i; i != 16; ++i)
400 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
403 // Check the rest of the elements to see if they are consequtive.
404 for (++i; i != 16; ++i)
405 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
412 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
413 /// specifies a splat of a single element that is suitable for input to
414 /// VSPLTB/VSPLTH/VSPLTW.
415 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
416 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
417 N->getNumOperands() == 16 &&
418 (EltSize == 1 || EltSize == 2 || EltSize == 4));
420 // This is a splat operation if each element of the permute is the same, and
421 // if the value doesn't reference the second vector.
422 unsigned ElementBase = 0;
423 SDOperand Elt = N->getOperand(0);
424 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
425 ElementBase = EltV->getValue();
427 return false; // FIXME: Handle UNDEF elements too!
429 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
432 // Check that they are consequtive.
433 for (unsigned i = 1; i != EltSize; ++i) {
434 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
435 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
439 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
440 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
441 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
442 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
443 "Invalid VECTOR_SHUFFLE mask!");
444 for (unsigned j = 0; j != EltSize; ++j)
445 if (N->getOperand(i+j) != N->getOperand(j))
452 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
453 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
454 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
455 assert(isSplatShuffleMask(N, EltSize));
456 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
459 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
460 /// by using a vspltis[bhw] instruction of the specified element size, return
461 /// the constant being splatted. The ByteSize field indicates the number of
462 /// bytes of each element [124] -> [bhw].
463 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
464 SDOperand OpVal(0, 0);
466 // If ByteSize of the splat is bigger than the element size of the
467 // build_vector, then we have a case where we are checking for a splat where
468 // multiple elements of the buildvector are folded together into a single
469 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
470 unsigned EltSize = 16/N->getNumOperands();
471 if (EltSize < ByteSize) {
472 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
473 SDOperand UniquedVals[4];
474 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
476 // See if all of the elements in the buildvector agree across.
477 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
478 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
479 // If the element isn't a constant, bail fully out.
480 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
483 if (UniquedVals[i&(Multiple-1)].Val == 0)
484 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
485 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
486 return SDOperand(); // no match.
489 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
490 // either constant or undef values that are identical for each chunk. See
491 // if these chunks can form into a larger vspltis*.
493 // Check to see if all of the leading entries are either 0 or -1. If
494 // neither, then this won't fit into the immediate field.
495 bool LeadingZero = true;
496 bool LeadingOnes = true;
497 for (unsigned i = 0; i != Multiple-1; ++i) {
498 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
500 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
501 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
503 // Finally, check the least significant entry.
505 if (UniquedVals[Multiple-1].Val == 0)
506 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
507 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
509 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
512 if (UniquedVals[Multiple-1].Val == 0)
513 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
514 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
515 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
516 return DAG.getTargetConstant(Val, MVT::i32);
522 // Check to see if this buildvec has a single non-undef value in its elements.
523 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
524 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
526 OpVal = N->getOperand(i);
527 else if (OpVal != N->getOperand(i))
531 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
533 unsigned ValSizeInBytes = 0;
535 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
536 Value = CN->getValue();
537 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
538 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
539 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
540 Value = FloatToBits(CN->getValue());
544 // If the splat value is larger than the element value, then we can never do
545 // this splat. The only case that we could fit the replicated bits into our
546 // immediate field for would be zero, and we prefer to use vxor for it.
547 if (ValSizeInBytes < ByteSize) return SDOperand();
549 // If the element value is larger than the splat value, cut it in half and
550 // check to see if the two halves are equal. Continue doing this until we
551 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
552 while (ValSizeInBytes > ByteSize) {
553 ValSizeInBytes >>= 1;
555 // If the top half equals the bottom half, we're still ok.
556 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
557 (Value & ((1 << (8*ValSizeInBytes))-1)))
561 // Properly sign extend the value.
562 int ShAmt = (4-ByteSize)*8;
563 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
565 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
566 if (MaskVal == 0) return SDOperand();
568 // Finally, if this value fits in a 5 bit sext field, return it
569 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
570 return DAG.getTargetConstant(MaskVal, MVT::i32);
574 //===----------------------------------------------------------------------===//
575 // LowerOperation implementation
576 //===----------------------------------------------------------------------===//
578 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
579 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
580 Constant *C = CP->get();
581 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32, CP->getAlignment());
582 SDOperand Zero = DAG.getConstant(0, MVT::i32);
584 const TargetMachine &TM = DAG.getTarget();
586 // If this is a non-darwin platform, we don't support non-static relo models
588 if (TM.getRelocationModel() == Reloc::Static ||
589 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
590 // Generate non-pic code that has direct accesses to the constant pool.
591 // The address of the global is just (hi(&g)+lo(&g)).
592 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
593 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
594 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
597 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
598 if (TM.getRelocationModel() == Reloc::PIC) {
599 // With PIC, the first instruction is actually "GR+hi(&G)".
600 Hi = DAG.getNode(ISD::ADD, MVT::i32,
601 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
604 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
605 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
609 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
610 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
611 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
612 SDOperand Zero = DAG.getConstant(0, MVT::i32);
614 const TargetMachine &TM = DAG.getTarget();
616 // If this is a non-darwin platform, we don't support non-static relo models
618 if (TM.getRelocationModel() == Reloc::Static ||
619 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
620 // Generate non-pic code that has direct accesses to the constant pool.
621 // The address of the global is just (hi(&g)+lo(&g)).
622 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, JTI, Zero);
623 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, JTI, Zero);
624 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
627 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, JTI, Zero);
628 if (TM.getRelocationModel() == Reloc::PIC) {
629 // With PIC, the first instruction is actually "GR+hi(&G)".
630 Hi = DAG.getNode(ISD::ADD, MVT::i32,
631 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
634 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, JTI, Zero);
635 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
639 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
640 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
641 GlobalValue *GV = GSDN->getGlobal();
642 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset());
643 SDOperand Zero = DAG.getConstant(0, MVT::i32);
645 const TargetMachine &TM = DAG.getTarget();
647 // If this is a non-darwin platform, we don't support non-static relo models
649 if (TM.getRelocationModel() == Reloc::Static ||
650 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
651 // Generate non-pic code that has direct accesses to globals.
652 // The address of the global is just (hi(&g)+lo(&g)).
653 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
654 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
655 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
658 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
659 if (TM.getRelocationModel() == Reloc::PIC) {
660 // With PIC, the first instruction is actually "GR+hi(&G)".
661 Hi = DAG.getNode(ISD::ADD, MVT::i32,
662 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
665 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
666 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
668 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() &&
669 (!GV->isExternal() || GV->hasNotBeenReadFromBytecode()))
672 // If the global is weak or external, we have to go through the lazy
674 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
677 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
678 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
680 // If we're comparing for equality to zero, expose the fact that this is
681 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
682 // fold the new nodes.
683 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
684 if (C->isNullValue() && CC == ISD::SETEQ) {
685 MVT::ValueType VT = Op.getOperand(0).getValueType();
686 SDOperand Zext = Op.getOperand(0);
689 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
691 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
692 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
693 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
694 DAG.getConstant(Log2b, MVT::i32));
695 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
697 // Leave comparisons against 0 and -1 alone for now, since they're usually
698 // optimized. FIXME: revisit this when we can custom lower all setcc
700 if (C->isAllOnesValue() || C->isNullValue())
704 // If we have an integer seteq/setne, turn it into a compare against zero
705 // by subtracting the rhs from the lhs, which is faster than setting a
706 // condition register, reading it back out, and masking the correct bit.
707 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
708 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
709 MVT::ValueType VT = Op.getValueType();
710 SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0),
712 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
717 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
718 unsigned VarArgsFrameIndex) {
719 // vastart just stores the address of the VarArgsFrameIndex slot into the
720 // memory location argument.
721 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
722 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
723 Op.getOperand(1), Op.getOperand(2));
726 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
728 switch(Op.getNumOperands()) {
730 assert(0 && "Do not know how to return this many arguments!");
733 return SDOperand(); // ret void is legal
735 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
737 if (MVT::isVector(ArgVT))
739 else if (MVT::isInteger(ArgVT))
742 assert(MVT::isFloatingPoint(ArgVT));
746 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
749 // If we haven't noted the R3/F1 are live out, do so now.
750 if (DAG.getMachineFunction().liveout_empty())
751 DAG.getMachineFunction().addLiveOut(ArgReg);
755 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2),
757 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
758 // If we haven't noted the R3+R4 are live out, do so now.
759 if (DAG.getMachineFunction().liveout_empty()) {
760 DAG.getMachineFunction().addLiveOut(PPC::R3);
761 DAG.getMachineFunction().addLiveOut(PPC::R4);
765 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
768 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
770 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
771 // Not FP? Not a fsel.
772 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
773 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
776 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
778 // Cannot handle SETEQ/SETNE.
779 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
781 MVT::ValueType ResVT = Op.getValueType();
782 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
783 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
784 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
786 // If the RHS of the comparison is a 0.0, we don't need to do the
787 // subtraction at all.
788 if (isFloatingPointZero(RHS))
790 default: break; // SETUO etc aren't handled by fsel.
793 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
796 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
797 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
798 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
801 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
804 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
805 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
806 return DAG.getNode(PPCISD::FSEL, ResVT,
807 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
812 default: break; // SETUO etc aren't handled by fsel.
815 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
816 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
817 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
818 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
821 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
822 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
823 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
824 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
827 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
828 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
829 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
830 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
833 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
834 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
835 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
836 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
841 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
842 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
843 SDOperand Src = Op.getOperand(0);
844 if (Src.getValueType() == MVT::f32)
845 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
848 switch (Op.getValueType()) {
849 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
851 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
854 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
858 // Convert the FP value to an int value through memory.
859 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
860 if (Op.getValueType() == MVT::i32)
861 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
865 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
866 if (Op.getOperand(0).getValueType() == MVT::i64) {
867 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
868 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
869 if (Op.getValueType() == MVT::f32)
870 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
874 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
875 "Unhandled SINT_TO_FP type in custom expander!");
876 // Since we only generate this in 64-bit mode, we can take advantage of
877 // 64-bit registers. In particular, sign extend the input value into the
878 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
879 // then lfd it and fcfid it.
880 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
881 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
882 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
884 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
887 // STD the extended value into the stack slot.
888 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
889 DAG.getEntryNode(), Ext64, FIdx,
890 DAG.getSrcValue(NULL));
891 // Load the value as a double.
892 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL));
894 // FCFID it and return it.
895 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
896 if (Op.getValueType() == MVT::f32)
897 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
901 static SDOperand LowerSHL(SDOperand Op, SelectionDAG &DAG) {
902 assert(Op.getValueType() == MVT::i64 &&
903 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
904 // The generic code does a fine job expanding shift by a constant.
905 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
907 // Otherwise, expand into a bunch of logical ops. Note that these ops
908 // depend on the PPC behavior for oversized shift amounts.
909 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
910 DAG.getConstant(0, MVT::i32));
911 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
912 DAG.getConstant(1, MVT::i32));
913 SDOperand Amt = Op.getOperand(1);
915 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
916 DAG.getConstant(32, MVT::i32), Amt);
917 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
918 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
919 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
920 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
921 DAG.getConstant(-32U, MVT::i32));
922 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
923 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
924 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
925 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
928 static SDOperand LowerSRL(SDOperand Op, SelectionDAG &DAG) {
929 assert(Op.getValueType() == MVT::i64 &&
930 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
931 // The generic code does a fine job expanding shift by a constant.
932 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
934 // Otherwise, expand into a bunch of logical ops. Note that these ops
935 // depend on the PPC behavior for oversized shift amounts.
936 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
937 DAG.getConstant(0, MVT::i32));
938 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
939 DAG.getConstant(1, MVT::i32));
940 SDOperand Amt = Op.getOperand(1);
942 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
943 DAG.getConstant(32, MVT::i32), Amt);
944 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
945 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
946 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
947 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
948 DAG.getConstant(-32U, MVT::i32));
949 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
950 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
951 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
952 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
955 static SDOperand LowerSRA(SDOperand Op, SelectionDAG &DAG) {
956 assert(Op.getValueType() == MVT::i64 &&
957 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
958 // The generic code does a fine job expanding shift by a constant.
959 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
961 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
962 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
963 DAG.getConstant(0, MVT::i32));
964 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
965 DAG.getConstant(1, MVT::i32));
966 SDOperand Amt = Op.getOperand(1);
968 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
969 DAG.getConstant(32, MVT::i32), Amt);
970 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
971 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
972 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
973 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
974 DAG.getConstant(-32U, MVT::i32));
975 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
976 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
977 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
978 Tmp4, Tmp6, ISD::SETLE);
979 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
982 //===----------------------------------------------------------------------===//
983 // Vector related lowering.
986 // If this is a vector of constants or undefs, get the bits. A bit in
987 // UndefBits is set if the corresponding element of the vector is an
988 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
989 // zero. Return true if this is not an array of constants, false if it is.
991 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
992 uint64_t UndefBits[2]) {
993 // Start with zero'd results.
994 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
996 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
997 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
998 SDOperand OpVal = BV->getOperand(i);
1000 unsigned PartNo = i >= e/2; // In the upper 128 bits?
1001 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
1003 uint64_t EltBits = 0;
1004 if (OpVal.getOpcode() == ISD::UNDEF) {
1005 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
1006 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
1008 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1009 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
1010 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1011 assert(CN->getValueType(0) == MVT::f32 &&
1012 "Only one legal FP vector type!");
1013 EltBits = FloatToBits(CN->getValue());
1015 // Nonconstant element.
1019 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
1022 //printf("%llx %llx %llx %llx\n",
1023 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
1027 // If this is a splat (repetition) of a value across the whole vector, return
1028 // the smallest size that splats it. For example, "0x01010101010101..." is a
1029 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1030 // SplatSize = 1 byte.
1031 static bool isConstantSplat(const uint64_t Bits128[2],
1032 const uint64_t Undef128[2],
1033 unsigned &SplatBits, unsigned &SplatUndef,
1034 unsigned &SplatSize) {
1036 // Don't let undefs prevent splats from matching. See if the top 64-bits are
1037 // the same as the lower 64-bits, ignoring undefs.
1038 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
1039 return false; // Can't be a splat if two pieces don't match.
1041 uint64_t Bits64 = Bits128[0] | Bits128[1];
1042 uint64_t Undef64 = Undef128[0] & Undef128[1];
1044 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
1046 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
1047 return false; // Can't be a splat if two pieces don't match.
1049 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
1050 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
1052 // If the top 16-bits are different than the lower 16-bits, ignoring
1053 // undefs, we have an i32 splat.
1054 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
1056 SplatUndef = Undef32;
1061 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
1062 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
1064 // If the top 8-bits are different than the lower 8-bits, ignoring
1065 // undefs, we have an i16 splat.
1066 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
1068 SplatUndef = Undef16;
1073 // Otherwise, we have an 8-bit splat.
1074 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
1075 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
1080 /// BuildSplatI - Build a canonical splati of Val with an element size of
1081 /// SplatSize. Cast the result to VT.
1082 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
1083 SelectionDAG &DAG) {
1084 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
1086 // Force vspltis[hw] -1 to vspltisb -1.
1087 if (Val == -1) SplatSize = 1;
1089 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
1090 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
1092 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
1094 // Build a canonical splat for this value.
1095 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT));
1096 std::vector<SDOperand> Ops(MVT::getVectorNumElements(CanonicalVT), Elt);
1097 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops);
1098 return DAG.getNode(ISD::BIT_CONVERT, VT, Res);
1101 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
1102 /// specified intrinsic ID.
1103 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
1105 MVT::ValueType DestVT = MVT::Other) {
1106 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
1107 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1108 DAG.getConstant(IID, MVT::i32), LHS, RHS);
1111 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
1112 /// specified intrinsic ID.
1113 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
1114 SDOperand Op2, SelectionDAG &DAG,
1115 MVT::ValueType DestVT = MVT::Other) {
1116 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
1117 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1118 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
1122 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
1123 /// amount. The result has the specified value type.
1124 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
1125 MVT::ValueType VT, SelectionDAG &DAG) {
1126 // Force LHS/RHS to be the right type.
1127 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
1128 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
1130 std::vector<SDOperand> Ops;
1131 for (unsigned i = 0; i != 16; ++i)
1132 Ops.push_back(DAG.getConstant(i+Amt, MVT::i32));
1133 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
1134 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
1135 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
1138 // If this is a case we can't handle, return null and let the default
1139 // expansion code take care of it. If we CAN select this case, and if it
1140 // selects to a single instruction, return Op. Otherwise, if we can codegen
1141 // this case more efficiently than a constant pool load, lower it to the
1142 // sequence of ops that should be used.
1143 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
1144 // If this is a vector of constants or undefs, get the bits. A bit in
1145 // UndefBits is set if the corresponding element of the vector is an
1146 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1148 uint64_t VectorBits[2];
1149 uint64_t UndefBits[2];
1150 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
1151 return SDOperand(); // Not a constant vector.
1153 // If this is a splat (repetition) of a value across the whole vector, return
1154 // the smallest size that splats it. For example, "0x01010101010101..." is a
1155 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1156 // SplatSize = 1 byte.
1157 unsigned SplatBits, SplatUndef, SplatSize;
1158 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
1159 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
1161 // First, handle single instruction cases.
1164 if (SplatBits == 0) {
1165 // Canonicalize all zero vectors to be v4i32.
1166 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
1167 SDOperand Z = DAG.getConstant(0, MVT::i32);
1168 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
1169 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
1174 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
1175 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
1176 if (SextVal >= -16 && SextVal <= 15)
1177 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
1180 // Two instruction sequences.
1182 // If this value is in the range [-32,30] and is even, use:
1183 // tmp = VSPLTI[bhw], result = add tmp, tmp
1184 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
1185 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
1186 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
1189 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
1190 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
1192 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
1193 // Make -1 and vspltisw -1:
1194 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
1196 // Make the VSLW intrinsic, computing 0x8000_0000.
1197 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
1200 // xor by OnesV to invert it.
1201 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
1202 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
1205 // Check to see if this is a wide variety of vsplti*, binop self cases.
1206 unsigned SplatBitSize = SplatSize*8;
1207 static const char SplatCsts[] = {
1208 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
1209 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
1211 for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){
1212 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
1213 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
1214 int i = SplatCsts[idx];
1216 // Figure out what shift amount will be used by altivec if shifted by i in
1218 unsigned TypeShiftAmt = i & (SplatBitSize-1);
1220 // vsplti + shl self.
1221 if (SextVal == (i << (int)TypeShiftAmt)) {
1222 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1223 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1224 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
1225 Intrinsic::ppc_altivec_vslw
1227 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1230 // vsplti + srl self.
1231 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
1232 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1233 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1234 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
1235 Intrinsic::ppc_altivec_vsrw
1237 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1240 // vsplti + sra self.
1241 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
1242 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1243 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1244 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
1245 Intrinsic::ppc_altivec_vsraw
1247 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1250 // vsplti + rol self.
1251 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
1252 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
1253 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1254 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1255 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
1256 Intrinsic::ppc_altivec_vrlw
1258 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1261 // t = vsplti c, result = vsldoi t, t, 1
1262 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
1263 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1264 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
1266 // t = vsplti c, result = vsldoi t, t, 2
1267 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
1268 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1269 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
1271 // t = vsplti c, result = vsldoi t, t, 3
1272 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
1273 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1274 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
1278 // Three instruction sequences.
1280 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
1281 if (SextVal >= 0 && SextVal <= 31) {
1282 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, Op.getValueType(),DAG);
1283 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
1284 return DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
1286 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
1287 if (SextVal >= -31 && SextVal <= 0) {
1288 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, Op.getValueType(),DAG);
1289 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
1290 return DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
1297 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
1298 /// the specified operations to build the shuffle.
1299 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
1300 SDOperand RHS, SelectionDAG &DAG) {
1301 unsigned OpNum = (PFEntry >> 26) & 0x0F;
1302 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
1303 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
1306 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
1318 if (OpNum == OP_COPY) {
1319 if (LHSID == (1*9+2)*9+3) return LHS;
1320 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
1324 SDOperand OpLHS, OpRHS;
1325 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
1326 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
1328 unsigned ShufIdxs[16];
1330 default: assert(0 && "Unknown i32 permute!");
1332 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
1333 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
1334 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
1335 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
1338 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
1339 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
1340 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
1341 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
1344 for (unsigned i = 0; i != 16; ++i)
1345 ShufIdxs[i] = (i&3)+0;
1348 for (unsigned i = 0; i != 16; ++i)
1349 ShufIdxs[i] = (i&3)+4;
1352 for (unsigned i = 0; i != 16; ++i)
1353 ShufIdxs[i] = (i&3)+8;
1356 for (unsigned i = 0; i != 16; ++i)
1357 ShufIdxs[i] = (i&3)+12;
1360 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
1362 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
1364 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
1366 std::vector<SDOperand> Ops;
1367 for (unsigned i = 0; i != 16; ++i)
1368 Ops.push_back(DAG.getConstant(ShufIdxs[i], MVT::i32));
1370 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
1371 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
1374 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
1375 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
1376 /// return the code it can be lowered into. Worst case, it can always be
1377 /// lowered into a vperm.
1378 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
1379 SDOperand V1 = Op.getOperand(0);
1380 SDOperand V2 = Op.getOperand(1);
1381 SDOperand PermMask = Op.getOperand(2);
1383 // Cases that are handled by instructions that take permute immediates
1384 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
1385 // selected by the instruction selector.
1386 if (V2.getOpcode() == ISD::UNDEF) {
1387 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
1388 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
1389 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
1390 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
1391 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
1392 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
1393 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
1394 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
1395 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
1396 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
1397 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
1398 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
1403 // Altivec has a variety of "shuffle immediates" that take two vector inputs
1404 // and produce a fixed permutation. If any of these match, do not lower to
1406 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
1407 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
1408 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
1409 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
1410 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
1411 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
1412 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
1413 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
1414 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
1417 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
1418 // perfect shuffle table to emit an optimal matching sequence.
1419 unsigned PFIndexes[4];
1420 bool isFourElementShuffle = true;
1421 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
1422 unsigned EltNo = 8; // Start out undef.
1423 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
1424 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
1425 continue; // Undef, ignore it.
1427 unsigned ByteSource =
1428 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
1429 if ((ByteSource & 3) != j) {
1430 isFourElementShuffle = false;
1435 EltNo = ByteSource/4;
1436 } else if (EltNo != ByteSource/4) {
1437 isFourElementShuffle = false;
1441 PFIndexes[i] = EltNo;
1444 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
1445 // perfect shuffle vector to determine if it is cost effective to do this as
1446 // discrete instructions, or whether we should use a vperm.
1447 if (isFourElementShuffle) {
1448 // Compute the index in the perfect shuffle table.
1449 unsigned PFTableIndex =
1450 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
1452 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
1453 unsigned Cost = (PFEntry >> 30);
1455 // Determining when to avoid vperm is tricky. Many things affect the cost
1456 // of vperm, particularly how many times the perm mask needs to be computed.
1457 // For example, if the perm mask can be hoisted out of a loop or is already
1458 // used (perhaps because there are multiple permutes with the same shuffle
1459 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
1460 // the loop requires an extra register.
1462 // As a compromise, we only emit discrete instructions if the shuffle can be
1463 // generated in 3 or fewer operations. When we have loop information
1464 // available, if this block is within a loop, we should avoid using vperm
1465 // for 3-operation perms and use a constant pool load instead.
1467 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
1470 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
1471 // vector that will get spilled to the constant pool.
1472 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
1474 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
1475 // that it is in input element units, not in bytes. Convert now.
1476 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
1477 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
1479 std::vector<SDOperand> ResultMask;
1480 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
1482 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
1485 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
1487 for (unsigned j = 0; j != BytesPerElement; ++j)
1488 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
1492 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask);
1493 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
1496 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
1497 /// altivec comparison. If it is, return true and fill in Opc/isDot with
1498 /// information about the intrinsic.
1499 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
1501 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
1504 switch (IntrinsicID) {
1505 default: return false;
1506 // Comparison predicates.
1507 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
1508 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
1509 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
1510 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
1511 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
1512 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
1513 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
1514 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
1515 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
1516 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
1517 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
1518 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
1519 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
1521 // Normal Comparisons.
1522 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
1523 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
1524 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
1525 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
1526 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
1527 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
1528 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
1529 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
1530 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
1531 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
1532 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
1533 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
1534 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
1539 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
1540 /// lower, do it, otherwise return null.
1541 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
1542 // If this is a lowered altivec predicate compare, CompareOpc is set to the
1543 // opcode number of the comparison.
1546 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
1547 return SDOperand(); // Don't custom lower most intrinsics.
1549 // If this is a non-dot comparison, make the VCMP node and we are done.
1551 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
1552 Op.getOperand(1), Op.getOperand(2),
1553 DAG.getConstant(CompareOpc, MVT::i32));
1554 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
1557 // Create the PPCISD altivec 'dot' comparison node.
1558 std::vector<SDOperand> Ops;
1559 std::vector<MVT::ValueType> VTs;
1560 Ops.push_back(Op.getOperand(2)); // LHS
1561 Ops.push_back(Op.getOperand(3)); // RHS
1562 Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32));
1563 VTs.push_back(Op.getOperand(2).getValueType());
1564 VTs.push_back(MVT::Flag);
1565 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops);
1567 // Now that we have the comparison, emit a copy from the CR to a GPR.
1568 // This is flagged to the above dot comparison.
1569 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
1570 DAG.getRegister(PPC::CR6, MVT::i32),
1571 CompNode.getValue(1));
1573 // Unpack the result based on how the target uses it.
1574 unsigned BitNo; // Bit # of CR6.
1575 bool InvertBit; // Invert result?
1576 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
1577 default: // Can't happen, don't crash on invalid number though.
1578 case 0: // Return the value of the EQ bit of CR6.
1579 BitNo = 0; InvertBit = false;
1581 case 1: // Return the inverted value of the EQ bit of CR6.
1582 BitNo = 0; InvertBit = true;
1584 case 2: // Return the value of the LT bit of CR6.
1585 BitNo = 2; InvertBit = false;
1587 case 3: // Return the inverted value of the LT bit of CR6.
1588 BitNo = 2; InvertBit = true;
1592 // Shift the bit into the low position.
1593 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
1594 DAG.getConstant(8-(3-BitNo), MVT::i32));
1596 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
1597 DAG.getConstant(1, MVT::i32));
1599 // If we are supposed to, toggle the bit.
1601 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
1602 DAG.getConstant(1, MVT::i32));
1606 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
1607 // Create a stack slot that is 16-byte aligned.
1608 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
1609 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
1610 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
1612 // Store the input value into Value#0 of the stack slot.
1613 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
1614 Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
1616 return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL));
1619 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
1620 if (Op.getValueType() == MVT::v4i32) {
1621 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1623 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
1624 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
1626 SDOperand RHSSwap = // = vrlw RHS, 16
1627 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
1629 // Shrinkify inputs to v8i16.
1630 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
1631 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
1632 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
1634 // Low parts multiplied together, generating 32-bit results (we ignore the
1636 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
1637 LHS, RHS, DAG, MVT::v4i32);
1639 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
1640 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
1641 // Shift the high parts up 16 bits.
1642 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
1643 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
1644 } else if (Op.getValueType() == MVT::v8i16) {
1645 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1647 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
1649 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
1650 LHS, RHS, Zero, DAG);
1651 } else if (Op.getValueType() == MVT::v16i8) {
1652 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1654 // Multiply the even 8-bit parts, producing 16-bit sums.
1655 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
1656 LHS, RHS, DAG, MVT::v8i16);
1657 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
1659 // Multiply the odd 8-bit parts, producing 16-bit sums.
1660 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
1661 LHS, RHS, DAG, MVT::v8i16);
1662 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
1664 // Merge the results together.
1665 std::vector<SDOperand> Ops;
1666 for (unsigned i = 0; i != 8; ++i) {
1667 Ops.push_back(DAG.getConstant(2*i+1, MVT::i8));
1668 Ops.push_back(DAG.getConstant(2*i+1+16, MVT::i8));
1671 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
1672 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
1674 assert(0 && "Unknown mul to lower!");
1679 /// LowerOperation - Provide custom lowering hooks for some operations.
1681 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1682 switch (Op.getOpcode()) {
1683 default: assert(0 && "Wasn't expecting to be able to lower this!");
1684 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1685 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
1686 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
1687 case ISD::SETCC: return LowerSETCC(Op, DAG);
1688 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1689 case ISD::RET: return LowerRET(Op, DAG);
1691 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1692 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1693 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
1695 // Lower 64-bit shifts.
1696 case ISD::SHL: return LowerSHL(Op, DAG);
1697 case ISD::SRL: return LowerSRL(Op, DAG);
1698 case ISD::SRA: return LowerSRA(Op, DAG);
1700 // Vector-related lowering.
1701 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
1702 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
1703 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1704 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
1705 case ISD::MUL: return LowerMUL(Op, DAG);
1710 //===----------------------------------------------------------------------===//
1711 // Other Lowering Code
1712 //===----------------------------------------------------------------------===//
1714 std::vector<SDOperand>
1715 PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
1717 // add beautiful description of PPC stack frame format, or at least some docs
1719 MachineFunction &MF = DAG.getMachineFunction();
1720 MachineFrameInfo *MFI = MF.getFrameInfo();
1721 MachineBasicBlock& BB = MF.front();
1722 SSARegMap *RegMap = MF.getSSARegMap();
1723 std::vector<SDOperand> ArgValues;
1725 unsigned ArgOffset = 24;
1726 unsigned GPR_remaining = 8;
1727 unsigned FPR_remaining = 13;
1728 unsigned GPR_idx = 0, FPR_idx = 0;
1729 static const unsigned GPR[] = {
1730 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1731 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1733 static const unsigned FPR[] = {
1734 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1735 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1738 // Add DAG nodes to load the arguments... On entry to a function on PPC,
1739 // the arguments start at offset 24, although they are likely to be passed
1741 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
1742 SDOperand newroot, argt;
1744 bool needsLoad = false;
1745 bool ArgLive = !I->use_empty();
1746 MVT::ValueType ObjectVT = getValueType(I->getType());
1749 default: assert(0 && "Unhandled argument type!");
1755 if (!ArgLive) break;
1756 if (GPR_remaining > 0) {
1757 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1758 MF.addLiveIn(GPR[GPR_idx], VReg);
1759 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
1760 if (ObjectVT != MVT::i32) {
1761 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
1763 argt = DAG.getNode(AssertOp, MVT::i32, argt,
1764 DAG.getValueType(ObjectVT));
1765 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
1773 if (!ArgLive) break;
1774 if (GPR_remaining > 0) {
1775 SDOperand argHi, argLo;
1776 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1777 MF.addLiveIn(GPR[GPR_idx], VReg);
1778 argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
1779 // If we have two or more remaining argument registers, then both halves
1780 // of the i64 can be sourced from there. Otherwise, the lower half will
1781 // have to come off the stack. This can happen when an i64 is preceded
1782 // by 28 bytes of arguments.
1783 if (GPR_remaining > 1) {
1784 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1785 MF.addLiveIn(GPR[GPR_idx+1], VReg);
1786 argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32);
1788 int FI = MFI->CreateFixedObject(4, ArgOffset+4);
1789 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
1790 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
1791 DAG.getSrcValue(NULL));
1793 // Build the outgoing arg thingy
1794 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
1802 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
1804 if (FPR_remaining > 0) {
1810 if (FPR_remaining > 0) {
1812 if (ObjectVT == MVT::f32)
1813 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
1815 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
1816 MF.addLiveIn(FPR[FPR_idx], VReg);
1817 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT);
1826 // We need to load the argument to a virtual register if we determined above
1827 // that we ran out of physical registers of the appropriate type
1829 unsigned SubregOffset = 0;
1830 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
1831 if (ObjectVT == MVT::i16) SubregOffset = 2;
1832 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
1833 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
1834 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
1835 DAG.getConstant(SubregOffset, MVT::i32));
1836 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
1837 DAG.getSrcValue(NULL));
1840 // Every 4 bytes of argument space consumes one of the GPRs available for
1841 // argument passing.
1842 if (GPR_remaining > 0) {
1843 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
1844 GPR_remaining -= delta;
1847 ArgOffset += ObjSize;
1849 DAG.setRoot(newroot.getValue(1));
1851 ArgValues.push_back(argt);
1854 // If the function takes variable number of arguments, make a frame index for
1855 // the start of the first vararg value... for expansion of llvm.va_start.
1857 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1858 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
1859 // If this function is vararg, store any remaining integer argument regs
1860 // to their spots on the stack so that they may be loaded by deferencing the
1861 // result of va_next.
1862 std::vector<SDOperand> MemOps;
1863 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
1864 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1865 MF.addLiveIn(GPR[GPR_idx], VReg);
1866 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
1867 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
1868 Val, FIN, DAG.getSrcValue(NULL));
1869 MemOps.push_back(Store);
1870 // Increment the address by four for the next argument to store
1871 SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
1872 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
1874 if (!MemOps.empty()) {
1875 MemOps.push_back(DAG.getRoot());
1876 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
1883 std::pair<SDOperand, SDOperand>
1884 PPCTargetLowering::LowerCallTo(SDOperand Chain,
1885 const Type *RetTy, bool isVarArg,
1886 unsigned CallingConv, bool isTailCall,
1887 SDOperand Callee, ArgListTy &Args,
1888 SelectionDAG &DAG) {
1889 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1890 // SelectExpr to use to put the arguments in the appropriate registers.
1891 std::vector<SDOperand> args_to_use;
1893 // Count how many bytes are to be pushed on the stack, including the linkage
1894 // area, and parameter passing area.
1895 unsigned NumBytes = 24;
1898 Chain = DAG.getCALLSEQ_START(Chain,
1899 DAG.getConstant(NumBytes, getPointerTy()));
1901 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1902 switch (getValueType(Args[i].second)) {
1903 default: assert(0 && "Unknown value type!");
1918 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
1919 // plus 32 bytes of argument space in case any called code gets funky on us.
1920 // (Required by ABI to support var arg)
1921 if (NumBytes < 56) NumBytes = 56;
1923 // Adjust the stack pointer for the new arguments...
1924 // These operations are automatically eliminated by the prolog/epilog pass
1925 Chain = DAG.getCALLSEQ_START(Chain,
1926 DAG.getConstant(NumBytes, getPointerTy()));
1928 // Set up a copy of the stack pointer for use loading and storing any
1929 // arguments that may not fit in the registers available for argument
1931 SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
1933 // Figure out which arguments are going to go in registers, and which in
1934 // memory. Also, if this is a vararg function, floating point operations
1935 // must be stored to our stack, and loaded into integer regs as well, if
1936 // any integer regs are available for argument passing.
1937 unsigned ArgOffset = 24;
1938 unsigned GPR_remaining = 8;
1939 unsigned FPR_remaining = 13;
1941 std::vector<SDOperand> MemOps;
1942 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1943 // PtrOff will be used to store the current argument to the stack if a
1944 // register cannot be found for it.
1945 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1946 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
1947 MVT::ValueType ArgVT = getValueType(Args[i].second);
1950 default: assert(0 && "Unexpected ValueType for argument!");
1954 // Promote the integer to 32 bits. If the input type is signed use a
1955 // sign extend, otherwise use a zero extend.
1956 if (Args[i].second->isSigned())
1957 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
1959 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
1962 if (GPR_remaining > 0) {
1963 args_to_use.push_back(Args[i].first);
1966 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1967 Args[i].first, PtrOff,
1968 DAG.getSrcValue(NULL)));
1973 // If we have one free GPR left, we can place the upper half of the i64
1974 // in it, and store the other half to the stack. If we have two or more
1975 // free GPRs, then we can pass both halves of the i64 in registers.
1976 if (GPR_remaining > 0) {
1977 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
1978 Args[i].first, DAG.getConstant(1, MVT::i32));
1979 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
1980 Args[i].first, DAG.getConstant(0, MVT::i32));
1981 args_to_use.push_back(Hi);
1983 if (GPR_remaining > 0) {
1984 args_to_use.push_back(Lo);
1987 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
1988 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
1989 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1990 Lo, PtrOff, DAG.getSrcValue(NULL)));
1993 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1994 Args[i].first, PtrOff,
1995 DAG.getSrcValue(NULL)));
2001 if (FPR_remaining > 0) {
2002 args_to_use.push_back(Args[i].first);
2005 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
2006 Args[i].first, PtrOff,
2007 DAG.getSrcValue(NULL));
2008 MemOps.push_back(Store);
2009 // Float varargs are always shadowed in available integer registers
2010 if (GPR_remaining > 0) {
2011 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
2012 DAG.getSrcValue(NULL));
2013 MemOps.push_back(Load.getValue(1));
2014 args_to_use.push_back(Load);
2017 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
2018 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
2019 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
2020 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
2021 DAG.getSrcValue(NULL));
2022 MemOps.push_back(Load.getValue(1));
2023 args_to_use.push_back(Load);
2027 // If we have any FPRs remaining, we may also have GPRs remaining.
2028 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
2030 if (GPR_remaining > 0) {
2031 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
2034 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
2035 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
2040 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
2041 Args[i].first, PtrOff,
2042 DAG.getSrcValue(NULL)));
2044 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
2048 if (!MemOps.empty())
2049 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
2052 std::vector<MVT::ValueType> RetVals;
2053 MVT::ValueType RetTyVT = getValueType(RetTy);
2054 MVT::ValueType ActualRetTyVT = RetTyVT;
2055 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16)
2056 ActualRetTyVT = MVT::i32; // Promote result to i32.
2058 if (RetTyVT == MVT::i64) {
2059 RetVals.push_back(MVT::i32);
2060 RetVals.push_back(MVT::i32);
2061 } else if (RetTyVT != MVT::isVoid) {
2062 RetVals.push_back(ActualRetTyVT);
2064 RetVals.push_back(MVT::Other);
2066 // If the callee is a GlobalAddress node (quite common, every direct call is)
2067 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
2068 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2069 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
2071 std::vector<SDOperand> Ops;
2072 Ops.push_back(Chain);
2073 Ops.push_back(Callee);
2074 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
2075 SDOperand TheCall = DAG.getNode(PPCISD::CALL, RetVals, Ops);
2076 Chain = TheCall.getValue(TheCall.Val->getNumValues()-1);
2077 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
2078 DAG.getConstant(NumBytes, getPointerTy()));
2079 SDOperand RetVal = TheCall;
2081 // If the result is a small value, add a note so that we keep track of the
2082 // information about whether it is sign or zero extended.
2083 if (RetTyVT != ActualRetTyVT) {
2084 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
2085 MVT::i32, RetVal, DAG.getValueType(RetTyVT));
2086 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
2087 } else if (RetTyVT == MVT::i64) {
2088 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, RetVal, RetVal.getValue(1));
2091 return std::make_pair(RetVal, Chain);
2095 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2096 MachineBasicBlock *BB) {
2097 assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
2098 MI->getOpcode() == PPC::SELECT_CC_F4 ||
2099 MI->getOpcode() == PPC::SELECT_CC_F8 ||
2100 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
2101 "Unexpected instr type to insert");
2103 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2104 // control-flow pattern. The incoming instruction knows the destination vreg
2105 // to set, the condition code register to branch on, the true/false values to
2106 // select between, and a branch opcode to use.
2107 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2108 ilist<MachineBasicBlock>::iterator It = BB;
2114 // cmpTY ccX, r1, r2
2116 // fallthrough --> copy0MBB
2117 MachineBasicBlock *thisMBB = BB;
2118 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2119 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2120 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
2121 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
2122 MachineFunction *F = BB->getParent();
2123 F->getBasicBlockList().insert(It, copy0MBB);
2124 F->getBasicBlockList().insert(It, sinkMBB);
2125 // Update machine-CFG edges by first adding all successors of the current
2126 // block to the new block which will contain the Phi node for the select.
2127 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2128 e = BB->succ_end(); i != e; ++i)
2129 sinkMBB->addSuccessor(*i);
2130 // Next, remove all successors of the current block, and add the true
2131 // and fallthrough blocks as its successors.
2132 while(!BB->succ_empty())
2133 BB->removeSuccessor(BB->succ_begin());
2134 BB->addSuccessor(copy0MBB);
2135 BB->addSuccessor(sinkMBB);
2138 // %FalseValue = ...
2139 // # fallthrough to sinkMBB
2142 // Update machine-CFG edges
2143 BB->addSuccessor(sinkMBB);
2146 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2149 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
2150 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
2151 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2153 delete MI; // The pseudo instruction is gone now.
2157 //===----------------------------------------------------------------------===//
2158 // Target Optimization Hooks
2159 //===----------------------------------------------------------------------===//
2161 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
2162 DAGCombinerInfo &DCI) const {
2163 TargetMachine &TM = getTargetMachine();
2164 SelectionDAG &DAG = DCI.DAG;
2165 switch (N->getOpcode()) {
2167 case ISD::SINT_TO_FP:
2168 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
2169 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
2170 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
2171 // We allow the src/dst to be either f32/f64, but the intermediate
2172 // type must be i64.
2173 if (N->getOperand(0).getValueType() == MVT::i64) {
2174 SDOperand Val = N->getOperand(0).getOperand(0);
2175 if (Val.getValueType() == MVT::f32) {
2176 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2177 DCI.AddToWorklist(Val.Val);
2180 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
2181 DCI.AddToWorklist(Val.Val);
2182 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
2183 DCI.AddToWorklist(Val.Val);
2184 if (N->getValueType(0) == MVT::f32) {
2185 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
2186 DCI.AddToWorklist(Val.Val);
2189 } else if (N->getOperand(0).getValueType() == MVT::i32) {
2190 // If the intermediate type is i32, we can avoid the load/store here
2197 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
2198 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
2199 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
2200 N->getOperand(1).getValueType() == MVT::i32) {
2201 SDOperand Val = N->getOperand(1).getOperand(0);
2202 if (Val.getValueType() == MVT::f32) {
2203 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2204 DCI.AddToWorklist(Val.Val);
2206 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
2207 DCI.AddToWorklist(Val.Val);
2209 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
2210 N->getOperand(2), N->getOperand(3));
2211 DCI.AddToWorklist(Val.Val);
2215 case PPCISD::VCMP: {
2216 // If a VCMPo node already exists with exactly the same operands as this
2217 // node, use its result instead of this node (VCMPo computes both a CR6 and
2218 // a normal output).
2220 if (!N->getOperand(0).hasOneUse() &&
2221 !N->getOperand(1).hasOneUse() &&
2222 !N->getOperand(2).hasOneUse()) {
2224 // Scan all of the users of the LHS, looking for VCMPo's that match.
2225 SDNode *VCMPoNode = 0;
2227 SDNode *LHSN = N->getOperand(0).Val;
2228 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
2230 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
2231 (*UI)->getOperand(1) == N->getOperand(1) &&
2232 (*UI)->getOperand(2) == N->getOperand(2) &&
2233 (*UI)->getOperand(0) == N->getOperand(0)) {
2238 // If there is no VCMPo node, or if the flag value has a single use, don't
2240 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
2243 // Look at the (necessarily single) use of the flag value. If it has a
2244 // chain, this transformation is more complex. Note that multiple things
2245 // could use the value result, which we should ignore.
2246 SDNode *FlagUser = 0;
2247 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
2248 FlagUser == 0; ++UI) {
2249 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
2251 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2252 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
2259 // If the user is a MFCR instruction, we know this is safe. Otherwise we
2260 // give up for right now.
2261 if (FlagUser->getOpcode() == PPCISD::MFCR)
2262 return SDOperand(VCMPoNode, 0);
2267 // If this is a branch on an altivec predicate comparison, lower this so
2268 // that we don't have to do a MFCR: instead, branch directly on CR6. This
2269 // lowering is done pre-legalize, because the legalizer lowers the predicate
2270 // compare down to code that is difficult to reassemble.
2271 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
2272 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
2276 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2277 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
2278 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
2279 assert(isDot && "Can't compare against a vector result!");
2281 // If this is a comparison against something other than 0/1, then we know
2282 // that the condition is never/always true.
2283 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
2284 if (Val != 0 && Val != 1) {
2285 if (CC == ISD::SETEQ) // Cond never true, remove branch.
2286 return N->getOperand(0);
2287 // Always !=, turn it into an unconditional branch.
2288 return DAG.getNode(ISD::BR, MVT::Other,
2289 N->getOperand(0), N->getOperand(4));
2292 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
2294 // Create the PPCISD altivec 'dot' comparison node.
2295 std::vector<SDOperand> Ops;
2296 std::vector<MVT::ValueType> VTs;
2297 Ops.push_back(LHS.getOperand(2)); // LHS of compare
2298 Ops.push_back(LHS.getOperand(3)); // RHS of compare
2299 Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32));
2300 VTs.push_back(LHS.getOperand(2).getValueType());
2301 VTs.push_back(MVT::Flag);
2302 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops);
2304 // Unpack the result based on how the target uses it.
2306 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
2307 default: // Can't happen, don't crash on invalid number though.
2308 case 0: // Branch on the value of the EQ bit of CR6.
2309 CompOpc = BranchOnWhenPredTrue ? PPC::BEQ : PPC::BNE;
2311 case 1: // Branch on the inverted value of the EQ bit of CR6.
2312 CompOpc = BranchOnWhenPredTrue ? PPC::BNE : PPC::BEQ;
2314 case 2: // Branch on the value of the LT bit of CR6.
2315 CompOpc = BranchOnWhenPredTrue ? PPC::BLT : PPC::BGE;
2317 case 3: // Branch on the inverted value of the LT bit of CR6.
2318 CompOpc = BranchOnWhenPredTrue ? PPC::BGE : PPC::BLT;
2322 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
2323 DAG.getRegister(PPC::CR6, MVT::i32),
2324 DAG.getConstant(CompOpc, MVT::i32),
2325 N->getOperand(4), CompNode.getValue(1));
2334 //===----------------------------------------------------------------------===//
2335 // Inline Assembly Support
2336 //===----------------------------------------------------------------------===//
2338 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
2340 uint64_t &KnownZero,
2342 unsigned Depth) const {
2345 switch (Op.getOpcode()) {
2347 case ISD::INTRINSIC_WO_CHAIN: {
2348 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
2350 case Intrinsic::ppc_altivec_vcmpbfp_p:
2351 case Intrinsic::ppc_altivec_vcmpeqfp_p:
2352 case Intrinsic::ppc_altivec_vcmpequb_p:
2353 case Intrinsic::ppc_altivec_vcmpequh_p:
2354 case Intrinsic::ppc_altivec_vcmpequw_p:
2355 case Intrinsic::ppc_altivec_vcmpgefp_p:
2356 case Intrinsic::ppc_altivec_vcmpgtfp_p:
2357 case Intrinsic::ppc_altivec_vcmpgtsb_p:
2358 case Intrinsic::ppc_altivec_vcmpgtsh_p:
2359 case Intrinsic::ppc_altivec_vcmpgtsw_p:
2360 case Intrinsic::ppc_altivec_vcmpgtub_p:
2361 case Intrinsic::ppc_altivec_vcmpgtuh_p:
2362 case Intrinsic::ppc_altivec_vcmpgtuw_p:
2363 KnownZero = ~1U; // All bits but the low one are known to be zero.
2371 /// getConstraintType - Given a constraint letter, return the type of
2372 /// constraint it is for this target.
2373 PPCTargetLowering::ConstraintType
2374 PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
2375 switch (ConstraintLetter) {
2382 return C_RegisterClass;
2384 return TargetLowering::getConstraintType(ConstraintLetter);
2388 std::vector<unsigned> PPCTargetLowering::
2389 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2390 MVT::ValueType VT) const {
2391 if (Constraint.size() == 1) {
2392 switch (Constraint[0]) { // GCC RS6000 Constraint Letters
2393 default: break; // Unknown constriant letter
2395 return make_vector<unsigned>(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 ,
2396 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
2397 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
2398 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
2399 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
2400 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
2401 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
2402 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
2405 return make_vector<unsigned>(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 ,
2406 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
2407 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
2408 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
2409 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
2410 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
2411 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
2412 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
2415 return make_vector<unsigned>(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 ,
2416 PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 ,
2417 PPC::F8 , PPC::F9 , PPC::F10, PPC::F11,
2418 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
2419 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
2420 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
2421 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
2422 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
2425 return make_vector<unsigned>(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 ,
2426 PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
2427 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11,
2428 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
2429 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
2430 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
2431 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
2432 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
2435 return make_vector<unsigned>(PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
2436 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7,
2441 return std::vector<unsigned>();
2444 // isOperandValidForConstraint
2445 bool PPCTargetLowering::
2446 isOperandValidForConstraint(SDOperand Op, char Letter) {
2457 if (!isa<ConstantSDNode>(Op)) return false; // Must be an immediate.
2458 unsigned Value = cast<ConstantSDNode>(Op)->getValue();
2460 default: assert(0 && "Unknown constraint letter!");
2461 case 'I': // "I" is a signed 16-bit constant.
2462 return (short)Value == (int)Value;
2463 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
2464 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
2465 return (short)Value == 0;
2466 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
2467 return (Value >> 16) == 0;
2468 case 'M': // "M" is a constant that is greater than 31.
2470 case 'N': // "N" is a positive constant that is an exact power of two.
2471 return (int)Value > 0 && isPowerOf2_32(Value);
2472 case 'O': // "O" is the constant zero.
2474 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
2475 return (short)-Value == (int)-Value;
2481 // Handle standard constraint letters.
2482 return TargetLowering::isOperandValidForConstraint(Op, Letter);
2485 /// isLegalAddressImmediate - Return true if the integer value can be used
2486 /// as the offset of the target addressing mode.
2487 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const {
2488 // PPC allows a sign-extended 16-bit immediate field.
2489 return (V > -(1 << 16) && V < (1 << 16)-1);