1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetOptions.h"
40 static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
41 CCValAssign::LocInfo &LocInfo,
42 ISD::ArgFlagsTy &ArgFlags,
44 static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
46 CCValAssign::LocInfo &LocInfo,
47 ISD::ArgFlagsTy &ArgFlags,
49 static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
51 CCValAssign::LocInfo &LocInfo,
52 ISD::ArgFlagsTy &ArgFlags,
55 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
56 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
58 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
59 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
61 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
62 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
64 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
65 if (TM.getSubtargetImpl()->isDarwin())
66 return new TargetLoweringObjectFileMachO();
68 if (TM.getSubtargetImpl()->isSVR4ABI())
69 return new PPC64LinuxTargetObjectFile();
71 return new TargetLoweringObjectFileELF();
74 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
75 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
76 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
77 PPCRegInfo = TM.getRegisterInfo();
78 PPCII = TM.getInstrInfo();
82 // Use _setjmp/_longjmp instead of setjmp/longjmp.
83 setUseUnderscoreSetJmp(true);
84 setUseUnderscoreLongJmp(true);
86 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
87 // arguments are at least 4/8 bytes aligned.
88 bool isPPC64 = Subtarget->isPPC64();
89 setMinStackArgumentAlignment(isPPC64 ? 8:4);
91 // Set up the register classes.
92 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
93 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
94 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
96 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
97 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
98 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
100 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
102 // PowerPC has pre-inc load and store's.
103 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
104 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
105 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
106 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
107 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
108 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
109 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
110 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
111 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
112 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
114 // This is used in the ppcf128->int sequence. Note it has different semantics
115 // from FP_ROUND: that rounds to nearest, this rounds to zero.
116 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
118 // We do not currently implement these libm ops for PowerPC.
119 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
120 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
121 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
122 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
123 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
124 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
126 // PowerPC has no SREM/UREM instructions
127 setOperationAction(ISD::SREM, MVT::i32, Expand);
128 setOperationAction(ISD::UREM, MVT::i32, Expand);
129 setOperationAction(ISD::SREM, MVT::i64, Expand);
130 setOperationAction(ISD::UREM, MVT::i64, Expand);
132 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
133 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
134 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
135 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
136 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
137 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
138 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
139 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
140 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
142 // We don't support sin/cos/sqrt/fmod/pow
143 setOperationAction(ISD::FSIN , MVT::f64, Expand);
144 setOperationAction(ISD::FCOS , MVT::f64, Expand);
145 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
146 setOperationAction(ISD::FREM , MVT::f64, Expand);
147 setOperationAction(ISD::FPOW , MVT::f64, Expand);
148 setOperationAction(ISD::FMA , MVT::f64, Legal);
149 setOperationAction(ISD::FSIN , MVT::f32, Expand);
150 setOperationAction(ISD::FCOS , MVT::f32, Expand);
151 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
152 setOperationAction(ISD::FREM , MVT::f32, Expand);
153 setOperationAction(ISD::FPOW , MVT::f32, Expand);
154 setOperationAction(ISD::FMA , MVT::f32, Legal);
156 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
158 // If we're enabling GP optimizations, use hardware square root
159 if (!Subtarget->hasFSQRT() &&
160 !(TM.Options.UnsafeFPMath &&
161 Subtarget->hasFRSQRTE() && Subtarget->hasFRE()))
162 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
164 if (!Subtarget->hasFSQRT() &&
165 !(TM.Options.UnsafeFPMath &&
166 Subtarget->hasFRSQRTES() && Subtarget->hasFRES()))
167 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
169 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
170 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
172 if (Subtarget->hasFPRND()) {
173 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
174 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
175 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
177 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
178 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
179 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
181 // frin does not implement "ties to even." Thus, this is safe only in
183 if (TM.Options.UnsafeFPMath) {
184 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
185 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
187 // These need to set FE_INEXACT, and use a custom inserter.
188 setOperationAction(ISD::FRINT, MVT::f64, Legal);
189 setOperationAction(ISD::FRINT, MVT::f32, Legal);
193 // PowerPC does not have BSWAP, CTPOP or CTTZ
194 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
195 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
196 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
197 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
198 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
199 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
200 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
201 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
203 if (Subtarget->hasPOPCNTD()) {
204 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
205 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
207 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
208 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
211 // PowerPC does not have ROTR
212 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
213 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
215 // PowerPC does not have Select
216 setOperationAction(ISD::SELECT, MVT::i32, Expand);
217 setOperationAction(ISD::SELECT, MVT::i64, Expand);
218 setOperationAction(ISD::SELECT, MVT::f32, Expand);
219 setOperationAction(ISD::SELECT, MVT::f64, Expand);
221 // PowerPC wants to turn select_cc of FP into fsel when possible.
222 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
223 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
225 // PowerPC wants to optimize integer setcc a bit
226 setOperationAction(ISD::SETCC, MVT::i32, Custom);
228 // PowerPC does not have BRCOND which requires SetCC
229 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
231 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
233 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
234 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
236 // PowerPC does not have [U|S]INT_TO_FP
237 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
238 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
240 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
241 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
242 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
243 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
245 // We cannot sextinreg(i1). Expand to shifts.
246 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
248 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
249 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
250 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
251 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
253 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
254 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
255 // support continuation, user-level threading, and etc.. As a result, no
256 // other SjLj exception interfaces are implemented and please don't build
257 // your own exception handling based on them.
258 // LLVM/Clang supports zero-cost DWARF exception handling.
259 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
260 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
262 // We want to legalize GlobalAddress and ConstantPool nodes into the
263 // appropriate instructions to materialize the address.
264 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
265 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
266 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
267 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
268 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
269 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
270 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
271 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
272 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
273 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
276 setOperationAction(ISD::TRAP, MVT::Other, Legal);
278 // TRAMPOLINE is custom lowered.
279 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
280 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
282 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
283 setOperationAction(ISD::VASTART , MVT::Other, Custom);
285 if (Subtarget->isSVR4ABI()) {
287 // VAARG always uses double-word chunks, so promote anything smaller.
288 setOperationAction(ISD::VAARG, MVT::i1, Promote);
289 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
290 setOperationAction(ISD::VAARG, MVT::i8, Promote);
291 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
292 setOperationAction(ISD::VAARG, MVT::i16, Promote);
293 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
294 setOperationAction(ISD::VAARG, MVT::i32, Promote);
295 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
296 setOperationAction(ISD::VAARG, MVT::Other, Expand);
298 // VAARG is custom lowered with the 32-bit SVR4 ABI.
299 setOperationAction(ISD::VAARG, MVT::Other, Custom);
300 setOperationAction(ISD::VAARG, MVT::i64, Custom);
303 setOperationAction(ISD::VAARG, MVT::Other, Expand);
305 // Use the default implementation.
306 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
307 setOperationAction(ISD::VAEND , MVT::Other, Expand);
308 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
309 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
310 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
311 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
313 // We want to custom lower some of our intrinsics.
314 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
316 // Comparisons that require checking two conditions.
317 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
318 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
319 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
320 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
321 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
322 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
323 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
324 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
325 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
326 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
327 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
328 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
330 if (Subtarget->has64BitSupport()) {
331 // They also have instructions for converting between i64 and fp.
332 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
333 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
334 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
335 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
336 // This is just the low 32 bits of a (signed) fp->i64 conversion.
337 // We cannot do this with Promote because i64 is not a legal type.
338 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
340 if (PPCSubTarget.hasLFIWAX() || Subtarget->isPPC64())
341 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
343 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
344 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
347 // With the instructions enabled under FPCVT, we can do everything.
348 if (PPCSubTarget.hasFPCVT()) {
349 if (Subtarget->has64BitSupport()) {
350 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
351 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
352 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
353 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
356 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
357 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
358 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
359 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
362 if (Subtarget->use64BitRegs()) {
363 // 64-bit PowerPC implementations can support i64 types directly
364 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
365 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
366 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
367 // 64-bit PowerPC wants to expand i128 shifts itself.
368 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
369 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
370 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
372 // 32-bit PowerPC wants to expand i64 shifts itself.
373 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
374 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
375 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
378 if (Subtarget->hasAltivec()) {
379 // First set operation action for all vector types to expand. Then we
380 // will selectively turn on ones that can be effectively codegen'd.
381 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
382 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
383 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
385 // add/sub are legal for all supported vector VT's.
386 setOperationAction(ISD::ADD , VT, Legal);
387 setOperationAction(ISD::SUB , VT, Legal);
389 // We promote all shuffles to v16i8.
390 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
391 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
393 // We promote all non-typed operations to v4i32.
394 setOperationAction(ISD::AND , VT, Promote);
395 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
396 setOperationAction(ISD::OR , VT, Promote);
397 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
398 setOperationAction(ISD::XOR , VT, Promote);
399 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
400 setOperationAction(ISD::LOAD , VT, Promote);
401 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
402 setOperationAction(ISD::SELECT, VT, Promote);
403 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
404 setOperationAction(ISD::STORE, VT, Promote);
405 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
407 // No other operations are legal.
408 setOperationAction(ISD::MUL , VT, Expand);
409 setOperationAction(ISD::SDIV, VT, Expand);
410 setOperationAction(ISD::SREM, VT, Expand);
411 setOperationAction(ISD::UDIV, VT, Expand);
412 setOperationAction(ISD::UREM, VT, Expand);
413 setOperationAction(ISD::FDIV, VT, Expand);
414 setOperationAction(ISD::FNEG, VT, Expand);
415 setOperationAction(ISD::FSQRT, VT, Expand);
416 setOperationAction(ISD::FLOG, VT, Expand);
417 setOperationAction(ISD::FLOG10, VT, Expand);
418 setOperationAction(ISD::FLOG2, VT, Expand);
419 setOperationAction(ISD::FEXP, VT, Expand);
420 setOperationAction(ISD::FEXP2, VT, Expand);
421 setOperationAction(ISD::FSIN, VT, Expand);
422 setOperationAction(ISD::FCOS, VT, Expand);
423 setOperationAction(ISD::FABS, VT, Expand);
424 setOperationAction(ISD::FPOWI, VT, Expand);
425 setOperationAction(ISD::FFLOOR, VT, Expand);
426 setOperationAction(ISD::FCEIL, VT, Expand);
427 setOperationAction(ISD::FTRUNC, VT, Expand);
428 setOperationAction(ISD::FRINT, VT, Expand);
429 setOperationAction(ISD::FNEARBYINT, VT, Expand);
430 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
431 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
432 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
433 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
434 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
435 setOperationAction(ISD::UDIVREM, VT, Expand);
436 setOperationAction(ISD::SDIVREM, VT, Expand);
437 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
438 setOperationAction(ISD::FPOW, VT, Expand);
439 setOperationAction(ISD::CTPOP, VT, Expand);
440 setOperationAction(ISD::CTLZ, VT, Expand);
441 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
442 setOperationAction(ISD::CTTZ, VT, Expand);
443 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
444 setOperationAction(ISD::VSELECT, VT, Expand);
445 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
447 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
448 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
449 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
450 setTruncStoreAction(VT, InnerVT, Expand);
452 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
453 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
454 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
457 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
458 // with merges, splats, etc.
459 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
461 setOperationAction(ISD::AND , MVT::v4i32, Legal);
462 setOperationAction(ISD::OR , MVT::v4i32, Legal);
463 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
464 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
465 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
466 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
467 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
468 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
469 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
470 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
471 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
472 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
473 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
474 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
476 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
477 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
478 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
479 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
481 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
482 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
484 if (TM.Options.UnsafeFPMath) {
485 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
486 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
489 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
490 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
491 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
493 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
494 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
496 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
497 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
498 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
499 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
501 // Altivec does not contain unordered floating-point compare instructions
502 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
503 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
504 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
505 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
506 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
507 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
510 if (Subtarget->has64BitSupport()) {
511 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
512 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
515 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
516 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
517 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
518 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
520 setBooleanContents(ZeroOrOneBooleanContent);
521 // Altivec instructions set fields to all zeros or all ones.
522 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
525 setStackPointerRegisterToSaveRestore(PPC::X1);
526 setExceptionPointerRegister(PPC::X3);
527 setExceptionSelectorRegister(PPC::X4);
529 setStackPointerRegisterToSaveRestore(PPC::R1);
530 setExceptionPointerRegister(PPC::R3);
531 setExceptionSelectorRegister(PPC::R4);
534 // We have target-specific dag combine patterns for the following nodes:
535 setTargetDAGCombine(ISD::SINT_TO_FP);
536 setTargetDAGCombine(ISD::STORE);
537 setTargetDAGCombine(ISD::BR_CC);
538 setTargetDAGCombine(ISD::BSWAP);
540 // Use reciprocal estimates.
541 if (TM.Options.UnsafeFPMath) {
542 setTargetDAGCombine(ISD::FDIV);
543 setTargetDAGCombine(ISD::FSQRT);
546 // Darwin long double math library functions have $LDBL128 appended.
547 if (Subtarget->isDarwin()) {
548 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
549 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
550 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
551 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
552 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
553 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
554 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
555 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
556 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
557 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
560 setMinFunctionAlignment(2);
561 if (PPCSubTarget.isDarwin())
562 setPrefFunctionAlignment(4);
564 if (isPPC64 && Subtarget->isJITCodeModel())
565 // Temporary workaround for the inability of PPC64 JIT to handle jump
567 setSupportJumpTables(false);
569 setInsertFencesForAtomic(true);
571 setSchedulingPreference(Sched::Hybrid);
573 computeRegisterProperties();
575 // The Freescale cores does better with aggressive inlining of memcpy and
576 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
577 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
578 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
579 MaxStoresPerMemset = 32;
580 MaxStoresPerMemsetOptSize = 16;
581 MaxStoresPerMemcpy = 32;
582 MaxStoresPerMemcpyOptSize = 8;
583 MaxStoresPerMemmove = 32;
584 MaxStoresPerMemmoveOptSize = 8;
586 setPrefFunctionAlignment(4);
590 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
591 /// function arguments in the caller parameter area.
592 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
593 const TargetMachine &TM = getTargetMachine();
594 // Darwin passes everything on 4 byte boundary.
595 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
598 // 16byte and wider vectors are passed on 16byte boundary.
599 if (VectorType *VTy = dyn_cast<VectorType>(Ty))
600 if (VTy->getBitWidth() >= 128)
603 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
604 if (PPCSubTarget.isPPC64())
610 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
613 case PPCISD::FSEL: return "PPCISD::FSEL";
614 case PPCISD::FCFID: return "PPCISD::FCFID";
615 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
616 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
617 case PPCISD::FRE: return "PPCISD::FRE";
618 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
619 case PPCISD::STFIWX: return "PPCISD::STFIWX";
620 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
621 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
622 case PPCISD::VPERM: return "PPCISD::VPERM";
623 case PPCISD::Hi: return "PPCISD::Hi";
624 case PPCISD::Lo: return "PPCISD::Lo";
625 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
626 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
627 case PPCISD::LOAD: return "PPCISD::LOAD";
628 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
629 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
630 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
631 case PPCISD::SRL: return "PPCISD::SRL";
632 case PPCISD::SRA: return "PPCISD::SRA";
633 case PPCISD::SHL: return "PPCISD::SHL";
634 case PPCISD::CALL: return "PPCISD::CALL";
635 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
636 case PPCISD::MTCTR: return "PPCISD::MTCTR";
637 case PPCISD::BCTRL: return "PPCISD::BCTRL";
638 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
639 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
640 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
641 case PPCISD::MFCR: return "PPCISD::MFCR";
642 case PPCISD::VCMP: return "PPCISD::VCMP";
643 case PPCISD::VCMPo: return "PPCISD::VCMPo";
644 case PPCISD::LBRX: return "PPCISD::LBRX";
645 case PPCISD::STBRX: return "PPCISD::STBRX";
646 case PPCISD::LARX: return "PPCISD::LARX";
647 case PPCISD::STCX: return "PPCISD::STCX";
648 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
649 case PPCISD::MFFS: return "PPCISD::MFFS";
650 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
651 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
652 case PPCISD::CR6SET: return "PPCISD::CR6SET";
653 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
654 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
655 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
656 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
657 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
658 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
659 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
660 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
661 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
662 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
663 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
664 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
665 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
666 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
667 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
668 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
672 EVT PPCTargetLowering::getSetCCResultType(EVT VT) const {
675 return VT.changeVectorElementTypeToInteger();
678 //===----------------------------------------------------------------------===//
679 // Node matching predicates, for use by the tblgen matching code.
680 //===----------------------------------------------------------------------===//
682 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
683 static bool isFloatingPointZero(SDValue Op) {
684 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
685 return CFP->getValueAPF().isZero();
686 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
687 // Maybe this has already been legalized into the constant pool?
688 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
689 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
690 return CFP->getValueAPF().isZero();
695 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
696 /// true if Op is undef or if it matches the specified value.
697 static bool isConstantOrUndef(int Op, int Val) {
698 return Op < 0 || Op == Val;
701 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
702 /// VPKUHUM instruction.
703 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
705 for (unsigned i = 0; i != 16; ++i)
706 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
709 for (unsigned i = 0; i != 8; ++i)
710 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
711 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
717 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
718 /// VPKUWUM instruction.
719 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
721 for (unsigned i = 0; i != 16; i += 2)
722 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
723 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
726 for (unsigned i = 0; i != 8; i += 2)
727 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
728 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
729 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
730 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
736 /// isVMerge - Common function, used to match vmrg* shuffles.
738 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
739 unsigned LHSStart, unsigned RHSStart) {
740 assert(N->getValueType(0) == MVT::v16i8 &&
741 "PPC only supports shuffles by bytes!");
742 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
743 "Unsupported merge size!");
745 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
746 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
747 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
748 LHSStart+j+i*UnitSize) ||
749 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
750 RHSStart+j+i*UnitSize))
756 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
757 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
758 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
761 return isVMerge(N, UnitSize, 8, 24);
762 return isVMerge(N, UnitSize, 8, 8);
765 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
766 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
767 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
770 return isVMerge(N, UnitSize, 0, 16);
771 return isVMerge(N, UnitSize, 0, 0);
775 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
776 /// amount, otherwise return -1.
777 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
778 assert(N->getValueType(0) == MVT::v16i8 &&
779 "PPC only supports shuffles by bytes!");
781 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
783 // Find the first non-undef value in the shuffle mask.
785 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
788 if (i == 16) return -1; // all undef.
790 // Otherwise, check to see if the rest of the elements are consecutively
791 // numbered from this value.
792 unsigned ShiftAmt = SVOp->getMaskElt(i);
793 if (ShiftAmt < i) return -1;
797 // Check the rest of the elements to see if they are consecutive.
798 for (++i; i != 16; ++i)
799 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
802 // Check the rest of the elements to see if they are consecutive.
803 for (++i; i != 16; ++i)
804 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
810 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
811 /// specifies a splat of a single element that is suitable for input to
812 /// VSPLTB/VSPLTH/VSPLTW.
813 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
814 assert(N->getValueType(0) == MVT::v16i8 &&
815 (EltSize == 1 || EltSize == 2 || EltSize == 4));
817 // This is a splat operation if each element of the permute is the same, and
818 // if the value doesn't reference the second vector.
819 unsigned ElementBase = N->getMaskElt(0);
821 // FIXME: Handle UNDEF elements too!
822 if (ElementBase >= 16)
825 // Check that the indices are consecutive, in the case of a multi-byte element
826 // splatted with a v16i8 mask.
827 for (unsigned i = 1; i != EltSize; ++i)
828 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
831 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
832 if (N->getMaskElt(i) < 0) continue;
833 for (unsigned j = 0; j != EltSize; ++j)
834 if (N->getMaskElt(i+j) != N->getMaskElt(j))
840 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
842 bool PPC::isAllNegativeZeroVector(SDNode *N) {
843 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
845 APInt APVal, APUndef;
849 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
850 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
851 return CFP->getValueAPF().isNegZero();
856 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
857 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
858 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
859 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
860 assert(isSplatShuffleMask(SVOp, EltSize));
861 return SVOp->getMaskElt(0) / EltSize;
864 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
865 /// by using a vspltis[bhw] instruction of the specified element size, return
866 /// the constant being splatted. The ByteSize field indicates the number of
867 /// bytes of each element [124] -> [bhw].
868 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
871 // If ByteSize of the splat is bigger than the element size of the
872 // build_vector, then we have a case where we are checking for a splat where
873 // multiple elements of the buildvector are folded together into a single
874 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
875 unsigned EltSize = 16/N->getNumOperands();
876 if (EltSize < ByteSize) {
877 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
878 SDValue UniquedVals[4];
879 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
881 // See if all of the elements in the buildvector agree across.
882 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
883 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
884 // If the element isn't a constant, bail fully out.
885 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
888 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
889 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
890 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
891 return SDValue(); // no match.
894 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
895 // either constant or undef values that are identical for each chunk. See
896 // if these chunks can form into a larger vspltis*.
898 // Check to see if all of the leading entries are either 0 or -1. If
899 // neither, then this won't fit into the immediate field.
900 bool LeadingZero = true;
901 bool LeadingOnes = true;
902 for (unsigned i = 0; i != Multiple-1; ++i) {
903 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
905 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
906 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
908 // Finally, check the least significant entry.
910 if (UniquedVals[Multiple-1].getNode() == 0)
911 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
912 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
914 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
917 if (UniquedVals[Multiple-1].getNode() == 0)
918 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
919 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
920 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
921 return DAG.getTargetConstant(Val, MVT::i32);
927 // Check to see if this buildvec has a single non-undef value in its elements.
928 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
929 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
930 if (OpVal.getNode() == 0)
931 OpVal = N->getOperand(i);
932 else if (OpVal != N->getOperand(i))
936 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
938 unsigned ValSizeInBytes = EltSize;
940 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
941 Value = CN->getZExtValue();
942 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
943 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
944 Value = FloatToBits(CN->getValueAPF().convertToFloat());
947 // If the splat value is larger than the element value, then we can never do
948 // this splat. The only case that we could fit the replicated bits into our
949 // immediate field for would be zero, and we prefer to use vxor for it.
950 if (ValSizeInBytes < ByteSize) return SDValue();
952 // If the element value is larger than the splat value, cut it in half and
953 // check to see if the two halves are equal. Continue doing this until we
954 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
955 while (ValSizeInBytes > ByteSize) {
956 ValSizeInBytes >>= 1;
958 // If the top half equals the bottom half, we're still ok.
959 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
960 (Value & ((1 << (8*ValSizeInBytes))-1)))
964 // Properly sign extend the value.
965 int MaskVal = SignExtend32(Value, ByteSize * 8);
967 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
968 if (MaskVal == 0) return SDValue();
970 // Finally, if this value fits in a 5 bit sext field, return it
971 if (SignExtend32<5>(MaskVal) == MaskVal)
972 return DAG.getTargetConstant(MaskVal, MVT::i32);
976 //===----------------------------------------------------------------------===//
977 // Addressing Mode Selection
978 //===----------------------------------------------------------------------===//
980 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
981 /// or 64-bit immediate, and if the value can be accurately represented as a
982 /// sign extension from a 16-bit value. If so, this returns true and the
984 static bool isIntS16Immediate(SDNode *N, short &Imm) {
985 if (N->getOpcode() != ISD::Constant)
988 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
989 if (N->getValueType(0) == MVT::i32)
990 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
992 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
994 static bool isIntS16Immediate(SDValue Op, short &Imm) {
995 return isIntS16Immediate(Op.getNode(), Imm);
999 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1000 /// can be represented as an indexed [r+r] operation. Returns false if it
1001 /// can be more efficiently represented with [r+imm].
1002 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1004 SelectionDAG &DAG) const {
1006 if (N.getOpcode() == ISD::ADD) {
1007 if (isIntS16Immediate(N.getOperand(1), imm))
1008 return false; // r+i
1009 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1010 return false; // r+i
1012 Base = N.getOperand(0);
1013 Index = N.getOperand(1);
1015 } else if (N.getOpcode() == ISD::OR) {
1016 if (isIntS16Immediate(N.getOperand(1), imm))
1017 return false; // r+i can fold it if we can.
1019 // If this is an or of disjoint bitfields, we can codegen this as an add
1020 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1022 APInt LHSKnownZero, LHSKnownOne;
1023 APInt RHSKnownZero, RHSKnownOne;
1024 DAG.ComputeMaskedBits(N.getOperand(0),
1025 LHSKnownZero, LHSKnownOne);
1027 if (LHSKnownZero.getBoolValue()) {
1028 DAG.ComputeMaskedBits(N.getOperand(1),
1029 RHSKnownZero, RHSKnownOne);
1030 // If all of the bits are known zero on the LHS or RHS, the add won't
1032 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1033 Base = N.getOperand(0);
1034 Index = N.getOperand(1);
1043 /// Returns true if the address N can be represented by a base register plus
1044 /// a signed 16-bit displacement [r+imm], and if it is not better
1045 /// represented as reg+reg.
1046 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1048 SelectionDAG &DAG) const {
1049 // FIXME dl should come from parent load or store, not from address
1050 DebugLoc dl = N.getDebugLoc();
1051 // If this can be more profitably realized as r+r, fail.
1052 if (SelectAddressRegReg(N, Disp, Base, DAG))
1055 if (N.getOpcode() == ISD::ADD) {
1057 if (isIntS16Immediate(N.getOperand(1), imm)) {
1058 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
1059 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1060 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1062 Base = N.getOperand(0);
1064 return true; // [r+i]
1065 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1066 // Match LOAD (ADD (X, Lo(G))).
1067 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1068 && "Cannot handle constant offsets yet!");
1069 Disp = N.getOperand(1).getOperand(0); // The global address.
1070 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1071 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1072 Disp.getOpcode() == ISD::TargetConstantPool ||
1073 Disp.getOpcode() == ISD::TargetJumpTable);
1074 Base = N.getOperand(0);
1075 return true; // [&g+r]
1077 } else if (N.getOpcode() == ISD::OR) {
1079 if (isIntS16Immediate(N.getOperand(1), imm)) {
1080 // If this is an or of disjoint bitfields, we can codegen this as an add
1081 // (for better address arithmetic) if the LHS and RHS of the OR are
1082 // provably disjoint.
1083 APInt LHSKnownZero, LHSKnownOne;
1084 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1086 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1087 // If all of the bits are known zero on the LHS or RHS, the add won't
1089 Base = N.getOperand(0);
1090 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
1094 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1095 // Loading from a constant address.
1097 // If this address fits entirely in a 16-bit sext immediate field, codegen
1100 if (isIntS16Immediate(CN, Imm)) {
1101 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1102 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1103 CN->getValueType(0));
1107 // Handle 32-bit sext immediates with LIS + addr mode.
1108 if (CN->getValueType(0) == MVT::i32 ||
1109 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1110 int Addr = (int)CN->getZExtValue();
1112 // Otherwise, break this down into an LIS + disp.
1113 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1115 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1116 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1117 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1122 Disp = DAG.getTargetConstant(0, getPointerTy());
1123 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1124 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1127 return true; // [r+0]
1130 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1131 /// represented as an indexed [r+r] operation.
1132 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1134 SelectionDAG &DAG) const {
1135 // Check to see if we can easily represent this as an [r+r] address. This
1136 // will fail if it thinks that the address is more profitably represented as
1137 // reg+imm, e.g. where imm = 0.
1138 if (SelectAddressRegReg(N, Base, Index, DAG))
1141 // If the operand is an addition, always emit this as [r+r], since this is
1142 // better (for code size, and execution, as the memop does the add for free)
1143 // than emitting an explicit add.
1144 if (N.getOpcode() == ISD::ADD) {
1145 Base = N.getOperand(0);
1146 Index = N.getOperand(1);
1150 // Otherwise, do it the hard way, using R0 as the base register.
1151 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1157 /// SelectAddressRegImmShift - Returns true if the address N can be
1158 /// represented by a base register plus a signed 14-bit displacement
1159 /// [r+imm*4]. Suitable for use by STD and friends.
1160 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
1162 SelectionDAG &DAG) const {
1163 // FIXME dl should come from the parent load or store, not the address
1164 DebugLoc dl = N.getDebugLoc();
1165 // If this can be more profitably realized as r+r, fail.
1166 if (SelectAddressRegReg(N, Disp, Base, DAG))
1169 if (N.getOpcode() == ISD::ADD) {
1171 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1172 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1173 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1174 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1176 Base = N.getOperand(0);
1178 return true; // [r+i]
1179 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1180 // Match LOAD (ADD (X, Lo(G))).
1181 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1182 && "Cannot handle constant offsets yet!");
1183 Disp = N.getOperand(1).getOperand(0); // The global address.
1184 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1185 Disp.getOpcode() == ISD::TargetConstantPool ||
1186 Disp.getOpcode() == ISD::TargetJumpTable);
1187 Base = N.getOperand(0);
1188 return true; // [&g+r]
1190 } else if (N.getOpcode() == ISD::OR) {
1192 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1193 // If this is an or of disjoint bitfields, we can codegen this as an add
1194 // (for better address arithmetic) if the LHS and RHS of the OR are
1195 // provably disjoint.
1196 APInt LHSKnownZero, LHSKnownOne;
1197 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1198 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1199 // If all of the bits are known zero on the LHS or RHS, the add won't
1201 Base = N.getOperand(0);
1202 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1206 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1207 // Loading from a constant address. Verify low two bits are clear.
1208 if ((CN->getZExtValue() & 3) == 0) {
1209 // If this address fits entirely in a 14-bit sext immediate field, codegen
1212 if (isIntS16Immediate(CN, Imm)) {
1213 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1214 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1215 CN->getValueType(0));
1219 // Fold the low-part of 32-bit absolute addresses into addr mode.
1220 if (CN->getValueType(0) == MVT::i32 ||
1221 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1222 int Addr = (int)CN->getZExtValue();
1224 // Otherwise, break this down into an LIS + disp.
1225 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1226 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1227 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1228 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1234 Disp = DAG.getTargetConstant(0, getPointerTy());
1235 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1236 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1239 return true; // [r+0]
1243 /// getPreIndexedAddressParts - returns true by value, base pointer and
1244 /// offset pointer and addressing mode by reference if the node's address
1245 /// can be legally represented as pre-indexed load / store address.
1246 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1248 ISD::MemIndexedMode &AM,
1249 SelectionDAG &DAG) const {
1250 if (DisablePPCPreinc) return false;
1256 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1257 Ptr = LD->getBasePtr();
1258 VT = LD->getMemoryVT();
1259 Alignment = LD->getAlignment();
1260 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1261 Ptr = ST->getBasePtr();
1262 VT = ST->getMemoryVT();
1263 Alignment = ST->getAlignment();
1268 // PowerPC doesn't have preinc load/store instructions for vectors.
1272 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1274 // Common code will reject creating a pre-inc form if the base pointer
1275 // is a frame index, or if N is a store and the base pointer is either
1276 // the same as or a predecessor of the value being stored. Check for
1277 // those situations here, and try with swapped Base/Offset instead.
1280 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1283 SDValue Val = cast<StoreSDNode>(N)->getValue();
1284 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1289 std::swap(Base, Offset);
1295 // LDU/STU use reg+imm*4, others use reg+imm.
1296 if (VT != MVT::i64) {
1298 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1301 // LDU/STU need an address with at least 4-byte alignment.
1306 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1310 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1311 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1312 // sext i32 to i64 when addr mode is r+i.
1313 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1314 LD->getExtensionType() == ISD::SEXTLOAD &&
1315 isa<ConstantSDNode>(Offset))
1323 //===----------------------------------------------------------------------===//
1324 // LowerOperation implementation
1325 //===----------------------------------------------------------------------===//
1327 /// GetLabelAccessInfo - Return true if we should reference labels using a
1328 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1329 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1330 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1331 HiOpFlags = PPCII::MO_HA16;
1332 LoOpFlags = PPCII::MO_LO16;
1334 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1335 // non-darwin platform. We don't support PIC on other platforms yet.
1336 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1337 TM.getSubtarget<PPCSubtarget>().isDarwin();
1339 HiOpFlags |= PPCII::MO_PIC_FLAG;
1340 LoOpFlags |= PPCII::MO_PIC_FLAG;
1343 // If this is a reference to a global value that requires a non-lazy-ptr, make
1344 // sure that instruction lowering adds it.
1345 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1346 HiOpFlags |= PPCII::MO_NLP_FLAG;
1347 LoOpFlags |= PPCII::MO_NLP_FLAG;
1349 if (GV->hasHiddenVisibility()) {
1350 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1351 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1358 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1359 SelectionDAG &DAG) {
1360 EVT PtrVT = HiPart.getValueType();
1361 SDValue Zero = DAG.getConstant(0, PtrVT);
1362 DebugLoc DL = HiPart.getDebugLoc();
1364 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1365 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1367 // With PIC, the first instruction is actually "GR+hi(&G)".
1369 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1370 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1372 // Generate non-pic code that has direct accesses to the constant pool.
1373 // The address of the global is just (hi(&g)+lo(&g)).
1374 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1377 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1378 SelectionDAG &DAG) const {
1379 EVT PtrVT = Op.getValueType();
1380 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1381 const Constant *C = CP->getConstVal();
1383 // 64-bit SVR4 ABI code is always position-independent.
1384 // The actual address of the GlobalValue is stored in the TOC.
1385 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1386 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1387 return DAG.getNode(PPCISD::TOC_ENTRY, CP->getDebugLoc(), MVT::i64, GA,
1388 DAG.getRegister(PPC::X2, MVT::i64));
1391 unsigned MOHiFlag, MOLoFlag;
1392 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1394 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1396 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1397 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1400 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1401 EVT PtrVT = Op.getValueType();
1402 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1404 // 64-bit SVR4 ABI code is always position-independent.
1405 // The actual address of the GlobalValue is stored in the TOC.
1406 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1407 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1408 return DAG.getNode(PPCISD::TOC_ENTRY, JT->getDebugLoc(), MVT::i64, GA,
1409 DAG.getRegister(PPC::X2, MVT::i64));
1412 unsigned MOHiFlag, MOLoFlag;
1413 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1414 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1415 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1416 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1419 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1420 SelectionDAG &DAG) const {
1421 EVT PtrVT = Op.getValueType();
1423 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1425 unsigned MOHiFlag, MOLoFlag;
1426 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1427 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1428 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1429 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1432 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1433 SelectionDAG &DAG) const {
1435 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1436 DebugLoc dl = GA->getDebugLoc();
1437 const GlobalValue *GV = GA->getGlobal();
1438 EVT PtrVT = getPointerTy();
1439 bool is64bit = PPCSubTarget.isPPC64();
1441 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1443 if (Model == TLSModel::LocalExec) {
1444 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1445 PPCII::MO_TPREL16_HA);
1446 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1447 PPCII::MO_TPREL16_LO);
1448 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1449 is64bit ? MVT::i64 : MVT::i32);
1450 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1451 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1455 llvm_unreachable("only local-exec is currently supported for ppc32");
1457 if (Model == TLSModel::InitialExec) {
1458 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1459 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1460 SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1461 PtrVT, GOTReg, TGA);
1462 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1463 PtrVT, TGA, TPOffsetHi);
1464 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGA);
1467 if (Model == TLSModel::GeneralDynamic) {
1468 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1469 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1470 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1472 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1475 // We need a chain node, and don't have one handy. The underlying
1476 // call has no side effects, so using the function entry node
1478 SDValue Chain = DAG.getEntryNode();
1479 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1480 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1481 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1482 PtrVT, ParmReg, TGA);
1483 // The return value from GET_TLS_ADDR really is in X3 already, but
1484 // some hacks are needed here to tie everything together. The extra
1485 // copies dissolve during subsequent transforms.
1486 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1487 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1490 if (Model == TLSModel::LocalDynamic) {
1491 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1492 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1493 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1495 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1498 // We need a chain node, and don't have one handy. The underlying
1499 // call has no side effects, so using the function entry node
1501 SDValue Chain = DAG.getEntryNode();
1502 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1503 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1504 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1505 PtrVT, ParmReg, TGA);
1506 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1507 // some hacks are needed here to tie everything together. The extra
1508 // copies dissolve during subsequent transforms.
1509 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1510 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1511 Chain, ParmReg, TGA);
1512 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1515 llvm_unreachable("Unknown TLS model!");
1518 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1519 SelectionDAG &DAG) const {
1520 EVT PtrVT = Op.getValueType();
1521 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1522 DebugLoc DL = GSDN->getDebugLoc();
1523 const GlobalValue *GV = GSDN->getGlobal();
1525 // 64-bit SVR4 ABI code is always position-independent.
1526 // The actual address of the GlobalValue is stored in the TOC.
1527 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1528 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1529 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1530 DAG.getRegister(PPC::X2, MVT::i64));
1533 unsigned MOHiFlag, MOLoFlag;
1534 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1537 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1539 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1541 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1543 // If the global reference is actually to a non-lazy-pointer, we have to do an
1544 // extra load to get the address of the global.
1545 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1546 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1547 false, false, false, 0);
1551 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1552 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1553 DebugLoc dl = Op.getDebugLoc();
1555 // If we're comparing for equality to zero, expose the fact that this is
1556 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1557 // fold the new nodes.
1558 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1559 if (C->isNullValue() && CC == ISD::SETEQ) {
1560 EVT VT = Op.getOperand(0).getValueType();
1561 SDValue Zext = Op.getOperand(0);
1562 if (VT.bitsLT(MVT::i32)) {
1564 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1566 unsigned Log2b = Log2_32(VT.getSizeInBits());
1567 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1568 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1569 DAG.getConstant(Log2b, MVT::i32));
1570 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1572 // Leave comparisons against 0 and -1 alone for now, since they're usually
1573 // optimized. FIXME: revisit this when we can custom lower all setcc
1575 if (C->isAllOnesValue() || C->isNullValue())
1579 // If we have an integer seteq/setne, turn it into a compare against zero
1580 // by xor'ing the rhs with the lhs, which is faster than setting a
1581 // condition register, reading it back out, and masking the correct bit. The
1582 // normal approach here uses sub to do this instead of xor. Using xor exposes
1583 // the result to other bit-twiddling opportunities.
1584 EVT LHSVT = Op.getOperand(0).getValueType();
1585 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1586 EVT VT = Op.getValueType();
1587 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1589 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1594 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1595 const PPCSubtarget &Subtarget) const {
1596 SDNode *Node = Op.getNode();
1597 EVT VT = Node->getValueType(0);
1598 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1599 SDValue InChain = Node->getOperand(0);
1600 SDValue VAListPtr = Node->getOperand(1);
1601 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1602 DebugLoc dl = Node->getDebugLoc();
1604 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1607 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1608 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1610 InChain = GprIndex.getValue(1);
1612 if (VT == MVT::i64) {
1613 // Check if GprIndex is even
1614 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1615 DAG.getConstant(1, MVT::i32));
1616 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1617 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1618 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1619 DAG.getConstant(1, MVT::i32));
1620 // Align GprIndex to be even if it isn't
1621 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1625 // fpr index is 1 byte after gpr
1626 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1627 DAG.getConstant(1, MVT::i32));
1630 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1631 FprPtr, MachinePointerInfo(SV), MVT::i8,
1633 InChain = FprIndex.getValue(1);
1635 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1636 DAG.getConstant(8, MVT::i32));
1638 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1639 DAG.getConstant(4, MVT::i32));
1642 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1643 MachinePointerInfo(), false, false,
1645 InChain = OverflowArea.getValue(1);
1647 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1648 MachinePointerInfo(), false, false,
1650 InChain = RegSaveArea.getValue(1);
1652 // select overflow_area if index > 8
1653 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1654 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1656 // adjustment constant gpr_index * 4/8
1657 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1658 VT.isInteger() ? GprIndex : FprIndex,
1659 DAG.getConstant(VT.isInteger() ? 4 : 8,
1662 // OurReg = RegSaveArea + RegConstant
1663 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1666 // Floating types are 32 bytes into RegSaveArea
1667 if (VT.isFloatingPoint())
1668 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1669 DAG.getConstant(32, MVT::i32));
1671 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1672 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1673 VT.isInteger() ? GprIndex : FprIndex,
1674 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1677 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1678 VT.isInteger() ? VAListPtr : FprPtr,
1679 MachinePointerInfo(SV),
1680 MVT::i8, false, false, 0);
1682 // determine if we should load from reg_save_area or overflow_area
1683 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1685 // increase overflow_area by 4/8 if gpr/fpr > 8
1686 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1687 DAG.getConstant(VT.isInteger() ? 4 : 8,
1690 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1693 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1695 MachinePointerInfo(),
1696 MVT::i32, false, false, 0);
1698 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1699 false, false, false, 0);
1702 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1703 SelectionDAG &DAG) const {
1704 return Op.getOperand(0);
1707 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1708 SelectionDAG &DAG) const {
1709 SDValue Chain = Op.getOperand(0);
1710 SDValue Trmp = Op.getOperand(1); // trampoline
1711 SDValue FPtr = Op.getOperand(2); // nested function
1712 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1713 DebugLoc dl = Op.getDebugLoc();
1715 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1716 bool isPPC64 = (PtrVT == MVT::i64);
1718 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1721 TargetLowering::ArgListTy Args;
1722 TargetLowering::ArgListEntry Entry;
1724 Entry.Ty = IntPtrTy;
1725 Entry.Node = Trmp; Args.push_back(Entry);
1727 // TrampSize == (isPPC64 ? 48 : 40);
1728 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1729 isPPC64 ? MVT::i64 : MVT::i32);
1730 Args.push_back(Entry);
1732 Entry.Node = FPtr; Args.push_back(Entry);
1733 Entry.Node = Nest; Args.push_back(Entry);
1735 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1736 TargetLowering::CallLoweringInfo CLI(Chain,
1737 Type::getVoidTy(*DAG.getContext()),
1738 false, false, false, false, 0,
1740 /*isTailCall=*/false,
1741 /*doesNotRet=*/false,
1742 /*isReturnValueUsed=*/true,
1743 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1745 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1747 return CallResult.second;
1750 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1751 const PPCSubtarget &Subtarget) const {
1752 MachineFunction &MF = DAG.getMachineFunction();
1753 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1755 DebugLoc dl = Op.getDebugLoc();
1757 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1758 // vastart just stores the address of the VarArgsFrameIndex slot into the
1759 // memory location argument.
1760 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1761 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1762 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1763 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1764 MachinePointerInfo(SV),
1768 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1769 // We suppose the given va_list is already allocated.
1772 // char gpr; /* index into the array of 8 GPRs
1773 // * stored in the register save area
1774 // * gpr=0 corresponds to r3,
1775 // * gpr=1 to r4, etc.
1777 // char fpr; /* index into the array of 8 FPRs
1778 // * stored in the register save area
1779 // * fpr=0 corresponds to f1,
1780 // * fpr=1 to f2, etc.
1782 // char *overflow_arg_area;
1783 // /* location on stack that holds
1784 // * the next overflow argument
1786 // char *reg_save_area;
1787 // /* where r3:r10 and f1:f8 (if saved)
1793 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1794 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1797 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1799 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1801 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1804 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1805 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1807 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1808 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1810 uint64_t FPROffset = 1;
1811 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1813 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1815 // Store first byte : number of int regs
1816 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1818 MachinePointerInfo(SV),
1819 MVT::i8, false, false, 0);
1820 uint64_t nextOffset = FPROffset;
1821 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1824 // Store second byte : number of float regs
1825 SDValue secondStore =
1826 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1827 MachinePointerInfo(SV, nextOffset), MVT::i8,
1829 nextOffset += StackOffset;
1830 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1832 // Store second word : arguments given on stack
1833 SDValue thirdStore =
1834 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1835 MachinePointerInfo(SV, nextOffset),
1837 nextOffset += FrameOffset;
1838 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1840 // Store third word : arguments given in registers
1841 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1842 MachinePointerInfo(SV, nextOffset),
1847 #include "PPCGenCallingConv.inc"
1849 static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1850 CCValAssign::LocInfo &LocInfo,
1851 ISD::ArgFlagsTy &ArgFlags,
1856 static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1858 CCValAssign::LocInfo &LocInfo,
1859 ISD::ArgFlagsTy &ArgFlags,
1861 static const uint16_t ArgRegs[] = {
1862 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1863 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1865 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1867 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1869 // Skip one register if the first unallocated register has an even register
1870 // number and there are still argument registers available which have not been
1871 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1872 // need to skip a register if RegNum is odd.
1873 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1874 State.AllocateReg(ArgRegs[RegNum]);
1877 // Always return false here, as this function only makes sure that the first
1878 // unallocated register has an odd register number and does not actually
1879 // allocate a register for the current argument.
1883 static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1885 CCValAssign::LocInfo &LocInfo,
1886 ISD::ArgFlagsTy &ArgFlags,
1888 static const uint16_t ArgRegs[] = {
1889 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1893 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1895 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1897 // If there is only one Floating-point register left we need to put both f64
1898 // values of a split ppc_fp128 value on the stack.
1899 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1900 State.AllocateReg(ArgRegs[RegNum]);
1903 // Always return false here, as this function only makes sure that the two f64
1904 // values a ppc_fp128 value is split into are both passed in registers or both
1905 // passed on the stack and does not actually allocate a register for the
1906 // current argument.
1910 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1912 static const uint16_t *GetFPR() {
1913 static const uint16_t FPR[] = {
1914 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1915 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1921 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1923 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1924 unsigned PtrByteSize) {
1925 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1926 if (Flags.isByVal())
1927 ArgSize = Flags.getByValSize();
1928 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1934 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1935 CallingConv::ID CallConv, bool isVarArg,
1936 const SmallVectorImpl<ISD::InputArg>
1938 DebugLoc dl, SelectionDAG &DAG,
1939 SmallVectorImpl<SDValue> &InVals)
1941 if (PPCSubTarget.isSVR4ABI()) {
1942 if (PPCSubTarget.isPPC64())
1943 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
1946 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
1949 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1955 PPCTargetLowering::LowerFormalArguments_32SVR4(
1957 CallingConv::ID CallConv, bool isVarArg,
1958 const SmallVectorImpl<ISD::InputArg>
1960 DebugLoc dl, SelectionDAG &DAG,
1961 SmallVectorImpl<SDValue> &InVals) const {
1963 // 32-bit SVR4 ABI Stack Frame Layout:
1964 // +-----------------------------------+
1965 // +--> | Back chain |
1966 // | +-----------------------------------+
1967 // | | Floating-point register save area |
1968 // | +-----------------------------------+
1969 // | | General register save area |
1970 // | +-----------------------------------+
1971 // | | CR save word |
1972 // | +-----------------------------------+
1973 // | | VRSAVE save word |
1974 // | +-----------------------------------+
1975 // | | Alignment padding |
1976 // | +-----------------------------------+
1977 // | | Vector register save area |
1978 // | +-----------------------------------+
1979 // | | Local variable space |
1980 // | +-----------------------------------+
1981 // | | Parameter list area |
1982 // | +-----------------------------------+
1983 // | | LR save word |
1984 // | +-----------------------------------+
1985 // SP--> +--- | Back chain |
1986 // +-----------------------------------+
1989 // System V Application Binary Interface PowerPC Processor Supplement
1990 // AltiVec Technology Programming Interface Manual
1992 MachineFunction &MF = DAG.getMachineFunction();
1993 MachineFrameInfo *MFI = MF.getFrameInfo();
1994 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1996 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1997 // Potential tail calls could cause overwriting of argument stack slots.
1998 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1999 (CallConv == CallingConv::Fast));
2000 unsigned PtrByteSize = 4;
2002 // Assign locations to all of the incoming arguments.
2003 SmallVector<CCValAssign, 16> ArgLocs;
2004 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2005 getTargetMachine(), ArgLocs, *DAG.getContext());
2007 // Reserve space for the linkage area on the stack.
2008 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2010 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2012 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2013 CCValAssign &VA = ArgLocs[i];
2015 // Arguments stored in registers.
2016 if (VA.isRegLoc()) {
2017 const TargetRegisterClass *RC;
2018 EVT ValVT = VA.getValVT();
2020 switch (ValVT.getSimpleVT().SimpleTy) {
2022 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2024 RC = &PPC::GPRCRegClass;
2027 RC = &PPC::F4RCRegClass;
2030 RC = &PPC::F8RCRegClass;
2036 RC = &PPC::VRRCRegClass;
2040 // Transform the arguments stored in physical registers into virtual ones.
2041 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2042 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
2044 InVals.push_back(ArgValue);
2046 // Argument stored in memory.
2047 assert(VA.isMemLoc());
2049 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
2050 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2053 // Create load nodes to retrieve arguments from the stack.
2054 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2055 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2056 MachinePointerInfo(),
2057 false, false, false, 0));
2061 // Assign locations to all of the incoming aggregate by value arguments.
2062 // Aggregates passed by value are stored in the local variable space of the
2063 // caller's stack frame, right above the parameter list area.
2064 SmallVector<CCValAssign, 16> ByValArgLocs;
2065 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2066 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2068 // Reserve stack space for the allocations in CCInfo.
2069 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2071 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2073 // Area that is at least reserved in the caller of this function.
2074 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2076 // Set the size that is at least reserved in caller of this function. Tail
2077 // call optimized function's reserved stack space needs to be aligned so that
2078 // taking the difference between two stack areas will result in an aligned
2080 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2083 std::max(MinReservedArea,
2084 PPCFrameLowering::getMinCallFrameSize(false, false));
2086 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2087 getStackAlignment();
2088 unsigned AlignMask = TargetAlign-1;
2089 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2091 FI->setMinReservedArea(MinReservedArea);
2093 SmallVector<SDValue, 8> MemOps;
2095 // If the function takes variable number of arguments, make a frame index for
2096 // the start of the first vararg value... for expansion of llvm.va_start.
2098 static const uint16_t GPArgRegs[] = {
2099 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2100 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2102 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2104 static const uint16_t FPArgRegs[] = {
2105 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2108 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2110 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2112 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2115 // Make room for NumGPArgRegs and NumFPArgRegs.
2116 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2117 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2119 FuncInfo->setVarArgsStackOffset(
2120 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2121 CCInfo.getNextStackOffset(), true));
2123 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2124 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2126 // The fixed integer arguments of a variadic function are stored to the
2127 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2128 // the result of va_next.
2129 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2130 // Get an existing live-in vreg, or add a new one.
2131 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2133 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2135 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2136 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2137 MachinePointerInfo(), false, false, 0);
2138 MemOps.push_back(Store);
2139 // Increment the address by four for the next argument to store
2140 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2141 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2144 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2146 // The double arguments are stored to the VarArgsFrameIndex
2148 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2149 // Get an existing live-in vreg, or add a new one.
2150 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2152 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2154 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2155 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2156 MachinePointerInfo(), false, false, 0);
2157 MemOps.push_back(Store);
2158 // Increment the address by eight for the next argument to store
2159 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2161 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2165 if (!MemOps.empty())
2166 Chain = DAG.getNode(ISD::TokenFactor, dl,
2167 MVT::Other, &MemOps[0], MemOps.size());
2172 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2173 // value to MVT::i64 and then truncate to the correct register size.
2175 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2176 SelectionDAG &DAG, SDValue ArgVal,
2177 DebugLoc dl) const {
2179 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2180 DAG.getValueType(ObjectVT));
2181 else if (Flags.isZExt())
2182 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2183 DAG.getValueType(ObjectVT));
2185 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2188 // Set the size that is at least reserved in caller of this function. Tail
2189 // call optimized functions' reserved stack space needs to be aligned so that
2190 // taking the difference between two stack areas will result in an aligned
2193 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2194 unsigned nAltivecParamsAtEnd,
2195 unsigned MinReservedArea,
2196 bool isPPC64) const {
2197 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2198 // Add the Altivec parameters at the end, if needed.
2199 if (nAltivecParamsAtEnd) {
2200 MinReservedArea = ((MinReservedArea+15)/16)*16;
2201 MinReservedArea += 16*nAltivecParamsAtEnd;
2204 std::max(MinReservedArea,
2205 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2206 unsigned TargetAlign
2207 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2208 getStackAlignment();
2209 unsigned AlignMask = TargetAlign-1;
2210 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2211 FI->setMinReservedArea(MinReservedArea);
2215 PPCTargetLowering::LowerFormalArguments_64SVR4(
2217 CallingConv::ID CallConv, bool isVarArg,
2218 const SmallVectorImpl<ISD::InputArg>
2220 DebugLoc dl, SelectionDAG &DAG,
2221 SmallVectorImpl<SDValue> &InVals) const {
2222 // TODO: add description of PPC stack frame format, or at least some docs.
2224 MachineFunction &MF = DAG.getMachineFunction();
2225 MachineFrameInfo *MFI = MF.getFrameInfo();
2226 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2228 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2229 // Potential tail calls could cause overwriting of argument stack slots.
2230 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2231 (CallConv == CallingConv::Fast));
2232 unsigned PtrByteSize = 8;
2234 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2235 // Area that is at least reserved in caller of this function.
2236 unsigned MinReservedArea = ArgOffset;
2238 static const uint16_t GPR[] = {
2239 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2240 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2243 static const uint16_t *FPR = GetFPR();
2245 static const uint16_t VR[] = {
2246 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2247 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2250 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2251 const unsigned Num_FPR_Regs = 13;
2252 const unsigned Num_VR_Regs = array_lengthof(VR);
2254 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2256 // Add DAG nodes to load the arguments or copy them out of registers. On
2257 // entry to a function on PPC, the arguments start after the linkage area,
2258 // although the first ones are often in registers.
2260 SmallVector<SDValue, 8> MemOps;
2261 unsigned nAltivecParamsAtEnd = 0;
2262 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2263 unsigned CurArgIdx = 0;
2264 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2266 bool needsLoad = false;
2267 EVT ObjectVT = Ins[ArgNo].VT;
2268 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2269 unsigned ArgSize = ObjSize;
2270 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2271 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2272 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2274 unsigned CurArgOffset = ArgOffset;
2276 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2277 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2278 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2280 MinReservedArea = ((MinReservedArea+15)/16)*16;
2281 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2285 nAltivecParamsAtEnd++;
2287 // Calculate min reserved area.
2288 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2292 // FIXME the codegen can be much improved in some cases.
2293 // We do not have to keep everything in memory.
2294 if (Flags.isByVal()) {
2295 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2296 ObjSize = Flags.getByValSize();
2297 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2298 // Empty aggregate parameters do not take up registers. Examples:
2302 // etc. However, we have to provide a place-holder in InVals, so
2303 // pretend we have an 8-byte item at the current address for that
2306 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2307 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2308 InVals.push_back(FIN);
2311 // All aggregates smaller than 8 bytes must be passed right-justified.
2312 if (ObjSize < PtrByteSize)
2313 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2314 // The value of the object is its address.
2315 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2316 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2317 InVals.push_back(FIN);
2320 if (GPR_idx != Num_GPR_Regs) {
2321 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2322 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2325 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2326 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2327 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2328 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2329 MachinePointerInfo(FuncArg, CurArgOffset),
2330 ObjType, false, false, 0);
2332 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2333 // store the whole register as-is to the parameter save area
2334 // slot. The address of the parameter was already calculated
2335 // above (InVals.push_back(FIN)) to be the right-justified
2336 // offset within the slot. For this store, we need a new
2337 // frame index that points at the beginning of the slot.
2338 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2339 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2340 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2341 MachinePointerInfo(FuncArg, ArgOffset),
2345 MemOps.push_back(Store);
2348 // Whether we copied from a register or not, advance the offset
2349 // into the parameter save area by a full doubleword.
2350 ArgOffset += PtrByteSize;
2354 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2355 // Store whatever pieces of the object are in registers
2356 // to memory. ArgOffset will be the address of the beginning
2358 if (GPR_idx != Num_GPR_Regs) {
2360 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2361 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2362 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2363 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2364 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2365 MachinePointerInfo(FuncArg, ArgOffset),
2367 MemOps.push_back(Store);
2369 ArgOffset += PtrByteSize;
2371 ArgOffset += ArgSize - j;
2378 switch (ObjectVT.getSimpleVT().SimpleTy) {
2379 default: llvm_unreachable("Unhandled argument type!");
2382 if (GPR_idx != Num_GPR_Regs) {
2383 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2384 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2386 if (ObjectVT == MVT::i32)
2387 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2388 // value to MVT::i64 and then truncate to the correct register size.
2389 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2394 ArgSize = PtrByteSize;
2401 // Every 8 bytes of argument space consumes one of the GPRs available for
2402 // argument passing.
2403 if (GPR_idx != Num_GPR_Regs) {
2406 if (FPR_idx != Num_FPR_Regs) {
2409 if (ObjectVT == MVT::f32)
2410 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2412 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2414 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2418 ArgSize = PtrByteSize;
2427 // Note that vector arguments in registers don't reserve stack space,
2428 // except in varargs functions.
2429 if (VR_idx != Num_VR_Regs) {
2430 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2431 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2433 while ((ArgOffset % 16) != 0) {
2434 ArgOffset += PtrByteSize;
2435 if (GPR_idx != Num_GPR_Regs)
2439 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2443 // Vectors are aligned.
2444 ArgOffset = ((ArgOffset+15)/16)*16;
2445 CurArgOffset = ArgOffset;
2452 // We need to load the argument to a virtual register if we determined
2453 // above that we ran out of physical registers of the appropriate type.
2455 int FI = MFI->CreateFixedObject(ObjSize,
2456 CurArgOffset + (ArgSize - ObjSize),
2458 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2459 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2460 false, false, false, 0);
2463 InVals.push_back(ArgVal);
2466 // Set the size that is at least reserved in caller of this function. Tail
2467 // call optimized functions' reserved stack space needs to be aligned so that
2468 // taking the difference between two stack areas will result in an aligned
2470 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2472 // If the function takes variable number of arguments, make a frame index for
2473 // the start of the first vararg value... for expansion of llvm.va_start.
2475 int Depth = ArgOffset;
2477 FuncInfo->setVarArgsFrameIndex(
2478 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2479 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2481 // If this function is vararg, store any remaining integer argument regs
2482 // to their spots on the stack so that they may be loaded by deferencing the
2483 // result of va_next.
2484 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2485 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2486 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2487 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2488 MachinePointerInfo(), false, false, 0);
2489 MemOps.push_back(Store);
2490 // Increment the address by four for the next argument to store
2491 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2492 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2496 if (!MemOps.empty())
2497 Chain = DAG.getNode(ISD::TokenFactor, dl,
2498 MVT::Other, &MemOps[0], MemOps.size());
2504 PPCTargetLowering::LowerFormalArguments_Darwin(
2506 CallingConv::ID CallConv, bool isVarArg,
2507 const SmallVectorImpl<ISD::InputArg>
2509 DebugLoc dl, SelectionDAG &DAG,
2510 SmallVectorImpl<SDValue> &InVals) const {
2511 // TODO: add description of PPC stack frame format, or at least some docs.
2513 MachineFunction &MF = DAG.getMachineFunction();
2514 MachineFrameInfo *MFI = MF.getFrameInfo();
2515 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2517 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2518 bool isPPC64 = PtrVT == MVT::i64;
2519 // Potential tail calls could cause overwriting of argument stack slots.
2520 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2521 (CallConv == CallingConv::Fast));
2522 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2524 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2525 // Area that is at least reserved in caller of this function.
2526 unsigned MinReservedArea = ArgOffset;
2528 static const uint16_t GPR_32[] = { // 32-bit registers.
2529 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2530 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2532 static const uint16_t GPR_64[] = { // 64-bit registers.
2533 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2534 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2537 static const uint16_t *FPR = GetFPR();
2539 static const uint16_t VR[] = {
2540 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2541 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2544 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2545 const unsigned Num_FPR_Regs = 13;
2546 const unsigned Num_VR_Regs = array_lengthof( VR);
2548 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2550 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2552 // In 32-bit non-varargs functions, the stack space for vectors is after the
2553 // stack space for non-vectors. We do not use this space unless we have
2554 // too many vectors to fit in registers, something that only occurs in
2555 // constructed examples:), but we have to walk the arglist to figure
2556 // that out...for the pathological case, compute VecArgOffset as the
2557 // start of the vector parameter area. Computing VecArgOffset is the
2558 // entire point of the following loop.
2559 unsigned VecArgOffset = ArgOffset;
2560 if (!isVarArg && !isPPC64) {
2561 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2563 EVT ObjectVT = Ins[ArgNo].VT;
2564 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2566 if (Flags.isByVal()) {
2567 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2568 unsigned ObjSize = Flags.getByValSize();
2570 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2571 VecArgOffset += ArgSize;
2575 switch(ObjectVT.getSimpleVT().SimpleTy) {
2576 default: llvm_unreachable("Unhandled argument type!");
2581 case MVT::i64: // PPC64
2583 // FIXME: We are guaranteed to be !isPPC64 at this point.
2584 // Does MVT::i64 apply?
2591 // Nothing to do, we're only looking at Nonvector args here.
2596 // We've found where the vector parameter area in memory is. Skip the
2597 // first 12 parameters; these don't use that memory.
2598 VecArgOffset = ((VecArgOffset+15)/16)*16;
2599 VecArgOffset += 12*16;
2601 // Add DAG nodes to load the arguments or copy them out of registers. On
2602 // entry to a function on PPC, the arguments start after the linkage area,
2603 // although the first ones are often in registers.
2605 SmallVector<SDValue, 8> MemOps;
2606 unsigned nAltivecParamsAtEnd = 0;
2607 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2608 unsigned CurArgIdx = 0;
2609 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2611 bool needsLoad = false;
2612 EVT ObjectVT = Ins[ArgNo].VT;
2613 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2614 unsigned ArgSize = ObjSize;
2615 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2616 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2617 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2619 unsigned CurArgOffset = ArgOffset;
2621 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2622 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2623 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2624 if (isVarArg || isPPC64) {
2625 MinReservedArea = ((MinReservedArea+15)/16)*16;
2626 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2629 } else nAltivecParamsAtEnd++;
2631 // Calculate min reserved area.
2632 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2636 // FIXME the codegen can be much improved in some cases.
2637 // We do not have to keep everything in memory.
2638 if (Flags.isByVal()) {
2639 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2640 ObjSize = Flags.getByValSize();
2641 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2642 // Objects of size 1 and 2 are right justified, everything else is
2643 // left justified. This means the memory address is adjusted forwards.
2644 if (ObjSize==1 || ObjSize==2) {
2645 CurArgOffset = CurArgOffset + (4 - ObjSize);
2647 // The value of the object is its address.
2648 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2649 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2650 InVals.push_back(FIN);
2651 if (ObjSize==1 || ObjSize==2) {
2652 if (GPR_idx != Num_GPR_Regs) {
2655 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2657 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2658 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2659 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2660 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2661 MachinePointerInfo(FuncArg,
2663 ObjType, false, false, 0);
2664 MemOps.push_back(Store);
2668 ArgOffset += PtrByteSize;
2672 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2673 // Store whatever pieces of the object are in registers
2674 // to memory. ArgOffset will be the address of the beginning
2676 if (GPR_idx != Num_GPR_Regs) {
2679 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2681 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2682 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2683 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2684 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2685 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2686 MachinePointerInfo(FuncArg, ArgOffset),
2688 MemOps.push_back(Store);
2690 ArgOffset += PtrByteSize;
2692 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2699 switch (ObjectVT.getSimpleVT().SimpleTy) {
2700 default: llvm_unreachable("Unhandled argument type!");
2703 if (GPR_idx != Num_GPR_Regs) {
2704 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2705 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2709 ArgSize = PtrByteSize;
2711 // All int arguments reserve stack space in the Darwin ABI.
2712 ArgOffset += PtrByteSize;
2716 case MVT::i64: // PPC64
2717 if (GPR_idx != Num_GPR_Regs) {
2718 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2719 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2721 if (ObjectVT == MVT::i32)
2722 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2723 // value to MVT::i64 and then truncate to the correct register size.
2724 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2729 ArgSize = PtrByteSize;
2731 // All int arguments reserve stack space in the Darwin ABI.
2737 // Every 4 bytes of argument space consumes one of the GPRs available for
2738 // argument passing.
2739 if (GPR_idx != Num_GPR_Regs) {
2741 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2744 if (FPR_idx != Num_FPR_Regs) {
2747 if (ObjectVT == MVT::f32)
2748 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2750 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2752 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2758 // All FP arguments reserve stack space in the Darwin ABI.
2759 ArgOffset += isPPC64 ? 8 : ObjSize;
2765 // Note that vector arguments in registers don't reserve stack space,
2766 // except in varargs functions.
2767 if (VR_idx != Num_VR_Regs) {
2768 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2769 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2771 while ((ArgOffset % 16) != 0) {
2772 ArgOffset += PtrByteSize;
2773 if (GPR_idx != Num_GPR_Regs)
2777 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2781 if (!isVarArg && !isPPC64) {
2782 // Vectors go after all the nonvectors.
2783 CurArgOffset = VecArgOffset;
2786 // Vectors are aligned.
2787 ArgOffset = ((ArgOffset+15)/16)*16;
2788 CurArgOffset = ArgOffset;
2796 // We need to load the argument to a virtual register if we determined above
2797 // that we ran out of physical registers of the appropriate type.
2799 int FI = MFI->CreateFixedObject(ObjSize,
2800 CurArgOffset + (ArgSize - ObjSize),
2802 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2803 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2804 false, false, false, 0);
2807 InVals.push_back(ArgVal);
2810 // Set the size that is at least reserved in caller of this function. Tail
2811 // call optimized functions' reserved stack space needs to be aligned so that
2812 // taking the difference between two stack areas will result in an aligned
2814 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
2816 // If the function takes variable number of arguments, make a frame index for
2817 // the start of the first vararg value... for expansion of llvm.va_start.
2819 int Depth = ArgOffset;
2821 FuncInfo->setVarArgsFrameIndex(
2822 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2824 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2826 // If this function is vararg, store any remaining integer argument regs
2827 // to their spots on the stack so that they may be loaded by deferencing the
2828 // result of va_next.
2829 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2833 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2835 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2837 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2838 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2839 MachinePointerInfo(), false, false, 0);
2840 MemOps.push_back(Store);
2841 // Increment the address by four for the next argument to store
2842 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2843 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2847 if (!MemOps.empty())
2848 Chain = DAG.getNode(ISD::TokenFactor, dl,
2849 MVT::Other, &MemOps[0], MemOps.size());
2854 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
2855 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
2857 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2861 const SmallVectorImpl<ISD::OutputArg>
2863 const SmallVectorImpl<SDValue> &OutVals,
2864 unsigned &nAltivecParamsAtEnd) {
2865 // Count how many bytes are to be pushed on the stack, including the linkage
2866 // area, and parameter passing area. We start with 24/48 bytes, which is
2867 // prereserved space for [SP][CR][LR][3 x unused].
2868 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2869 unsigned NumOps = Outs.size();
2870 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2872 // Add up all the space actually used.
2873 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2874 // they all go in registers, but we must reserve stack space for them for
2875 // possible use by the caller. In varargs or 64-bit calls, parameters are
2876 // assigned stack space in order, with padding so Altivec parameters are
2878 nAltivecParamsAtEnd = 0;
2879 for (unsigned i = 0; i != NumOps; ++i) {
2880 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2881 EVT ArgVT = Outs[i].VT;
2882 // Varargs Altivec parameters are padded to a 16 byte boundary.
2883 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2884 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2885 if (!isVarArg && !isPPC64) {
2886 // Non-varargs Altivec parameters go after all the non-Altivec
2887 // parameters; handle those later so we know how much padding we need.
2888 nAltivecParamsAtEnd++;
2891 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2892 NumBytes = ((NumBytes+15)/16)*16;
2894 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2897 // Allow for Altivec parameters at the end, if needed.
2898 if (nAltivecParamsAtEnd) {
2899 NumBytes = ((NumBytes+15)/16)*16;
2900 NumBytes += 16*nAltivecParamsAtEnd;
2903 // The prolog code of the callee may store up to 8 GPR argument registers to
2904 // the stack, allowing va_start to index over them in memory if its varargs.
2905 // Because we cannot tell if this is needed on the caller side, we have to
2906 // conservatively assume that it is needed. As such, make sure we have at
2907 // least enough stack space for the caller to store the 8 GPRs.
2908 NumBytes = std::max(NumBytes,
2909 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2911 // Tail call needs the stack to be aligned.
2912 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2913 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2914 getFrameLowering()->getStackAlignment();
2915 unsigned AlignMask = TargetAlign-1;
2916 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2922 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2923 /// adjusted to accommodate the arguments for the tailcall.
2924 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2925 unsigned ParamSize) {
2927 if (!isTailCall) return 0;
2929 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2930 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2931 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2932 // Remember only if the new adjustement is bigger.
2933 if (SPDiff < FI->getTailCallSPDelta())
2934 FI->setTailCallSPDelta(SPDiff);
2939 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2940 /// for tail call optimization. Targets which want to do tail call
2941 /// optimization should implement this function.
2943 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2944 CallingConv::ID CalleeCC,
2946 const SmallVectorImpl<ISD::InputArg> &Ins,
2947 SelectionDAG& DAG) const {
2948 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2951 // Variable argument functions are not supported.
2955 MachineFunction &MF = DAG.getMachineFunction();
2956 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2957 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2958 // Functions containing by val parameters are not supported.
2959 for (unsigned i = 0; i != Ins.size(); i++) {
2960 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2961 if (Flags.isByVal()) return false;
2964 // Non PIC/GOT tail calls are supported.
2965 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2968 // At the moment we can only do local tail calls (in same module, hidden
2969 // or protected) if we are generating PIC.
2970 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2971 return G->getGlobal()->hasHiddenVisibility()
2972 || G->getGlobal()->hasProtectedVisibility();
2978 /// isCallCompatibleAddress - Return the immediate to use if the specified
2979 /// 32-bit value is representable in the immediate field of a BxA instruction.
2980 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2981 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2984 int Addr = C->getZExtValue();
2985 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2986 SignExtend32<26>(Addr) != Addr)
2987 return 0; // Top 6 bits have to be sext of immediate.
2989 return DAG.getConstant((int)C->getZExtValue() >> 2,
2990 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2995 struct TailCallArgumentInfo {
3000 TailCallArgumentInfo() : FrameIdx(0) {}
3005 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3007 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3009 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
3010 SmallVector<SDValue, 8> &MemOpChains,
3012 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3013 SDValue Arg = TailCallArgs[i].Arg;
3014 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3015 int FI = TailCallArgs[i].FrameIdx;
3016 // Store relative to framepointer.
3017 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3018 MachinePointerInfo::getFixedStack(FI),
3023 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3024 /// the appropriate stack slot for the tail call optimized function call.
3025 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3026 MachineFunction &MF,
3035 // Calculate the new stack slot for the return address.
3036 int SlotSize = isPPC64 ? 8 : 4;
3037 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3039 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3040 NewRetAddrLoc, true);
3041 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3042 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3043 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3044 MachinePointerInfo::getFixedStack(NewRetAddr),
3047 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3048 // slot as the FP is never overwritten.
3051 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3052 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3054 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3055 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3056 MachinePointerInfo::getFixedStack(NewFPIdx),
3063 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3064 /// the position of the argument.
3066 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3067 SDValue Arg, int SPDiff, unsigned ArgOffset,
3068 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
3069 int Offset = ArgOffset + SPDiff;
3070 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3071 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3072 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3073 SDValue FIN = DAG.getFrameIndex(FI, VT);
3074 TailCallArgumentInfo Info;
3076 Info.FrameIdxOp = FIN;
3078 TailCallArguments.push_back(Info);
3081 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3082 /// stack slot. Returns the chain as result and the loaded frame pointers in
3083 /// LROpOut/FPOpout. Used when tail calling.
3084 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3090 DebugLoc dl) const {
3092 // Load the LR and FP stack slot for later adjusting.
3093 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3094 LROpOut = getReturnAddrFrameIndex(DAG);
3095 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3096 false, false, false, 0);
3097 Chain = SDValue(LROpOut.getNode(), 1);
3099 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3100 // slot as the FP is never overwritten.
3102 FPOpOut = getFramePointerFrameIndex(DAG);
3103 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3104 false, false, false, 0);
3105 Chain = SDValue(FPOpOut.getNode(), 1);
3111 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3112 /// by "Src" to address "Dst" of size "Size". Alignment information is
3113 /// specified by the specific parameter attribute. The copy will be passed as
3114 /// a byval function parameter.
3115 /// Sometimes what we are copying is the end of a larger object, the part that
3116 /// does not fit in registers.
3118 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3119 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3121 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3122 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3123 false, false, MachinePointerInfo(0),
3124 MachinePointerInfo(0));
3127 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3130 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3131 SDValue Arg, SDValue PtrOff, int SPDiff,
3132 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3133 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
3134 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
3136 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3141 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3143 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3144 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3145 DAG.getConstant(ArgOffset, PtrVT));
3147 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3148 MachinePointerInfo(), false, false, 0));
3149 // Calculate and remember argument location.
3150 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3155 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3156 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3157 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3158 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
3159 MachineFunction &MF = DAG.getMachineFunction();
3161 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3162 // might overwrite each other in case of tail call optimization.
3163 SmallVector<SDValue, 8> MemOpChains2;
3164 // Do not flag preceding copytoreg stuff together with the following stuff.
3166 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3168 if (!MemOpChains2.empty())
3169 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3170 &MemOpChains2[0], MemOpChains2.size());
3172 // Store the return address to the appropriate stack slot.
3173 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3174 isPPC64, isDarwinABI, dl);
3176 // Emit callseq_end just before tailcall node.
3177 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3178 DAG.getIntPtrConstant(0, true), InFlag);
3179 InFlag = Chain.getValue(1);
3183 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3184 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
3185 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
3186 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
3187 const PPCSubtarget &PPCSubTarget) {
3189 bool isPPC64 = PPCSubTarget.isPPC64();
3190 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3192 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3193 NodeTys.push_back(MVT::Other); // Returns a chain
3194 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3196 unsigned CallOpc = PPCISD::CALL;
3198 bool needIndirectCall = true;
3199 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3200 // If this is an absolute destination address, use the munged value.
3201 Callee = SDValue(Dest, 0);
3202 needIndirectCall = false;
3205 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3206 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3207 // Use indirect calls for ALL functions calls in JIT mode, since the
3208 // far-call stubs may be outside relocation limits for a BL instruction.
3209 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3210 unsigned OpFlags = 0;
3211 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3212 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3213 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3214 (G->getGlobal()->isDeclaration() ||
3215 G->getGlobal()->isWeakForLinker())) {
3216 // PC-relative references to external symbols should go through $stub,
3217 // unless we're building with the leopard linker or later, which
3218 // automatically synthesizes these stubs.
3219 OpFlags = PPCII::MO_DARWIN_STUB;
3222 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3223 // every direct call is) turn it into a TargetGlobalAddress /
3224 // TargetExternalSymbol node so that legalize doesn't hack it.
3225 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3226 Callee.getValueType(),
3228 needIndirectCall = false;
3232 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3233 unsigned char OpFlags = 0;
3235 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3236 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3237 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3238 // PC-relative references to external symbols should go through $stub,
3239 // unless we're building with the leopard linker or later, which
3240 // automatically synthesizes these stubs.
3241 OpFlags = PPCII::MO_DARWIN_STUB;
3244 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3246 needIndirectCall = false;
3249 if (needIndirectCall) {
3250 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3251 // to do the call, we can't use PPCISD::CALL.
3252 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3254 if (isSVR4ABI && isPPC64) {
3255 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3256 // entry point, but to the function descriptor (the function entry point
3257 // address is part of the function descriptor though).
3258 // The function descriptor is a three doubleword structure with the
3259 // following fields: function entry point, TOC base address and
3260 // environment pointer.
3261 // Thus for a call through a function pointer, the following actions need
3263 // 1. Save the TOC of the caller in the TOC save area of its stack
3264 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3265 // 2. Load the address of the function entry point from the function
3267 // 3. Load the TOC of the callee from the function descriptor into r2.
3268 // 4. Load the environment pointer from the function descriptor into
3270 // 5. Branch to the function entry point address.
3271 // 6. On return of the callee, the TOC of the caller needs to be
3272 // restored (this is done in FinishCall()).
3274 // All those operations are flagged together to ensure that no other
3275 // operations can be scheduled in between. E.g. without flagging the
3276 // operations together, a TOC access in the caller could be scheduled
3277 // between the load of the callee TOC and the branch to the callee, which
3278 // results in the TOC access going through the TOC of the callee instead
3279 // of going through the TOC of the caller, which leads to incorrect code.
3281 // Load the address of the function entry point from the function
3283 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3284 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
3285 InFlag.getNode() ? 3 : 2);
3286 Chain = LoadFuncPtr.getValue(1);
3287 InFlag = LoadFuncPtr.getValue(2);
3289 // Load environment pointer into r11.
3290 // Offset of the environment pointer within the function descriptor.
3291 SDValue PtrOff = DAG.getIntPtrConstant(16);
3293 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3294 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3296 Chain = LoadEnvPtr.getValue(1);
3297 InFlag = LoadEnvPtr.getValue(2);
3299 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3301 Chain = EnvVal.getValue(0);
3302 InFlag = EnvVal.getValue(1);
3304 // Load TOC of the callee into r2. We are using a target-specific load
3305 // with r2 hard coded, because the result of a target-independent load
3306 // would never go directly into r2, since r2 is a reserved register (which
3307 // prevents the register allocator from allocating it), resulting in an
3308 // additional register being allocated and an unnecessary move instruction
3310 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3311 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3313 Chain = LoadTOCPtr.getValue(0);
3314 InFlag = LoadTOCPtr.getValue(1);
3316 MTCTROps[0] = Chain;
3317 MTCTROps[1] = LoadFuncPtr;
3318 MTCTROps[2] = InFlag;
3321 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
3322 2 + (InFlag.getNode() != 0));
3323 InFlag = Chain.getValue(1);
3326 NodeTys.push_back(MVT::Other);
3327 NodeTys.push_back(MVT::Glue);
3328 Ops.push_back(Chain);
3329 CallOpc = PPCISD::BCTRL;
3331 // Add use of X11 (holding environment pointer)
3332 if (isSVR4ABI && isPPC64)
3333 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3334 // Add CTR register as callee so a bctr can be emitted later.
3336 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3339 // If this is a direct call, pass the chain and the callee.
3340 if (Callee.getNode()) {
3341 Ops.push_back(Chain);
3342 Ops.push_back(Callee);
3344 // If this is a tail call add stack pointer delta.
3346 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3348 // Add argument registers to the end of the list so that they are known live
3350 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3351 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3352 RegsToPass[i].second.getValueType()));
3358 bool isLocalCall(const SDValue &Callee)
3360 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3361 return !G->getGlobal()->isDeclaration() &&
3362 !G->getGlobal()->isWeakForLinker();
3367 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3368 CallingConv::ID CallConv, bool isVarArg,
3369 const SmallVectorImpl<ISD::InputArg> &Ins,
3370 DebugLoc dl, SelectionDAG &DAG,
3371 SmallVectorImpl<SDValue> &InVals) const {
3373 SmallVector<CCValAssign, 16> RVLocs;
3374 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3375 getTargetMachine(), RVLocs, *DAG.getContext());
3376 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3378 // Copy all of the result registers out of their specified physreg.
3379 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3380 CCValAssign &VA = RVLocs[i];
3381 assert(VA.isRegLoc() && "Can only return in registers!");
3383 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3384 VA.getLocReg(), VA.getLocVT(), InFlag);
3385 Chain = Val.getValue(1);
3386 InFlag = Val.getValue(2);
3388 switch (VA.getLocInfo()) {
3389 default: llvm_unreachable("Unknown loc info!");
3390 case CCValAssign::Full: break;
3391 case CCValAssign::AExt:
3392 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3394 case CCValAssign::ZExt:
3395 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3396 DAG.getValueType(VA.getValVT()));
3397 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3399 case CCValAssign::SExt:
3400 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3401 DAG.getValueType(VA.getValVT()));
3402 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3406 InVals.push_back(Val);
3413 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
3414 bool isTailCall, bool isVarArg,
3416 SmallVector<std::pair<unsigned, SDValue>, 8>
3418 SDValue InFlag, SDValue Chain,
3420 int SPDiff, unsigned NumBytes,
3421 const SmallVectorImpl<ISD::InputArg> &Ins,
3422 SmallVectorImpl<SDValue> &InVals) const {
3423 std::vector<EVT> NodeTys;
3424 SmallVector<SDValue, 8> Ops;
3425 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3426 isTailCall, RegsToPass, Ops, NodeTys,
3429 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3430 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3431 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3433 // When performing tail call optimization the callee pops its arguments off
3434 // the stack. Account for this here so these bytes can be pushed back on in
3435 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3436 int BytesCalleePops =
3437 (CallConv == CallingConv::Fast &&
3438 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3440 // Add a register mask operand representing the call-preserved registers.
3441 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3442 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3443 assert(Mask && "Missing call preserved mask for calling convention");
3444 Ops.push_back(DAG.getRegisterMask(Mask));
3446 if (InFlag.getNode())
3447 Ops.push_back(InFlag);
3451 assert(((Callee.getOpcode() == ISD::Register &&
3452 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3453 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3454 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3455 isa<ConstantSDNode>(Callee)) &&
3456 "Expecting an global address, external symbol, absolute value or register");
3458 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3461 // Add a NOP immediately after the branch instruction when using the 64-bit
3462 // SVR4 ABI. At link time, if caller and callee are in a different module and
3463 // thus have a different TOC, the call will be replaced with a call to a stub
3464 // function which saves the current TOC, loads the TOC of the callee and
3465 // branches to the callee. The NOP will be replaced with a load instruction
3466 // which restores the TOC of the caller from the TOC save slot of the current
3467 // stack frame. If caller and callee belong to the same module (and have the
3468 // same TOC), the NOP will remain unchanged.
3470 bool needsTOCRestore = false;
3471 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3472 if (CallOpc == PPCISD::BCTRL) {
3473 // This is a call through a function pointer.
3474 // Restore the caller TOC from the save area into R2.
3475 // See PrepareCall() for more information about calls through function
3476 // pointers in the 64-bit SVR4 ABI.
3477 // We are using a target-specific load with r2 hard coded, because the
3478 // result of a target-independent load would never go directly into r2,
3479 // since r2 is a reserved register (which prevents the register allocator
3480 // from allocating it), resulting in an additional register being
3481 // allocated and an unnecessary move instruction being generated.
3482 needsTOCRestore = true;
3483 } else if ((CallOpc == PPCISD::CALL) && !isLocalCall(Callee)) {
3484 // Otherwise insert NOP for non-local calls.
3485 CallOpc = PPCISD::CALL_NOP;
3489 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
3490 InFlag = Chain.getValue(1);
3492 if (needsTOCRestore) {
3493 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3494 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3495 InFlag = Chain.getValue(1);
3498 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3499 DAG.getIntPtrConstant(BytesCalleePops, true),
3502 InFlag = Chain.getValue(1);
3504 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3505 Ins, dl, DAG, InVals);
3509 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3510 SmallVectorImpl<SDValue> &InVals) const {
3511 SelectionDAG &DAG = CLI.DAG;
3512 DebugLoc &dl = CLI.DL;
3513 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
3514 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
3515 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
3516 SDValue Chain = CLI.Chain;
3517 SDValue Callee = CLI.Callee;
3518 bool &isTailCall = CLI.IsTailCall;
3519 CallingConv::ID CallConv = CLI.CallConv;
3520 bool isVarArg = CLI.IsVarArg;
3523 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3526 if (PPCSubTarget.isSVR4ABI()) {
3527 if (PPCSubTarget.isPPC64())
3528 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3529 isTailCall, Outs, OutVals, Ins,
3532 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3533 isTailCall, Outs, OutVals, Ins,
3537 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3538 isTailCall, Outs, OutVals, Ins,
3543 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3544 CallingConv::ID CallConv, bool isVarArg,
3546 const SmallVectorImpl<ISD::OutputArg> &Outs,
3547 const SmallVectorImpl<SDValue> &OutVals,
3548 const SmallVectorImpl<ISD::InputArg> &Ins,
3549 DebugLoc dl, SelectionDAG &DAG,
3550 SmallVectorImpl<SDValue> &InVals) const {
3551 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3552 // of the 32-bit SVR4 ABI stack frame layout.
3554 assert((CallConv == CallingConv::C ||
3555 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3557 unsigned PtrByteSize = 4;
3559 MachineFunction &MF = DAG.getMachineFunction();
3561 // Mark this function as potentially containing a function that contains a
3562 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3563 // and restoring the callers stack pointer in this functions epilog. This is
3564 // done because by tail calling the called function might overwrite the value
3565 // in this function's (MF) stack pointer stack slot 0(SP).
3566 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3567 CallConv == CallingConv::Fast)
3568 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3570 // Count how many bytes are to be pushed on the stack, including the linkage
3571 // area, parameter list area and the part of the local variable space which
3572 // contains copies of aggregates which are passed by value.
3574 // Assign locations to all of the outgoing arguments.
3575 SmallVector<CCValAssign, 16> ArgLocs;
3576 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3577 getTargetMachine(), ArgLocs, *DAG.getContext());
3579 // Reserve space for the linkage area on the stack.
3580 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3583 // Handle fixed and variable vector arguments differently.
3584 // Fixed vector arguments go into registers as long as registers are
3585 // available. Variable vector arguments always go into memory.
3586 unsigned NumArgs = Outs.size();
3588 for (unsigned i = 0; i != NumArgs; ++i) {
3589 MVT ArgVT = Outs[i].VT;
3590 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3593 if (Outs[i].IsFixed) {
3594 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3597 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3603 errs() << "Call operand #" << i << " has unhandled type "
3604 << EVT(ArgVT).getEVTString() << "\n";
3606 llvm_unreachable(0);
3610 // All arguments are treated the same.
3611 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3614 // Assign locations to all of the outgoing aggregate by value arguments.
3615 SmallVector<CCValAssign, 16> ByValArgLocs;
3616 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3617 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3619 // Reserve stack space for the allocations in CCInfo.
3620 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3622 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3624 // Size of the linkage area, parameter list area and the part of the local
3625 // space variable where copies of aggregates which are passed by value are
3627 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3629 // Calculate by how many bytes the stack has to be adjusted in case of tail
3630 // call optimization.
3631 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3633 // Adjust the stack pointer for the new arguments...
3634 // These operations are automatically eliminated by the prolog/epilog pass
3635 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3636 SDValue CallSeqStart = Chain;
3638 // Load the return address and frame pointer so it can be moved somewhere else
3641 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3644 // Set up a copy of the stack pointer for use loading and storing any
3645 // arguments that may not fit in the registers available for argument
3647 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3649 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3650 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3651 SmallVector<SDValue, 8> MemOpChains;
3653 bool seenFloatArg = false;
3654 // Walk the register/memloc assignments, inserting copies/loads.
3655 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3658 CCValAssign &VA = ArgLocs[i];
3659 SDValue Arg = OutVals[i];
3660 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3662 if (Flags.isByVal()) {
3663 // Argument is an aggregate which is passed by value, thus we need to
3664 // create a copy of it in the local variable space of the current stack
3665 // frame (which is the stack frame of the caller) and pass the address of
3666 // this copy to the callee.
3667 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3668 CCValAssign &ByValVA = ByValArgLocs[j++];
3669 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3671 // Memory reserved in the local variable space of the callers stack frame.
3672 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3674 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3675 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3677 // Create a copy of the argument in the local area of the current
3679 SDValue MemcpyCall =
3680 CreateCopyOfByValArgument(Arg, PtrOff,
3681 CallSeqStart.getNode()->getOperand(0),
3684 // This must go outside the CALLSEQ_START..END.
3685 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3686 CallSeqStart.getNode()->getOperand(1));
3687 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3688 NewCallSeqStart.getNode());
3689 Chain = CallSeqStart = NewCallSeqStart;
3691 // Pass the address of the aggregate copy on the stack either in a
3692 // physical register or in the parameter list area of the current stack
3693 // frame to the callee.
3697 if (VA.isRegLoc()) {
3698 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3699 // Put argument in a physical register.
3700 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3702 // Put argument in the parameter list area of the current stack frame.
3703 assert(VA.isMemLoc());
3704 unsigned LocMemOffset = VA.getLocMemOffset();
3707 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3708 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3710 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3711 MachinePointerInfo(),
3714 // Calculate and remember argument location.
3715 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3721 if (!MemOpChains.empty())
3722 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3723 &MemOpChains[0], MemOpChains.size());
3725 // Build a sequence of copy-to-reg nodes chained together with token chain
3726 // and flag operands which copy the outgoing args into the appropriate regs.
3728 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3729 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3730 RegsToPass[i].second, InFlag);
3731 InFlag = Chain.getValue(1);
3734 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3737 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3738 SDValue Ops[] = { Chain, InFlag };
3740 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3741 dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
3743 InFlag = Chain.getValue(1);
3747 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3748 false, TailCallArguments);
3750 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3751 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3755 // Copy an argument into memory, being careful to do this outside the
3756 // call sequence for the call to which the argument belongs.
3758 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3759 SDValue CallSeqStart,
3760 ISD::ArgFlagsTy Flags,
3762 DebugLoc dl) const {
3763 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3764 CallSeqStart.getNode()->getOperand(0),
3766 // The MEMCPY must go outside the CALLSEQ_START..END.
3767 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3768 CallSeqStart.getNode()->getOperand(1));
3769 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3770 NewCallSeqStart.getNode());
3771 return NewCallSeqStart;
3775 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3776 CallingConv::ID CallConv, bool isVarArg,
3778 const SmallVectorImpl<ISD::OutputArg> &Outs,
3779 const SmallVectorImpl<SDValue> &OutVals,
3780 const SmallVectorImpl<ISD::InputArg> &Ins,
3781 DebugLoc dl, SelectionDAG &DAG,
3782 SmallVectorImpl<SDValue> &InVals) const {
3784 unsigned NumOps = Outs.size();
3786 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3787 unsigned PtrByteSize = 8;
3789 MachineFunction &MF = DAG.getMachineFunction();
3791 // Mark this function as potentially containing a function that contains a
3792 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3793 // and restoring the callers stack pointer in this functions epilog. This is
3794 // done because by tail calling the called function might overwrite the value
3795 // in this function's (MF) stack pointer stack slot 0(SP).
3796 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3797 CallConv == CallingConv::Fast)
3798 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3800 unsigned nAltivecParamsAtEnd = 0;
3802 // Count how many bytes are to be pushed on the stack, including the linkage
3803 // area, and parameter passing area. We start with at least 48 bytes, which
3804 // is reserved space for [SP][CR][LR][3 x unused].
3805 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
3808 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
3809 Outs, OutVals, nAltivecParamsAtEnd);
3811 // Calculate by how many bytes the stack has to be adjusted in case of tail
3812 // call optimization.
3813 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3815 // To protect arguments on the stack from being clobbered in a tail call,
3816 // force all the loads to happen before doing any other lowering.
3818 Chain = DAG.getStackArgumentTokenFactor(Chain);
3820 // Adjust the stack pointer for the new arguments...
3821 // These operations are automatically eliminated by the prolog/epilog pass
3822 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3823 SDValue CallSeqStart = Chain;
3825 // Load the return address and frame pointer so it can be move somewhere else
3828 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3831 // Set up a copy of the stack pointer for use loading and storing any
3832 // arguments that may not fit in the registers available for argument
3834 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3836 // Figure out which arguments are going to go in registers, and which in
3837 // memory. Also, if this is a vararg function, floating point operations
3838 // must be stored to our stack, and loaded into integer regs as well, if
3839 // any integer regs are available for argument passing.
3840 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
3841 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3843 static const uint16_t GPR[] = {
3844 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3845 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3847 static const uint16_t *FPR = GetFPR();
3849 static const uint16_t VR[] = {
3850 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3851 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3853 const unsigned NumGPRs = array_lengthof(GPR);
3854 const unsigned NumFPRs = 13;
3855 const unsigned NumVRs = array_lengthof(VR);
3857 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3858 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3860 SmallVector<SDValue, 8> MemOpChains;
3861 for (unsigned i = 0; i != NumOps; ++i) {
3862 SDValue Arg = OutVals[i];
3863 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3865 // PtrOff will be used to store the current argument to the stack if a
3866 // register cannot be found for it.
3869 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3871 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3873 // Promote integers to 64-bit values.
3874 if (Arg.getValueType() == MVT::i32) {
3875 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3876 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3877 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3880 // FIXME memcpy is used way more than necessary. Correctness first.
3881 // Note: "by value" is code for passing a structure by value, not
3883 if (Flags.isByVal()) {
3884 // Note: Size includes alignment padding, so
3885 // struct x { short a; char b; }
3886 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
3887 // These are the proper values we need for right-justifying the
3888 // aggregate in a parameter register.
3889 unsigned Size = Flags.getByValSize();
3891 // An empty aggregate parameter takes up no storage and no
3896 // All aggregates smaller than 8 bytes must be passed right-justified.
3897 if (Size==1 || Size==2 || Size==4) {
3898 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
3899 if (GPR_idx != NumGPRs) {
3900 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3901 MachinePointerInfo(), VT,
3903 MemOpChains.push_back(Load.getValue(1));
3904 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3906 ArgOffset += PtrByteSize;
3911 if (GPR_idx == NumGPRs && Size < 8) {
3912 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3913 PtrOff.getValueType());
3914 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3915 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3918 ArgOffset += PtrByteSize;
3921 // Copy entire object into memory. There are cases where gcc-generated
3922 // code assumes it is there, even if it could be put entirely into
3923 // registers. (This is not what the doc says.)
3925 // FIXME: The above statement is likely due to a misunderstanding of the
3926 // documents. All arguments must be copied into the parameter area BY
3927 // THE CALLEE in the event that the callee takes the address of any
3928 // formal argument. That has not yet been implemented. However, it is
3929 // reasonable to use the stack area as a staging area for the register
3932 // Skip this for small aggregates, as we will use the same slot for a
3933 // right-justified copy, below.
3935 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
3939 // When a register is available, pass a small aggregate right-justified.
3940 if (Size < 8 && GPR_idx != NumGPRs) {
3941 // The easiest way to get this right-justified in a register
3942 // is to copy the structure into the rightmost portion of a
3943 // local variable slot, then load the whole slot into the
3945 // FIXME: The memcpy seems to produce pretty awful code for
3946 // small aggregates, particularly for packed ones.
3947 // FIXME: It would be preferable to use the slot in the
3948 // parameter save area instead of a new local variable.
3949 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
3950 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3951 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3955 // Load the slot into the register.
3956 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
3957 MachinePointerInfo(),
3958 false, false, false, 0);
3959 MemOpChains.push_back(Load.getValue(1));
3960 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3962 // Done with this argument.
3963 ArgOffset += PtrByteSize;
3967 // For aggregates larger than PtrByteSize, copy the pieces of the
3968 // object that fit into registers from the parameter save area.
3969 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3970 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3971 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3972 if (GPR_idx != NumGPRs) {
3973 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3974 MachinePointerInfo(),
3975 false, false, false, 0);
3976 MemOpChains.push_back(Load.getValue(1));
3977 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3978 ArgOffset += PtrByteSize;
3980 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3987 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3988 default: llvm_unreachable("Unexpected ValueType for argument!");
3991 if (GPR_idx != NumGPRs) {
3992 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3994 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3995 true, isTailCall, false, MemOpChains,
3996 TailCallArguments, dl);
3998 ArgOffset += PtrByteSize;
4002 if (FPR_idx != NumFPRs) {
4003 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4006 // A single float or an aggregate containing only a single float
4007 // must be passed right-justified in the stack doubleword, and
4008 // in the GPR, if one is available.
4010 if (Arg.getValueType().getSimpleVT().SimpleTy == MVT::f32) {
4011 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4012 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4016 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
4017 MachinePointerInfo(), false, false, 0);
4018 MemOpChains.push_back(Store);
4020 // Float varargs are always shadowed in available integer registers
4021 if (GPR_idx != NumGPRs) {
4022 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4023 MachinePointerInfo(), false, false,
4025 MemOpChains.push_back(Load.getValue(1));
4026 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4028 } else if (GPR_idx != NumGPRs)
4029 // If we have any FPRs remaining, we may also have GPRs remaining.
4032 // Single-precision floating-point values are mapped to the
4033 // second (rightmost) word of the stack doubleword.
4034 if (Arg.getValueType() == MVT::f32) {
4035 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4036 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4039 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4040 true, isTailCall, false, MemOpChains,
4041 TailCallArguments, dl);
4050 // These go aligned on the stack, or in the corresponding R registers
4051 // when within range. The Darwin PPC ABI doc claims they also go in
4052 // V registers; in fact gcc does this only for arguments that are
4053 // prototyped, not for those that match the ... We do it for all
4054 // arguments, seems to work.
4055 while (ArgOffset % 16 !=0) {
4056 ArgOffset += PtrByteSize;
4057 if (GPR_idx != NumGPRs)
4060 // We could elide this store in the case where the object fits
4061 // entirely in R registers. Maybe later.
4062 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4063 DAG.getConstant(ArgOffset, PtrVT));
4064 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4065 MachinePointerInfo(), false, false, 0);
4066 MemOpChains.push_back(Store);
4067 if (VR_idx != NumVRs) {
4068 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4069 MachinePointerInfo(),
4070 false, false, false, 0);
4071 MemOpChains.push_back(Load.getValue(1));
4072 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4075 for (unsigned i=0; i<16; i+=PtrByteSize) {
4076 if (GPR_idx == NumGPRs)
4078 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4079 DAG.getConstant(i, PtrVT));
4080 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4081 false, false, false, 0);
4082 MemOpChains.push_back(Load.getValue(1));
4083 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4088 // Non-varargs Altivec params generally go in registers, but have
4089 // stack space allocated at the end.
4090 if (VR_idx != NumVRs) {
4091 // Doesn't have GPR space allocated.
4092 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4094 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4095 true, isTailCall, true, MemOpChains,
4096 TailCallArguments, dl);
4103 if (!MemOpChains.empty())
4104 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4105 &MemOpChains[0], MemOpChains.size());
4107 // Check if this is an indirect call (MTCTR/BCTRL).
4108 // See PrepareCall() for more information about calls through function
4109 // pointers in the 64-bit SVR4 ABI.
4111 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4112 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4113 !isBLACompatibleAddress(Callee, DAG)) {
4114 // Load r2 into a virtual register and store it to the TOC save area.
4115 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4116 // TOC save area offset.
4117 SDValue PtrOff = DAG.getIntPtrConstant(40);
4118 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4119 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4121 // R12 must contain the address of an indirect callee. This does not
4122 // mean the MTCTR instruction must use R12; it's easier to model this
4123 // as an extra parameter, so do that.
4124 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4127 // Build a sequence of copy-to-reg nodes chained together with token chain
4128 // and flag operands which copy the outgoing args into the appropriate regs.
4130 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4131 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4132 RegsToPass[i].second, InFlag);
4133 InFlag = Chain.getValue(1);
4137 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4138 FPOp, true, TailCallArguments);
4140 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4141 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4146 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4147 CallingConv::ID CallConv, bool isVarArg,
4149 const SmallVectorImpl<ISD::OutputArg> &Outs,
4150 const SmallVectorImpl<SDValue> &OutVals,
4151 const SmallVectorImpl<ISD::InputArg> &Ins,
4152 DebugLoc dl, SelectionDAG &DAG,
4153 SmallVectorImpl<SDValue> &InVals) const {
4155 unsigned NumOps = Outs.size();
4157 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4158 bool isPPC64 = PtrVT == MVT::i64;
4159 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4161 MachineFunction &MF = DAG.getMachineFunction();
4163 // Mark this function as potentially containing a function that contains a
4164 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4165 // and restoring the callers stack pointer in this functions epilog. This is
4166 // done because by tail calling the called function might overwrite the value
4167 // in this function's (MF) stack pointer stack slot 0(SP).
4168 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4169 CallConv == CallingConv::Fast)
4170 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4172 unsigned nAltivecParamsAtEnd = 0;
4174 // Count how many bytes are to be pushed on the stack, including the linkage
4175 // area, and parameter passing area. We start with 24/48 bytes, which is
4176 // prereserved space for [SP][CR][LR][3 x unused].
4178 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4180 nAltivecParamsAtEnd);
4182 // Calculate by how many bytes the stack has to be adjusted in case of tail
4183 // call optimization.
4184 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4186 // To protect arguments on the stack from being clobbered in a tail call,
4187 // force all the loads to happen before doing any other lowering.
4189 Chain = DAG.getStackArgumentTokenFactor(Chain);
4191 // Adjust the stack pointer for the new arguments...
4192 // These operations are automatically eliminated by the prolog/epilog pass
4193 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
4194 SDValue CallSeqStart = Chain;
4196 // Load the return address and frame pointer so it can be move somewhere else
4199 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4202 // Set up a copy of the stack pointer for use loading and storing any
4203 // arguments that may not fit in the registers available for argument
4207 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4209 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4211 // Figure out which arguments are going to go in registers, and which in
4212 // memory. Also, if this is a vararg function, floating point operations
4213 // must be stored to our stack, and loaded into integer regs as well, if
4214 // any integer regs are available for argument passing.
4215 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4216 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4218 static const uint16_t GPR_32[] = { // 32-bit registers.
4219 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4220 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4222 static const uint16_t GPR_64[] = { // 64-bit registers.
4223 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4224 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4226 static const uint16_t *FPR = GetFPR();
4228 static const uint16_t VR[] = {
4229 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4230 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4232 const unsigned NumGPRs = array_lengthof(GPR_32);
4233 const unsigned NumFPRs = 13;
4234 const unsigned NumVRs = array_lengthof(VR);
4236 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4238 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4239 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4241 SmallVector<SDValue, 8> MemOpChains;
4242 for (unsigned i = 0; i != NumOps; ++i) {
4243 SDValue Arg = OutVals[i];
4244 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4246 // PtrOff will be used to store the current argument to the stack if a
4247 // register cannot be found for it.
4250 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4252 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4254 // On PPC64, promote integers to 64-bit values.
4255 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4256 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4257 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4258 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4261 // FIXME memcpy is used way more than necessary. Correctness first.
4262 // Note: "by value" is code for passing a structure by value, not
4264 if (Flags.isByVal()) {
4265 unsigned Size = Flags.getByValSize();
4266 // Very small objects are passed right-justified. Everything else is
4267 // passed left-justified.
4268 if (Size==1 || Size==2) {
4269 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4270 if (GPR_idx != NumGPRs) {
4271 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4272 MachinePointerInfo(), VT,
4274 MemOpChains.push_back(Load.getValue(1));
4275 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4277 ArgOffset += PtrByteSize;
4279 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4280 PtrOff.getValueType());
4281 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4282 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4285 ArgOffset += PtrByteSize;
4289 // Copy entire object into memory. There are cases where gcc-generated
4290 // code assumes it is there, even if it could be put entirely into
4291 // registers. (This is not what the doc says.)
4292 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4296 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4297 // copy the pieces of the object that fit into registers from the
4298 // parameter save area.
4299 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4300 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4301 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4302 if (GPR_idx != NumGPRs) {
4303 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4304 MachinePointerInfo(),
4305 false, false, false, 0);
4306 MemOpChains.push_back(Load.getValue(1));
4307 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4308 ArgOffset += PtrByteSize;
4310 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4317 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
4318 default: llvm_unreachable("Unexpected ValueType for argument!");
4321 if (GPR_idx != NumGPRs) {
4322 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4324 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4325 isPPC64, isTailCall, false, MemOpChains,
4326 TailCallArguments, dl);
4328 ArgOffset += PtrByteSize;
4332 if (FPR_idx != NumFPRs) {
4333 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4336 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4337 MachinePointerInfo(), false, false, 0);
4338 MemOpChains.push_back(Store);
4340 // Float varargs are always shadowed in available integer registers
4341 if (GPR_idx != NumGPRs) {
4342 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4343 MachinePointerInfo(), false, false,
4345 MemOpChains.push_back(Load.getValue(1));
4346 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4348 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4349 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4350 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4351 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4352 MachinePointerInfo(),
4353 false, false, false, 0);
4354 MemOpChains.push_back(Load.getValue(1));
4355 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4358 // If we have any FPRs remaining, we may also have GPRs remaining.
4359 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4361 if (GPR_idx != NumGPRs)
4363 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4364 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4368 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4369 isPPC64, isTailCall, false, MemOpChains,
4370 TailCallArguments, dl);
4374 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4381 // These go aligned on the stack, or in the corresponding R registers
4382 // when within range. The Darwin PPC ABI doc claims they also go in
4383 // V registers; in fact gcc does this only for arguments that are
4384 // prototyped, not for those that match the ... We do it for all
4385 // arguments, seems to work.
4386 while (ArgOffset % 16 !=0) {
4387 ArgOffset += PtrByteSize;
4388 if (GPR_idx != NumGPRs)
4391 // We could elide this store in the case where the object fits
4392 // entirely in R registers. Maybe later.
4393 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4394 DAG.getConstant(ArgOffset, PtrVT));
4395 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4396 MachinePointerInfo(), false, false, 0);
4397 MemOpChains.push_back(Store);
4398 if (VR_idx != NumVRs) {
4399 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4400 MachinePointerInfo(),
4401 false, false, false, 0);
4402 MemOpChains.push_back(Load.getValue(1));
4403 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4406 for (unsigned i=0; i<16; i+=PtrByteSize) {
4407 if (GPR_idx == NumGPRs)
4409 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4410 DAG.getConstant(i, PtrVT));
4411 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4412 false, false, false, 0);
4413 MemOpChains.push_back(Load.getValue(1));
4414 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4419 // Non-varargs Altivec params generally go in registers, but have
4420 // stack space allocated at the end.
4421 if (VR_idx != NumVRs) {
4422 // Doesn't have GPR space allocated.
4423 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4424 } else if (nAltivecParamsAtEnd==0) {
4425 // We are emitting Altivec params in order.
4426 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4427 isPPC64, isTailCall, true, MemOpChains,
4428 TailCallArguments, dl);
4434 // If all Altivec parameters fit in registers, as they usually do,
4435 // they get stack space following the non-Altivec parameters. We
4436 // don't track this here because nobody below needs it.
4437 // If there are more Altivec parameters than fit in registers emit
4439 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4441 // Offset is aligned; skip 1st 12 params which go in V registers.
4442 ArgOffset = ((ArgOffset+15)/16)*16;
4444 for (unsigned i = 0; i != NumOps; ++i) {
4445 SDValue Arg = OutVals[i];
4446 EVT ArgType = Outs[i].VT;
4447 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4448 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4451 // We are emitting Altivec params in order.
4452 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4453 isPPC64, isTailCall, true, MemOpChains,
4454 TailCallArguments, dl);
4461 if (!MemOpChains.empty())
4462 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4463 &MemOpChains[0], MemOpChains.size());
4465 // On Darwin, R12 must contain the address of an indirect callee. This does
4466 // not mean the MTCTR instruction must use R12; it's easier to model this as
4467 // an extra parameter, so do that.
4469 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4470 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4471 !isBLACompatibleAddress(Callee, DAG))
4472 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4473 PPC::R12), Callee));
4475 // Build a sequence of copy-to-reg nodes chained together with token chain
4476 // and flag operands which copy the outgoing args into the appropriate regs.
4478 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4479 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4480 RegsToPass[i].second, InFlag);
4481 InFlag = Chain.getValue(1);
4485 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4486 FPOp, true, TailCallArguments);
4488 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4489 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4494 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4495 MachineFunction &MF, bool isVarArg,
4496 const SmallVectorImpl<ISD::OutputArg> &Outs,
4497 LLVMContext &Context) const {
4498 SmallVector<CCValAssign, 16> RVLocs;
4499 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4501 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4505 PPCTargetLowering::LowerReturn(SDValue Chain,
4506 CallingConv::ID CallConv, bool isVarArg,
4507 const SmallVectorImpl<ISD::OutputArg> &Outs,
4508 const SmallVectorImpl<SDValue> &OutVals,
4509 DebugLoc dl, SelectionDAG &DAG) const {
4511 SmallVector<CCValAssign, 16> RVLocs;
4512 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4513 getTargetMachine(), RVLocs, *DAG.getContext());
4514 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4517 SmallVector<SDValue, 4> RetOps(1, Chain);
4519 // Copy the result values into the output registers.
4520 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4521 CCValAssign &VA = RVLocs[i];
4522 assert(VA.isRegLoc() && "Can only return in registers!");
4524 SDValue Arg = OutVals[i];
4526 switch (VA.getLocInfo()) {
4527 default: llvm_unreachable("Unknown loc info!");
4528 case CCValAssign::Full: break;
4529 case CCValAssign::AExt:
4530 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4532 case CCValAssign::ZExt:
4533 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4535 case CCValAssign::SExt:
4536 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4540 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4541 Flag = Chain.getValue(1);
4542 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4545 RetOps[0] = Chain; // Update chain.
4547 // Add the flag if we have it.
4549 RetOps.push_back(Flag);
4551 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4552 &RetOps[0], RetOps.size());
4555 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4556 const PPCSubtarget &Subtarget) const {
4557 // When we pop the dynamic allocation we need to restore the SP link.
4558 DebugLoc dl = Op.getDebugLoc();
4560 // Get the corect type for pointers.
4561 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4563 // Construct the stack pointer operand.
4564 bool isPPC64 = Subtarget.isPPC64();
4565 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4566 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4568 // Get the operands for the STACKRESTORE.
4569 SDValue Chain = Op.getOperand(0);
4570 SDValue SaveSP = Op.getOperand(1);
4572 // Load the old link SP.
4573 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4574 MachinePointerInfo(),
4575 false, false, false, 0);
4577 // Restore the stack pointer.
4578 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4580 // Store the old link SP.
4581 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4588 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4589 MachineFunction &MF = DAG.getMachineFunction();
4590 bool isPPC64 = PPCSubTarget.isPPC64();
4591 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4592 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4594 // Get current frame pointer save index. The users of this index will be
4595 // primarily DYNALLOC instructions.
4596 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4597 int RASI = FI->getReturnAddrSaveIndex();
4599 // If the frame pointer save index hasn't been defined yet.
4601 // Find out what the fix offset of the frame pointer save area.
4602 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4603 // Allocate the frame index for frame pointer save area.
4604 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4606 FI->setReturnAddrSaveIndex(RASI);
4608 return DAG.getFrameIndex(RASI, PtrVT);
4612 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4613 MachineFunction &MF = DAG.getMachineFunction();
4614 bool isPPC64 = PPCSubTarget.isPPC64();
4615 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4616 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4618 // Get current frame pointer save index. The users of this index will be
4619 // primarily DYNALLOC instructions.
4620 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4621 int FPSI = FI->getFramePointerSaveIndex();
4623 // If the frame pointer save index hasn't been defined yet.
4625 // Find out what the fix offset of the frame pointer save area.
4626 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4629 // Allocate the frame index for frame pointer save area.
4630 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4632 FI->setFramePointerSaveIndex(FPSI);
4634 return DAG.getFrameIndex(FPSI, PtrVT);
4637 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4639 const PPCSubtarget &Subtarget) const {
4641 SDValue Chain = Op.getOperand(0);
4642 SDValue Size = Op.getOperand(1);
4643 DebugLoc dl = Op.getDebugLoc();
4645 // Get the corect type for pointers.
4646 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4648 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4649 DAG.getConstant(0, PtrVT), Size);
4650 // Construct a node for the frame pointer save index.
4651 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4652 // Build a DYNALLOC node.
4653 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4654 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4655 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
4658 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4659 SelectionDAG &DAG) const {
4660 DebugLoc DL = Op.getDebugLoc();
4661 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4662 DAG.getVTList(MVT::i32, MVT::Other),
4663 Op.getOperand(0), Op.getOperand(1));
4666 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4667 SelectionDAG &DAG) const {
4668 DebugLoc DL = Op.getDebugLoc();
4669 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4670 Op.getOperand(0), Op.getOperand(1));
4673 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4675 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4676 // Not FP? Not a fsel.
4677 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4678 !Op.getOperand(2).getValueType().isFloatingPoint())
4681 // We might be able to do better than this under some circumstances, but in
4682 // general, fsel-based lowering of select is a finite-math-only optimization.
4683 // For more information, see section F.3 of the 2.06 ISA specification.
4684 if (!DAG.getTarget().Options.NoInfsFPMath ||
4685 !DAG.getTarget().Options.NoNaNsFPMath)
4688 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4690 EVT ResVT = Op.getValueType();
4691 EVT CmpVT = Op.getOperand(0).getValueType();
4692 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4693 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4694 DebugLoc dl = Op.getDebugLoc();
4696 // If the RHS of the comparison is a 0.0, we don't need to do the
4697 // subtraction at all.
4699 if (isFloatingPointZero(RHS))
4701 default: break; // SETUO etc aren't handled by fsel.
4705 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4706 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4707 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4708 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4709 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4710 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4711 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
4714 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4717 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4718 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4719 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4722 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4725 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4726 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4727 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4728 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4733 default: break; // SETUO etc aren't handled by fsel.
4737 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4738 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4739 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4740 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4741 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4742 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4743 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4744 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
4747 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4748 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4749 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4750 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4753 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4754 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4755 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4756 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4759 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4760 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4761 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4762 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4765 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4766 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4767 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4768 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4773 // FIXME: Split this code up when LegalizeDAGTypes lands.
4774 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
4775 DebugLoc dl) const {
4776 assert(Op.getOperand(0).getValueType().isFloatingPoint());
4777 SDValue Src = Op.getOperand(0);
4778 if (Src.getValueType() == MVT::f32)
4779 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4782 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4783 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
4785 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4786 (PPCSubTarget.hasFPCVT() ? PPCISD::FCTIWUZ :
4791 assert((Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT()) &&
4792 "i64 FP_TO_UINT is supported only with FPCVT");
4793 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
4799 // Convert the FP value to an int value through memory.
4800 bool i32Stack = Op.getValueType() == MVT::i32 && PPCSubTarget.hasSTFIWX() &&
4801 (Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT());
4802 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
4803 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
4804 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
4806 // Emit a store to the stack slot.
4809 MachineFunction &MF = DAG.getMachineFunction();
4810 MachineMemOperand *MMO =
4811 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
4812 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
4813 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
4814 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
4817 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
4818 MPI, false, false, 0);
4820 // Result is a load from the stack slot. If loading 4 bytes, make sure to
4822 if (Op.getValueType() == MVT::i32 && !i32Stack) {
4823 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
4824 DAG.getConstant(4, FIPtr.getValueType()));
4825 MPI = MachinePointerInfo();
4828 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
4829 false, false, false, 0);
4832 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
4833 SelectionDAG &DAG) const {
4834 DebugLoc dl = Op.getDebugLoc();
4835 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
4836 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4839 assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) &&
4840 "UINT_TO_FP is supported only with FPCVT");
4842 // If we have FCFIDS, then use it when converting to single-precision.
4843 // Otherwise, convert to double-precision and then round.
4844 unsigned FCFOp = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4845 (Op.getOpcode() == ISD::UINT_TO_FP ?
4846 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
4847 (Op.getOpcode() == ISD::UINT_TO_FP ?
4848 PPCISD::FCFIDU : PPCISD::FCFID);
4849 MVT FCFTy = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4850 MVT::f32 : MVT::f64;
4852 if (Op.getOperand(0).getValueType() == MVT::i64) {
4853 SDValue SINT = Op.getOperand(0);
4854 // When converting to single-precision, we actually need to convert
4855 // to double-precision first and then round to single-precision.
4856 // To avoid double-rounding effects during that operation, we have
4857 // to prepare the input operand. Bits that might be truncated when
4858 // converting to double-precision are replaced by a bit that won't
4859 // be lost at this stage, but is below the single-precision rounding
4862 // However, if -enable-unsafe-fp-math is in effect, accept double
4863 // rounding to avoid the extra overhead.
4864 if (Op.getValueType() == MVT::f32 &&
4865 !PPCSubTarget.hasFPCVT() &&
4866 !DAG.getTarget().Options.UnsafeFPMath) {
4868 // Twiddle input to make sure the low 11 bits are zero. (If this
4869 // is the case, we are guaranteed the value will fit into the 53 bit
4870 // mantissa of an IEEE double-precision value without rounding.)
4871 // If any of those low 11 bits were not zero originally, make sure
4872 // bit 12 (value 2048) is set instead, so that the final rounding
4873 // to single-precision gets the correct result.
4874 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4875 SINT, DAG.getConstant(2047, MVT::i64));
4876 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4877 Round, DAG.getConstant(2047, MVT::i64));
4878 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4879 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4880 Round, DAG.getConstant(-2048, MVT::i64));
4882 // However, we cannot use that value unconditionally: if the magnitude
4883 // of the input value is small, the bit-twiddling we did above might
4884 // end up visibly changing the output. Fortunately, in that case, we
4885 // don't need to twiddle bits since the original input will convert
4886 // exactly to double-precision floating-point already. Therefore,
4887 // construct a conditional to use the original value if the top 11
4888 // bits are all sign-bit copies, and use the rounded value computed
4890 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4891 SINT, DAG.getConstant(53, MVT::i32));
4892 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4893 Cond, DAG.getConstant(1, MVT::i64));
4894 Cond = DAG.getSetCC(dl, MVT::i32,
4895 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4897 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4900 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4901 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
4903 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4904 FP = DAG.getNode(ISD::FP_ROUND, dl,
4905 MVT::f32, FP, DAG.getIntPtrConstant(0));
4909 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
4910 "Unhandled INT_TO_FP type in custom expander!");
4911 // Since we only generate this in 64-bit mode, we can take advantage of
4912 // 64-bit registers. In particular, sign extend the input value into the
4913 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
4914 // then lfd it and fcfid it.
4915 MachineFunction &MF = DAG.getMachineFunction();
4916 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
4917 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4920 if (PPCSubTarget.hasLFIWAX() || PPCSubTarget.hasFPCVT()) {
4921 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
4922 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4924 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
4925 MachinePointerInfo::getFixedStack(FrameIdx),
4928 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
4929 "Expected an i32 store");
4930 MachineMemOperand *MMO =
4931 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
4932 MachineMemOperand::MOLoad, 4, 4);
4933 SDValue Ops[] = { Store, FIdx };
4934 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
4935 PPCISD::LFIWZX : PPCISD::LFIWAX,
4936 dl, DAG.getVTList(MVT::f64, MVT::Other),
4937 Ops, 2, MVT::i32, MMO);
4939 assert(PPCSubTarget.isPPC64() &&
4940 "i32->FP without LFIWAX supported only on PPC64");
4942 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
4943 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4945 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
4948 // STD the extended value into the stack slot.
4949 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
4950 MachinePointerInfo::getFixedStack(FrameIdx),
4953 // Load the value as a double.
4954 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
4955 MachinePointerInfo::getFixedStack(FrameIdx),
4956 false, false, false, 0);
4959 // FCFID it and return it.
4960 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
4961 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4962 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
4966 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4967 SelectionDAG &DAG) const {
4968 DebugLoc dl = Op.getDebugLoc();
4970 The rounding mode is in bits 30:31 of FPSR, and has the following
4977 FLT_ROUNDS, on the other hand, expects the following:
4984 To perform the conversion, we do:
4985 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
4988 MachineFunction &MF = DAG.getMachineFunction();
4989 EVT VT = Op.getValueType();
4990 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4991 SDValue MFFSreg, InFlag;
4993 // Save FP Control Word to register
4995 MVT::f64, // return register
4996 MVT::Glue // unused in this context
4998 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
5000 // Save FP register to stack slot
5001 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5002 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5003 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5004 StackSlot, MachinePointerInfo(), false, false,0);
5006 // Load FP Control Word from low 32 bits of stack slot.
5007 SDValue Four = DAG.getConstant(4, PtrVT);
5008 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5009 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5010 false, false, false, 0);
5012 // Transform as necessary
5014 DAG.getNode(ISD::AND, dl, MVT::i32,
5015 CWD, DAG.getConstant(3, MVT::i32));
5017 DAG.getNode(ISD::SRL, dl, MVT::i32,
5018 DAG.getNode(ISD::AND, dl, MVT::i32,
5019 DAG.getNode(ISD::XOR, dl, MVT::i32,
5020 CWD, DAG.getConstant(3, MVT::i32)),
5021 DAG.getConstant(3, MVT::i32)),
5022 DAG.getConstant(1, MVT::i32));
5025 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5027 return DAG.getNode((VT.getSizeInBits() < 16 ?
5028 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5031 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5032 EVT VT = Op.getValueType();
5033 unsigned BitWidth = VT.getSizeInBits();
5034 DebugLoc dl = Op.getDebugLoc();
5035 assert(Op.getNumOperands() == 3 &&
5036 VT == Op.getOperand(1).getValueType() &&
5039 // Expand into a bunch of logical ops. Note that these ops
5040 // depend on the PPC behavior for oversized shift amounts.
5041 SDValue Lo = Op.getOperand(0);
5042 SDValue Hi = Op.getOperand(1);
5043 SDValue Amt = Op.getOperand(2);
5044 EVT AmtVT = Amt.getValueType();
5046 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5047 DAG.getConstant(BitWidth, AmtVT), Amt);
5048 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5049 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5050 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5051 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5052 DAG.getConstant(-BitWidth, AmtVT));
5053 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5054 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5055 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5056 SDValue OutOps[] = { OutLo, OutHi };
5057 return DAG.getMergeValues(OutOps, 2, dl);
5060 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5061 EVT VT = Op.getValueType();
5062 DebugLoc dl = Op.getDebugLoc();
5063 unsigned BitWidth = VT.getSizeInBits();
5064 assert(Op.getNumOperands() == 3 &&
5065 VT == Op.getOperand(1).getValueType() &&
5068 // Expand into a bunch of logical ops. Note that these ops
5069 // depend on the PPC behavior for oversized shift amounts.
5070 SDValue Lo = Op.getOperand(0);
5071 SDValue Hi = Op.getOperand(1);
5072 SDValue Amt = Op.getOperand(2);
5073 EVT AmtVT = Amt.getValueType();
5075 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5076 DAG.getConstant(BitWidth, AmtVT), Amt);
5077 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5078 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5079 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5080 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5081 DAG.getConstant(-BitWidth, AmtVT));
5082 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5083 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5084 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5085 SDValue OutOps[] = { OutLo, OutHi };
5086 return DAG.getMergeValues(OutOps, 2, dl);
5089 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5090 DebugLoc dl = Op.getDebugLoc();
5091 EVT VT = Op.getValueType();
5092 unsigned BitWidth = VT.getSizeInBits();
5093 assert(Op.getNumOperands() == 3 &&
5094 VT == Op.getOperand(1).getValueType() &&
5097 // Expand into a bunch of logical ops, followed by a select_cc.
5098 SDValue Lo = Op.getOperand(0);
5099 SDValue Hi = Op.getOperand(1);
5100 SDValue Amt = Op.getOperand(2);
5101 EVT AmtVT = Amt.getValueType();
5103 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5104 DAG.getConstant(BitWidth, AmtVT), Amt);
5105 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5106 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5107 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5108 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5109 DAG.getConstant(-BitWidth, AmtVT));
5110 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5111 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5112 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5113 Tmp4, Tmp6, ISD::SETLE);
5114 SDValue OutOps[] = { OutLo, OutHi };
5115 return DAG.getMergeValues(OutOps, 2, dl);
5118 //===----------------------------------------------------------------------===//
5119 // Vector related lowering.
5122 /// BuildSplatI - Build a canonical splati of Val with an element size of
5123 /// SplatSize. Cast the result to VT.
5124 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5125 SelectionDAG &DAG, DebugLoc dl) {
5126 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5128 static const EVT VTys[] = { // canonical VT to use for each size.
5129 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5132 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5134 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5138 EVT CanonicalVT = VTys[SplatSize-1];
5140 // Build a canonical splat for this value.
5141 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5142 SmallVector<SDValue, 8> Ops;
5143 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5144 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
5145 &Ops[0], Ops.size());
5146 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5149 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5150 /// specified intrinsic ID.
5151 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5152 SelectionDAG &DAG, DebugLoc dl,
5153 EVT DestVT = MVT::Other) {
5154 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5155 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5156 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5159 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5160 /// specified intrinsic ID.
5161 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5162 SDValue Op2, SelectionDAG &DAG,
5163 DebugLoc dl, EVT DestVT = MVT::Other) {
5164 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5165 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5166 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5170 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5171 /// amount. The result has the specified value type.
5172 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5173 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
5174 // Force LHS/RHS to be the right type.
5175 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5176 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5179 for (unsigned i = 0; i != 16; ++i)
5181 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5182 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5185 // If this is a case we can't handle, return null and let the default
5186 // expansion code take care of it. If we CAN select this case, and if it
5187 // selects to a single instruction, return Op. Otherwise, if we can codegen
5188 // this case more efficiently than a constant pool load, lower it to the
5189 // sequence of ops that should be used.
5190 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5191 SelectionDAG &DAG) const {
5192 DebugLoc dl = Op.getDebugLoc();
5193 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5194 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5196 // Check if this is a splat of a constant value.
5197 APInt APSplatBits, APSplatUndef;
5198 unsigned SplatBitSize;
5200 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5201 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5204 unsigned SplatBits = APSplatBits.getZExtValue();
5205 unsigned SplatUndef = APSplatUndef.getZExtValue();
5206 unsigned SplatSize = SplatBitSize / 8;
5208 // First, handle single instruction cases.
5211 if (SplatBits == 0) {
5212 // Canonicalize all zero vectors to be v4i32.
5213 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5214 SDValue Z = DAG.getConstant(0, MVT::i32);
5215 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5216 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5221 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5222 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5224 if (SextVal >= -16 && SextVal <= 15)
5225 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5228 // Two instruction sequences.
5230 // If this value is in the range [-32,30] and is even, use:
5231 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5232 // If this value is in the range [17,31] and is odd, use:
5233 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5234 // If this value is in the range [-31,-17] and is odd, use:
5235 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5236 // Note the last two are three-instruction sequences.
5237 if (SextVal >= -32 && SextVal <= 31) {
5238 // To avoid having these optimizations undone by constant folding,
5239 // we convert to a pseudo that will be expanded later into one of
5241 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5242 EVT VT = Op.getValueType();
5243 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5244 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5245 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5248 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5249 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5251 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5252 // Make -1 and vspltisw -1:
5253 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5255 // Make the VSLW intrinsic, computing 0x8000_0000.
5256 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5259 // xor by OnesV to invert it.
5260 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5261 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5264 // Check to see if this is a wide variety of vsplti*, binop self cases.
5265 static const signed char SplatCsts[] = {
5266 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5267 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5270 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5271 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5272 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5273 int i = SplatCsts[idx];
5275 // Figure out what shift amount will be used by altivec if shifted by i in
5277 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5279 // vsplti + shl self.
5280 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5281 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5282 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5283 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5284 Intrinsic::ppc_altivec_vslw
5286 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5287 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5290 // vsplti + srl self.
5291 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5292 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5293 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5294 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5295 Intrinsic::ppc_altivec_vsrw
5297 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5298 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5301 // vsplti + sra self.
5302 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5303 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5304 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5305 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5306 Intrinsic::ppc_altivec_vsraw
5308 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5309 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5312 // vsplti + rol self.
5313 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5314 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5315 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5316 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5317 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5318 Intrinsic::ppc_altivec_vrlw
5320 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5321 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5324 // t = vsplti c, result = vsldoi t, t, 1
5325 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5326 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5327 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5329 // t = vsplti c, result = vsldoi t, t, 2
5330 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5331 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5332 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5334 // t = vsplti c, result = vsldoi t, t, 3
5335 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5336 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5337 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5344 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5345 /// the specified operations to build the shuffle.
5346 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5347 SDValue RHS, SelectionDAG &DAG,
5349 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5350 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5351 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5354 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5366 if (OpNum == OP_COPY) {
5367 if (LHSID == (1*9+2)*9+3) return LHS;
5368 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5372 SDValue OpLHS, OpRHS;
5373 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5374 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5378 default: llvm_unreachable("Unknown i32 permute!");
5380 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5381 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5382 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5383 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5386 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5387 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5388 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5389 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5392 for (unsigned i = 0; i != 16; ++i)
5393 ShufIdxs[i] = (i&3)+0;
5396 for (unsigned i = 0; i != 16; ++i)
5397 ShufIdxs[i] = (i&3)+4;
5400 for (unsigned i = 0; i != 16; ++i)
5401 ShufIdxs[i] = (i&3)+8;
5404 for (unsigned i = 0; i != 16; ++i)
5405 ShufIdxs[i] = (i&3)+12;
5408 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5410 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5412 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5414 EVT VT = OpLHS.getValueType();
5415 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5416 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5417 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5418 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5421 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5422 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5423 /// return the code it can be lowered into. Worst case, it can always be
5424 /// lowered into a vperm.
5425 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5426 SelectionDAG &DAG) const {
5427 DebugLoc dl = Op.getDebugLoc();
5428 SDValue V1 = Op.getOperand(0);
5429 SDValue V2 = Op.getOperand(1);
5430 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5431 EVT VT = Op.getValueType();
5433 // Cases that are handled by instructions that take permute immediates
5434 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5435 // selected by the instruction selector.
5436 if (V2.getOpcode() == ISD::UNDEF) {
5437 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5438 PPC::isSplatShuffleMask(SVOp, 2) ||
5439 PPC::isSplatShuffleMask(SVOp, 4) ||
5440 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5441 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5442 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5443 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5444 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5445 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5446 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5447 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5448 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5453 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5454 // and produce a fixed permutation. If any of these match, do not lower to
5456 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5457 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5458 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5459 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5460 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5461 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5462 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5463 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5464 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5467 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5468 // perfect shuffle table to emit an optimal matching sequence.
5469 ArrayRef<int> PermMask = SVOp->getMask();
5471 unsigned PFIndexes[4];
5472 bool isFourElementShuffle = true;
5473 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5474 unsigned EltNo = 8; // Start out undef.
5475 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5476 if (PermMask[i*4+j] < 0)
5477 continue; // Undef, ignore it.
5479 unsigned ByteSource = PermMask[i*4+j];
5480 if ((ByteSource & 3) != j) {
5481 isFourElementShuffle = false;
5486 EltNo = ByteSource/4;
5487 } else if (EltNo != ByteSource/4) {
5488 isFourElementShuffle = false;
5492 PFIndexes[i] = EltNo;
5495 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5496 // perfect shuffle vector to determine if it is cost effective to do this as
5497 // discrete instructions, or whether we should use a vperm.
5498 if (isFourElementShuffle) {
5499 // Compute the index in the perfect shuffle table.
5500 unsigned PFTableIndex =
5501 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5503 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5504 unsigned Cost = (PFEntry >> 30);
5506 // Determining when to avoid vperm is tricky. Many things affect the cost
5507 // of vperm, particularly how many times the perm mask needs to be computed.
5508 // For example, if the perm mask can be hoisted out of a loop or is already
5509 // used (perhaps because there are multiple permutes with the same shuffle
5510 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5511 // the loop requires an extra register.
5513 // As a compromise, we only emit discrete instructions if the shuffle can be
5514 // generated in 3 or fewer operations. When we have loop information
5515 // available, if this block is within a loop, we should avoid using vperm
5516 // for 3-operation perms and use a constant pool load instead.
5518 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5521 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5522 // vector that will get spilled to the constant pool.
5523 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5525 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5526 // that it is in input element units, not in bytes. Convert now.
5527 EVT EltVT = V1.getValueType().getVectorElementType();
5528 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5530 SmallVector<SDValue, 16> ResultMask;
5531 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5532 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5534 for (unsigned j = 0; j != BytesPerElement; ++j)
5535 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5539 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5540 &ResultMask[0], ResultMask.size());
5541 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5544 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5545 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5546 /// information about the intrinsic.
5547 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5549 unsigned IntrinsicID =
5550 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5553 switch (IntrinsicID) {
5554 default: return false;
5555 // Comparison predicates.
5556 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5557 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5558 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5559 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5560 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5561 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5562 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5563 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5564 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5565 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5566 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5567 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5568 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5570 // Normal Comparisons.
5571 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5572 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5573 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5574 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5575 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5576 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5577 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5578 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5579 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5580 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5581 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5582 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5583 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5588 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5589 /// lower, do it, otherwise return null.
5590 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5591 SelectionDAG &DAG) const {
5592 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5593 // opcode number of the comparison.
5594 DebugLoc dl = Op.getDebugLoc();
5597 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5598 return SDValue(); // Don't custom lower most intrinsics.
5600 // If this is a non-dot comparison, make the VCMP node and we are done.
5602 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5603 Op.getOperand(1), Op.getOperand(2),
5604 DAG.getConstant(CompareOpc, MVT::i32));
5605 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5608 // Create the PPCISD altivec 'dot' comparison node.
5610 Op.getOperand(2), // LHS
5611 Op.getOperand(3), // RHS
5612 DAG.getConstant(CompareOpc, MVT::i32)
5614 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5615 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5617 // Now that we have the comparison, emit a copy from the CR to a GPR.
5618 // This is flagged to the above dot comparison.
5619 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
5620 DAG.getRegister(PPC::CR6, MVT::i32),
5621 CompNode.getValue(1));
5623 // Unpack the result based on how the target uses it.
5624 unsigned BitNo; // Bit # of CR6.
5625 bool InvertBit; // Invert result?
5626 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5627 default: // Can't happen, don't crash on invalid number though.
5628 case 0: // Return the value of the EQ bit of CR6.
5629 BitNo = 0; InvertBit = false;
5631 case 1: // Return the inverted value of the EQ bit of CR6.
5632 BitNo = 0; InvertBit = true;
5634 case 2: // Return the value of the LT bit of CR6.
5635 BitNo = 2; InvertBit = false;
5637 case 3: // Return the inverted value of the LT bit of CR6.
5638 BitNo = 2; InvertBit = true;
5642 // Shift the bit into the low position.
5643 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5644 DAG.getConstant(8-(3-BitNo), MVT::i32));
5646 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5647 DAG.getConstant(1, MVT::i32));
5649 // If we are supposed to, toggle the bit.
5651 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5652 DAG.getConstant(1, MVT::i32));
5656 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5657 SelectionDAG &DAG) const {
5658 DebugLoc dl = Op.getDebugLoc();
5659 // Create a stack slot that is 16-byte aligned.
5660 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5661 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5662 EVT PtrVT = getPointerTy();
5663 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5665 // Store the input value into Value#0 of the stack slot.
5666 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5667 Op.getOperand(0), FIdx, MachinePointerInfo(),
5670 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5671 false, false, false, 0);
5674 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5675 DebugLoc dl = Op.getDebugLoc();
5676 if (Op.getValueType() == MVT::v4i32) {
5677 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5679 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5680 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5682 SDValue RHSSwap = // = vrlw RHS, 16
5683 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
5685 // Shrinkify inputs to v8i16.
5686 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5687 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5688 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5690 // Low parts multiplied together, generating 32-bit results (we ignore the
5692 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
5693 LHS, RHS, DAG, dl, MVT::v4i32);
5695 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
5696 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5697 // Shift the high parts up 16 bits.
5698 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
5700 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5701 } else if (Op.getValueType() == MVT::v8i16) {
5702 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5704 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5706 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
5707 LHS, RHS, Zero, DAG, dl);
5708 } else if (Op.getValueType() == MVT::v16i8) {
5709 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5711 // Multiply the even 8-bit parts, producing 16-bit sums.
5712 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
5713 LHS, RHS, DAG, dl, MVT::v8i16);
5714 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5716 // Multiply the odd 8-bit parts, producing 16-bit sums.
5717 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
5718 LHS, RHS, DAG, dl, MVT::v8i16);
5719 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5721 // Merge the results together.
5723 for (unsigned i = 0; i != 8; ++i) {
5725 Ops[i*2+1] = 2*i+1+16;
5727 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5729 llvm_unreachable("Unknown mul to lower!");
5733 /// LowerOperation - Provide custom lowering hooks for some operations.
5735 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5736 switch (Op.getOpcode()) {
5737 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
5738 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5739 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5740 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5741 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5742 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5743 case ISD::SETCC: return LowerSETCC(Op, DAG);
5744 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
5745 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
5747 return LowerVASTART(Op, DAG, PPCSubTarget);
5750 return LowerVAARG(Op, DAG, PPCSubTarget);
5752 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
5753 case ISD::DYNAMIC_STACKALLOC:
5754 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
5756 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
5757 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
5759 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5760 case ISD::FP_TO_UINT:
5761 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
5763 case ISD::UINT_TO_FP:
5764 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
5765 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5767 // Lower 64-bit shifts.
5768 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
5769 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
5770 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
5772 // Vector-related lowering.
5773 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5774 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5775 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5776 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5777 case ISD::MUL: return LowerMUL(Op, DAG);
5779 // Frame & Return address.
5780 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5781 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5785 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
5786 SmallVectorImpl<SDValue>&Results,
5787 SelectionDAG &DAG) const {
5788 const TargetMachine &TM = getTargetMachine();
5789 DebugLoc dl = N->getDebugLoc();
5790 switch (N->getOpcode()) {
5792 llvm_unreachable("Do not know how to custom type legalize this operation!");
5794 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
5795 || TM.getSubtarget<PPCSubtarget>().isPPC64())
5798 EVT VT = N->getValueType(0);
5800 if (VT == MVT::i64) {
5801 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
5803 Results.push_back(NewNode);
5804 Results.push_back(NewNode.getValue(1));
5808 case ISD::FP_ROUND_INREG: {
5809 assert(N->getValueType(0) == MVT::ppcf128);
5810 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5811 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5812 MVT::f64, N->getOperand(0),
5813 DAG.getIntPtrConstant(0));
5814 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5815 MVT::f64, N->getOperand(0),
5816 DAG.getIntPtrConstant(1));
5818 // Add the two halves of the long double in round-to-zero mode.
5819 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
5821 // We know the low half is about to be thrown away, so just use something
5823 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5827 case ISD::FP_TO_SINT:
5828 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
5834 //===----------------------------------------------------------------------===//
5835 // Other Lowering Code
5836 //===----------------------------------------------------------------------===//
5839 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5840 bool is64bit, unsigned BinOpcode) const {
5841 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5842 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5844 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5845 MachineFunction *F = BB->getParent();
5846 MachineFunction::iterator It = BB;
5849 unsigned dest = MI->getOperand(0).getReg();
5850 unsigned ptrA = MI->getOperand(1).getReg();
5851 unsigned ptrB = MI->getOperand(2).getReg();
5852 unsigned incr = MI->getOperand(3).getReg();
5853 DebugLoc dl = MI->getDebugLoc();
5855 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5856 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5857 F->insert(It, loopMBB);
5858 F->insert(It, exitMBB);
5859 exitMBB->splice(exitMBB->begin(), BB,
5860 llvm::next(MachineBasicBlock::iterator(MI)),
5862 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5864 MachineRegisterInfo &RegInfo = F->getRegInfo();
5865 unsigned TmpReg = (!BinOpcode) ? incr :
5866 RegInfo.createVirtualRegister(
5867 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5868 (const TargetRegisterClass *) &PPC::GPRCRegClass);
5872 // fallthrough --> loopMBB
5873 BB->addSuccessor(loopMBB);
5876 // l[wd]arx dest, ptr
5877 // add r0, dest, incr
5878 // st[wd]cx. r0, ptr
5880 // fallthrough --> exitMBB
5882 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5883 .addReg(ptrA).addReg(ptrB);
5885 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
5886 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5887 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
5888 BuildMI(BB, dl, TII->get(PPC::BCC))
5889 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5890 BB->addSuccessor(loopMBB);
5891 BB->addSuccessor(exitMBB);
5900 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
5901 MachineBasicBlock *BB,
5902 bool is8bit, // operation
5903 unsigned BinOpcode) const {
5904 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5905 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5906 // In 64 bit mode we have to use 64 bits for addresses, even though the
5907 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
5908 // registers without caring whether they're 32 or 64, but here we're
5909 // doing actual arithmetic on the addresses.
5910 bool is64bit = PPCSubTarget.isPPC64();
5911 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
5913 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5914 MachineFunction *F = BB->getParent();
5915 MachineFunction::iterator It = BB;
5918 unsigned dest = MI->getOperand(0).getReg();
5919 unsigned ptrA = MI->getOperand(1).getReg();
5920 unsigned ptrB = MI->getOperand(2).getReg();
5921 unsigned incr = MI->getOperand(3).getReg();
5922 DebugLoc dl = MI->getDebugLoc();
5924 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5925 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5926 F->insert(It, loopMBB);
5927 F->insert(It, exitMBB);
5928 exitMBB->splice(exitMBB->begin(), BB,
5929 llvm::next(MachineBasicBlock::iterator(MI)),
5931 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5933 MachineRegisterInfo &RegInfo = F->getRegInfo();
5934 const TargetRegisterClass *RC =
5935 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5936 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5937 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5938 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5939 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5940 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
5941 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
5942 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
5943 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
5944 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
5945 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
5946 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
5947 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
5949 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
5953 // fallthrough --> loopMBB
5954 BB->addSuccessor(loopMBB);
5956 // The 4-byte load must be aligned, while a char or short may be
5957 // anywhere in the word. Hence all this nasty bookkeeping code.
5958 // add ptr1, ptrA, ptrB [copy if ptrA==0]
5959 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
5960 // xori shift, shift1, 24 [16]
5961 // rlwinm ptr, ptr1, 0, 0, 29
5962 // slw incr2, incr, shift
5963 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
5964 // slw mask, mask2, shift
5966 // lwarx tmpDest, ptr
5967 // add tmp, tmpDest, incr2
5968 // andc tmp2, tmpDest, mask
5969 // and tmp3, tmp, mask
5970 // or tmp4, tmp3, tmp2
5973 // fallthrough --> exitMBB
5974 // srw dest, tmpDest, shift
5975 if (ptrA != ZeroReg) {
5976 Ptr1Reg = RegInfo.createVirtualRegister(RC);
5977 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
5978 .addReg(ptrA).addReg(ptrB);
5982 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5983 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
5984 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5985 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
5987 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
5988 .addReg(Ptr1Reg).addImm(0).addImm(61);
5990 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
5991 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
5992 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
5993 .addReg(incr).addReg(ShiftReg);
5995 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
5997 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
5998 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6000 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6001 .addReg(Mask2Reg).addReg(ShiftReg);
6004 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6005 .addReg(ZeroReg).addReg(PtrReg);
6007 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6008 .addReg(Incr2Reg).addReg(TmpDestReg);
6009 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6010 .addReg(TmpDestReg).addReg(MaskReg);
6011 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6012 .addReg(TmpReg).addReg(MaskReg);
6013 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6014 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6015 BuildMI(BB, dl, TII->get(PPC::STWCX))
6016 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6017 BuildMI(BB, dl, TII->get(PPC::BCC))
6018 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6019 BB->addSuccessor(loopMBB);
6020 BB->addSuccessor(exitMBB);
6025 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6030 llvm::MachineBasicBlock*
6031 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6032 MachineBasicBlock *MBB) const {
6033 DebugLoc DL = MI->getDebugLoc();
6034 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6036 MachineFunction *MF = MBB->getParent();
6037 MachineRegisterInfo &MRI = MF->getRegInfo();
6039 const BasicBlock *BB = MBB->getBasicBlock();
6040 MachineFunction::iterator I = MBB;
6044 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6045 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6047 unsigned DstReg = MI->getOperand(0).getReg();
6048 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6049 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6050 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6051 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6053 MVT PVT = getPointerTy();
6054 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6055 "Invalid Pointer Size!");
6056 // For v = setjmp(buf), we generate
6059 // SjLjSetup mainMBB
6065 // buf[LabelOffset] = LR
6069 // v = phi(main, restore)
6072 MachineBasicBlock *thisMBB = MBB;
6073 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6074 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6075 MF->insert(I, mainMBB);
6076 MF->insert(I, sinkMBB);
6078 MachineInstrBuilder MIB;
6080 // Transfer the remainder of BB and its successor edges to sinkMBB.
6081 sinkMBB->splice(sinkMBB->begin(), MBB,
6082 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
6083 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6085 // Note that the structure of the jmp_buf used here is not compatible
6086 // with that used by libc, and is not designed to be. Specifically, it
6087 // stores only those 'reserved' registers that LLVM does not otherwise
6088 // understand how to spill. Also, by convention, by the time this
6089 // intrinsic is called, Clang has already stored the frame address in the
6090 // first slot of the buffer and stack address in the third. Following the
6091 // X86 target code, we'll store the jump address in the second slot. We also
6092 // need to save the TOC pointer (R2) to handle jumps between shared
6093 // libraries, and that will be stored in the fourth slot. The thread
6094 // identifier (R13) is not affected.
6097 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6098 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6100 // Prepare IP either in reg.
6101 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6102 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6103 unsigned BufReg = MI->getOperand(1).getReg();
6105 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) {
6106 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6108 .addImm(TOCOffset / 4)
6111 MIB.setMemRefs(MMOBegin, MMOEnd);
6115 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6116 MIB.addRegMask(PPCRegInfo->getNoPreservedMask());
6118 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6120 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6122 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6124 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6125 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6129 MIB = BuildMI(mainMBB, DL,
6130 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6133 if (PPCSubTarget.isPPC64()) {
6134 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6136 .addImm(LabelOffset / 4)
6139 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6141 .addImm(LabelOffset)
6145 MIB.setMemRefs(MMOBegin, MMOEnd);
6147 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6148 mainMBB->addSuccessor(sinkMBB);
6151 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6152 TII->get(PPC::PHI), DstReg)
6153 .addReg(mainDstReg).addMBB(mainMBB)
6154 .addReg(restoreDstReg).addMBB(thisMBB);
6156 MI->eraseFromParent();
6161 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6162 MachineBasicBlock *MBB) const {
6163 DebugLoc DL = MI->getDebugLoc();
6164 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6166 MachineFunction *MF = MBB->getParent();
6167 MachineRegisterInfo &MRI = MF->getRegInfo();
6170 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6171 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6173 MVT PVT = getPointerTy();
6174 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6175 "Invalid Pointer Size!");
6177 const TargetRegisterClass *RC =
6178 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6179 unsigned Tmp = MRI.createVirtualRegister(RC);
6180 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6181 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6182 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6184 MachineInstrBuilder MIB;
6186 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6187 const int64_t SPOffset = 2 * PVT.getStoreSize();
6188 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6190 unsigned BufReg = MI->getOperand(0).getReg();
6192 // Reload FP (the jumped-to function may not have had a
6193 // frame pointer, and if so, then its r31 will be restored
6195 if (PVT == MVT::i64) {
6196 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6200 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6204 MIB.setMemRefs(MMOBegin, MMOEnd);
6207 if (PVT == MVT::i64) {
6208 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6209 .addImm(LabelOffset / 4)
6212 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6213 .addImm(LabelOffset)
6216 MIB.setMemRefs(MMOBegin, MMOEnd);
6219 if (PVT == MVT::i64) {
6220 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6221 .addImm(SPOffset / 4)
6224 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6228 MIB.setMemRefs(MMOBegin, MMOEnd);
6230 // FIXME: When we also support base pointers, that register must also be
6234 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6235 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6236 .addImm(TOCOffset / 4)
6239 MIB.setMemRefs(MMOBegin, MMOEnd);
6243 BuildMI(*MBB, MI, DL,
6244 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6245 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6247 MI->eraseFromParent();
6252 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6253 MachineBasicBlock *BB) const {
6254 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6255 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6256 return emitEHSjLjSetJmp(MI, BB);
6257 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6258 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6259 return emitEHSjLjLongJmp(MI, BB);
6262 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6264 // To "insert" these instructions we actually have to insert their
6265 // control-flow patterns.
6266 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6267 MachineFunction::iterator It = BB;
6270 MachineFunction *F = BB->getParent();
6272 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6273 MI->getOpcode() == PPC::SELECT_CC_I8)) {
6274 SmallVector<MachineOperand, 2> Cond;
6275 Cond.push_back(MI->getOperand(4));
6276 Cond.push_back(MI->getOperand(1));
6278 DebugLoc dl = MI->getDebugLoc();
6279 PPCII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(), Cond,
6280 MI->getOperand(2).getReg(), MI->getOperand(3).getReg());
6281 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6282 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6283 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6284 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6285 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
6288 // The incoming instruction knows the destination vreg to set, the
6289 // condition code register to branch on, the true/false values to
6290 // select between, and a branch opcode to use.
6295 // cmpTY ccX, r1, r2
6297 // fallthrough --> copy0MBB
6298 MachineBasicBlock *thisMBB = BB;
6299 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6300 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6301 unsigned SelectPred = MI->getOperand(4).getImm();
6302 DebugLoc dl = MI->getDebugLoc();
6303 F->insert(It, copy0MBB);
6304 F->insert(It, sinkMBB);
6306 // Transfer the remainder of BB and its successor edges to sinkMBB.
6307 sinkMBB->splice(sinkMBB->begin(), BB,
6308 llvm::next(MachineBasicBlock::iterator(MI)),
6310 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6312 // Next, add the true and fallthrough blocks as its successors.
6313 BB->addSuccessor(copy0MBB);
6314 BB->addSuccessor(sinkMBB);
6316 BuildMI(BB, dl, TII->get(PPC::BCC))
6317 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6320 // %FalseValue = ...
6321 // # fallthrough to sinkMBB
6324 // Update machine-CFG edges
6325 BB->addSuccessor(sinkMBB);
6328 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6331 BuildMI(*BB, BB->begin(), dl,
6332 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6333 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6334 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6336 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6337 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6338 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6339 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6340 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6341 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6342 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6343 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6345 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6346 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6347 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6348 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6349 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6350 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6351 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6352 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6354 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6355 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6356 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6357 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6358 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6359 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6360 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6361 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6363 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6364 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6365 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6366 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6367 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6368 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6369 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6370 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6372 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6373 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6374 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6375 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6376 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6377 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6378 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6379 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6381 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6382 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6383 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6384 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6385 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6386 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6387 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6388 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6390 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6391 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6392 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6393 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6394 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6395 BB = EmitAtomicBinary(MI, BB, false, 0);
6396 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6397 BB = EmitAtomicBinary(MI, BB, true, 0);
6399 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6400 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6401 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6403 unsigned dest = MI->getOperand(0).getReg();
6404 unsigned ptrA = MI->getOperand(1).getReg();
6405 unsigned ptrB = MI->getOperand(2).getReg();
6406 unsigned oldval = MI->getOperand(3).getReg();
6407 unsigned newval = MI->getOperand(4).getReg();
6408 DebugLoc dl = MI->getDebugLoc();
6410 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6411 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6412 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6413 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6414 F->insert(It, loop1MBB);
6415 F->insert(It, loop2MBB);
6416 F->insert(It, midMBB);
6417 F->insert(It, exitMBB);
6418 exitMBB->splice(exitMBB->begin(), BB,
6419 llvm::next(MachineBasicBlock::iterator(MI)),
6421 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6425 // fallthrough --> loopMBB
6426 BB->addSuccessor(loop1MBB);
6429 // l[wd]arx dest, ptr
6430 // cmp[wd] dest, oldval
6433 // st[wd]cx. newval, ptr
6437 // st[wd]cx. dest, ptr
6440 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6441 .addReg(ptrA).addReg(ptrB);
6442 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6443 .addReg(oldval).addReg(dest);
6444 BuildMI(BB, dl, TII->get(PPC::BCC))
6445 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6446 BB->addSuccessor(loop2MBB);
6447 BB->addSuccessor(midMBB);
6450 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6451 .addReg(newval).addReg(ptrA).addReg(ptrB);
6452 BuildMI(BB, dl, TII->get(PPC::BCC))
6453 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6454 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6455 BB->addSuccessor(loop1MBB);
6456 BB->addSuccessor(exitMBB);
6459 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6460 .addReg(dest).addReg(ptrA).addReg(ptrB);
6461 BB->addSuccessor(exitMBB);
6466 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6467 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6468 // We must use 64-bit registers for addresses when targeting 64-bit,
6469 // since we're actually doing arithmetic on them. Other registers
6471 bool is64bit = PPCSubTarget.isPPC64();
6472 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6474 unsigned dest = MI->getOperand(0).getReg();
6475 unsigned ptrA = MI->getOperand(1).getReg();
6476 unsigned ptrB = MI->getOperand(2).getReg();
6477 unsigned oldval = MI->getOperand(3).getReg();
6478 unsigned newval = MI->getOperand(4).getReg();
6479 DebugLoc dl = MI->getDebugLoc();
6481 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6482 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6483 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6484 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6485 F->insert(It, loop1MBB);
6486 F->insert(It, loop2MBB);
6487 F->insert(It, midMBB);
6488 F->insert(It, exitMBB);
6489 exitMBB->splice(exitMBB->begin(), BB,
6490 llvm::next(MachineBasicBlock::iterator(MI)),
6492 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6494 MachineRegisterInfo &RegInfo = F->getRegInfo();
6495 const TargetRegisterClass *RC =
6496 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6497 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6498 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6499 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6500 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6501 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6502 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6503 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6504 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6505 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6506 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6507 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6508 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6509 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6510 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6512 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6513 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6516 // fallthrough --> loopMBB
6517 BB->addSuccessor(loop1MBB);
6519 // The 4-byte load must be aligned, while a char or short may be
6520 // anywhere in the word. Hence all this nasty bookkeeping code.
6521 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6522 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6523 // xori shift, shift1, 24 [16]
6524 // rlwinm ptr, ptr1, 0, 0, 29
6525 // slw newval2, newval, shift
6526 // slw oldval2, oldval,shift
6527 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6528 // slw mask, mask2, shift
6529 // and newval3, newval2, mask
6530 // and oldval3, oldval2, mask
6532 // lwarx tmpDest, ptr
6533 // and tmp, tmpDest, mask
6534 // cmpw tmp, oldval3
6537 // andc tmp2, tmpDest, mask
6538 // or tmp4, tmp2, newval3
6543 // stwcx. tmpDest, ptr
6545 // srw dest, tmpDest, shift
6546 if (ptrA != ZeroReg) {
6547 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6548 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6549 .addReg(ptrA).addReg(ptrB);
6553 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6554 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6555 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6556 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6558 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6559 .addReg(Ptr1Reg).addImm(0).addImm(61);
6561 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6562 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6563 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6564 .addReg(newval).addReg(ShiftReg);
6565 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6566 .addReg(oldval).addReg(ShiftReg);
6568 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6570 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6571 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6572 .addReg(Mask3Reg).addImm(65535);
6574 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6575 .addReg(Mask2Reg).addReg(ShiftReg);
6576 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6577 .addReg(NewVal2Reg).addReg(MaskReg);
6578 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6579 .addReg(OldVal2Reg).addReg(MaskReg);
6582 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6583 .addReg(ZeroReg).addReg(PtrReg);
6584 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6585 .addReg(TmpDestReg).addReg(MaskReg);
6586 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6587 .addReg(TmpReg).addReg(OldVal3Reg);
6588 BuildMI(BB, dl, TII->get(PPC::BCC))
6589 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6590 BB->addSuccessor(loop2MBB);
6591 BB->addSuccessor(midMBB);
6594 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6595 .addReg(TmpDestReg).addReg(MaskReg);
6596 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6597 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6598 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6599 .addReg(ZeroReg).addReg(PtrReg);
6600 BuildMI(BB, dl, TII->get(PPC::BCC))
6601 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6602 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6603 BB->addSuccessor(loop1MBB);
6604 BB->addSuccessor(exitMBB);
6607 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
6608 .addReg(ZeroReg).addReg(PtrReg);
6609 BB->addSuccessor(exitMBB);
6614 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
6616 } else if (MI->getOpcode() == PPC::FADDrtz) {
6617 // This pseudo performs an FADD with rounding mode temporarily forced
6618 // to round-to-zero. We emit this via custom inserter since the FPSCR
6619 // is not modeled at the SelectionDAG level.
6620 unsigned Dest = MI->getOperand(0).getReg();
6621 unsigned Src1 = MI->getOperand(1).getReg();
6622 unsigned Src2 = MI->getOperand(2).getReg();
6623 DebugLoc dl = MI->getDebugLoc();
6625 MachineRegisterInfo &RegInfo = F->getRegInfo();
6626 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
6628 // Save FPSCR value.
6629 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
6631 // Set rounding mode to round-to-zero.
6632 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
6633 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
6635 // Perform addition.
6636 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
6638 // Restore FPSCR value.
6639 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
6640 } else if (MI->getOpcode() == PPC::FRINDrint ||
6641 MI->getOpcode() == PPC::FRINSrint) {
6642 bool isf32 = MI->getOpcode() == PPC::FRINSrint;
6643 unsigned Dest = MI->getOperand(0).getReg();
6644 unsigned Src = MI->getOperand(1).getReg();
6645 DebugLoc dl = MI->getDebugLoc();
6647 MachineRegisterInfo &RegInfo = F->getRegInfo();
6648 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
6650 // Perform the rounding.
6651 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FRINS : PPC::FRIND), Dest)
6654 // Compare the results.
6655 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FCMPUS : PPC::FCMPUD), CRReg)
6656 .addReg(Dest).addReg(Src);
6658 // If the results were not equal, then set the FPSCR XX bit.
6659 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6660 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6661 F->insert(It, midMBB);
6662 F->insert(It, exitMBB);
6663 exitMBB->splice(exitMBB->begin(), BB,
6664 llvm::next(MachineBasicBlock::iterator(MI)),
6666 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6668 BuildMI(*BB, MI, dl, TII->get(PPC::BCC))
6669 .addImm(PPC::PRED_EQ).addReg(CRReg).addMBB(exitMBB);
6671 BB->addSuccessor(midMBB);
6672 BB->addSuccessor(exitMBB);
6676 // Set the FPSCR XX bit (FE_INEXACT). Note that we cannot just set
6677 // the FI bit here because that will not automatically set XX also,
6678 // and XX is what libm interprets as the FE_INEXACT flag.
6679 BuildMI(BB, dl, TII->get(PPC::MTFSB1)).addImm(/* 38 - 32 = */ 6);
6680 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6682 BB->addSuccessor(exitMBB);
6686 llvm_unreachable("Unexpected instr type to insert");
6689 MI->eraseFromParent(); // The pseudo instruction is gone now.
6693 //===----------------------------------------------------------------------===//
6694 // Target Optimization Hooks
6695 //===----------------------------------------------------------------------===//
6697 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
6698 DAGCombinerInfo &DCI) const {
6699 if (DCI.isAfterLegalizeVectorOps())
6702 EVT VT = Op.getValueType();
6704 if ((VT == MVT::f32 && PPCSubTarget.hasFRES()) ||
6705 (VT == MVT::f64 && PPCSubTarget.hasFRE()) ||
6706 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6708 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6709 // For the reciprocal, we need to find the zero of the function:
6710 // F(X) = A X - 1 [which has a zero at X = 1/A]
6712 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
6713 // does not require additional intermediate precision]
6715 // Convergence is quadratic, so we essentially double the number of digits
6716 // correct after every iteration. The minimum architected relative
6717 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6718 // 23 digits and double has 52 digits.
6719 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6720 if (VT.getScalarType() == MVT::f64)
6723 SelectionDAG &DAG = DCI.DAG;
6724 DebugLoc dl = Op.getDebugLoc();
6727 DAG.getConstantFP(1.0, VT.getScalarType());
6728 if (VT.isVector()) {
6729 assert(VT.getVectorNumElements() == 4 &&
6730 "Unknown vector type");
6731 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6732 FPOne, FPOne, FPOne, FPOne);
6735 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
6736 DCI.AddToWorklist(Est.getNode());
6738 // Newton iterations: Est = Est + Est (1 - Arg * Est)
6739 for (int i = 0; i < Iterations; ++i) {
6740 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
6741 DCI.AddToWorklist(NewEst.getNode());
6743 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
6744 DCI.AddToWorklist(NewEst.getNode());
6746 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6747 DCI.AddToWorklist(NewEst.getNode());
6749 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
6750 DCI.AddToWorklist(Est.getNode());
6759 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
6760 DAGCombinerInfo &DCI) const {
6761 if (DCI.isAfterLegalizeVectorOps())
6764 EVT VT = Op.getValueType();
6766 if ((VT == MVT::f32 && PPCSubTarget.hasFRSQRTES()) ||
6767 (VT == MVT::f64 && PPCSubTarget.hasFRSQRTE()) ||
6768 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6770 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6771 // For the reciprocal sqrt, we need to find the zero of the function:
6772 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
6774 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
6775 // As a result, we precompute A/2 prior to the iteration loop.
6777 // Convergence is quadratic, so we essentially double the number of digits
6778 // correct after every iteration. The minimum architected relative
6779 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6780 // 23 digits and double has 52 digits.
6781 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6782 if (VT.getScalarType() == MVT::f64)
6785 SelectionDAG &DAG = DCI.DAG;
6786 DebugLoc dl = Op.getDebugLoc();
6788 SDValue FPThreeHalves =
6789 DAG.getConstantFP(1.5, VT.getScalarType());
6790 if (VT.isVector()) {
6791 assert(VT.getVectorNumElements() == 4 &&
6792 "Unknown vector type");
6793 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6794 FPThreeHalves, FPThreeHalves,
6795 FPThreeHalves, FPThreeHalves);
6798 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
6799 DCI.AddToWorklist(Est.getNode());
6801 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
6802 // this entire sequence requires only one FP constant.
6803 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
6804 DCI.AddToWorklist(HalfArg.getNode());
6806 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
6807 DCI.AddToWorklist(HalfArg.getNode());
6809 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
6810 for (int i = 0; i < Iterations; ++i) {
6811 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
6812 DCI.AddToWorklist(NewEst.getNode());
6814 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
6815 DCI.AddToWorklist(NewEst.getNode());
6817 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
6818 DCI.AddToWorklist(NewEst.getNode());
6820 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6821 DCI.AddToWorklist(Est.getNode());
6830 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
6831 DAGCombinerInfo &DCI) const {
6832 const TargetMachine &TM = getTargetMachine();
6833 SelectionDAG &DAG = DCI.DAG;
6834 DebugLoc dl = N->getDebugLoc();
6835 switch (N->getOpcode()) {
6838 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6839 if (C->isNullValue()) // 0 << V -> 0.
6840 return N->getOperand(0);
6844 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6845 if (C->isNullValue()) // 0 >>u V -> 0.
6846 return N->getOperand(0);
6850 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6851 if (C->isNullValue() || // 0 >>s V -> 0.
6852 C->isAllOnesValue()) // -1 >>s V -> -1.
6853 return N->getOperand(0);
6857 assert(TM.Options.UnsafeFPMath &&
6858 "Reciprocal estimates require UnsafeFPMath");
6860 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
6862 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
6863 if (RV.getNode() != 0) {
6864 DCI.AddToWorklist(RV.getNode());
6865 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6866 N->getOperand(0), RV);
6868 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
6869 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
6871 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
6873 if (RV.getNode() != 0) {
6874 DCI.AddToWorklist(RV.getNode());
6875 RV = DAG.getNode(ISD::FP_EXTEND, N->getOperand(1).getDebugLoc(),
6876 N->getValueType(0), RV);
6877 DCI.AddToWorklist(RV.getNode());
6878 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6879 N->getOperand(0), RV);
6881 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
6882 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
6884 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
6886 if (RV.getNode() != 0) {
6887 DCI.AddToWorklist(RV.getNode());
6888 RV = DAG.getNode(ISD::FP_ROUND, N->getOperand(1).getDebugLoc(),
6889 N->getValueType(0), RV,
6890 N->getOperand(1).getOperand(1));
6891 DCI.AddToWorklist(RV.getNode());
6892 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6893 N->getOperand(0), RV);
6897 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
6898 if (RV.getNode() != 0) {
6899 DCI.AddToWorklist(RV.getNode());
6900 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6901 N->getOperand(0), RV);
6907 assert(TM.Options.UnsafeFPMath &&
6908 "Reciprocal estimates require UnsafeFPMath");
6910 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
6912 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
6913 if (RV.getNode() != 0) {
6914 DCI.AddToWorklist(RV.getNode());
6915 RV = DAGCombineFastRecip(RV, DCI);
6916 if (RV.getNode() != 0)
6922 case ISD::SINT_TO_FP:
6923 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
6924 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
6925 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
6926 // We allow the src/dst to be either f32/f64, but the intermediate
6927 // type must be i64.
6928 if (N->getOperand(0).getValueType() == MVT::i64 &&
6929 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
6930 SDValue Val = N->getOperand(0).getOperand(0);
6931 if (Val.getValueType() == MVT::f32) {
6932 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
6933 DCI.AddToWorklist(Val.getNode());
6936 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
6937 DCI.AddToWorklist(Val.getNode());
6938 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
6939 DCI.AddToWorklist(Val.getNode());
6940 if (N->getValueType(0) == MVT::f32) {
6941 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
6942 DAG.getIntPtrConstant(0));
6943 DCI.AddToWorklist(Val.getNode());
6946 } else if (N->getOperand(0).getValueType() == MVT::i32) {
6947 // If the intermediate type is i32, we can avoid the load/store here
6954 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
6955 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
6956 !cast<StoreSDNode>(N)->isTruncatingStore() &&
6957 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
6958 N->getOperand(1).getValueType() == MVT::i32 &&
6959 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
6960 SDValue Val = N->getOperand(1).getOperand(0);
6961 if (Val.getValueType() == MVT::f32) {
6962 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
6963 DCI.AddToWorklist(Val.getNode());
6965 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
6966 DCI.AddToWorklist(Val.getNode());
6969 N->getOperand(0), Val, N->getOperand(2),
6970 DAG.getValueType(N->getOperand(1).getValueType())
6973 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
6974 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
6975 cast<StoreSDNode>(N)->getMemoryVT(),
6976 cast<StoreSDNode>(N)->getMemOperand());
6977 DCI.AddToWorklist(Val.getNode());
6981 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
6982 if (cast<StoreSDNode>(N)->isUnindexed() &&
6983 N->getOperand(1).getOpcode() == ISD::BSWAP &&
6984 N->getOperand(1).getNode()->hasOneUse() &&
6985 (N->getOperand(1).getValueType() == MVT::i32 ||
6986 N->getOperand(1).getValueType() == MVT::i16 ||
6987 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
6988 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
6989 N->getOperand(1).getValueType() == MVT::i64))) {
6990 SDValue BSwapOp = N->getOperand(1).getOperand(0);
6991 // Do an any-extend to 32-bits if this is a half-word input.
6992 if (BSwapOp.getValueType() == MVT::i16)
6993 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
6996 N->getOperand(0), BSwapOp, N->getOperand(2),
6997 DAG.getValueType(N->getOperand(1).getValueType())
7000 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
7001 Ops, array_lengthof(Ops),
7002 cast<StoreSDNode>(N)->getMemoryVT(),
7003 cast<StoreSDNode>(N)->getMemOperand());
7007 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
7008 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
7009 N->getOperand(0).hasOneUse() &&
7010 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
7011 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7012 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7013 N->getValueType(0) == MVT::i64))) {
7014 SDValue Load = N->getOperand(0);
7015 LoadSDNode *LD = cast<LoadSDNode>(Load);
7016 // Create the byte-swapping load.
7018 LD->getChain(), // Chain
7019 LD->getBasePtr(), // Ptr
7020 DAG.getValueType(N->getValueType(0)) // VT
7023 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
7024 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
7025 MVT::i64 : MVT::i32, MVT::Other),
7026 Ops, 3, LD->getMemoryVT(), LD->getMemOperand());
7028 // If this is an i16 load, insert the truncate.
7029 SDValue ResVal = BSLoad;
7030 if (N->getValueType(0) == MVT::i16)
7031 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
7033 // First, combine the bswap away. This makes the value produced by the
7035 DCI.CombineTo(N, ResVal);
7037 // Next, combine the load away, we give it a bogus result value but a real
7038 // chain result. The result value is dead because the bswap is dead.
7039 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
7041 // Return N so it doesn't get rechecked!
7042 return SDValue(N, 0);
7046 case PPCISD::VCMP: {
7047 // If a VCMPo node already exists with exactly the same operands as this
7048 // node, use its result instead of this node (VCMPo computes both a CR6 and
7049 // a normal output).
7051 if (!N->getOperand(0).hasOneUse() &&
7052 !N->getOperand(1).hasOneUse() &&
7053 !N->getOperand(2).hasOneUse()) {
7055 // Scan all of the users of the LHS, looking for VCMPo's that match.
7056 SDNode *VCMPoNode = 0;
7058 SDNode *LHSN = N->getOperand(0).getNode();
7059 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
7061 if (UI->getOpcode() == PPCISD::VCMPo &&
7062 UI->getOperand(1) == N->getOperand(1) &&
7063 UI->getOperand(2) == N->getOperand(2) &&
7064 UI->getOperand(0) == N->getOperand(0)) {
7069 // If there is no VCMPo node, or if the flag value has a single use, don't
7071 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
7074 // Look at the (necessarily single) use of the flag value. If it has a
7075 // chain, this transformation is more complex. Note that multiple things
7076 // could use the value result, which we should ignore.
7077 SDNode *FlagUser = 0;
7078 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
7079 FlagUser == 0; ++UI) {
7080 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
7082 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
7083 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
7090 // If the user is a MFCR instruction, we know this is safe. Otherwise we
7091 // give up for right now.
7092 if (FlagUser->getOpcode() == PPCISD::MFCR)
7093 return SDValue(VCMPoNode, 0);
7098 // If this is a branch on an altivec predicate comparison, lower this so
7099 // that we don't have to do a MFCR: instead, branch directly on CR6. This
7100 // lowering is done pre-legalize, because the legalizer lowers the predicate
7101 // compare down to code that is difficult to reassemble.
7102 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
7103 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
7107 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7108 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
7109 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
7110 assert(isDot && "Can't compare against a vector result!");
7112 // If this is a comparison against something other than 0/1, then we know
7113 // that the condition is never/always true.
7114 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7115 if (Val != 0 && Val != 1) {
7116 if (CC == ISD::SETEQ) // Cond never true, remove branch.
7117 return N->getOperand(0);
7118 // Always !=, turn it into an unconditional branch.
7119 return DAG.getNode(ISD::BR, dl, MVT::Other,
7120 N->getOperand(0), N->getOperand(4));
7123 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
7125 // Create the PPCISD altivec 'dot' comparison node.
7127 LHS.getOperand(2), // LHS of compare
7128 LHS.getOperand(3), // RHS of compare
7129 DAG.getConstant(CompareOpc, MVT::i32)
7131 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
7132 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
7134 // Unpack the result based on how the target uses it.
7135 PPC::Predicate CompOpc;
7136 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
7137 default: // Can't happen, don't crash on invalid number though.
7138 case 0: // Branch on the value of the EQ bit of CR6.
7139 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
7141 case 1: // Branch on the inverted value of the EQ bit of CR6.
7142 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
7144 case 2: // Branch on the value of the LT bit of CR6.
7145 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
7147 case 3: // Branch on the inverted value of the LT bit of CR6.
7148 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
7152 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
7153 DAG.getConstant(CompOpc, MVT::i32),
7154 DAG.getRegister(PPC::CR6, MVT::i32),
7155 N->getOperand(4), CompNode.getValue(1));
7164 //===----------------------------------------------------------------------===//
7165 // Inline Assembly Support
7166 //===----------------------------------------------------------------------===//
7168 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7171 const SelectionDAG &DAG,
7172 unsigned Depth) const {
7173 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
7174 switch (Op.getOpcode()) {
7176 case PPCISD::LBRX: {
7177 // lhbrx is known to have the top bits cleared out.
7178 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
7179 KnownZero = 0xFFFF0000;
7182 case ISD::INTRINSIC_WO_CHAIN: {
7183 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
7185 case Intrinsic::ppc_altivec_vcmpbfp_p:
7186 case Intrinsic::ppc_altivec_vcmpeqfp_p:
7187 case Intrinsic::ppc_altivec_vcmpequb_p:
7188 case Intrinsic::ppc_altivec_vcmpequh_p:
7189 case Intrinsic::ppc_altivec_vcmpequw_p:
7190 case Intrinsic::ppc_altivec_vcmpgefp_p:
7191 case Intrinsic::ppc_altivec_vcmpgtfp_p:
7192 case Intrinsic::ppc_altivec_vcmpgtsb_p:
7193 case Intrinsic::ppc_altivec_vcmpgtsh_p:
7194 case Intrinsic::ppc_altivec_vcmpgtsw_p:
7195 case Intrinsic::ppc_altivec_vcmpgtub_p:
7196 case Intrinsic::ppc_altivec_vcmpgtuh_p:
7197 case Intrinsic::ppc_altivec_vcmpgtuw_p:
7198 KnownZero = ~1U; // All bits but the low one are known to be zero.
7206 /// getConstraintType - Given a constraint, return the type of
7207 /// constraint it is for this target.
7208 PPCTargetLowering::ConstraintType
7209 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
7210 if (Constraint.size() == 1) {
7211 switch (Constraint[0]) {
7218 return C_RegisterClass;
7220 // FIXME: While Z does indicate a memory constraint, it specifically
7221 // indicates an r+r address (used in conjunction with the 'y' modifier
7222 // in the replacement string). Currently, we're forcing the base
7223 // register to be r0 in the asm printer (which is interpreted as zero)
7224 // and forming the complete address in the second register. This is
7229 return TargetLowering::getConstraintType(Constraint);
7232 /// Examine constraint type and operand type and determine a weight value.
7233 /// This object must already have been set up with the operand type
7234 /// and the current alternative constraint selected.
7235 TargetLowering::ConstraintWeight
7236 PPCTargetLowering::getSingleConstraintMatchWeight(
7237 AsmOperandInfo &info, const char *constraint) const {
7238 ConstraintWeight weight = CW_Invalid;
7239 Value *CallOperandVal = info.CallOperandVal;
7240 // If we don't have a value, we can't do a match,
7241 // but allow it at the lowest weight.
7242 if (CallOperandVal == NULL)
7244 Type *type = CallOperandVal->getType();
7245 // Look at the constraint type.
7246 switch (*constraint) {
7248 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
7251 if (type->isIntegerTy())
7252 weight = CW_Register;
7255 if (type->isFloatTy())
7256 weight = CW_Register;
7259 if (type->isDoubleTy())
7260 weight = CW_Register;
7263 if (type->isVectorTy())
7264 weight = CW_Register;
7267 weight = CW_Register;
7276 std::pair<unsigned, const TargetRegisterClass*>
7277 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7279 if (Constraint.size() == 1) {
7280 // GCC RS6000 Constraint Letters
7281 switch (Constraint[0]) {
7283 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7284 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
7285 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
7287 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7288 return std::make_pair(0U, &PPC::G8RCRegClass);
7289 return std::make_pair(0U, &PPC::GPRCRegClass);
7291 if (VT == MVT::f32 || VT == MVT::i32)
7292 return std::make_pair(0U, &PPC::F4RCRegClass);
7293 if (VT == MVT::f64 || VT == MVT::i64)
7294 return std::make_pair(0U, &PPC::F8RCRegClass);
7297 return std::make_pair(0U, &PPC::VRRCRegClass);
7299 return std::make_pair(0U, &PPC::CRRCRegClass);
7303 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7307 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7308 /// vector. If it is invalid, don't add anything to Ops.
7309 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7310 std::string &Constraint,
7311 std::vector<SDValue>&Ops,
7312 SelectionDAG &DAG) const {
7313 SDValue Result(0,0);
7315 // Only support length 1 constraints.
7316 if (Constraint.length() > 1) return;
7318 char Letter = Constraint[0];
7329 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
7330 if (!CST) return; // Must be an immediate to match.
7331 unsigned Value = CST->getZExtValue();
7333 default: llvm_unreachable("Unknown constraint letter!");
7334 case 'I': // "I" is a signed 16-bit constant.
7335 if ((short)Value == (int)Value)
7336 Result = DAG.getTargetConstant(Value, Op.getValueType());
7338 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
7339 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
7340 if ((short)Value == 0)
7341 Result = DAG.getTargetConstant(Value, Op.getValueType());
7343 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
7344 if ((Value >> 16) == 0)
7345 Result = DAG.getTargetConstant(Value, Op.getValueType());
7347 case 'M': // "M" is a constant that is greater than 31.
7349 Result = DAG.getTargetConstant(Value, Op.getValueType());
7351 case 'N': // "N" is a positive constant that is an exact power of two.
7352 if ((int)Value > 0 && isPowerOf2_32(Value))
7353 Result = DAG.getTargetConstant(Value, Op.getValueType());
7355 case 'O': // "O" is the constant zero.
7357 Result = DAG.getTargetConstant(Value, Op.getValueType());
7359 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
7360 if ((short)-Value == (int)-Value)
7361 Result = DAG.getTargetConstant(Value, Op.getValueType());
7368 if (Result.getNode()) {
7369 Ops.push_back(Result);
7373 // Handle standard constraint letters.
7374 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7377 // isLegalAddressingMode - Return true if the addressing mode represented
7378 // by AM is legal for this target, for a load/store of the specified type.
7379 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
7381 // FIXME: PPC does not allow r+i addressing modes for vectors!
7383 // PPC allows a sign-extended 16-bit immediate field.
7384 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
7387 // No global is ever allowed as a base.
7391 // PPC only support r+r,
7393 case 0: // "r+i" or just "i", depending on HasBaseReg.
7396 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
7398 // Otherwise we have r+r or r+i.
7401 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
7403 // Allow 2*r as r+r.
7406 // No other scales are supported.
7413 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
7414 SelectionDAG &DAG) const {
7415 MachineFunction &MF = DAG.getMachineFunction();
7416 MachineFrameInfo *MFI = MF.getFrameInfo();
7417 MFI->setReturnAddressIsTaken(true);
7419 DebugLoc dl = Op.getDebugLoc();
7420 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7422 // Make sure the function does not optimize away the store of the RA to
7424 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
7425 FuncInfo->setLRStoreRequired();
7426 bool isPPC64 = PPCSubTarget.isPPC64();
7427 bool isDarwinABI = PPCSubTarget.isDarwinABI();
7430 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7433 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
7434 isPPC64? MVT::i64 : MVT::i32);
7435 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7436 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7438 MachinePointerInfo(), false, false, false, 0);
7441 // Just load the return address off the stack.
7442 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
7443 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7444 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
7447 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
7448 SelectionDAG &DAG) const {
7449 DebugLoc dl = Op.getDebugLoc();
7450 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7452 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
7453 bool isPPC64 = PtrVT == MVT::i64;
7455 MachineFunction &MF = DAG.getMachineFunction();
7456 MachineFrameInfo *MFI = MF.getFrameInfo();
7457 MFI->setFrameAddressIsTaken(true);
7459 // Naked functions never have a frame pointer, and so we use r1. For all
7460 // other functions, this decision must be delayed until during PEI.
7462 if (MF.getFunction()->getAttributes().hasAttribute(
7463 AttributeSet::FunctionIndex, Attribute::Naked))
7464 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
7466 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
7468 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
7471 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
7472 FrameAddr, MachinePointerInfo(), false, false,
7478 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7479 // The PowerPC target isn't yet aware of offsets.
7483 /// getOptimalMemOpType - Returns the target specific optimal type for load
7484 /// and store operations as a result of memset, memcpy, and memmove
7485 /// lowering. If DstAlign is zero that means it's safe to destination
7486 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
7487 /// means there isn't a need to check it against alignment requirement,
7488 /// probably because the source does not need to be loaded. If 'IsMemset' is
7489 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
7490 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
7491 /// source is constant so it does not need to be loaded.
7492 /// It returns EVT::Other if the type should be determined using generic
7493 /// target-independent logic.
7494 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
7495 unsigned DstAlign, unsigned SrcAlign,
7496 bool IsMemset, bool ZeroMemset,
7498 MachineFunction &MF) const {
7499 if (this->PPCSubTarget.isPPC64()) {
7506 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
7508 if (DisablePPCUnaligned)
7511 // PowerPC supports unaligned memory access for simple non-vector types.
7512 // Although accessing unaligned addresses is not as efficient as accessing
7513 // aligned addresses, it is generally more efficient than manual expansion,
7514 // and generally only traps for software emulation when crossing page
7520 if (VT.getSimpleVT().isVector())
7523 if (VT == MVT::ppcf128)
7532 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
7533 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
7534 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
7535 /// is expanded to mul + add.
7536 bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const {
7540 switch (VT.getSimpleVT().SimpleTy) {
7552 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
7554 return TargetLowering::getSchedulingPreference(N);