1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
44 // FIXME: Remove this once soft-float is supported.
45 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
46 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
49 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
51 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
52 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
54 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
55 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
57 // FIXME: Remove this once the bug has been fixed!
58 extern cl::opt<bool> ANDIGlueBug;
60 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM)
62 Subtarget(*TM.getSubtargetImpl()) {
63 // Use _setjmp/_longjmp instead of setjmp/longjmp.
64 setUseUnderscoreSetJmp(true);
65 setUseUnderscoreLongJmp(true);
67 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
68 // arguments are at least 4/8 bytes aligned.
69 bool isPPC64 = Subtarget.isPPC64();
70 setMinStackArgumentAlignment(isPPC64 ? 8:4);
72 // Set up the register classes.
73 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
74 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
75 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
77 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
78 for (MVT VT : MVT::integer_valuetypes()) {
79 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
85 // PowerPC has pre-inc load and store's.
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
97 if (Subtarget.useCRBits()) {
98 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
100 if (isPPC64 || Subtarget.hasFPCVT()) {
101 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
102 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
103 isPPC64 ? MVT::i64 : MVT::i32);
104 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
108 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
109 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
112 // PowerPC does not support direct load / store of condition registers
113 setOperationAction(ISD::LOAD, MVT::i1, Custom);
114 setOperationAction(ISD::STORE, MVT::i1, Custom);
116 // FIXME: Remove this once the ANDI glue bug is fixed:
118 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
120 for (MVT VT : MVT::integer_valuetypes()) {
121 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
122 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
123 setTruncStoreAction(VT, MVT::i1, Expand);
126 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
129 // This is used in the ppcf128->int sequence. Note it has different semantics
130 // from FP_ROUND: that rounds to nearest, this rounds to zero.
131 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
133 // We do not currently implement these libm ops for PowerPC.
134 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
135 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
136 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
137 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
138 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
141 // PowerPC has no SREM/UREM instructions
142 setOperationAction(ISD::SREM, MVT::i32, Expand);
143 setOperationAction(ISD::UREM, MVT::i32, Expand);
144 setOperationAction(ISD::SREM, MVT::i64, Expand);
145 setOperationAction(ISD::UREM, MVT::i64, Expand);
147 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
148 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
149 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
150 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
151 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
152 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
153 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
154 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
155 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
157 // We don't support sin/cos/sqrt/fmod/pow
158 setOperationAction(ISD::FSIN , MVT::f64, Expand);
159 setOperationAction(ISD::FCOS , MVT::f64, Expand);
160 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
161 setOperationAction(ISD::FREM , MVT::f64, Expand);
162 setOperationAction(ISD::FPOW , MVT::f64, Expand);
163 setOperationAction(ISD::FMA , MVT::f64, Legal);
164 setOperationAction(ISD::FSIN , MVT::f32, Expand);
165 setOperationAction(ISD::FCOS , MVT::f32, Expand);
166 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
167 setOperationAction(ISD::FREM , MVT::f32, Expand);
168 setOperationAction(ISD::FPOW , MVT::f32, Expand);
169 setOperationAction(ISD::FMA , MVT::f32, Legal);
171 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
173 // If we're enabling GP optimizations, use hardware square root
174 if (!Subtarget.hasFSQRT() &&
175 !(TM.Options.UnsafeFPMath &&
176 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
177 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
179 if (!Subtarget.hasFSQRT() &&
180 !(TM.Options.UnsafeFPMath &&
181 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
182 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
184 if (Subtarget.hasFCPSGN()) {
185 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
186 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
188 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
189 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
192 if (Subtarget.hasFPRND()) {
193 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
194 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
195 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
196 setOperationAction(ISD::FROUND, MVT::f64, Legal);
198 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
199 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
200 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
201 setOperationAction(ISD::FROUND, MVT::f32, Legal);
204 // PowerPC does not have BSWAP, CTPOP or CTTZ
205 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
206 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
207 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
208 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
209 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
214 if (Subtarget.hasPOPCNTD()) {
215 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
216 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
218 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
219 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
222 // PowerPC does not have ROTR
223 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
224 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
226 if (!Subtarget.useCRBits()) {
227 // PowerPC does not have Select
228 setOperationAction(ISD::SELECT, MVT::i32, Expand);
229 setOperationAction(ISD::SELECT, MVT::i64, Expand);
230 setOperationAction(ISD::SELECT, MVT::f32, Expand);
231 setOperationAction(ISD::SELECT, MVT::f64, Expand);
234 // PowerPC wants to turn select_cc of FP into fsel when possible.
235 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
236 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
238 // PowerPC wants to optimize integer setcc a bit
239 if (!Subtarget.useCRBits())
240 setOperationAction(ISD::SETCC, MVT::i32, Custom);
242 // PowerPC does not have BRCOND which requires SetCC
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
246 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
248 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
249 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
251 // PowerPC does not have [U|S]INT_TO_FP
252 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
253 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
255 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
256 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
257 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
258 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
260 // We cannot sextinreg(i1). Expand to shifts.
261 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
263 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
264 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
265 // support continuation, user-level threading, and etc.. As a result, no
266 // other SjLj exception interfaces are implemented and please don't build
267 // your own exception handling based on them.
268 // LLVM/Clang supports zero-cost DWARF exception handling.
269 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
270 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
272 // We want to legalize GlobalAddress and ConstantPool nodes into the
273 // appropriate instructions to materialize the address.
274 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
275 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
276 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
277 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
278 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
280 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
281 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
282 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
283 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
286 setOperationAction(ISD::TRAP, MVT::Other, Legal);
288 // TRAMPOLINE is custom lowered.
289 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
290 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
292 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
293 setOperationAction(ISD::VASTART , MVT::Other, Custom);
295 if (Subtarget.isSVR4ABI()) {
297 // VAARG always uses double-word chunks, so promote anything smaller.
298 setOperationAction(ISD::VAARG, MVT::i1, Promote);
299 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
300 setOperationAction(ISD::VAARG, MVT::i8, Promote);
301 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
302 setOperationAction(ISD::VAARG, MVT::i16, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i32, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::Other, Expand);
308 // VAARG is custom lowered with the 32-bit SVR4 ABI.
309 setOperationAction(ISD::VAARG, MVT::Other, Custom);
310 setOperationAction(ISD::VAARG, MVT::i64, Custom);
313 setOperationAction(ISD::VAARG, MVT::Other, Expand);
315 if (Subtarget.isSVR4ABI() && !isPPC64)
316 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
317 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
319 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
321 // Use the default implementation.
322 setOperationAction(ISD::VAEND , MVT::Other, Expand);
323 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
324 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
325 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
326 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
328 // We want to custom lower some of our intrinsics.
329 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
331 // To handle counter-based loop conditions.
332 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
334 // Comparisons that require checking two conditions.
335 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
336 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
337 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
338 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
339 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
348 if (Subtarget.has64BitSupport()) {
349 // They also have instructions for converting between i64 and fp.
350 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
351 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
352 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
353 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
354 // This is just the low 32 bits of a (signed) fp->i64 conversion.
355 // We cannot do this with Promote because i64 is not a legal type.
356 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
358 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
359 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
361 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
362 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
365 // With the instructions enabled under FPCVT, we can do everything.
366 if (Subtarget.hasFPCVT()) {
367 if (Subtarget.has64BitSupport()) {
368 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
369 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
370 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
371 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
374 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
375 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
376 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
377 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
380 if (Subtarget.use64BitRegs()) {
381 // 64-bit PowerPC implementations can support i64 types directly
382 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
383 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
384 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
385 // 64-bit PowerPC wants to expand i128 shifts itself.
386 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
387 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
388 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
390 // 32-bit PowerPC wants to expand i64 shifts itself.
391 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
392 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
393 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
396 if (Subtarget.hasAltivec()) {
397 // First set operation action for all vector types to expand. Then we
398 // will selectively turn on ones that can be effectively codegen'd.
399 for (MVT VT : MVT::vector_valuetypes()) {
400 // add/sub are legal for all supported vector VT's.
401 setOperationAction(ISD::ADD , VT, Legal);
402 setOperationAction(ISD::SUB , VT, Legal);
404 // We promote all shuffles to v16i8.
405 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
406 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
408 // We promote all non-typed operations to v4i32.
409 setOperationAction(ISD::AND , VT, Promote);
410 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
411 setOperationAction(ISD::OR , VT, Promote);
412 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
413 setOperationAction(ISD::XOR , VT, Promote);
414 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
415 setOperationAction(ISD::LOAD , VT, Promote);
416 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
417 setOperationAction(ISD::SELECT, VT, Promote);
418 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
419 setOperationAction(ISD::STORE, VT, Promote);
420 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
422 // No other operations are legal.
423 setOperationAction(ISD::MUL , VT, Expand);
424 setOperationAction(ISD::SDIV, VT, Expand);
425 setOperationAction(ISD::SREM, VT, Expand);
426 setOperationAction(ISD::UDIV, VT, Expand);
427 setOperationAction(ISD::UREM, VT, Expand);
428 setOperationAction(ISD::FDIV, VT, Expand);
429 setOperationAction(ISD::FREM, VT, Expand);
430 setOperationAction(ISD::FNEG, VT, Expand);
431 setOperationAction(ISD::FSQRT, VT, Expand);
432 setOperationAction(ISD::FLOG, VT, Expand);
433 setOperationAction(ISD::FLOG10, VT, Expand);
434 setOperationAction(ISD::FLOG2, VT, Expand);
435 setOperationAction(ISD::FEXP, VT, Expand);
436 setOperationAction(ISD::FEXP2, VT, Expand);
437 setOperationAction(ISD::FSIN, VT, Expand);
438 setOperationAction(ISD::FCOS, VT, Expand);
439 setOperationAction(ISD::FABS, VT, Expand);
440 setOperationAction(ISD::FPOWI, VT, Expand);
441 setOperationAction(ISD::FFLOOR, VT, Expand);
442 setOperationAction(ISD::FCEIL, VT, Expand);
443 setOperationAction(ISD::FTRUNC, VT, Expand);
444 setOperationAction(ISD::FRINT, VT, Expand);
445 setOperationAction(ISD::FNEARBYINT, VT, Expand);
446 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
447 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
448 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
449 setOperationAction(ISD::MULHU, VT, Expand);
450 setOperationAction(ISD::MULHS, VT, Expand);
451 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
452 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
453 setOperationAction(ISD::UDIVREM, VT, Expand);
454 setOperationAction(ISD::SDIVREM, VT, Expand);
455 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
456 setOperationAction(ISD::FPOW, VT, Expand);
457 setOperationAction(ISD::BSWAP, VT, Expand);
458 setOperationAction(ISD::CTPOP, VT, Expand);
459 setOperationAction(ISD::CTLZ, VT, Expand);
460 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
461 setOperationAction(ISD::CTTZ, VT, Expand);
462 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
463 setOperationAction(ISD::VSELECT, VT, Expand);
464 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
466 for (MVT InnerVT : MVT::vector_valuetypes()) {
467 setTruncStoreAction(VT, InnerVT, Expand);
468 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
469 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
470 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
474 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
475 // with merges, splats, etc.
476 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
478 setOperationAction(ISD::AND , MVT::v4i32, Legal);
479 setOperationAction(ISD::OR , MVT::v4i32, Legal);
480 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
481 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
482 setOperationAction(ISD::SELECT, MVT::v4i32,
483 Subtarget.useCRBits() ? Legal : Expand);
484 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
485 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
486 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
487 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
488 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
489 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
490 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
491 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
492 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
494 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
495 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
496 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
497 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
499 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
500 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
502 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
503 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
504 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
507 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
508 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
509 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
511 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
512 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
514 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
515 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
516 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
517 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
519 // Altivec does not contain unordered floating-point compare instructions
520 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
521 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
522 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
523 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
525 if (Subtarget.hasVSX()) {
526 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
527 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
529 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
530 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
531 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
532 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
533 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
535 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
537 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
538 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
540 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
541 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
543 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
544 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
545 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
546 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
547 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
549 // Share the Altivec comparison restrictions.
550 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
551 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
552 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
553 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
555 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
556 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
558 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
560 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
562 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
563 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
565 // VSX v2i64 only supports non-arithmetic operations.
566 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
567 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
569 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
570 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
571 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
573 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
575 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
576 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
577 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
578 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
580 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
582 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
583 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
584 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
585 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
587 // Vector operation legalization checks the result type of
588 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
589 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
590 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
591 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
592 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
594 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
598 if (Subtarget.has64BitSupport())
599 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
601 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
604 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
605 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
608 setBooleanContents(ZeroOrOneBooleanContent);
609 // Altivec instructions set fields to all zeros or all ones.
610 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
613 // These libcalls are not available in 32-bit.
614 setLibcallName(RTLIB::SHL_I128, nullptr);
615 setLibcallName(RTLIB::SRL_I128, nullptr);
616 setLibcallName(RTLIB::SRA_I128, nullptr);
620 setStackPointerRegisterToSaveRestore(PPC::X1);
621 setExceptionPointerRegister(PPC::X3);
622 setExceptionSelectorRegister(PPC::X4);
624 setStackPointerRegisterToSaveRestore(PPC::R1);
625 setExceptionPointerRegister(PPC::R3);
626 setExceptionSelectorRegister(PPC::R4);
629 // We have target-specific dag combine patterns for the following nodes:
630 setTargetDAGCombine(ISD::SINT_TO_FP);
631 if (Subtarget.hasFPCVT())
632 setTargetDAGCombine(ISD::UINT_TO_FP);
633 setTargetDAGCombine(ISD::LOAD);
634 setTargetDAGCombine(ISD::STORE);
635 setTargetDAGCombine(ISD::BR_CC);
636 if (Subtarget.useCRBits())
637 setTargetDAGCombine(ISD::BRCOND);
638 setTargetDAGCombine(ISD::BSWAP);
639 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
640 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
641 setTargetDAGCombine(ISD::INTRINSIC_VOID);
643 setTargetDAGCombine(ISD::SIGN_EXTEND);
644 setTargetDAGCombine(ISD::ZERO_EXTEND);
645 setTargetDAGCombine(ISD::ANY_EXTEND);
647 if (Subtarget.useCRBits()) {
648 setTargetDAGCombine(ISD::TRUNCATE);
649 setTargetDAGCombine(ISD::SETCC);
650 setTargetDAGCombine(ISD::SELECT_CC);
653 // Use reciprocal estimates.
654 if (TM.Options.UnsafeFPMath) {
655 setTargetDAGCombine(ISD::FDIV);
656 setTargetDAGCombine(ISD::FSQRT);
659 // Darwin long double math library functions have $LDBL128 appended.
660 if (Subtarget.isDarwin()) {
661 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
662 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
663 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
664 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
665 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
666 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
667 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
668 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
669 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
670 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
673 // With 32 condition bits, we don't need to sink (and duplicate) compares
674 // aggressively in CodeGenPrep.
675 if (Subtarget.useCRBits())
676 setHasMultipleConditionRegisters();
678 setMinFunctionAlignment(2);
679 if (Subtarget.isDarwin())
680 setPrefFunctionAlignment(4);
682 switch (Subtarget.getDarwinDirective()) {
686 case PPC::DIR_E500mc:
695 setPrefFunctionAlignment(4);
696 setPrefLoopAlignment(4);
700 setInsertFencesForAtomic(true);
702 if (Subtarget.enableMachineScheduler())
703 setSchedulingPreference(Sched::Source);
705 setSchedulingPreference(Sched::Hybrid);
707 computeRegisterProperties();
709 // The Freescale cores do better with aggressive inlining of memcpy and
710 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
711 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
712 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
713 MaxStoresPerMemset = 32;
714 MaxStoresPerMemsetOptSize = 16;
715 MaxStoresPerMemcpy = 32;
716 MaxStoresPerMemcpyOptSize = 8;
717 MaxStoresPerMemmove = 32;
718 MaxStoresPerMemmoveOptSize = 8;
722 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
723 /// the desired ByVal argument alignment.
724 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
725 unsigned MaxMaxAlign) {
726 if (MaxAlign == MaxMaxAlign)
728 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
729 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
731 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
733 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
734 unsigned EltAlign = 0;
735 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
736 if (EltAlign > MaxAlign)
738 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
739 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
740 unsigned EltAlign = 0;
741 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
742 if (EltAlign > MaxAlign)
744 if (MaxAlign == MaxMaxAlign)
750 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
751 /// function arguments in the caller parameter area.
752 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
753 // Darwin passes everything on 4 byte boundary.
754 if (Subtarget.isDarwin())
757 // 16byte and wider vectors are passed on 16byte boundary.
758 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
759 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
760 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
761 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
765 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
767 default: return nullptr;
768 case PPCISD::FSEL: return "PPCISD::FSEL";
769 case PPCISD::FCFID: return "PPCISD::FCFID";
770 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
771 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
772 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
773 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
774 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
775 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
776 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
777 case PPCISD::FRE: return "PPCISD::FRE";
778 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
779 case PPCISD::STFIWX: return "PPCISD::STFIWX";
780 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
781 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
782 case PPCISD::VPERM: return "PPCISD::VPERM";
783 case PPCISD::CMPB: return "PPCISD::CMPB";
784 case PPCISD::Hi: return "PPCISD::Hi";
785 case PPCISD::Lo: return "PPCISD::Lo";
786 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
787 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
788 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
789 case PPCISD::SRL: return "PPCISD::SRL";
790 case PPCISD::SRA: return "PPCISD::SRA";
791 case PPCISD::SHL: return "PPCISD::SHL";
792 case PPCISD::CALL: return "PPCISD::CALL";
793 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
794 case PPCISD::CALL_TLS: return "PPCISD::CALL_TLS";
795 case PPCISD::CALL_NOP_TLS: return "PPCISD::CALL_NOP_TLS";
796 case PPCISD::MTCTR: return "PPCISD::MTCTR";
797 case PPCISD::BCTRL: return "PPCISD::BCTRL";
798 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
799 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
800 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
801 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
802 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
803 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
804 case PPCISD::VCMP: return "PPCISD::VCMP";
805 case PPCISD::VCMPo: return "PPCISD::VCMPo";
806 case PPCISD::LBRX: return "PPCISD::LBRX";
807 case PPCISD::STBRX: return "PPCISD::STBRX";
808 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
809 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
810 case PPCISD::LARX: return "PPCISD::LARX";
811 case PPCISD::STCX: return "PPCISD::STCX";
812 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
813 case PPCISD::BDNZ: return "PPCISD::BDNZ";
814 case PPCISD::BDZ: return "PPCISD::BDZ";
815 case PPCISD::MFFS: return "PPCISD::MFFS";
816 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
817 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
818 case PPCISD::CR6SET: return "PPCISD::CR6SET";
819 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
820 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
821 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
822 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
823 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
824 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
825 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
826 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
827 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
828 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
829 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
830 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
831 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
832 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
833 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
834 case PPCISD::SC: return "PPCISD::SC";
838 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
840 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
841 return VT.changeVectorElementTypeToInteger();
844 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
845 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
849 //===----------------------------------------------------------------------===//
850 // Node matching predicates, for use by the tblgen matching code.
851 //===----------------------------------------------------------------------===//
853 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
854 static bool isFloatingPointZero(SDValue Op) {
855 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
856 return CFP->getValueAPF().isZero();
857 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
858 // Maybe this has already been legalized into the constant pool?
859 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
860 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
861 return CFP->getValueAPF().isZero();
866 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
867 /// true if Op is undef or if it matches the specified value.
868 static bool isConstantOrUndef(int Op, int Val) {
869 return Op < 0 || Op == Val;
872 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
873 /// VPKUHUM instruction.
874 /// The ShuffleKind distinguishes between big-endian operations with
875 /// two different inputs (0), either-endian operations with two identical
876 /// inputs (1), and little-endian operantion with two different inputs (2).
877 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
878 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
880 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
881 if (ShuffleKind == 0) {
884 for (unsigned i = 0; i != 16; ++i)
885 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
887 } else if (ShuffleKind == 2) {
890 for (unsigned i = 0; i != 16; ++i)
891 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
893 } else if (ShuffleKind == 1) {
894 unsigned j = IsLE ? 0 : 1;
895 for (unsigned i = 0; i != 8; ++i)
896 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
897 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
903 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
904 /// VPKUWUM instruction.
905 /// The ShuffleKind distinguishes between big-endian operations with
906 /// two different inputs (0), either-endian operations with two identical
907 /// inputs (1), and little-endian operantion with two different inputs (2).
908 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
909 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
911 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
912 if (ShuffleKind == 0) {
915 for (unsigned i = 0; i != 16; i += 2)
916 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
917 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
919 } else if (ShuffleKind == 2) {
922 for (unsigned i = 0; i != 16; i += 2)
923 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
924 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
926 } else if (ShuffleKind == 1) {
927 unsigned j = IsLE ? 0 : 2;
928 for (unsigned i = 0; i != 8; i += 2)
929 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
930 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
931 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
932 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
938 /// isVMerge - Common function, used to match vmrg* shuffles.
940 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
941 unsigned LHSStart, unsigned RHSStart) {
942 if (N->getValueType(0) != MVT::v16i8)
944 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
945 "Unsupported merge size!");
947 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
948 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
949 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
950 LHSStart+j+i*UnitSize) ||
951 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
952 RHSStart+j+i*UnitSize))
958 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
959 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
960 /// The ShuffleKind distinguishes between big-endian merges with two
961 /// different inputs (0), either-endian merges with two identical inputs (1),
962 /// and little-endian merges with two different inputs (2). For the latter,
963 /// the input operands are swapped (see PPCInstrAltivec.td).
964 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
965 unsigned ShuffleKind, SelectionDAG &DAG) {
966 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
967 if (ShuffleKind == 1) // unary
968 return isVMerge(N, UnitSize, 0, 0);
969 else if (ShuffleKind == 2) // swapped
970 return isVMerge(N, UnitSize, 0, 16);
974 if (ShuffleKind == 1) // unary
975 return isVMerge(N, UnitSize, 8, 8);
976 else if (ShuffleKind == 0) // normal
977 return isVMerge(N, UnitSize, 8, 24);
983 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
984 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
985 /// The ShuffleKind distinguishes between big-endian merges with two
986 /// different inputs (0), either-endian merges with two identical inputs (1),
987 /// and little-endian merges with two different inputs (2). For the latter,
988 /// the input operands are swapped (see PPCInstrAltivec.td).
989 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
990 unsigned ShuffleKind, SelectionDAG &DAG) {
991 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
992 if (ShuffleKind == 1) // unary
993 return isVMerge(N, UnitSize, 8, 8);
994 else if (ShuffleKind == 2) // swapped
995 return isVMerge(N, UnitSize, 8, 24);
999 if (ShuffleKind == 1) // unary
1000 return isVMerge(N, UnitSize, 0, 0);
1001 else if (ShuffleKind == 0) // normal
1002 return isVMerge(N, UnitSize, 0, 16);
1009 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1010 /// amount, otherwise return -1.
1011 /// The ShuffleKind distinguishes between big-endian operations with two
1012 /// different inputs (0), either-endian operations with two identical inputs
1013 /// (1), and little-endian operations with two different inputs (2). For the
1014 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1015 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1016 SelectionDAG &DAG) {
1017 if (N->getValueType(0) != MVT::v16i8)
1020 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1022 // Find the first non-undef value in the shuffle mask.
1024 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1027 if (i == 16) return -1; // all undef.
1029 // Otherwise, check to see if the rest of the elements are consecutively
1030 // numbered from this value.
1031 unsigned ShiftAmt = SVOp->getMaskElt(i);
1032 if (ShiftAmt < i) return -1;
1035 bool isLE = DAG.getTarget().getSubtargetImpl()->getDataLayout()->
1038 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1039 // Check the rest of the elements to see if they are consecutive.
1040 for (++i; i != 16; ++i)
1041 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1043 } else if (ShuffleKind == 1) {
1044 // Check the rest of the elements to see if they are consecutive.
1045 for (++i; i != 16; ++i)
1046 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1051 if (ShuffleKind == 2 && isLE)
1052 ShiftAmt = 16 - ShiftAmt;
1057 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1058 /// specifies a splat of a single element that is suitable for input to
1059 /// VSPLTB/VSPLTH/VSPLTW.
1060 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1061 assert(N->getValueType(0) == MVT::v16i8 &&
1062 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1064 // This is a splat operation if each element of the permute is the same, and
1065 // if the value doesn't reference the second vector.
1066 unsigned ElementBase = N->getMaskElt(0);
1068 // FIXME: Handle UNDEF elements too!
1069 if (ElementBase >= 16)
1072 // Check that the indices are consecutive, in the case of a multi-byte element
1073 // splatted with a v16i8 mask.
1074 for (unsigned i = 1; i != EltSize; ++i)
1075 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1078 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1079 if (N->getMaskElt(i) < 0) continue;
1080 for (unsigned j = 0; j != EltSize; ++j)
1081 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1087 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1089 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1090 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1092 APInt APVal, APUndef;
1096 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1097 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1098 return CFP->getValueAPF().isNegZero();
1103 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1104 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1105 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1106 SelectionDAG &DAG) {
1107 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1108 assert(isSplatShuffleMask(SVOp, EltSize));
1109 if (DAG.getSubtarget().getDataLayout()->isLittleEndian())
1110 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1112 return SVOp->getMaskElt(0) / EltSize;
1115 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1116 /// by using a vspltis[bhw] instruction of the specified element size, return
1117 /// the constant being splatted. The ByteSize field indicates the number of
1118 /// bytes of each element [124] -> [bhw].
1119 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1120 SDValue OpVal(nullptr, 0);
1122 // If ByteSize of the splat is bigger than the element size of the
1123 // build_vector, then we have a case where we are checking for a splat where
1124 // multiple elements of the buildvector are folded together into a single
1125 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1126 unsigned EltSize = 16/N->getNumOperands();
1127 if (EltSize < ByteSize) {
1128 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1129 SDValue UniquedVals[4];
1130 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1132 // See if all of the elements in the buildvector agree across.
1133 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1134 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1135 // If the element isn't a constant, bail fully out.
1136 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1139 if (!UniquedVals[i&(Multiple-1)].getNode())
1140 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1141 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1142 return SDValue(); // no match.
1145 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1146 // either constant or undef values that are identical for each chunk. See
1147 // if these chunks can form into a larger vspltis*.
1149 // Check to see if all of the leading entries are either 0 or -1. If
1150 // neither, then this won't fit into the immediate field.
1151 bool LeadingZero = true;
1152 bool LeadingOnes = true;
1153 for (unsigned i = 0; i != Multiple-1; ++i) {
1154 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1156 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1157 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1159 // Finally, check the least significant entry.
1161 if (!UniquedVals[Multiple-1].getNode())
1162 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1163 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1165 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1168 if (!UniquedVals[Multiple-1].getNode())
1169 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1170 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1171 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1172 return DAG.getTargetConstant(Val, MVT::i32);
1178 // Check to see if this buildvec has a single non-undef value in its elements.
1179 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1180 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1181 if (!OpVal.getNode())
1182 OpVal = N->getOperand(i);
1183 else if (OpVal != N->getOperand(i))
1187 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1189 unsigned ValSizeInBytes = EltSize;
1191 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1192 Value = CN->getZExtValue();
1193 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1194 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1195 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1198 // If the splat value is larger than the element value, then we can never do
1199 // this splat. The only case that we could fit the replicated bits into our
1200 // immediate field for would be zero, and we prefer to use vxor for it.
1201 if (ValSizeInBytes < ByteSize) return SDValue();
1203 // If the element value is larger than the splat value, cut it in half and
1204 // check to see if the two halves are equal. Continue doing this until we
1205 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1206 while (ValSizeInBytes > ByteSize) {
1207 ValSizeInBytes >>= 1;
1209 // If the top half equals the bottom half, we're still ok.
1210 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1211 (Value & ((1 << (8*ValSizeInBytes))-1)))
1215 // Properly sign extend the value.
1216 int MaskVal = SignExtend32(Value, ByteSize * 8);
1218 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1219 if (MaskVal == 0) return SDValue();
1221 // Finally, if this value fits in a 5 bit sext field, return it
1222 if (SignExtend32<5>(MaskVal) == MaskVal)
1223 return DAG.getTargetConstant(MaskVal, MVT::i32);
1227 //===----------------------------------------------------------------------===//
1228 // Addressing Mode Selection
1229 //===----------------------------------------------------------------------===//
1231 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1232 /// or 64-bit immediate, and if the value can be accurately represented as a
1233 /// sign extension from a 16-bit value. If so, this returns true and the
1235 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1236 if (!isa<ConstantSDNode>(N))
1239 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1240 if (N->getValueType(0) == MVT::i32)
1241 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1243 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1245 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1246 return isIntS16Immediate(Op.getNode(), Imm);
1250 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1251 /// can be represented as an indexed [r+r] operation. Returns false if it
1252 /// can be more efficiently represented with [r+imm].
1253 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1255 SelectionDAG &DAG) const {
1257 if (N.getOpcode() == ISD::ADD) {
1258 if (isIntS16Immediate(N.getOperand(1), imm))
1259 return false; // r+i
1260 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1261 return false; // r+i
1263 Base = N.getOperand(0);
1264 Index = N.getOperand(1);
1266 } else if (N.getOpcode() == ISD::OR) {
1267 if (isIntS16Immediate(N.getOperand(1), imm))
1268 return false; // r+i can fold it if we can.
1270 // If this is an or of disjoint bitfields, we can codegen this as an add
1271 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1273 APInt LHSKnownZero, LHSKnownOne;
1274 APInt RHSKnownZero, RHSKnownOne;
1275 DAG.computeKnownBits(N.getOperand(0),
1276 LHSKnownZero, LHSKnownOne);
1278 if (LHSKnownZero.getBoolValue()) {
1279 DAG.computeKnownBits(N.getOperand(1),
1280 RHSKnownZero, RHSKnownOne);
1281 // If all of the bits are known zero on the LHS or RHS, the add won't
1283 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1284 Base = N.getOperand(0);
1285 Index = N.getOperand(1);
1294 // If we happen to be doing an i64 load or store into a stack slot that has
1295 // less than a 4-byte alignment, then the frame-index elimination may need to
1296 // use an indexed load or store instruction (because the offset may not be a
1297 // multiple of 4). The extra register needed to hold the offset comes from the
1298 // register scavenger, and it is possible that the scavenger will need to use
1299 // an emergency spill slot. As a result, we need to make sure that a spill slot
1300 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1302 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1303 // FIXME: This does not handle the LWA case.
1307 // NOTE: We'll exclude negative FIs here, which come from argument
1308 // lowering, because there are no known test cases triggering this problem
1309 // using packed structures (or similar). We can remove this exclusion if
1310 // we find such a test case. The reason why this is so test-case driven is
1311 // because this entire 'fixup' is only to prevent crashes (from the
1312 // register scavenger) on not-really-valid inputs. For example, if we have:
1314 // %b = bitcast i1* %a to i64*
1315 // store i64* a, i64 b
1316 // then the store should really be marked as 'align 1', but is not. If it
1317 // were marked as 'align 1' then the indexed form would have been
1318 // instruction-selected initially, and the problem this 'fixup' is preventing
1319 // won't happen regardless.
1323 MachineFunction &MF = DAG.getMachineFunction();
1324 MachineFrameInfo *MFI = MF.getFrameInfo();
1326 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1330 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1331 FuncInfo->setHasNonRISpills();
1334 /// Returns true if the address N can be represented by a base register plus
1335 /// a signed 16-bit displacement [r+imm], and if it is not better
1336 /// represented as reg+reg. If Aligned is true, only accept displacements
1337 /// suitable for STD and friends, i.e. multiples of 4.
1338 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1341 bool Aligned) const {
1342 // FIXME dl should come from parent load or store, not from address
1344 // If this can be more profitably realized as r+r, fail.
1345 if (SelectAddressRegReg(N, Disp, Base, DAG))
1348 if (N.getOpcode() == ISD::ADD) {
1350 if (isIntS16Immediate(N.getOperand(1), imm) &&
1351 (!Aligned || (imm & 3) == 0)) {
1352 Disp = DAG.getTargetConstant(imm, N.getValueType());
1353 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1354 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1355 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1357 Base = N.getOperand(0);
1359 return true; // [r+i]
1360 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1361 // Match LOAD (ADD (X, Lo(G))).
1362 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1363 && "Cannot handle constant offsets yet!");
1364 Disp = N.getOperand(1).getOperand(0); // The global address.
1365 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1366 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1367 Disp.getOpcode() == ISD::TargetConstantPool ||
1368 Disp.getOpcode() == ISD::TargetJumpTable);
1369 Base = N.getOperand(0);
1370 return true; // [&g+r]
1372 } else if (N.getOpcode() == ISD::OR) {
1374 if (isIntS16Immediate(N.getOperand(1), imm) &&
1375 (!Aligned || (imm & 3) == 0)) {
1376 // If this is an or of disjoint bitfields, we can codegen this as an add
1377 // (for better address arithmetic) if the LHS and RHS of the OR are
1378 // provably disjoint.
1379 APInt LHSKnownZero, LHSKnownOne;
1380 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1382 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1383 // If all of the bits are known zero on the LHS or RHS, the add won't
1385 if (FrameIndexSDNode *FI =
1386 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1387 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1388 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1390 Base = N.getOperand(0);
1392 Disp = DAG.getTargetConstant(imm, N.getValueType());
1396 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1397 // Loading from a constant address.
1399 // If this address fits entirely in a 16-bit sext immediate field, codegen
1402 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1403 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1404 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1405 CN->getValueType(0));
1409 // Handle 32-bit sext immediates with LIS + addr mode.
1410 if ((CN->getValueType(0) == MVT::i32 ||
1411 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1412 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1413 int Addr = (int)CN->getZExtValue();
1415 // Otherwise, break this down into an LIS + disp.
1416 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1418 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1419 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1420 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1425 Disp = DAG.getTargetConstant(0, getPointerTy());
1426 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1427 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1428 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1431 return true; // [r+0]
1434 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1435 /// represented as an indexed [r+r] operation.
1436 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1438 SelectionDAG &DAG) const {
1439 // Check to see if we can easily represent this as an [r+r] address. This
1440 // will fail if it thinks that the address is more profitably represented as
1441 // reg+imm, e.g. where imm = 0.
1442 if (SelectAddressRegReg(N, Base, Index, DAG))
1445 // If the operand is an addition, always emit this as [r+r], since this is
1446 // better (for code size, and execution, as the memop does the add for free)
1447 // than emitting an explicit add.
1448 if (N.getOpcode() == ISD::ADD) {
1449 Base = N.getOperand(0);
1450 Index = N.getOperand(1);
1454 // Otherwise, do it the hard way, using R0 as the base register.
1455 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1461 /// getPreIndexedAddressParts - returns true by value, base pointer and
1462 /// offset pointer and addressing mode by reference if the node's address
1463 /// can be legally represented as pre-indexed load / store address.
1464 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1466 ISD::MemIndexedMode &AM,
1467 SelectionDAG &DAG) const {
1468 if (DisablePPCPreinc) return false;
1474 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1475 Ptr = LD->getBasePtr();
1476 VT = LD->getMemoryVT();
1477 Alignment = LD->getAlignment();
1478 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1479 Ptr = ST->getBasePtr();
1480 VT = ST->getMemoryVT();
1481 Alignment = ST->getAlignment();
1486 // PowerPC doesn't have preinc load/store instructions for vectors.
1490 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1492 // Common code will reject creating a pre-inc form if the base pointer
1493 // is a frame index, or if N is a store and the base pointer is either
1494 // the same as or a predecessor of the value being stored. Check for
1495 // those situations here, and try with swapped Base/Offset instead.
1498 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1501 SDValue Val = cast<StoreSDNode>(N)->getValue();
1502 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1507 std::swap(Base, Offset);
1513 // LDU/STU can only handle immediates that are a multiple of 4.
1514 if (VT != MVT::i64) {
1515 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1518 // LDU/STU need an address with at least 4-byte alignment.
1522 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1526 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1527 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1528 // sext i32 to i64 when addr mode is r+i.
1529 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1530 LD->getExtensionType() == ISD::SEXTLOAD &&
1531 isa<ConstantSDNode>(Offset))
1539 //===----------------------------------------------------------------------===//
1540 // LowerOperation implementation
1541 //===----------------------------------------------------------------------===//
1543 /// GetLabelAccessInfo - Return true if we should reference labels using a
1544 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1545 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1546 unsigned &LoOpFlags,
1547 const GlobalValue *GV = nullptr) {
1548 HiOpFlags = PPCII::MO_HA;
1549 LoOpFlags = PPCII::MO_LO;
1551 // Don't use the pic base if not in PIC relocation model.
1552 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1555 HiOpFlags |= PPCII::MO_PIC_FLAG;
1556 LoOpFlags |= PPCII::MO_PIC_FLAG;
1559 // If this is a reference to a global value that requires a non-lazy-ptr, make
1560 // sure that instruction lowering adds it.
1561 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1562 HiOpFlags |= PPCII::MO_NLP_FLAG;
1563 LoOpFlags |= PPCII::MO_NLP_FLAG;
1565 if (GV->hasHiddenVisibility()) {
1566 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1567 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1574 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1575 SelectionDAG &DAG) {
1576 EVT PtrVT = HiPart.getValueType();
1577 SDValue Zero = DAG.getConstant(0, PtrVT);
1580 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1581 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1583 // With PIC, the first instruction is actually "GR+hi(&G)".
1585 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1586 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1588 // Generate non-pic code that has direct accesses to the constant pool.
1589 // The address of the global is just (hi(&g)+lo(&g)).
1590 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1593 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1594 SelectionDAG &DAG) const {
1595 EVT PtrVT = Op.getValueType();
1596 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1597 const Constant *C = CP->getConstVal();
1599 // 64-bit SVR4 ABI code is always position-independent.
1600 // The actual address of the GlobalValue is stored in the TOC.
1601 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1602 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1603 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1604 DAG.getRegister(PPC::X2, MVT::i64));
1607 unsigned MOHiFlag, MOLoFlag;
1608 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1610 if (isPIC && Subtarget.isSVR4ABI()) {
1611 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1612 PPCII::MO_PIC_FLAG);
1614 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1615 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1619 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1621 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1622 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1625 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1626 EVT PtrVT = Op.getValueType();
1627 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1629 // 64-bit SVR4 ABI code is always position-independent.
1630 // The actual address of the GlobalValue is stored in the TOC.
1631 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1632 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1633 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1634 DAG.getRegister(PPC::X2, MVT::i64));
1637 unsigned MOHiFlag, MOLoFlag;
1638 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1640 if (isPIC && Subtarget.isSVR4ABI()) {
1641 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1642 PPCII::MO_PIC_FLAG);
1644 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1645 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1648 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1649 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1650 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1653 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1654 SelectionDAG &DAG) const {
1655 EVT PtrVT = Op.getValueType();
1656 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
1657 const BlockAddress *BA = BASDN->getBlockAddress();
1659 // 64-bit SVR4 ABI code is always position-independent.
1660 // The actual BlockAddress is stored in the TOC.
1661 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1662 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
1663 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(BASDN), MVT::i64, GA,
1664 DAG.getRegister(PPC::X2, MVT::i64));
1667 unsigned MOHiFlag, MOLoFlag;
1668 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1669 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1670 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1671 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1674 // Generate a call to __tls_get_addr for the given GOT entry Op.
1675 std::pair<SDValue,SDValue>
1676 PPCTargetLowering::lowerTLSCall(SDValue Op, SDLoc dl,
1677 SelectionDAG &DAG) const {
1679 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
1680 TargetLowering::ArgListTy Args;
1681 TargetLowering::ArgListEntry Entry;
1683 Entry.Ty = IntPtrTy;
1684 Args.push_back(Entry);
1686 TargetLowering::CallLoweringInfo CLI(DAG);
1687 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1688 .setCallee(CallingConv::C, IntPtrTy,
1689 DAG.getTargetExternalSymbol("__tls_get_addr", getPointerTy()),
1690 std::move(Args), 0);
1692 return LowerCallTo(CLI);
1695 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1696 SelectionDAG &DAG) const {
1698 // FIXME: TLS addresses currently use medium model code sequences,
1699 // which is the most useful form. Eventually support for small and
1700 // large models could be added if users need it, at the cost of
1701 // additional complexity.
1702 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1704 const GlobalValue *GV = GA->getGlobal();
1705 EVT PtrVT = getPointerTy();
1706 bool is64bit = Subtarget.isPPC64();
1707 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
1708 PICLevel::Level picLevel = M->getPICLevel();
1710 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1712 if (Model == TLSModel::LocalExec) {
1713 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1714 PPCII::MO_TPREL_HA);
1715 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1716 PPCII::MO_TPREL_LO);
1717 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1718 is64bit ? MVT::i64 : MVT::i32);
1719 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1720 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1723 if (Model == TLSModel::InitialExec) {
1724 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1725 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1729 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1730 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1731 PtrVT, GOTReg, TGA);
1733 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1734 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1735 PtrVT, TGA, GOTPtr);
1736 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1739 if (Model == TLSModel::GeneralDynamic) {
1740 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1744 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1745 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1748 if (picLevel == PICLevel::Small)
1749 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1751 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1753 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1755 std::pair<SDValue, SDValue> CallResult = lowerTLSCall(GOTEntry, dl, DAG);
1756 return CallResult.first;
1759 if (Model == TLSModel::LocalDynamic) {
1760 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1764 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1765 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1768 if (picLevel == PICLevel::Small)
1769 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1771 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1773 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1775 std::pair<SDValue, SDValue> CallResult = lowerTLSCall(GOTEntry, dl, DAG);
1776 SDValue TLSAddr = CallResult.first;
1777 SDValue Chain = CallResult.second;
1778 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1779 Chain, TLSAddr, TGA);
1780 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1783 llvm_unreachable("Unknown TLS model!");
1786 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1787 SelectionDAG &DAG) const {
1788 EVT PtrVT = Op.getValueType();
1789 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1791 const GlobalValue *GV = GSDN->getGlobal();
1793 // 64-bit SVR4 ABI code is always position-independent.
1794 // The actual address of the GlobalValue is stored in the TOC.
1795 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1796 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1797 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1798 DAG.getRegister(PPC::X2, MVT::i64));
1801 unsigned MOHiFlag, MOLoFlag;
1802 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1804 if (isPIC && Subtarget.isSVR4ABI()) {
1805 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1807 PPCII::MO_PIC_FLAG);
1808 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1809 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1813 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1815 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1817 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1819 // If the global reference is actually to a non-lazy-pointer, we have to do an
1820 // extra load to get the address of the global.
1821 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1822 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1823 false, false, false, 0);
1827 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1828 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1831 if (Op.getValueType() == MVT::v2i64) {
1832 // When the operands themselves are v2i64 values, we need to do something
1833 // special because VSX has no underlying comparison operations for these.
1834 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1835 // Equality can be handled by casting to the legal type for Altivec
1836 // comparisons, everything else needs to be expanded.
1837 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1838 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1839 DAG.getSetCC(dl, MVT::v4i32,
1840 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1841 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1848 // We handle most of these in the usual way.
1852 // If we're comparing for equality to zero, expose the fact that this is
1853 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1854 // fold the new nodes.
1855 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1856 if (C->isNullValue() && CC == ISD::SETEQ) {
1857 EVT VT = Op.getOperand(0).getValueType();
1858 SDValue Zext = Op.getOperand(0);
1859 if (VT.bitsLT(MVT::i32)) {
1861 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1863 unsigned Log2b = Log2_32(VT.getSizeInBits());
1864 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1865 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1866 DAG.getConstant(Log2b, MVT::i32));
1867 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1869 // Leave comparisons against 0 and -1 alone for now, since they're usually
1870 // optimized. FIXME: revisit this when we can custom lower all setcc
1872 if (C->isAllOnesValue() || C->isNullValue())
1876 // If we have an integer seteq/setne, turn it into a compare against zero
1877 // by xor'ing the rhs with the lhs, which is faster than setting a
1878 // condition register, reading it back out, and masking the correct bit. The
1879 // normal approach here uses sub to do this instead of xor. Using xor exposes
1880 // the result to other bit-twiddling opportunities.
1881 EVT LHSVT = Op.getOperand(0).getValueType();
1882 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1883 EVT VT = Op.getValueType();
1884 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1886 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1891 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1892 const PPCSubtarget &Subtarget) const {
1893 SDNode *Node = Op.getNode();
1894 EVT VT = Node->getValueType(0);
1895 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1896 SDValue InChain = Node->getOperand(0);
1897 SDValue VAListPtr = Node->getOperand(1);
1898 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1901 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1904 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1905 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1906 false, false, false, 0);
1907 InChain = GprIndex.getValue(1);
1909 if (VT == MVT::i64) {
1910 // Check if GprIndex is even
1911 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1912 DAG.getConstant(1, MVT::i32));
1913 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1914 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1915 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1916 DAG.getConstant(1, MVT::i32));
1917 // Align GprIndex to be even if it isn't
1918 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1922 // fpr index is 1 byte after gpr
1923 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1924 DAG.getConstant(1, MVT::i32));
1927 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1928 FprPtr, MachinePointerInfo(SV), MVT::i8,
1929 false, false, false, 0);
1930 InChain = FprIndex.getValue(1);
1932 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1933 DAG.getConstant(8, MVT::i32));
1935 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1936 DAG.getConstant(4, MVT::i32));
1939 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1940 MachinePointerInfo(), false, false,
1942 InChain = OverflowArea.getValue(1);
1944 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1945 MachinePointerInfo(), false, false,
1947 InChain = RegSaveArea.getValue(1);
1949 // select overflow_area if index > 8
1950 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1951 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1953 // adjustment constant gpr_index * 4/8
1954 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1955 VT.isInteger() ? GprIndex : FprIndex,
1956 DAG.getConstant(VT.isInteger() ? 4 : 8,
1959 // OurReg = RegSaveArea + RegConstant
1960 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1963 // Floating types are 32 bytes into RegSaveArea
1964 if (VT.isFloatingPoint())
1965 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1966 DAG.getConstant(32, MVT::i32));
1968 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1969 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1970 VT.isInteger() ? GprIndex : FprIndex,
1971 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1974 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1975 VT.isInteger() ? VAListPtr : FprPtr,
1976 MachinePointerInfo(SV),
1977 MVT::i8, false, false, 0);
1979 // determine if we should load from reg_save_area or overflow_area
1980 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1982 // increase overflow_area by 4/8 if gpr/fpr > 8
1983 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1984 DAG.getConstant(VT.isInteger() ? 4 : 8,
1987 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1990 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1992 MachinePointerInfo(),
1993 MVT::i32, false, false, 0);
1995 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1996 false, false, false, 0);
1999 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2000 const PPCSubtarget &Subtarget) const {
2001 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2003 // We have to copy the entire va_list struct:
2004 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2005 return DAG.getMemcpy(Op.getOperand(0), Op,
2006 Op.getOperand(1), Op.getOperand(2),
2007 DAG.getConstant(12, MVT::i32), 8, false, true,
2008 MachinePointerInfo(), MachinePointerInfo());
2011 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2012 SelectionDAG &DAG) const {
2013 return Op.getOperand(0);
2016 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2017 SelectionDAG &DAG) const {
2018 SDValue Chain = Op.getOperand(0);
2019 SDValue Trmp = Op.getOperand(1); // trampoline
2020 SDValue FPtr = Op.getOperand(2); // nested function
2021 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2024 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2025 bool isPPC64 = (PtrVT == MVT::i64);
2027 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2030 TargetLowering::ArgListTy Args;
2031 TargetLowering::ArgListEntry Entry;
2033 Entry.Ty = IntPtrTy;
2034 Entry.Node = Trmp; Args.push_back(Entry);
2036 // TrampSize == (isPPC64 ? 48 : 40);
2037 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2038 isPPC64 ? MVT::i64 : MVT::i32);
2039 Args.push_back(Entry);
2041 Entry.Node = FPtr; Args.push_back(Entry);
2042 Entry.Node = Nest; Args.push_back(Entry);
2044 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2045 TargetLowering::CallLoweringInfo CLI(DAG);
2046 CLI.setDebugLoc(dl).setChain(Chain)
2047 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2048 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2049 std::move(Args), 0);
2051 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2052 return CallResult.second;
2055 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2056 const PPCSubtarget &Subtarget) const {
2057 MachineFunction &MF = DAG.getMachineFunction();
2058 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2062 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2063 // vastart just stores the address of the VarArgsFrameIndex slot into the
2064 // memory location argument.
2065 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2066 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2067 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2068 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2069 MachinePointerInfo(SV),
2073 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2074 // We suppose the given va_list is already allocated.
2077 // char gpr; /* index into the array of 8 GPRs
2078 // * stored in the register save area
2079 // * gpr=0 corresponds to r3,
2080 // * gpr=1 to r4, etc.
2082 // char fpr; /* index into the array of 8 FPRs
2083 // * stored in the register save area
2084 // * fpr=0 corresponds to f1,
2085 // * fpr=1 to f2, etc.
2087 // char *overflow_arg_area;
2088 // /* location on stack that holds
2089 // * the next overflow argument
2091 // char *reg_save_area;
2092 // /* where r3:r10 and f1:f8 (if saved)
2098 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2099 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2102 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2104 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2106 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2109 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2110 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2112 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2113 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2115 uint64_t FPROffset = 1;
2116 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2118 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2120 // Store first byte : number of int regs
2121 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2123 MachinePointerInfo(SV),
2124 MVT::i8, false, false, 0);
2125 uint64_t nextOffset = FPROffset;
2126 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2129 // Store second byte : number of float regs
2130 SDValue secondStore =
2131 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2132 MachinePointerInfo(SV, nextOffset), MVT::i8,
2134 nextOffset += StackOffset;
2135 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2137 // Store second word : arguments given on stack
2138 SDValue thirdStore =
2139 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2140 MachinePointerInfo(SV, nextOffset),
2142 nextOffset += FrameOffset;
2143 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2145 // Store third word : arguments given in registers
2146 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2147 MachinePointerInfo(SV, nextOffset),
2152 #include "PPCGenCallingConv.inc"
2154 // Function whose sole purpose is to kill compiler warnings
2155 // stemming from unused functions included from PPCGenCallingConv.inc.
2156 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2157 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2160 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2161 CCValAssign::LocInfo &LocInfo,
2162 ISD::ArgFlagsTy &ArgFlags,
2167 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2169 CCValAssign::LocInfo &LocInfo,
2170 ISD::ArgFlagsTy &ArgFlags,
2172 static const MCPhysReg ArgRegs[] = {
2173 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2174 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2176 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2178 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2180 // Skip one register if the first unallocated register has an even register
2181 // number and there are still argument registers available which have not been
2182 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2183 // need to skip a register if RegNum is odd.
2184 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2185 State.AllocateReg(ArgRegs[RegNum]);
2188 // Always return false here, as this function only makes sure that the first
2189 // unallocated register has an odd register number and does not actually
2190 // allocate a register for the current argument.
2194 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2196 CCValAssign::LocInfo &LocInfo,
2197 ISD::ArgFlagsTy &ArgFlags,
2199 static const MCPhysReg ArgRegs[] = {
2200 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2204 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2206 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2208 // If there is only one Floating-point register left we need to put both f64
2209 // values of a split ppc_fp128 value on the stack.
2210 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2211 State.AllocateReg(ArgRegs[RegNum]);
2214 // Always return false here, as this function only makes sure that the two f64
2215 // values a ppc_fp128 value is split into are both passed in registers or both
2216 // passed on the stack and does not actually allocate a register for the
2217 // current argument.
2221 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2223 static const MCPhysReg *GetFPR() {
2224 static const MCPhysReg FPR[] = {
2225 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2226 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2232 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2234 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2235 unsigned PtrByteSize) {
2236 unsigned ArgSize = ArgVT.getStoreSize();
2237 if (Flags.isByVal())
2238 ArgSize = Flags.getByValSize();
2240 // Round up to multiples of the pointer size, except for array members,
2241 // which are always packed.
2242 if (!Flags.isInConsecutiveRegs())
2243 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2248 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2250 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2251 ISD::ArgFlagsTy Flags,
2252 unsigned PtrByteSize) {
2253 unsigned Align = PtrByteSize;
2255 // Altivec parameters are padded to a 16 byte boundary.
2256 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2257 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2258 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2261 // ByVal parameters are aligned as requested.
2262 if (Flags.isByVal()) {
2263 unsigned BVAlign = Flags.getByValAlign();
2264 if (BVAlign > PtrByteSize) {
2265 if (BVAlign % PtrByteSize != 0)
2267 "ByVal alignment is not a multiple of the pointer size");
2273 // Array members are always packed to their original alignment.
2274 if (Flags.isInConsecutiveRegs()) {
2275 // If the array member was split into multiple registers, the first
2276 // needs to be aligned to the size of the full type. (Except for
2277 // ppcf128, which is only aligned as its f64 components.)
2278 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2279 Align = OrigVT.getStoreSize();
2281 Align = ArgVT.getStoreSize();
2287 /// CalculateStackSlotUsed - Return whether this argument will use its
2288 /// stack slot (instead of being passed in registers). ArgOffset,
2289 /// AvailableFPRs, and AvailableVRs must hold the current argument
2290 /// position, and will be updated to account for this argument.
2291 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2292 ISD::ArgFlagsTy Flags,
2293 unsigned PtrByteSize,
2294 unsigned LinkageSize,
2295 unsigned ParamAreaSize,
2296 unsigned &ArgOffset,
2297 unsigned &AvailableFPRs,
2298 unsigned &AvailableVRs) {
2299 bool UseMemory = false;
2301 // Respect alignment of argument on the stack.
2303 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2304 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2305 // If there's no space left in the argument save area, we must
2306 // use memory (this check also catches zero-sized arguments).
2307 if (ArgOffset >= LinkageSize + ParamAreaSize)
2310 // Allocate argument on the stack.
2311 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2312 if (Flags.isInConsecutiveRegsLast())
2313 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2314 // If we overran the argument save area, we must use memory
2315 // (this check catches arguments passed partially in memory)
2316 if (ArgOffset > LinkageSize + ParamAreaSize)
2319 // However, if the argument is actually passed in an FPR or a VR,
2320 // we don't use memory after all.
2321 if (!Flags.isByVal()) {
2322 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2323 if (AvailableFPRs > 0) {
2327 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2328 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2329 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2330 if (AvailableVRs > 0) {
2339 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2340 /// ensure minimum alignment required for target.
2341 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2342 unsigned NumBytes) {
2343 unsigned TargetAlign =
2344 Target.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
2345 unsigned AlignMask = TargetAlign - 1;
2346 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2351 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2352 CallingConv::ID CallConv, bool isVarArg,
2353 const SmallVectorImpl<ISD::InputArg>
2355 SDLoc dl, SelectionDAG &DAG,
2356 SmallVectorImpl<SDValue> &InVals)
2358 if (Subtarget.isSVR4ABI()) {
2359 if (Subtarget.isPPC64())
2360 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2363 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2366 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2372 PPCTargetLowering::LowerFormalArguments_32SVR4(
2374 CallingConv::ID CallConv, bool isVarArg,
2375 const SmallVectorImpl<ISD::InputArg>
2377 SDLoc dl, SelectionDAG &DAG,
2378 SmallVectorImpl<SDValue> &InVals) const {
2380 // 32-bit SVR4 ABI Stack Frame Layout:
2381 // +-----------------------------------+
2382 // +--> | Back chain |
2383 // | +-----------------------------------+
2384 // | | Floating-point register save area |
2385 // | +-----------------------------------+
2386 // | | General register save area |
2387 // | +-----------------------------------+
2388 // | | CR save word |
2389 // | +-----------------------------------+
2390 // | | VRSAVE save word |
2391 // | +-----------------------------------+
2392 // | | Alignment padding |
2393 // | +-----------------------------------+
2394 // | | Vector register save area |
2395 // | +-----------------------------------+
2396 // | | Local variable space |
2397 // | +-----------------------------------+
2398 // | | Parameter list area |
2399 // | +-----------------------------------+
2400 // | | LR save word |
2401 // | +-----------------------------------+
2402 // SP--> +--- | Back chain |
2403 // +-----------------------------------+
2406 // System V Application Binary Interface PowerPC Processor Supplement
2407 // AltiVec Technology Programming Interface Manual
2409 MachineFunction &MF = DAG.getMachineFunction();
2410 MachineFrameInfo *MFI = MF.getFrameInfo();
2411 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2413 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2414 // Potential tail calls could cause overwriting of argument stack slots.
2415 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2416 (CallConv == CallingConv::Fast));
2417 unsigned PtrByteSize = 4;
2419 // Assign locations to all of the incoming arguments.
2420 SmallVector<CCValAssign, 16> ArgLocs;
2421 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2424 // Reserve space for the linkage area on the stack.
2425 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2426 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2428 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2430 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2431 CCValAssign &VA = ArgLocs[i];
2433 // Arguments stored in registers.
2434 if (VA.isRegLoc()) {
2435 const TargetRegisterClass *RC;
2436 EVT ValVT = VA.getValVT();
2438 switch (ValVT.getSimpleVT().SimpleTy) {
2440 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2443 RC = &PPC::GPRCRegClass;
2446 RC = &PPC::F4RCRegClass;
2449 if (Subtarget.hasVSX())
2450 RC = &PPC::VSFRCRegClass;
2452 RC = &PPC::F8RCRegClass;
2458 RC = &PPC::VRRCRegClass;
2462 RC = &PPC::VSHRCRegClass;
2466 // Transform the arguments stored in physical registers into virtual ones.
2467 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2468 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2469 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2471 if (ValVT == MVT::i1)
2472 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2474 InVals.push_back(ArgValue);
2476 // Argument stored in memory.
2477 assert(VA.isMemLoc());
2479 unsigned ArgSize = VA.getLocVT().getStoreSize();
2480 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2483 // Create load nodes to retrieve arguments from the stack.
2484 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2485 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2486 MachinePointerInfo(),
2487 false, false, false, 0));
2491 // Assign locations to all of the incoming aggregate by value arguments.
2492 // Aggregates passed by value are stored in the local variable space of the
2493 // caller's stack frame, right above the parameter list area.
2494 SmallVector<CCValAssign, 16> ByValArgLocs;
2495 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2496 ByValArgLocs, *DAG.getContext());
2498 // Reserve stack space for the allocations in CCInfo.
2499 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2501 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2503 // Area that is at least reserved in the caller of this function.
2504 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2505 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2507 // Set the size that is at least reserved in caller of this function. Tail
2508 // call optimized function's reserved stack space needs to be aligned so that
2509 // taking the difference between two stack areas will result in an aligned
2511 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2512 FuncInfo->setMinReservedArea(MinReservedArea);
2514 SmallVector<SDValue, 8> MemOps;
2516 // If the function takes variable number of arguments, make a frame index for
2517 // the start of the first vararg value... for expansion of llvm.va_start.
2519 static const MCPhysReg GPArgRegs[] = {
2520 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2521 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2523 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2525 static const MCPhysReg FPArgRegs[] = {
2526 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2529 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2530 if (DisablePPCFloatInVariadic)
2533 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2535 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2538 // Make room for NumGPArgRegs and NumFPArgRegs.
2539 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2540 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2542 FuncInfo->setVarArgsStackOffset(
2543 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2544 CCInfo.getNextStackOffset(), true));
2546 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2547 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2549 // The fixed integer arguments of a variadic function are stored to the
2550 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2551 // the result of va_next.
2552 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2553 // Get an existing live-in vreg, or add a new one.
2554 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2556 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2558 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2559 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2560 MachinePointerInfo(), false, false, 0);
2561 MemOps.push_back(Store);
2562 // Increment the address by four for the next argument to store
2563 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2564 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2567 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2569 // The double arguments are stored to the VarArgsFrameIndex
2571 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2572 // Get an existing live-in vreg, or add a new one.
2573 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2575 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2577 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2578 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2579 MachinePointerInfo(), false, false, 0);
2580 MemOps.push_back(Store);
2581 // Increment the address by eight for the next argument to store
2582 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
2584 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2588 if (!MemOps.empty())
2589 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2594 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2595 // value to MVT::i64 and then truncate to the correct register size.
2597 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2598 SelectionDAG &DAG, SDValue ArgVal,
2601 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2602 DAG.getValueType(ObjectVT));
2603 else if (Flags.isZExt())
2604 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2605 DAG.getValueType(ObjectVT));
2607 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2611 PPCTargetLowering::LowerFormalArguments_64SVR4(
2613 CallingConv::ID CallConv, bool isVarArg,
2614 const SmallVectorImpl<ISD::InputArg>
2616 SDLoc dl, SelectionDAG &DAG,
2617 SmallVectorImpl<SDValue> &InVals) const {
2618 // TODO: add description of PPC stack frame format, or at least some docs.
2620 bool isELFv2ABI = Subtarget.isELFv2ABI();
2621 bool isLittleEndian = Subtarget.isLittleEndian();
2622 MachineFunction &MF = DAG.getMachineFunction();
2623 MachineFrameInfo *MFI = MF.getFrameInfo();
2624 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2626 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
2627 "fastcc not supported on varargs functions");
2629 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2630 // Potential tail calls could cause overwriting of argument stack slots.
2631 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2632 (CallConv == CallingConv::Fast));
2633 unsigned PtrByteSize = 8;
2635 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2638 static const MCPhysReg GPR[] = {
2639 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2640 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2643 static const MCPhysReg *FPR = GetFPR();
2645 static const MCPhysReg VR[] = {
2646 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2647 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2649 static const MCPhysReg VSRH[] = {
2650 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2651 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2654 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2655 const unsigned Num_FPR_Regs = 13;
2656 const unsigned Num_VR_Regs = array_lengthof(VR);
2658 // Do a first pass over the arguments to determine whether the ABI
2659 // guarantees that our caller has allocated the parameter save area
2660 // on its stack frame. In the ELFv1 ABI, this is always the case;
2661 // in the ELFv2 ABI, it is true if this is a vararg function or if
2662 // any parameter is located in a stack slot.
2664 bool HasParameterArea = !isELFv2ABI || isVarArg;
2665 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2666 unsigned NumBytes = LinkageSize;
2667 unsigned AvailableFPRs = Num_FPR_Regs;
2668 unsigned AvailableVRs = Num_VR_Regs;
2669 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2670 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2671 PtrByteSize, LinkageSize, ParamAreaSize,
2672 NumBytes, AvailableFPRs, AvailableVRs))
2673 HasParameterArea = true;
2675 // Add DAG nodes to load the arguments or copy them out of registers. On
2676 // entry to a function on PPC, the arguments start after the linkage area,
2677 // although the first ones are often in registers.
2679 unsigned ArgOffset = LinkageSize;
2680 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2681 SmallVector<SDValue, 8> MemOps;
2682 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2683 unsigned CurArgIdx = 0;
2684 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2686 bool needsLoad = false;
2687 EVT ObjectVT = Ins[ArgNo].VT;
2688 EVT OrigVT = Ins[ArgNo].ArgVT;
2689 unsigned ObjSize = ObjectVT.getStoreSize();
2690 unsigned ArgSize = ObjSize;
2691 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2692 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2693 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2695 // We re-align the argument offset for each argument, except when using the
2696 // fast calling convention, when we need to make sure we do that only when
2697 // we'll actually use a stack slot.
2698 unsigned CurArgOffset, Align;
2699 auto ComputeArgOffset = [&]() {
2700 /* Respect alignment of argument on the stack. */
2701 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2702 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2703 CurArgOffset = ArgOffset;
2706 if (CallConv != CallingConv::Fast) {
2709 /* Compute GPR index associated with argument offset. */
2710 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2711 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2714 // FIXME the codegen can be much improved in some cases.
2715 // We do not have to keep everything in memory.
2716 if (Flags.isByVal()) {
2717 if (CallConv == CallingConv::Fast)
2720 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2721 ObjSize = Flags.getByValSize();
2722 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2723 // Empty aggregate parameters do not take up registers. Examples:
2727 // etc. However, we have to provide a place-holder in InVals, so
2728 // pretend we have an 8-byte item at the current address for that
2731 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2732 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2733 InVals.push_back(FIN);
2737 // Create a stack object covering all stack doublewords occupied
2738 // by the argument. If the argument is (fully or partially) on
2739 // the stack, or if the argument is fully in registers but the
2740 // caller has allocated the parameter save anyway, we can refer
2741 // directly to the caller's stack frame. Otherwise, create a
2742 // local copy in our own frame.
2744 if (HasParameterArea ||
2745 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2746 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
2748 FI = MFI->CreateStackObject(ArgSize, Align, false);
2749 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2751 // Handle aggregates smaller than 8 bytes.
2752 if (ObjSize < PtrByteSize) {
2753 // The value of the object is its address, which differs from the
2754 // address of the enclosing doubleword on big-endian systems.
2756 if (!isLittleEndian) {
2757 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2758 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2760 InVals.push_back(Arg);
2762 if (GPR_idx != Num_GPR_Regs) {
2763 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
2764 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2767 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2768 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2769 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2770 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2771 MachinePointerInfo(FuncArg),
2772 ObjType, false, false, 0);
2774 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2775 // store the whole register as-is to the parameter save area
2777 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2778 MachinePointerInfo(FuncArg),
2782 MemOps.push_back(Store);
2784 // Whether we copied from a register or not, advance the offset
2785 // into the parameter save area by a full doubleword.
2786 ArgOffset += PtrByteSize;
2790 // The value of the object is its address, which is the address of
2791 // its first stack doubleword.
2792 InVals.push_back(FIN);
2794 // Store whatever pieces of the object are in registers to memory.
2795 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2796 if (GPR_idx == Num_GPR_Regs)
2799 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2800 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2803 SDValue Off = DAG.getConstant(j, PtrVT);
2804 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2806 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2807 MachinePointerInfo(FuncArg, j),
2809 MemOps.push_back(Store);
2812 ArgOffset += ArgSize;
2816 switch (ObjectVT.getSimpleVT().SimpleTy) {
2817 default: llvm_unreachable("Unhandled argument type!");
2821 // These can be scalar arguments or elements of an integer array type
2822 // passed directly. Clang may use those instead of "byval" aggregate
2823 // types to avoid forcing arguments to memory unnecessarily.
2824 if (GPR_idx != Num_GPR_Regs) {
2825 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
2826 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2828 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2829 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2830 // value to MVT::i64 and then truncate to the correct register size.
2831 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2833 if (CallConv == CallingConv::Fast)
2837 ArgSize = PtrByteSize;
2839 if (CallConv != CallingConv::Fast || needsLoad)
2845 // These can be scalar arguments or elements of a float array type
2846 // passed directly. The latter are used to implement ELFv2 homogenous
2847 // float aggregates.
2848 if (FPR_idx != Num_FPR_Regs) {
2851 if (ObjectVT == MVT::f32)
2852 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2854 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2855 &PPC::VSFRCRegClass :
2856 &PPC::F8RCRegClass);
2858 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2860 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
2861 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
2862 // once we support fp <-> gpr moves.
2864 // This can only ever happen in the presence of f32 array types,
2865 // since otherwise we never run out of FPRs before running out
2867 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
2868 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2870 if (ObjectVT == MVT::f32) {
2871 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2872 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2873 DAG.getConstant(32, MVT::i32));
2874 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2877 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2879 if (CallConv == CallingConv::Fast)
2885 // When passing an array of floats, the array occupies consecutive
2886 // space in the argument area; only round up to the next doubleword
2887 // at the end of the array. Otherwise, each float takes 8 bytes.
2888 if (CallConv != CallingConv::Fast || needsLoad) {
2889 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2890 ArgOffset += ArgSize;
2891 if (Flags.isInConsecutiveRegsLast())
2892 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2901 // These can be scalar arguments or elements of a vector array type
2902 // passed directly. The latter are used to implement ELFv2 homogenous
2903 // vector aggregates.
2904 if (VR_idx != Num_VR_Regs) {
2905 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2906 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2907 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2908 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2911 if (CallConv == CallingConv::Fast)
2916 if (CallConv != CallingConv::Fast || needsLoad)
2921 // We need to load the argument to a virtual register if we determined
2922 // above that we ran out of physical registers of the appropriate type.
2924 if (ObjSize < ArgSize && !isLittleEndian)
2925 CurArgOffset += ArgSize - ObjSize;
2926 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2927 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2928 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2929 false, false, false, 0);
2932 InVals.push_back(ArgVal);
2935 // Area that is at least reserved in the caller of this function.
2936 unsigned MinReservedArea;
2937 if (HasParameterArea)
2938 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2940 MinReservedArea = LinkageSize;
2942 // Set the size that is at least reserved in caller of this function. Tail
2943 // call optimized functions' reserved stack space needs to be aligned so that
2944 // taking the difference between two stack areas will result in an aligned
2946 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2947 FuncInfo->setMinReservedArea(MinReservedArea);
2949 // If the function takes variable number of arguments, make a frame index for
2950 // the start of the first vararg value... for expansion of llvm.va_start.
2952 int Depth = ArgOffset;
2954 FuncInfo->setVarArgsFrameIndex(
2955 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2956 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2958 // If this function is vararg, store any remaining integer argument regs
2959 // to their spots on the stack so that they may be loaded by deferencing the
2960 // result of va_next.
2961 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2962 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2963 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2964 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2965 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2966 MachinePointerInfo(), false, false, 0);
2967 MemOps.push_back(Store);
2968 // Increment the address by four for the next argument to store
2969 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2970 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2974 if (!MemOps.empty())
2975 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2981 PPCTargetLowering::LowerFormalArguments_Darwin(
2983 CallingConv::ID CallConv, bool isVarArg,
2984 const SmallVectorImpl<ISD::InputArg>
2986 SDLoc dl, SelectionDAG &DAG,
2987 SmallVectorImpl<SDValue> &InVals) const {
2988 // TODO: add description of PPC stack frame format, or at least some docs.
2990 MachineFunction &MF = DAG.getMachineFunction();
2991 MachineFrameInfo *MFI = MF.getFrameInfo();
2992 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2994 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2995 bool isPPC64 = PtrVT == MVT::i64;
2996 // Potential tail calls could cause overwriting of argument stack slots.
2997 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2998 (CallConv == CallingConv::Fast));
2999 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3001 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
3003 unsigned ArgOffset = LinkageSize;
3004 // Area that is at least reserved in caller of this function.
3005 unsigned MinReservedArea = ArgOffset;
3007 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3008 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3009 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3011 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3012 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3013 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3016 static const MCPhysReg *FPR = GetFPR();
3018 static const MCPhysReg VR[] = {
3019 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3020 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3023 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3024 const unsigned Num_FPR_Regs = 13;
3025 const unsigned Num_VR_Regs = array_lengthof( VR);
3027 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3029 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3031 // In 32-bit non-varargs functions, the stack space for vectors is after the
3032 // stack space for non-vectors. We do not use this space unless we have
3033 // too many vectors to fit in registers, something that only occurs in
3034 // constructed examples:), but we have to walk the arglist to figure
3035 // that out...for the pathological case, compute VecArgOffset as the
3036 // start of the vector parameter area. Computing VecArgOffset is the
3037 // entire point of the following loop.
3038 unsigned VecArgOffset = ArgOffset;
3039 if (!isVarArg && !isPPC64) {
3040 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3042 EVT ObjectVT = Ins[ArgNo].VT;
3043 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3045 if (Flags.isByVal()) {
3046 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3047 unsigned ObjSize = Flags.getByValSize();
3049 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3050 VecArgOffset += ArgSize;
3054 switch(ObjectVT.getSimpleVT().SimpleTy) {
3055 default: llvm_unreachable("Unhandled argument type!");
3061 case MVT::i64: // PPC64
3063 // FIXME: We are guaranteed to be !isPPC64 at this point.
3064 // Does MVT::i64 apply?
3071 // Nothing to do, we're only looking at Nonvector args here.
3076 // We've found where the vector parameter area in memory is. Skip the
3077 // first 12 parameters; these don't use that memory.
3078 VecArgOffset = ((VecArgOffset+15)/16)*16;
3079 VecArgOffset += 12*16;
3081 // Add DAG nodes to load the arguments or copy them out of registers. On
3082 // entry to a function on PPC, the arguments start after the linkage area,
3083 // although the first ones are often in registers.
3085 SmallVector<SDValue, 8> MemOps;
3086 unsigned nAltivecParamsAtEnd = 0;
3087 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3088 unsigned CurArgIdx = 0;
3089 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3091 bool needsLoad = false;
3092 EVT ObjectVT = Ins[ArgNo].VT;
3093 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3094 unsigned ArgSize = ObjSize;
3095 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3096 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3097 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3099 unsigned CurArgOffset = ArgOffset;
3101 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3102 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3103 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3104 if (isVarArg || isPPC64) {
3105 MinReservedArea = ((MinReservedArea+15)/16)*16;
3106 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3109 } else nAltivecParamsAtEnd++;
3111 // Calculate min reserved area.
3112 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3116 // FIXME the codegen can be much improved in some cases.
3117 // We do not have to keep everything in memory.
3118 if (Flags.isByVal()) {
3119 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3120 ObjSize = Flags.getByValSize();
3121 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3122 // Objects of size 1 and 2 are right justified, everything else is
3123 // left justified. This means the memory address is adjusted forwards.
3124 if (ObjSize==1 || ObjSize==2) {
3125 CurArgOffset = CurArgOffset + (4 - ObjSize);
3127 // The value of the object is its address.
3128 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3129 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3130 InVals.push_back(FIN);
3131 if (ObjSize==1 || ObjSize==2) {
3132 if (GPR_idx != Num_GPR_Regs) {
3135 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3137 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3138 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3139 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3140 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3141 MachinePointerInfo(FuncArg),
3142 ObjType, false, false, 0);
3143 MemOps.push_back(Store);
3147 ArgOffset += PtrByteSize;
3151 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3152 // Store whatever pieces of the object are in registers
3153 // to memory. ArgOffset will be the address of the beginning
3155 if (GPR_idx != Num_GPR_Regs) {
3158 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3160 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3161 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3162 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3163 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3164 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3165 MachinePointerInfo(FuncArg, j),
3167 MemOps.push_back(Store);
3169 ArgOffset += PtrByteSize;
3171 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3178 switch (ObjectVT.getSimpleVT().SimpleTy) {
3179 default: llvm_unreachable("Unhandled argument type!");
3183 if (GPR_idx != Num_GPR_Regs) {
3184 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3185 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3187 if (ObjectVT == MVT::i1)
3188 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3193 ArgSize = PtrByteSize;
3195 // All int arguments reserve stack space in the Darwin ABI.
3196 ArgOffset += PtrByteSize;
3200 case MVT::i64: // PPC64
3201 if (GPR_idx != Num_GPR_Regs) {
3202 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3203 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3205 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3206 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3207 // value to MVT::i64 and then truncate to the correct register size.
3208 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3213 ArgSize = PtrByteSize;
3215 // All int arguments reserve stack space in the Darwin ABI.
3221 // Every 4 bytes of argument space consumes one of the GPRs available for
3222 // argument passing.
3223 if (GPR_idx != Num_GPR_Regs) {
3225 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3228 if (FPR_idx != Num_FPR_Regs) {
3231 if (ObjectVT == MVT::f32)
3232 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3234 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3236 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3242 // All FP arguments reserve stack space in the Darwin ABI.
3243 ArgOffset += isPPC64 ? 8 : ObjSize;
3249 // Note that vector arguments in registers don't reserve stack space,
3250 // except in varargs functions.
3251 if (VR_idx != Num_VR_Regs) {
3252 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3253 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3255 while ((ArgOffset % 16) != 0) {
3256 ArgOffset += PtrByteSize;
3257 if (GPR_idx != Num_GPR_Regs)
3261 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3265 if (!isVarArg && !isPPC64) {
3266 // Vectors go after all the nonvectors.
3267 CurArgOffset = VecArgOffset;
3270 // Vectors are aligned.
3271 ArgOffset = ((ArgOffset+15)/16)*16;
3272 CurArgOffset = ArgOffset;
3280 // We need to load the argument to a virtual register if we determined above
3281 // that we ran out of physical registers of the appropriate type.
3283 int FI = MFI->CreateFixedObject(ObjSize,
3284 CurArgOffset + (ArgSize - ObjSize),
3286 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3287 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3288 false, false, false, 0);
3291 InVals.push_back(ArgVal);
3294 // Allow for Altivec parameters at the end, if needed.
3295 if (nAltivecParamsAtEnd) {
3296 MinReservedArea = ((MinReservedArea+15)/16)*16;
3297 MinReservedArea += 16*nAltivecParamsAtEnd;
3300 // Area that is at least reserved in the caller of this function.
3301 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3303 // Set the size that is at least reserved in caller of this function. Tail
3304 // call optimized functions' reserved stack space needs to be aligned so that
3305 // taking the difference between two stack areas will result in an aligned
3307 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3308 FuncInfo->setMinReservedArea(MinReservedArea);
3310 // If the function takes variable number of arguments, make a frame index for
3311 // the start of the first vararg value... for expansion of llvm.va_start.
3313 int Depth = ArgOffset;
3315 FuncInfo->setVarArgsFrameIndex(
3316 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3318 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3320 // If this function is vararg, store any remaining integer argument regs
3321 // to their spots on the stack so that they may be loaded by deferencing the
3322 // result of va_next.
3323 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3327 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3329 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3331 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3332 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3333 MachinePointerInfo(), false, false, 0);
3334 MemOps.push_back(Store);
3335 // Increment the address by four for the next argument to store
3336 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3337 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3341 if (!MemOps.empty())
3342 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3347 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3348 /// adjusted to accommodate the arguments for the tailcall.
3349 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3350 unsigned ParamSize) {
3352 if (!isTailCall) return 0;
3354 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3355 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3356 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3357 // Remember only if the new adjustement is bigger.
3358 if (SPDiff < FI->getTailCallSPDelta())
3359 FI->setTailCallSPDelta(SPDiff);
3364 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3365 /// for tail call optimization. Targets which want to do tail call
3366 /// optimization should implement this function.
3368 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3369 CallingConv::ID CalleeCC,
3371 const SmallVectorImpl<ISD::InputArg> &Ins,
3372 SelectionDAG& DAG) const {
3373 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3376 // Variable argument functions are not supported.
3380 MachineFunction &MF = DAG.getMachineFunction();
3381 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3382 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3383 // Functions containing by val parameters are not supported.
3384 for (unsigned i = 0; i != Ins.size(); i++) {
3385 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3386 if (Flags.isByVal()) return false;
3389 // Non-PIC/GOT tail calls are supported.
3390 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3393 // At the moment we can only do local tail calls (in same module, hidden
3394 // or protected) if we are generating PIC.
3395 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3396 return G->getGlobal()->hasHiddenVisibility()
3397 || G->getGlobal()->hasProtectedVisibility();
3403 /// isCallCompatibleAddress - Return the immediate to use if the specified
3404 /// 32-bit value is representable in the immediate field of a BxA instruction.
3405 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3406 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3407 if (!C) return nullptr;
3409 int Addr = C->getZExtValue();
3410 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3411 SignExtend32<26>(Addr) != Addr)
3412 return nullptr; // Top 6 bits have to be sext of immediate.
3414 return DAG.getConstant((int)C->getZExtValue() >> 2,
3415 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3420 struct TailCallArgumentInfo {
3425 TailCallArgumentInfo() : FrameIdx(0) {}
3430 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3432 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3434 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3435 SmallVectorImpl<SDValue> &MemOpChains,
3437 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3438 SDValue Arg = TailCallArgs[i].Arg;
3439 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3440 int FI = TailCallArgs[i].FrameIdx;
3441 // Store relative to framepointer.
3442 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3443 MachinePointerInfo::getFixedStack(FI),
3448 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3449 /// the appropriate stack slot for the tail call optimized function call.
3450 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3451 MachineFunction &MF,
3460 // Calculate the new stack slot for the return address.
3461 int SlotSize = isPPC64 ? 8 : 4;
3462 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3464 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3465 NewRetAddrLoc, true);
3466 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3467 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3468 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3469 MachinePointerInfo::getFixedStack(NewRetAddr),
3472 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3473 // slot as the FP is never overwritten.
3476 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3477 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3479 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3480 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3481 MachinePointerInfo::getFixedStack(NewFPIdx),
3488 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3489 /// the position of the argument.
3491 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3492 SDValue Arg, int SPDiff, unsigned ArgOffset,
3493 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3494 int Offset = ArgOffset + SPDiff;
3495 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3496 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3497 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3498 SDValue FIN = DAG.getFrameIndex(FI, VT);
3499 TailCallArgumentInfo Info;
3501 Info.FrameIdxOp = FIN;
3503 TailCallArguments.push_back(Info);
3506 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3507 /// stack slot. Returns the chain as result and the loaded frame pointers in
3508 /// LROpOut/FPOpout. Used when tail calling.
3509 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3517 // Load the LR and FP stack slot for later adjusting.
3518 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3519 LROpOut = getReturnAddrFrameIndex(DAG);
3520 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3521 false, false, false, 0);
3522 Chain = SDValue(LROpOut.getNode(), 1);
3524 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3525 // slot as the FP is never overwritten.
3527 FPOpOut = getFramePointerFrameIndex(DAG);
3528 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3529 false, false, false, 0);
3530 Chain = SDValue(FPOpOut.getNode(), 1);
3536 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3537 /// by "Src" to address "Dst" of size "Size". Alignment information is
3538 /// specified by the specific parameter attribute. The copy will be passed as
3539 /// a byval function parameter.
3540 /// Sometimes what we are copying is the end of a larger object, the part that
3541 /// does not fit in registers.
3543 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3544 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3546 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3547 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3548 false, false, MachinePointerInfo(),
3549 MachinePointerInfo());
3552 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3555 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3556 SDValue Arg, SDValue PtrOff, int SPDiff,
3557 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3558 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3559 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3561 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3566 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3568 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3569 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3570 DAG.getConstant(ArgOffset, PtrVT));
3572 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3573 MachinePointerInfo(), false, false, 0));
3574 // Calculate and remember argument location.
3575 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3580 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3581 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3582 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3583 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3584 MachineFunction &MF = DAG.getMachineFunction();
3586 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3587 // might overwrite each other in case of tail call optimization.
3588 SmallVector<SDValue, 8> MemOpChains2;
3589 // Do not flag preceding copytoreg stuff together with the following stuff.
3591 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3593 if (!MemOpChains2.empty())
3594 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3596 // Store the return address to the appropriate stack slot.
3597 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3598 isPPC64, isDarwinABI, dl);
3600 // Emit callseq_end just before tailcall node.
3601 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3602 DAG.getIntPtrConstant(0, true), InFlag, dl);
3603 InFlag = Chain.getValue(1);
3606 // Is this global address that of a function that can be called by name? (as
3607 // opposed to something that must hold a descriptor for an indirect call).
3608 static bool isFunctionGlobalAddress(SDValue Callee) {
3609 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3610 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
3611 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
3614 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
3621 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3622 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
3623 bool isTailCall, bool IsPatchPoint,
3624 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3625 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3626 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
3628 bool isPPC64 = Subtarget.isPPC64();
3629 bool isSVR4ABI = Subtarget.isSVR4ABI();
3630 bool isELFv2ABI = Subtarget.isELFv2ABI();
3632 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3633 NodeTys.push_back(MVT::Other); // Returns a chain
3634 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3636 unsigned CallOpc = PPCISD::CALL;
3638 bool needIndirectCall = true;
3639 if (!isSVR4ABI || !isPPC64)
3640 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3641 // If this is an absolute destination address, use the munged value.
3642 Callee = SDValue(Dest, 0);
3643 needIndirectCall = false;
3646 if (isFunctionGlobalAddress(Callee)) {
3647 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
3648 // A call to a TLS address is actually an indirect call to a
3649 // thread-specific pointer.
3650 unsigned OpFlags = 0;
3651 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3652 (Subtarget.getTargetTriple().isMacOSX() &&
3653 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3654 (G->getGlobal()->isDeclaration() ||
3655 G->getGlobal()->isWeakForLinker())) ||
3656 (Subtarget.isTargetELF() && !isPPC64 &&
3657 !G->getGlobal()->hasLocalLinkage() &&
3658 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3659 // PC-relative references to external symbols should go through $stub,
3660 // unless we're building with the leopard linker or later, which
3661 // automatically synthesizes these stubs.
3662 OpFlags = PPCII::MO_PLT_OR_STUB;
3665 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3666 // every direct call is) turn it into a TargetGlobalAddress /
3667 // TargetExternalSymbol node so that legalize doesn't hack it.
3668 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3669 Callee.getValueType(), 0, OpFlags);
3670 needIndirectCall = false;
3673 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3674 unsigned char OpFlags = 0;
3676 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3677 (Subtarget.getTargetTriple().isMacOSX() &&
3678 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3679 (Subtarget.isTargetELF() && !isPPC64 &&
3680 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3681 // PC-relative references to external symbols should go through $stub,
3682 // unless we're building with the leopard linker or later, which
3683 // automatically synthesizes these stubs.
3684 OpFlags = PPCII::MO_PLT_OR_STUB;
3687 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3689 needIndirectCall = false;
3693 // We'll form an invalid direct call when lowering a patchpoint; the full
3694 // sequence for an indirect call is complicated, and many of the
3695 // instructions introduced might have side effects (and, thus, can't be
3696 // removed later). The call itself will be removed as soon as the
3697 // argument/return lowering is complete, so the fact that it has the wrong
3698 // kind of operands should not really matter.
3699 needIndirectCall = false;
3702 if (needIndirectCall) {
3703 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3704 // to do the call, we can't use PPCISD::CALL.
3705 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3707 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3708 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3709 // entry point, but to the function descriptor (the function entry point
3710 // address is part of the function descriptor though).
3711 // The function descriptor is a three doubleword structure with the
3712 // following fields: function entry point, TOC base address and
3713 // environment pointer.
3714 // Thus for a call through a function pointer, the following actions need
3716 // 1. Save the TOC of the caller in the TOC save area of its stack
3717 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3718 // 2. Load the address of the function entry point from the function
3720 // 3. Load the TOC of the callee from the function descriptor into r2.
3721 // 4. Load the environment pointer from the function descriptor into
3723 // 5. Branch to the function entry point address.
3724 // 6. On return of the callee, the TOC of the caller needs to be
3725 // restored (this is done in FinishCall()).
3727 // The loads are scheduled at the beginning of the call sequence, and the
3728 // register copies are flagged together to ensure that no other
3729 // operations can be scheduled in between. E.g. without flagging the
3730 // copies together, a TOC access in the caller could be scheduled between
3731 // the assignment of the callee TOC and the branch to the callee, which
3732 // results in the TOC access going through the TOC of the callee instead
3733 // of going through the TOC of the caller, which leads to incorrect code.
3735 // Load the address of the function entry point from the function
3737 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
3738 if (LDChain.getValueType() == MVT::Glue)
3739 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
3741 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
3743 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
3744 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
3745 false, false, LoadsInv, 8);
3747 // Load environment pointer into r11.
3748 SDValue PtrOff = DAG.getIntPtrConstant(16);
3749 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3750 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
3751 MPI.getWithOffset(16), false, false,
3754 SDValue TOCOff = DAG.getIntPtrConstant(8);
3755 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3756 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
3757 MPI.getWithOffset(8), false, false,
3760 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
3762 Chain = TOCVal.getValue(0);
3763 InFlag = TOCVal.getValue(1);
3765 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3768 Chain = EnvVal.getValue(0);
3769 InFlag = EnvVal.getValue(1);
3771 MTCTROps[0] = Chain;
3772 MTCTROps[1] = LoadFuncPtr;
3773 MTCTROps[2] = InFlag;
3776 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3777 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3778 InFlag = Chain.getValue(1);
3781 NodeTys.push_back(MVT::Other);
3782 NodeTys.push_back(MVT::Glue);
3783 Ops.push_back(Chain);
3784 CallOpc = PPCISD::BCTRL;
3785 Callee.setNode(nullptr);
3786 // Add use of X11 (holding environment pointer)
3787 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3788 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3789 // Add CTR register as callee so a bctr can be emitted later.
3791 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3794 // If this is a direct call, pass the chain and the callee.
3795 if (Callee.getNode()) {
3796 Ops.push_back(Chain);
3797 Ops.push_back(Callee);
3799 // If this is a call to __tls_get_addr, find the symbol whose address
3800 // is to be taken and add it to the list. This will be used to
3801 // generate __tls_get_addr(<sym>@tlsgd) or __tls_get_addr(<sym>@tlsld).
3802 // We find the symbol by walking the chain to the CopyFromReg, walking
3803 // back from the CopyFromReg to the ADDI_TLSGD_L or ADDI_TLSLD_L, and
3804 // pulling the symbol from that node.
3805 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
3806 if (!strcmp(S->getSymbol(), "__tls_get_addr")) {
3807 assert(!needIndirectCall && "Indirect call to __tls_get_addr???");
3808 SDNode *AddI = Chain.getNode()->getOperand(2).getNode();
3809 SDValue TGTAddr = AddI->getOperand(1);
3810 assert(TGTAddr.getNode()->getOpcode() == ISD::TargetGlobalTLSAddress &&
3811 "Didn't find target global TLS address where we expected one");
3812 Ops.push_back(TGTAddr);
3813 CallOpc = PPCISD::CALL_TLS;
3816 // If this is a tail call add stack pointer delta.
3818 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3820 // Add argument registers to the end of the list so that they are known live
3822 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3823 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3824 RegsToPass[i].second.getValueType()));
3826 // Direct calls in the ELFv2 ABI need the TOC register live into the call.
3827 if (Callee.getNode() && isELFv2ABI && !IsPatchPoint)
3828 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3834 bool isLocalCall(const SDValue &Callee)
3836 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3837 return !G->getGlobal()->isDeclaration() &&
3838 !G->getGlobal()->isWeakForLinker();
3843 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3844 CallingConv::ID CallConv, bool isVarArg,
3845 const SmallVectorImpl<ISD::InputArg> &Ins,
3846 SDLoc dl, SelectionDAG &DAG,
3847 SmallVectorImpl<SDValue> &InVals) const {
3849 SmallVector<CCValAssign, 16> RVLocs;
3850 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3852 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3854 // Copy all of the result registers out of their specified physreg.
3855 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3856 CCValAssign &VA = RVLocs[i];
3857 assert(VA.isRegLoc() && "Can only return in registers!");
3859 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3860 VA.getLocReg(), VA.getLocVT(), InFlag);
3861 Chain = Val.getValue(1);
3862 InFlag = Val.getValue(2);
3864 switch (VA.getLocInfo()) {
3865 default: llvm_unreachable("Unknown loc info!");
3866 case CCValAssign::Full: break;
3867 case CCValAssign::AExt:
3868 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3870 case CCValAssign::ZExt:
3871 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3872 DAG.getValueType(VA.getValVT()));
3873 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3875 case CCValAssign::SExt:
3876 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3877 DAG.getValueType(VA.getValVT()));
3878 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3882 InVals.push_back(Val);
3889 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3890 bool isTailCall, bool isVarArg, bool IsPatchPoint,
3892 SmallVector<std::pair<unsigned, SDValue>, 8>
3894 SDValue InFlag, SDValue Chain,
3895 SDValue CallSeqStart, SDValue &Callee,
3896 int SPDiff, unsigned NumBytes,
3897 const SmallVectorImpl<ISD::InputArg> &Ins,
3898 SmallVectorImpl<SDValue> &InVals,
3899 ImmutableCallSite *CS) const {
3901 bool isELFv2ABI = Subtarget.isELFv2ABI();
3902 std::vector<EVT> NodeTys;
3903 SmallVector<SDValue, 8> Ops;
3904 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
3905 SPDiff, isTailCall, IsPatchPoint, RegsToPass,
3906 Ops, NodeTys, CS, Subtarget);
3908 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3909 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3910 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3912 // When performing tail call optimization the callee pops its arguments off
3913 // the stack. Account for this here so these bytes can be pushed back on in
3914 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3915 int BytesCalleePops =
3916 (CallConv == CallingConv::Fast &&
3917 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3919 // Add a register mask operand representing the call-preserved registers.
3920 const TargetRegisterInfo *TRI =
3921 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3922 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3923 assert(Mask && "Missing call preserved mask for calling convention");
3924 Ops.push_back(DAG.getRegisterMask(Mask));
3926 if (InFlag.getNode())
3927 Ops.push_back(InFlag);
3931 assert(((Callee.getOpcode() == ISD::Register &&
3932 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3933 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3934 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3935 isa<ConstantSDNode>(Callee)) &&
3936 "Expecting an global address, external symbol, absolute value or register");
3938 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3941 // Add a NOP immediately after the branch instruction when using the 64-bit
3942 // SVR4 ABI. At link time, if caller and callee are in a different module and
3943 // thus have a different TOC, the call will be replaced with a call to a stub
3944 // function which saves the current TOC, loads the TOC of the callee and
3945 // branches to the callee. The NOP will be replaced with a load instruction
3946 // which restores the TOC of the caller from the TOC save slot of the current
3947 // stack frame. If caller and callee belong to the same module (and have the
3948 // same TOC), the NOP will remain unchanged.
3950 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
3952 if (CallOpc == PPCISD::BCTRL) {
3953 // This is a call through a function pointer.
3954 // Restore the caller TOC from the save area into R2.
3955 // See PrepareCall() for more information about calls through function
3956 // pointers in the 64-bit SVR4 ABI.
3957 // We are using a target-specific load with r2 hard coded, because the
3958 // result of a target-independent load would never go directly into r2,
3959 // since r2 is a reserved register (which prevents the register allocator
3960 // from allocating it), resulting in an additional register being
3961 // allocated and an unnecessary move instruction being generated.
3962 CallOpc = PPCISD::BCTRL_LOAD_TOC;
3964 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3965 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3966 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3967 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3968 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3970 // The address needs to go after the chain input but before the flag (or
3971 // any other variadic arguments).
3972 Ops.insert(std::next(Ops.begin()), AddTOC);
3973 } else if ((CallOpc == PPCISD::CALL) &&
3974 (!isLocalCall(Callee) ||
3975 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3976 // Otherwise insert NOP for non-local calls.
3977 CallOpc = PPCISD::CALL_NOP;
3978 } else if (CallOpc == PPCISD::CALL_TLS)
3979 // For 64-bit SVR4, TLS calls are always non-local.
3980 CallOpc = PPCISD::CALL_NOP_TLS;
3983 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3984 InFlag = Chain.getValue(1);
3986 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3987 DAG.getIntPtrConstant(BytesCalleePops, true),
3990 InFlag = Chain.getValue(1);
3992 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3993 Ins, dl, DAG, InVals);
3997 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3998 SmallVectorImpl<SDValue> &InVals) const {
3999 SelectionDAG &DAG = CLI.DAG;
4001 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
4002 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4003 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4004 SDValue Chain = CLI.Chain;
4005 SDValue Callee = CLI.Callee;
4006 bool &isTailCall = CLI.IsTailCall;
4007 CallingConv::ID CallConv = CLI.CallConv;
4008 bool isVarArg = CLI.IsVarArg;
4009 bool IsPatchPoint = CLI.IsPatchPoint;
4010 ImmutableCallSite *CS = CLI.CS;
4013 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
4016 if (!isTailCall && CS && CS->isMustTailCall())
4017 report_fatal_error("failed to perform tail call elimination on a call "
4018 "site marked musttail");
4020 if (Subtarget.isSVR4ABI()) {
4021 if (Subtarget.isPPC64())
4022 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4023 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4024 dl, DAG, InVals, CS);
4026 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4027 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4028 dl, DAG, InVals, CS);
4031 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4032 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4033 dl, DAG, InVals, CS);
4037 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4038 CallingConv::ID CallConv, bool isVarArg,
4039 bool isTailCall, bool IsPatchPoint,
4040 const SmallVectorImpl<ISD::OutputArg> &Outs,
4041 const SmallVectorImpl<SDValue> &OutVals,
4042 const SmallVectorImpl<ISD::InputArg> &Ins,
4043 SDLoc dl, SelectionDAG &DAG,
4044 SmallVectorImpl<SDValue> &InVals,
4045 ImmutableCallSite *CS) const {
4046 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4047 // of the 32-bit SVR4 ABI stack frame layout.
4049 assert((CallConv == CallingConv::C ||
4050 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4052 unsigned PtrByteSize = 4;
4054 MachineFunction &MF = DAG.getMachineFunction();
4056 // Mark this function as potentially containing a function that contains a
4057 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4058 // and restoring the callers stack pointer in this functions epilog. This is
4059 // done because by tail calling the called function might overwrite the value
4060 // in this function's (MF) stack pointer stack slot 0(SP).
4061 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4062 CallConv == CallingConv::Fast)
4063 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4065 // Count how many bytes are to be pushed on the stack, including the linkage
4066 // area, parameter list area and the part of the local variable space which
4067 // contains copies of aggregates which are passed by value.
4069 // Assign locations to all of the outgoing arguments.
4070 SmallVector<CCValAssign, 16> ArgLocs;
4071 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4074 // Reserve space for the linkage area on the stack.
4075 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
4079 // Handle fixed and variable vector arguments differently.
4080 // Fixed vector arguments go into registers as long as registers are
4081 // available. Variable vector arguments always go into memory.
4082 unsigned NumArgs = Outs.size();
4084 for (unsigned i = 0; i != NumArgs; ++i) {
4085 MVT ArgVT = Outs[i].VT;
4086 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4089 if (Outs[i].IsFixed) {
4090 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4093 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4099 errs() << "Call operand #" << i << " has unhandled type "
4100 << EVT(ArgVT).getEVTString() << "\n";
4102 llvm_unreachable(nullptr);
4106 // All arguments are treated the same.
4107 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4110 // Assign locations to all of the outgoing aggregate by value arguments.
4111 SmallVector<CCValAssign, 16> ByValArgLocs;
4112 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4113 ByValArgLocs, *DAG.getContext());
4115 // Reserve stack space for the allocations in CCInfo.
4116 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4118 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4120 // Size of the linkage area, parameter list area and the part of the local
4121 // space variable where copies of aggregates which are passed by value are
4123 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4125 // Calculate by how many bytes the stack has to be adjusted in case of tail
4126 // call optimization.
4127 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4129 // Adjust the stack pointer for the new arguments...
4130 // These operations are automatically eliminated by the prolog/epilog pass
4131 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4133 SDValue CallSeqStart = Chain;
4135 // Load the return address and frame pointer so it can be moved somewhere else
4138 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4141 // Set up a copy of the stack pointer for use loading and storing any
4142 // arguments that may not fit in the registers available for argument
4144 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4146 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4147 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4148 SmallVector<SDValue, 8> MemOpChains;
4150 bool seenFloatArg = false;
4151 // Walk the register/memloc assignments, inserting copies/loads.
4152 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4155 CCValAssign &VA = ArgLocs[i];
4156 SDValue Arg = OutVals[i];
4157 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4159 if (Flags.isByVal()) {
4160 // Argument is an aggregate which is passed by value, thus we need to
4161 // create a copy of it in the local variable space of the current stack
4162 // frame (which is the stack frame of the caller) and pass the address of
4163 // this copy to the callee.
4164 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4165 CCValAssign &ByValVA = ByValArgLocs[j++];
4166 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4168 // Memory reserved in the local variable space of the callers stack frame.
4169 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4171 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4172 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4174 // Create a copy of the argument in the local area of the current
4176 SDValue MemcpyCall =
4177 CreateCopyOfByValArgument(Arg, PtrOff,
4178 CallSeqStart.getNode()->getOperand(0),
4181 // This must go outside the CALLSEQ_START..END.
4182 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4183 CallSeqStart.getNode()->getOperand(1),
4185 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4186 NewCallSeqStart.getNode());
4187 Chain = CallSeqStart = NewCallSeqStart;
4189 // Pass the address of the aggregate copy on the stack either in a
4190 // physical register or in the parameter list area of the current stack
4191 // frame to the callee.
4195 if (VA.isRegLoc()) {
4196 if (Arg.getValueType() == MVT::i1)
4197 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4199 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4200 // Put argument in a physical register.
4201 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4203 // Put argument in the parameter list area of the current stack frame.
4204 assert(VA.isMemLoc());
4205 unsigned LocMemOffset = VA.getLocMemOffset();
4208 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4209 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4211 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4212 MachinePointerInfo(),
4215 // Calculate and remember argument location.
4216 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4222 if (!MemOpChains.empty())
4223 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4225 // Build a sequence of copy-to-reg nodes chained together with token chain
4226 // and flag operands which copy the outgoing args into the appropriate regs.
4228 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4229 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4230 RegsToPass[i].second, InFlag);
4231 InFlag = Chain.getValue(1);
4234 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4237 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4238 SDValue Ops[] = { Chain, InFlag };
4240 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4241 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4243 InFlag = Chain.getValue(1);
4247 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4248 false, TailCallArguments);
4250 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
4251 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4252 NumBytes, Ins, InVals, CS);
4255 // Copy an argument into memory, being careful to do this outside the
4256 // call sequence for the call to which the argument belongs.
4258 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4259 SDValue CallSeqStart,
4260 ISD::ArgFlagsTy Flags,
4263 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4264 CallSeqStart.getNode()->getOperand(0),
4266 // The MEMCPY must go outside the CALLSEQ_START..END.
4267 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4268 CallSeqStart.getNode()->getOperand(1),
4270 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4271 NewCallSeqStart.getNode());
4272 return NewCallSeqStart;
4276 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4277 CallingConv::ID CallConv, bool isVarArg,
4278 bool isTailCall, bool IsPatchPoint,
4279 const SmallVectorImpl<ISD::OutputArg> &Outs,
4280 const SmallVectorImpl<SDValue> &OutVals,
4281 const SmallVectorImpl<ISD::InputArg> &Ins,
4282 SDLoc dl, SelectionDAG &DAG,
4283 SmallVectorImpl<SDValue> &InVals,
4284 ImmutableCallSite *CS) const {
4286 bool isELFv2ABI = Subtarget.isELFv2ABI();
4287 bool isLittleEndian = Subtarget.isLittleEndian();
4288 unsigned NumOps = Outs.size();
4290 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4291 unsigned PtrByteSize = 8;
4293 MachineFunction &MF = DAG.getMachineFunction();
4295 // Mark this function as potentially containing a function that contains a
4296 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4297 // and restoring the callers stack pointer in this functions epilog. This is
4298 // done because by tail calling the called function might overwrite the value
4299 // in this function's (MF) stack pointer stack slot 0(SP).
4300 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4301 CallConv == CallingConv::Fast)
4302 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4304 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
4305 "fastcc not supported on varargs functions");
4307 // Count how many bytes are to be pushed on the stack, including the linkage
4308 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4309 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4310 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4311 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4313 unsigned NumBytes = LinkageSize;
4314 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4316 static const MCPhysReg GPR[] = {
4317 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4318 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4320 static const MCPhysReg *FPR = GetFPR();
4322 static const MCPhysReg VR[] = {
4323 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4324 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4326 static const MCPhysReg VSRH[] = {
4327 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4328 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4331 const unsigned NumGPRs = array_lengthof(GPR);
4332 const unsigned NumFPRs = 13;
4333 const unsigned NumVRs = array_lengthof(VR);
4335 // When using the fast calling convention, we don't provide backing for
4336 // arguments that will be in registers.
4337 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
4339 // Add up all the space actually used.
4340 for (unsigned i = 0; i != NumOps; ++i) {
4341 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4342 EVT ArgVT = Outs[i].VT;
4343 EVT OrigVT = Outs[i].ArgVT;
4345 if (CallConv == CallingConv::Fast) {
4346 if (Flags.isByVal())
4347 NumGPRsUsed += (Flags.getByValSize()+7)/8;
4349 switch (ArgVT.getSimpleVT().SimpleTy) {
4350 default: llvm_unreachable("Unexpected ValueType for argument!");
4354 if (++NumGPRsUsed <= NumGPRs)
4359 if (++NumFPRsUsed <= NumFPRs)
4368 if (++NumVRsUsed <= NumVRs)
4374 /* Respect alignment of argument on the stack. */
4376 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4377 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4379 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4380 if (Flags.isInConsecutiveRegsLast())
4381 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4384 unsigned NumBytesActuallyUsed = NumBytes;
4386 // The prolog code of the callee may store up to 8 GPR argument registers to
4387 // the stack, allowing va_start to index over them in memory if its varargs.
4388 // Because we cannot tell if this is needed on the caller side, we have to
4389 // conservatively assume that it is needed. As such, make sure we have at
4390 // least enough stack space for the caller to store the 8 GPRs.
4391 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4392 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4394 // Tail call needs the stack to be aligned.
4395 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4396 CallConv == CallingConv::Fast)
4397 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4399 // Calculate by how many bytes the stack has to be adjusted in case of tail
4400 // call optimization.
4401 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4403 // To protect arguments on the stack from being clobbered in a tail call,
4404 // force all the loads to happen before doing any other lowering.
4406 Chain = DAG.getStackArgumentTokenFactor(Chain);
4408 // Adjust the stack pointer for the new arguments...
4409 // These operations are automatically eliminated by the prolog/epilog pass
4410 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4412 SDValue CallSeqStart = Chain;
4414 // Load the return address and frame pointer so it can be move somewhere else
4417 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4420 // Set up a copy of the stack pointer for use loading and storing any
4421 // arguments that may not fit in the registers available for argument
4423 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4425 // Figure out which arguments are going to go in registers, and which in
4426 // memory. Also, if this is a vararg function, floating point operations
4427 // must be stored to our stack, and loaded into integer regs as well, if
4428 // any integer regs are available for argument passing.
4429 unsigned ArgOffset = LinkageSize;
4431 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4432 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4434 SmallVector<SDValue, 8> MemOpChains;
4435 for (unsigned i = 0; i != NumOps; ++i) {
4436 SDValue Arg = OutVals[i];
4437 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4438 EVT ArgVT = Outs[i].VT;
4439 EVT OrigVT = Outs[i].ArgVT;
4441 // PtrOff will be used to store the current argument to the stack if a
4442 // register cannot be found for it.
4445 // We re-align the argument offset for each argument, except when using the
4446 // fast calling convention, when we need to make sure we do that only when
4447 // we'll actually use a stack slot.
4448 auto ComputePtrOff = [&]() {
4449 /* Respect alignment of argument on the stack. */
4451 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4452 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4454 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4456 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4459 if (CallConv != CallingConv::Fast) {
4462 /* Compute GPR index associated with argument offset. */
4463 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4464 GPR_idx = std::min(GPR_idx, NumGPRs);
4467 // Promote integers to 64-bit values.
4468 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4469 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4470 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4471 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4474 // FIXME memcpy is used way more than necessary. Correctness first.
4475 // Note: "by value" is code for passing a structure by value, not
4477 if (Flags.isByVal()) {
4478 // Note: Size includes alignment padding, so
4479 // struct x { short a; char b; }
4480 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4481 // These are the proper values we need for right-justifying the
4482 // aggregate in a parameter register.
4483 unsigned Size = Flags.getByValSize();
4485 // An empty aggregate parameter takes up no storage and no
4490 if (CallConv == CallingConv::Fast)
4493 // All aggregates smaller than 8 bytes must be passed right-justified.
4494 if (Size==1 || Size==2 || Size==4) {
4495 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4496 if (GPR_idx != NumGPRs) {
4497 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4498 MachinePointerInfo(), VT,
4499 false, false, false, 0);
4500 MemOpChains.push_back(Load.getValue(1));
4501 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4503 ArgOffset += PtrByteSize;
4508 if (GPR_idx == NumGPRs && Size < 8) {
4509 SDValue AddPtr = PtrOff;
4510 if (!isLittleEndian) {
4511 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4512 PtrOff.getValueType());
4513 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4515 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4518 ArgOffset += PtrByteSize;
4521 // Copy entire object into memory. There are cases where gcc-generated
4522 // code assumes it is there, even if it could be put entirely into
4523 // registers. (This is not what the doc says.)
4525 // FIXME: The above statement is likely due to a misunderstanding of the
4526 // documents. All arguments must be copied into the parameter area BY
4527 // THE CALLEE in the event that the callee takes the address of any
4528 // formal argument. That has not yet been implemented. However, it is
4529 // reasonable to use the stack area as a staging area for the register
4532 // Skip this for small aggregates, as we will use the same slot for a
4533 // right-justified copy, below.
4535 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4539 // When a register is available, pass a small aggregate right-justified.
4540 if (Size < 8 && GPR_idx != NumGPRs) {
4541 // The easiest way to get this right-justified in a register
4542 // is to copy the structure into the rightmost portion of a
4543 // local variable slot, then load the whole slot into the
4545 // FIXME: The memcpy seems to produce pretty awful code for
4546 // small aggregates, particularly for packed ones.
4547 // FIXME: It would be preferable to use the slot in the
4548 // parameter save area instead of a new local variable.
4549 SDValue AddPtr = PtrOff;
4550 if (!isLittleEndian) {
4551 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4552 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4554 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4558 // Load the slot into the register.
4559 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4560 MachinePointerInfo(),
4561 false, false, false, 0);
4562 MemOpChains.push_back(Load.getValue(1));
4563 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4565 // Done with this argument.
4566 ArgOffset += PtrByteSize;
4570 // For aggregates larger than PtrByteSize, copy the pieces of the
4571 // object that fit into registers from the parameter save area.
4572 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4573 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4574 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4575 if (GPR_idx != NumGPRs) {
4576 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4577 MachinePointerInfo(),
4578 false, false, false, 0);
4579 MemOpChains.push_back(Load.getValue(1));
4580 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4581 ArgOffset += PtrByteSize;
4583 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4590 switch (Arg.getSimpleValueType().SimpleTy) {
4591 default: llvm_unreachable("Unexpected ValueType for argument!");
4595 // These can be scalar arguments or elements of an integer array type
4596 // passed directly. Clang may use those instead of "byval" aggregate
4597 // types to avoid forcing arguments to memory unnecessarily.
4598 if (GPR_idx != NumGPRs) {
4599 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4601 if (CallConv == CallingConv::Fast)
4604 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4605 true, isTailCall, false, MemOpChains,
4606 TailCallArguments, dl);
4607 if (CallConv == CallingConv::Fast)
4608 ArgOffset += PtrByteSize;
4610 if (CallConv != CallingConv::Fast)
4611 ArgOffset += PtrByteSize;
4615 // These can be scalar arguments or elements of a float array type
4616 // passed directly. The latter are used to implement ELFv2 homogenous
4617 // float aggregates.
4619 // Named arguments go into FPRs first, and once they overflow, the
4620 // remaining arguments go into GPRs and then the parameter save area.
4621 // Unnamed arguments for vararg functions always go to GPRs and
4622 // then the parameter save area. For now, put all arguments to vararg
4623 // routines always in both locations (FPR *and* GPR or stack slot).
4624 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4625 bool NeededLoad = false;
4627 // First load the argument into the next available FPR.
4628 if (FPR_idx != NumFPRs)
4629 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4631 // Next, load the argument into GPR or stack slot if needed.
4632 if (!NeedGPROrStack)
4634 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
4635 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
4636 // once we support fp <-> gpr moves.
4638 // In the non-vararg case, this can only ever happen in the
4639 // presence of f32 array types, since otherwise we never run
4640 // out of FPRs before running out of GPRs.
4643 // Double values are always passed in a single GPR.
4644 if (Arg.getValueType() != MVT::f32) {
4645 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4647 // Non-array float values are extended and passed in a GPR.
4648 } else if (!Flags.isInConsecutiveRegs()) {
4649 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4650 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4652 // If we have an array of floats, we collect every odd element
4653 // together with its predecessor into one GPR.
4654 } else if (ArgOffset % PtrByteSize != 0) {
4656 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4657 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4658 if (!isLittleEndian)
4660 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4662 // The final element, if even, goes into the first half of a GPR.
4663 } else if (Flags.isInConsecutiveRegsLast()) {
4664 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4665 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4666 if (!isLittleEndian)
4667 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4668 DAG.getConstant(32, MVT::i32));
4670 // Non-final even elements are skipped; they will be handled
4671 // together the with subsequent argument on the next go-around.
4675 if (ArgVal.getNode())
4676 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
4678 if (CallConv == CallingConv::Fast)
4681 // Single-precision floating-point values are mapped to the
4682 // second (rightmost) word of the stack doubleword.
4683 if (Arg.getValueType() == MVT::f32 &&
4684 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4685 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4686 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4689 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4690 true, isTailCall, false, MemOpChains,
4691 TailCallArguments, dl);
4695 // When passing an array of floats, the array occupies consecutive
4696 // space in the argument area; only round up to the next doubleword
4697 // at the end of the array. Otherwise, each float takes 8 bytes.
4698 if (CallConv != CallingConv::Fast || NeededLoad) {
4699 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4700 Flags.isInConsecutiveRegs()) ? 4 : 8;
4701 if (Flags.isInConsecutiveRegsLast())
4702 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4712 // These can be scalar arguments or elements of a vector array type
4713 // passed directly. The latter are used to implement ELFv2 homogenous
4714 // vector aggregates.
4716 // For a varargs call, named arguments go into VRs or on the stack as
4717 // usual; unnamed arguments always go to the stack or the corresponding
4718 // GPRs when within range. For now, we always put the value in both
4719 // locations (or even all three).
4721 // We could elide this store in the case where the object fits
4722 // entirely in R registers. Maybe later.
4723 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4724 MachinePointerInfo(), false, false, 0);
4725 MemOpChains.push_back(Store);
4726 if (VR_idx != NumVRs) {
4727 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4728 MachinePointerInfo(),
4729 false, false, false, 0);
4730 MemOpChains.push_back(Load.getValue(1));
4732 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4733 Arg.getSimpleValueType() == MVT::v2i64) ?
4734 VSRH[VR_idx] : VR[VR_idx];
4737 RegsToPass.push_back(std::make_pair(VReg, Load));
4740 for (unsigned i=0; i<16; i+=PtrByteSize) {
4741 if (GPR_idx == NumGPRs)
4743 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4744 DAG.getConstant(i, PtrVT));
4745 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4746 false, false, false, 0);
4747 MemOpChains.push_back(Load.getValue(1));
4748 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4753 // Non-varargs Altivec params go into VRs or on the stack.
4754 if (VR_idx != NumVRs) {
4755 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4756 Arg.getSimpleValueType() == MVT::v2i64) ?
4757 VSRH[VR_idx] : VR[VR_idx];
4760 RegsToPass.push_back(std::make_pair(VReg, Arg));
4762 if (CallConv == CallingConv::Fast)
4765 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4766 true, isTailCall, true, MemOpChains,
4767 TailCallArguments, dl);
4768 if (CallConv == CallingConv::Fast)
4772 if (CallConv != CallingConv::Fast)
4778 assert(NumBytesActuallyUsed == ArgOffset);
4779 (void)NumBytesActuallyUsed;
4781 if (!MemOpChains.empty())
4782 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4784 // Check if this is an indirect call (MTCTR/BCTRL).
4785 // See PrepareCall() for more information about calls through function
4786 // pointers in the 64-bit SVR4 ABI.
4787 if (!isTailCall && !IsPatchPoint &&
4788 !isFunctionGlobalAddress(Callee) &&
4789 !isa<ExternalSymbolSDNode>(Callee)) {
4790 // Load r2 into a virtual register and store it to the TOC save area.
4791 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4792 // TOC save area offset.
4793 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4794 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4795 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4796 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr,
4797 MachinePointerInfo::getStack(TOCSaveOffset),
4799 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4800 // This does not mean the MTCTR instruction must use R12; it's easier
4801 // to model this as an extra parameter, so do that.
4802 if (isELFv2ABI && !IsPatchPoint)
4803 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4806 // Build a sequence of copy-to-reg nodes chained together with token chain
4807 // and flag operands which copy the outgoing args into the appropriate regs.
4809 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4810 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4811 RegsToPass[i].second, InFlag);
4812 InFlag = Chain.getValue(1);
4816 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4817 FPOp, true, TailCallArguments);
4819 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
4820 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4821 NumBytes, Ins, InVals, CS);
4825 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4826 CallingConv::ID CallConv, bool isVarArg,
4827 bool isTailCall, bool IsPatchPoint,
4828 const SmallVectorImpl<ISD::OutputArg> &Outs,
4829 const SmallVectorImpl<SDValue> &OutVals,
4830 const SmallVectorImpl<ISD::InputArg> &Ins,
4831 SDLoc dl, SelectionDAG &DAG,
4832 SmallVectorImpl<SDValue> &InVals,
4833 ImmutableCallSite *CS) const {
4835 unsigned NumOps = Outs.size();
4837 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4838 bool isPPC64 = PtrVT == MVT::i64;
4839 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4841 MachineFunction &MF = DAG.getMachineFunction();
4843 // Mark this function as potentially containing a function that contains a
4844 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4845 // and restoring the callers stack pointer in this functions epilog. This is
4846 // done because by tail calling the called function might overwrite the value
4847 // in this function's (MF) stack pointer stack slot 0(SP).
4848 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4849 CallConv == CallingConv::Fast)
4850 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4852 // Count how many bytes are to be pushed on the stack, including the linkage
4853 // area, and parameter passing area. We start with 24/48 bytes, which is
4854 // prereserved space for [SP][CR][LR][3 x unused].
4855 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4857 unsigned NumBytes = LinkageSize;
4859 // Add up all the space actually used.
4860 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4861 // they all go in registers, but we must reserve stack space for them for
4862 // possible use by the caller. In varargs or 64-bit calls, parameters are
4863 // assigned stack space in order, with padding so Altivec parameters are
4865 unsigned nAltivecParamsAtEnd = 0;
4866 for (unsigned i = 0; i != NumOps; ++i) {
4867 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4868 EVT ArgVT = Outs[i].VT;
4869 // Varargs Altivec parameters are padded to a 16 byte boundary.
4870 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4871 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4872 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4873 if (!isVarArg && !isPPC64) {
4874 // Non-varargs Altivec parameters go after all the non-Altivec
4875 // parameters; handle those later so we know how much padding we need.
4876 nAltivecParamsAtEnd++;
4879 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4880 NumBytes = ((NumBytes+15)/16)*16;
4882 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4885 // Allow for Altivec parameters at the end, if needed.
4886 if (nAltivecParamsAtEnd) {
4887 NumBytes = ((NumBytes+15)/16)*16;
4888 NumBytes += 16*nAltivecParamsAtEnd;
4891 // The prolog code of the callee may store up to 8 GPR argument registers to
4892 // the stack, allowing va_start to index over them in memory if its varargs.
4893 // Because we cannot tell if this is needed on the caller side, we have to
4894 // conservatively assume that it is needed. As such, make sure we have at
4895 // least enough stack space for the caller to store the 8 GPRs.
4896 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4898 // Tail call needs the stack to be aligned.
4899 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4900 CallConv == CallingConv::Fast)
4901 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4903 // Calculate by how many bytes the stack has to be adjusted in case of tail
4904 // call optimization.
4905 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4907 // To protect arguments on the stack from being clobbered in a tail call,
4908 // force all the loads to happen before doing any other lowering.
4910 Chain = DAG.getStackArgumentTokenFactor(Chain);
4912 // Adjust the stack pointer for the new arguments...
4913 // These operations are automatically eliminated by the prolog/epilog pass
4914 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4916 SDValue CallSeqStart = Chain;
4918 // Load the return address and frame pointer so it can be move somewhere else
4921 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4924 // Set up a copy of the stack pointer for use loading and storing any
4925 // arguments that may not fit in the registers available for argument
4929 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4931 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4933 // Figure out which arguments are going to go in registers, and which in
4934 // memory. Also, if this is a vararg function, floating point operations
4935 // must be stored to our stack, and loaded into integer regs as well, if
4936 // any integer regs are available for argument passing.
4937 unsigned ArgOffset = LinkageSize;
4938 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4940 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4941 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4942 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4944 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4945 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4946 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4948 static const MCPhysReg *FPR = GetFPR();
4950 static const MCPhysReg VR[] = {
4951 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4952 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4954 const unsigned NumGPRs = array_lengthof(GPR_32);
4955 const unsigned NumFPRs = 13;
4956 const unsigned NumVRs = array_lengthof(VR);
4958 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4960 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4961 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4963 SmallVector<SDValue, 8> MemOpChains;
4964 for (unsigned i = 0; i != NumOps; ++i) {
4965 SDValue Arg = OutVals[i];
4966 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4968 // PtrOff will be used to store the current argument to the stack if a
4969 // register cannot be found for it.
4972 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4974 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4976 // On PPC64, promote integers to 64-bit values.
4977 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4978 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4979 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4980 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4983 // FIXME memcpy is used way more than necessary. Correctness first.
4984 // Note: "by value" is code for passing a structure by value, not
4986 if (Flags.isByVal()) {
4987 unsigned Size = Flags.getByValSize();
4988 // Very small objects are passed right-justified. Everything else is
4989 // passed left-justified.
4990 if (Size==1 || Size==2) {
4991 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4992 if (GPR_idx != NumGPRs) {
4993 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4994 MachinePointerInfo(), VT,
4995 false, false, false, 0);
4996 MemOpChains.push_back(Load.getValue(1));
4997 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4999 ArgOffset += PtrByteSize;
5001 SDValue Const = DAG.getConstant(PtrByteSize - Size,
5002 PtrOff.getValueType());
5003 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5004 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5007 ArgOffset += PtrByteSize;
5011 // Copy entire object into memory. There are cases where gcc-generated
5012 // code assumes it is there, even if it could be put entirely into
5013 // registers. (This is not what the doc says.)
5014 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5018 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5019 // copy the pieces of the object that fit into registers from the
5020 // parameter save area.
5021 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5022 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
5023 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5024 if (GPR_idx != NumGPRs) {
5025 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5026 MachinePointerInfo(),
5027 false, false, false, 0);
5028 MemOpChains.push_back(Load.getValue(1));
5029 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5030 ArgOffset += PtrByteSize;
5032 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5039 switch (Arg.getSimpleValueType().SimpleTy) {
5040 default: llvm_unreachable("Unexpected ValueType for argument!");
5044 if (GPR_idx != NumGPRs) {
5045 if (Arg.getValueType() == MVT::i1)
5046 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5048 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5050 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5051 isPPC64, isTailCall, false, MemOpChains,
5052 TailCallArguments, dl);
5054 ArgOffset += PtrByteSize;
5058 if (FPR_idx != NumFPRs) {
5059 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5062 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5063 MachinePointerInfo(), false, false, 0);
5064 MemOpChains.push_back(Store);
5066 // Float varargs are always shadowed in available integer registers
5067 if (GPR_idx != NumGPRs) {
5068 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5069 MachinePointerInfo(), false, false,
5071 MemOpChains.push_back(Load.getValue(1));
5072 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5074 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5075 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
5076 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5077 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5078 MachinePointerInfo(),
5079 false, false, false, 0);
5080 MemOpChains.push_back(Load.getValue(1));
5081 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5084 // If we have any FPRs remaining, we may also have GPRs remaining.
5085 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5087 if (GPR_idx != NumGPRs)
5089 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5090 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5094 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5095 isPPC64, isTailCall, false, MemOpChains,
5096 TailCallArguments, dl);
5100 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5107 // These go aligned on the stack, or in the corresponding R registers
5108 // when within range. The Darwin PPC ABI doc claims they also go in
5109 // V registers; in fact gcc does this only for arguments that are
5110 // prototyped, not for those that match the ... We do it for all
5111 // arguments, seems to work.
5112 while (ArgOffset % 16 !=0) {
5113 ArgOffset += PtrByteSize;
5114 if (GPR_idx != NumGPRs)
5117 // We could elide this store in the case where the object fits
5118 // entirely in R registers. Maybe later.
5119 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5120 DAG.getConstant(ArgOffset, PtrVT));
5121 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5122 MachinePointerInfo(), false, false, 0);
5123 MemOpChains.push_back(Store);
5124 if (VR_idx != NumVRs) {
5125 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5126 MachinePointerInfo(),
5127 false, false, false, 0);
5128 MemOpChains.push_back(Load.getValue(1));
5129 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5132 for (unsigned i=0; i<16; i+=PtrByteSize) {
5133 if (GPR_idx == NumGPRs)
5135 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5136 DAG.getConstant(i, PtrVT));
5137 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5138 false, false, false, 0);
5139 MemOpChains.push_back(Load.getValue(1));
5140 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5145 // Non-varargs Altivec params generally go in registers, but have
5146 // stack space allocated at the end.
5147 if (VR_idx != NumVRs) {
5148 // Doesn't have GPR space allocated.
5149 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5150 } else if (nAltivecParamsAtEnd==0) {
5151 // We are emitting Altivec params in order.
5152 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5153 isPPC64, isTailCall, true, MemOpChains,
5154 TailCallArguments, dl);
5160 // If all Altivec parameters fit in registers, as they usually do,
5161 // they get stack space following the non-Altivec parameters. We
5162 // don't track this here because nobody below needs it.
5163 // If there are more Altivec parameters than fit in registers emit
5165 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5167 // Offset is aligned; skip 1st 12 params which go in V registers.
5168 ArgOffset = ((ArgOffset+15)/16)*16;
5170 for (unsigned i = 0; i != NumOps; ++i) {
5171 SDValue Arg = OutVals[i];
5172 EVT ArgType = Outs[i].VT;
5173 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5174 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5177 // We are emitting Altivec params in order.
5178 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5179 isPPC64, isTailCall, true, MemOpChains,
5180 TailCallArguments, dl);
5187 if (!MemOpChains.empty())
5188 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5190 // On Darwin, R12 must contain the address of an indirect callee. This does
5191 // not mean the MTCTR instruction must use R12; it's easier to model this as
5192 // an extra parameter, so do that.
5194 !isFunctionGlobalAddress(Callee) &&
5195 !isa<ExternalSymbolSDNode>(Callee) &&
5196 !isBLACompatibleAddress(Callee, DAG))
5197 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5198 PPC::R12), Callee));
5200 // Build a sequence of copy-to-reg nodes chained together with token chain
5201 // and flag operands which copy the outgoing args into the appropriate regs.
5203 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5204 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5205 RegsToPass[i].second, InFlag);
5206 InFlag = Chain.getValue(1);
5210 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5211 FPOp, true, TailCallArguments);
5213 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, DAG,
5214 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5215 NumBytes, Ins, InVals, CS);
5219 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5220 MachineFunction &MF, bool isVarArg,
5221 const SmallVectorImpl<ISD::OutputArg> &Outs,
5222 LLVMContext &Context) const {
5223 SmallVector<CCValAssign, 16> RVLocs;
5224 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5225 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5229 PPCTargetLowering::LowerReturn(SDValue Chain,
5230 CallingConv::ID CallConv, bool isVarArg,
5231 const SmallVectorImpl<ISD::OutputArg> &Outs,
5232 const SmallVectorImpl<SDValue> &OutVals,
5233 SDLoc dl, SelectionDAG &DAG) const {
5235 SmallVector<CCValAssign, 16> RVLocs;
5236 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5238 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5241 SmallVector<SDValue, 4> RetOps(1, Chain);
5243 // Copy the result values into the output registers.
5244 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5245 CCValAssign &VA = RVLocs[i];
5246 assert(VA.isRegLoc() && "Can only return in registers!");
5248 SDValue Arg = OutVals[i];
5250 switch (VA.getLocInfo()) {
5251 default: llvm_unreachable("Unknown loc info!");
5252 case CCValAssign::Full: break;
5253 case CCValAssign::AExt:
5254 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5256 case CCValAssign::ZExt:
5257 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5259 case CCValAssign::SExt:
5260 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5264 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5265 Flag = Chain.getValue(1);
5266 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5269 RetOps[0] = Chain; // Update chain.
5271 // Add the flag if we have it.
5273 RetOps.push_back(Flag);
5275 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5278 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5279 const PPCSubtarget &Subtarget) const {
5280 // When we pop the dynamic allocation we need to restore the SP link.
5283 // Get the corect type for pointers.
5284 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5286 // Construct the stack pointer operand.
5287 bool isPPC64 = Subtarget.isPPC64();
5288 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5289 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5291 // Get the operands for the STACKRESTORE.
5292 SDValue Chain = Op.getOperand(0);
5293 SDValue SaveSP = Op.getOperand(1);
5295 // Load the old link SP.
5296 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5297 MachinePointerInfo(),
5298 false, false, false, 0);
5300 // Restore the stack pointer.
5301 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5303 // Store the old link SP.
5304 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5311 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5312 MachineFunction &MF = DAG.getMachineFunction();
5313 bool isPPC64 = Subtarget.isPPC64();
5314 bool isDarwinABI = Subtarget.isDarwinABI();
5315 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5317 // Get current frame pointer save index. The users of this index will be
5318 // primarily DYNALLOC instructions.
5319 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5320 int RASI = FI->getReturnAddrSaveIndex();
5322 // If the frame pointer save index hasn't been defined yet.
5324 // Find out what the fix offset of the frame pointer save area.
5325 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5326 // Allocate the frame index for frame pointer save area.
5327 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5329 FI->setReturnAddrSaveIndex(RASI);
5331 return DAG.getFrameIndex(RASI, PtrVT);
5335 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5336 MachineFunction &MF = DAG.getMachineFunction();
5337 bool isPPC64 = Subtarget.isPPC64();
5338 bool isDarwinABI = Subtarget.isDarwinABI();
5339 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5341 // Get current frame pointer save index. The users of this index will be
5342 // primarily DYNALLOC instructions.
5343 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5344 int FPSI = FI->getFramePointerSaveIndex();
5346 // If the frame pointer save index hasn't been defined yet.
5348 // Find out what the fix offset of the frame pointer save area.
5349 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5352 // Allocate the frame index for frame pointer save area.
5353 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5355 FI->setFramePointerSaveIndex(FPSI);
5357 return DAG.getFrameIndex(FPSI, PtrVT);
5360 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5362 const PPCSubtarget &Subtarget) const {
5364 SDValue Chain = Op.getOperand(0);
5365 SDValue Size = Op.getOperand(1);
5368 // Get the corect type for pointers.
5369 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5371 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5372 DAG.getConstant(0, PtrVT), Size);
5373 // Construct a node for the frame pointer save index.
5374 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5375 // Build a DYNALLOC node.
5376 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5377 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5378 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5381 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5382 SelectionDAG &DAG) const {
5384 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5385 DAG.getVTList(MVT::i32, MVT::Other),
5386 Op.getOperand(0), Op.getOperand(1));
5389 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5390 SelectionDAG &DAG) const {
5392 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5393 Op.getOperand(0), Op.getOperand(1));
5396 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5397 assert(Op.getValueType() == MVT::i1 &&
5398 "Custom lowering only for i1 loads");
5400 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5403 LoadSDNode *LD = cast<LoadSDNode>(Op);
5405 SDValue Chain = LD->getChain();
5406 SDValue BasePtr = LD->getBasePtr();
5407 MachineMemOperand *MMO = LD->getMemOperand();
5409 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5410 BasePtr, MVT::i8, MMO);
5411 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5413 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5414 return DAG.getMergeValues(Ops, dl);
5417 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5418 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5419 "Custom lowering only for i1 stores");
5421 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5424 StoreSDNode *ST = cast<StoreSDNode>(Op);
5426 SDValue Chain = ST->getChain();
5427 SDValue BasePtr = ST->getBasePtr();
5428 SDValue Value = ST->getValue();
5429 MachineMemOperand *MMO = ST->getMemOperand();
5431 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5432 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5435 // FIXME: Remove this once the ANDI glue bug is fixed:
5436 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5437 assert(Op.getValueType() == MVT::i1 &&
5438 "Custom lowering only for i1 results");
5441 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5445 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5447 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5448 // Not FP? Not a fsel.
5449 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5450 !Op.getOperand(2).getValueType().isFloatingPoint())
5453 // We might be able to do better than this under some circumstances, but in
5454 // general, fsel-based lowering of select is a finite-math-only optimization.
5455 // For more information, see section F.3 of the 2.06 ISA specification.
5456 if (!DAG.getTarget().Options.NoInfsFPMath ||
5457 !DAG.getTarget().Options.NoNaNsFPMath)
5460 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5462 EVT ResVT = Op.getValueType();
5463 EVT CmpVT = Op.getOperand(0).getValueType();
5464 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5465 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5468 // If the RHS of the comparison is a 0.0, we don't need to do the
5469 // subtraction at all.
5471 if (isFloatingPointZero(RHS))
5473 default: break; // SETUO etc aren't handled by fsel.
5477 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5478 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5479 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5480 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5481 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5482 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5483 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5486 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5489 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5490 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5491 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5494 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5497 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5498 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5499 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5500 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5505 default: break; // SETUO etc aren't handled by fsel.
5509 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5510 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5511 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5512 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5513 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5514 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5515 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5516 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5519 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5520 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5521 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5522 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5525 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5526 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5527 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5528 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5531 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5532 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5533 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5534 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5537 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5538 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5539 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5540 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5545 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
5548 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5549 SDValue Src = Op.getOperand(0);
5550 if (Src.getValueType() == MVT::f32)
5551 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5554 switch (Op.getSimpleValueType().SimpleTy) {
5555 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5557 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5558 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5563 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5564 "i64 FP_TO_UINT is supported only with FPCVT");
5565 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5571 // Convert the FP value to an int value through memory.
5572 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5573 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5574 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5575 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5576 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5578 // Emit a store to the stack slot.
5581 MachineFunction &MF = DAG.getMachineFunction();
5582 MachineMemOperand *MMO =
5583 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5584 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5585 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5586 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5588 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5589 MPI, false, false, 0);
5591 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5593 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5594 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5595 DAG.getConstant(4, FIPtr.getValueType()));
5596 MPI = MPI.getWithOffset(4);
5604 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5607 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5609 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5610 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5614 // We're trying to insert a regular store, S, and then a load, L. If the
5615 // incoming value, O, is a load, we might just be able to have our load use the
5616 // address used by O. However, we don't know if anything else will store to
5617 // that address before we can load from it. To prevent this situation, we need
5618 // to insert our load, L, into the chain as a peer of O. To do this, we give L
5619 // the same chain operand as O, we create a token factor from the chain results
5620 // of O and L, and we replace all uses of O's chain result with that token
5621 // factor (see spliceIntoChain below for this last part).
5622 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
5625 ISD::LoadExtType ET) const {
5627 if (ET == ISD::NON_EXTLOAD &&
5628 (Op.getOpcode() == ISD::FP_TO_UINT ||
5629 Op.getOpcode() == ISD::FP_TO_SINT) &&
5630 isOperationLegalOrCustom(Op.getOpcode(),
5631 Op.getOperand(0).getValueType())) {
5633 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5637 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
5638 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
5639 LD->isNonTemporal())
5641 if (LD->getMemoryVT() != MemVT)
5644 RLI.Ptr = LD->getBasePtr();
5645 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
5646 assert(LD->getAddressingMode() == ISD::PRE_INC &&
5647 "Non-pre-inc AM on PPC?");
5648 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
5652 RLI.Chain = LD->getChain();
5653 RLI.MPI = LD->getPointerInfo();
5654 RLI.IsInvariant = LD->isInvariant();
5655 RLI.Alignment = LD->getAlignment();
5656 RLI.AAInfo = LD->getAAInfo();
5657 RLI.Ranges = LD->getRanges();
5659 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
5663 // Given the head of the old chain, ResChain, insert a token factor containing
5664 // it and NewResChain, and make users of ResChain now be users of that token
5666 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
5667 SDValue NewResChain,
5668 SelectionDAG &DAG) const {
5672 SDLoc dl(NewResChain);
5674 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5675 NewResChain, DAG.getUNDEF(MVT::Other));
5676 assert(TF.getNode() != NewResChain.getNode() &&
5677 "A new TF really is required here");
5679 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
5680 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
5683 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5684 SelectionDAG &DAG) const {
5686 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5687 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5690 if (Op.getOperand(0).getValueType() == MVT::i1)
5691 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5692 DAG.getConstantFP(1.0, Op.getValueType()),
5693 DAG.getConstantFP(0.0, Op.getValueType()));
5695 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5696 "UINT_TO_FP is supported only with FPCVT");
5698 // If we have FCFIDS, then use it when converting to single-precision.
5699 // Otherwise, convert to double-precision and then round.
5700 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5701 (Op.getOpcode() == ISD::UINT_TO_FP ?
5702 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5703 (Op.getOpcode() == ISD::UINT_TO_FP ?
5704 PPCISD::FCFIDU : PPCISD::FCFID);
5705 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5706 MVT::f32 : MVT::f64;
5708 if (Op.getOperand(0).getValueType() == MVT::i64) {
5709 SDValue SINT = Op.getOperand(0);
5710 // When converting to single-precision, we actually need to convert
5711 // to double-precision first and then round to single-precision.
5712 // To avoid double-rounding effects during that operation, we have
5713 // to prepare the input operand. Bits that might be truncated when
5714 // converting to double-precision are replaced by a bit that won't
5715 // be lost at this stage, but is below the single-precision rounding
5718 // However, if -enable-unsafe-fp-math is in effect, accept double
5719 // rounding to avoid the extra overhead.
5720 if (Op.getValueType() == MVT::f32 &&
5721 !Subtarget.hasFPCVT() &&
5722 !DAG.getTarget().Options.UnsafeFPMath) {
5724 // Twiddle input to make sure the low 11 bits are zero. (If this
5725 // is the case, we are guaranteed the value will fit into the 53 bit
5726 // mantissa of an IEEE double-precision value without rounding.)
5727 // If any of those low 11 bits were not zero originally, make sure
5728 // bit 12 (value 2048) is set instead, so that the final rounding
5729 // to single-precision gets the correct result.
5730 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5731 SINT, DAG.getConstant(2047, MVT::i64));
5732 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5733 Round, DAG.getConstant(2047, MVT::i64));
5734 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5735 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5736 Round, DAG.getConstant(-2048, MVT::i64));
5738 // However, we cannot use that value unconditionally: if the magnitude
5739 // of the input value is small, the bit-twiddling we did above might
5740 // end up visibly changing the output. Fortunately, in that case, we
5741 // don't need to twiddle bits since the original input will convert
5742 // exactly to double-precision floating-point already. Therefore,
5743 // construct a conditional to use the original value if the top 11
5744 // bits are all sign-bit copies, and use the rounded value computed
5746 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5747 SINT, DAG.getConstant(53, MVT::i32));
5748 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5749 Cond, DAG.getConstant(1, MVT::i64));
5750 Cond = DAG.getSetCC(dl, MVT::i32,
5751 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5753 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5759 MachineFunction &MF = DAG.getMachineFunction();
5760 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
5761 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5762 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5764 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5765 } else if (Subtarget.hasLFIWAX() &&
5766 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
5767 MachineMemOperand *MMO =
5768 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5769 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5770 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5771 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
5772 DAG.getVTList(MVT::f64, MVT::Other),
5773 Ops, MVT::i32, MMO);
5774 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5775 } else if (Subtarget.hasFPCVT() &&
5776 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
5777 MachineMemOperand *MMO =
5778 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5779 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5780 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5781 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
5782 DAG.getVTList(MVT::f64, MVT::Other),
5783 Ops, MVT::i32, MMO);
5784 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5785 } else if (((Subtarget.hasLFIWAX() &&
5786 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
5787 (Subtarget.hasFPCVT() &&
5788 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
5789 SINT.getOperand(0).getValueType() == MVT::i32) {
5790 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5791 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5793 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5794 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5797 DAG.getStore(DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
5798 MachinePointerInfo::getFixedStack(FrameIdx),
5801 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5802 "Expected an i32 store");
5806 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
5809 MachineMemOperand *MMO =
5810 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5811 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5812 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5813 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
5814 PPCISD::LFIWZX : PPCISD::LFIWAX,
5815 dl, DAG.getVTList(MVT::f64, MVT::Other),
5816 Ops, MVT::i32, MMO);
5818 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5820 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5822 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5823 FP = DAG.getNode(ISD::FP_ROUND, dl,
5824 MVT::f32, FP, DAG.getIntPtrConstant(0));
5828 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5829 "Unhandled INT_TO_FP type in custom expander!");
5830 // Since we only generate this in 64-bit mode, we can take advantage of
5831 // 64-bit registers. In particular, sign extend the input value into the
5832 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5833 // then lfd it and fcfid it.
5834 MachineFunction &MF = DAG.getMachineFunction();
5835 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5836 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5839 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5842 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
5844 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5845 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5847 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5848 MachinePointerInfo::getFixedStack(FrameIdx),
5851 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5852 "Expected an i32 store");
5856 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
5860 MachineMemOperand *MMO =
5861 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5862 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5863 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5864 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5865 PPCISD::LFIWZX : PPCISD::LFIWAX,
5866 dl, DAG.getVTList(MVT::f64, MVT::Other),
5867 Ops, MVT::i32, MMO);
5869 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
5871 assert(Subtarget.isPPC64() &&
5872 "i32->FP without LFIWAX supported only on PPC64");
5874 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5875 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5877 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5880 // STD the extended value into the stack slot.
5881 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5882 MachinePointerInfo::getFixedStack(FrameIdx),
5885 // Load the value as a double.
5886 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5887 MachinePointerInfo::getFixedStack(FrameIdx),
5888 false, false, false, 0);
5891 // FCFID it and return it.
5892 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5893 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5894 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5898 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5899 SelectionDAG &DAG) const {
5902 The rounding mode is in bits 30:31 of FPSR, and has the following
5909 FLT_ROUNDS, on the other hand, expects the following:
5916 To perform the conversion, we do:
5917 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5920 MachineFunction &MF = DAG.getMachineFunction();
5921 EVT VT = Op.getValueType();
5922 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5924 // Save FP Control Word to register
5926 MVT::f64, // return register
5927 MVT::Glue // unused in this context
5929 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5931 // Save FP register to stack slot
5932 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5933 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5934 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5935 StackSlot, MachinePointerInfo(), false, false,0);
5937 // Load FP Control Word from low 32 bits of stack slot.
5938 SDValue Four = DAG.getConstant(4, PtrVT);
5939 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5940 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5941 false, false, false, 0);
5943 // Transform as necessary
5945 DAG.getNode(ISD::AND, dl, MVT::i32,
5946 CWD, DAG.getConstant(3, MVT::i32));
5948 DAG.getNode(ISD::SRL, dl, MVT::i32,
5949 DAG.getNode(ISD::AND, dl, MVT::i32,
5950 DAG.getNode(ISD::XOR, dl, MVT::i32,
5951 CWD, DAG.getConstant(3, MVT::i32)),
5952 DAG.getConstant(3, MVT::i32)),
5953 DAG.getConstant(1, MVT::i32));
5956 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5958 return DAG.getNode((VT.getSizeInBits() < 16 ?
5959 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5962 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5963 EVT VT = Op.getValueType();
5964 unsigned BitWidth = VT.getSizeInBits();
5966 assert(Op.getNumOperands() == 3 &&
5967 VT == Op.getOperand(1).getValueType() &&
5970 // Expand into a bunch of logical ops. Note that these ops
5971 // depend on the PPC behavior for oversized shift amounts.
5972 SDValue Lo = Op.getOperand(0);
5973 SDValue Hi = Op.getOperand(1);
5974 SDValue Amt = Op.getOperand(2);
5975 EVT AmtVT = Amt.getValueType();
5977 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5978 DAG.getConstant(BitWidth, AmtVT), Amt);
5979 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5980 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5981 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5982 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5983 DAG.getConstant(-BitWidth, AmtVT));
5984 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5985 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5986 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5987 SDValue OutOps[] = { OutLo, OutHi };
5988 return DAG.getMergeValues(OutOps, dl);
5991 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5992 EVT VT = Op.getValueType();
5994 unsigned BitWidth = VT.getSizeInBits();
5995 assert(Op.getNumOperands() == 3 &&
5996 VT == Op.getOperand(1).getValueType() &&
5999 // Expand into a bunch of logical ops. Note that these ops
6000 // depend on the PPC behavior for oversized shift amounts.
6001 SDValue Lo = Op.getOperand(0);
6002 SDValue Hi = Op.getOperand(1);
6003 SDValue Amt = Op.getOperand(2);
6004 EVT AmtVT = Amt.getValueType();
6006 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6007 DAG.getConstant(BitWidth, AmtVT), Amt);
6008 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6009 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6010 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6011 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6012 DAG.getConstant(-BitWidth, AmtVT));
6013 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
6014 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6015 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
6016 SDValue OutOps[] = { OutLo, OutHi };
6017 return DAG.getMergeValues(OutOps, dl);
6020 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6022 EVT VT = Op.getValueType();
6023 unsigned BitWidth = VT.getSizeInBits();
6024 assert(Op.getNumOperands() == 3 &&
6025 VT == Op.getOperand(1).getValueType() &&
6028 // Expand into a bunch of logical ops, followed by a select_cc.
6029 SDValue Lo = Op.getOperand(0);
6030 SDValue Hi = Op.getOperand(1);
6031 SDValue Amt = Op.getOperand(2);
6032 EVT AmtVT = Amt.getValueType();
6034 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6035 DAG.getConstant(BitWidth, AmtVT), Amt);
6036 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6037 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6038 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6039 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6040 DAG.getConstant(-BitWidth, AmtVT));
6041 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
6042 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
6043 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
6044 Tmp4, Tmp6, ISD::SETLE);
6045 SDValue OutOps[] = { OutLo, OutHi };
6046 return DAG.getMergeValues(OutOps, dl);
6049 //===----------------------------------------------------------------------===//
6050 // Vector related lowering.
6053 /// BuildSplatI - Build a canonical splati of Val with an element size of
6054 /// SplatSize. Cast the result to VT.
6055 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6056 SelectionDAG &DAG, SDLoc dl) {
6057 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
6059 static const EVT VTys[] = { // canonical VT to use for each size.
6060 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6063 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
6065 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
6069 EVT CanonicalVT = VTys[SplatSize-1];
6071 // Build a canonical splat for this value.
6072 SDValue Elt = DAG.getConstant(Val, MVT::i32);
6073 SmallVector<SDValue, 8> Ops;
6074 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
6075 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
6076 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
6079 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
6080 /// specified intrinsic ID.
6081 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6082 SelectionDAG &DAG, SDLoc dl,
6083 EVT DestVT = MVT::Other) {
6084 if (DestVT == MVT::Other) DestVT = Op.getValueType();
6085 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6086 DAG.getConstant(IID, MVT::i32), Op);
6089 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
6090 /// specified intrinsic ID.
6091 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6092 SelectionDAG &DAG, SDLoc dl,
6093 EVT DestVT = MVT::Other) {
6094 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
6095 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6096 DAG.getConstant(IID, MVT::i32), LHS, RHS);
6099 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
6100 /// specified intrinsic ID.
6101 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6102 SDValue Op2, SelectionDAG &DAG,
6103 SDLoc dl, EVT DestVT = MVT::Other) {
6104 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6105 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6106 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
6110 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6111 /// amount. The result has the specified value type.
6112 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6113 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6114 // Force LHS/RHS to be the right type.
6115 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6116 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6119 for (unsigned i = 0; i != 16; ++i)
6121 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6122 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6125 // If this is a case we can't handle, return null and let the default
6126 // expansion code take care of it. If we CAN select this case, and if it
6127 // selects to a single instruction, return Op. Otherwise, if we can codegen
6128 // this case more efficiently than a constant pool load, lower it to the
6129 // sequence of ops that should be used.
6130 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6131 SelectionDAG &DAG) const {
6133 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6134 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6136 // Check if this is a splat of a constant value.
6137 APInt APSplatBits, APSplatUndef;
6138 unsigned SplatBitSize;
6140 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6141 HasAnyUndefs, 0, true) || SplatBitSize > 32)
6144 unsigned SplatBits = APSplatBits.getZExtValue();
6145 unsigned SplatUndef = APSplatUndef.getZExtValue();
6146 unsigned SplatSize = SplatBitSize / 8;
6148 // First, handle single instruction cases.
6151 if (SplatBits == 0) {
6152 // Canonicalize all zero vectors to be v4i32.
6153 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6154 SDValue Z = DAG.getConstant(0, MVT::i32);
6155 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6156 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6161 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6162 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6164 if (SextVal >= -16 && SextVal <= 15)
6165 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6168 // Two instruction sequences.
6170 // If this value is in the range [-32,30] and is even, use:
6171 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6172 // If this value is in the range [17,31] and is odd, use:
6173 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6174 // If this value is in the range [-31,-17] and is odd, use:
6175 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6176 // Note the last two are three-instruction sequences.
6177 if (SextVal >= -32 && SextVal <= 31) {
6178 // To avoid having these optimizations undone by constant folding,
6179 // we convert to a pseudo that will be expanded later into one of
6181 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
6182 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6183 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6184 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
6185 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6186 if (VT == Op.getValueType())
6189 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6192 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6193 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6195 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6196 // Make -1 and vspltisw -1:
6197 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6199 // Make the VSLW intrinsic, computing 0x8000_0000.
6200 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6203 // xor by OnesV to invert it.
6204 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6205 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6208 // The remaining cases assume either big endian element order or
6209 // a splat-size that equates to the element size of the vector
6210 // to be built. An example that doesn't work for little endian is
6211 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
6212 // and a vector element size of 16 bits. The code below will
6213 // produce the vector in big endian element order, which for little
6214 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
6216 // For now, just avoid these optimizations in that case.
6217 // FIXME: Develop correct optimizations for LE with mismatched
6218 // splat and element sizes.
6220 if (Subtarget.isLittleEndian() &&
6221 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
6224 // Check to see if this is a wide variety of vsplti*, binop self cases.
6225 static const signed char SplatCsts[] = {
6226 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6227 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6230 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6231 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6232 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6233 int i = SplatCsts[idx];
6235 // Figure out what shift amount will be used by altivec if shifted by i in
6237 unsigned TypeShiftAmt = i & (SplatBitSize-1);
6239 // vsplti + shl self.
6240 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
6241 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6242 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6243 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
6244 Intrinsic::ppc_altivec_vslw
6246 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6247 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6250 // vsplti + srl self.
6251 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6252 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6253 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6254 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
6255 Intrinsic::ppc_altivec_vsrw
6257 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6258 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6261 // vsplti + sra self.
6262 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6263 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6264 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6265 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
6266 Intrinsic::ppc_altivec_vsraw
6268 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6269 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6272 // vsplti + rol self.
6273 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
6274 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
6275 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6276 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6277 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
6278 Intrinsic::ppc_altivec_vrlw
6280 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6281 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6284 // t = vsplti c, result = vsldoi t, t, 1
6285 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
6286 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6287 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
6289 // t = vsplti c, result = vsldoi t, t, 2
6290 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
6291 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6292 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
6294 // t = vsplti c, result = vsldoi t, t, 3
6295 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
6296 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6297 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
6304 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
6305 /// the specified operations to build the shuffle.
6306 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
6307 SDValue RHS, SelectionDAG &DAG,
6309 unsigned OpNum = (PFEntry >> 26) & 0x0F;
6310 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
6311 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
6314 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
6326 if (OpNum == OP_COPY) {
6327 if (LHSID == (1*9+2)*9+3) return LHS;
6328 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
6332 SDValue OpLHS, OpRHS;
6333 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
6334 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
6338 default: llvm_unreachable("Unknown i32 permute!");
6340 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
6341 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
6342 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
6343 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
6346 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
6347 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
6348 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
6349 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6352 for (unsigned i = 0; i != 16; ++i)
6353 ShufIdxs[i] = (i&3)+0;
6356 for (unsigned i = 0; i != 16; ++i)
6357 ShufIdxs[i] = (i&3)+4;
6360 for (unsigned i = 0; i != 16; ++i)
6361 ShufIdxs[i] = (i&3)+8;
6364 for (unsigned i = 0; i != 16; ++i)
6365 ShufIdxs[i] = (i&3)+12;
6368 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6370 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6372 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6374 EVT VT = OpLHS.getValueType();
6375 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6376 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6377 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6378 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6381 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6382 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6383 /// return the code it can be lowered into. Worst case, it can always be
6384 /// lowered into a vperm.
6385 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6386 SelectionDAG &DAG) const {
6388 SDValue V1 = Op.getOperand(0);
6389 SDValue V2 = Op.getOperand(1);
6390 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6391 EVT VT = Op.getValueType();
6392 bool isLittleEndian = Subtarget.isLittleEndian();
6394 // Cases that are handled by instructions that take permute immediates
6395 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6396 // selected by the instruction selector.
6397 if (V2.getOpcode() == ISD::UNDEF) {
6398 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6399 PPC::isSplatShuffleMask(SVOp, 2) ||
6400 PPC::isSplatShuffleMask(SVOp, 4) ||
6401 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6402 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6403 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
6404 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6405 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6406 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6407 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6408 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6409 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6414 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6415 // and produce a fixed permutation. If any of these match, do not lower to
6417 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6418 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6419 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6420 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
6421 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6422 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6423 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6424 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6425 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6426 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6429 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6430 // perfect shuffle table to emit an optimal matching sequence.
6431 ArrayRef<int> PermMask = SVOp->getMask();
6433 unsigned PFIndexes[4];
6434 bool isFourElementShuffle = true;
6435 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6436 unsigned EltNo = 8; // Start out undef.
6437 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6438 if (PermMask[i*4+j] < 0)
6439 continue; // Undef, ignore it.
6441 unsigned ByteSource = PermMask[i*4+j];
6442 if ((ByteSource & 3) != j) {
6443 isFourElementShuffle = false;
6448 EltNo = ByteSource/4;
6449 } else if (EltNo != ByteSource/4) {
6450 isFourElementShuffle = false;
6454 PFIndexes[i] = EltNo;
6457 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6458 // perfect shuffle vector to determine if it is cost effective to do this as
6459 // discrete instructions, or whether we should use a vperm.
6460 // For now, we skip this for little endian until such time as we have a
6461 // little-endian perfect shuffle table.
6462 if (isFourElementShuffle && !isLittleEndian) {
6463 // Compute the index in the perfect shuffle table.
6464 unsigned PFTableIndex =
6465 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6467 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6468 unsigned Cost = (PFEntry >> 30);
6470 // Determining when to avoid vperm is tricky. Many things affect the cost
6471 // of vperm, particularly how many times the perm mask needs to be computed.
6472 // For example, if the perm mask can be hoisted out of a loop or is already
6473 // used (perhaps because there are multiple permutes with the same shuffle
6474 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6475 // the loop requires an extra register.
6477 // As a compromise, we only emit discrete instructions if the shuffle can be
6478 // generated in 3 or fewer operations. When we have loop information
6479 // available, if this block is within a loop, we should avoid using vperm
6480 // for 3-operation perms and use a constant pool load instead.
6482 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6485 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6486 // vector that will get spilled to the constant pool.
6487 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6489 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6490 // that it is in input element units, not in bytes. Convert now.
6492 // For little endian, the order of the input vectors is reversed, and
6493 // the permutation mask is complemented with respect to 31. This is
6494 // necessary to produce proper semantics with the big-endian-biased vperm
6496 EVT EltVT = V1.getValueType().getVectorElementType();
6497 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6499 SmallVector<SDValue, 16> ResultMask;
6500 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6501 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6503 for (unsigned j = 0; j != BytesPerElement; ++j)
6505 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6508 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6512 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6515 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6518 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6522 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6523 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6524 /// information about the intrinsic.
6525 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6527 unsigned IntrinsicID =
6528 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6531 switch (IntrinsicID) {
6532 default: return false;
6533 // Comparison predicates.
6534 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6535 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6536 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6537 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6538 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6539 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6540 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6541 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6542 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6543 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6544 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6545 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6546 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6548 // Normal Comparisons.
6549 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6550 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6551 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6552 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6553 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6554 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6555 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6556 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6557 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6558 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6559 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6560 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6561 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6566 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6567 /// lower, do it, otherwise return null.
6568 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6569 SelectionDAG &DAG) const {
6570 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6571 // opcode number of the comparison.
6575 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6576 return SDValue(); // Don't custom lower most intrinsics.
6578 // If this is a non-dot comparison, make the VCMP node and we are done.
6580 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6581 Op.getOperand(1), Op.getOperand(2),
6582 DAG.getConstant(CompareOpc, MVT::i32));
6583 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6586 // Create the PPCISD altivec 'dot' comparison node.
6588 Op.getOperand(2), // LHS
6589 Op.getOperand(3), // RHS
6590 DAG.getConstant(CompareOpc, MVT::i32)
6592 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6593 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6595 // Now that we have the comparison, emit a copy from the CR to a GPR.
6596 // This is flagged to the above dot comparison.
6597 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6598 DAG.getRegister(PPC::CR6, MVT::i32),
6599 CompNode.getValue(1));
6601 // Unpack the result based on how the target uses it.
6602 unsigned BitNo; // Bit # of CR6.
6603 bool InvertBit; // Invert result?
6604 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6605 default: // Can't happen, don't crash on invalid number though.
6606 case 0: // Return the value of the EQ bit of CR6.
6607 BitNo = 0; InvertBit = false;
6609 case 1: // Return the inverted value of the EQ bit of CR6.
6610 BitNo = 0; InvertBit = true;
6612 case 2: // Return the value of the LT bit of CR6.
6613 BitNo = 2; InvertBit = false;
6615 case 3: // Return the inverted value of the LT bit of CR6.
6616 BitNo = 2; InvertBit = true;
6620 // Shift the bit into the low position.
6621 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6622 DAG.getConstant(8-(3-BitNo), MVT::i32));
6624 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6625 DAG.getConstant(1, MVT::i32));
6627 // If we are supposed to, toggle the bit.
6629 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6630 DAG.getConstant(1, MVT::i32));
6634 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6635 SelectionDAG &DAG) const {
6637 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6638 // instructions), but for smaller types, we need to first extend up to v2i32
6639 // before doing going farther.
6640 if (Op.getValueType() == MVT::v2i64) {
6641 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6642 if (ExtVT != MVT::v2i32) {
6643 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6644 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6645 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6646 ExtVT.getVectorElementType(), 4)));
6647 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6648 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6649 DAG.getValueType(MVT::v2i32));
6658 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6659 SelectionDAG &DAG) const {
6661 // Create a stack slot that is 16-byte aligned.
6662 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6663 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6664 EVT PtrVT = getPointerTy();
6665 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6667 // Store the input value into Value#0 of the stack slot.
6668 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6669 Op.getOperand(0), FIdx, MachinePointerInfo(),
6672 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6673 false, false, false, 0);
6676 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6678 if (Op.getValueType() == MVT::v4i32) {
6679 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6681 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6682 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6684 SDValue RHSSwap = // = vrlw RHS, 16
6685 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6687 // Shrinkify inputs to v8i16.
6688 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6689 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6690 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6692 // Low parts multiplied together, generating 32-bit results (we ignore the
6694 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6695 LHS, RHS, DAG, dl, MVT::v4i32);
6697 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6698 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6699 // Shift the high parts up 16 bits.
6700 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6702 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6703 } else if (Op.getValueType() == MVT::v8i16) {
6704 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6706 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6708 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6709 LHS, RHS, Zero, DAG, dl);
6710 } else if (Op.getValueType() == MVT::v16i8) {
6711 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6712 bool isLittleEndian = Subtarget.isLittleEndian();
6714 // Multiply the even 8-bit parts, producing 16-bit sums.
6715 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6716 LHS, RHS, DAG, dl, MVT::v8i16);
6717 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6719 // Multiply the odd 8-bit parts, producing 16-bit sums.
6720 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6721 LHS, RHS, DAG, dl, MVT::v8i16);
6722 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6724 // Merge the results together. Because vmuleub and vmuloub are
6725 // instructions with a big-endian bias, we must reverse the
6726 // element numbering and reverse the meaning of "odd" and "even"
6727 // when generating little endian code.
6729 for (unsigned i = 0; i != 8; ++i) {
6730 if (isLittleEndian) {
6732 Ops[i*2+1] = 2*i+16;
6735 Ops[i*2+1] = 2*i+1+16;
6739 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6741 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6743 llvm_unreachable("Unknown mul to lower!");
6747 /// LowerOperation - Provide custom lowering hooks for some operations.
6749 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6750 switch (Op.getOpcode()) {
6751 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6752 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6753 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6754 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6755 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6756 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6757 case ISD::SETCC: return LowerSETCC(Op, DAG);
6758 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6759 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6761 return LowerVASTART(Op, DAG, Subtarget);
6764 return LowerVAARG(Op, DAG, Subtarget);
6767 return LowerVACOPY(Op, DAG, Subtarget);
6769 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6770 case ISD::DYNAMIC_STACKALLOC:
6771 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6773 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6774 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6776 case ISD::LOAD: return LowerLOAD(Op, DAG);
6777 case ISD::STORE: return LowerSTORE(Op, DAG);
6778 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6779 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6780 case ISD::FP_TO_UINT:
6781 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6783 case ISD::UINT_TO_FP:
6784 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6785 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6787 // Lower 64-bit shifts.
6788 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6789 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6790 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6792 // Vector-related lowering.
6793 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6794 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6795 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6796 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6797 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6798 case ISD::MUL: return LowerMUL(Op, DAG);
6800 // For counter-based loop handling.
6801 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6803 // Frame & Return address.
6804 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6805 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6809 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6810 SmallVectorImpl<SDValue>&Results,
6811 SelectionDAG &DAG) const {
6812 const TargetMachine &TM = getTargetMachine();
6814 switch (N->getOpcode()) {
6816 llvm_unreachable("Do not know how to custom type legalize this operation!");
6817 case ISD::READCYCLECOUNTER: {
6818 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6819 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
6821 Results.push_back(RTB);
6822 Results.push_back(RTB.getValue(1));
6823 Results.push_back(RTB.getValue(2));
6826 case ISD::INTRINSIC_W_CHAIN: {
6827 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6828 Intrinsic::ppc_is_decremented_ctr_nonzero)
6831 assert(N->getValueType(0) == MVT::i1 &&
6832 "Unexpected result type for CTR decrement intrinsic");
6833 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6834 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6835 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6838 Results.push_back(NewInt);
6839 Results.push_back(NewInt.getValue(1));
6843 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6844 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6847 EVT VT = N->getValueType(0);
6849 if (VT == MVT::i64) {
6850 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6852 Results.push_back(NewNode);
6853 Results.push_back(NewNode.getValue(1));
6857 case ISD::FP_ROUND_INREG: {
6858 assert(N->getValueType(0) == MVT::ppcf128);
6859 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6860 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6861 MVT::f64, N->getOperand(0),
6862 DAG.getIntPtrConstant(0));
6863 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6864 MVT::f64, N->getOperand(0),
6865 DAG.getIntPtrConstant(1));
6867 // Add the two halves of the long double in round-to-zero mode.
6868 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6870 // We know the low half is about to be thrown away, so just use something
6872 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6876 case ISD::FP_TO_SINT:
6877 // LowerFP_TO_INT() can only handle f32 and f64.
6878 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6880 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6886 //===----------------------------------------------------------------------===//
6887 // Other Lowering Code
6888 //===----------------------------------------------------------------------===//
6890 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
6891 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
6892 Function *Func = Intrinsic::getDeclaration(M, Id);
6893 return Builder.CreateCall(Func);
6896 // The mappings for emitLeading/TrailingFence is taken from
6897 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
6898 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
6899 AtomicOrdering Ord, bool IsStore,
6900 bool IsLoad) const {
6901 if (Ord == SequentiallyConsistent)
6902 return callIntrinsic(Builder, Intrinsic::ppc_sync);
6903 else if (isAtLeastRelease(Ord))
6904 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6909 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
6910 AtomicOrdering Ord, bool IsStore,
6911 bool IsLoad) const {
6912 if (IsLoad && isAtLeastAcquire(Ord))
6913 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6914 // FIXME: this is too conservative, a dependent branch + isync is enough.
6915 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
6916 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
6917 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
6923 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6924 bool is64bit, unsigned BinOpcode) const {
6925 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6926 const TargetInstrInfo *TII =
6927 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6929 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6930 MachineFunction *F = BB->getParent();
6931 MachineFunction::iterator It = BB;
6934 unsigned dest = MI->getOperand(0).getReg();
6935 unsigned ptrA = MI->getOperand(1).getReg();
6936 unsigned ptrB = MI->getOperand(2).getReg();
6937 unsigned incr = MI->getOperand(3).getReg();
6938 DebugLoc dl = MI->getDebugLoc();
6940 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6941 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6942 F->insert(It, loopMBB);
6943 F->insert(It, exitMBB);
6944 exitMBB->splice(exitMBB->begin(), BB,
6945 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6946 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6948 MachineRegisterInfo &RegInfo = F->getRegInfo();
6949 unsigned TmpReg = (!BinOpcode) ? incr :
6950 RegInfo.createVirtualRegister( is64bit ? &PPC::G8RCRegClass
6951 : &PPC::GPRCRegClass);
6955 // fallthrough --> loopMBB
6956 BB->addSuccessor(loopMBB);
6959 // l[wd]arx dest, ptr
6960 // add r0, dest, incr
6961 // st[wd]cx. r0, ptr
6963 // fallthrough --> exitMBB
6965 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6966 .addReg(ptrA).addReg(ptrB);
6968 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6969 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6970 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6971 BuildMI(BB, dl, TII->get(PPC::BCC))
6972 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6973 BB->addSuccessor(loopMBB);
6974 BB->addSuccessor(exitMBB);
6983 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6984 MachineBasicBlock *BB,
6985 bool is8bit, // operation
6986 unsigned BinOpcode) const {
6987 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6988 const TargetInstrInfo *TII =
6989 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6990 // In 64 bit mode we have to use 64 bits for addresses, even though the
6991 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6992 // registers without caring whether they're 32 or 64, but here we're
6993 // doing actual arithmetic on the addresses.
6994 bool is64bit = Subtarget.isPPC64();
6995 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6997 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6998 MachineFunction *F = BB->getParent();
6999 MachineFunction::iterator It = BB;
7002 unsigned dest = MI->getOperand(0).getReg();
7003 unsigned ptrA = MI->getOperand(1).getReg();
7004 unsigned ptrB = MI->getOperand(2).getReg();
7005 unsigned incr = MI->getOperand(3).getReg();
7006 DebugLoc dl = MI->getDebugLoc();
7008 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
7009 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7010 F->insert(It, loopMBB);
7011 F->insert(It, exitMBB);
7012 exitMBB->splice(exitMBB->begin(), BB,
7013 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7014 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7016 MachineRegisterInfo &RegInfo = F->getRegInfo();
7017 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
7018 : &PPC::GPRCRegClass;
7019 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7020 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7021 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7022 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
7023 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7024 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7025 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7026 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7027 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
7028 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7029 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7031 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
7035 // fallthrough --> loopMBB
7036 BB->addSuccessor(loopMBB);
7038 // The 4-byte load must be aligned, while a char or short may be
7039 // anywhere in the word. Hence all this nasty bookkeeping code.
7040 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7041 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7042 // xori shift, shift1, 24 [16]
7043 // rlwinm ptr, ptr1, 0, 0, 29
7044 // slw incr2, incr, shift
7045 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7046 // slw mask, mask2, shift
7048 // lwarx tmpDest, ptr
7049 // add tmp, tmpDest, incr2
7050 // andc tmp2, tmpDest, mask
7051 // and tmp3, tmp, mask
7052 // or tmp4, tmp3, tmp2
7055 // fallthrough --> exitMBB
7056 // srw dest, tmpDest, shift
7057 if (ptrA != ZeroReg) {
7058 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7059 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7060 .addReg(ptrA).addReg(ptrB);
7064 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7065 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7066 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7067 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7069 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7070 .addReg(Ptr1Reg).addImm(0).addImm(61);
7072 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7073 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7074 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
7075 .addReg(incr).addReg(ShiftReg);
7077 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7079 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7080 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
7082 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7083 .addReg(Mask2Reg).addReg(ShiftReg);
7086 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7087 .addReg(ZeroReg).addReg(PtrReg);
7089 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
7090 .addReg(Incr2Reg).addReg(TmpDestReg);
7091 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
7092 .addReg(TmpDestReg).addReg(MaskReg);
7093 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
7094 .addReg(TmpReg).addReg(MaskReg);
7095 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
7096 .addReg(Tmp3Reg).addReg(Tmp2Reg);
7097 BuildMI(BB, dl, TII->get(PPC::STWCX))
7098 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
7099 BuildMI(BB, dl, TII->get(PPC::BCC))
7100 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
7101 BB->addSuccessor(loopMBB);
7102 BB->addSuccessor(exitMBB);
7107 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
7112 llvm::MachineBasicBlock*
7113 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
7114 MachineBasicBlock *MBB) const {
7115 DebugLoc DL = MI->getDebugLoc();
7116 const TargetInstrInfo *TII =
7117 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7119 MachineFunction *MF = MBB->getParent();
7120 MachineRegisterInfo &MRI = MF->getRegInfo();
7122 const BasicBlock *BB = MBB->getBasicBlock();
7123 MachineFunction::iterator I = MBB;
7127 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
7128 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
7130 unsigned DstReg = MI->getOperand(0).getReg();
7131 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
7132 assert(RC->hasType(MVT::i32) && "Invalid destination!");
7133 unsigned mainDstReg = MRI.createVirtualRegister(RC);
7134 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
7136 MVT PVT = getPointerTy();
7137 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
7138 "Invalid Pointer Size!");
7139 // For v = setjmp(buf), we generate
7142 // SjLjSetup mainMBB
7148 // buf[LabelOffset] = LR
7152 // v = phi(main, restore)
7155 MachineBasicBlock *thisMBB = MBB;
7156 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
7157 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
7158 MF->insert(I, mainMBB);
7159 MF->insert(I, sinkMBB);
7161 MachineInstrBuilder MIB;
7163 // Transfer the remainder of BB and its successor edges to sinkMBB.
7164 sinkMBB->splice(sinkMBB->begin(), MBB,
7165 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
7166 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
7168 // Note that the structure of the jmp_buf used here is not compatible
7169 // with that used by libc, and is not designed to be. Specifically, it
7170 // stores only those 'reserved' registers that LLVM does not otherwise
7171 // understand how to spill. Also, by convention, by the time this
7172 // intrinsic is called, Clang has already stored the frame address in the
7173 // first slot of the buffer and stack address in the third. Following the
7174 // X86 target code, we'll store the jump address in the second slot. We also
7175 // need to save the TOC pointer (R2) to handle jumps between shared
7176 // libraries, and that will be stored in the fourth slot. The thread
7177 // identifier (R13) is not affected.
7180 const int64_t LabelOffset = 1 * PVT.getStoreSize();
7181 const int64_t TOCOffset = 3 * PVT.getStoreSize();
7182 const int64_t BPOffset = 4 * PVT.getStoreSize();
7184 // Prepare IP either in reg.
7185 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
7186 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
7187 unsigned BufReg = MI->getOperand(1).getReg();
7189 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
7190 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
7194 MIB.setMemRefs(MMOBegin, MMOEnd);
7197 // Naked functions never have a base pointer, and so we use r1. For all
7198 // other functions, this decision must be delayed until during PEI.
7200 if (MF->getFunction()->getAttributes().hasAttribute(
7201 AttributeSet::FunctionIndex, Attribute::Naked))
7202 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
7204 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
7206 MIB = BuildMI(*thisMBB, MI, DL,
7207 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
7211 MIB.setMemRefs(MMOBegin, MMOEnd);
7214 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
7215 const PPCRegisterInfo *TRI =
7216 getTargetMachine().getSubtarget<PPCSubtarget>().getRegisterInfo();
7217 MIB.addRegMask(TRI->getNoPreservedMask());
7219 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
7221 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
7223 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
7225 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
7226 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
7230 MIB = BuildMI(mainMBB, DL,
7231 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
7234 if (Subtarget.isPPC64()) {
7235 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
7237 .addImm(LabelOffset)
7240 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
7242 .addImm(LabelOffset)
7246 MIB.setMemRefs(MMOBegin, MMOEnd);
7248 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
7249 mainMBB->addSuccessor(sinkMBB);
7252 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
7253 TII->get(PPC::PHI), DstReg)
7254 .addReg(mainDstReg).addMBB(mainMBB)
7255 .addReg(restoreDstReg).addMBB(thisMBB);
7257 MI->eraseFromParent();
7262 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
7263 MachineBasicBlock *MBB) const {
7264 DebugLoc DL = MI->getDebugLoc();
7265 const TargetInstrInfo *TII =
7266 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7268 MachineFunction *MF = MBB->getParent();
7269 MachineRegisterInfo &MRI = MF->getRegInfo();
7272 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
7273 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
7275 MVT PVT = getPointerTy();
7276 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
7277 "Invalid Pointer Size!");
7279 const TargetRegisterClass *RC =
7280 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
7281 unsigned Tmp = MRI.createVirtualRegister(RC);
7282 // Since FP is only updated here but NOT referenced, it's treated as GPR.
7283 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
7284 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
7285 unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
7286 (Subtarget.isSVR4ABI() &&
7287 MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
7288 PPC::R29 : PPC::R30);
7290 MachineInstrBuilder MIB;
7292 const int64_t LabelOffset = 1 * PVT.getStoreSize();
7293 const int64_t SPOffset = 2 * PVT.getStoreSize();
7294 const int64_t TOCOffset = 3 * PVT.getStoreSize();
7295 const int64_t BPOffset = 4 * PVT.getStoreSize();
7297 unsigned BufReg = MI->getOperand(0).getReg();
7299 // Reload FP (the jumped-to function may not have had a
7300 // frame pointer, and if so, then its r31 will be restored
7302 if (PVT == MVT::i64) {
7303 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
7307 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
7311 MIB.setMemRefs(MMOBegin, MMOEnd);
7314 if (PVT == MVT::i64) {
7315 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
7316 .addImm(LabelOffset)
7319 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
7320 .addImm(LabelOffset)
7323 MIB.setMemRefs(MMOBegin, MMOEnd);
7326 if (PVT == MVT::i64) {
7327 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
7331 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
7335 MIB.setMemRefs(MMOBegin, MMOEnd);
7338 if (PVT == MVT::i64) {
7339 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
7343 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
7347 MIB.setMemRefs(MMOBegin, MMOEnd);
7350 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
7351 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
7355 MIB.setMemRefs(MMOBegin, MMOEnd);
7359 BuildMI(*MBB, MI, DL,
7360 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
7361 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
7363 MI->eraseFromParent();
7368 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7369 MachineBasicBlock *BB) const {
7370 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
7371 MI->getOpcode() == TargetOpcode::PATCHPOINT)
7372 return emitPatchPoint(MI, BB);
7374 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
7375 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
7376 return emitEHSjLjSetJmp(MI, BB);
7377 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
7378 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
7379 return emitEHSjLjLongJmp(MI, BB);
7382 const TargetInstrInfo *TII =
7383 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7385 // To "insert" these instructions we actually have to insert their
7386 // control-flow patterns.
7387 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7388 MachineFunction::iterator It = BB;
7391 MachineFunction *F = BB->getParent();
7393 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7394 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7395 MI->getOpcode() == PPC::SELECT_I4 ||
7396 MI->getOpcode() == PPC::SELECT_I8)) {
7397 SmallVector<MachineOperand, 2> Cond;
7398 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7399 MI->getOpcode() == PPC::SELECT_CC_I8)
7400 Cond.push_back(MI->getOperand(4));
7402 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
7403 Cond.push_back(MI->getOperand(1));
7405 DebugLoc dl = MI->getDebugLoc();
7406 const TargetInstrInfo *TII =
7407 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7408 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7409 Cond, MI->getOperand(2).getReg(),
7410 MI->getOperand(3).getReg());
7411 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7412 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7413 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7414 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7415 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7416 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
7417 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
7418 MI->getOpcode() == PPC::SELECT_I4 ||
7419 MI->getOpcode() == PPC::SELECT_I8 ||
7420 MI->getOpcode() == PPC::SELECT_F4 ||
7421 MI->getOpcode() == PPC::SELECT_F8 ||
7422 MI->getOpcode() == PPC::SELECT_VRRC ||
7423 MI->getOpcode() == PPC::SELECT_VSFRC ||
7424 MI->getOpcode() == PPC::SELECT_VSRC) {
7425 // The incoming instruction knows the destination vreg to set, the
7426 // condition code register to branch on, the true/false values to
7427 // select between, and a branch opcode to use.
7432 // cmpTY ccX, r1, r2
7434 // fallthrough --> copy0MBB
7435 MachineBasicBlock *thisMBB = BB;
7436 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7437 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7438 DebugLoc dl = MI->getDebugLoc();
7439 F->insert(It, copy0MBB);
7440 F->insert(It, sinkMBB);
7442 // Transfer the remainder of BB and its successor edges to sinkMBB.
7443 sinkMBB->splice(sinkMBB->begin(), BB,
7444 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7445 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7447 // Next, add the true and fallthrough blocks as its successors.
7448 BB->addSuccessor(copy0MBB);
7449 BB->addSuccessor(sinkMBB);
7451 if (MI->getOpcode() == PPC::SELECT_I4 ||
7452 MI->getOpcode() == PPC::SELECT_I8 ||
7453 MI->getOpcode() == PPC::SELECT_F4 ||
7454 MI->getOpcode() == PPC::SELECT_F8 ||
7455 MI->getOpcode() == PPC::SELECT_VRRC ||
7456 MI->getOpcode() == PPC::SELECT_VSFRC ||
7457 MI->getOpcode() == PPC::SELECT_VSRC) {
7458 BuildMI(BB, dl, TII->get(PPC::BC))
7459 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7461 unsigned SelectPred = MI->getOperand(4).getImm();
7462 BuildMI(BB, dl, TII->get(PPC::BCC))
7463 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7467 // %FalseValue = ...
7468 // # fallthrough to sinkMBB
7471 // Update machine-CFG edges
7472 BB->addSuccessor(sinkMBB);
7475 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7478 BuildMI(*BB, BB->begin(), dl,
7479 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7480 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7481 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7482 } else if (MI->getOpcode() == PPC::ReadTB) {
7483 // To read the 64-bit time-base register on a 32-bit target, we read the
7484 // two halves. Should the counter have wrapped while it was being read, we
7485 // need to try again.
7488 // mfspr Rx,TBU # load from TBU
7489 // mfspr Ry,TB # load from TB
7490 // mfspr Rz,TBU # load from TBU
7491 // cmpw crX,Rx,Rz # check if ‘old’=’new’
7492 // bne readLoop # branch if they're not equal
7495 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
7496 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7497 DebugLoc dl = MI->getDebugLoc();
7498 F->insert(It, readMBB);
7499 F->insert(It, sinkMBB);
7501 // Transfer the remainder of BB and its successor edges to sinkMBB.
7502 sinkMBB->splice(sinkMBB->begin(), BB,
7503 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7504 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7506 BB->addSuccessor(readMBB);
7509 MachineRegisterInfo &RegInfo = F->getRegInfo();
7510 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
7511 unsigned LoReg = MI->getOperand(0).getReg();
7512 unsigned HiReg = MI->getOperand(1).getReg();
7514 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
7515 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
7516 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
7518 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
7520 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
7521 .addReg(HiReg).addReg(ReadAgainReg);
7522 BuildMI(BB, dl, TII->get(PPC::BCC))
7523 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
7525 BB->addSuccessor(readMBB);
7526 BB->addSuccessor(sinkMBB);
7528 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7529 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7530 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7531 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7532 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7533 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7534 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7535 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7537 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7538 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7539 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7540 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7541 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7542 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7543 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7544 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7546 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7547 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7548 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7549 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7550 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7551 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7552 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7553 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7555 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7556 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7557 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7558 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7559 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7560 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7561 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7562 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7564 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7565 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7566 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7567 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7568 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7569 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7570 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7571 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7573 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7574 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7575 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7576 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7577 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7578 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7579 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7580 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7582 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7583 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7584 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7585 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7586 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7587 BB = EmitAtomicBinary(MI, BB, false, 0);
7588 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7589 BB = EmitAtomicBinary(MI, BB, true, 0);
7591 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7592 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7593 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7595 unsigned dest = MI->getOperand(0).getReg();
7596 unsigned ptrA = MI->getOperand(1).getReg();
7597 unsigned ptrB = MI->getOperand(2).getReg();
7598 unsigned oldval = MI->getOperand(3).getReg();
7599 unsigned newval = MI->getOperand(4).getReg();
7600 DebugLoc dl = MI->getDebugLoc();
7602 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7603 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7604 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7605 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7606 F->insert(It, loop1MBB);
7607 F->insert(It, loop2MBB);
7608 F->insert(It, midMBB);
7609 F->insert(It, exitMBB);
7610 exitMBB->splice(exitMBB->begin(), BB,
7611 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7612 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7616 // fallthrough --> loopMBB
7617 BB->addSuccessor(loop1MBB);
7620 // l[wd]arx dest, ptr
7621 // cmp[wd] dest, oldval
7624 // st[wd]cx. newval, ptr
7628 // st[wd]cx. dest, ptr
7631 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7632 .addReg(ptrA).addReg(ptrB);
7633 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7634 .addReg(oldval).addReg(dest);
7635 BuildMI(BB, dl, TII->get(PPC::BCC))
7636 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7637 BB->addSuccessor(loop2MBB);
7638 BB->addSuccessor(midMBB);
7641 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7642 .addReg(newval).addReg(ptrA).addReg(ptrB);
7643 BuildMI(BB, dl, TII->get(PPC::BCC))
7644 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7645 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7646 BB->addSuccessor(loop1MBB);
7647 BB->addSuccessor(exitMBB);
7650 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7651 .addReg(dest).addReg(ptrA).addReg(ptrB);
7652 BB->addSuccessor(exitMBB);
7657 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7658 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7659 // We must use 64-bit registers for addresses when targeting 64-bit,
7660 // since we're actually doing arithmetic on them. Other registers
7662 bool is64bit = Subtarget.isPPC64();
7663 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7665 unsigned dest = MI->getOperand(0).getReg();
7666 unsigned ptrA = MI->getOperand(1).getReg();
7667 unsigned ptrB = MI->getOperand(2).getReg();
7668 unsigned oldval = MI->getOperand(3).getReg();
7669 unsigned newval = MI->getOperand(4).getReg();
7670 DebugLoc dl = MI->getDebugLoc();
7672 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7673 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7674 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7675 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7676 F->insert(It, loop1MBB);
7677 F->insert(It, loop2MBB);
7678 F->insert(It, midMBB);
7679 F->insert(It, exitMBB);
7680 exitMBB->splice(exitMBB->begin(), BB,
7681 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7682 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7684 MachineRegisterInfo &RegInfo = F->getRegInfo();
7685 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
7686 : &PPC::GPRCRegClass;
7687 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7688 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7689 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7690 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7691 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7692 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7693 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7694 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7695 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7696 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7697 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7698 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7699 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7701 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7702 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7705 // fallthrough --> loopMBB
7706 BB->addSuccessor(loop1MBB);
7708 // The 4-byte load must be aligned, while a char or short may be
7709 // anywhere in the word. Hence all this nasty bookkeeping code.
7710 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7711 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7712 // xori shift, shift1, 24 [16]
7713 // rlwinm ptr, ptr1, 0, 0, 29
7714 // slw newval2, newval, shift
7715 // slw oldval2, oldval,shift
7716 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7717 // slw mask, mask2, shift
7718 // and newval3, newval2, mask
7719 // and oldval3, oldval2, mask
7721 // lwarx tmpDest, ptr
7722 // and tmp, tmpDest, mask
7723 // cmpw tmp, oldval3
7726 // andc tmp2, tmpDest, mask
7727 // or tmp4, tmp2, newval3
7732 // stwcx. tmpDest, ptr
7734 // srw dest, tmpDest, shift
7735 if (ptrA != ZeroReg) {
7736 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7737 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7738 .addReg(ptrA).addReg(ptrB);
7742 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7743 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7744 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7745 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7747 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7748 .addReg(Ptr1Reg).addImm(0).addImm(61);
7750 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7751 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7752 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7753 .addReg(newval).addReg(ShiftReg);
7754 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7755 .addReg(oldval).addReg(ShiftReg);
7757 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7759 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7760 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7761 .addReg(Mask3Reg).addImm(65535);
7763 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7764 .addReg(Mask2Reg).addReg(ShiftReg);
7765 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7766 .addReg(NewVal2Reg).addReg(MaskReg);
7767 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7768 .addReg(OldVal2Reg).addReg(MaskReg);
7771 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7772 .addReg(ZeroReg).addReg(PtrReg);
7773 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7774 .addReg(TmpDestReg).addReg(MaskReg);
7775 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7776 .addReg(TmpReg).addReg(OldVal3Reg);
7777 BuildMI(BB, dl, TII->get(PPC::BCC))
7778 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7779 BB->addSuccessor(loop2MBB);
7780 BB->addSuccessor(midMBB);
7783 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7784 .addReg(TmpDestReg).addReg(MaskReg);
7785 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7786 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7787 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7788 .addReg(ZeroReg).addReg(PtrReg);
7789 BuildMI(BB, dl, TII->get(PPC::BCC))
7790 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7791 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7792 BB->addSuccessor(loop1MBB);
7793 BB->addSuccessor(exitMBB);
7796 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7797 .addReg(ZeroReg).addReg(PtrReg);
7798 BB->addSuccessor(exitMBB);
7803 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7805 } else if (MI->getOpcode() == PPC::FADDrtz) {
7806 // This pseudo performs an FADD with rounding mode temporarily forced
7807 // to round-to-zero. We emit this via custom inserter since the FPSCR
7808 // is not modeled at the SelectionDAG level.
7809 unsigned Dest = MI->getOperand(0).getReg();
7810 unsigned Src1 = MI->getOperand(1).getReg();
7811 unsigned Src2 = MI->getOperand(2).getReg();
7812 DebugLoc dl = MI->getDebugLoc();
7814 MachineRegisterInfo &RegInfo = F->getRegInfo();
7815 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7817 // Save FPSCR value.
7818 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7820 // Set rounding mode to round-to-zero.
7821 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7822 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7824 // Perform addition.
7825 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7827 // Restore FPSCR value.
7828 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
7829 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7830 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7831 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7832 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7833 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7834 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7835 PPC::ANDIo8 : PPC::ANDIo;
7836 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7837 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7839 MachineRegisterInfo &RegInfo = F->getRegInfo();
7840 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7841 &PPC::GPRCRegClass :
7842 &PPC::G8RCRegClass);
7844 DebugLoc dl = MI->getDebugLoc();
7845 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7846 .addReg(MI->getOperand(1).getReg()).addImm(1);
7847 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7848 MI->getOperand(0).getReg())
7849 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7851 llvm_unreachable("Unexpected instr type to insert");
7854 MI->eraseFromParent(); // The pseudo instruction is gone now.
7858 //===----------------------------------------------------------------------===//
7859 // Target Optimization Hooks
7860 //===----------------------------------------------------------------------===//
7862 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
7863 DAGCombinerInfo &DCI,
7864 unsigned &RefinementSteps,
7865 bool &UseOneConstNR) const {
7866 EVT VT = Operand.getValueType();
7867 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7868 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7869 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7870 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7871 // Convergence is quadratic, so we essentially double the number of digits
7872 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7873 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7874 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7875 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7876 if (VT.getScalarType() == MVT::f64)
7878 UseOneConstNR = true;
7879 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
7884 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
7885 DAGCombinerInfo &DCI,
7886 unsigned &RefinementSteps) const {
7887 EVT VT = Operand.getValueType();
7888 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7889 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7890 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7891 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7892 // Convergence is quadratic, so we essentially double the number of digits
7893 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7894 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7895 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7896 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7897 if (VT.getScalarType() == MVT::f64)
7899 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
7904 bool PPCTargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
7905 // Note: This functionality is used only when unsafe-fp-math is enabled, and
7906 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
7907 // enabled for division), this functionality is redundant with the default
7908 // combiner logic (once the division -> reciprocal/multiply transformation
7909 // has taken place). As a result, this matters more for older cores than for
7912 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
7913 // reciprocal if there are two or more FDIVs (for embedded cores with only
7914 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
7915 switch (Subtarget.getDarwinDirective()) {
7917 return NumUsers > 2;
7920 case PPC::DIR_E500mc:
7921 case PPC::DIR_E5500:
7922 return NumUsers > 1;
7926 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
7927 unsigned Bytes, int Dist,
7928 SelectionDAG &DAG) {
7929 if (VT.getSizeInBits() / 8 != Bytes)
7932 SDValue BaseLoc = Base->getBasePtr();
7933 if (Loc.getOpcode() == ISD::FrameIndex) {
7934 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7936 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7937 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7938 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7939 int FS = MFI->getObjectSize(FI);
7940 int BFS = MFI->getObjectSize(BFI);
7941 if (FS != BFS || FS != (int)Bytes) return false;
7942 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7946 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7947 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7950 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7951 const GlobalValue *GV1 = nullptr;
7952 const GlobalValue *GV2 = nullptr;
7953 int64_t Offset1 = 0;
7954 int64_t Offset2 = 0;
7955 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7956 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7957 if (isGA1 && isGA2 && GV1 == GV2)
7958 return Offset1 == (Offset2 + Dist*Bytes);
7962 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7963 // not enforce equality of the chain operands.
7964 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
7965 unsigned Bytes, int Dist,
7966 SelectionDAG &DAG) {
7967 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
7968 EVT VT = LS->getMemoryVT();
7969 SDValue Loc = LS->getBasePtr();
7970 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
7973 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
7975 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7976 default: return false;
7977 case Intrinsic::ppc_altivec_lvx:
7978 case Intrinsic::ppc_altivec_lvxl:
7979 case Intrinsic::ppc_vsx_lxvw4x:
7982 case Intrinsic::ppc_vsx_lxvd2x:
7985 case Intrinsic::ppc_altivec_lvebx:
7988 case Intrinsic::ppc_altivec_lvehx:
7991 case Intrinsic::ppc_altivec_lvewx:
7996 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
7999 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
8001 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8002 default: return false;
8003 case Intrinsic::ppc_altivec_stvx:
8004 case Intrinsic::ppc_altivec_stvxl:
8005 case Intrinsic::ppc_vsx_stxvw4x:
8008 case Intrinsic::ppc_vsx_stxvd2x:
8011 case Intrinsic::ppc_altivec_stvebx:
8014 case Intrinsic::ppc_altivec_stvehx:
8017 case Intrinsic::ppc_altivec_stvewx:
8022 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
8028 // Return true is there is a nearyby consecutive load to the one provided
8029 // (regardless of alignment). We search up and down the chain, looking though
8030 // token factors and other loads (but nothing else). As a result, a true result
8031 // indicates that it is safe to create a new consecutive load adjacent to the
8033 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
8034 SDValue Chain = LD->getChain();
8035 EVT VT = LD->getMemoryVT();
8037 SmallSet<SDNode *, 16> LoadRoots;
8038 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
8039 SmallSet<SDNode *, 16> Visited;
8041 // First, search up the chain, branching to follow all token-factor operands.
8042 // If we find a consecutive load, then we're done, otherwise, record all
8043 // nodes just above the top-level loads and token factors.
8044 while (!Queue.empty()) {
8045 SDNode *ChainNext = Queue.pop_back_val();
8046 if (!Visited.insert(ChainNext).second)
8049 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
8050 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
8053 if (!Visited.count(ChainLD->getChain().getNode()))
8054 Queue.push_back(ChainLD->getChain().getNode());
8055 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
8056 for (const SDUse &O : ChainNext->ops())
8057 if (!Visited.count(O.getNode()))
8058 Queue.push_back(O.getNode());
8060 LoadRoots.insert(ChainNext);
8063 // Second, search down the chain, starting from the top-level nodes recorded
8064 // in the first phase. These top-level nodes are the nodes just above all
8065 // loads and token factors. Starting with their uses, recursively look though
8066 // all loads (just the chain uses) and token factors to find a consecutive
8071 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
8072 IE = LoadRoots.end(); I != IE; ++I) {
8073 Queue.push_back(*I);
8075 while (!Queue.empty()) {
8076 SDNode *LoadRoot = Queue.pop_back_val();
8077 if (!Visited.insert(LoadRoot).second)
8080 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
8081 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
8084 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
8085 UE = LoadRoot->use_end(); UI != UE; ++UI)
8086 if (((isa<MemSDNode>(*UI) &&
8087 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
8088 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
8089 Queue.push_back(*UI);
8096 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
8097 DAGCombinerInfo &DCI) const {
8098 SelectionDAG &DAG = DCI.DAG;
8101 assert(Subtarget.useCRBits() &&
8102 "Expecting to be tracking CR bits");
8103 // If we're tracking CR bits, we need to be careful that we don't have:
8104 // trunc(binary-ops(zext(x), zext(y)))
8106 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
8107 // such that we're unnecessarily moving things into GPRs when it would be
8108 // better to keep them in CR bits.
8110 // Note that trunc here can be an actual i1 trunc, or can be the effective
8111 // truncation that comes from a setcc or select_cc.
8112 if (N->getOpcode() == ISD::TRUNCATE &&
8113 N->getValueType(0) != MVT::i1)
8116 if (N->getOperand(0).getValueType() != MVT::i32 &&
8117 N->getOperand(0).getValueType() != MVT::i64)
8120 if (N->getOpcode() == ISD::SETCC ||
8121 N->getOpcode() == ISD::SELECT_CC) {
8122 // If we're looking at a comparison, then we need to make sure that the
8123 // high bits (all except for the first) don't matter the result.
8125 cast<CondCodeSDNode>(N->getOperand(
8126 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
8127 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
8129 if (ISD::isSignedIntSetCC(CC)) {
8130 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
8131 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
8133 } else if (ISD::isUnsignedIntSetCC(CC)) {
8134 if (!DAG.MaskedValueIsZero(N->getOperand(0),
8135 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
8136 !DAG.MaskedValueIsZero(N->getOperand(1),
8137 APInt::getHighBitsSet(OpBits, OpBits-1)))
8140 // This is neither a signed nor an unsigned comparison, just make sure
8141 // that the high bits are equal.
8142 APInt Op1Zero, Op1One;
8143 APInt Op2Zero, Op2One;
8144 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
8145 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
8147 // We don't really care about what is known about the first bit (if
8148 // anything), so clear it in all masks prior to comparing them.
8149 Op1Zero.clearBit(0); Op1One.clearBit(0);
8150 Op2Zero.clearBit(0); Op2One.clearBit(0);
8152 if (Op1Zero != Op2Zero || Op1One != Op2One)
8157 // We now know that the higher-order bits are irrelevant, we just need to
8158 // make sure that all of the intermediate operations are bit operations, and
8159 // all inputs are extensions.
8160 if (N->getOperand(0).getOpcode() != ISD::AND &&
8161 N->getOperand(0).getOpcode() != ISD::OR &&
8162 N->getOperand(0).getOpcode() != ISD::XOR &&
8163 N->getOperand(0).getOpcode() != ISD::SELECT &&
8164 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
8165 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
8166 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
8167 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
8168 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
8171 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
8172 N->getOperand(1).getOpcode() != ISD::AND &&
8173 N->getOperand(1).getOpcode() != ISD::OR &&
8174 N->getOperand(1).getOpcode() != ISD::XOR &&
8175 N->getOperand(1).getOpcode() != ISD::SELECT &&
8176 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
8177 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
8178 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
8179 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
8180 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
8183 SmallVector<SDValue, 4> Inputs;
8184 SmallVector<SDValue, 8> BinOps, PromOps;
8185 SmallPtrSet<SDNode *, 16> Visited;
8187 for (unsigned i = 0; i < 2; ++i) {
8188 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8189 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8190 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
8191 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
8192 isa<ConstantSDNode>(N->getOperand(i)))
8193 Inputs.push_back(N->getOperand(i));
8195 BinOps.push_back(N->getOperand(i));
8197 if (N->getOpcode() == ISD::TRUNCATE)
8201 // Visit all inputs, collect all binary operations (and, or, xor and
8202 // select) that are all fed by extensions.
8203 while (!BinOps.empty()) {
8204 SDValue BinOp = BinOps.back();
8207 if (!Visited.insert(BinOp.getNode()).second)
8210 PromOps.push_back(BinOp);
8212 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8213 // The condition of the select is not promoted.
8214 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8216 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8219 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8220 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8221 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
8222 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
8223 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8224 Inputs.push_back(BinOp.getOperand(i));
8225 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8226 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8227 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8228 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8229 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
8230 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8231 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8232 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8233 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
8234 BinOps.push_back(BinOp.getOperand(i));
8236 // We have an input that is not an extension or another binary
8237 // operation; we'll abort this transformation.
8243 // Make sure that this is a self-contained cluster of operations (which
8244 // is not quite the same thing as saying that everything has only one
8246 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8247 if (isa<ConstantSDNode>(Inputs[i]))
8250 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8251 UE = Inputs[i].getNode()->use_end();
8254 if (User != N && !Visited.count(User))
8257 // Make sure that we're not going to promote the non-output-value
8258 // operand(s) or SELECT or SELECT_CC.
8259 // FIXME: Although we could sometimes handle this, and it does occur in
8260 // practice that one of the condition inputs to the select is also one of
8261 // the outputs, we currently can't deal with this.
8262 if (User->getOpcode() == ISD::SELECT) {
8263 if (User->getOperand(0) == Inputs[i])
8265 } else if (User->getOpcode() == ISD::SELECT_CC) {
8266 if (User->getOperand(0) == Inputs[i] ||
8267 User->getOperand(1) == Inputs[i])
8273 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8274 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8275 UE = PromOps[i].getNode()->use_end();
8278 if (User != N && !Visited.count(User))
8281 // Make sure that we're not going to promote the non-output-value
8282 // operand(s) or SELECT or SELECT_CC.
8283 // FIXME: Although we could sometimes handle this, and it does occur in
8284 // practice that one of the condition inputs to the select is also one of
8285 // the outputs, we currently can't deal with this.
8286 if (User->getOpcode() == ISD::SELECT) {
8287 if (User->getOperand(0) == PromOps[i])
8289 } else if (User->getOpcode() == ISD::SELECT_CC) {
8290 if (User->getOperand(0) == PromOps[i] ||
8291 User->getOperand(1) == PromOps[i])
8297 // Replace all inputs with the extension operand.
8298 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8299 // Constants may have users outside the cluster of to-be-promoted nodes,
8300 // and so we need to replace those as we do the promotions.
8301 if (isa<ConstantSDNode>(Inputs[i]))
8304 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
8307 // Replace all operations (these are all the same, but have a different
8308 // (i1) return type). DAG.getNode will validate that the types of
8309 // a binary operator match, so go through the list in reverse so that
8310 // we've likely promoted both operands first. Any intermediate truncations or
8311 // extensions disappear.
8312 while (!PromOps.empty()) {
8313 SDValue PromOp = PromOps.back();
8316 if (PromOp.getOpcode() == ISD::TRUNCATE ||
8317 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
8318 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
8319 PromOp.getOpcode() == ISD::ANY_EXTEND) {
8320 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
8321 PromOp.getOperand(0).getValueType() != MVT::i1) {
8322 // The operand is not yet ready (see comment below).
8323 PromOps.insert(PromOps.begin(), PromOp);
8327 SDValue RepValue = PromOp.getOperand(0);
8328 if (isa<ConstantSDNode>(RepValue))
8329 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
8331 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
8336 switch (PromOp.getOpcode()) {
8337 default: C = 0; break;
8338 case ISD::SELECT: C = 1; break;
8339 case ISD::SELECT_CC: C = 2; break;
8342 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8343 PromOp.getOperand(C).getValueType() != MVT::i1) ||
8344 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8345 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
8346 // The to-be-promoted operands of this node have not yet been
8347 // promoted (this should be rare because we're going through the
8348 // list backward, but if one of the operands has several users in
8349 // this cluster of to-be-promoted nodes, it is possible).
8350 PromOps.insert(PromOps.begin(), PromOp);
8354 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8355 PromOp.getNode()->op_end());
8357 // If there are any constant inputs, make sure they're replaced now.
8358 for (unsigned i = 0; i < 2; ++i)
8359 if (isa<ConstantSDNode>(Ops[C+i]))
8360 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
8362 DAG.ReplaceAllUsesOfValueWith(PromOp,
8363 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
8366 // Now we're left with the initial truncation itself.
8367 if (N->getOpcode() == ISD::TRUNCATE)
8368 return N->getOperand(0);
8370 // Otherwise, this is a comparison. The operands to be compared have just
8371 // changed type (to i1), but everything else is the same.
8372 return SDValue(N, 0);
8375 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
8376 DAGCombinerInfo &DCI) const {
8377 SelectionDAG &DAG = DCI.DAG;
8380 // If we're tracking CR bits, we need to be careful that we don't have:
8381 // zext(binary-ops(trunc(x), trunc(y)))
8383 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
8384 // such that we're unnecessarily moving things into CR bits that can more
8385 // efficiently stay in GPRs. Note that if we're not certain that the high
8386 // bits are set as required by the final extension, we still may need to do
8387 // some masking to get the proper behavior.
8389 // This same functionality is important on PPC64 when dealing with
8390 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
8391 // the return values of functions. Because it is so similar, it is handled
8394 if (N->getValueType(0) != MVT::i32 &&
8395 N->getValueType(0) != MVT::i64)
8398 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
8399 Subtarget.useCRBits()) ||
8400 (N->getOperand(0).getValueType() == MVT::i32 &&
8401 Subtarget.isPPC64())))
8404 if (N->getOperand(0).getOpcode() != ISD::AND &&
8405 N->getOperand(0).getOpcode() != ISD::OR &&
8406 N->getOperand(0).getOpcode() != ISD::XOR &&
8407 N->getOperand(0).getOpcode() != ISD::SELECT &&
8408 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
8411 SmallVector<SDValue, 4> Inputs;
8412 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
8413 SmallPtrSet<SDNode *, 16> Visited;
8415 // Visit all inputs, collect all binary operations (and, or, xor and
8416 // select) that are all fed by truncations.
8417 while (!BinOps.empty()) {
8418 SDValue BinOp = BinOps.back();
8421 if (!Visited.insert(BinOp.getNode()).second)
8424 PromOps.push_back(BinOp);
8426 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8427 // The condition of the select is not promoted.
8428 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8430 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8433 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8434 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8435 Inputs.push_back(BinOp.getOperand(i));
8436 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8437 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8438 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8439 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8440 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
8441 BinOps.push_back(BinOp.getOperand(i));
8443 // We have an input that is not a truncation or another binary
8444 // operation; we'll abort this transformation.
8450 // The operands of a select that must be truncated when the select is
8451 // promoted because the operand is actually part of the to-be-promoted set.
8452 DenseMap<SDNode *, EVT> SelectTruncOp[2];
8454 // Make sure that this is a self-contained cluster of operations (which
8455 // is not quite the same thing as saying that everything has only one
8457 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8458 if (isa<ConstantSDNode>(Inputs[i]))
8461 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8462 UE = Inputs[i].getNode()->use_end();
8465 if (User != N && !Visited.count(User))
8468 // If we're going to promote the non-output-value operand(s) or SELECT or
8469 // SELECT_CC, record them for truncation.
8470 if (User->getOpcode() == ISD::SELECT) {
8471 if (User->getOperand(0) == Inputs[i])
8472 SelectTruncOp[0].insert(std::make_pair(User,
8473 User->getOperand(0).getValueType()));
8474 } else if (User->getOpcode() == ISD::SELECT_CC) {
8475 if (User->getOperand(0) == Inputs[i])
8476 SelectTruncOp[0].insert(std::make_pair(User,
8477 User->getOperand(0).getValueType()));
8478 if (User->getOperand(1) == Inputs[i])
8479 SelectTruncOp[1].insert(std::make_pair(User,
8480 User->getOperand(1).getValueType()));
8485 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8486 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8487 UE = PromOps[i].getNode()->use_end();
8490 if (User != N && !Visited.count(User))
8493 // If we're going to promote the non-output-value operand(s) or SELECT or
8494 // SELECT_CC, record them for truncation.
8495 if (User->getOpcode() == ISD::SELECT) {
8496 if (User->getOperand(0) == PromOps[i])
8497 SelectTruncOp[0].insert(std::make_pair(User,
8498 User->getOperand(0).getValueType()));
8499 } else if (User->getOpcode() == ISD::SELECT_CC) {
8500 if (User->getOperand(0) == PromOps[i])
8501 SelectTruncOp[0].insert(std::make_pair(User,
8502 User->getOperand(0).getValueType()));
8503 if (User->getOperand(1) == PromOps[i])
8504 SelectTruncOp[1].insert(std::make_pair(User,
8505 User->getOperand(1).getValueType()));
8510 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8511 bool ReallyNeedsExt = false;
8512 if (N->getOpcode() != ISD::ANY_EXTEND) {
8513 // If all of the inputs are not already sign/zero extended, then
8514 // we'll still need to do that at the end.
8515 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8516 if (isa<ConstantSDNode>(Inputs[i]))
8520 Inputs[i].getOperand(0).getValueSizeInBits();
8521 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8523 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8524 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8525 APInt::getHighBitsSet(OpBits,
8526 OpBits-PromBits))) ||
8527 (N->getOpcode() == ISD::SIGN_EXTEND &&
8528 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8529 (OpBits-(PromBits-1)))) {
8530 ReallyNeedsExt = true;
8536 // Replace all inputs, either with the truncation operand, or a
8537 // truncation or extension to the final output type.
8538 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8539 // Constant inputs need to be replaced with the to-be-promoted nodes that
8540 // use them because they might have users outside of the cluster of
8542 if (isa<ConstantSDNode>(Inputs[i]))
8545 SDValue InSrc = Inputs[i].getOperand(0);
8546 if (Inputs[i].getValueType() == N->getValueType(0))
8547 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8548 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8549 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8550 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8551 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8552 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8553 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8555 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8556 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8559 // Replace all operations (these are all the same, but have a different
8560 // (promoted) return type). DAG.getNode will validate that the types of
8561 // a binary operator match, so go through the list in reverse so that
8562 // we've likely promoted both operands first.
8563 while (!PromOps.empty()) {
8564 SDValue PromOp = PromOps.back();
8568 switch (PromOp.getOpcode()) {
8569 default: C = 0; break;
8570 case ISD::SELECT: C = 1; break;
8571 case ISD::SELECT_CC: C = 2; break;
8574 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8575 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8576 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8577 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8578 // The to-be-promoted operands of this node have not yet been
8579 // promoted (this should be rare because we're going through the
8580 // list backward, but if one of the operands has several users in
8581 // this cluster of to-be-promoted nodes, it is possible).
8582 PromOps.insert(PromOps.begin(), PromOp);
8586 // For SELECT and SELECT_CC nodes, we do a similar check for any
8587 // to-be-promoted comparison inputs.
8588 if (PromOp.getOpcode() == ISD::SELECT ||
8589 PromOp.getOpcode() == ISD::SELECT_CC) {
8590 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
8591 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
8592 (SelectTruncOp[1].count(PromOp.getNode()) &&
8593 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
8594 PromOps.insert(PromOps.begin(), PromOp);
8599 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8600 PromOp.getNode()->op_end());
8602 // If this node has constant inputs, then they'll need to be promoted here.
8603 for (unsigned i = 0; i < 2; ++i) {
8604 if (!isa<ConstantSDNode>(Ops[C+i]))
8606 if (Ops[C+i].getValueType() == N->getValueType(0))
8609 if (N->getOpcode() == ISD::SIGN_EXTEND)
8610 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8611 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8612 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8614 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8617 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
8618 // truncate them again to the original value type.
8619 if (PromOp.getOpcode() == ISD::SELECT ||
8620 PromOp.getOpcode() == ISD::SELECT_CC) {
8621 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
8622 if (SI0 != SelectTruncOp[0].end())
8623 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
8624 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
8625 if (SI1 != SelectTruncOp[1].end())
8626 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
8629 DAG.ReplaceAllUsesOfValueWith(PromOp,
8630 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8633 // Now we're left with the initial extension itself.
8634 if (!ReallyNeedsExt)
8635 return N->getOperand(0);
8637 // To zero extend, just mask off everything except for the first bit (in the
8639 if (N->getOpcode() == ISD::ZERO_EXTEND)
8640 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8641 DAG.getConstant(APInt::getLowBitsSet(
8642 N->getValueSizeInBits(0), PromBits),
8643 N->getValueType(0)));
8645 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8646 "Invalid extension type");
8647 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8649 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8650 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8651 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8652 N->getOperand(0), ShiftCst), ShiftCst);
8655 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
8656 DAGCombinerInfo &DCI) const {
8657 assert((N->getOpcode() == ISD::SINT_TO_FP ||
8658 N->getOpcode() == ISD::UINT_TO_FP) &&
8659 "Need an int -> FP conversion node here");
8661 if (!Subtarget.has64BitSupport())
8664 SelectionDAG &DAG = DCI.DAG;
8668 // Don't handle ppc_fp128 here or i1 conversions.
8669 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
8671 if (Op.getOperand(0).getValueType() == MVT::i1)
8674 // For i32 intermediate values, unfortunately, the conversion functions
8675 // leave the upper 32 bits of the value are undefined. Within the set of
8676 // scalar instructions, we have no method for zero- or sign-extending the
8677 // value. Thus, we cannot handle i32 intermediate values here.
8678 if (Op.getOperand(0).getValueType() == MVT::i32)
8681 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
8682 "UINT_TO_FP is supported only with FPCVT");
8684 // If we have FCFIDS, then use it when converting to single-precision.
8685 // Otherwise, convert to double-precision and then round.
8686 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
8687 (Op.getOpcode() == ISD::UINT_TO_FP ?
8688 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
8689 (Op.getOpcode() == ISD::UINT_TO_FP ?
8690 PPCISD::FCFIDU : PPCISD::FCFID);
8691 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
8692 MVT::f32 : MVT::f64;
8694 // If we're converting from a float, to an int, and back to a float again,
8695 // then we don't need the store/load pair at all.
8696 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
8697 Subtarget.hasFPCVT()) ||
8698 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
8699 SDValue Src = Op.getOperand(0).getOperand(0);
8700 if (Src.getValueType() == MVT::f32) {
8701 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
8702 DCI.AddToWorklist(Src.getNode());
8706 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
8709 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
8710 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
8712 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
8713 FP = DAG.getNode(ISD::FP_ROUND, dl,
8714 MVT::f32, FP, DAG.getIntPtrConstant(0));
8715 DCI.AddToWorklist(FP.getNode());
8724 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
8725 // builtins) into loads with swaps.
8726 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
8727 DAGCombinerInfo &DCI) const {
8728 SelectionDAG &DAG = DCI.DAG;
8732 MachineMemOperand *MMO;
8734 switch (N->getOpcode()) {
8736 llvm_unreachable("Unexpected opcode for little endian VSX load");
8738 LoadSDNode *LD = cast<LoadSDNode>(N);
8739 Chain = LD->getChain();
8740 Base = LD->getBasePtr();
8741 MMO = LD->getMemOperand();
8742 // If the MMO suggests this isn't a load of a full vector, leave
8743 // things alone. For a built-in, we have to make the change for
8744 // correctness, so if there is a size problem that will be a bug.
8745 if (MMO->getSize() < 16)
8749 case ISD::INTRINSIC_W_CHAIN: {
8750 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8751 Chain = Intrin->getChain();
8752 Base = Intrin->getBasePtr();
8753 MMO = Intrin->getMemOperand();
8758 MVT VecTy = N->getValueType(0).getSimpleVT();
8759 SDValue LoadOps[] = { Chain, Base };
8760 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
8761 DAG.getVTList(VecTy, MVT::Other),
8762 LoadOps, VecTy, MMO);
8763 DCI.AddToWorklist(Load.getNode());
8764 Chain = Load.getValue(1);
8765 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8766 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
8767 DCI.AddToWorklist(Swap.getNode());
8771 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
8772 // builtins) into stores with swaps.
8773 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
8774 DAGCombinerInfo &DCI) const {
8775 SelectionDAG &DAG = DCI.DAG;
8780 MachineMemOperand *MMO;
8782 switch (N->getOpcode()) {
8784 llvm_unreachable("Unexpected opcode for little endian VSX store");
8786 StoreSDNode *ST = cast<StoreSDNode>(N);
8787 Chain = ST->getChain();
8788 Base = ST->getBasePtr();
8789 MMO = ST->getMemOperand();
8791 // If the MMO suggests this isn't a store of a full vector, leave
8792 // things alone. For a built-in, we have to make the change for
8793 // correctness, so if there is a size problem that will be a bug.
8794 if (MMO->getSize() < 16)
8798 case ISD::INTRINSIC_VOID: {
8799 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8800 Chain = Intrin->getChain();
8801 // Intrin->getBasePtr() oddly does not get what we want.
8802 Base = Intrin->getOperand(3);
8803 MMO = Intrin->getMemOperand();
8809 SDValue Src = N->getOperand(SrcOpnd);
8810 MVT VecTy = Src.getValueType().getSimpleVT();
8811 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8812 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
8813 DCI.AddToWorklist(Swap.getNode());
8814 Chain = Swap.getValue(1);
8815 SDValue StoreOps[] = { Chain, Swap, Base };
8816 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
8817 DAG.getVTList(MVT::Other),
8818 StoreOps, VecTy, MMO);
8819 DCI.AddToWorklist(Store.getNode());
8823 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8824 DAGCombinerInfo &DCI) const {
8825 const TargetMachine &TM = getTargetMachine();
8826 SelectionDAG &DAG = DCI.DAG;
8828 switch (N->getOpcode()) {
8831 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8832 if (C->isNullValue()) // 0 << V -> 0.
8833 return N->getOperand(0);
8837 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8838 if (C->isNullValue()) // 0 >>u V -> 0.
8839 return N->getOperand(0);
8843 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8844 if (C->isNullValue() || // 0 >>s V -> 0.
8845 C->isAllOnesValue()) // -1 >>s V -> -1.
8846 return N->getOperand(0);
8849 case ISD::SIGN_EXTEND:
8850 case ISD::ZERO_EXTEND:
8851 case ISD::ANY_EXTEND:
8852 return DAGCombineExtBoolTrunc(N, DCI);
8855 case ISD::SELECT_CC:
8856 return DAGCombineTruncBoolExt(N, DCI);
8857 case ISD::SINT_TO_FP:
8858 case ISD::UINT_TO_FP:
8859 return combineFPToIntToFP(N, DCI);
8861 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8862 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8863 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8864 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8865 N->getOperand(1).getValueType() == MVT::i32 &&
8866 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8867 SDValue Val = N->getOperand(1).getOperand(0);
8868 if (Val.getValueType() == MVT::f32) {
8869 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8870 DCI.AddToWorklist(Val.getNode());
8872 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8873 DCI.AddToWorklist(Val.getNode());
8876 N->getOperand(0), Val, N->getOperand(2),
8877 DAG.getValueType(N->getOperand(1).getValueType())
8880 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8881 DAG.getVTList(MVT::Other), Ops,
8882 cast<StoreSDNode>(N)->getMemoryVT(),
8883 cast<StoreSDNode>(N)->getMemOperand());
8884 DCI.AddToWorklist(Val.getNode());
8888 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8889 if (cast<StoreSDNode>(N)->isUnindexed() &&
8890 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8891 N->getOperand(1).getNode()->hasOneUse() &&
8892 (N->getOperand(1).getValueType() == MVT::i32 ||
8893 N->getOperand(1).getValueType() == MVT::i16 ||
8894 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8895 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8896 N->getOperand(1).getValueType() == MVT::i64))) {
8897 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8898 // Do an any-extend to 32-bits if this is a half-word input.
8899 if (BSwapOp.getValueType() == MVT::i16)
8900 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8903 N->getOperand(0), BSwapOp, N->getOperand(2),
8904 DAG.getValueType(N->getOperand(1).getValueType())
8907 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8908 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8909 cast<StoreSDNode>(N)->getMemOperand());
8912 // For little endian, VSX stores require generating xxswapd/lxvd2x.
8913 EVT VT = N->getOperand(1).getValueType();
8914 if (VT.isSimple()) {
8915 MVT StoreVT = VT.getSimpleVT();
8916 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8917 TM.getSubtarget<PPCSubtarget>().isLittleEndian() &&
8918 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
8919 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
8920 return expandVSXStoreForLE(N, DCI);
8925 LoadSDNode *LD = cast<LoadSDNode>(N);
8926 EVT VT = LD->getValueType(0);
8928 // For little endian, VSX loads require generating lxvd2x/xxswapd.
8929 if (VT.isSimple()) {
8930 MVT LoadVT = VT.getSimpleVT();
8931 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8932 TM.getSubtarget<PPCSubtarget>().isLittleEndian() &&
8933 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
8934 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
8935 return expandVSXLoadForLE(N, DCI);
8938 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8939 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8940 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8941 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8942 // P8 and later hardware should just use LOAD.
8943 !TM.getSubtarget<PPCSubtarget>().hasP8Vector() &&
8944 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8945 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8946 LD->getAlignment() < ABIAlignment) {
8947 // This is a type-legal unaligned Altivec load.
8948 SDValue Chain = LD->getChain();
8949 SDValue Ptr = LD->getBasePtr();
8950 bool isLittleEndian = Subtarget.isLittleEndian();
8952 // This implements the loading of unaligned vectors as described in
8953 // the venerable Apple Velocity Engine overview. Specifically:
8954 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8955 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8957 // The general idea is to expand a sequence of one or more unaligned
8958 // loads into an alignment-based permutation-control instruction (lvsl
8959 // or lvsr), a series of regular vector loads (which always truncate
8960 // their input address to an aligned address), and a series of
8961 // permutations. The results of these permutations are the requested
8962 // loaded values. The trick is that the last "extra" load is not taken
8963 // from the address you might suspect (sizeof(vector) bytes after the
8964 // last requested load), but rather sizeof(vector) - 1 bytes after the
8965 // last requested vector. The point of this is to avoid a page fault if
8966 // the base address happened to be aligned. This works because if the
8967 // base address is aligned, then adding less than a full vector length
8968 // will cause the last vector in the sequence to be (re)loaded.
8969 // Otherwise, the next vector will be fetched as you might suspect was
8972 // We might be able to reuse the permutation generation from
8973 // a different base address offset from this one by an aligned amount.
8974 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8975 // optimization later.
8976 Intrinsic::ID Intr = (isLittleEndian ?
8977 Intrinsic::ppc_altivec_lvsr :
8978 Intrinsic::ppc_altivec_lvsl);
8979 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8981 // Create the new MMO for the new base load. It is like the original MMO,
8982 // but represents an area in memory almost twice the vector size centered
8983 // on the original address. If the address is unaligned, we might start
8984 // reading up to (sizeof(vector)-1) bytes below the address of the
8985 // original unaligned load.
8986 MachineFunction &MF = DAG.getMachineFunction();
8987 MachineMemOperand *BaseMMO =
8988 MF.getMachineMemOperand(LD->getMemOperand(),
8989 -LD->getMemoryVT().getStoreSize()+1,
8990 2*LD->getMemoryVT().getStoreSize()-1);
8992 // Create the new base load.
8993 SDValue LDXIntID = DAG.getTargetConstant(Intrinsic::ppc_altivec_lvx,
8995 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
8997 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8998 DAG.getVTList(MVT::v4i32, MVT::Other),
8999 BaseLoadOps, MVT::v4i32, BaseMMO);
9001 // Note that the value of IncOffset (which is provided to the next
9002 // load's pointer info offset value, and thus used to calculate the
9003 // alignment), and the value of IncValue (which is actually used to
9004 // increment the pointer value) are different! This is because we
9005 // require the next load to appear to be aligned, even though it
9006 // is actually offset from the base pointer by a lesser amount.
9007 int IncOffset = VT.getSizeInBits() / 8;
9008 int IncValue = IncOffset;
9010 // Walk (both up and down) the chain looking for another load at the real
9011 // (aligned) offset (the alignment of the other load does not matter in
9012 // this case). If found, then do not use the offset reduction trick, as
9013 // that will prevent the loads from being later combined (as they would
9014 // otherwise be duplicates).
9015 if (!findConsecutiveLoad(LD, DAG))
9018 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
9019 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
9021 MachineMemOperand *ExtraMMO =
9022 MF.getMachineMemOperand(LD->getMemOperand(),
9023 1, 2*LD->getMemoryVT().getStoreSize()-1);
9024 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
9026 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
9027 DAG.getVTList(MVT::v4i32, MVT::Other),
9028 ExtraLoadOps, MVT::v4i32, ExtraMMO);
9030 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
9031 BaseLoad.getValue(1), ExtraLoad.getValue(1));
9033 // Because vperm has a big-endian bias, we must reverse the order
9034 // of the input vectors and complement the permute control vector
9035 // when generating little endian code. We have already handled the
9036 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
9037 // and ExtraLoad here.
9040 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
9041 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
9043 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
9044 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
9046 if (VT != MVT::v4i32)
9047 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
9049 // The output of the permutation is our loaded result, the TokenFactor is
9051 DCI.CombineTo(N, Perm, TF);
9052 return SDValue(N, 0);
9056 case ISD::INTRINSIC_WO_CHAIN: {
9057 bool isLittleEndian = Subtarget.isLittleEndian();
9058 Intrinsic::ID Intr = (isLittleEndian ?
9059 Intrinsic::ppc_altivec_lvsr :
9060 Intrinsic::ppc_altivec_lvsl);
9061 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
9062 N->getOperand(1)->getOpcode() == ISD::ADD) {
9063 SDValue Add = N->getOperand(1);
9065 if (DAG.MaskedValueIsZero(Add->getOperand(1),
9066 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
9067 Add.getValueType().getScalarType().getSizeInBits()))) {
9068 SDNode *BasePtr = Add->getOperand(0).getNode();
9069 for (SDNode::use_iterator UI = BasePtr->use_begin(),
9070 UE = BasePtr->use_end(); UI != UE; ++UI) {
9071 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
9072 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
9074 // We've found another LVSL/LVSR, and this address is an aligned
9075 // multiple of that one. The results will be the same, so use the
9076 // one we've just found instead.
9078 return SDValue(*UI, 0);
9086 case ISD::INTRINSIC_W_CHAIN: {
9087 // For little endian, VSX loads require generating lxvd2x/xxswapd.
9088 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
9089 TM.getSubtarget<PPCSubtarget>().isLittleEndian()) {
9090 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9093 case Intrinsic::ppc_vsx_lxvw4x:
9094 case Intrinsic::ppc_vsx_lxvd2x:
9095 return expandVSXLoadForLE(N, DCI);
9100 case ISD::INTRINSIC_VOID: {
9101 // For little endian, VSX stores require generating xxswapd/stxvd2x.
9102 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
9103 TM.getSubtarget<PPCSubtarget>().isLittleEndian()) {
9104 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9107 case Intrinsic::ppc_vsx_stxvw4x:
9108 case Intrinsic::ppc_vsx_stxvd2x:
9109 return expandVSXStoreForLE(N, DCI);
9115 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
9116 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
9117 N->getOperand(0).hasOneUse() &&
9118 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
9119 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
9120 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
9121 N->getValueType(0) == MVT::i64))) {
9122 SDValue Load = N->getOperand(0);
9123 LoadSDNode *LD = cast<LoadSDNode>(Load);
9124 // Create the byte-swapping load.
9126 LD->getChain(), // Chain
9127 LD->getBasePtr(), // Ptr
9128 DAG.getValueType(N->getValueType(0)) // VT
9131 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
9132 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
9133 MVT::i64 : MVT::i32, MVT::Other),
9134 Ops, LD->getMemoryVT(), LD->getMemOperand());
9136 // If this is an i16 load, insert the truncate.
9137 SDValue ResVal = BSLoad;
9138 if (N->getValueType(0) == MVT::i16)
9139 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
9141 // First, combine the bswap away. This makes the value produced by the
9143 DCI.CombineTo(N, ResVal);
9145 // Next, combine the load away, we give it a bogus result value but a real
9146 // chain result. The result value is dead because the bswap is dead.
9147 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
9149 // Return N so it doesn't get rechecked!
9150 return SDValue(N, 0);
9154 case PPCISD::VCMP: {
9155 // If a VCMPo node already exists with exactly the same operands as this
9156 // node, use its result instead of this node (VCMPo computes both a CR6 and
9157 // a normal output).
9159 if (!N->getOperand(0).hasOneUse() &&
9160 !N->getOperand(1).hasOneUse() &&
9161 !N->getOperand(2).hasOneUse()) {
9163 // Scan all of the users of the LHS, looking for VCMPo's that match.
9164 SDNode *VCMPoNode = nullptr;
9166 SDNode *LHSN = N->getOperand(0).getNode();
9167 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
9169 if (UI->getOpcode() == PPCISD::VCMPo &&
9170 UI->getOperand(1) == N->getOperand(1) &&
9171 UI->getOperand(2) == N->getOperand(2) &&
9172 UI->getOperand(0) == N->getOperand(0)) {
9177 // If there is no VCMPo node, or if the flag value has a single use, don't
9179 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
9182 // Look at the (necessarily single) use of the flag value. If it has a
9183 // chain, this transformation is more complex. Note that multiple things
9184 // could use the value result, which we should ignore.
9185 SDNode *FlagUser = nullptr;
9186 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
9187 FlagUser == nullptr; ++UI) {
9188 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
9190 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
9191 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
9198 // If the user is a MFOCRF instruction, we know this is safe.
9199 // Otherwise we give up for right now.
9200 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
9201 return SDValue(VCMPoNode, 0);
9206 SDValue Cond = N->getOperand(1);
9207 SDValue Target = N->getOperand(2);
9209 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9210 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
9211 Intrinsic::ppc_is_decremented_ctr_nonzero) {
9213 // We now need to make the intrinsic dead (it cannot be instruction
9215 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
9216 assert(Cond.getNode()->hasOneUse() &&
9217 "Counter decrement has more than one use");
9219 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
9220 N->getOperand(0), Target);
9225 // If this is a branch on an altivec predicate comparison, lower this so
9226 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
9227 // lowering is done pre-legalize, because the legalizer lowers the predicate
9228 // compare down to code that is difficult to reassemble.
9229 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
9230 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
9232 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
9233 // value. If so, pass-through the AND to get to the intrinsic.
9234 if (LHS.getOpcode() == ISD::AND &&
9235 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9236 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
9237 Intrinsic::ppc_is_decremented_ctr_nonzero &&
9238 isa<ConstantSDNode>(LHS.getOperand(1)) &&
9239 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
9241 LHS = LHS.getOperand(0);
9243 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9244 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
9245 Intrinsic::ppc_is_decremented_ctr_nonzero &&
9246 isa<ConstantSDNode>(RHS)) {
9247 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
9248 "Counter decrement comparison is not EQ or NE");
9250 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
9251 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
9252 (CC == ISD::SETNE && !Val);
9254 // We now need to make the intrinsic dead (it cannot be instruction
9256 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
9257 assert(LHS.getNode()->hasOneUse() &&
9258 "Counter decrement has more than one use");
9260 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
9261 N->getOperand(0), N->getOperand(4));
9267 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
9268 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
9269 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
9270 assert(isDot && "Can't compare against a vector result!");
9272 // If this is a comparison against something other than 0/1, then we know
9273 // that the condition is never/always true.
9274 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
9275 if (Val != 0 && Val != 1) {
9276 if (CC == ISD::SETEQ) // Cond never true, remove branch.
9277 return N->getOperand(0);
9278 // Always !=, turn it into an unconditional branch.
9279 return DAG.getNode(ISD::BR, dl, MVT::Other,
9280 N->getOperand(0), N->getOperand(4));
9283 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
9285 // Create the PPCISD altivec 'dot' comparison node.
9287 LHS.getOperand(2), // LHS of compare
9288 LHS.getOperand(3), // RHS of compare
9289 DAG.getConstant(CompareOpc, MVT::i32)
9291 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
9292 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
9294 // Unpack the result based on how the target uses it.
9295 PPC::Predicate CompOpc;
9296 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
9297 default: // Can't happen, don't crash on invalid number though.
9298 case 0: // Branch on the value of the EQ bit of CR6.
9299 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
9301 case 1: // Branch on the inverted value of the EQ bit of CR6.
9302 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
9304 case 2: // Branch on the value of the LT bit of CR6.
9305 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
9307 case 3: // Branch on the inverted value of the LT bit of CR6.
9308 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
9312 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
9313 DAG.getConstant(CompOpc, MVT::i32),
9314 DAG.getRegister(PPC::CR6, MVT::i32),
9315 N->getOperand(4), CompNode.getValue(1));
9325 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
9327 std::vector<SDNode *> *Created) const {
9328 // fold (sdiv X, pow2)
9329 EVT VT = N->getValueType(0);
9330 if (VT == MVT::i64 && !Subtarget.isPPC64())
9332 if ((VT != MVT::i32 && VT != MVT::i64) ||
9333 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
9337 SDValue N0 = N->getOperand(0);
9339 bool IsNegPow2 = (-Divisor).isPowerOf2();
9340 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
9341 SDValue ShiftAmt = DAG.getConstant(Lg2, VT);
9343 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
9345 Created->push_back(Op.getNode());
9348 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), Op);
9350 Created->push_back(Op.getNode());
9356 //===----------------------------------------------------------------------===//
9357 // Inline Assembly Support
9358 //===----------------------------------------------------------------------===//
9360 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
9363 const SelectionDAG &DAG,
9364 unsigned Depth) const {
9365 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
9366 switch (Op.getOpcode()) {
9368 case PPCISD::LBRX: {
9369 // lhbrx is known to have the top bits cleared out.
9370 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
9371 KnownZero = 0xFFFF0000;
9374 case ISD::INTRINSIC_WO_CHAIN: {
9375 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
9377 case Intrinsic::ppc_altivec_vcmpbfp_p:
9378 case Intrinsic::ppc_altivec_vcmpeqfp_p:
9379 case Intrinsic::ppc_altivec_vcmpequb_p:
9380 case Intrinsic::ppc_altivec_vcmpequh_p:
9381 case Intrinsic::ppc_altivec_vcmpequw_p:
9382 case Intrinsic::ppc_altivec_vcmpgefp_p:
9383 case Intrinsic::ppc_altivec_vcmpgtfp_p:
9384 case Intrinsic::ppc_altivec_vcmpgtsb_p:
9385 case Intrinsic::ppc_altivec_vcmpgtsh_p:
9386 case Intrinsic::ppc_altivec_vcmpgtsw_p:
9387 case Intrinsic::ppc_altivec_vcmpgtub_p:
9388 case Intrinsic::ppc_altivec_vcmpgtuh_p:
9389 case Intrinsic::ppc_altivec_vcmpgtuw_p:
9390 KnownZero = ~1U; // All bits but the low one are known to be zero.
9397 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
9398 switch (Subtarget.getDarwinDirective()) {
9403 case PPC::DIR_PWR5X:
9405 case PPC::DIR_PWR6X:
9407 case PPC::DIR_PWR8: {
9411 const PPCInstrInfo *TII =
9412 static_cast<const PPCInstrInfo *>(getTargetMachine().getSubtargetImpl()->
9415 // For small loops (between 5 and 8 instructions), align to a 32-byte
9416 // boundary so that the entire loop fits in one instruction-cache line.
9417 uint64_t LoopSize = 0;
9418 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
9419 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
9420 LoopSize += TII->GetInstSizeInBytes(J);
9422 if (LoopSize > 16 && LoopSize <= 32)
9429 return TargetLowering::getPrefLoopAlignment(ML);
9432 /// getConstraintType - Given a constraint, return the type of
9433 /// constraint it is for this target.
9434 PPCTargetLowering::ConstraintType
9435 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
9436 if (Constraint.size() == 1) {
9437 switch (Constraint[0]) {
9444 return C_RegisterClass;
9446 // FIXME: While Z does indicate a memory constraint, it specifically
9447 // indicates an r+r address (used in conjunction with the 'y' modifier
9448 // in the replacement string). Currently, we're forcing the base
9449 // register to be r0 in the asm printer (which is interpreted as zero)
9450 // and forming the complete address in the second register. This is
9454 } else if (Constraint == "wc") { // individual CR bits.
9455 return C_RegisterClass;
9456 } else if (Constraint == "wa" || Constraint == "wd" ||
9457 Constraint == "wf" || Constraint == "ws") {
9458 return C_RegisterClass; // VSX registers.
9460 return TargetLowering::getConstraintType(Constraint);
9463 /// Examine constraint type and operand type and determine a weight value.
9464 /// This object must already have been set up with the operand type
9465 /// and the current alternative constraint selected.
9466 TargetLowering::ConstraintWeight
9467 PPCTargetLowering::getSingleConstraintMatchWeight(
9468 AsmOperandInfo &info, const char *constraint) const {
9469 ConstraintWeight weight = CW_Invalid;
9470 Value *CallOperandVal = info.CallOperandVal;
9471 // If we don't have a value, we can't do a match,
9472 // but allow it at the lowest weight.
9473 if (!CallOperandVal)
9475 Type *type = CallOperandVal->getType();
9477 // Look at the constraint type.
9478 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
9479 return CW_Register; // an individual CR bit.
9480 else if ((StringRef(constraint) == "wa" ||
9481 StringRef(constraint) == "wd" ||
9482 StringRef(constraint) == "wf") &&
9485 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
9488 switch (*constraint) {
9490 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
9493 if (type->isIntegerTy())
9494 weight = CW_Register;
9497 if (type->isFloatTy())
9498 weight = CW_Register;
9501 if (type->isDoubleTy())
9502 weight = CW_Register;
9505 if (type->isVectorTy())
9506 weight = CW_Register;
9509 weight = CW_Register;
9518 std::pair<unsigned, const TargetRegisterClass*>
9519 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9521 if (Constraint.size() == 1) {
9522 // GCC RS6000 Constraint Letters
9523 switch (Constraint[0]) {
9525 if (VT == MVT::i64 && Subtarget.isPPC64())
9526 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
9527 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
9529 if (VT == MVT::i64 && Subtarget.isPPC64())
9530 return std::make_pair(0U, &PPC::G8RCRegClass);
9531 return std::make_pair(0U, &PPC::GPRCRegClass);
9533 if (VT == MVT::f32 || VT == MVT::i32)
9534 return std::make_pair(0U, &PPC::F4RCRegClass);
9535 if (VT == MVT::f64 || VT == MVT::i64)
9536 return std::make_pair(0U, &PPC::F8RCRegClass);
9539 return std::make_pair(0U, &PPC::VRRCRegClass);
9541 return std::make_pair(0U, &PPC::CRRCRegClass);
9543 } else if (Constraint == "wc") { // an individual CR bit.
9544 return std::make_pair(0U, &PPC::CRBITRCRegClass);
9545 } else if (Constraint == "wa" || Constraint == "wd" ||
9546 Constraint == "wf") {
9547 return std::make_pair(0U, &PPC::VSRCRegClass);
9548 } else if (Constraint == "ws") {
9549 return std::make_pair(0U, &PPC::VSFRCRegClass);
9552 std::pair<unsigned, const TargetRegisterClass*> R =
9553 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9555 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
9556 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
9557 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
9559 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
9560 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
9561 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
9562 PPC::GPRCRegClass.contains(R.first)) {
9563 const TargetRegisterInfo *TRI =
9564 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
9565 return std::make_pair(TRI->getMatchingSuperReg(R.first,
9566 PPC::sub_32, &PPC::G8RCRegClass),
9567 &PPC::G8RCRegClass);
9570 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
9571 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
9573 R.second = &PPC::CRRCRegClass;
9580 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9581 /// vector. If it is invalid, don't add anything to Ops.
9582 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9583 std::string &Constraint,
9584 std::vector<SDValue>&Ops,
9585 SelectionDAG &DAG) const {
9588 // Only support length 1 constraints.
9589 if (Constraint.length() > 1) return;
9591 char Letter = Constraint[0];
9602 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
9603 if (!CST) return; // Must be an immediate to match.
9604 int64_t Value = CST->getSExtValue();
9605 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
9606 // numbers are printed as such.
9608 default: llvm_unreachable("Unknown constraint letter!");
9609 case 'I': // "I" is a signed 16-bit constant.
9610 if (isInt<16>(Value))
9611 Result = DAG.getTargetConstant(Value, TCVT);
9613 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
9614 if (isShiftedUInt<16, 16>(Value))
9615 Result = DAG.getTargetConstant(Value, TCVT);
9617 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
9618 if (isShiftedInt<16, 16>(Value))
9619 Result = DAG.getTargetConstant(Value, TCVT);
9621 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
9622 if (isUInt<16>(Value))
9623 Result = DAG.getTargetConstant(Value, TCVT);
9625 case 'M': // "M" is a constant that is greater than 31.
9627 Result = DAG.getTargetConstant(Value, TCVT);
9629 case 'N': // "N" is a positive constant that is an exact power of two.
9630 if (Value > 0 && isPowerOf2_64(Value))
9631 Result = DAG.getTargetConstant(Value, TCVT);
9633 case 'O': // "O" is the constant zero.
9635 Result = DAG.getTargetConstant(Value, TCVT);
9637 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
9638 if (isInt<16>(-Value))
9639 Result = DAG.getTargetConstant(Value, TCVT);
9646 if (Result.getNode()) {
9647 Ops.push_back(Result);
9651 // Handle standard constraint letters.
9652 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9655 // isLegalAddressingMode - Return true if the addressing mode represented
9656 // by AM is legal for this target, for a load/store of the specified type.
9657 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9659 // FIXME: PPC does not allow r+i addressing modes for vectors!
9661 // PPC allows a sign-extended 16-bit immediate field.
9662 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
9665 // No global is ever allowed as a base.
9669 // PPC only support r+r,
9671 case 0: // "r+i" or just "i", depending on HasBaseReg.
9674 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9676 // Otherwise we have r+r or r+i.
9679 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9681 // Allow 2*r as r+r.
9684 // No other scales are supported.
9691 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
9692 SelectionDAG &DAG) const {
9693 MachineFunction &MF = DAG.getMachineFunction();
9694 MachineFrameInfo *MFI = MF.getFrameInfo();
9695 MFI->setReturnAddressIsTaken(true);
9697 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9701 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9703 // Make sure the function does not optimize away the store of the RA to
9705 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9706 FuncInfo->setLRStoreRequired();
9707 bool isPPC64 = Subtarget.isPPC64();
9708 bool isDarwinABI = Subtarget.isDarwinABI();
9711 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9714 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
9715 isPPC64? MVT::i64 : MVT::i32);
9716 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9717 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9719 MachinePointerInfo(), false, false, false, 0);
9722 // Just load the return address off the stack.
9723 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9724 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9725 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9728 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9729 SelectionDAG &DAG) const {
9731 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9733 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9734 bool isPPC64 = PtrVT == MVT::i64;
9736 MachineFunction &MF = DAG.getMachineFunction();
9737 MachineFrameInfo *MFI = MF.getFrameInfo();
9738 MFI->setFrameAddressIsTaken(true);
9740 // Naked functions never have a frame pointer, and so we use r1. For all
9741 // other functions, this decision must be delayed until during PEI.
9743 if (MF.getFunction()->getAttributes().hasAttribute(
9744 AttributeSet::FunctionIndex, Attribute::Naked))
9745 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9747 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9749 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9752 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9753 FrameAddr, MachinePointerInfo(), false, false,
9758 // FIXME? Maybe this could be a TableGen attribute on some registers and
9759 // this table could be generated automatically from RegInfo.
9760 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9762 bool isPPC64 = Subtarget.isPPC64();
9763 bool isDarwinABI = Subtarget.isDarwinABI();
9765 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9766 (!isPPC64 && VT != MVT::i32))
9767 report_fatal_error("Invalid register global variable type");
9769 bool is64Bit = isPPC64 && VT == MVT::i64;
9770 unsigned Reg = StringSwitch<unsigned>(RegName)
9771 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9772 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
9773 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9774 (is64Bit ? PPC::X13 : PPC::R13))
9779 report_fatal_error("Invalid register name global variable");
9783 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9784 // The PowerPC target isn't yet aware of offsets.
9788 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
9790 unsigned Intrinsic) const {
9792 switch (Intrinsic) {
9793 case Intrinsic::ppc_altivec_lvx:
9794 case Intrinsic::ppc_altivec_lvxl:
9795 case Intrinsic::ppc_altivec_lvebx:
9796 case Intrinsic::ppc_altivec_lvehx:
9797 case Intrinsic::ppc_altivec_lvewx:
9798 case Intrinsic::ppc_vsx_lxvd2x:
9799 case Intrinsic::ppc_vsx_lxvw4x: {
9801 switch (Intrinsic) {
9802 case Intrinsic::ppc_altivec_lvebx:
9805 case Intrinsic::ppc_altivec_lvehx:
9808 case Intrinsic::ppc_altivec_lvewx:
9811 case Intrinsic::ppc_vsx_lxvd2x:
9819 Info.opc = ISD::INTRINSIC_W_CHAIN;
9821 Info.ptrVal = I.getArgOperand(0);
9822 Info.offset = -VT.getStoreSize()+1;
9823 Info.size = 2*VT.getStoreSize()-1;
9826 Info.readMem = true;
9827 Info.writeMem = false;
9830 case Intrinsic::ppc_altivec_stvx:
9831 case Intrinsic::ppc_altivec_stvxl:
9832 case Intrinsic::ppc_altivec_stvebx:
9833 case Intrinsic::ppc_altivec_stvehx:
9834 case Intrinsic::ppc_altivec_stvewx:
9835 case Intrinsic::ppc_vsx_stxvd2x:
9836 case Intrinsic::ppc_vsx_stxvw4x: {
9838 switch (Intrinsic) {
9839 case Intrinsic::ppc_altivec_stvebx:
9842 case Intrinsic::ppc_altivec_stvehx:
9845 case Intrinsic::ppc_altivec_stvewx:
9848 case Intrinsic::ppc_vsx_stxvd2x:
9856 Info.opc = ISD::INTRINSIC_VOID;
9858 Info.ptrVal = I.getArgOperand(1);
9859 Info.offset = -VT.getStoreSize()+1;
9860 Info.size = 2*VT.getStoreSize()-1;
9863 Info.readMem = false;
9864 Info.writeMem = true;
9874 /// getOptimalMemOpType - Returns the target specific optimal type for load
9875 /// and store operations as a result of memset, memcpy, and memmove
9876 /// lowering. If DstAlign is zero that means it's safe to destination
9877 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9878 /// means there isn't a need to check it against alignment requirement,
9879 /// probably because the source does not need to be loaded. If 'IsMemset' is
9880 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9881 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9882 /// source is constant so it does not need to be loaded.
9883 /// It returns EVT::Other if the type should be determined using generic
9884 /// target-independent logic.
9885 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9886 unsigned DstAlign, unsigned SrcAlign,
9887 bool IsMemset, bool ZeroMemset,
9889 MachineFunction &MF) const {
9890 if (Subtarget.isPPC64()) {
9897 /// \brief Returns true if it is beneficial to convert a load of a constant
9898 /// to just the constant itself.
9899 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9901 assert(Ty->isIntegerTy());
9903 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9904 if (BitSize == 0 || BitSize > 64)
9909 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9910 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9912 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9913 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9914 return NumBits1 == 64 && NumBits2 == 32;
9917 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9918 if (!VT1.isInteger() || !VT2.isInteger())
9920 unsigned NumBits1 = VT1.getSizeInBits();
9921 unsigned NumBits2 = VT2.getSizeInBits();
9922 return NumBits1 == 64 && NumBits2 == 32;
9925 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
9926 // Generally speaking, zexts are not free, but they are free when they can be
9927 // folded with other operations.
9928 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
9929 EVT MemVT = LD->getMemoryVT();
9930 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
9931 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
9932 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
9933 LD->getExtensionType() == ISD::ZEXTLOAD))
9937 // FIXME: Add other cases...
9938 // - 32-bit shifts with a zext to i64
9939 // - zext after ctlz, bswap, etc.
9940 // - zext after and by a constant mask
9942 return TargetLowering::isZExtFree(Val, VT2);
9945 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
9946 assert(VT.isFloatingPoint());
9950 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9951 return isInt<16>(Imm) || isUInt<16>(Imm);
9954 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9955 return isInt<16>(Imm) || isUInt<16>(Imm);
9958 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9962 if (DisablePPCUnaligned)
9965 // PowerPC supports unaligned memory access for simple non-vector types.
9966 // Although accessing unaligned addresses is not as efficient as accessing
9967 // aligned addresses, it is generally more efficient than manual expansion,
9968 // and generally only traps for software emulation when crossing page
9974 if (VT.getSimpleVT().isVector()) {
9975 if (Subtarget.hasVSX()) {
9976 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
9977 VT != MVT::v4f32 && VT != MVT::v4i32)
9984 if (VT == MVT::ppcf128)
9993 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9994 VT = VT.getScalarType();
9999 switch (VT.getSimpleVT().SimpleTy) {
10011 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
10012 // LR is a callee-save register, but we must treat it as clobbered by any call
10013 // site. Hence we include LR in the scratch registers, which are in turn added
10014 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
10015 // to CTR, which is used by any indirect call.
10016 static const MCPhysReg ScratchRegs[] = {
10017 PPC::X12, PPC::LR8, PPC::CTR8, 0
10020 return ScratchRegs;
10024 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
10025 EVT VT , unsigned DefinedValues) const {
10026 if (VT == MVT::v2i64)
10029 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
10032 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
10033 if (DisableILPPref || Subtarget.enableMachineScheduler())
10034 return TargetLowering::getSchedulingPreference(N);
10039 // Create a fast isel object.
10041 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
10042 const TargetLibraryInfo *LibInfo) const {
10043 return PPC::createFastISel(FuncInfo, LibInfo);