1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/Function.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Target/TargetLoweringObjectFile.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/DerivedTypes.h"
41 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
42 CCValAssign::LocInfo &LocInfo,
43 ISD::ArgFlagsTy &ArgFlags,
45 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT,
47 CCValAssign::LocInfo &LocInfo,
48 ISD::ArgFlagsTy &ArgFlags,
50 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT,
52 CCValAssign::LocInfo &LocInfo,
53 ISD::ArgFlagsTy &ArgFlags,
56 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
57 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
60 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
61 if (TM.getSubtargetImpl()->isDarwin())
62 return new TargetLoweringObjectFileMachO();
63 return new TargetLoweringObjectFileELF();
67 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
72 // Use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(true);
76 // Set up the register classes.
77 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
78 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
79 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
81 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
82 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
85 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
87 // PowerPC has pre-inc load and store's.
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
99 // This is used in the ppcf128->int sequence. Note it has different semantics
100 // from FP_ROUND: that rounds to nearest, this rounds to zero.
101 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
103 // PowerPC has no SREM/UREM instructions
104 setOperationAction(ISD::SREM, MVT::i32, Expand);
105 setOperationAction(ISD::UREM, MVT::i32, Expand);
106 setOperationAction(ISD::SREM, MVT::i64, Expand);
107 setOperationAction(ISD::UREM, MVT::i64, Expand);
109 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
110 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
111 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
112 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
113 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
114 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
115 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
116 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
117 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
119 // We don't support sin/cos/sqrt/fmod/pow
120 setOperationAction(ISD::FSIN , MVT::f64, Expand);
121 setOperationAction(ISD::FCOS , MVT::f64, Expand);
122 setOperationAction(ISD::FREM , MVT::f64, Expand);
123 setOperationAction(ISD::FPOW , MVT::f64, Expand);
124 setOperationAction(ISD::FSIN , MVT::f32, Expand);
125 setOperationAction(ISD::FCOS , MVT::f32, Expand);
126 setOperationAction(ISD::FREM , MVT::f32, Expand);
127 setOperationAction(ISD::FPOW , MVT::f32, Expand);
129 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
131 // If we're enabling GP optimizations, use hardware square root
132 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
133 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
134 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
137 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
138 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
140 // PowerPC does not have BSWAP, CTPOP or CTTZ
141 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
142 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
143 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
144 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
145 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
146 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
148 // PowerPC does not have ROTR
149 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
150 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
152 // PowerPC does not have Select
153 setOperationAction(ISD::SELECT, MVT::i32, Expand);
154 setOperationAction(ISD::SELECT, MVT::i64, Expand);
155 setOperationAction(ISD::SELECT, MVT::f32, Expand);
156 setOperationAction(ISD::SELECT, MVT::f64, Expand);
158 // PowerPC wants to turn select_cc of FP into fsel when possible.
159 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
160 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
162 // PowerPC wants to optimize integer setcc a bit
163 setOperationAction(ISD::SETCC, MVT::i32, Custom);
165 // PowerPC does not have BRCOND which requires SetCC
166 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
168 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
170 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
171 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
173 // PowerPC does not have [U|S]INT_TO_FP
174 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
175 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
177 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
178 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
179 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
180 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
182 // We cannot sextinreg(i1). Expand to shifts.
183 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
185 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
186 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
187 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
188 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
191 // We want to legalize GlobalAddress and ConstantPool nodes into the
192 // appropriate instructions to materialize the address.
193 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
194 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
195 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
196 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
197 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
198 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
199 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
200 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
201 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
202 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
205 setOperationAction(ISD::TRAP, MVT::Other, Legal);
207 // TRAMPOLINE is custom lowered.
208 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
210 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
211 setOperationAction(ISD::VASTART , MVT::Other, Custom);
213 // VAARG is custom lowered with the 32-bit SVR4 ABI.
214 if ( TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
215 && !TM.getSubtarget<PPCSubtarget>().isPPC64())
216 setOperationAction(ISD::VAARG, MVT::Other, Custom);
218 setOperationAction(ISD::VAARG, MVT::Other, Expand);
220 // Use the default implementation.
221 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
222 setOperationAction(ISD::VAEND , MVT::Other, Expand);
223 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
224 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
225 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
226 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
228 // We want to custom lower some of our intrinsics.
229 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
231 // Comparisons that require checking two conditions.
232 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
233 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
234 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
235 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
236 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
237 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
238 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
239 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
240 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
243 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
245 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
246 // They also have instructions for converting between i64 and fp.
247 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
248 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
249 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
250 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
251 // This is just the low 32 bits of a (signed) fp->i64 conversion.
252 // We cannot do this with Promote because i64 is not a legal type.
253 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
255 // FIXME: disable this lowered code. This generates 64-bit register values,
256 // and we don't model the fact that the top part is clobbered by calls. We
257 // need to flag these together so that the value isn't live across a call.
258 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
260 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
261 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
264 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
265 // 64-bit PowerPC implementations can support i64 types directly
266 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
267 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
268 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
269 // 64-bit PowerPC wants to expand i128 shifts itself.
270 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
271 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
272 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
274 // 32-bit PowerPC wants to expand i64 shifts itself.
275 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
276 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
277 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
280 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
281 // First set operation action for all vector types to expand. Then we
282 // will selectively turn on ones that can be effectively codegen'd.
283 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
284 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
285 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
287 // add/sub are legal for all supported vector VT's.
288 setOperationAction(ISD::ADD , VT, Legal);
289 setOperationAction(ISD::SUB , VT, Legal);
291 // We promote all shuffles to v16i8.
292 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
293 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
295 // We promote all non-typed operations to v4i32.
296 setOperationAction(ISD::AND , VT, Promote);
297 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
298 setOperationAction(ISD::OR , VT, Promote);
299 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
300 setOperationAction(ISD::XOR , VT, Promote);
301 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
302 setOperationAction(ISD::LOAD , VT, Promote);
303 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
304 setOperationAction(ISD::SELECT, VT, Promote);
305 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
306 setOperationAction(ISD::STORE, VT, Promote);
307 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
309 // No other operations are legal.
310 setOperationAction(ISD::MUL , VT, Expand);
311 setOperationAction(ISD::SDIV, VT, Expand);
312 setOperationAction(ISD::SREM, VT, Expand);
313 setOperationAction(ISD::UDIV, VT, Expand);
314 setOperationAction(ISD::UREM, VT, Expand);
315 setOperationAction(ISD::FDIV, VT, Expand);
316 setOperationAction(ISD::FNEG, VT, Expand);
317 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
318 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
319 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
320 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
321 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
322 setOperationAction(ISD::UDIVREM, VT, Expand);
323 setOperationAction(ISD::SDIVREM, VT, Expand);
324 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
325 setOperationAction(ISD::FPOW, VT, Expand);
326 setOperationAction(ISD::CTPOP, VT, Expand);
327 setOperationAction(ISD::CTLZ, VT, Expand);
328 setOperationAction(ISD::CTTZ, VT, Expand);
331 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
332 // with merges, splats, etc.
333 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
335 setOperationAction(ISD::AND , MVT::v4i32, Legal);
336 setOperationAction(ISD::OR , MVT::v4i32, Legal);
337 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
338 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
339 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
340 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
342 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
343 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
344 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
345 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
347 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
348 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
349 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
350 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
352 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
353 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
355 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
356 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
357 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
358 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
361 setShiftAmountType(MVT::i32);
362 setBooleanContents(ZeroOrOneBooleanContent);
364 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
365 setStackPointerRegisterToSaveRestore(PPC::X1);
366 setExceptionPointerRegister(PPC::X3);
367 setExceptionSelectorRegister(PPC::X4);
369 setStackPointerRegisterToSaveRestore(PPC::R1);
370 setExceptionPointerRegister(PPC::R3);
371 setExceptionSelectorRegister(PPC::R4);
374 // We have target-specific dag combine patterns for the following nodes:
375 setTargetDAGCombine(ISD::SINT_TO_FP);
376 setTargetDAGCombine(ISD::STORE);
377 setTargetDAGCombine(ISD::BR_CC);
378 setTargetDAGCombine(ISD::BSWAP);
380 // Darwin long double math library functions have $LDBL128 appended.
381 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
382 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
383 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
384 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
385 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
386 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
387 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
388 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
389 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
390 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
391 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
394 computeRegisterProperties();
397 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
398 /// function arguments in the caller parameter area.
399 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
400 TargetMachine &TM = getTargetMachine();
401 // Darwin passes everything on 4 byte boundary.
402 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
408 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
411 case PPCISD::FSEL: return "PPCISD::FSEL";
412 case PPCISD::FCFID: return "PPCISD::FCFID";
413 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
414 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
415 case PPCISD::STFIWX: return "PPCISD::STFIWX";
416 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
417 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
418 case PPCISD::VPERM: return "PPCISD::VPERM";
419 case PPCISD::Hi: return "PPCISD::Hi";
420 case PPCISD::Lo: return "PPCISD::Lo";
421 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
422 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
423 case PPCISD::LOAD: return "PPCISD::LOAD";
424 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
425 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
426 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
427 case PPCISD::SRL: return "PPCISD::SRL";
428 case PPCISD::SRA: return "PPCISD::SRA";
429 case PPCISD::SHL: return "PPCISD::SHL";
430 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
431 case PPCISD::STD_32: return "PPCISD::STD_32";
432 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4";
433 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin";
434 case PPCISD::NOP: return "PPCISD::NOP";
435 case PPCISD::MTCTR: return "PPCISD::MTCTR";
436 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin";
437 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4";
438 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
439 case PPCISD::MFCR: return "PPCISD::MFCR";
440 case PPCISD::VCMP: return "PPCISD::VCMP";
441 case PPCISD::VCMPo: return "PPCISD::VCMPo";
442 case PPCISD::LBRX: return "PPCISD::LBRX";
443 case PPCISD::STBRX: return "PPCISD::STBRX";
444 case PPCISD::LARX: return "PPCISD::LARX";
445 case PPCISD::STCX: return "PPCISD::STCX";
446 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
447 case PPCISD::MFFS: return "PPCISD::MFFS";
448 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
449 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
450 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
451 case PPCISD::MTFSF: return "PPCISD::MTFSF";
452 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
456 MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const {
460 /// getFunctionAlignment - Return the Log2 alignment of this function.
461 unsigned PPCTargetLowering::getFunctionAlignment(const Function *F) const {
462 if (getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin())
463 return F->hasFnAttr(Attribute::OptimizeForSize) ? 2 : 4;
468 //===----------------------------------------------------------------------===//
469 // Node matching predicates, for use by the tblgen matching code.
470 //===----------------------------------------------------------------------===//
472 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
473 static bool isFloatingPointZero(SDValue Op) {
474 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
475 return CFP->getValueAPF().isZero();
476 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
477 // Maybe this has already been legalized into the constant pool?
478 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
479 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
480 return CFP->getValueAPF().isZero();
485 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
486 /// true if Op is undef or if it matches the specified value.
487 static bool isConstantOrUndef(int Op, int Val) {
488 return Op < 0 || Op == Val;
491 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
492 /// VPKUHUM instruction.
493 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
495 for (unsigned i = 0; i != 16; ++i)
496 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
499 for (unsigned i = 0; i != 8; ++i)
500 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
501 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
507 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
508 /// VPKUWUM instruction.
509 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
511 for (unsigned i = 0; i != 16; i += 2)
512 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
513 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
516 for (unsigned i = 0; i != 8; i += 2)
517 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
518 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
519 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
520 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
526 /// isVMerge - Common function, used to match vmrg* shuffles.
528 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
529 unsigned LHSStart, unsigned RHSStart) {
530 assert(N->getValueType(0) == MVT::v16i8 &&
531 "PPC only supports shuffles by bytes!");
532 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
533 "Unsupported merge size!");
535 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
536 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
537 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
538 LHSStart+j+i*UnitSize) ||
539 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
540 RHSStart+j+i*UnitSize))
546 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
547 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
548 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
551 return isVMerge(N, UnitSize, 8, 24);
552 return isVMerge(N, UnitSize, 8, 8);
555 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
556 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
557 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
560 return isVMerge(N, UnitSize, 0, 16);
561 return isVMerge(N, UnitSize, 0, 0);
565 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
566 /// amount, otherwise return -1.
567 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
568 assert(N->getValueType(0) == MVT::v16i8 &&
569 "PPC only supports shuffles by bytes!");
571 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
573 // Find the first non-undef value in the shuffle mask.
575 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
578 if (i == 16) return -1; // all undef.
580 // Otherwise, check to see if the rest of the elements are consecutively
581 // numbered from this value.
582 unsigned ShiftAmt = SVOp->getMaskElt(i);
583 if (ShiftAmt < i) return -1;
587 // Check the rest of the elements to see if they are consecutive.
588 for (++i; i != 16; ++i)
589 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
592 // Check the rest of the elements to see if they are consecutive.
593 for (++i; i != 16; ++i)
594 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
600 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
601 /// specifies a splat of a single element that is suitable for input to
602 /// VSPLTB/VSPLTH/VSPLTW.
603 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
604 assert(N->getValueType(0) == MVT::v16i8 &&
605 (EltSize == 1 || EltSize == 2 || EltSize == 4));
607 // This is a splat operation if each element of the permute is the same, and
608 // if the value doesn't reference the second vector.
609 unsigned ElementBase = N->getMaskElt(0);
611 // FIXME: Handle UNDEF elements too!
612 if (ElementBase >= 16)
615 // Check that the indices are consecutive, in the case of a multi-byte element
616 // splatted with a v16i8 mask.
617 for (unsigned i = 1; i != EltSize; ++i)
618 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
621 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
622 if (N->getMaskElt(i) < 0) continue;
623 for (unsigned j = 0; j != EltSize; ++j)
624 if (N->getMaskElt(i+j) != N->getMaskElt(j))
630 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
632 bool PPC::isAllNegativeZeroVector(SDNode *N) {
633 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
635 APInt APVal, APUndef;
639 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
640 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
641 return CFP->getValueAPF().isNegZero();
646 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
647 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
648 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
649 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
650 assert(isSplatShuffleMask(SVOp, EltSize));
651 return SVOp->getMaskElt(0) / EltSize;
654 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
655 /// by using a vspltis[bhw] instruction of the specified element size, return
656 /// the constant being splatted. The ByteSize field indicates the number of
657 /// bytes of each element [124] -> [bhw].
658 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
661 // If ByteSize of the splat is bigger than the element size of the
662 // build_vector, then we have a case where we are checking for a splat where
663 // multiple elements of the buildvector are folded together into a single
664 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
665 unsigned EltSize = 16/N->getNumOperands();
666 if (EltSize < ByteSize) {
667 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
668 SDValue UniquedVals[4];
669 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
671 // See if all of the elements in the buildvector agree across.
672 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
673 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
674 // If the element isn't a constant, bail fully out.
675 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
678 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
679 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
680 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
681 return SDValue(); // no match.
684 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
685 // either constant or undef values that are identical for each chunk. See
686 // if these chunks can form into a larger vspltis*.
688 // Check to see if all of the leading entries are either 0 or -1. If
689 // neither, then this won't fit into the immediate field.
690 bool LeadingZero = true;
691 bool LeadingOnes = true;
692 for (unsigned i = 0; i != Multiple-1; ++i) {
693 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
695 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
696 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
698 // Finally, check the least significant entry.
700 if (UniquedVals[Multiple-1].getNode() == 0)
701 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
702 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
704 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
707 if (UniquedVals[Multiple-1].getNode() == 0)
708 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
709 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
710 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
711 return DAG.getTargetConstant(Val, MVT::i32);
717 // Check to see if this buildvec has a single non-undef value in its elements.
718 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
719 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
720 if (OpVal.getNode() == 0)
721 OpVal = N->getOperand(i);
722 else if (OpVal != N->getOperand(i))
726 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
728 unsigned ValSizeInBytes = EltSize;
730 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
731 Value = CN->getZExtValue();
732 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
733 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
734 Value = FloatToBits(CN->getValueAPF().convertToFloat());
737 // If the splat value is larger than the element value, then we can never do
738 // this splat. The only case that we could fit the replicated bits into our
739 // immediate field for would be zero, and we prefer to use vxor for it.
740 if (ValSizeInBytes < ByteSize) return SDValue();
742 // If the element value is larger than the splat value, cut it in half and
743 // check to see if the two halves are equal. Continue doing this until we
744 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
745 while (ValSizeInBytes > ByteSize) {
746 ValSizeInBytes >>= 1;
748 // If the top half equals the bottom half, we're still ok.
749 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
750 (Value & ((1 << (8*ValSizeInBytes))-1)))
754 // Properly sign extend the value.
755 int ShAmt = (4-ByteSize)*8;
756 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
758 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
759 if (MaskVal == 0) return SDValue();
761 // Finally, if this value fits in a 5 bit sext field, return it
762 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
763 return DAG.getTargetConstant(MaskVal, MVT::i32);
767 //===----------------------------------------------------------------------===//
768 // Addressing Mode Selection
769 //===----------------------------------------------------------------------===//
771 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
772 /// or 64-bit immediate, and if the value can be accurately represented as a
773 /// sign extension from a 16-bit value. If so, this returns true and the
775 static bool isIntS16Immediate(SDNode *N, short &Imm) {
776 if (N->getOpcode() != ISD::Constant)
779 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
780 if (N->getValueType(0) == MVT::i32)
781 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
783 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
785 static bool isIntS16Immediate(SDValue Op, short &Imm) {
786 return isIntS16Immediate(Op.getNode(), Imm);
790 /// SelectAddressRegReg - Given the specified addressed, check to see if it
791 /// can be represented as an indexed [r+r] operation. Returns false if it
792 /// can be more efficiently represented with [r+imm].
793 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
795 SelectionDAG &DAG) const {
797 if (N.getOpcode() == ISD::ADD) {
798 if (isIntS16Immediate(N.getOperand(1), imm))
800 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
803 Base = N.getOperand(0);
804 Index = N.getOperand(1);
806 } else if (N.getOpcode() == ISD::OR) {
807 if (isIntS16Immediate(N.getOperand(1), imm))
808 return false; // r+i can fold it if we can.
810 // If this is an or of disjoint bitfields, we can codegen this as an add
811 // (for better address arithmetic) if the LHS and RHS of the OR are provably
813 APInt LHSKnownZero, LHSKnownOne;
814 APInt RHSKnownZero, RHSKnownOne;
815 DAG.ComputeMaskedBits(N.getOperand(0),
816 APInt::getAllOnesValue(N.getOperand(0)
817 .getValueSizeInBits()),
818 LHSKnownZero, LHSKnownOne);
820 if (LHSKnownZero.getBoolValue()) {
821 DAG.ComputeMaskedBits(N.getOperand(1),
822 APInt::getAllOnesValue(N.getOperand(1)
823 .getValueSizeInBits()),
824 RHSKnownZero, RHSKnownOne);
825 // If all of the bits are known zero on the LHS or RHS, the add won't
827 if (~(LHSKnownZero | RHSKnownZero) == 0) {
828 Base = N.getOperand(0);
829 Index = N.getOperand(1);
838 /// Returns true if the address N can be represented by a base register plus
839 /// a signed 16-bit displacement [r+imm], and if it is not better
840 /// represented as reg+reg.
841 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
843 SelectionDAG &DAG) const {
844 // FIXME dl should come from parent load or store, not from address
845 DebugLoc dl = N.getDebugLoc();
846 // If this can be more profitably realized as r+r, fail.
847 if (SelectAddressRegReg(N, Disp, Base, DAG))
850 if (N.getOpcode() == ISD::ADD) {
852 if (isIntS16Immediate(N.getOperand(1), imm)) {
853 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
854 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
855 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
857 Base = N.getOperand(0);
859 return true; // [r+i]
860 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
861 // Match LOAD (ADD (X, Lo(G))).
862 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
863 && "Cannot handle constant offsets yet!");
864 Disp = N.getOperand(1).getOperand(0); // The global address.
865 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
866 Disp.getOpcode() == ISD::TargetConstantPool ||
867 Disp.getOpcode() == ISD::TargetJumpTable);
868 Base = N.getOperand(0);
869 return true; // [&g+r]
871 } else if (N.getOpcode() == ISD::OR) {
873 if (isIntS16Immediate(N.getOperand(1), imm)) {
874 // If this is an or of disjoint bitfields, we can codegen this as an add
875 // (for better address arithmetic) if the LHS and RHS of the OR are
876 // provably disjoint.
877 APInt LHSKnownZero, LHSKnownOne;
878 DAG.ComputeMaskedBits(N.getOperand(0),
879 APInt::getAllOnesValue(N.getOperand(0)
880 .getValueSizeInBits()),
881 LHSKnownZero, LHSKnownOne);
883 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
884 // If all of the bits are known zero on the LHS or RHS, the add won't
886 Base = N.getOperand(0);
887 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
891 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
892 // Loading from a constant address.
894 // If this address fits entirely in a 16-bit sext immediate field, codegen
897 if (isIntS16Immediate(CN, Imm)) {
898 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
899 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
903 // Handle 32-bit sext immediates with LIS + addr mode.
904 if (CN->getValueType(0) == MVT::i32 ||
905 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
906 int Addr = (int)CN->getZExtValue();
908 // Otherwise, break this down into an LIS + disp.
909 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
911 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
912 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
913 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
918 Disp = DAG.getTargetConstant(0, getPointerTy());
919 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
920 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
923 return true; // [r+0]
926 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
927 /// represented as an indexed [r+r] operation.
928 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
930 SelectionDAG &DAG) const {
931 // Check to see if we can easily represent this as an [r+r] address. This
932 // will fail if it thinks that the address is more profitably represented as
933 // reg+imm, e.g. where imm = 0.
934 if (SelectAddressRegReg(N, Base, Index, DAG))
937 // If the operand is an addition, always emit this as [r+r], since this is
938 // better (for code size, and execution, as the memop does the add for free)
939 // than emitting an explicit add.
940 if (N.getOpcode() == ISD::ADD) {
941 Base = N.getOperand(0);
942 Index = N.getOperand(1);
946 // Otherwise, do it the hard way, using R0 as the base register.
947 Base = DAG.getRegister(PPC::R0, N.getValueType());
952 /// SelectAddressRegImmShift - Returns true if the address N can be
953 /// represented by a base register plus a signed 14-bit displacement
954 /// [r+imm*4]. Suitable for use by STD and friends.
955 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
957 SelectionDAG &DAG) const {
958 // FIXME dl should come from the parent load or store, not the address
959 DebugLoc dl = N.getDebugLoc();
960 // If this can be more profitably realized as r+r, fail.
961 if (SelectAddressRegReg(N, Disp, Base, DAG))
964 if (N.getOpcode() == ISD::ADD) {
966 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
967 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
968 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
969 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
971 Base = N.getOperand(0);
973 return true; // [r+i]
974 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
975 // Match LOAD (ADD (X, Lo(G))).
976 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
977 && "Cannot handle constant offsets yet!");
978 Disp = N.getOperand(1).getOperand(0); // The global address.
979 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
980 Disp.getOpcode() == ISD::TargetConstantPool ||
981 Disp.getOpcode() == ISD::TargetJumpTable);
982 Base = N.getOperand(0);
983 return true; // [&g+r]
985 } else if (N.getOpcode() == ISD::OR) {
987 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
988 // If this is an or of disjoint bitfields, we can codegen this as an add
989 // (for better address arithmetic) if the LHS and RHS of the OR are
990 // provably disjoint.
991 APInt LHSKnownZero, LHSKnownOne;
992 DAG.ComputeMaskedBits(N.getOperand(0),
993 APInt::getAllOnesValue(N.getOperand(0)
994 .getValueSizeInBits()),
995 LHSKnownZero, LHSKnownOne);
996 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
997 // If all of the bits are known zero on the LHS or RHS, the add won't
999 Base = N.getOperand(0);
1000 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1004 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1005 // Loading from a constant address. Verify low two bits are clear.
1006 if ((CN->getZExtValue() & 3) == 0) {
1007 // If this address fits entirely in a 14-bit sext immediate field, codegen
1010 if (isIntS16Immediate(CN, Imm)) {
1011 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1012 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
1016 // Fold the low-part of 32-bit absolute addresses into addr mode.
1017 if (CN->getValueType(0) == MVT::i32 ||
1018 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1019 int Addr = (int)CN->getZExtValue();
1021 // Otherwise, break this down into an LIS + disp.
1022 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1023 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1024 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1025 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1031 Disp = DAG.getTargetConstant(0, getPointerTy());
1032 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1033 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1036 return true; // [r+0]
1040 /// getPreIndexedAddressParts - returns true by value, base pointer and
1041 /// offset pointer and addressing mode by reference if the node's address
1042 /// can be legally represented as pre-indexed load / store address.
1043 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1045 ISD::MemIndexedMode &AM,
1046 SelectionDAG &DAG) const {
1047 // Disabled by default for now.
1048 if (!EnablePPCPreinc) return false;
1052 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1053 Ptr = LD->getBasePtr();
1054 VT = LD->getMemoryVT();
1056 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1058 Ptr = ST->getBasePtr();
1059 VT = ST->getMemoryVT();
1063 // PowerPC doesn't have preinc load/store instructions for vectors.
1067 // TODO: Check reg+reg first.
1069 // LDU/STU use reg+imm*4, others use reg+imm.
1070 if (VT != MVT::i64) {
1072 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1076 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1080 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1081 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1082 // sext i32 to i64 when addr mode is r+i.
1083 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1084 LD->getExtensionType() == ISD::SEXTLOAD &&
1085 isa<ConstantSDNode>(Offset))
1093 //===----------------------------------------------------------------------===//
1094 // LowerOperation implementation
1095 //===----------------------------------------------------------------------===//
1097 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1098 SelectionDAG &DAG) {
1099 EVT PtrVT = Op.getValueType();
1100 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1101 Constant *C = CP->getConstVal();
1102 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1103 SDValue Zero = DAG.getConstant(0, PtrVT);
1104 // FIXME there isn't really any debug info here
1105 DebugLoc dl = Op.getDebugLoc();
1107 const TargetMachine &TM = DAG.getTarget();
1109 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, CPI, Zero);
1110 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, CPI, Zero);
1112 // If this is a non-darwin platform, we don't support non-static relo models
1114 if (TM.getRelocationModel() == Reloc::Static ||
1115 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1116 // Generate non-pic code that has direct accesses to the constant pool.
1117 // The address of the global is just (hi(&g)+lo(&g)).
1118 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1121 if (TM.getRelocationModel() == Reloc::PIC_) {
1122 // With PIC, the first instruction is actually "GR+hi(&G)".
1123 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1124 DAG.getNode(PPCISD::GlobalBaseReg,
1125 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1128 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1132 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
1133 EVT PtrVT = Op.getValueType();
1134 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1135 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1136 SDValue Zero = DAG.getConstant(0, PtrVT);
1137 // FIXME there isn't really any debug loc here
1138 DebugLoc dl = Op.getDebugLoc();
1140 const TargetMachine &TM = DAG.getTarget();
1142 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, JTI, Zero);
1143 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, JTI, Zero);
1145 // If this is a non-darwin platform, we don't support non-static relo models
1147 if (TM.getRelocationModel() == Reloc::Static ||
1148 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1149 // Generate non-pic code that has direct accesses to the constant pool.
1150 // The address of the global is just (hi(&g)+lo(&g)).
1151 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1154 if (TM.getRelocationModel() == Reloc::PIC_) {
1155 // With PIC, the first instruction is actually "GR+hi(&G)".
1156 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1157 DAG.getNode(PPCISD::GlobalBaseReg,
1158 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1161 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1165 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1166 SelectionDAG &DAG) {
1167 llvm_unreachable("TLS not implemented for PPC.");
1168 return SDValue(); // Not reached
1171 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) {
1172 EVT PtrVT = Op.getValueType();
1173 DebugLoc DL = Op.getDebugLoc();
1175 BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1176 SDValue TgtBA = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true);
1177 SDValue Zero = DAG.getConstant(0, PtrVT);
1178 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, TgtBA, Zero);
1179 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, TgtBA, Zero);
1181 // If this is a non-darwin platform, we don't support non-static relo models
1183 const TargetMachine &TM = DAG.getTarget();
1184 if (TM.getRelocationModel() == Reloc::Static ||
1185 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1186 // Generate non-pic code that has direct accesses to globals.
1187 // The address of the global is just (hi(&g)+lo(&g)).
1188 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1191 if (TM.getRelocationModel() == Reloc::PIC_) {
1192 // With PIC, the first instruction is actually "GR+hi(&G)".
1193 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1194 DAG.getNode(PPCISD::GlobalBaseReg,
1195 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1198 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1201 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1202 SelectionDAG &DAG) {
1203 EVT PtrVT = Op.getValueType();
1204 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1205 GlobalValue *GV = GSDN->getGlobal();
1206 SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1207 SDValue Zero = DAG.getConstant(0, PtrVT);
1208 // FIXME there isn't really any debug info here
1209 DebugLoc dl = GSDN->getDebugLoc();
1211 const TargetMachine &TM = DAG.getTarget();
1213 // 64-bit SVR4 ABI code is always position-independent.
1214 // The actual address of the GlobalValue is stored in the TOC.
1215 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1216 return DAG.getNode(PPCISD::TOC_ENTRY, dl, MVT::i64, GA,
1217 DAG.getRegister(PPC::X2, MVT::i64));
1220 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero);
1221 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero);
1223 // If this is a non-darwin platform, we don't support non-static relo models
1225 if (TM.getRelocationModel() == Reloc::Static ||
1226 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1227 // Generate non-pic code that has direct accesses to globals.
1228 // The address of the global is just (hi(&g)+lo(&g)).
1229 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1232 if (TM.getRelocationModel() == Reloc::PIC_) {
1233 // With PIC, the first instruction is actually "GR+hi(&G)".
1234 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1235 DAG.getNode(PPCISD::GlobalBaseReg,
1236 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1239 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1241 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM))
1244 // If the global is weak or external, we have to go through the lazy
1246 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0);
1249 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
1250 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1251 DebugLoc dl = Op.getDebugLoc();
1253 // If we're comparing for equality to zero, expose the fact that this is
1254 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1255 // fold the new nodes.
1256 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1257 if (C->isNullValue() && CC == ISD::SETEQ) {
1258 EVT VT = Op.getOperand(0).getValueType();
1259 SDValue Zext = Op.getOperand(0);
1260 if (VT.bitsLT(MVT::i32)) {
1262 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1264 unsigned Log2b = Log2_32(VT.getSizeInBits());
1265 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1266 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1267 DAG.getConstant(Log2b, MVT::i32));
1268 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1270 // Leave comparisons against 0 and -1 alone for now, since they're usually
1271 // optimized. FIXME: revisit this when we can custom lower all setcc
1273 if (C->isAllOnesValue() || C->isNullValue())
1277 // If we have an integer seteq/setne, turn it into a compare against zero
1278 // by xor'ing the rhs with the lhs, which is faster than setting a
1279 // condition register, reading it back out, and masking the correct bit. The
1280 // normal approach here uses sub to do this instead of xor. Using xor exposes
1281 // the result to other bit-twiddling opportunities.
1282 EVT LHSVT = Op.getOperand(0).getValueType();
1283 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1284 EVT VT = Op.getValueType();
1285 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1287 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1292 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1293 int VarArgsFrameIndex,
1294 int VarArgsStackOffset,
1295 unsigned VarArgsNumGPR,
1296 unsigned VarArgsNumFPR,
1297 const PPCSubtarget &Subtarget) {
1299 llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!");
1300 return SDValue(); // Not reached
1303 SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
1304 SDValue Chain = Op.getOperand(0);
1305 SDValue Trmp = Op.getOperand(1); // trampoline
1306 SDValue FPtr = Op.getOperand(2); // nested function
1307 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1308 DebugLoc dl = Op.getDebugLoc();
1310 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1311 bool isPPC64 = (PtrVT == MVT::i64);
1312 const Type *IntPtrTy =
1313 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType(
1316 TargetLowering::ArgListTy Args;
1317 TargetLowering::ArgListEntry Entry;
1319 Entry.Ty = IntPtrTy;
1320 Entry.Node = Trmp; Args.push_back(Entry);
1322 // TrampSize == (isPPC64 ? 48 : 40);
1323 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1324 isPPC64 ? MVT::i64 : MVT::i32);
1325 Args.push_back(Entry);
1327 Entry.Node = FPtr; Args.push_back(Entry);
1328 Entry.Node = Nest; Args.push_back(Entry);
1330 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1331 std::pair<SDValue, SDValue> CallResult =
1332 LowerCallTo(Chain, Op.getValueType().getTypeForEVT(*DAG.getContext()),
1333 false, false, false, false, 0, CallingConv::C, false,
1334 /*isReturnValueUsed=*/true,
1335 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1336 Args, DAG, dl, DAG.GetOrdering(Chain.getNode()));
1339 { CallResult.first, CallResult.second };
1341 return DAG.getMergeValues(Ops, 2, dl);
1344 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1345 int VarArgsFrameIndex,
1346 int VarArgsStackOffset,
1347 unsigned VarArgsNumGPR,
1348 unsigned VarArgsNumFPR,
1349 const PPCSubtarget &Subtarget) {
1350 DebugLoc dl = Op.getDebugLoc();
1352 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1353 // vastart just stores the address of the VarArgsFrameIndex slot into the
1354 // memory location argument.
1355 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1356 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1357 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1358 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1361 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1362 // We suppose the given va_list is already allocated.
1365 // char gpr; /* index into the array of 8 GPRs
1366 // * stored in the register save area
1367 // * gpr=0 corresponds to r3,
1368 // * gpr=1 to r4, etc.
1370 // char fpr; /* index into the array of 8 FPRs
1371 // * stored in the register save area
1372 // * fpr=0 corresponds to f1,
1373 // * fpr=1 to f2, etc.
1375 // char *overflow_arg_area;
1376 // /* location on stack that holds
1377 // * the next overflow argument
1379 // char *reg_save_area;
1380 // /* where r3:r10 and f1:f8 (if saved)
1386 SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i32);
1387 SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i32);
1390 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1392 SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1393 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1395 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1396 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1398 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1399 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1401 uint64_t FPROffset = 1;
1402 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1404 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1406 // Store first byte : number of int regs
1407 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1408 Op.getOperand(1), SV, 0, MVT::i8);
1409 uint64_t nextOffset = FPROffset;
1410 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1413 // Store second byte : number of float regs
1414 SDValue secondStore =
1415 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset, MVT::i8);
1416 nextOffset += StackOffset;
1417 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1419 // Store second word : arguments given on stack
1420 SDValue thirdStore =
1421 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset);
1422 nextOffset += FrameOffset;
1423 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1425 // Store third word : arguments given in registers
1426 return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset);
1430 #include "PPCGenCallingConv.inc"
1432 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
1433 CCValAssign::LocInfo &LocInfo,
1434 ISD::ArgFlagsTy &ArgFlags,
1439 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT,
1441 CCValAssign::LocInfo &LocInfo,
1442 ISD::ArgFlagsTy &ArgFlags,
1444 static const unsigned ArgRegs[] = {
1445 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1446 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1448 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1450 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1452 // Skip one register if the first unallocated register has an even register
1453 // number and there are still argument registers available which have not been
1454 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1455 // need to skip a register if RegNum is odd.
1456 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1457 State.AllocateReg(ArgRegs[RegNum]);
1460 // Always return false here, as this function only makes sure that the first
1461 // unallocated register has an odd register number and does not actually
1462 // allocate a register for the current argument.
1466 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT,
1468 CCValAssign::LocInfo &LocInfo,
1469 ISD::ArgFlagsTy &ArgFlags,
1471 static const unsigned ArgRegs[] = {
1472 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1476 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1478 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1480 // If there is only one Floating-point register left we need to put both f64
1481 // values of a split ppc_fp128 value on the stack.
1482 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1483 State.AllocateReg(ArgRegs[RegNum]);
1486 // Always return false here, as this function only makes sure that the two f64
1487 // values a ppc_fp128 value is split into are both passed in registers or both
1488 // passed on the stack and does not actually allocate a register for the
1489 // current argument.
1493 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1495 static const unsigned *GetFPR() {
1496 static const unsigned FPR[] = {
1497 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1498 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1504 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1506 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1507 unsigned PtrByteSize) {
1508 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1509 if (Flags.isByVal())
1510 ArgSize = Flags.getByValSize();
1511 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1517 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1518 CallingConv::ID CallConv, bool isVarArg,
1519 const SmallVectorImpl<ISD::InputArg>
1521 DebugLoc dl, SelectionDAG &DAG,
1522 SmallVectorImpl<SDValue> &InVals) {
1523 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
1524 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins,
1527 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1533 PPCTargetLowering::LowerFormalArguments_SVR4(
1535 CallingConv::ID CallConv, bool isVarArg,
1536 const SmallVectorImpl<ISD::InputArg>
1538 DebugLoc dl, SelectionDAG &DAG,
1539 SmallVectorImpl<SDValue> &InVals) {
1541 // 32-bit SVR4 ABI Stack Frame Layout:
1542 // +-----------------------------------+
1543 // +--> | Back chain |
1544 // | +-----------------------------------+
1545 // | | Floating-point register save area |
1546 // | +-----------------------------------+
1547 // | | General register save area |
1548 // | +-----------------------------------+
1549 // | | CR save word |
1550 // | +-----------------------------------+
1551 // | | VRSAVE save word |
1552 // | +-----------------------------------+
1553 // | | Alignment padding |
1554 // | +-----------------------------------+
1555 // | | Vector register save area |
1556 // | +-----------------------------------+
1557 // | | Local variable space |
1558 // | +-----------------------------------+
1559 // | | Parameter list area |
1560 // | +-----------------------------------+
1561 // | | LR save word |
1562 // | +-----------------------------------+
1563 // SP--> +--- | Back chain |
1564 // +-----------------------------------+
1567 // System V Application Binary Interface PowerPC Processor Supplement
1568 // AltiVec Technology Programming Interface Manual
1570 MachineFunction &MF = DAG.getMachineFunction();
1571 MachineFrameInfo *MFI = MF.getFrameInfo();
1573 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1574 // Potential tail calls could cause overwriting of argument stack slots.
1575 bool isImmutable = !(PerformTailCallOpt && (CallConv==CallingConv::Fast));
1576 unsigned PtrByteSize = 4;
1578 // Assign locations to all of the incoming arguments.
1579 SmallVector<CCValAssign, 16> ArgLocs;
1580 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1583 // Reserve space for the linkage area on the stack.
1584 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
1586 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4);
1588 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1589 CCValAssign &VA = ArgLocs[i];
1591 // Arguments stored in registers.
1592 if (VA.isRegLoc()) {
1593 TargetRegisterClass *RC;
1594 EVT ValVT = VA.getValVT();
1596 switch (ValVT.getSimpleVT().SimpleTy) {
1598 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1600 RC = PPC::GPRCRegisterClass;
1603 RC = PPC::F4RCRegisterClass;
1606 RC = PPC::F8RCRegisterClass;
1612 RC = PPC::VRRCRegisterClass;
1616 // Transform the arguments stored in physical registers into virtual ones.
1617 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1618 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1620 InVals.push_back(ArgValue);
1622 // Argument stored in memory.
1623 assert(VA.isMemLoc());
1625 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1626 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1627 isImmutable, false);
1629 // Create load nodes to retrieve arguments from the stack.
1630 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1631 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0));
1635 // Assign locations to all of the incoming aggregate by value arguments.
1636 // Aggregates passed by value are stored in the local variable space of the
1637 // caller's stack frame, right above the parameter list area.
1638 SmallVector<CCValAssign, 16> ByValArgLocs;
1639 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(),
1640 ByValArgLocs, *DAG.getContext());
1642 // Reserve stack space for the allocations in CCInfo.
1643 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1645 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal);
1647 // Area that is at least reserved in the caller of this function.
1648 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1650 // Set the size that is at least reserved in caller of this function. Tail
1651 // call optimized function's reserved stack space needs to be aligned so that
1652 // taking the difference between two stack areas will result in an aligned
1654 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1657 std::max(MinReservedArea,
1658 PPCFrameInfo::getMinCallFrameSize(false, false));
1660 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1661 getStackAlignment();
1662 unsigned AlignMask = TargetAlign-1;
1663 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1665 FI->setMinReservedArea(MinReservedArea);
1667 SmallVector<SDValue, 8> MemOps;
1669 // If the function takes variable number of arguments, make a frame index for
1670 // the start of the first vararg value... for expansion of llvm.va_start.
1672 static const unsigned GPArgRegs[] = {
1673 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1674 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1676 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
1678 static const unsigned FPArgRegs[] = {
1679 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1682 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
1684 VarArgsNumGPR = CCInfo.getFirstUnallocated(GPArgRegs, NumGPArgRegs);
1685 VarArgsNumFPR = CCInfo.getFirstUnallocated(FPArgRegs, NumFPArgRegs);
1687 // Make room for NumGPArgRegs and NumFPArgRegs.
1688 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
1689 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
1691 VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1692 CCInfo.getNextStackOffset(),
1695 VarArgsFrameIndex = MFI->CreateStackObject(Depth, 8, false);
1696 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1698 // The fixed integer arguments of a variadic function are
1699 // stored to the VarArgsFrameIndex on the stack.
1700 unsigned GPRIndex = 0;
1701 for (; GPRIndex != VarArgsNumGPR; ++GPRIndex) {
1702 SDValue Val = DAG.getRegister(GPArgRegs[GPRIndex], PtrVT);
1703 SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0);
1704 MemOps.push_back(Store);
1705 // Increment the address by four for the next argument to store
1706 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1707 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1710 // If this function is vararg, store any remaining integer argument regs
1711 // to their spots on the stack so that they may be loaded by deferencing the
1712 // result of va_next.
1713 for (; GPRIndex != NumGPArgRegs; ++GPRIndex) {
1714 unsigned VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
1716 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1717 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1718 MemOps.push_back(Store);
1719 // Increment the address by four for the next argument to store
1720 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1721 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1724 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
1727 // The double arguments are stored to the VarArgsFrameIndex
1729 unsigned FPRIndex = 0;
1730 for (FPRIndex = 0; FPRIndex != VarArgsNumFPR; ++FPRIndex) {
1731 SDValue Val = DAG.getRegister(FPArgRegs[FPRIndex], MVT::f64);
1732 SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0);
1733 MemOps.push_back(Store);
1734 // Increment the address by eight for the next argument to store
1735 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1737 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1740 for (; FPRIndex != NumFPArgRegs; ++FPRIndex) {
1741 unsigned VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
1743 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
1744 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1745 MemOps.push_back(Store);
1746 // Increment the address by eight for the next argument to store
1747 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1749 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1753 if (!MemOps.empty())
1754 Chain = DAG.getNode(ISD::TokenFactor, dl,
1755 MVT::Other, &MemOps[0], MemOps.size());
1761 PPCTargetLowering::LowerFormalArguments_Darwin(
1763 CallingConv::ID CallConv, bool isVarArg,
1764 const SmallVectorImpl<ISD::InputArg>
1766 DebugLoc dl, SelectionDAG &DAG,
1767 SmallVectorImpl<SDValue> &InVals) {
1768 // TODO: add description of PPC stack frame format, or at least some docs.
1770 MachineFunction &MF = DAG.getMachineFunction();
1771 MachineFrameInfo *MFI = MF.getFrameInfo();
1773 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1774 bool isPPC64 = PtrVT == MVT::i64;
1775 // Potential tail calls could cause overwriting of argument stack slots.
1776 bool isImmutable = !(PerformTailCallOpt && (CallConv==CallingConv::Fast));
1777 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1779 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
1780 // Area that is at least reserved in caller of this function.
1781 unsigned MinReservedArea = ArgOffset;
1783 static const unsigned GPR_32[] = { // 32-bit registers.
1784 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1785 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1787 static const unsigned GPR_64[] = { // 64-bit registers.
1788 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1789 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1792 static const unsigned *FPR = GetFPR();
1794 static const unsigned VR[] = {
1795 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1796 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1799 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1800 const unsigned Num_FPR_Regs = 13;
1801 const unsigned Num_VR_Regs = array_lengthof( VR);
1803 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1805 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1807 // In 32-bit non-varargs functions, the stack space for vectors is after the
1808 // stack space for non-vectors. We do not use this space unless we have
1809 // too many vectors to fit in registers, something that only occurs in
1810 // constructed examples:), but we have to walk the arglist to figure
1811 // that out...for the pathological case, compute VecArgOffset as the
1812 // start of the vector parameter area. Computing VecArgOffset is the
1813 // entire point of the following loop.
1814 unsigned VecArgOffset = ArgOffset;
1815 if (!isVarArg && !isPPC64) {
1816 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
1818 EVT ObjectVT = Ins[ArgNo].VT;
1819 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1820 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1822 if (Flags.isByVal()) {
1823 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1824 ObjSize = Flags.getByValSize();
1826 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1827 VecArgOffset += ArgSize;
1831 switch(ObjectVT.getSimpleVT().SimpleTy) {
1832 default: llvm_unreachable("Unhandled argument type!");
1835 VecArgOffset += isPPC64 ? 8 : 4;
1837 case MVT::i64: // PPC64
1845 // Nothing to do, we're only looking at Nonvector args here.
1850 // We've found where the vector parameter area in memory is. Skip the
1851 // first 12 parameters; these don't use that memory.
1852 VecArgOffset = ((VecArgOffset+15)/16)*16;
1853 VecArgOffset += 12*16;
1855 // Add DAG nodes to load the arguments or copy them out of registers. On
1856 // entry to a function on PPC, the arguments start after the linkage area,
1857 // although the first ones are often in registers.
1859 SmallVector<SDValue, 8> MemOps;
1860 unsigned nAltivecParamsAtEnd = 0;
1861 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
1863 bool needsLoad = false;
1864 EVT ObjectVT = Ins[ArgNo].VT;
1865 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1866 unsigned ArgSize = ObjSize;
1867 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1869 unsigned CurArgOffset = ArgOffset;
1871 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1872 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1873 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1874 if (isVarArg || isPPC64) {
1875 MinReservedArea = ((MinReservedArea+15)/16)*16;
1876 MinReservedArea += CalculateStackSlotSize(ObjectVT,
1879 } else nAltivecParamsAtEnd++;
1881 // Calculate min reserved area.
1882 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
1886 // FIXME the codegen can be much improved in some cases.
1887 // We do not have to keep everything in memory.
1888 if (Flags.isByVal()) {
1889 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1890 ObjSize = Flags.getByValSize();
1891 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1892 // Objects of size 1 and 2 are right justified, everything else is
1893 // left justified. This means the memory address is adjusted forwards.
1894 if (ObjSize==1 || ObjSize==2) {
1895 CurArgOffset = CurArgOffset + (4 - ObjSize);
1897 // The value of the object is its address.
1898 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true, false);
1899 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1900 InVals.push_back(FIN);
1901 if (ObjSize==1 || ObjSize==2) {
1902 if (GPR_idx != Num_GPR_Regs) {
1903 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1904 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1905 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
1906 NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
1907 MemOps.push_back(Store);
1911 ArgOffset += PtrByteSize;
1915 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1916 // Store whatever pieces of the object are in registers
1917 // to memory. ArgVal will be address of the beginning of
1919 if (GPR_idx != Num_GPR_Regs) {
1920 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1921 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true, false);
1922 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1923 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1924 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1925 MemOps.push_back(Store);
1927 ArgOffset += PtrByteSize;
1929 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1936 switch (ObjectVT.getSimpleVT().SimpleTy) {
1937 default: llvm_unreachable("Unhandled argument type!");
1940 if (GPR_idx != Num_GPR_Regs) {
1941 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1942 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1946 ArgSize = PtrByteSize;
1948 // All int arguments reserve stack space in the Darwin ABI.
1949 ArgOffset += PtrByteSize;
1953 case MVT::i64: // PPC64
1954 if (GPR_idx != Num_GPR_Regs) {
1955 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
1956 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1958 if (ObjectVT == MVT::i32) {
1959 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1960 // value to MVT::i64 and then truncate to the correct register size.
1962 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
1963 DAG.getValueType(ObjectVT));
1964 else if (Flags.isZExt())
1965 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
1966 DAG.getValueType(ObjectVT));
1968 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
1974 ArgSize = PtrByteSize;
1976 // All int arguments reserve stack space in the Darwin ABI.
1982 // Every 4 bytes of argument space consumes one of the GPRs available for
1983 // argument passing.
1984 if (GPR_idx != Num_GPR_Regs) {
1986 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1989 if (FPR_idx != Num_FPR_Regs) {
1992 if (ObjectVT == MVT::f32)
1993 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
1995 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
1997 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2003 // All FP arguments reserve stack space in the Darwin ABI.
2004 ArgOffset += isPPC64 ? 8 : ObjSize;
2010 // Note that vector arguments in registers don't reserve stack space,
2011 // except in varargs functions.
2012 if (VR_idx != Num_VR_Regs) {
2013 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2014 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2016 while ((ArgOffset % 16) != 0) {
2017 ArgOffset += PtrByteSize;
2018 if (GPR_idx != Num_GPR_Regs)
2022 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2026 if (!isVarArg && !isPPC64) {
2027 // Vectors go after all the nonvectors.
2028 CurArgOffset = VecArgOffset;
2031 // Vectors are aligned.
2032 ArgOffset = ((ArgOffset+15)/16)*16;
2033 CurArgOffset = ArgOffset;
2041 // We need to load the argument to a virtual register if we determined above
2042 // that we ran out of physical registers of the appropriate type.
2044 int FI = MFI->CreateFixedObject(ObjSize,
2045 CurArgOffset + (ArgSize - ObjSize),
2046 isImmutable, false);
2047 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2048 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0);
2051 InVals.push_back(ArgVal);
2054 // Set the size that is at least reserved in caller of this function. Tail
2055 // call optimized function's reserved stack space needs to be aligned so that
2056 // taking the difference between two stack areas will result in an aligned
2058 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2059 // Add the Altivec parameters at the end, if needed.
2060 if (nAltivecParamsAtEnd) {
2061 MinReservedArea = ((MinReservedArea+15)/16)*16;
2062 MinReservedArea += 16*nAltivecParamsAtEnd;
2065 std::max(MinReservedArea,
2066 PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
2067 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
2068 getStackAlignment();
2069 unsigned AlignMask = TargetAlign-1;
2070 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2071 FI->setMinReservedArea(MinReservedArea);
2073 // If the function takes variable number of arguments, make a frame index for
2074 // the start of the first vararg value... for expansion of llvm.va_start.
2076 int Depth = ArgOffset;
2078 VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2079 Depth, true, false);
2080 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
2082 // If this function is vararg, store any remaining integer argument regs
2083 // to their spots on the stack so that they may be loaded by deferencing the
2084 // result of va_next.
2085 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2089 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2091 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2093 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2094 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
2095 MemOps.push_back(Store);
2096 // Increment the address by four for the next argument to store
2097 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2098 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2102 if (!MemOps.empty())
2103 Chain = DAG.getNode(ISD::TokenFactor, dl,
2104 MVT::Other, &MemOps[0], MemOps.size());
2109 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
2110 /// linkage area for the Darwin ABI.
2112 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2116 const SmallVectorImpl<ISD::OutputArg>
2118 unsigned &nAltivecParamsAtEnd) {
2119 // Count how many bytes are to be pushed on the stack, including the linkage
2120 // area, and parameter passing area. We start with 24/48 bytes, which is
2121 // prereserved space for [SP][CR][LR][3 x unused].
2122 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, true);
2123 unsigned NumOps = Outs.size();
2124 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2126 // Add up all the space actually used.
2127 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2128 // they all go in registers, but we must reserve stack space for them for
2129 // possible use by the caller. In varargs or 64-bit calls, parameters are
2130 // assigned stack space in order, with padding so Altivec parameters are
2132 nAltivecParamsAtEnd = 0;
2133 for (unsigned i = 0; i != NumOps; ++i) {
2134 SDValue Arg = Outs[i].Val;
2135 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2136 EVT ArgVT = Arg.getValueType();
2137 // Varargs Altivec parameters are padded to a 16 byte boundary.
2138 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2139 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2140 if (!isVarArg && !isPPC64) {
2141 // Non-varargs Altivec parameters go after all the non-Altivec
2142 // parameters; handle those later so we know how much padding we need.
2143 nAltivecParamsAtEnd++;
2146 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2147 NumBytes = ((NumBytes+15)/16)*16;
2149 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2152 // Allow for Altivec parameters at the end, if needed.
2153 if (nAltivecParamsAtEnd) {
2154 NumBytes = ((NumBytes+15)/16)*16;
2155 NumBytes += 16*nAltivecParamsAtEnd;
2158 // The prolog code of the callee may store up to 8 GPR argument registers to
2159 // the stack, allowing va_start to index over them in memory if its varargs.
2160 // Because we cannot tell if this is needed on the caller side, we have to
2161 // conservatively assume that it is needed. As such, make sure we have at
2162 // least enough stack space for the caller to store the 8 GPRs.
2163 NumBytes = std::max(NumBytes,
2164 PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
2166 // Tail call needs the stack to be aligned.
2167 if (CC==CallingConv::Fast && PerformTailCallOpt) {
2168 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
2169 getStackAlignment();
2170 unsigned AlignMask = TargetAlign-1;
2171 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2177 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2178 /// adjusted to accomodate the arguments for the tailcall.
2179 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2180 unsigned ParamSize) {
2182 if (!isTailCall) return 0;
2184 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2185 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2186 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2187 // Remember only if the new adjustement is bigger.
2188 if (SPDiff < FI->getTailCallSPDelta())
2189 FI->setTailCallSPDelta(SPDiff);
2194 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2195 /// for tail call optimization. Targets which want to do tail call
2196 /// optimization should implement this function.
2198 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2199 CallingConv::ID CalleeCC,
2201 const SmallVectorImpl<ISD::InputArg> &Ins,
2202 SelectionDAG& DAG) const {
2203 // Variable argument functions are not supported.
2207 MachineFunction &MF = DAG.getMachineFunction();
2208 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2209 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2210 // Functions containing by val parameters are not supported.
2211 for (unsigned i = 0; i != Ins.size(); i++) {
2212 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2213 if (Flags.isByVal()) return false;
2216 // Non PIC/GOT tail calls are supported.
2217 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2220 // At the moment we can only do local tail calls (in same module, hidden
2221 // or protected) if we are generating PIC.
2222 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2223 return G->getGlobal()->hasHiddenVisibility()
2224 || G->getGlobal()->hasProtectedVisibility();
2230 /// isCallCompatibleAddress - Return the immediate to use if the specified
2231 /// 32-bit value is representable in the immediate field of a BxA instruction.
2232 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2233 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2236 int Addr = C->getZExtValue();
2237 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2238 (Addr << 6 >> 6) != Addr)
2239 return 0; // Top 6 bits have to be sext of immediate.
2241 return DAG.getConstant((int)C->getZExtValue() >> 2,
2242 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2247 struct TailCallArgumentInfo {
2252 TailCallArgumentInfo() : FrameIdx(0) {}
2257 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2259 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2261 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2262 SmallVector<SDValue, 8> &MemOpChains,
2264 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2265 SDValue Arg = TailCallArgs[i].Arg;
2266 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2267 int FI = TailCallArgs[i].FrameIdx;
2268 // Store relative to framepointer.
2269 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2270 PseudoSourceValue::getFixedStack(FI),
2275 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2276 /// the appropriate stack slot for the tail call optimized function call.
2277 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2278 MachineFunction &MF,
2287 // Calculate the new stack slot for the return address.
2288 int SlotSize = isPPC64 ? 8 : 4;
2289 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
2291 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2294 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2295 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2296 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2297 PseudoSourceValue::getFixedStack(NewRetAddr), 0);
2299 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2300 // slot as the FP is never overwritten.
2303 SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2304 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
2306 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2307 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2308 PseudoSourceValue::getFixedStack(NewFPIdx), 0);
2314 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2315 /// the position of the argument.
2317 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2318 SDValue Arg, int SPDiff, unsigned ArgOffset,
2319 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2320 int Offset = ArgOffset + SPDiff;
2321 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2322 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true,false);
2323 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2324 SDValue FIN = DAG.getFrameIndex(FI, VT);
2325 TailCallArgumentInfo Info;
2327 Info.FrameIdxOp = FIN;
2329 TailCallArguments.push_back(Info);
2332 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2333 /// stack slot. Returns the chain as result and the loaded frame pointers in
2334 /// LROpOut/FPOpout. Used when tail calling.
2335 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2343 // Load the LR and FP stack slot for later adjusting.
2344 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2345 LROpOut = getReturnAddrFrameIndex(DAG);
2346 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0);
2347 Chain = SDValue(LROpOut.getNode(), 1);
2349 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
2350 // slot as the FP is never overwritten.
2352 FPOpOut = getFramePointerFrameIndex(DAG);
2353 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0);
2354 Chain = SDValue(FPOpOut.getNode(), 1);
2360 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2361 /// by "Src" to address "Dst" of size "Size". Alignment information is
2362 /// specified by the specific parameter attribute. The copy will be passed as
2363 /// a byval function parameter.
2364 /// Sometimes what we are copying is the end of a larger object, the part that
2365 /// does not fit in registers.
2367 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2368 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2370 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2371 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2372 false, NULL, 0, NULL, 0);
2375 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2378 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2379 SDValue Arg, SDValue PtrOff, int SPDiff,
2380 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2381 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2382 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments,
2384 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2389 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2391 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2392 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2393 DAG.getConstant(ArgOffset, PtrVT));
2395 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
2396 // Calculate and remember argument location.
2397 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2402 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
2403 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
2404 SDValue LROp, SDValue FPOp, bool isDarwinABI,
2405 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
2406 MachineFunction &MF = DAG.getMachineFunction();
2408 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2409 // might overwrite each other in case of tail call optimization.
2410 SmallVector<SDValue, 8> MemOpChains2;
2411 // Do not flag preceeding copytoreg stuff together with the following stuff.
2413 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2415 if (!MemOpChains2.empty())
2416 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2417 &MemOpChains2[0], MemOpChains2.size());
2419 // Store the return address to the appropriate stack slot.
2420 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2421 isPPC64, isDarwinABI, dl);
2423 // Emit callseq_end just before tailcall node.
2424 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2425 DAG.getIntPtrConstant(0, true), InFlag);
2426 InFlag = Chain.getValue(1);
2430 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
2431 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
2432 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
2433 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
2434 bool isPPC64, bool isSVR4ABI) {
2435 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2436 NodeTys.push_back(MVT::Other); // Returns a chain
2437 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
2439 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
2441 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2442 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2443 // node so that legalize doesn't hack it.
2444 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2445 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
2446 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
2447 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
2448 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
2449 // If this is an absolute destination address, use the munged value.
2450 Callee = SDValue(Dest, 0);
2452 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2453 // to do the call, we can't use PPCISD::CALL.
2454 SDValue MTCTROps[] = {Chain, Callee, InFlag};
2456 if (isSVR4ABI && isPPC64) {
2457 // Function pointers in the 64-bit SVR4 ABI do not point to the function
2458 // entry point, but to the function descriptor (the function entry point
2459 // address is part of the function descriptor though).
2460 // The function descriptor is a three doubleword structure with the
2461 // following fields: function entry point, TOC base address and
2462 // environment pointer.
2463 // Thus for a call through a function pointer, the following actions need
2465 // 1. Save the TOC of the caller in the TOC save area of its stack
2466 // frame (this is done in LowerCall_Darwin()).
2467 // 2. Load the address of the function entry point from the function
2469 // 3. Load the TOC of the callee from the function descriptor into r2.
2470 // 4. Load the environment pointer from the function descriptor into
2472 // 5. Branch to the function entry point address.
2473 // 6. On return of the callee, the TOC of the caller needs to be
2474 // restored (this is done in FinishCall()).
2476 // All those operations are flagged together to ensure that no other
2477 // operations can be scheduled in between. E.g. without flagging the
2478 // operations together, a TOC access in the caller could be scheduled
2479 // between the load of the callee TOC and the branch to the callee, which
2480 // results in the TOC access going through the TOC of the callee instead
2481 // of going through the TOC of the caller, which leads to incorrect code.
2483 // Load the address of the function entry point from the function
2485 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Flag);
2486 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
2487 InFlag.getNode() ? 3 : 2);
2488 Chain = LoadFuncPtr.getValue(1);
2489 InFlag = LoadFuncPtr.getValue(2);
2491 // Load environment pointer into r11.
2492 // Offset of the environment pointer within the function descriptor.
2493 SDValue PtrOff = DAG.getIntPtrConstant(16);
2495 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
2496 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
2498 Chain = LoadEnvPtr.getValue(1);
2499 InFlag = LoadEnvPtr.getValue(2);
2501 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
2503 Chain = EnvVal.getValue(0);
2504 InFlag = EnvVal.getValue(1);
2506 // Load TOC of the callee into r2. We are using a target-specific load
2507 // with r2 hard coded, because the result of a target-independent load
2508 // would never go directly into r2, since r2 is a reserved register (which
2509 // prevents the register allocator from allocating it), resulting in an
2510 // additional register being allocated and an unnecessary move instruction
2512 VTs = DAG.getVTList(MVT::Other, MVT::Flag);
2513 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
2515 Chain = LoadTOCPtr.getValue(0);
2516 InFlag = LoadTOCPtr.getValue(1);
2518 MTCTROps[0] = Chain;
2519 MTCTROps[1] = LoadFuncPtr;
2520 MTCTROps[2] = InFlag;
2523 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2524 2 + (InFlag.getNode() != 0));
2525 InFlag = Chain.getValue(1);
2528 NodeTys.push_back(MVT::Other);
2529 NodeTys.push_back(MVT::Flag);
2530 Ops.push_back(Chain);
2531 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
2533 // Add CTR register as callee so a bctr can be emitted later.
2535 Ops.push_back(DAG.getRegister(PPC::CTR, PtrVT));
2538 // If this is a direct call, pass the chain and the callee.
2539 if (Callee.getNode()) {
2540 Ops.push_back(Chain);
2541 Ops.push_back(Callee);
2543 // If this is a tail call add stack pointer delta.
2545 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2547 // Add argument registers to the end of the list so that they are known live
2549 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2550 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2551 RegsToPass[i].second.getValueType()));
2557 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2558 CallingConv::ID CallConv, bool isVarArg,
2559 const SmallVectorImpl<ISD::InputArg> &Ins,
2560 DebugLoc dl, SelectionDAG &DAG,
2561 SmallVectorImpl<SDValue> &InVals) {
2563 SmallVector<CCValAssign, 16> RVLocs;
2564 CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(),
2565 RVLocs, *DAG.getContext());
2566 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2568 // Copy all of the result registers out of their specified physreg.
2569 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2570 CCValAssign &VA = RVLocs[i];
2571 EVT VT = VA.getValVT();
2572 assert(VA.isRegLoc() && "Can only return in registers!");
2573 Chain = DAG.getCopyFromReg(Chain, dl,
2574 VA.getLocReg(), VT, InFlag).getValue(1);
2575 InVals.push_back(Chain.getValue(0));
2576 InFlag = Chain.getValue(2);
2583 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
2584 bool isTailCall, bool isVarArg,
2586 SmallVector<std::pair<unsigned, SDValue>, 8>
2588 SDValue InFlag, SDValue Chain,
2590 int SPDiff, unsigned NumBytes,
2591 const SmallVectorImpl<ISD::InputArg> &Ins,
2592 SmallVectorImpl<SDValue> &InVals) {
2593 std::vector<EVT> NodeTys;
2594 SmallVector<SDValue, 8> Ops;
2595 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
2596 isTailCall, RegsToPass, Ops, NodeTys,
2597 PPCSubTarget.isPPC64(),
2598 PPCSubTarget.isSVR4ABI());
2600 // When performing tail call optimization the callee pops its arguments off
2601 // the stack. Account for this here so these bytes can be pushed back on in
2602 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2603 int BytesCalleePops =
2604 (CallConv==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0;
2606 if (InFlag.getNode())
2607 Ops.push_back(InFlag);
2611 // If this is the first return lowered for this function, add the regs
2612 // to the liveout set for the function.
2613 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2614 SmallVector<CCValAssign, 16> RVLocs;
2615 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2617 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2618 for (unsigned i = 0; i != RVLocs.size(); ++i)
2619 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2622 assert(((Callee.getOpcode() == ISD::Register &&
2623 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
2624 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2625 Callee.getOpcode() == ISD::TargetGlobalAddress ||
2626 isa<ConstantSDNode>(Callee)) &&
2627 "Expecting an global address, external symbol, absolute value or register");
2629 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
2632 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
2633 InFlag = Chain.getValue(1);
2635 // Add a NOP immediately after the branch instruction when using the 64-bit
2636 // SVR4 ABI. At link time, if caller and callee are in a different module and
2637 // thus have a different TOC, the call will be replaced with a call to a stub
2638 // function which saves the current TOC, loads the TOC of the callee and
2639 // branches to the callee. The NOP will be replaced with a load instruction
2640 // which restores the TOC of the caller from the TOC save slot of the current
2641 // stack frame. If caller and callee belong to the same module (and have the
2642 // same TOC), the NOP will remain unchanged.
2643 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
2644 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag);
2645 if (CallOpc == PPCISD::BCTRL_SVR4) {
2646 // This is a call through a function pointer.
2647 // Restore the caller TOC from the save area into R2.
2648 // See PrepareCall() for more information about calls through function
2649 // pointers in the 64-bit SVR4 ABI.
2650 // We are using a target-specific load with r2 hard coded, because the
2651 // result of a target-independent load would never go directly into r2,
2652 // since r2 is a reserved register (which prevents the register allocator
2653 // from allocating it), resulting in an additional register being
2654 // allocated and an unnecessary move instruction being generated.
2655 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
2656 InFlag = Chain.getValue(1);
2658 // Otherwise insert NOP.
2659 InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Flag, InFlag);
2663 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2664 DAG.getIntPtrConstant(BytesCalleePops, true),
2667 InFlag = Chain.getValue(1);
2669 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2670 Ins, dl, DAG, InVals);
2674 PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2675 CallingConv::ID CallConv, bool isVarArg,
2677 const SmallVectorImpl<ISD::OutputArg> &Outs,
2678 const SmallVectorImpl<ISD::InputArg> &Ins,
2679 DebugLoc dl, SelectionDAG &DAG,
2680 SmallVectorImpl<SDValue> &InVals) {
2682 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
2685 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
2686 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg,
2687 isTailCall, Outs, Ins,
2690 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
2691 isTailCall, Outs, Ins,
2697 PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
2698 CallingConv::ID CallConv, bool isVarArg,
2700 const SmallVectorImpl<ISD::OutputArg> &Outs,
2701 const SmallVectorImpl<ISD::InputArg> &Ins,
2702 DebugLoc dl, SelectionDAG &DAG,
2703 SmallVectorImpl<SDValue> &InVals) {
2704 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description
2705 // of the 32-bit SVR4 ABI stack frame layout.
2707 assert((CallConv == CallingConv::C ||
2708 CallConv == CallingConv::Fast) && "Unknown calling convention!");
2710 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2711 unsigned PtrByteSize = 4;
2713 MachineFunction &MF = DAG.getMachineFunction();
2715 // Mark this function as potentially containing a function that contains a
2716 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2717 // and restoring the callers stack pointer in this functions epilog. This is
2718 // done because by tail calling the called function might overwrite the value
2719 // in this function's (MF) stack pointer stack slot 0(SP).
2720 if (PerformTailCallOpt && CallConv==CallingConv::Fast)
2721 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2723 // Count how many bytes are to be pushed on the stack, including the linkage
2724 // area, parameter list area and the part of the local variable space which
2725 // contains copies of aggregates which are passed by value.
2727 // Assign locations to all of the outgoing arguments.
2728 SmallVector<CCValAssign, 16> ArgLocs;
2729 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
2730 ArgLocs, *DAG.getContext());
2732 // Reserve space for the linkage area on the stack.
2733 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
2736 // Handle fixed and variable vector arguments differently.
2737 // Fixed vector arguments go into registers as long as registers are
2738 // available. Variable vector arguments always go into memory.
2739 unsigned NumArgs = Outs.size();
2741 for (unsigned i = 0; i != NumArgs; ++i) {
2742 EVT ArgVT = Outs[i].Val.getValueType();
2743 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2746 if (Outs[i].IsFixed) {
2747 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
2750 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
2756 errs() << "Call operand #" << i << " has unhandled type "
2757 << ArgVT.getEVTString() << "\n";
2759 llvm_unreachable(0);
2763 // All arguments are treated the same.
2764 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4);
2767 // Assign locations to all of the outgoing aggregate by value arguments.
2768 SmallVector<CCValAssign, 16> ByValArgLocs;
2769 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), ByValArgLocs,
2772 // Reserve stack space for the allocations in CCInfo.
2773 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2775 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal);
2777 // Size of the linkage area, parameter list area and the part of the local
2778 // space variable where copies of aggregates which are passed by value are
2780 unsigned NumBytes = CCByValInfo.getNextStackOffset();
2782 // Calculate by how many bytes the stack has to be adjusted in case of tail
2783 // call optimization.
2784 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2786 // Adjust the stack pointer for the new arguments...
2787 // These operations are automatically eliminated by the prolog/epilog pass
2788 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2789 SDValue CallSeqStart = Chain;
2791 // Load the return address and frame pointer so it can be moved somewhere else
2794 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
2797 // Set up a copy of the stack pointer for use loading and storing any
2798 // arguments that may not fit in the registers available for argument
2800 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2802 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2803 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2804 SmallVector<SDValue, 8> MemOpChains;
2806 // Walk the register/memloc assignments, inserting copies/loads.
2807 for (unsigned i = 0, j = 0, e = ArgLocs.size();
2810 CCValAssign &VA = ArgLocs[i];
2811 SDValue Arg = Outs[i].Val;
2812 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2814 if (Flags.isByVal()) {
2815 // Argument is an aggregate which is passed by value, thus we need to
2816 // create a copy of it in the local variable space of the current stack
2817 // frame (which is the stack frame of the caller) and pass the address of
2818 // this copy to the callee.
2819 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
2820 CCValAssign &ByValVA = ByValArgLocs[j++];
2821 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
2823 // Memory reserved in the local variable space of the callers stack frame.
2824 unsigned LocMemOffset = ByValVA.getLocMemOffset();
2826 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2827 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2829 // Create a copy of the argument in the local area of the current
2831 SDValue MemcpyCall =
2832 CreateCopyOfByValArgument(Arg, PtrOff,
2833 CallSeqStart.getNode()->getOperand(0),
2836 // This must go outside the CALLSEQ_START..END.
2837 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2838 CallSeqStart.getNode()->getOperand(1));
2839 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2840 NewCallSeqStart.getNode());
2841 Chain = CallSeqStart = NewCallSeqStart;
2843 // Pass the address of the aggregate copy on the stack either in a
2844 // physical register or in the parameter list area of the current stack
2845 // frame to the callee.
2849 if (VA.isRegLoc()) {
2850 // Put argument in a physical register.
2851 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2853 // Put argument in the parameter list area of the current stack frame.
2854 assert(VA.isMemLoc());
2855 unsigned LocMemOffset = VA.getLocMemOffset();
2858 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2859 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2861 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2862 PseudoSourceValue::getStack(), LocMemOffset));
2864 // Calculate and remember argument location.
2865 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
2871 if (!MemOpChains.empty())
2872 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2873 &MemOpChains[0], MemOpChains.size());
2875 // Build a sequence of copy-to-reg nodes chained together with token chain
2876 // and flag operands which copy the outgoing args into the appropriate regs.
2878 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2879 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2880 RegsToPass[i].second, InFlag);
2881 InFlag = Chain.getValue(1);
2884 // Set CR6 to true if this is a vararg call.
2886 SDValue SetCR(DAG.getMachineNode(PPC::CRSET, dl, MVT::i32), 0);
2887 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
2888 InFlag = Chain.getValue(1);
2892 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
2893 false, TailCallArguments);
2896 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
2897 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
2902 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
2903 CallingConv::ID CallConv, bool isVarArg,
2905 const SmallVectorImpl<ISD::OutputArg> &Outs,
2906 const SmallVectorImpl<ISD::InputArg> &Ins,
2907 DebugLoc dl, SelectionDAG &DAG,
2908 SmallVectorImpl<SDValue> &InVals) {
2910 unsigned NumOps = Outs.size();
2912 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2913 bool isPPC64 = PtrVT == MVT::i64;
2914 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2916 MachineFunction &MF = DAG.getMachineFunction();
2918 // Mark this function as potentially containing a function that contains a
2919 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2920 // and restoring the callers stack pointer in this functions epilog. This is
2921 // done because by tail calling the called function might overwrite the value
2922 // in this function's (MF) stack pointer stack slot 0(SP).
2923 if (PerformTailCallOpt && CallConv==CallingConv::Fast)
2924 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2926 unsigned nAltivecParamsAtEnd = 0;
2928 // Count how many bytes are to be pushed on the stack, including the linkage
2929 // area, and parameter passing area. We start with 24/48 bytes, which is
2930 // prereserved space for [SP][CR][LR][3 x unused].
2932 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
2934 nAltivecParamsAtEnd);
2936 // Calculate by how many bytes the stack has to be adjusted in case of tail
2937 // call optimization.
2938 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2940 // To protect arguments on the stack from being clobbered in a tail call,
2941 // force all the loads to happen before doing any other lowering.
2943 Chain = DAG.getStackArgumentTokenFactor(Chain);
2945 // Adjust the stack pointer for the new arguments...
2946 // These operations are automatically eliminated by the prolog/epilog pass
2947 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2948 SDValue CallSeqStart = Chain;
2950 // Load the return address and frame pointer so it can be move somewhere else
2953 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
2956 // Set up a copy of the stack pointer for use loading and storing any
2957 // arguments that may not fit in the registers available for argument
2961 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2963 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2965 // Figure out which arguments are going to go in registers, and which in
2966 // memory. Also, if this is a vararg function, floating point operations
2967 // must be stored to our stack, and loaded into integer regs as well, if
2968 // any integer regs are available for argument passing.
2969 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
2970 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2972 static const unsigned GPR_32[] = { // 32-bit registers.
2973 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2974 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2976 static const unsigned GPR_64[] = { // 64-bit registers.
2977 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2978 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2980 static const unsigned *FPR = GetFPR();
2982 static const unsigned VR[] = {
2983 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2984 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2986 const unsigned NumGPRs = array_lengthof(GPR_32);
2987 const unsigned NumFPRs = 13;
2988 const unsigned NumVRs = array_lengthof(VR);
2990 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
2992 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2993 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2995 SmallVector<SDValue, 8> MemOpChains;
2996 for (unsigned i = 0; i != NumOps; ++i) {
2997 SDValue Arg = Outs[i].Val;
2998 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3000 // PtrOff will be used to store the current argument to the stack if a
3001 // register cannot be found for it.
3004 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3006 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3008 // On PPC64, promote integers to 64-bit values.
3009 if (isPPC64 && Arg.getValueType() == MVT::i32) {
3010 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3011 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3012 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3015 // FIXME memcpy is used way more than necessary. Correctness first.
3016 if (Flags.isByVal()) {
3017 unsigned Size = Flags.getByValSize();
3018 if (Size==1 || Size==2) {
3019 // Very small objects are passed right-justified.
3020 // Everything else is passed left-justified.
3021 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
3022 if (GPR_idx != NumGPRs) {
3023 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3025 MemOpChains.push_back(Load.getValue(1));
3026 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3028 ArgOffset += PtrByteSize;
3030 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
3031 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3032 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
3033 CallSeqStart.getNode()->getOperand(0),
3035 // This must go outside the CALLSEQ_START..END.
3036 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3037 CallSeqStart.getNode()->getOperand(1));
3038 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3039 NewCallSeqStart.getNode());
3040 Chain = CallSeqStart = NewCallSeqStart;
3041 ArgOffset += PtrByteSize;
3045 // Copy entire object into memory. There are cases where gcc-generated
3046 // code assumes it is there, even if it could be put entirely into
3047 // registers. (This is not what the doc says.)
3048 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3049 CallSeqStart.getNode()->getOperand(0),
3051 // This must go outside the CALLSEQ_START..END.
3052 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3053 CallSeqStart.getNode()->getOperand(1));
3054 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
3055 Chain = CallSeqStart = NewCallSeqStart;
3056 // And copy the pieces of it that fit into registers.
3057 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3058 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3059 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3060 if (GPR_idx != NumGPRs) {
3061 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, NULL, 0);
3062 MemOpChains.push_back(Load.getValue(1));
3063 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3064 ArgOffset += PtrByteSize;
3066 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3073 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3074 default: llvm_unreachable("Unexpected ValueType for argument!");
3077 if (GPR_idx != NumGPRs) {
3078 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3080 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3081 isPPC64, isTailCall, false, MemOpChains,
3082 TailCallArguments, dl);
3084 ArgOffset += PtrByteSize;
3088 if (FPR_idx != NumFPRs) {
3089 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3092 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
3093 MemOpChains.push_back(Store);
3095 // Float varargs are always shadowed in available integer registers
3096 if (GPR_idx != NumGPRs) {
3097 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
3098 MemOpChains.push_back(Load.getValue(1));
3099 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3101 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
3102 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3103 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3104 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
3105 MemOpChains.push_back(Load.getValue(1));
3106 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3109 // If we have any FPRs remaining, we may also have GPRs remaining.
3110 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
3112 if (GPR_idx != NumGPRs)
3114 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
3115 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
3119 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3120 isPPC64, isTailCall, false, MemOpChains,
3121 TailCallArguments, dl);
3126 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
3133 // These go aligned on the stack, or in the corresponding R registers
3134 // when within range. The Darwin PPC ABI doc claims they also go in
3135 // V registers; in fact gcc does this only for arguments that are
3136 // prototyped, not for those that match the ... We do it for all
3137 // arguments, seems to work.
3138 while (ArgOffset % 16 !=0) {
3139 ArgOffset += PtrByteSize;
3140 if (GPR_idx != NumGPRs)
3143 // We could elide this store in the case where the object fits
3144 // entirely in R registers. Maybe later.
3145 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3146 DAG.getConstant(ArgOffset, PtrVT));
3147 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
3148 MemOpChains.push_back(Store);
3149 if (VR_idx != NumVRs) {
3150 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0);
3151 MemOpChains.push_back(Load.getValue(1));
3152 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
3155 for (unsigned i=0; i<16; i+=PtrByteSize) {
3156 if (GPR_idx == NumGPRs)
3158 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
3159 DAG.getConstant(i, PtrVT));
3160 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, NULL, 0);
3161 MemOpChains.push_back(Load.getValue(1));
3162 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3167 // Non-varargs Altivec params generally go in registers, but have
3168 // stack space allocated at the end.
3169 if (VR_idx != NumVRs) {
3170 // Doesn't have GPR space allocated.
3171 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
3172 } else if (nAltivecParamsAtEnd==0) {
3173 // We are emitting Altivec params in order.
3174 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3175 isPPC64, isTailCall, true, MemOpChains,
3176 TailCallArguments, dl);
3182 // If all Altivec parameters fit in registers, as they usually do,
3183 // they get stack space following the non-Altivec parameters. We
3184 // don't track this here because nobody below needs it.
3185 // If there are more Altivec parameters than fit in registers emit
3187 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
3189 // Offset is aligned; skip 1st 12 params which go in V registers.
3190 ArgOffset = ((ArgOffset+15)/16)*16;
3192 for (unsigned i = 0; i != NumOps; ++i) {
3193 SDValue Arg = Outs[i].Val;
3194 EVT ArgType = Arg.getValueType();
3195 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
3196 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
3199 // We are emitting Altivec params in order.
3200 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3201 isPPC64, isTailCall, true, MemOpChains,
3202 TailCallArguments, dl);
3209 if (!MemOpChains.empty())
3210 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3211 &MemOpChains[0], MemOpChains.size());
3213 // Check if this is an indirect call (MTCTR/BCTRL).
3214 // See PrepareCall() for more information about calls through function
3215 // pointers in the 64-bit SVR4 ABI.
3216 if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() &&
3217 !dyn_cast<GlobalAddressSDNode>(Callee) &&
3218 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3219 !isBLACompatibleAddress(Callee, DAG)) {
3220 // Load r2 into a virtual register and store it to the TOC save area.
3221 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
3222 // TOC save area offset.
3223 SDValue PtrOff = DAG.getIntPtrConstant(40);
3224 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3225 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, NULL, 0);
3228 // Build a sequence of copy-to-reg nodes chained together with token chain
3229 // and flag operands which copy the outgoing args into the appropriate regs.
3231 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3232 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3233 RegsToPass[i].second, InFlag);
3234 InFlag = Chain.getValue(1);
3238 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
3239 FPOp, true, TailCallArguments);
3242 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3243 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3248 PPCTargetLowering::LowerReturn(SDValue Chain,
3249 CallingConv::ID CallConv, bool isVarArg,
3250 const SmallVectorImpl<ISD::OutputArg> &Outs,
3251 DebugLoc dl, SelectionDAG &DAG) {
3253 SmallVector<CCValAssign, 16> RVLocs;
3254 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
3255 RVLocs, *DAG.getContext());
3256 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
3258 // If this is the first return lowered for this function, add the regs to the
3259 // liveout set for the function.
3260 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3261 for (unsigned i = 0; i != RVLocs.size(); ++i)
3262 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3267 // Copy the result values into the output registers.
3268 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3269 CCValAssign &VA = RVLocs[i];
3270 assert(VA.isRegLoc() && "Can only return in registers!");
3271 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3273 Flag = Chain.getValue(1);
3277 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
3279 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
3282 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
3283 const PPCSubtarget &Subtarget) {
3284 // When we pop the dynamic allocation we need to restore the SP link.
3285 DebugLoc dl = Op.getDebugLoc();
3287 // Get the corect type for pointers.
3288 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3290 // Construct the stack pointer operand.
3291 bool isPPC64 = Subtarget.isPPC64();
3292 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
3293 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
3295 // Get the operands for the STACKRESTORE.
3296 SDValue Chain = Op.getOperand(0);
3297 SDValue SaveSP = Op.getOperand(1);
3299 // Load the old link SP.
3300 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0);
3302 // Restore the stack pointer.
3303 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
3305 // Store the old link SP.
3306 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0);
3312 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
3313 MachineFunction &MF = DAG.getMachineFunction();
3314 bool isPPC64 = PPCSubTarget.isPPC64();
3315 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3316 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3318 // Get current frame pointer save index. The users of this index will be
3319 // primarily DYNALLOC instructions.
3320 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3321 int RASI = FI->getReturnAddrSaveIndex();
3323 // If the frame pointer save index hasn't been defined yet.
3325 // Find out what the fix offset of the frame pointer save area.
3326 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI);
3327 // Allocate the frame index for frame pointer save area.
3328 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset,
3331 FI->setReturnAddrSaveIndex(RASI);
3333 return DAG.getFrameIndex(RASI, PtrVT);
3337 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
3338 MachineFunction &MF = DAG.getMachineFunction();
3339 bool isPPC64 = PPCSubTarget.isPPC64();
3340 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3341 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3343 // Get current frame pointer save index. The users of this index will be
3344 // primarily DYNALLOC instructions.
3345 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3346 int FPSI = FI->getFramePointerSaveIndex();
3348 // If the frame pointer save index hasn't been defined yet.
3350 // Find out what the fix offset of the frame pointer save area.
3351 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64,
3354 // Allocate the frame index for frame pointer save area.
3355 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset,
3358 FI->setFramePointerSaveIndex(FPSI);
3360 return DAG.getFrameIndex(FPSI, PtrVT);
3363 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3365 const PPCSubtarget &Subtarget) {
3367 SDValue Chain = Op.getOperand(0);
3368 SDValue Size = Op.getOperand(1);
3369 DebugLoc dl = Op.getDebugLoc();
3371 // Get the corect type for pointers.
3372 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3374 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
3375 DAG.getConstant(0, PtrVT), Size);
3376 // Construct a node for the frame pointer save index.
3377 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
3378 // Build a DYNALLOC node.
3379 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
3380 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
3381 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
3384 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
3386 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
3387 // Not FP? Not a fsel.
3388 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
3389 !Op.getOperand(2).getValueType().isFloatingPoint())
3392 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3394 // Cannot handle SETEQ/SETNE.
3395 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
3397 EVT ResVT = Op.getValueType();
3398 EVT CmpVT = Op.getOperand(0).getValueType();
3399 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3400 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
3401 DebugLoc dl = Op.getDebugLoc();
3403 // If the RHS of the comparison is a 0.0, we don't need to do the
3404 // subtraction at all.
3405 if (isFloatingPointZero(RHS))
3407 default: break; // SETUO etc aren't handled by fsel.
3410 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3413 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3414 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3415 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
3418 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3421 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3422 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3423 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
3424 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
3429 default: break; // SETUO etc aren't handled by fsel.
3432 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3433 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3434 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3435 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3438 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3439 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3440 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3441 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3444 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3445 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3446 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3447 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3450 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3451 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3452 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3453 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3458 // FIXME: Split this code up when LegalizeDAGTypes lands.
3459 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
3461 assert(Op.getOperand(0).getValueType().isFloatingPoint());
3462 SDValue Src = Op.getOperand(0);
3463 if (Src.getValueType() == MVT::f32)
3464 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
3467 switch (Op.getValueType().getSimpleVT().SimpleTy) {
3468 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
3470 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
3475 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
3479 // Convert the FP value to an int value through memory.
3480 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
3482 // Emit a store to the stack slot.
3483 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0);
3485 // Result is a load from the stack slot. If loading 4 bytes, make sure to
3487 if (Op.getValueType() == MVT::i32)
3488 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
3489 DAG.getConstant(4, FIPtr.getValueType()));
3490 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0);
3493 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
3494 DebugLoc dl = Op.getDebugLoc();
3495 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
3496 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
3499 if (Op.getOperand(0).getValueType() == MVT::i64) {
3500 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl,
3501 MVT::f64, Op.getOperand(0));
3502 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
3503 if (Op.getValueType() == MVT::f32)
3504 FP = DAG.getNode(ISD::FP_ROUND, dl,
3505 MVT::f32, FP, DAG.getIntPtrConstant(0));
3509 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
3510 "Unhandled SINT_TO_FP type in custom expander!");
3511 // Since we only generate this in 64-bit mode, we can take advantage of
3512 // 64-bit registers. In particular, sign extend the input value into the
3513 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
3514 // then lfd it and fcfid it.
3515 MachineFunction &MF = DAG.getMachineFunction();
3516 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
3517 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
3518 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3519 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3521 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
3524 // STD the extended value into the stack slot.
3525 MachineMemOperand *MMO =
3526 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
3527 MachineMemOperand::MOStore, 0, 8, 8);
3528 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
3530 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other),
3531 Ops, 4, MVT::i64, MMO);
3532 // Load the value as a double.
3533 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0);
3535 // FCFID it and return it.
3536 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
3537 if (Op.getValueType() == MVT::f32)
3538 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
3542 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
3543 DebugLoc dl = Op.getDebugLoc();
3545 The rounding mode is in bits 30:31 of FPSR, and has the following
3552 FLT_ROUNDS, on the other hand, expects the following:
3559 To perform the conversion, we do:
3560 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
3563 MachineFunction &MF = DAG.getMachineFunction();
3564 EVT VT = Op.getValueType();
3565 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3566 std::vector<EVT> NodeTys;
3567 SDValue MFFSreg, InFlag;
3569 // Save FP Control Word to register
3570 NodeTys.push_back(MVT::f64); // return register
3571 NodeTys.push_back(MVT::Flag); // unused in this context
3572 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
3574 // Save FP register to stack slot
3575 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
3576 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
3577 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
3578 StackSlot, NULL, 0);
3580 // Load FP Control Word from low 32 bits of stack slot.
3581 SDValue Four = DAG.getConstant(4, PtrVT);
3582 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
3583 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0);
3585 // Transform as necessary
3587 DAG.getNode(ISD::AND, dl, MVT::i32,
3588 CWD, DAG.getConstant(3, MVT::i32));
3590 DAG.getNode(ISD::SRL, dl, MVT::i32,
3591 DAG.getNode(ISD::AND, dl, MVT::i32,
3592 DAG.getNode(ISD::XOR, dl, MVT::i32,
3593 CWD, DAG.getConstant(3, MVT::i32)),
3594 DAG.getConstant(3, MVT::i32)),
3595 DAG.getConstant(1, MVT::i32));
3598 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
3600 return DAG.getNode((VT.getSizeInBits() < 16 ?
3601 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3604 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) {
3605 EVT VT = Op.getValueType();
3606 unsigned BitWidth = VT.getSizeInBits();
3607 DebugLoc dl = Op.getDebugLoc();
3608 assert(Op.getNumOperands() == 3 &&
3609 VT == Op.getOperand(1).getValueType() &&
3612 // Expand into a bunch of logical ops. Note that these ops
3613 // depend on the PPC behavior for oversized shift amounts.
3614 SDValue Lo = Op.getOperand(0);
3615 SDValue Hi = Op.getOperand(1);
3616 SDValue Amt = Op.getOperand(2);
3617 EVT AmtVT = Amt.getValueType();
3619 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3620 DAG.getConstant(BitWidth, AmtVT), Amt);
3621 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3622 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3623 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3624 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3625 DAG.getConstant(-BitWidth, AmtVT));
3626 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3627 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3628 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3629 SDValue OutOps[] = { OutLo, OutHi };
3630 return DAG.getMergeValues(OutOps, 2, dl);
3633 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) {
3634 EVT VT = Op.getValueType();
3635 DebugLoc dl = Op.getDebugLoc();
3636 unsigned BitWidth = VT.getSizeInBits();
3637 assert(Op.getNumOperands() == 3 &&
3638 VT == Op.getOperand(1).getValueType() &&
3641 // Expand into a bunch of logical ops. Note that these ops
3642 // depend on the PPC behavior for oversized shift amounts.
3643 SDValue Lo = Op.getOperand(0);
3644 SDValue Hi = Op.getOperand(1);
3645 SDValue Amt = Op.getOperand(2);
3646 EVT AmtVT = Amt.getValueType();
3648 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3649 DAG.getConstant(BitWidth, AmtVT), Amt);
3650 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3651 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3652 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3653 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3654 DAG.getConstant(-BitWidth, AmtVT));
3655 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3656 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3657 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3658 SDValue OutOps[] = { OutLo, OutHi };
3659 return DAG.getMergeValues(OutOps, 2, dl);
3662 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) {
3663 DebugLoc dl = Op.getDebugLoc();
3664 EVT VT = Op.getValueType();
3665 unsigned BitWidth = VT.getSizeInBits();
3666 assert(Op.getNumOperands() == 3 &&
3667 VT == Op.getOperand(1).getValueType() &&
3670 // Expand into a bunch of logical ops, followed by a select_cc.
3671 SDValue Lo = Op.getOperand(0);
3672 SDValue Hi = Op.getOperand(1);
3673 SDValue Amt = Op.getOperand(2);
3674 EVT AmtVT = Amt.getValueType();
3676 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3677 DAG.getConstant(BitWidth, AmtVT), Amt);
3678 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3679 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3680 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3681 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3682 DAG.getConstant(-BitWidth, AmtVT));
3683 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3684 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3685 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
3686 Tmp4, Tmp6, ISD::SETLE);
3687 SDValue OutOps[] = { OutLo, OutHi };
3688 return DAG.getMergeValues(OutOps, 2, dl);
3691 //===----------------------------------------------------------------------===//
3692 // Vector related lowering.
3695 /// BuildSplatI - Build a canonical splati of Val with an element size of
3696 /// SplatSize. Cast the result to VT.
3697 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
3698 SelectionDAG &DAG, DebugLoc dl) {
3699 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3701 static const EVT VTys[] = { // canonical VT to use for each size.
3702 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3705 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3707 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3711 EVT CanonicalVT = VTys[SplatSize-1];
3713 // Build a canonical splat for this value.
3714 SDValue Elt = DAG.getConstant(Val, MVT::i32);
3715 SmallVector<SDValue, 8> Ops;
3716 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3717 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
3718 &Ops[0], Ops.size());
3719 return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res);
3722 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3723 /// specified intrinsic ID.
3724 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3725 SelectionDAG &DAG, DebugLoc dl,
3726 EVT DestVT = MVT::Other) {
3727 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3728 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3729 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3732 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3733 /// specified intrinsic ID.
3734 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3735 SDValue Op2, SelectionDAG &DAG,
3736 DebugLoc dl, EVT DestVT = MVT::Other) {
3737 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3738 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3739 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3743 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3744 /// amount. The result has the specified value type.
3745 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3746 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3747 // Force LHS/RHS to be the right type.
3748 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS);
3749 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS);
3752 for (unsigned i = 0; i != 16; ++i)
3754 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
3755 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
3758 // If this is a case we can't handle, return null and let the default
3759 // expansion code take care of it. If we CAN select this case, and if it
3760 // selects to a single instruction, return Op. Otherwise, if we can codegen
3761 // this case more efficiently than a constant pool load, lower it to the
3762 // sequence of ops that should be used.
3763 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3764 DebugLoc dl = Op.getDebugLoc();
3765 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3766 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
3768 // Check if this is a splat of a constant value.
3769 APInt APSplatBits, APSplatUndef;
3770 unsigned SplatBitSize;
3772 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
3773 HasAnyUndefs, 0, true) || SplatBitSize > 32)
3776 unsigned SplatBits = APSplatBits.getZExtValue();
3777 unsigned SplatUndef = APSplatUndef.getZExtValue();
3778 unsigned SplatSize = SplatBitSize / 8;
3780 // First, handle single instruction cases.
3783 if (SplatBits == 0) {
3784 // Canonicalize all zero vectors to be v4i32.
3785 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3786 SDValue Z = DAG.getConstant(0, MVT::i32);
3787 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
3788 Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z);
3793 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3794 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
3796 if (SextVal >= -16 && SextVal <= 15)
3797 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
3800 // Two instruction sequences.
3802 // If this value is in the range [-32,30] and is even, use:
3803 // tmp = VSPLTI[bhw], result = add tmp, tmp
3804 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
3805 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
3806 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
3807 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3810 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
3811 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
3813 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
3814 // Make -1 and vspltisw -1:
3815 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
3817 // Make the VSLW intrinsic, computing 0x8000_0000.
3818 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
3821 // xor by OnesV to invert it.
3822 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
3823 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3826 // Check to see if this is a wide variety of vsplti*, binop self cases.
3827 static const signed char SplatCsts[] = {
3828 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
3829 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
3832 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
3833 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
3834 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
3835 int i = SplatCsts[idx];
3837 // Figure out what shift amount will be used by altivec if shifted by i in
3839 unsigned TypeShiftAmt = i & (SplatBitSize-1);
3841 // vsplti + shl self.
3842 if (SextVal == (i << (int)TypeShiftAmt)) {
3843 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3844 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3845 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
3846 Intrinsic::ppc_altivec_vslw
3848 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3849 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3852 // vsplti + srl self.
3853 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3854 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3855 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3856 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
3857 Intrinsic::ppc_altivec_vsrw
3859 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3860 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3863 // vsplti + sra self.
3864 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3865 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3866 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3867 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
3868 Intrinsic::ppc_altivec_vsraw
3870 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3871 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3874 // vsplti + rol self.
3875 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
3876 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
3877 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3878 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3879 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
3880 Intrinsic::ppc_altivec_vrlw
3882 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3883 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3886 // t = vsplti c, result = vsldoi t, t, 1
3887 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
3888 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3889 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
3891 // t = vsplti c, result = vsldoi t, t, 2
3892 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
3893 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3894 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
3896 // t = vsplti c, result = vsldoi t, t, 3
3897 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
3898 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3899 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
3903 // Three instruction sequences.
3905 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
3906 if (SextVal >= 0 && SextVal <= 31) {
3907 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
3908 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3909 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
3910 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3912 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
3913 if (SextVal >= -31 && SextVal <= 0) {
3914 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
3915 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3916 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
3917 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3923 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3924 /// the specified operations to build the shuffle.
3925 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3926 SDValue RHS, SelectionDAG &DAG,
3928 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3929 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3930 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3933 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3945 if (OpNum == OP_COPY) {
3946 if (LHSID == (1*9+2)*9+3) return LHS;
3947 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3951 SDValue OpLHS, OpRHS;
3952 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3953 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3957 default: llvm_unreachable("Unknown i32 permute!");
3959 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
3960 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
3961 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
3962 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
3965 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
3966 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
3967 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
3968 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
3971 for (unsigned i = 0; i != 16; ++i)
3972 ShufIdxs[i] = (i&3)+0;
3975 for (unsigned i = 0; i != 16; ++i)
3976 ShufIdxs[i] = (i&3)+4;
3979 for (unsigned i = 0; i != 16; ++i)
3980 ShufIdxs[i] = (i&3)+8;
3983 for (unsigned i = 0; i != 16; ++i)
3984 ShufIdxs[i] = (i&3)+12;
3987 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
3989 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
3991 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
3993 EVT VT = OpLHS.getValueType();
3994 OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS);
3995 OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS);
3996 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
3997 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
4000 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
4001 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
4002 /// return the code it can be lowered into. Worst case, it can always be
4003 /// lowered into a vperm.
4004 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4005 SelectionDAG &DAG) {
4006 DebugLoc dl = Op.getDebugLoc();
4007 SDValue V1 = Op.getOperand(0);
4008 SDValue V2 = Op.getOperand(1);
4009 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4010 EVT VT = Op.getValueType();
4012 // Cases that are handled by instructions that take permute immediates
4013 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
4014 // selected by the instruction selector.
4015 if (V2.getOpcode() == ISD::UNDEF) {
4016 if (PPC::isSplatShuffleMask(SVOp, 1) ||
4017 PPC::isSplatShuffleMask(SVOp, 2) ||
4018 PPC::isSplatShuffleMask(SVOp, 4) ||
4019 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
4020 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
4021 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
4022 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
4023 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
4024 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
4025 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
4026 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
4027 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
4032 // Altivec has a variety of "shuffle immediates" that take two vector inputs
4033 // and produce a fixed permutation. If any of these match, do not lower to
4035 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
4036 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
4037 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
4038 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
4039 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
4040 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
4041 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
4042 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
4043 PPC::isVMRGHShuffleMask(SVOp, 4, false))
4046 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
4047 // perfect shuffle table to emit an optimal matching sequence.
4048 SmallVector<int, 16> PermMask;
4049 SVOp->getMask(PermMask);
4051 unsigned PFIndexes[4];
4052 bool isFourElementShuffle = true;
4053 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
4054 unsigned EltNo = 8; // Start out undef.
4055 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
4056 if (PermMask[i*4+j] < 0)
4057 continue; // Undef, ignore it.
4059 unsigned ByteSource = PermMask[i*4+j];
4060 if ((ByteSource & 3) != j) {
4061 isFourElementShuffle = false;
4066 EltNo = ByteSource/4;
4067 } else if (EltNo != ByteSource/4) {
4068 isFourElementShuffle = false;
4072 PFIndexes[i] = EltNo;
4075 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
4076 // perfect shuffle vector to determine if it is cost effective to do this as
4077 // discrete instructions, or whether we should use a vperm.
4078 if (isFourElementShuffle) {
4079 // Compute the index in the perfect shuffle table.
4080 unsigned PFTableIndex =
4081 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4083 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4084 unsigned Cost = (PFEntry >> 30);
4086 // Determining when to avoid vperm is tricky. Many things affect the cost
4087 // of vperm, particularly how many times the perm mask needs to be computed.
4088 // For example, if the perm mask can be hoisted out of a loop or is already
4089 // used (perhaps because there are multiple permutes with the same shuffle
4090 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
4091 // the loop requires an extra register.
4093 // As a compromise, we only emit discrete instructions if the shuffle can be
4094 // generated in 3 or fewer operations. When we have loop information
4095 // available, if this block is within a loop, we should avoid using vperm
4096 // for 3-operation perms and use a constant pool load instead.
4098 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4101 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
4102 // vector that will get spilled to the constant pool.
4103 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
4105 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
4106 // that it is in input element units, not in bytes. Convert now.
4107 EVT EltVT = V1.getValueType().getVectorElementType();
4108 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
4110 SmallVector<SDValue, 16> ResultMask;
4111 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
4112 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
4114 for (unsigned j = 0; j != BytesPerElement; ++j)
4115 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
4119 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
4120 &ResultMask[0], ResultMask.size());
4121 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
4124 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
4125 /// altivec comparison. If it is, return true and fill in Opc/isDot with
4126 /// information about the intrinsic.
4127 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
4129 unsigned IntrinsicID =
4130 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
4133 switch (IntrinsicID) {
4134 default: return false;
4135 // Comparison predicates.
4136 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
4137 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
4138 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
4139 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
4140 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
4141 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
4142 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
4143 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
4144 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
4145 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
4146 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
4147 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
4148 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
4150 // Normal Comparisons.
4151 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
4152 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
4153 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
4154 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
4155 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
4156 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
4157 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
4158 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
4159 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
4160 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
4161 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
4162 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
4163 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
4168 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
4169 /// lower, do it, otherwise return null.
4170 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
4171 SelectionDAG &DAG) {
4172 // If this is a lowered altivec predicate compare, CompareOpc is set to the
4173 // opcode number of the comparison.
4174 DebugLoc dl = Op.getDebugLoc();
4177 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
4178 return SDValue(); // Don't custom lower most intrinsics.
4180 // If this is a non-dot comparison, make the VCMP node and we are done.
4182 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
4183 Op.getOperand(1), Op.getOperand(2),
4184 DAG.getConstant(CompareOpc, MVT::i32));
4185 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp);
4188 // Create the PPCISD altivec 'dot' comparison node.
4190 Op.getOperand(2), // LHS
4191 Op.getOperand(3), // RHS
4192 DAG.getConstant(CompareOpc, MVT::i32)
4194 std::vector<EVT> VTs;
4195 VTs.push_back(Op.getOperand(2).getValueType());
4196 VTs.push_back(MVT::Flag);
4197 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
4199 // Now that we have the comparison, emit a copy from the CR to a GPR.
4200 // This is flagged to the above dot comparison.
4201 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
4202 DAG.getRegister(PPC::CR6, MVT::i32),
4203 CompNode.getValue(1));
4205 // Unpack the result based on how the target uses it.
4206 unsigned BitNo; // Bit # of CR6.
4207 bool InvertBit; // Invert result?
4208 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
4209 default: // Can't happen, don't crash on invalid number though.
4210 case 0: // Return the value of the EQ bit of CR6.
4211 BitNo = 0; InvertBit = false;
4213 case 1: // Return the inverted value of the EQ bit of CR6.
4214 BitNo = 0; InvertBit = true;
4216 case 2: // Return the value of the LT bit of CR6.
4217 BitNo = 2; InvertBit = false;
4219 case 3: // Return the inverted value of the LT bit of CR6.
4220 BitNo = 2; InvertBit = true;
4224 // Shift the bit into the low position.
4225 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
4226 DAG.getConstant(8-(3-BitNo), MVT::i32));
4228 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
4229 DAG.getConstant(1, MVT::i32));
4231 // If we are supposed to, toggle the bit.
4233 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
4234 DAG.getConstant(1, MVT::i32));
4238 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
4239 SelectionDAG &DAG) {
4240 DebugLoc dl = Op.getDebugLoc();
4241 // Create a stack slot that is 16-byte aligned.
4242 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4243 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
4244 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4245 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4247 // Store the input value into Value#0 of the stack slot.
4248 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
4249 Op.getOperand(0), FIdx, NULL, 0);
4251 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0);
4254 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
4255 DebugLoc dl = Op.getDebugLoc();
4256 if (Op.getValueType() == MVT::v4i32) {
4257 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4259 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
4260 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
4262 SDValue RHSSwap = // = vrlw RHS, 16
4263 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
4265 // Shrinkify inputs to v8i16.
4266 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS);
4267 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS);
4268 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap);
4270 // Low parts multiplied together, generating 32-bit results (we ignore the
4272 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
4273 LHS, RHS, DAG, dl, MVT::v4i32);
4275 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
4276 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
4277 // Shift the high parts up 16 bits.
4278 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
4280 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
4281 } else if (Op.getValueType() == MVT::v8i16) {
4282 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4284 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
4286 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
4287 LHS, RHS, Zero, DAG, dl);
4288 } else if (Op.getValueType() == MVT::v16i8) {
4289 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4291 // Multiply the even 8-bit parts, producing 16-bit sums.
4292 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
4293 LHS, RHS, DAG, dl, MVT::v8i16);
4294 EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts);
4296 // Multiply the odd 8-bit parts, producing 16-bit sums.
4297 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
4298 LHS, RHS, DAG, dl, MVT::v8i16);
4299 OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts);
4301 // Merge the results together.
4303 for (unsigned i = 0; i != 8; ++i) {
4305 Ops[i*2+1] = 2*i+1+16;
4307 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
4309 llvm_unreachable("Unknown mul to lower!");
4313 /// LowerOperation - Provide custom lowering hooks for some operations.
4315 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
4316 switch (Op.getOpcode()) {
4317 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
4318 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4319 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4320 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4321 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4322 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4323 case ISD::SETCC: return LowerSETCC(Op, DAG);
4324 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
4326 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
4327 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
4330 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
4331 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
4333 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
4334 case ISD::DYNAMIC_STACKALLOC:
4335 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
4337 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4338 case ISD::FP_TO_UINT:
4339 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
4341 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4342 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4344 // Lower 64-bit shifts.
4345 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
4346 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
4347 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
4349 // Vector-related lowering.
4350 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4351 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4352 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4353 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4354 case ISD::MUL: return LowerMUL(Op, DAG);
4356 // Frame & Return address.
4357 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4358 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4363 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
4364 SmallVectorImpl<SDValue>&Results,
4365 SelectionDAG &DAG) {
4366 DebugLoc dl = N->getDebugLoc();
4367 switch (N->getOpcode()) {
4369 assert(false && "Do not know how to custom type legalize this operation!");
4371 case ISD::FP_ROUND_INREG: {
4372 assert(N->getValueType(0) == MVT::ppcf128);
4373 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
4374 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4375 MVT::f64, N->getOperand(0),
4376 DAG.getIntPtrConstant(0));
4377 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4378 MVT::f64, N->getOperand(0),
4379 DAG.getIntPtrConstant(1));
4381 // This sequence changes FPSCR to do round-to-zero, adds the two halves
4382 // of the long double, and puts FPSCR back the way it was. We do not
4383 // actually model FPSCR.
4384 std::vector<EVT> NodeTys;
4385 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
4387 NodeTys.push_back(MVT::f64); // Return register
4388 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
4389 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4390 MFFSreg = Result.getValue(0);
4391 InFlag = Result.getValue(1);
4394 NodeTys.push_back(MVT::Flag); // Returns a flag
4395 Ops[0] = DAG.getConstant(31, MVT::i32);
4397 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
4398 InFlag = Result.getValue(0);
4401 NodeTys.push_back(MVT::Flag); // Returns a flag
4402 Ops[0] = DAG.getConstant(30, MVT::i32);
4404 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
4405 InFlag = Result.getValue(0);
4408 NodeTys.push_back(MVT::f64); // result of add
4409 NodeTys.push_back(MVT::Flag); // Returns a flag
4413 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
4414 FPreg = Result.getValue(0);
4415 InFlag = Result.getValue(1);
4418 NodeTys.push_back(MVT::f64);
4419 Ops[0] = DAG.getConstant(1, MVT::i32);
4423 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
4424 FPreg = Result.getValue(0);
4426 // We know the low half is about to be thrown away, so just use something
4428 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
4432 case ISD::FP_TO_SINT:
4433 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
4439 //===----------------------------------------------------------------------===//
4440 // Other Lowering Code
4441 //===----------------------------------------------------------------------===//
4444 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4445 bool is64bit, unsigned BinOpcode) const {
4446 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4447 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4449 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4450 MachineFunction *F = BB->getParent();
4451 MachineFunction::iterator It = BB;
4454 unsigned dest = MI->getOperand(0).getReg();
4455 unsigned ptrA = MI->getOperand(1).getReg();
4456 unsigned ptrB = MI->getOperand(2).getReg();
4457 unsigned incr = MI->getOperand(3).getReg();
4458 DebugLoc dl = MI->getDebugLoc();
4460 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4461 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4462 F->insert(It, loopMBB);
4463 F->insert(It, exitMBB);
4464 exitMBB->transferSuccessors(BB);
4466 MachineRegisterInfo &RegInfo = F->getRegInfo();
4467 unsigned TmpReg = (!BinOpcode) ? incr :
4468 RegInfo.createVirtualRegister(
4469 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4470 (const TargetRegisterClass *) &PPC::GPRCRegClass);
4474 // fallthrough --> loopMBB
4475 BB->addSuccessor(loopMBB);
4478 // l[wd]arx dest, ptr
4479 // add r0, dest, incr
4480 // st[wd]cx. r0, ptr
4482 // fallthrough --> exitMBB
4484 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4485 .addReg(ptrA).addReg(ptrB);
4487 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
4488 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4489 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
4490 BuildMI(BB, dl, TII->get(PPC::BCC))
4491 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4492 BB->addSuccessor(loopMBB);
4493 BB->addSuccessor(exitMBB);
4502 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
4503 MachineBasicBlock *BB,
4504 bool is8bit, // operation
4505 unsigned BinOpcode) const {
4506 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4507 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4508 // In 64 bit mode we have to use 64 bits for addresses, even though the
4509 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
4510 // registers without caring whether they're 32 or 64, but here we're
4511 // doing actual arithmetic on the addresses.
4512 bool is64bit = PPCSubTarget.isPPC64();
4514 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4515 MachineFunction *F = BB->getParent();
4516 MachineFunction::iterator It = BB;
4519 unsigned dest = MI->getOperand(0).getReg();
4520 unsigned ptrA = MI->getOperand(1).getReg();
4521 unsigned ptrB = MI->getOperand(2).getReg();
4522 unsigned incr = MI->getOperand(3).getReg();
4523 DebugLoc dl = MI->getDebugLoc();
4525 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4526 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4527 F->insert(It, loopMBB);
4528 F->insert(It, exitMBB);
4529 exitMBB->transferSuccessors(BB);
4531 MachineRegisterInfo &RegInfo = F->getRegInfo();
4532 const TargetRegisterClass *RC =
4533 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4534 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4535 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4536 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4537 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4538 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4539 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4540 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4541 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4542 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4543 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
4544 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4545 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4547 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
4551 // fallthrough --> loopMBB
4552 BB->addSuccessor(loopMBB);
4554 // The 4-byte load must be aligned, while a char or short may be
4555 // anywhere in the word. Hence all this nasty bookkeeping code.
4556 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4557 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4558 // xori shift, shift1, 24 [16]
4559 // rlwinm ptr, ptr1, 0, 0, 29
4560 // slw incr2, incr, shift
4561 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4562 // slw mask, mask2, shift
4564 // lwarx tmpDest, ptr
4565 // add tmp, tmpDest, incr2
4566 // andc tmp2, tmpDest, mask
4567 // and tmp3, tmp, mask
4568 // or tmp4, tmp3, tmp2
4571 // fallthrough --> exitMBB
4572 // srw dest, tmpDest, shift
4574 if (ptrA!=PPC::R0) {
4575 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4576 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4577 .addReg(ptrA).addReg(ptrB);
4581 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4582 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4583 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4584 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4586 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4587 .addReg(Ptr1Reg).addImm(0).addImm(61);
4589 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4590 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4591 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
4592 .addReg(incr).addReg(ShiftReg);
4594 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4596 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4597 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
4599 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4600 .addReg(Mask2Reg).addReg(ShiftReg);
4603 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4604 .addReg(PPC::R0).addReg(PtrReg);
4606 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
4607 .addReg(Incr2Reg).addReg(TmpDestReg);
4608 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4609 .addReg(TmpDestReg).addReg(MaskReg);
4610 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4611 .addReg(TmpReg).addReg(MaskReg);
4612 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4613 .addReg(Tmp3Reg).addReg(Tmp2Reg);
4614 BuildMI(BB, dl, TII->get(PPC::STWCX))
4615 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
4616 BuildMI(BB, dl, TII->get(PPC::BCC))
4617 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4618 BB->addSuccessor(loopMBB);
4619 BB->addSuccessor(exitMBB);
4624 BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
4629 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4630 MachineBasicBlock *BB,
4631 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const {
4632 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4634 // To "insert" these instructions we actually have to insert their
4635 // control-flow patterns.
4636 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4637 MachineFunction::iterator It = BB;
4640 MachineFunction *F = BB->getParent();
4642 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4643 MI->getOpcode() == PPC::SELECT_CC_I8 ||
4644 MI->getOpcode() == PPC::SELECT_CC_F4 ||
4645 MI->getOpcode() == PPC::SELECT_CC_F8 ||
4646 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4648 // The incoming instruction knows the destination vreg to set, the
4649 // condition code register to branch on, the true/false values to
4650 // select between, and a branch opcode to use.
4655 // cmpTY ccX, r1, r2
4657 // fallthrough --> copy0MBB
4658 MachineBasicBlock *thisMBB = BB;
4659 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4660 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4661 unsigned SelectPred = MI->getOperand(4).getImm();
4662 DebugLoc dl = MI->getDebugLoc();
4663 BuildMI(BB, dl, TII->get(PPC::BCC))
4664 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4665 F->insert(It, copy0MBB);
4666 F->insert(It, sinkMBB);
4667 // Update machine-CFG edges by first adding all successors of the current
4668 // block to the new block which will contain the Phi node for the select.
4669 // Also inform sdisel of the edge changes.
4670 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
4671 E = BB->succ_end(); I != E; ++I) {
4672 EM->insert(std::make_pair(*I, sinkMBB));
4673 sinkMBB->addSuccessor(*I);
4675 // Next, remove all successors of the current block, and add the true
4676 // and fallthrough blocks as its successors.
4677 while (!BB->succ_empty())
4678 BB->removeSuccessor(BB->succ_begin());
4679 // Next, add the true and fallthrough blocks as its successors.
4680 BB->addSuccessor(copy0MBB);
4681 BB->addSuccessor(sinkMBB);
4684 // %FalseValue = ...
4685 // # fallthrough to sinkMBB
4688 // Update machine-CFG edges
4689 BB->addSuccessor(sinkMBB);
4692 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4695 BuildMI(BB, dl, TII->get(PPC::PHI), MI->getOperand(0).getReg())
4696 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4697 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4699 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4700 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4701 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4702 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4703 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4704 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4705 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4706 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4708 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4709 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4710 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4711 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4712 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4713 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4714 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4715 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4717 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4718 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4719 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4720 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4721 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4722 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4723 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4724 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4726 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4727 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4728 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4729 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4730 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4731 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4732 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4733 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4735 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4736 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
4737 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4738 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
4739 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4740 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
4741 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4742 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
4744 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
4745 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
4746 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
4747 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
4748 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
4749 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
4750 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
4751 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
4753 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
4754 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
4755 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
4756 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
4757 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
4758 BB = EmitAtomicBinary(MI, BB, false, 0);
4759 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
4760 BB = EmitAtomicBinary(MI, BB, true, 0);
4762 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
4763 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
4764 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
4766 unsigned dest = MI->getOperand(0).getReg();
4767 unsigned ptrA = MI->getOperand(1).getReg();
4768 unsigned ptrB = MI->getOperand(2).getReg();
4769 unsigned oldval = MI->getOperand(3).getReg();
4770 unsigned newval = MI->getOperand(4).getReg();
4771 DebugLoc dl = MI->getDebugLoc();
4773 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4774 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4775 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4776 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4777 F->insert(It, loop1MBB);
4778 F->insert(It, loop2MBB);
4779 F->insert(It, midMBB);
4780 F->insert(It, exitMBB);
4781 exitMBB->transferSuccessors(BB);
4785 // fallthrough --> loopMBB
4786 BB->addSuccessor(loop1MBB);
4789 // l[wd]arx dest, ptr
4790 // cmp[wd] dest, oldval
4793 // st[wd]cx. newval, ptr
4797 // st[wd]cx. dest, ptr
4800 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4801 .addReg(ptrA).addReg(ptrB);
4802 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
4803 .addReg(oldval).addReg(dest);
4804 BuildMI(BB, dl, TII->get(PPC::BCC))
4805 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4806 BB->addSuccessor(loop2MBB);
4807 BB->addSuccessor(midMBB);
4810 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4811 .addReg(newval).addReg(ptrA).addReg(ptrB);
4812 BuildMI(BB, dl, TII->get(PPC::BCC))
4813 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4814 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4815 BB->addSuccessor(loop1MBB);
4816 BB->addSuccessor(exitMBB);
4819 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4820 .addReg(dest).addReg(ptrA).addReg(ptrB);
4821 BB->addSuccessor(exitMBB);
4826 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
4827 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
4828 // We must use 64-bit registers for addresses when targeting 64-bit,
4829 // since we're actually doing arithmetic on them. Other registers
4831 bool is64bit = PPCSubTarget.isPPC64();
4832 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
4834 unsigned dest = MI->getOperand(0).getReg();
4835 unsigned ptrA = MI->getOperand(1).getReg();
4836 unsigned ptrB = MI->getOperand(2).getReg();
4837 unsigned oldval = MI->getOperand(3).getReg();
4838 unsigned newval = MI->getOperand(4).getReg();
4839 DebugLoc dl = MI->getDebugLoc();
4841 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4842 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4843 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4844 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4845 F->insert(It, loop1MBB);
4846 F->insert(It, loop2MBB);
4847 F->insert(It, midMBB);
4848 F->insert(It, exitMBB);
4849 exitMBB->transferSuccessors(BB);
4851 MachineRegisterInfo &RegInfo = F->getRegInfo();
4852 const TargetRegisterClass *RC =
4853 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4854 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4855 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4856 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4857 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4858 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
4859 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
4860 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
4861 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
4862 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4863 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4864 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4865 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4866 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4867 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4869 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
4872 // fallthrough --> loopMBB
4873 BB->addSuccessor(loop1MBB);
4875 // The 4-byte load must be aligned, while a char or short may be
4876 // anywhere in the word. Hence all this nasty bookkeeping code.
4877 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4878 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4879 // xori shift, shift1, 24 [16]
4880 // rlwinm ptr, ptr1, 0, 0, 29
4881 // slw newval2, newval, shift
4882 // slw oldval2, oldval,shift
4883 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4884 // slw mask, mask2, shift
4885 // and newval3, newval2, mask
4886 // and oldval3, oldval2, mask
4888 // lwarx tmpDest, ptr
4889 // and tmp, tmpDest, mask
4890 // cmpw tmp, oldval3
4893 // andc tmp2, tmpDest, mask
4894 // or tmp4, tmp2, newval3
4899 // stwcx. tmpDest, ptr
4901 // srw dest, tmpDest, shift
4902 if (ptrA!=PPC::R0) {
4903 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4904 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4905 .addReg(ptrA).addReg(ptrB);
4909 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4910 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4911 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4912 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4914 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4915 .addReg(Ptr1Reg).addImm(0).addImm(61);
4917 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4918 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4919 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
4920 .addReg(newval).addReg(ShiftReg);
4921 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
4922 .addReg(oldval).addReg(ShiftReg);
4924 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4926 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4927 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
4928 .addReg(Mask3Reg).addImm(65535);
4930 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4931 .addReg(Mask2Reg).addReg(ShiftReg);
4932 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
4933 .addReg(NewVal2Reg).addReg(MaskReg);
4934 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
4935 .addReg(OldVal2Reg).addReg(MaskReg);
4938 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4939 .addReg(PPC::R0).addReg(PtrReg);
4940 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
4941 .addReg(TmpDestReg).addReg(MaskReg);
4942 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
4943 .addReg(TmpReg).addReg(OldVal3Reg);
4944 BuildMI(BB, dl, TII->get(PPC::BCC))
4945 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4946 BB->addSuccessor(loop2MBB);
4947 BB->addSuccessor(midMBB);
4950 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
4951 .addReg(TmpDestReg).addReg(MaskReg);
4952 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
4953 .addReg(Tmp2Reg).addReg(NewVal3Reg);
4954 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
4955 .addReg(PPC::R0).addReg(PtrReg);
4956 BuildMI(BB, dl, TII->get(PPC::BCC))
4957 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4958 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4959 BB->addSuccessor(loop1MBB);
4960 BB->addSuccessor(exitMBB);
4963 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
4964 .addReg(PPC::R0).addReg(PtrReg);
4965 BB->addSuccessor(exitMBB);
4970 BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
4972 llvm_unreachable("Unexpected instr type to insert");
4975 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
4979 //===----------------------------------------------------------------------===//
4980 // Target Optimization Hooks
4981 //===----------------------------------------------------------------------===//
4983 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
4984 DAGCombinerInfo &DCI) const {
4985 TargetMachine &TM = getTargetMachine();
4986 SelectionDAG &DAG = DCI.DAG;
4987 DebugLoc dl = N->getDebugLoc();
4988 switch (N->getOpcode()) {
4991 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4992 if (C->getZExtValue() == 0) // 0 << V -> 0.
4993 return N->getOperand(0);
4997 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4998 if (C->getZExtValue() == 0) // 0 >>u V -> 0.
4999 return N->getOperand(0);
5003 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5004 if (C->getZExtValue() == 0 || // 0 >>s V -> 0.
5005 C->isAllOnesValue()) // -1 >>s V -> -1.
5006 return N->getOperand(0);
5010 case ISD::SINT_TO_FP:
5011 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
5012 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
5013 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
5014 // We allow the src/dst to be either f32/f64, but the intermediate
5015 // type must be i64.
5016 if (N->getOperand(0).getValueType() == MVT::i64 &&
5017 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
5018 SDValue Val = N->getOperand(0).getOperand(0);
5019 if (Val.getValueType() == MVT::f32) {
5020 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5021 DCI.AddToWorklist(Val.getNode());
5024 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
5025 DCI.AddToWorklist(Val.getNode());
5026 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
5027 DCI.AddToWorklist(Val.getNode());
5028 if (N->getValueType(0) == MVT::f32) {
5029 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
5030 DAG.getIntPtrConstant(0));
5031 DCI.AddToWorklist(Val.getNode());
5034 } else if (N->getOperand(0).getValueType() == MVT::i32) {
5035 // If the intermediate type is i32, we can avoid the load/store here
5042 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
5043 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
5044 !cast<StoreSDNode>(N)->isTruncatingStore() &&
5045 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
5046 N->getOperand(1).getValueType() == MVT::i32 &&
5047 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
5048 SDValue Val = N->getOperand(1).getOperand(0);
5049 if (Val.getValueType() == MVT::f32) {
5050 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5051 DCI.AddToWorklist(Val.getNode());
5053 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
5054 DCI.AddToWorklist(Val.getNode());
5056 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
5057 N->getOperand(2), N->getOperand(3));
5058 DCI.AddToWorklist(Val.getNode());
5062 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
5063 if (cast<StoreSDNode>(N)->isUnindexed() &&
5064 N->getOperand(1).getOpcode() == ISD::BSWAP &&
5065 N->getOperand(1).getNode()->hasOneUse() &&
5066 (N->getOperand(1).getValueType() == MVT::i32 ||
5067 N->getOperand(1).getValueType() == MVT::i16)) {
5068 SDValue BSwapOp = N->getOperand(1).getOperand(0);
5069 // Do an any-extend to 32-bits if this is a half-word input.
5070 if (BSwapOp.getValueType() == MVT::i16)
5071 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
5074 N->getOperand(0), BSwapOp, N->getOperand(2),
5075 DAG.getValueType(N->getOperand(1).getValueType())
5078 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
5079 Ops, array_lengthof(Ops),
5080 cast<StoreSDNode>(N)->getMemoryVT(),
5081 cast<StoreSDNode>(N)->getMemOperand());
5085 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
5086 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
5087 N->getOperand(0).hasOneUse() &&
5088 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
5089 SDValue Load = N->getOperand(0);
5090 LoadSDNode *LD = cast<LoadSDNode>(Load);
5091 // Create the byte-swapping load.
5093 LD->getChain(), // Chain
5094 LD->getBasePtr(), // Ptr
5095 DAG.getValueType(N->getValueType(0)) // VT
5098 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
5099 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3,
5100 LD->getMemoryVT(), LD->getMemOperand());
5102 // If this is an i16 load, insert the truncate.
5103 SDValue ResVal = BSLoad;
5104 if (N->getValueType(0) == MVT::i16)
5105 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
5107 // First, combine the bswap away. This makes the value produced by the
5109 DCI.CombineTo(N, ResVal);
5111 // Next, combine the load away, we give it a bogus result value but a real
5112 // chain result. The result value is dead because the bswap is dead.
5113 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
5115 // Return N so it doesn't get rechecked!
5116 return SDValue(N, 0);
5120 case PPCISD::VCMP: {
5121 // If a VCMPo node already exists with exactly the same operands as this
5122 // node, use its result instead of this node (VCMPo computes both a CR6 and
5123 // a normal output).
5125 if (!N->getOperand(0).hasOneUse() &&
5126 !N->getOperand(1).hasOneUse() &&
5127 !N->getOperand(2).hasOneUse()) {
5129 // Scan all of the users of the LHS, looking for VCMPo's that match.
5130 SDNode *VCMPoNode = 0;
5132 SDNode *LHSN = N->getOperand(0).getNode();
5133 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
5135 if (UI->getOpcode() == PPCISD::VCMPo &&
5136 UI->getOperand(1) == N->getOperand(1) &&
5137 UI->getOperand(2) == N->getOperand(2) &&
5138 UI->getOperand(0) == N->getOperand(0)) {
5143 // If there is no VCMPo node, or if the flag value has a single use, don't
5145 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
5148 // Look at the (necessarily single) use of the flag value. If it has a
5149 // chain, this transformation is more complex. Note that multiple things
5150 // could use the value result, which we should ignore.
5151 SDNode *FlagUser = 0;
5152 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
5153 FlagUser == 0; ++UI) {
5154 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
5156 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
5157 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
5164 // If the user is a MFCR instruction, we know this is safe. Otherwise we
5165 // give up for right now.
5166 if (FlagUser->getOpcode() == PPCISD::MFCR)
5167 return SDValue(VCMPoNode, 0);
5172 // If this is a branch on an altivec predicate comparison, lower this so
5173 // that we don't have to do a MFCR: instead, branch directly on CR6. This
5174 // lowering is done pre-legalize, because the legalizer lowers the predicate
5175 // compare down to code that is difficult to reassemble.
5176 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
5177 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
5181 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
5182 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
5183 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
5184 assert(isDot && "Can't compare against a vector result!");
5186 // If this is a comparison against something other than 0/1, then we know
5187 // that the condition is never/always true.
5188 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
5189 if (Val != 0 && Val != 1) {
5190 if (CC == ISD::SETEQ) // Cond never true, remove branch.
5191 return N->getOperand(0);
5192 // Always !=, turn it into an unconditional branch.
5193 return DAG.getNode(ISD::BR, dl, MVT::Other,
5194 N->getOperand(0), N->getOperand(4));
5197 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
5199 // Create the PPCISD altivec 'dot' comparison node.
5200 std::vector<EVT> VTs;
5202 LHS.getOperand(2), // LHS of compare
5203 LHS.getOperand(3), // RHS of compare
5204 DAG.getConstant(CompareOpc, MVT::i32)
5206 VTs.push_back(LHS.getOperand(2).getValueType());
5207 VTs.push_back(MVT::Flag);
5208 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5210 // Unpack the result based on how the target uses it.
5211 PPC::Predicate CompOpc;
5212 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
5213 default: // Can't happen, don't crash on invalid number though.
5214 case 0: // Branch on the value of the EQ bit of CR6.
5215 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
5217 case 1: // Branch on the inverted value of the EQ bit of CR6.
5218 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
5220 case 2: // Branch on the value of the LT bit of CR6.
5221 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
5223 case 3: // Branch on the inverted value of the LT bit of CR6.
5224 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
5228 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
5229 DAG.getConstant(CompOpc, MVT::i32),
5230 DAG.getRegister(PPC::CR6, MVT::i32),
5231 N->getOperand(4), CompNode.getValue(1));
5240 //===----------------------------------------------------------------------===//
5241 // Inline Assembly Support
5242 //===----------------------------------------------------------------------===//
5244 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5248 const SelectionDAG &DAG,
5249 unsigned Depth) const {
5250 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5251 switch (Op.getOpcode()) {
5253 case PPCISD::LBRX: {
5254 // lhbrx is known to have the top bits cleared out.
5255 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
5256 KnownZero = 0xFFFF0000;
5259 case ISD::INTRINSIC_WO_CHAIN: {
5260 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
5262 case Intrinsic::ppc_altivec_vcmpbfp_p:
5263 case Intrinsic::ppc_altivec_vcmpeqfp_p:
5264 case Intrinsic::ppc_altivec_vcmpequb_p:
5265 case Intrinsic::ppc_altivec_vcmpequh_p:
5266 case Intrinsic::ppc_altivec_vcmpequw_p:
5267 case Intrinsic::ppc_altivec_vcmpgefp_p:
5268 case Intrinsic::ppc_altivec_vcmpgtfp_p:
5269 case Intrinsic::ppc_altivec_vcmpgtsb_p:
5270 case Intrinsic::ppc_altivec_vcmpgtsh_p:
5271 case Intrinsic::ppc_altivec_vcmpgtsw_p:
5272 case Intrinsic::ppc_altivec_vcmpgtub_p:
5273 case Intrinsic::ppc_altivec_vcmpgtuh_p:
5274 case Intrinsic::ppc_altivec_vcmpgtuw_p:
5275 KnownZero = ~1U; // All bits but the low one are known to be zero.
5283 /// getConstraintType - Given a constraint, return the type of
5284 /// constraint it is for this target.
5285 PPCTargetLowering::ConstraintType
5286 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
5287 if (Constraint.size() == 1) {
5288 switch (Constraint[0]) {
5295 return C_RegisterClass;
5298 return TargetLowering::getConstraintType(Constraint);
5301 std::pair<unsigned, const TargetRegisterClass*>
5302 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5304 if (Constraint.size() == 1) {
5305 // GCC RS6000 Constraint Letters
5306 switch (Constraint[0]) {
5309 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
5310 return std::make_pair(0U, PPC::G8RCRegisterClass);
5311 return std::make_pair(0U, PPC::GPRCRegisterClass);
5314 return std::make_pair(0U, PPC::F4RCRegisterClass);
5315 else if (VT == MVT::f64)
5316 return std::make_pair(0U, PPC::F8RCRegisterClass);
5319 return std::make_pair(0U, PPC::VRRCRegisterClass);
5321 return std::make_pair(0U, PPC::CRRCRegisterClass);
5325 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5329 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5330 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
5331 /// it means one of the asm constraint of the inline asm instruction being
5332 /// processed is 'm'.
5333 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
5335 std::vector<SDValue>&Ops,
5336 SelectionDAG &DAG) const {
5337 SDValue Result(0,0);
5348 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
5349 if (!CST) return; // Must be an immediate to match.
5350 unsigned Value = CST->getZExtValue();
5352 default: llvm_unreachable("Unknown constraint letter!");
5353 case 'I': // "I" is a signed 16-bit constant.
5354 if ((short)Value == (int)Value)
5355 Result = DAG.getTargetConstant(Value, Op.getValueType());
5357 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
5358 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
5359 if ((short)Value == 0)
5360 Result = DAG.getTargetConstant(Value, Op.getValueType());
5362 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
5363 if ((Value >> 16) == 0)
5364 Result = DAG.getTargetConstant(Value, Op.getValueType());
5366 case 'M': // "M" is a constant that is greater than 31.
5368 Result = DAG.getTargetConstant(Value, Op.getValueType());
5370 case 'N': // "N" is a positive constant that is an exact power of two.
5371 if ((int)Value > 0 && isPowerOf2_32(Value))
5372 Result = DAG.getTargetConstant(Value, Op.getValueType());
5374 case 'O': // "O" is the constant zero.
5376 Result = DAG.getTargetConstant(Value, Op.getValueType());
5378 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
5379 if ((short)-Value == (int)-Value)
5380 Result = DAG.getTargetConstant(Value, Op.getValueType());
5387 if (Result.getNode()) {
5388 Ops.push_back(Result);
5392 // Handle standard constraint letters.
5393 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, hasMemory, Ops, DAG);
5396 // isLegalAddressingMode - Return true if the addressing mode represented
5397 // by AM is legal for this target, for a load/store of the specified type.
5398 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5399 const Type *Ty) const {
5400 // FIXME: PPC does not allow r+i addressing modes for vectors!
5402 // PPC allows a sign-extended 16-bit immediate field.
5403 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
5406 // No global is ever allowed as a base.
5410 // PPC only support r+r,
5412 case 0: // "r+i" or just "i", depending on HasBaseReg.
5415 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
5417 // Otherwise we have r+r or r+i.
5420 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
5422 // Allow 2*r as r+r.
5425 // No other scales are supported.
5432 /// isLegalAddressImmediate - Return true if the integer value can be used
5433 /// as the offset of the target addressing mode for load / store of the
5435 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
5436 // PPC allows a sign-extended 16-bit immediate field.
5437 return (V > -(1 << 16) && V < (1 << 16)-1);
5440 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
5444 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
5445 DebugLoc dl = Op.getDebugLoc();
5446 // Depths > 0 not supported yet!
5447 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5450 MachineFunction &MF = DAG.getMachineFunction();
5451 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
5453 // Just load the return address off the stack.
5454 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
5456 // Make sure the function really does not optimize away the store of the RA
5458 FuncInfo->setLRStoreRequired();
5459 return DAG.getLoad(getPointerTy(), dl,
5460 DAG.getEntryNode(), RetAddrFI, NULL, 0);
5463 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
5464 DebugLoc dl = Op.getDebugLoc();
5465 // Depths > 0 not supported yet!
5466 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
5469 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5470 bool isPPC64 = PtrVT == MVT::i64;
5472 MachineFunction &MF = DAG.getMachineFunction();
5473 MachineFrameInfo *MFI = MF.getFrameInfo();
5474 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
5475 && MFI->getStackSize();
5478 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::X31 : PPC::X1,
5481 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::R31 : PPC::R1,
5486 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5487 // The PowerPC target isn't yet aware of offsets.
5491 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size, unsigned Align,
5492 bool isSrcConst, bool isSrcStr,
5493 SelectionDAG &DAG) const {
5494 if (this->PPCSubTarget.isPPC64()) {