1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPerfectShuffle.h"
17 #include "PPCPredicates.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/CallingConv.h"
30 #include "llvm/Constants.h"
31 #include "llvm/Function.h"
32 #include "llvm/Intrinsics.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/DerivedTypes.h"
41 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
42 CCValAssign::LocInfo &LocInfo,
43 ISD::ArgFlagsTy &ArgFlags,
45 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
47 CCValAssign::LocInfo &LocInfo,
48 ISD::ArgFlagsTy &ArgFlags,
50 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
52 CCValAssign::LocInfo &LocInfo,
53 ISD::ArgFlagsTy &ArgFlags,
56 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
57 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
60 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
61 if (TM.getSubtargetImpl()->isDarwin())
62 return new TargetLoweringObjectFileMachO();
64 return new TargetLoweringObjectFileELF();
67 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
72 // Use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(true);
76 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
77 // arguments are at least 4/8 bytes aligned.
78 setMinStackArgumentAlignment(TM.getSubtarget<PPCSubtarget>().isPPC64() ? 8:4);
80 // Set up the register classes.
81 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
82 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
83 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
85 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
86 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
89 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
91 // PowerPC has pre-inc load and store's.
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
94 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
95 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
96 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
101 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
103 // This is used in the ppcf128->int sequence. Note it has different semantics
104 // from FP_ROUND: that rounds to nearest, this rounds to zero.
105 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
107 // PowerPC has no SREM/UREM instructions
108 setOperationAction(ISD::SREM, MVT::i32, Expand);
109 setOperationAction(ISD::UREM, MVT::i32, Expand);
110 setOperationAction(ISD::SREM, MVT::i64, Expand);
111 setOperationAction(ISD::UREM, MVT::i64, Expand);
113 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
114 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
115 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
116 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
117 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
118 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
119 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
121 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
123 // We don't support sin/cos/sqrt/fmod/pow
124 setOperationAction(ISD::FSIN , MVT::f64, Expand);
125 setOperationAction(ISD::FCOS , MVT::f64, Expand);
126 setOperationAction(ISD::FREM , MVT::f64, Expand);
127 setOperationAction(ISD::FPOW , MVT::f64, Expand);
128 setOperationAction(ISD::FSIN , MVT::f32, Expand);
129 setOperationAction(ISD::FCOS , MVT::f32, Expand);
130 setOperationAction(ISD::FREM , MVT::f32, Expand);
131 setOperationAction(ISD::FPOW , MVT::f32, Expand);
133 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
135 // If we're enabling GP optimizations, use hardware square root
136 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
137 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
138 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
141 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
142 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
144 // PowerPC does not have BSWAP, CTPOP or CTTZ
145 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
146 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
147 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
148 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
149 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
150 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
152 // PowerPC does not have ROTR
153 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
154 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
156 // PowerPC does not have Select
157 setOperationAction(ISD::SELECT, MVT::i32, Expand);
158 setOperationAction(ISD::SELECT, MVT::i64, Expand);
159 setOperationAction(ISD::SELECT, MVT::f32, Expand);
160 setOperationAction(ISD::SELECT, MVT::f64, Expand);
162 // PowerPC wants to turn select_cc of FP into fsel when possible.
163 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
164 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
166 // PowerPC wants to optimize integer setcc a bit
167 setOperationAction(ISD::SETCC, MVT::i32, Custom);
169 // PowerPC does not have BRCOND which requires SetCC
170 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
172 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
174 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
175 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
177 // PowerPC does not have [U|S]INT_TO_FP
178 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
179 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
181 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
182 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
183 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
184 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
186 // We cannot sextinreg(i1). Expand to shifts.
187 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
189 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
190 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
191 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
192 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
195 // We want to legalize GlobalAddress and ConstantPool nodes into the
196 // appropriate instructions to materialize the address.
197 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
198 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
199 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
200 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
201 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
202 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
203 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
204 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
205 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
206 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
209 setOperationAction(ISD::TRAP, MVT::Other, Legal);
211 // TRAMPOLINE is custom lowered.
212 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
214 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
215 setOperationAction(ISD::VASTART , MVT::Other, Custom);
217 // VAARG is custom lowered with the 32-bit SVR4 ABI.
218 if ( TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
219 && !TM.getSubtarget<PPCSubtarget>().isPPC64())
220 setOperationAction(ISD::VAARG, MVT::Other, Custom);
222 setOperationAction(ISD::VAARG, MVT::Other, Expand);
224 // Use the default implementation.
225 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
226 setOperationAction(ISD::VAEND , MVT::Other, Expand);
227 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
228 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
229 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
230 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
232 // We want to custom lower some of our intrinsics.
233 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
235 // Comparisons that require checking two conditions.
236 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
237 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
238 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
239 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
240 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
243 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
244 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
247 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
249 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
250 // They also have instructions for converting between i64 and fp.
251 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
252 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
253 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
254 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
255 // This is just the low 32 bits of a (signed) fp->i64 conversion.
256 // We cannot do this with Promote because i64 is not a legal type.
257 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
259 // FIXME: disable this lowered code. This generates 64-bit register values,
260 // and we don't model the fact that the top part is clobbered by calls. We
261 // need to flag these together so that the value isn't live across a call.
262 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
264 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
265 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
268 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
269 // 64-bit PowerPC implementations can support i64 types directly
270 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
271 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
272 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
273 // 64-bit PowerPC wants to expand i128 shifts itself.
274 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
275 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
276 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
278 // 32-bit PowerPC wants to expand i64 shifts itself.
279 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
280 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
281 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
284 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
285 // First set operation action for all vector types to expand. Then we
286 // will selectively turn on ones that can be effectively codegen'd.
287 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
288 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
289 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
291 // add/sub are legal for all supported vector VT's.
292 setOperationAction(ISD::ADD , VT, Legal);
293 setOperationAction(ISD::SUB , VT, Legal);
295 // We promote all shuffles to v16i8.
296 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
297 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
299 // We promote all non-typed operations to v4i32.
300 setOperationAction(ISD::AND , VT, Promote);
301 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
302 setOperationAction(ISD::OR , VT, Promote);
303 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
304 setOperationAction(ISD::XOR , VT, Promote);
305 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
306 setOperationAction(ISD::LOAD , VT, Promote);
307 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
308 setOperationAction(ISD::SELECT, VT, Promote);
309 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
310 setOperationAction(ISD::STORE, VT, Promote);
311 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
313 // No other operations are legal.
314 setOperationAction(ISD::MUL , VT, Expand);
315 setOperationAction(ISD::SDIV, VT, Expand);
316 setOperationAction(ISD::SREM, VT, Expand);
317 setOperationAction(ISD::UDIV, VT, Expand);
318 setOperationAction(ISD::UREM, VT, Expand);
319 setOperationAction(ISD::FDIV, VT, Expand);
320 setOperationAction(ISD::FNEG, VT, Expand);
321 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
322 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
323 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
324 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
325 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
326 setOperationAction(ISD::UDIVREM, VT, Expand);
327 setOperationAction(ISD::SDIVREM, VT, Expand);
328 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
329 setOperationAction(ISD::FPOW, VT, Expand);
330 setOperationAction(ISD::CTPOP, VT, Expand);
331 setOperationAction(ISD::CTLZ, VT, Expand);
332 setOperationAction(ISD::CTTZ, VT, Expand);
335 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
336 // with merges, splats, etc.
337 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
339 setOperationAction(ISD::AND , MVT::v4i32, Legal);
340 setOperationAction(ISD::OR , MVT::v4i32, Legal);
341 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
342 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
343 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
344 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
346 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
347 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
348 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
349 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
351 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
352 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
353 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
354 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
356 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
357 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
359 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
360 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
361 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
362 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
365 setShiftAmountType(MVT::i32);
366 setBooleanContents(ZeroOrOneBooleanContent);
368 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
369 setStackPointerRegisterToSaveRestore(PPC::X1);
370 setExceptionPointerRegister(PPC::X3);
371 setExceptionSelectorRegister(PPC::X4);
373 setStackPointerRegisterToSaveRestore(PPC::R1);
374 setExceptionPointerRegister(PPC::R3);
375 setExceptionSelectorRegister(PPC::R4);
378 // We have target-specific dag combine patterns for the following nodes:
379 setTargetDAGCombine(ISD::SINT_TO_FP);
380 setTargetDAGCombine(ISD::STORE);
381 setTargetDAGCombine(ISD::BR_CC);
382 setTargetDAGCombine(ISD::BSWAP);
384 // Darwin long double math library functions have $LDBL128 appended.
385 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
386 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
387 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
388 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
389 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
390 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
391 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
392 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
393 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
394 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
395 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
398 computeRegisterProperties();
401 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
402 /// function arguments in the caller parameter area.
403 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
404 const TargetMachine &TM = getTargetMachine();
405 // Darwin passes everything on 4 byte boundary.
406 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
412 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
415 case PPCISD::FSEL: return "PPCISD::FSEL";
416 case PPCISD::FCFID: return "PPCISD::FCFID";
417 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
418 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
419 case PPCISD::STFIWX: return "PPCISD::STFIWX";
420 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
421 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
422 case PPCISD::VPERM: return "PPCISD::VPERM";
423 case PPCISD::Hi: return "PPCISD::Hi";
424 case PPCISD::Lo: return "PPCISD::Lo";
425 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
426 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
427 case PPCISD::LOAD: return "PPCISD::LOAD";
428 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
429 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
430 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
431 case PPCISD::SRL: return "PPCISD::SRL";
432 case PPCISD::SRA: return "PPCISD::SRA";
433 case PPCISD::SHL: return "PPCISD::SHL";
434 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
435 case PPCISD::STD_32: return "PPCISD::STD_32";
436 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4";
437 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin";
438 case PPCISD::NOP: return "PPCISD::NOP";
439 case PPCISD::MTCTR: return "PPCISD::MTCTR";
440 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin";
441 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4";
442 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
443 case PPCISD::MFCR: return "PPCISD::MFCR";
444 case PPCISD::VCMP: return "PPCISD::VCMP";
445 case PPCISD::VCMPo: return "PPCISD::VCMPo";
446 case PPCISD::LBRX: return "PPCISD::LBRX";
447 case PPCISD::STBRX: return "PPCISD::STBRX";
448 case PPCISD::LARX: return "PPCISD::LARX";
449 case PPCISD::STCX: return "PPCISD::STCX";
450 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
451 case PPCISD::MFFS: return "PPCISD::MFFS";
452 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
453 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
454 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
455 case PPCISD::MTFSF: return "PPCISD::MTFSF";
456 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
460 MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const {
464 /// getFunctionAlignment - Return the Log2 alignment of this function.
465 unsigned PPCTargetLowering::getFunctionAlignment(const Function *F) const {
466 if (getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin())
467 return F->hasFnAttr(Attribute::OptimizeForSize) ? 2 : 4;
472 //===----------------------------------------------------------------------===//
473 // Node matching predicates, for use by the tblgen matching code.
474 //===----------------------------------------------------------------------===//
476 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
477 static bool isFloatingPointZero(SDValue Op) {
478 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
479 return CFP->getValueAPF().isZero();
480 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
481 // Maybe this has already been legalized into the constant pool?
482 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
483 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
484 return CFP->getValueAPF().isZero();
489 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
490 /// true if Op is undef or if it matches the specified value.
491 static bool isConstantOrUndef(int Op, int Val) {
492 return Op < 0 || Op == Val;
495 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
496 /// VPKUHUM instruction.
497 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
499 for (unsigned i = 0; i != 16; ++i)
500 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
503 for (unsigned i = 0; i != 8; ++i)
504 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
505 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
511 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
512 /// VPKUWUM instruction.
513 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
515 for (unsigned i = 0; i != 16; i += 2)
516 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
517 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
520 for (unsigned i = 0; i != 8; i += 2)
521 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
522 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
523 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
524 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
530 /// isVMerge - Common function, used to match vmrg* shuffles.
532 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
533 unsigned LHSStart, unsigned RHSStart) {
534 assert(N->getValueType(0) == MVT::v16i8 &&
535 "PPC only supports shuffles by bytes!");
536 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
537 "Unsupported merge size!");
539 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
540 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
541 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
542 LHSStart+j+i*UnitSize) ||
543 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
544 RHSStart+j+i*UnitSize))
550 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
551 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
552 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
555 return isVMerge(N, UnitSize, 8, 24);
556 return isVMerge(N, UnitSize, 8, 8);
559 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
560 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
561 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
564 return isVMerge(N, UnitSize, 0, 16);
565 return isVMerge(N, UnitSize, 0, 0);
569 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
570 /// amount, otherwise return -1.
571 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
572 assert(N->getValueType(0) == MVT::v16i8 &&
573 "PPC only supports shuffles by bytes!");
575 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
577 // Find the first non-undef value in the shuffle mask.
579 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
582 if (i == 16) return -1; // all undef.
584 // Otherwise, check to see if the rest of the elements are consecutively
585 // numbered from this value.
586 unsigned ShiftAmt = SVOp->getMaskElt(i);
587 if (ShiftAmt < i) return -1;
591 // Check the rest of the elements to see if they are consecutive.
592 for (++i; i != 16; ++i)
593 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
596 // Check the rest of the elements to see if they are consecutive.
597 for (++i; i != 16; ++i)
598 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
604 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
605 /// specifies a splat of a single element that is suitable for input to
606 /// VSPLTB/VSPLTH/VSPLTW.
607 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
608 assert(N->getValueType(0) == MVT::v16i8 &&
609 (EltSize == 1 || EltSize == 2 || EltSize == 4));
611 // This is a splat operation if each element of the permute is the same, and
612 // if the value doesn't reference the second vector.
613 unsigned ElementBase = N->getMaskElt(0);
615 // FIXME: Handle UNDEF elements too!
616 if (ElementBase >= 16)
619 // Check that the indices are consecutive, in the case of a multi-byte element
620 // splatted with a v16i8 mask.
621 for (unsigned i = 1; i != EltSize; ++i)
622 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
625 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
626 if (N->getMaskElt(i) < 0) continue;
627 for (unsigned j = 0; j != EltSize; ++j)
628 if (N->getMaskElt(i+j) != N->getMaskElt(j))
634 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
636 bool PPC::isAllNegativeZeroVector(SDNode *N) {
637 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
639 APInt APVal, APUndef;
643 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
644 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
645 return CFP->getValueAPF().isNegZero();
650 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
651 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
652 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
653 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
654 assert(isSplatShuffleMask(SVOp, EltSize));
655 return SVOp->getMaskElt(0) / EltSize;
658 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
659 /// by using a vspltis[bhw] instruction of the specified element size, return
660 /// the constant being splatted. The ByteSize field indicates the number of
661 /// bytes of each element [124] -> [bhw].
662 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
665 // If ByteSize of the splat is bigger than the element size of the
666 // build_vector, then we have a case where we are checking for a splat where
667 // multiple elements of the buildvector are folded together into a single
668 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
669 unsigned EltSize = 16/N->getNumOperands();
670 if (EltSize < ByteSize) {
671 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
672 SDValue UniquedVals[4];
673 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
675 // See if all of the elements in the buildvector agree across.
676 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
677 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
678 // If the element isn't a constant, bail fully out.
679 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
682 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
683 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
684 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
685 return SDValue(); // no match.
688 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
689 // either constant or undef values that are identical for each chunk. See
690 // if these chunks can form into a larger vspltis*.
692 // Check to see if all of the leading entries are either 0 or -1. If
693 // neither, then this won't fit into the immediate field.
694 bool LeadingZero = true;
695 bool LeadingOnes = true;
696 for (unsigned i = 0; i != Multiple-1; ++i) {
697 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
699 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
700 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
702 // Finally, check the least significant entry.
704 if (UniquedVals[Multiple-1].getNode() == 0)
705 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
706 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
708 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
711 if (UniquedVals[Multiple-1].getNode() == 0)
712 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
713 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
714 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
715 return DAG.getTargetConstant(Val, MVT::i32);
721 // Check to see if this buildvec has a single non-undef value in its elements.
722 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
723 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
724 if (OpVal.getNode() == 0)
725 OpVal = N->getOperand(i);
726 else if (OpVal != N->getOperand(i))
730 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
732 unsigned ValSizeInBytes = EltSize;
734 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
735 Value = CN->getZExtValue();
736 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
737 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
738 Value = FloatToBits(CN->getValueAPF().convertToFloat());
741 // If the splat value is larger than the element value, then we can never do
742 // this splat. The only case that we could fit the replicated bits into our
743 // immediate field for would be zero, and we prefer to use vxor for it.
744 if (ValSizeInBytes < ByteSize) return SDValue();
746 // If the element value is larger than the splat value, cut it in half and
747 // check to see if the two halves are equal. Continue doing this until we
748 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
749 while (ValSizeInBytes > ByteSize) {
750 ValSizeInBytes >>= 1;
752 // If the top half equals the bottom half, we're still ok.
753 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
754 (Value & ((1 << (8*ValSizeInBytes))-1)))
758 // Properly sign extend the value.
759 int ShAmt = (4-ByteSize)*8;
760 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
762 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
763 if (MaskVal == 0) return SDValue();
765 // Finally, if this value fits in a 5 bit sext field, return it
766 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
767 return DAG.getTargetConstant(MaskVal, MVT::i32);
771 //===----------------------------------------------------------------------===//
772 // Addressing Mode Selection
773 //===----------------------------------------------------------------------===//
775 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
776 /// or 64-bit immediate, and if the value can be accurately represented as a
777 /// sign extension from a 16-bit value. If so, this returns true and the
779 static bool isIntS16Immediate(SDNode *N, short &Imm) {
780 if (N->getOpcode() != ISD::Constant)
783 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
784 if (N->getValueType(0) == MVT::i32)
785 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
787 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
789 static bool isIntS16Immediate(SDValue Op, short &Imm) {
790 return isIntS16Immediate(Op.getNode(), Imm);
794 /// SelectAddressRegReg - Given the specified addressed, check to see if it
795 /// can be represented as an indexed [r+r] operation. Returns false if it
796 /// can be more efficiently represented with [r+imm].
797 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
799 SelectionDAG &DAG) const {
801 if (N.getOpcode() == ISD::ADD) {
802 if (isIntS16Immediate(N.getOperand(1), imm))
804 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
807 Base = N.getOperand(0);
808 Index = N.getOperand(1);
810 } else if (N.getOpcode() == ISD::OR) {
811 if (isIntS16Immediate(N.getOperand(1), imm))
812 return false; // r+i can fold it if we can.
814 // If this is an or of disjoint bitfields, we can codegen this as an add
815 // (for better address arithmetic) if the LHS and RHS of the OR are provably
817 APInt LHSKnownZero, LHSKnownOne;
818 APInt RHSKnownZero, RHSKnownOne;
819 DAG.ComputeMaskedBits(N.getOperand(0),
820 APInt::getAllOnesValue(N.getOperand(0)
821 .getValueSizeInBits()),
822 LHSKnownZero, LHSKnownOne);
824 if (LHSKnownZero.getBoolValue()) {
825 DAG.ComputeMaskedBits(N.getOperand(1),
826 APInt::getAllOnesValue(N.getOperand(1)
827 .getValueSizeInBits()),
828 RHSKnownZero, RHSKnownOne);
829 // If all of the bits are known zero on the LHS or RHS, the add won't
831 if (~(LHSKnownZero | RHSKnownZero) == 0) {
832 Base = N.getOperand(0);
833 Index = N.getOperand(1);
842 /// Returns true if the address N can be represented by a base register plus
843 /// a signed 16-bit displacement [r+imm], and if it is not better
844 /// represented as reg+reg.
845 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
847 SelectionDAG &DAG) const {
848 // FIXME dl should come from parent load or store, not from address
849 DebugLoc dl = N.getDebugLoc();
850 // If this can be more profitably realized as r+r, fail.
851 if (SelectAddressRegReg(N, Disp, Base, DAG))
854 if (N.getOpcode() == ISD::ADD) {
856 if (isIntS16Immediate(N.getOperand(1), imm)) {
857 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
858 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
859 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
861 Base = N.getOperand(0);
863 return true; // [r+i]
864 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
865 // Match LOAD (ADD (X, Lo(G))).
866 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
867 && "Cannot handle constant offsets yet!");
868 Disp = N.getOperand(1).getOperand(0); // The global address.
869 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
870 Disp.getOpcode() == ISD::TargetConstantPool ||
871 Disp.getOpcode() == ISD::TargetJumpTable);
872 Base = N.getOperand(0);
873 return true; // [&g+r]
875 } else if (N.getOpcode() == ISD::OR) {
877 if (isIntS16Immediate(N.getOperand(1), imm)) {
878 // If this is an or of disjoint bitfields, we can codegen this as an add
879 // (for better address arithmetic) if the LHS and RHS of the OR are
880 // provably disjoint.
881 APInt LHSKnownZero, LHSKnownOne;
882 DAG.ComputeMaskedBits(N.getOperand(0),
883 APInt::getAllOnesValue(N.getOperand(0)
884 .getValueSizeInBits()),
885 LHSKnownZero, LHSKnownOne);
887 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
888 // If all of the bits are known zero on the LHS or RHS, the add won't
890 Base = N.getOperand(0);
891 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
895 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
896 // Loading from a constant address.
898 // If this address fits entirely in a 16-bit sext immediate field, codegen
901 if (isIntS16Immediate(CN, Imm)) {
902 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
903 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
907 // Handle 32-bit sext immediates with LIS + addr mode.
908 if (CN->getValueType(0) == MVT::i32 ||
909 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
910 int Addr = (int)CN->getZExtValue();
912 // Otherwise, break this down into an LIS + disp.
913 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
915 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
916 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
917 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
922 Disp = DAG.getTargetConstant(0, getPointerTy());
923 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
924 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
927 return true; // [r+0]
930 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
931 /// represented as an indexed [r+r] operation.
932 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
934 SelectionDAG &DAG) const {
935 // Check to see if we can easily represent this as an [r+r] address. This
936 // will fail if it thinks that the address is more profitably represented as
937 // reg+imm, e.g. where imm = 0.
938 if (SelectAddressRegReg(N, Base, Index, DAG))
941 // If the operand is an addition, always emit this as [r+r], since this is
942 // better (for code size, and execution, as the memop does the add for free)
943 // than emitting an explicit add.
944 if (N.getOpcode() == ISD::ADD) {
945 Base = N.getOperand(0);
946 Index = N.getOperand(1);
950 // Otherwise, do it the hard way, using R0 as the base register.
951 Base = DAG.getRegister(PPC::R0, N.getValueType());
956 /// SelectAddressRegImmShift - Returns true if the address N can be
957 /// represented by a base register plus a signed 14-bit displacement
958 /// [r+imm*4]. Suitable for use by STD and friends.
959 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
961 SelectionDAG &DAG) const {
962 // FIXME dl should come from the parent load or store, not the address
963 DebugLoc dl = N.getDebugLoc();
964 // If this can be more profitably realized as r+r, fail.
965 if (SelectAddressRegReg(N, Disp, Base, DAG))
968 if (N.getOpcode() == ISD::ADD) {
970 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
971 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
972 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
973 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
975 Base = N.getOperand(0);
977 return true; // [r+i]
978 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
979 // Match LOAD (ADD (X, Lo(G))).
980 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
981 && "Cannot handle constant offsets yet!");
982 Disp = N.getOperand(1).getOperand(0); // The global address.
983 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
984 Disp.getOpcode() == ISD::TargetConstantPool ||
985 Disp.getOpcode() == ISD::TargetJumpTable);
986 Base = N.getOperand(0);
987 return true; // [&g+r]
989 } else if (N.getOpcode() == ISD::OR) {
991 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
992 // If this is an or of disjoint bitfields, we can codegen this as an add
993 // (for better address arithmetic) if the LHS and RHS of the OR are
994 // provably disjoint.
995 APInt LHSKnownZero, LHSKnownOne;
996 DAG.ComputeMaskedBits(N.getOperand(0),
997 APInt::getAllOnesValue(N.getOperand(0)
998 .getValueSizeInBits()),
999 LHSKnownZero, LHSKnownOne);
1000 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1001 // If all of the bits are known zero on the LHS or RHS, the add won't
1003 Base = N.getOperand(0);
1004 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1008 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1009 // Loading from a constant address. Verify low two bits are clear.
1010 if ((CN->getZExtValue() & 3) == 0) {
1011 // If this address fits entirely in a 14-bit sext immediate field, codegen
1014 if (isIntS16Immediate(CN, Imm)) {
1015 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1016 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
1020 // Fold the low-part of 32-bit absolute addresses into addr mode.
1021 if (CN->getValueType(0) == MVT::i32 ||
1022 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1023 int Addr = (int)CN->getZExtValue();
1025 // Otherwise, break this down into an LIS + disp.
1026 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1027 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1028 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1029 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1035 Disp = DAG.getTargetConstant(0, getPointerTy());
1036 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1037 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1040 return true; // [r+0]
1044 /// getPreIndexedAddressParts - returns true by value, base pointer and
1045 /// offset pointer and addressing mode by reference if the node's address
1046 /// can be legally represented as pre-indexed load / store address.
1047 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1049 ISD::MemIndexedMode &AM,
1050 SelectionDAG &DAG) const {
1051 // Disabled by default for now.
1052 if (!EnablePPCPreinc) return false;
1056 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1057 Ptr = LD->getBasePtr();
1058 VT = LD->getMemoryVT();
1060 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1061 Ptr = ST->getBasePtr();
1062 VT = ST->getMemoryVT();
1066 // PowerPC doesn't have preinc load/store instructions for vectors.
1070 // TODO: Check reg+reg first.
1072 // LDU/STU use reg+imm*4, others use reg+imm.
1073 if (VT != MVT::i64) {
1075 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1079 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1083 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1084 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1085 // sext i32 to i64 when addr mode is r+i.
1086 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1087 LD->getExtensionType() == ISD::SEXTLOAD &&
1088 isa<ConstantSDNode>(Offset))
1096 //===----------------------------------------------------------------------===//
1097 // LowerOperation implementation
1098 //===----------------------------------------------------------------------===//
1100 /// GetLabelAccessInfo - Return true if we should reference labels using a
1101 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1102 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1103 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1104 HiOpFlags = PPCII::MO_HA16;
1105 LoOpFlags = PPCII::MO_LO16;
1107 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1108 // non-darwin platform. We don't support PIC on other platforms yet.
1109 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1110 TM.getSubtarget<PPCSubtarget>().isDarwin();
1112 HiOpFlags |= PPCII::MO_PIC_FLAG;
1113 LoOpFlags |= PPCII::MO_PIC_FLAG;
1116 // If this is a reference to a global value that requires a non-lazy-ptr, make
1117 // sure that instruction lowering adds it.
1118 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1119 HiOpFlags |= PPCII::MO_NLP_FLAG;
1120 LoOpFlags |= PPCII::MO_NLP_FLAG;
1122 if (GV->hasHiddenVisibility()) {
1123 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1124 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1131 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1132 SelectionDAG &DAG) {
1133 EVT PtrVT = HiPart.getValueType();
1134 SDValue Zero = DAG.getConstant(0, PtrVT);
1135 DebugLoc DL = HiPart.getDebugLoc();
1137 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1138 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1140 // With PIC, the first instruction is actually "GR+hi(&G)".
1142 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1143 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1145 // Generate non-pic code that has direct accesses to the constant pool.
1146 // The address of the global is just (hi(&g)+lo(&g)).
1147 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1150 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1151 SelectionDAG &DAG) const {
1152 EVT PtrVT = Op.getValueType();
1153 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1154 const Constant *C = CP->getConstVal();
1156 unsigned MOHiFlag, MOLoFlag;
1157 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1159 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1161 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1162 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1165 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1166 EVT PtrVT = Op.getValueType();
1167 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1169 unsigned MOHiFlag, MOLoFlag;
1170 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1171 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1172 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1173 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1176 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1177 SelectionDAG &DAG) const {
1178 EVT PtrVT = Op.getValueType();
1180 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1182 unsigned MOHiFlag, MOLoFlag;
1183 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1184 SDValue TgtBAHi = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOHiFlag);
1185 SDValue TgtBALo = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOLoFlag);
1186 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1189 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1190 SelectionDAG &DAG) const {
1191 EVT PtrVT = Op.getValueType();
1192 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1193 DebugLoc DL = GSDN->getDebugLoc();
1194 const GlobalValue *GV = GSDN->getGlobal();
1196 // 64-bit SVR4 ABI code is always position-independent.
1197 // The actual address of the GlobalValue is stored in the TOC.
1198 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1199 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1200 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1201 DAG.getRegister(PPC::X2, MVT::i64));
1204 unsigned MOHiFlag, MOLoFlag;
1205 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1208 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1210 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1212 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1214 // If the global reference is actually to a non-lazy-pointer, we have to do an
1215 // extra load to get the address of the global.
1216 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1217 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1222 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1223 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1224 DebugLoc dl = Op.getDebugLoc();
1226 // If we're comparing for equality to zero, expose the fact that this is
1227 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1228 // fold the new nodes.
1229 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1230 if (C->isNullValue() && CC == ISD::SETEQ) {
1231 EVT VT = Op.getOperand(0).getValueType();
1232 SDValue Zext = Op.getOperand(0);
1233 if (VT.bitsLT(MVT::i32)) {
1235 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1237 unsigned Log2b = Log2_32(VT.getSizeInBits());
1238 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1239 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1240 DAG.getConstant(Log2b, MVT::i32));
1241 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1243 // Leave comparisons against 0 and -1 alone for now, since they're usually
1244 // optimized. FIXME: revisit this when we can custom lower all setcc
1246 if (C->isAllOnesValue() || C->isNullValue())
1250 // If we have an integer seteq/setne, turn it into a compare against zero
1251 // by xor'ing the rhs with the lhs, which is faster than setting a
1252 // condition register, reading it back out, and masking the correct bit. The
1253 // normal approach here uses sub to do this instead of xor. Using xor exposes
1254 // the result to other bit-twiddling opportunities.
1255 EVT LHSVT = Op.getOperand(0).getValueType();
1256 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1257 EVT VT = Op.getValueType();
1258 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1260 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1265 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1266 const PPCSubtarget &Subtarget) const {
1268 llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!");
1269 return SDValue(); // Not reached
1272 SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op,
1273 SelectionDAG &DAG) const {
1274 SDValue Chain = Op.getOperand(0);
1275 SDValue Trmp = Op.getOperand(1); // trampoline
1276 SDValue FPtr = Op.getOperand(2); // nested function
1277 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1278 DebugLoc dl = Op.getDebugLoc();
1280 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1281 bool isPPC64 = (PtrVT == MVT::i64);
1282 const Type *IntPtrTy =
1283 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType(
1286 TargetLowering::ArgListTy Args;
1287 TargetLowering::ArgListEntry Entry;
1289 Entry.Ty = IntPtrTy;
1290 Entry.Node = Trmp; Args.push_back(Entry);
1292 // TrampSize == (isPPC64 ? 48 : 40);
1293 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1294 isPPC64 ? MVT::i64 : MVT::i32);
1295 Args.push_back(Entry);
1297 Entry.Node = FPtr; Args.push_back(Entry);
1298 Entry.Node = Nest; Args.push_back(Entry);
1300 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1301 std::pair<SDValue, SDValue> CallResult =
1302 LowerCallTo(Chain, Op.getValueType().getTypeForEVT(*DAG.getContext()),
1303 false, false, false, false, 0, CallingConv::C, false,
1304 /*isReturnValueUsed=*/true,
1305 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1309 { CallResult.first, CallResult.second };
1311 return DAG.getMergeValues(Ops, 2, dl);
1314 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1315 const PPCSubtarget &Subtarget) const {
1316 MachineFunction &MF = DAG.getMachineFunction();
1317 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1319 DebugLoc dl = Op.getDebugLoc();
1321 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1322 // vastart just stores the address of the VarArgsFrameIndex slot into the
1323 // memory location argument.
1324 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1325 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1326 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1327 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1328 MachinePointerInfo(SV),
1332 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1333 // We suppose the given va_list is already allocated.
1336 // char gpr; /* index into the array of 8 GPRs
1337 // * stored in the register save area
1338 // * gpr=0 corresponds to r3,
1339 // * gpr=1 to r4, etc.
1341 // char fpr; /* index into the array of 8 FPRs
1342 // * stored in the register save area
1343 // * fpr=0 corresponds to f1,
1344 // * fpr=1 to f2, etc.
1346 // char *overflow_arg_area;
1347 // /* location on stack that holds
1348 // * the next overflow argument
1350 // char *reg_save_area;
1351 // /* where r3:r10 and f1:f8 (if saved)
1357 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1358 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1361 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1363 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1365 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1368 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1369 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1371 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1372 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1374 uint64_t FPROffset = 1;
1375 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1377 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1379 // Store first byte : number of int regs
1380 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1382 MachinePointerInfo(SV),
1383 MVT::i8, false, false, 0);
1384 uint64_t nextOffset = FPROffset;
1385 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1388 // Store second byte : number of float regs
1389 SDValue secondStore =
1390 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1391 MachinePointerInfo(SV, nextOffset), MVT::i8,
1393 nextOffset += StackOffset;
1394 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1396 // Store second word : arguments given on stack
1397 SDValue thirdStore =
1398 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1399 MachinePointerInfo(SV, nextOffset),
1401 nextOffset += FrameOffset;
1402 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1404 // Store third word : arguments given in registers
1405 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1406 MachinePointerInfo(SV, nextOffset),
1411 #include "PPCGenCallingConv.inc"
1413 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1414 CCValAssign::LocInfo &LocInfo,
1415 ISD::ArgFlagsTy &ArgFlags,
1420 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1422 CCValAssign::LocInfo &LocInfo,
1423 ISD::ArgFlagsTy &ArgFlags,
1425 static const unsigned ArgRegs[] = {
1426 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1427 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1429 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1431 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1433 // Skip one register if the first unallocated register has an even register
1434 // number and there are still argument registers available which have not been
1435 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1436 // need to skip a register if RegNum is odd.
1437 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1438 State.AllocateReg(ArgRegs[RegNum]);
1441 // Always return false here, as this function only makes sure that the first
1442 // unallocated register has an odd register number and does not actually
1443 // allocate a register for the current argument.
1447 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1449 CCValAssign::LocInfo &LocInfo,
1450 ISD::ArgFlagsTy &ArgFlags,
1452 static const unsigned ArgRegs[] = {
1453 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1457 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1459 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1461 // If there is only one Floating-point register left we need to put both f64
1462 // values of a split ppc_fp128 value on the stack.
1463 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1464 State.AllocateReg(ArgRegs[RegNum]);
1467 // Always return false here, as this function only makes sure that the two f64
1468 // values a ppc_fp128 value is split into are both passed in registers or both
1469 // passed on the stack and does not actually allocate a register for the
1470 // current argument.
1474 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1476 static const unsigned *GetFPR() {
1477 static const unsigned FPR[] = {
1478 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1479 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1485 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1487 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1488 unsigned PtrByteSize) {
1489 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1490 if (Flags.isByVal())
1491 ArgSize = Flags.getByValSize();
1492 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1498 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1499 CallingConv::ID CallConv, bool isVarArg,
1500 const SmallVectorImpl<ISD::InputArg>
1502 DebugLoc dl, SelectionDAG &DAG,
1503 SmallVectorImpl<SDValue> &InVals)
1505 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
1506 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins,
1509 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1515 PPCTargetLowering::LowerFormalArguments_SVR4(
1517 CallingConv::ID CallConv, bool isVarArg,
1518 const SmallVectorImpl<ISD::InputArg>
1520 DebugLoc dl, SelectionDAG &DAG,
1521 SmallVectorImpl<SDValue> &InVals) const {
1523 // 32-bit SVR4 ABI Stack Frame Layout:
1524 // +-----------------------------------+
1525 // +--> | Back chain |
1526 // | +-----------------------------------+
1527 // | | Floating-point register save area |
1528 // | +-----------------------------------+
1529 // | | General register save area |
1530 // | +-----------------------------------+
1531 // | | CR save word |
1532 // | +-----------------------------------+
1533 // | | VRSAVE save word |
1534 // | +-----------------------------------+
1535 // | | Alignment padding |
1536 // | +-----------------------------------+
1537 // | | Vector register save area |
1538 // | +-----------------------------------+
1539 // | | Local variable space |
1540 // | +-----------------------------------+
1541 // | | Parameter list area |
1542 // | +-----------------------------------+
1543 // | | LR save word |
1544 // | +-----------------------------------+
1545 // SP--> +--- | Back chain |
1546 // +-----------------------------------+
1549 // System V Application Binary Interface PowerPC Processor Supplement
1550 // AltiVec Technology Programming Interface Manual
1552 MachineFunction &MF = DAG.getMachineFunction();
1553 MachineFrameInfo *MFI = MF.getFrameInfo();
1554 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1556 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1557 // Potential tail calls could cause overwriting of argument stack slots.
1558 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast));
1559 unsigned PtrByteSize = 4;
1561 // Assign locations to all of the incoming arguments.
1562 SmallVector<CCValAssign, 16> ArgLocs;
1563 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1566 // Reserve space for the linkage area on the stack.
1567 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
1569 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4);
1571 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1572 CCValAssign &VA = ArgLocs[i];
1574 // Arguments stored in registers.
1575 if (VA.isRegLoc()) {
1576 TargetRegisterClass *RC;
1577 EVT ValVT = VA.getValVT();
1579 switch (ValVT.getSimpleVT().SimpleTy) {
1581 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1583 RC = PPC::GPRCRegisterClass;
1586 RC = PPC::F4RCRegisterClass;
1589 RC = PPC::F8RCRegisterClass;
1595 RC = PPC::VRRCRegisterClass;
1599 // Transform the arguments stored in physical registers into virtual ones.
1600 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1601 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1603 InVals.push_back(ArgValue);
1605 // Argument stored in memory.
1606 assert(VA.isMemLoc());
1608 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1609 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1612 // Create load nodes to retrieve arguments from the stack.
1613 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1614 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1615 MachinePointerInfo(),
1620 // Assign locations to all of the incoming aggregate by value arguments.
1621 // Aggregates passed by value are stored in the local variable space of the
1622 // caller's stack frame, right above the parameter list area.
1623 SmallVector<CCValAssign, 16> ByValArgLocs;
1624 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(),
1625 ByValArgLocs, *DAG.getContext());
1627 // Reserve stack space for the allocations in CCInfo.
1628 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1630 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal);
1632 // Area that is at least reserved in the caller of this function.
1633 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1635 // Set the size that is at least reserved in caller of this function. Tail
1636 // call optimized function's reserved stack space needs to be aligned so that
1637 // taking the difference between two stack areas will result in an aligned
1639 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1642 std::max(MinReservedArea,
1643 PPCFrameLowering::getMinCallFrameSize(false, false));
1645 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
1646 getStackAlignment();
1647 unsigned AlignMask = TargetAlign-1;
1648 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1650 FI->setMinReservedArea(MinReservedArea);
1652 SmallVector<SDValue, 8> MemOps;
1654 // If the function takes variable number of arguments, make a frame index for
1655 // the start of the first vararg value... for expansion of llvm.va_start.
1657 static const unsigned GPArgRegs[] = {
1658 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1659 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1661 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
1663 static const unsigned FPArgRegs[] = {
1664 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1667 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
1669 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
1671 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
1674 // Make room for NumGPArgRegs and NumFPArgRegs.
1675 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
1676 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
1678 FuncInfo->setVarArgsStackOffset(
1679 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1680 CCInfo.getNextStackOffset(), true));
1682 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
1683 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1685 // The fixed integer arguments of a variadic function are stored to the
1686 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
1687 // the result of va_next.
1688 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
1689 // Get an existing live-in vreg, or add a new one.
1690 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
1692 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
1694 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1695 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1696 MachinePointerInfo(), false, false, 0);
1697 MemOps.push_back(Store);
1698 // Increment the address by four for the next argument to store
1699 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1700 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1703 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
1705 // The double arguments are stored to the VarArgsFrameIndex
1707 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
1708 // Get an existing live-in vreg, or add a new one.
1709 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
1711 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
1713 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
1714 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1715 MachinePointerInfo(), false, false, 0);
1716 MemOps.push_back(Store);
1717 // Increment the address by eight for the next argument to store
1718 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1720 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1724 if (!MemOps.empty())
1725 Chain = DAG.getNode(ISD::TokenFactor, dl,
1726 MVT::Other, &MemOps[0], MemOps.size());
1732 PPCTargetLowering::LowerFormalArguments_Darwin(
1734 CallingConv::ID CallConv, bool isVarArg,
1735 const SmallVectorImpl<ISD::InputArg>
1737 DebugLoc dl, SelectionDAG &DAG,
1738 SmallVectorImpl<SDValue> &InVals) const {
1739 // TODO: add description of PPC stack frame format, or at least some docs.
1741 MachineFunction &MF = DAG.getMachineFunction();
1742 MachineFrameInfo *MFI = MF.getFrameInfo();
1743 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1745 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1746 bool isPPC64 = PtrVT == MVT::i64;
1747 // Potential tail calls could cause overwriting of argument stack slots.
1748 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast));
1749 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1751 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
1752 // Area that is at least reserved in caller of this function.
1753 unsigned MinReservedArea = ArgOffset;
1755 static const unsigned GPR_32[] = { // 32-bit registers.
1756 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1757 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1759 static const unsigned GPR_64[] = { // 64-bit registers.
1760 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1761 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1764 static const unsigned *FPR = GetFPR();
1766 static const unsigned VR[] = {
1767 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1768 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1771 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1772 const unsigned Num_FPR_Regs = 13;
1773 const unsigned Num_VR_Regs = array_lengthof( VR);
1775 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1777 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1779 // In 32-bit non-varargs functions, the stack space for vectors is after the
1780 // stack space for non-vectors. We do not use this space unless we have
1781 // too many vectors to fit in registers, something that only occurs in
1782 // constructed examples:), but we have to walk the arglist to figure
1783 // that out...for the pathological case, compute VecArgOffset as the
1784 // start of the vector parameter area. Computing VecArgOffset is the
1785 // entire point of the following loop.
1786 unsigned VecArgOffset = ArgOffset;
1787 if (!isVarArg && !isPPC64) {
1788 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
1790 EVT ObjectVT = Ins[ArgNo].VT;
1791 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1792 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1794 if (Flags.isByVal()) {
1795 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1796 ObjSize = Flags.getByValSize();
1798 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1799 VecArgOffset += ArgSize;
1803 switch(ObjectVT.getSimpleVT().SimpleTy) {
1804 default: llvm_unreachable("Unhandled argument type!");
1807 VecArgOffset += isPPC64 ? 8 : 4;
1809 case MVT::i64: // PPC64
1817 // Nothing to do, we're only looking at Nonvector args here.
1822 // We've found where the vector parameter area in memory is. Skip the
1823 // first 12 parameters; these don't use that memory.
1824 VecArgOffset = ((VecArgOffset+15)/16)*16;
1825 VecArgOffset += 12*16;
1827 // Add DAG nodes to load the arguments or copy them out of registers. On
1828 // entry to a function on PPC, the arguments start after the linkage area,
1829 // although the first ones are often in registers.
1831 SmallVector<SDValue, 8> MemOps;
1832 unsigned nAltivecParamsAtEnd = 0;
1833 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
1835 bool needsLoad = false;
1836 EVT ObjectVT = Ins[ArgNo].VT;
1837 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1838 unsigned ArgSize = ObjSize;
1839 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1841 unsigned CurArgOffset = ArgOffset;
1843 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1844 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1845 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1846 if (isVarArg || isPPC64) {
1847 MinReservedArea = ((MinReservedArea+15)/16)*16;
1848 MinReservedArea += CalculateStackSlotSize(ObjectVT,
1851 } else nAltivecParamsAtEnd++;
1853 // Calculate min reserved area.
1854 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
1858 // FIXME the codegen can be much improved in some cases.
1859 // We do not have to keep everything in memory.
1860 if (Flags.isByVal()) {
1861 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1862 ObjSize = Flags.getByValSize();
1863 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1864 // Objects of size 1 and 2 are right justified, everything else is
1865 // left justified. This means the memory address is adjusted forwards.
1866 if (ObjSize==1 || ObjSize==2) {
1867 CurArgOffset = CurArgOffset + (4 - ObjSize);
1869 // The value of the object is its address.
1870 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
1871 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1872 InVals.push_back(FIN);
1873 if (ObjSize==1 || ObjSize==2) {
1874 if (GPR_idx != Num_GPR_Regs) {
1875 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1876 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1877 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
1878 MachinePointerInfo(),
1879 ObjSize==1 ? MVT::i8 : MVT::i16,
1881 MemOps.push_back(Store);
1885 ArgOffset += PtrByteSize;
1889 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1890 // Store whatever pieces of the object are in registers
1891 // to memory. ArgVal will be address of the beginning of
1893 if (GPR_idx != Num_GPR_Regs) {
1894 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1895 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
1896 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1897 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1898 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1899 MachinePointerInfo(),
1901 MemOps.push_back(Store);
1903 ArgOffset += PtrByteSize;
1905 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1912 switch (ObjectVT.getSimpleVT().SimpleTy) {
1913 default: llvm_unreachable("Unhandled argument type!");
1916 if (GPR_idx != Num_GPR_Regs) {
1917 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1918 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1922 ArgSize = PtrByteSize;
1924 // All int arguments reserve stack space in the Darwin ABI.
1925 ArgOffset += PtrByteSize;
1929 case MVT::i64: // PPC64
1930 if (GPR_idx != Num_GPR_Regs) {
1931 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
1932 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1934 if (ObjectVT == MVT::i32) {
1935 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1936 // value to MVT::i64 and then truncate to the correct register size.
1938 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
1939 DAG.getValueType(ObjectVT));
1940 else if (Flags.isZExt())
1941 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
1942 DAG.getValueType(ObjectVT));
1944 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
1950 ArgSize = PtrByteSize;
1952 // All int arguments reserve stack space in the Darwin ABI.
1958 // Every 4 bytes of argument space consumes one of the GPRs available for
1959 // argument passing.
1960 if (GPR_idx != Num_GPR_Regs) {
1962 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1965 if (FPR_idx != Num_FPR_Regs) {
1968 if (ObjectVT == MVT::f32)
1969 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
1971 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
1973 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
1979 // All FP arguments reserve stack space in the Darwin ABI.
1980 ArgOffset += isPPC64 ? 8 : ObjSize;
1986 // Note that vector arguments in registers don't reserve stack space,
1987 // except in varargs functions.
1988 if (VR_idx != Num_VR_Regs) {
1989 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
1990 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
1992 while ((ArgOffset % 16) != 0) {
1993 ArgOffset += PtrByteSize;
1994 if (GPR_idx != Num_GPR_Regs)
1998 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2002 if (!isVarArg && !isPPC64) {
2003 // Vectors go after all the nonvectors.
2004 CurArgOffset = VecArgOffset;
2007 // Vectors are aligned.
2008 ArgOffset = ((ArgOffset+15)/16)*16;
2009 CurArgOffset = ArgOffset;
2017 // We need to load the argument to a virtual register if we determined above
2018 // that we ran out of physical registers of the appropriate type.
2020 int FI = MFI->CreateFixedObject(ObjSize,
2021 CurArgOffset + (ArgSize - ObjSize),
2023 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2024 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2028 InVals.push_back(ArgVal);
2031 // Set the size that is at least reserved in caller of this function. Tail
2032 // call optimized function's reserved stack space needs to be aligned so that
2033 // taking the difference between two stack areas will result in an aligned
2035 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2036 // Add the Altivec parameters at the end, if needed.
2037 if (nAltivecParamsAtEnd) {
2038 MinReservedArea = ((MinReservedArea+15)/16)*16;
2039 MinReservedArea += 16*nAltivecParamsAtEnd;
2042 std::max(MinReservedArea,
2043 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2044 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2045 getStackAlignment();
2046 unsigned AlignMask = TargetAlign-1;
2047 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2048 FI->setMinReservedArea(MinReservedArea);
2050 // If the function takes variable number of arguments, make a frame index for
2051 // the start of the first vararg value... for expansion of llvm.va_start.
2053 int Depth = ArgOffset;
2055 FuncInfo->setVarArgsFrameIndex(
2056 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2058 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2060 // If this function is vararg, store any remaining integer argument regs
2061 // to their spots on the stack so that they may be loaded by deferencing the
2062 // result of va_next.
2063 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2067 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2069 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2071 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2072 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2073 MachinePointerInfo(), false, false, 0);
2074 MemOps.push_back(Store);
2075 // Increment the address by four for the next argument to store
2076 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2077 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2081 if (!MemOps.empty())
2082 Chain = DAG.getNode(ISD::TokenFactor, dl,
2083 MVT::Other, &MemOps[0], MemOps.size());
2088 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
2089 /// linkage area for the Darwin ABI.
2091 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2095 const SmallVectorImpl<ISD::OutputArg>
2097 const SmallVectorImpl<SDValue> &OutVals,
2098 unsigned &nAltivecParamsAtEnd) {
2099 // Count how many bytes are to be pushed on the stack, including the linkage
2100 // area, and parameter passing area. We start with 24/48 bytes, which is
2101 // prereserved space for [SP][CR][LR][3 x unused].
2102 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2103 unsigned NumOps = Outs.size();
2104 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2106 // Add up all the space actually used.
2107 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2108 // they all go in registers, but we must reserve stack space for them for
2109 // possible use by the caller. In varargs or 64-bit calls, parameters are
2110 // assigned stack space in order, with padding so Altivec parameters are
2112 nAltivecParamsAtEnd = 0;
2113 for (unsigned i = 0; i != NumOps; ++i) {
2114 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2115 EVT ArgVT = Outs[i].VT;
2116 // Varargs Altivec parameters are padded to a 16 byte boundary.
2117 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2118 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2119 if (!isVarArg && !isPPC64) {
2120 // Non-varargs Altivec parameters go after all the non-Altivec
2121 // parameters; handle those later so we know how much padding we need.
2122 nAltivecParamsAtEnd++;
2125 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2126 NumBytes = ((NumBytes+15)/16)*16;
2128 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2131 // Allow for Altivec parameters at the end, if needed.
2132 if (nAltivecParamsAtEnd) {
2133 NumBytes = ((NumBytes+15)/16)*16;
2134 NumBytes += 16*nAltivecParamsAtEnd;
2137 // The prolog code of the callee may store up to 8 GPR argument registers to
2138 // the stack, allowing va_start to index over them in memory if its varargs.
2139 // Because we cannot tell if this is needed on the caller side, we have to
2140 // conservatively assume that it is needed. As such, make sure we have at
2141 // least enough stack space for the caller to store the 8 GPRs.
2142 NumBytes = std::max(NumBytes,
2143 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2145 // Tail call needs the stack to be aligned.
2146 if (CC==CallingConv::Fast && GuaranteedTailCallOpt) {
2147 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2148 getStackAlignment();
2149 unsigned AlignMask = TargetAlign-1;
2150 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2156 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2157 /// adjusted to accomodate the arguments for the tailcall.
2158 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2159 unsigned ParamSize) {
2161 if (!isTailCall) return 0;
2163 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2164 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2165 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2166 // Remember only if the new adjustement is bigger.
2167 if (SPDiff < FI->getTailCallSPDelta())
2168 FI->setTailCallSPDelta(SPDiff);
2173 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2174 /// for tail call optimization. Targets which want to do tail call
2175 /// optimization should implement this function.
2177 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2178 CallingConv::ID CalleeCC,
2180 const SmallVectorImpl<ISD::InputArg> &Ins,
2181 SelectionDAG& DAG) const {
2182 if (!GuaranteedTailCallOpt)
2185 // Variable argument functions are not supported.
2189 MachineFunction &MF = DAG.getMachineFunction();
2190 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2191 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2192 // Functions containing by val parameters are not supported.
2193 for (unsigned i = 0; i != Ins.size(); i++) {
2194 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2195 if (Flags.isByVal()) return false;
2198 // Non PIC/GOT tail calls are supported.
2199 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2202 // At the moment we can only do local tail calls (in same module, hidden
2203 // or protected) if we are generating PIC.
2204 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2205 return G->getGlobal()->hasHiddenVisibility()
2206 || G->getGlobal()->hasProtectedVisibility();
2212 /// isCallCompatibleAddress - Return the immediate to use if the specified
2213 /// 32-bit value is representable in the immediate field of a BxA instruction.
2214 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2215 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2218 int Addr = C->getZExtValue();
2219 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2220 (Addr << 6 >> 6) != Addr)
2221 return 0; // Top 6 bits have to be sext of immediate.
2223 return DAG.getConstant((int)C->getZExtValue() >> 2,
2224 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2229 struct TailCallArgumentInfo {
2234 TailCallArgumentInfo() : FrameIdx(0) {}
2239 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2241 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2243 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2244 SmallVector<SDValue, 8> &MemOpChains,
2246 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2247 SDValue Arg = TailCallArgs[i].Arg;
2248 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2249 int FI = TailCallArgs[i].FrameIdx;
2250 // Store relative to framepointer.
2251 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2252 MachinePointerInfo::getFixedStack(FI),
2257 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2258 /// the appropriate stack slot for the tail call optimized function call.
2259 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2260 MachineFunction &MF,
2269 // Calculate the new stack slot for the return address.
2270 int SlotSize = isPPC64 ? 8 : 4;
2271 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
2273 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2274 NewRetAddrLoc, true);
2275 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2276 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2277 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2278 MachinePointerInfo::getFixedStack(NewRetAddr),
2281 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2282 // slot as the FP is never overwritten.
2285 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2286 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
2288 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2289 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2290 MachinePointerInfo::getFixedStack(NewFPIdx),
2297 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2298 /// the position of the argument.
2300 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2301 SDValue Arg, int SPDiff, unsigned ArgOffset,
2302 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2303 int Offset = ArgOffset + SPDiff;
2304 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2305 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2306 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2307 SDValue FIN = DAG.getFrameIndex(FI, VT);
2308 TailCallArgumentInfo Info;
2310 Info.FrameIdxOp = FIN;
2312 TailCallArguments.push_back(Info);
2315 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2316 /// stack slot. Returns the chain as result and the loaded frame pointers in
2317 /// LROpOut/FPOpout. Used when tail calling.
2318 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2324 DebugLoc dl) const {
2326 // Load the LR and FP stack slot for later adjusting.
2327 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2328 LROpOut = getReturnAddrFrameIndex(DAG);
2329 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
2331 Chain = SDValue(LROpOut.getNode(), 1);
2333 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
2334 // slot as the FP is never overwritten.
2336 FPOpOut = getFramePointerFrameIndex(DAG);
2337 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
2339 Chain = SDValue(FPOpOut.getNode(), 1);
2345 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2346 /// by "Src" to address "Dst" of size "Size". Alignment information is
2347 /// specified by the specific parameter attribute. The copy will be passed as
2348 /// a byval function parameter.
2349 /// Sometimes what we are copying is the end of a larger object, the part that
2350 /// does not fit in registers.
2352 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2353 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2355 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2356 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2357 false, false, MachinePointerInfo(0),
2358 MachinePointerInfo(0));
2361 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2364 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2365 SDValue Arg, SDValue PtrOff, int SPDiff,
2366 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2367 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2368 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
2370 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2375 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2377 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2378 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2379 DAG.getConstant(ArgOffset, PtrVT));
2381 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2382 MachinePointerInfo(), false, false, 0));
2383 // Calculate and remember argument location.
2384 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2389 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
2390 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
2391 SDValue LROp, SDValue FPOp, bool isDarwinABI,
2392 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
2393 MachineFunction &MF = DAG.getMachineFunction();
2395 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2396 // might overwrite each other in case of tail call optimization.
2397 SmallVector<SDValue, 8> MemOpChains2;
2398 // Do not flag preceeding copytoreg stuff together with the following stuff.
2400 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2402 if (!MemOpChains2.empty())
2403 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2404 &MemOpChains2[0], MemOpChains2.size());
2406 // Store the return address to the appropriate stack slot.
2407 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2408 isPPC64, isDarwinABI, dl);
2410 // Emit callseq_end just before tailcall node.
2411 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2412 DAG.getIntPtrConstant(0, true), InFlag);
2413 InFlag = Chain.getValue(1);
2417 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
2418 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
2419 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
2420 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
2421 const PPCSubtarget &PPCSubTarget) {
2423 bool isPPC64 = PPCSubTarget.isPPC64();
2424 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
2426 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2427 NodeTys.push_back(MVT::Other); // Returns a chain
2428 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
2430 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
2432 bool needIndirectCall = true;
2433 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
2434 // If this is an absolute destination address, use the munged value.
2435 Callee = SDValue(Dest, 0);
2436 needIndirectCall = false;
2439 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2440 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
2441 // Use indirect calls for ALL functions calls in JIT mode, since the
2442 // far-call stubs may be outside relocation limits for a BL instruction.
2443 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
2444 unsigned OpFlags = 0;
2445 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
2446 PPCSubTarget.getDarwinVers() < 9 &&
2447 (G->getGlobal()->isDeclaration() ||
2448 G->getGlobal()->isWeakForLinker())) {
2449 // PC-relative references to external symbols should go through $stub,
2450 // unless we're building with the leopard linker or later, which
2451 // automatically synthesizes these stubs.
2452 OpFlags = PPCII::MO_DARWIN_STUB;
2455 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
2456 // every direct call is) turn it into a TargetGlobalAddress /
2457 // TargetExternalSymbol node so that legalize doesn't hack it.
2458 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2459 Callee.getValueType(),
2461 needIndirectCall = false;
2465 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2466 unsigned char OpFlags = 0;
2468 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
2469 PPCSubTarget.getDarwinVers() < 9) {
2470 // PC-relative references to external symbols should go through $stub,
2471 // unless we're building with the leopard linker or later, which
2472 // automatically synthesizes these stubs.
2473 OpFlags = PPCII::MO_DARWIN_STUB;
2476 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
2478 needIndirectCall = false;
2481 if (needIndirectCall) {
2482 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2483 // to do the call, we can't use PPCISD::CALL.
2484 SDValue MTCTROps[] = {Chain, Callee, InFlag};
2486 if (isSVR4ABI && isPPC64) {
2487 // Function pointers in the 64-bit SVR4 ABI do not point to the function
2488 // entry point, but to the function descriptor (the function entry point
2489 // address is part of the function descriptor though).
2490 // The function descriptor is a three doubleword structure with the
2491 // following fields: function entry point, TOC base address and
2492 // environment pointer.
2493 // Thus for a call through a function pointer, the following actions need
2495 // 1. Save the TOC of the caller in the TOC save area of its stack
2496 // frame (this is done in LowerCall_Darwin()).
2497 // 2. Load the address of the function entry point from the function
2499 // 3. Load the TOC of the callee from the function descriptor into r2.
2500 // 4. Load the environment pointer from the function descriptor into
2502 // 5. Branch to the function entry point address.
2503 // 6. On return of the callee, the TOC of the caller needs to be
2504 // restored (this is done in FinishCall()).
2506 // All those operations are flagged together to ensure that no other
2507 // operations can be scheduled in between. E.g. without flagging the
2508 // operations together, a TOC access in the caller could be scheduled
2509 // between the load of the callee TOC and the branch to the callee, which
2510 // results in the TOC access going through the TOC of the callee instead
2511 // of going through the TOC of the caller, which leads to incorrect code.
2513 // Load the address of the function entry point from the function
2515 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
2516 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
2517 InFlag.getNode() ? 3 : 2);
2518 Chain = LoadFuncPtr.getValue(1);
2519 InFlag = LoadFuncPtr.getValue(2);
2521 // Load environment pointer into r11.
2522 // Offset of the environment pointer within the function descriptor.
2523 SDValue PtrOff = DAG.getIntPtrConstant(16);
2525 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
2526 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
2528 Chain = LoadEnvPtr.getValue(1);
2529 InFlag = LoadEnvPtr.getValue(2);
2531 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
2533 Chain = EnvVal.getValue(0);
2534 InFlag = EnvVal.getValue(1);
2536 // Load TOC of the callee into r2. We are using a target-specific load
2537 // with r2 hard coded, because the result of a target-independent load
2538 // would never go directly into r2, since r2 is a reserved register (which
2539 // prevents the register allocator from allocating it), resulting in an
2540 // additional register being allocated and an unnecessary move instruction
2542 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2543 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
2545 Chain = LoadTOCPtr.getValue(0);
2546 InFlag = LoadTOCPtr.getValue(1);
2548 MTCTROps[0] = Chain;
2549 MTCTROps[1] = LoadFuncPtr;
2550 MTCTROps[2] = InFlag;
2553 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2554 2 + (InFlag.getNode() != 0));
2555 InFlag = Chain.getValue(1);
2558 NodeTys.push_back(MVT::Other);
2559 NodeTys.push_back(MVT::Glue);
2560 Ops.push_back(Chain);
2561 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
2563 // Add CTR register as callee so a bctr can be emitted later.
2565 Ops.push_back(DAG.getRegister(PPC::CTR, PtrVT));
2568 // If this is a direct call, pass the chain and the callee.
2569 if (Callee.getNode()) {
2570 Ops.push_back(Chain);
2571 Ops.push_back(Callee);
2573 // If this is a tail call add stack pointer delta.
2575 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2577 // Add argument registers to the end of the list so that they are known live
2579 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2580 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2581 RegsToPass[i].second.getValueType()));
2587 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2588 CallingConv::ID CallConv, bool isVarArg,
2589 const SmallVectorImpl<ISD::InputArg> &Ins,
2590 DebugLoc dl, SelectionDAG &DAG,
2591 SmallVectorImpl<SDValue> &InVals) const {
2593 SmallVector<CCValAssign, 16> RVLocs;
2594 CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(),
2595 RVLocs, *DAG.getContext());
2596 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2598 // Copy all of the result registers out of their specified physreg.
2599 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2600 CCValAssign &VA = RVLocs[i];
2601 EVT VT = VA.getValVT();
2602 assert(VA.isRegLoc() && "Can only return in registers!");
2603 Chain = DAG.getCopyFromReg(Chain, dl,
2604 VA.getLocReg(), VT, InFlag).getValue(1);
2605 InVals.push_back(Chain.getValue(0));
2606 InFlag = Chain.getValue(2);
2613 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
2614 bool isTailCall, bool isVarArg,
2616 SmallVector<std::pair<unsigned, SDValue>, 8>
2618 SDValue InFlag, SDValue Chain,
2620 int SPDiff, unsigned NumBytes,
2621 const SmallVectorImpl<ISD::InputArg> &Ins,
2622 SmallVectorImpl<SDValue> &InVals) const {
2623 std::vector<EVT> NodeTys;
2624 SmallVector<SDValue, 8> Ops;
2625 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
2626 isTailCall, RegsToPass, Ops, NodeTys,
2629 // When performing tail call optimization the callee pops its arguments off
2630 // the stack. Account for this here so these bytes can be pushed back on in
2631 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2632 int BytesCalleePops =
2633 (CallConv==CallingConv::Fast && GuaranteedTailCallOpt) ? NumBytes : 0;
2635 if (InFlag.getNode())
2636 Ops.push_back(InFlag);
2640 // If this is the first return lowered for this function, add the regs
2641 // to the liveout set for the function.
2642 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2643 SmallVector<CCValAssign, 16> RVLocs;
2644 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2646 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2647 for (unsigned i = 0; i != RVLocs.size(); ++i)
2648 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2651 assert(((Callee.getOpcode() == ISD::Register &&
2652 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
2653 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2654 Callee.getOpcode() == ISD::TargetGlobalAddress ||
2655 isa<ConstantSDNode>(Callee)) &&
2656 "Expecting an global address, external symbol, absolute value or register");
2658 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
2661 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
2662 InFlag = Chain.getValue(1);
2664 // Add a NOP immediately after the branch instruction when using the 64-bit
2665 // SVR4 ABI. At link time, if caller and callee are in a different module and
2666 // thus have a different TOC, the call will be replaced with a call to a stub
2667 // function which saves the current TOC, loads the TOC of the callee and
2668 // branches to the callee. The NOP will be replaced with a load instruction
2669 // which restores the TOC of the caller from the TOC save slot of the current
2670 // stack frame. If caller and callee belong to the same module (and have the
2671 // same TOC), the NOP will remain unchanged.
2672 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
2673 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2674 if (CallOpc == PPCISD::BCTRL_SVR4) {
2675 // This is a call through a function pointer.
2676 // Restore the caller TOC from the save area into R2.
2677 // See PrepareCall() for more information about calls through function
2678 // pointers in the 64-bit SVR4 ABI.
2679 // We are using a target-specific load with r2 hard coded, because the
2680 // result of a target-independent load would never go directly into r2,
2681 // since r2 is a reserved register (which prevents the register allocator
2682 // from allocating it), resulting in an additional register being
2683 // allocated and an unnecessary move instruction being generated.
2684 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
2685 InFlag = Chain.getValue(1);
2687 // Otherwise insert NOP.
2688 InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Glue, InFlag);
2692 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2693 DAG.getIntPtrConstant(BytesCalleePops, true),
2696 InFlag = Chain.getValue(1);
2698 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2699 Ins, dl, DAG, InVals);
2703 PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2704 CallingConv::ID CallConv, bool isVarArg,
2706 const SmallVectorImpl<ISD::OutputArg> &Outs,
2707 const SmallVectorImpl<SDValue> &OutVals,
2708 const SmallVectorImpl<ISD::InputArg> &Ins,
2709 DebugLoc dl, SelectionDAG &DAG,
2710 SmallVectorImpl<SDValue> &InVals) const {
2712 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
2715 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
2716 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg,
2717 isTailCall, Outs, OutVals, Ins,
2720 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
2721 isTailCall, Outs, OutVals, Ins,
2726 PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
2727 CallingConv::ID CallConv, bool isVarArg,
2729 const SmallVectorImpl<ISD::OutputArg> &Outs,
2730 const SmallVectorImpl<SDValue> &OutVals,
2731 const SmallVectorImpl<ISD::InputArg> &Ins,
2732 DebugLoc dl, SelectionDAG &DAG,
2733 SmallVectorImpl<SDValue> &InVals) const {
2734 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description
2735 // of the 32-bit SVR4 ABI stack frame layout.
2737 assert((CallConv == CallingConv::C ||
2738 CallConv == CallingConv::Fast) && "Unknown calling convention!");
2740 unsigned PtrByteSize = 4;
2742 MachineFunction &MF = DAG.getMachineFunction();
2744 // Mark this function as potentially containing a function that contains a
2745 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2746 // and restoring the callers stack pointer in this functions epilog. This is
2747 // done because by tail calling the called function might overwrite the value
2748 // in this function's (MF) stack pointer stack slot 0(SP).
2749 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast)
2750 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2752 // Count how many bytes are to be pushed on the stack, including the linkage
2753 // area, parameter list area and the part of the local variable space which
2754 // contains copies of aggregates which are passed by value.
2756 // Assign locations to all of the outgoing arguments.
2757 SmallVector<CCValAssign, 16> ArgLocs;
2758 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
2759 ArgLocs, *DAG.getContext());
2761 // Reserve space for the linkage area on the stack.
2762 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2765 // Handle fixed and variable vector arguments differently.
2766 // Fixed vector arguments go into registers as long as registers are
2767 // available. Variable vector arguments always go into memory.
2768 unsigned NumArgs = Outs.size();
2770 for (unsigned i = 0; i != NumArgs; ++i) {
2771 MVT ArgVT = Outs[i].VT;
2772 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2775 if (Outs[i].IsFixed) {
2776 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
2779 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
2785 errs() << "Call operand #" << i << " has unhandled type "
2786 << EVT(ArgVT).getEVTString() << "\n";
2788 llvm_unreachable(0);
2792 // All arguments are treated the same.
2793 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4);
2796 // Assign locations to all of the outgoing aggregate by value arguments.
2797 SmallVector<CCValAssign, 16> ByValArgLocs;
2798 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), ByValArgLocs,
2801 // Reserve stack space for the allocations in CCInfo.
2802 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2804 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal);
2806 // Size of the linkage area, parameter list area and the part of the local
2807 // space variable where copies of aggregates which are passed by value are
2809 unsigned NumBytes = CCByValInfo.getNextStackOffset();
2811 // Calculate by how many bytes the stack has to be adjusted in case of tail
2812 // call optimization.
2813 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2815 // Adjust the stack pointer for the new arguments...
2816 // These operations are automatically eliminated by the prolog/epilog pass
2817 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2818 SDValue CallSeqStart = Chain;
2820 // Load the return address and frame pointer so it can be moved somewhere else
2823 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
2826 // Set up a copy of the stack pointer for use loading and storing any
2827 // arguments that may not fit in the registers available for argument
2829 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2831 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2832 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2833 SmallVector<SDValue, 8> MemOpChains;
2835 // Walk the register/memloc assignments, inserting copies/loads.
2836 for (unsigned i = 0, j = 0, e = ArgLocs.size();
2839 CCValAssign &VA = ArgLocs[i];
2840 SDValue Arg = OutVals[i];
2841 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2843 if (Flags.isByVal()) {
2844 // Argument is an aggregate which is passed by value, thus we need to
2845 // create a copy of it in the local variable space of the current stack
2846 // frame (which is the stack frame of the caller) and pass the address of
2847 // this copy to the callee.
2848 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
2849 CCValAssign &ByValVA = ByValArgLocs[j++];
2850 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
2852 // Memory reserved in the local variable space of the callers stack frame.
2853 unsigned LocMemOffset = ByValVA.getLocMemOffset();
2855 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2856 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2858 // Create a copy of the argument in the local area of the current
2860 SDValue MemcpyCall =
2861 CreateCopyOfByValArgument(Arg, PtrOff,
2862 CallSeqStart.getNode()->getOperand(0),
2865 // This must go outside the CALLSEQ_START..END.
2866 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2867 CallSeqStart.getNode()->getOperand(1));
2868 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2869 NewCallSeqStart.getNode());
2870 Chain = CallSeqStart = NewCallSeqStart;
2872 // Pass the address of the aggregate copy on the stack either in a
2873 // physical register or in the parameter list area of the current stack
2874 // frame to the callee.
2878 if (VA.isRegLoc()) {
2879 // Put argument in a physical register.
2880 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2882 // Put argument in the parameter list area of the current stack frame.
2883 assert(VA.isMemLoc());
2884 unsigned LocMemOffset = VA.getLocMemOffset();
2887 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2888 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2890 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2891 MachinePointerInfo(),
2894 // Calculate and remember argument location.
2895 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
2901 if (!MemOpChains.empty())
2902 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2903 &MemOpChains[0], MemOpChains.size());
2905 // Build a sequence of copy-to-reg nodes chained together with token chain
2906 // and flag operands which copy the outgoing args into the appropriate regs.
2908 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2909 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2910 RegsToPass[i].second, InFlag);
2911 InFlag = Chain.getValue(1);
2914 // Set CR6 to true if this is a vararg call.
2916 SDValue SetCR(DAG.getMachineNode(PPC::CRSET, dl, MVT::i32), 0);
2917 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
2918 InFlag = Chain.getValue(1);
2922 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
2923 false, TailCallArguments);
2925 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
2926 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
2931 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
2932 CallingConv::ID CallConv, bool isVarArg,
2934 const SmallVectorImpl<ISD::OutputArg> &Outs,
2935 const SmallVectorImpl<SDValue> &OutVals,
2936 const SmallVectorImpl<ISD::InputArg> &Ins,
2937 DebugLoc dl, SelectionDAG &DAG,
2938 SmallVectorImpl<SDValue> &InVals) const {
2940 unsigned NumOps = Outs.size();
2942 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2943 bool isPPC64 = PtrVT == MVT::i64;
2944 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2946 MachineFunction &MF = DAG.getMachineFunction();
2948 // Mark this function as potentially containing a function that contains a
2949 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2950 // and restoring the callers stack pointer in this functions epilog. This is
2951 // done because by tail calling the called function might overwrite the value
2952 // in this function's (MF) stack pointer stack slot 0(SP).
2953 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast)
2954 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2956 unsigned nAltivecParamsAtEnd = 0;
2958 // Count how many bytes are to be pushed on the stack, including the linkage
2959 // area, and parameter passing area. We start with 24/48 bytes, which is
2960 // prereserved space for [SP][CR][LR][3 x unused].
2962 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
2964 nAltivecParamsAtEnd);
2966 // Calculate by how many bytes the stack has to be adjusted in case of tail
2967 // call optimization.
2968 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2970 // To protect arguments on the stack from being clobbered in a tail call,
2971 // force all the loads to happen before doing any other lowering.
2973 Chain = DAG.getStackArgumentTokenFactor(Chain);
2975 // Adjust the stack pointer for the new arguments...
2976 // These operations are automatically eliminated by the prolog/epilog pass
2977 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2978 SDValue CallSeqStart = Chain;
2980 // Load the return address and frame pointer so it can be move somewhere else
2983 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
2986 // Set up a copy of the stack pointer for use loading and storing any
2987 // arguments that may not fit in the registers available for argument
2991 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2993 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2995 // Figure out which arguments are going to go in registers, and which in
2996 // memory. Also, if this is a vararg function, floating point operations
2997 // must be stored to our stack, and loaded into integer regs as well, if
2998 // any integer regs are available for argument passing.
2999 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
3000 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3002 static const unsigned GPR_32[] = { // 32-bit registers.
3003 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3004 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3006 static const unsigned GPR_64[] = { // 64-bit registers.
3007 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3008 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3010 static const unsigned *FPR = GetFPR();
3012 static const unsigned VR[] = {
3013 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3014 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3016 const unsigned NumGPRs = array_lengthof(GPR_32);
3017 const unsigned NumFPRs = 13;
3018 const unsigned NumVRs = array_lengthof(VR);
3020 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
3022 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3023 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3025 SmallVector<SDValue, 8> MemOpChains;
3026 for (unsigned i = 0; i != NumOps; ++i) {
3027 SDValue Arg = OutVals[i];
3028 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3030 // PtrOff will be used to store the current argument to the stack if a
3031 // register cannot be found for it.
3034 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3036 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3038 // On PPC64, promote integers to 64-bit values.
3039 if (isPPC64 && Arg.getValueType() == MVT::i32) {
3040 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3041 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3042 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3045 // FIXME memcpy is used way more than necessary. Correctness first.
3046 if (Flags.isByVal()) {
3047 unsigned Size = Flags.getByValSize();
3048 if (Size==1 || Size==2) {
3049 // Very small objects are passed right-justified.
3050 // Everything else is passed left-justified.
3051 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
3052 if (GPR_idx != NumGPRs) {
3053 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3054 MachinePointerInfo(), VT,
3056 MemOpChains.push_back(Load.getValue(1));
3057 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3059 ArgOffset += PtrByteSize;
3061 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
3062 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3063 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
3064 CallSeqStart.getNode()->getOperand(0),
3066 // This must go outside the CALLSEQ_START..END.
3067 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3068 CallSeqStart.getNode()->getOperand(1));
3069 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3070 NewCallSeqStart.getNode());
3071 Chain = CallSeqStart = NewCallSeqStart;
3072 ArgOffset += PtrByteSize;
3076 // Copy entire object into memory. There are cases where gcc-generated
3077 // code assumes it is there, even if it could be put entirely into
3078 // registers. (This is not what the doc says.)
3079 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3080 CallSeqStart.getNode()->getOperand(0),
3082 // This must go outside the CALLSEQ_START..END.
3083 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3084 CallSeqStart.getNode()->getOperand(1));
3085 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
3086 Chain = CallSeqStart = NewCallSeqStart;
3087 // And copy the pieces of it that fit into registers.
3088 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3089 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3090 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3091 if (GPR_idx != NumGPRs) {
3092 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3093 MachinePointerInfo(),
3095 MemOpChains.push_back(Load.getValue(1));
3096 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3097 ArgOffset += PtrByteSize;
3099 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3106 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3107 default: llvm_unreachable("Unexpected ValueType for argument!");
3110 if (GPR_idx != NumGPRs) {
3111 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3113 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3114 isPPC64, isTailCall, false, MemOpChains,
3115 TailCallArguments, dl);
3117 ArgOffset += PtrByteSize;
3121 if (FPR_idx != NumFPRs) {
3122 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3125 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3126 MachinePointerInfo(), false, false, 0);
3127 MemOpChains.push_back(Store);
3129 // Float varargs are always shadowed in available integer registers
3130 if (GPR_idx != NumGPRs) {
3131 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3132 MachinePointerInfo(), false, false, 0);
3133 MemOpChains.push_back(Load.getValue(1));
3134 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3136 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
3137 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3138 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3139 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3140 MachinePointerInfo(),
3142 MemOpChains.push_back(Load.getValue(1));
3143 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3146 // If we have any FPRs remaining, we may also have GPRs remaining.
3147 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
3149 if (GPR_idx != NumGPRs)
3151 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
3152 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
3156 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3157 isPPC64, isTailCall, false, MemOpChains,
3158 TailCallArguments, dl);
3163 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
3170 // These go aligned on the stack, or in the corresponding R registers
3171 // when within range. The Darwin PPC ABI doc claims they also go in
3172 // V registers; in fact gcc does this only for arguments that are
3173 // prototyped, not for those that match the ... We do it for all
3174 // arguments, seems to work.
3175 while (ArgOffset % 16 !=0) {
3176 ArgOffset += PtrByteSize;
3177 if (GPR_idx != NumGPRs)
3180 // We could elide this store in the case where the object fits
3181 // entirely in R registers. Maybe later.
3182 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3183 DAG.getConstant(ArgOffset, PtrVT));
3184 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3185 MachinePointerInfo(), false, false, 0);
3186 MemOpChains.push_back(Store);
3187 if (VR_idx != NumVRs) {
3188 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
3189 MachinePointerInfo(),
3191 MemOpChains.push_back(Load.getValue(1));
3192 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
3195 for (unsigned i=0; i<16; i+=PtrByteSize) {
3196 if (GPR_idx == NumGPRs)
3198 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
3199 DAG.getConstant(i, PtrVT));
3200 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
3202 MemOpChains.push_back(Load.getValue(1));
3203 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3208 // Non-varargs Altivec params generally go in registers, but have
3209 // stack space allocated at the end.
3210 if (VR_idx != NumVRs) {
3211 // Doesn't have GPR space allocated.
3212 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
3213 } else if (nAltivecParamsAtEnd==0) {
3214 // We are emitting Altivec params in order.
3215 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3216 isPPC64, isTailCall, true, MemOpChains,
3217 TailCallArguments, dl);
3223 // If all Altivec parameters fit in registers, as they usually do,
3224 // they get stack space following the non-Altivec parameters. We
3225 // don't track this here because nobody below needs it.
3226 // If there are more Altivec parameters than fit in registers emit
3228 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
3230 // Offset is aligned; skip 1st 12 params which go in V registers.
3231 ArgOffset = ((ArgOffset+15)/16)*16;
3233 for (unsigned i = 0; i != NumOps; ++i) {
3234 SDValue Arg = OutVals[i];
3235 EVT ArgType = Outs[i].VT;
3236 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
3237 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
3240 // We are emitting Altivec params in order.
3241 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3242 isPPC64, isTailCall, true, MemOpChains,
3243 TailCallArguments, dl);
3250 if (!MemOpChains.empty())
3251 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3252 &MemOpChains[0], MemOpChains.size());
3254 // Check if this is an indirect call (MTCTR/BCTRL).
3255 // See PrepareCall() for more information about calls through function
3256 // pointers in the 64-bit SVR4 ABI.
3257 if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() &&
3258 !dyn_cast<GlobalAddressSDNode>(Callee) &&
3259 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3260 !isBLACompatibleAddress(Callee, DAG)) {
3261 // Load r2 into a virtual register and store it to the TOC save area.
3262 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
3263 // TOC save area offset.
3264 SDValue PtrOff = DAG.getIntPtrConstant(40);
3265 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3266 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
3270 // On Darwin, R12 must contain the address of an indirect callee. This does
3271 // not mean the MTCTR instruction must use R12; it's easier to model this as
3272 // an extra parameter, so do that.
3274 !dyn_cast<GlobalAddressSDNode>(Callee) &&
3275 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3276 !isBLACompatibleAddress(Callee, DAG))
3277 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
3278 PPC::R12), Callee));
3280 // Build a sequence of copy-to-reg nodes chained together with token chain
3281 // and flag operands which copy the outgoing args into the appropriate regs.
3283 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3284 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3285 RegsToPass[i].second, InFlag);
3286 InFlag = Chain.getValue(1);
3290 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
3291 FPOp, true, TailCallArguments);
3293 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3294 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3299 PPCTargetLowering::LowerReturn(SDValue Chain,
3300 CallingConv::ID CallConv, bool isVarArg,
3301 const SmallVectorImpl<ISD::OutputArg> &Outs,
3302 const SmallVectorImpl<SDValue> &OutVals,
3303 DebugLoc dl, SelectionDAG &DAG) const {
3305 SmallVector<CCValAssign, 16> RVLocs;
3306 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
3307 RVLocs, *DAG.getContext());
3308 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
3310 // If this is the first return lowered for this function, add the regs to the
3311 // liveout set for the function.
3312 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3313 for (unsigned i = 0; i != RVLocs.size(); ++i)
3314 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3319 // Copy the result values into the output registers.
3320 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3321 CCValAssign &VA = RVLocs[i];
3322 assert(VA.isRegLoc() && "Can only return in registers!");
3323 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3325 Flag = Chain.getValue(1);
3329 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
3331 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
3334 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
3335 const PPCSubtarget &Subtarget) const {
3336 // When we pop the dynamic allocation we need to restore the SP link.
3337 DebugLoc dl = Op.getDebugLoc();
3339 // Get the corect type for pointers.
3340 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3342 // Construct the stack pointer operand.
3343 bool isPPC64 = Subtarget.isPPC64();
3344 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
3345 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
3347 // Get the operands for the STACKRESTORE.
3348 SDValue Chain = Op.getOperand(0);
3349 SDValue SaveSP = Op.getOperand(1);
3351 // Load the old link SP.
3352 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
3353 MachinePointerInfo(),
3356 // Restore the stack pointer.
3357 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
3359 // Store the old link SP.
3360 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
3367 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
3368 MachineFunction &MF = DAG.getMachineFunction();
3369 bool isPPC64 = PPCSubTarget.isPPC64();
3370 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3371 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3373 // Get current frame pointer save index. The users of this index will be
3374 // primarily DYNALLOC instructions.
3375 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3376 int RASI = FI->getReturnAddrSaveIndex();
3378 // If the frame pointer save index hasn't been defined yet.
3380 // Find out what the fix offset of the frame pointer save area.
3381 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
3382 // Allocate the frame index for frame pointer save area.
3383 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
3385 FI->setReturnAddrSaveIndex(RASI);
3387 return DAG.getFrameIndex(RASI, PtrVT);
3391 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
3392 MachineFunction &MF = DAG.getMachineFunction();
3393 bool isPPC64 = PPCSubTarget.isPPC64();
3394 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3395 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3397 // Get current frame pointer save index. The users of this index will be
3398 // primarily DYNALLOC instructions.
3399 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3400 int FPSI = FI->getFramePointerSaveIndex();
3402 // If the frame pointer save index hasn't been defined yet.
3404 // Find out what the fix offset of the frame pointer save area.
3405 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
3408 // Allocate the frame index for frame pointer save area.
3409 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
3411 FI->setFramePointerSaveIndex(FPSI);
3413 return DAG.getFrameIndex(FPSI, PtrVT);
3416 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3418 const PPCSubtarget &Subtarget) const {
3420 SDValue Chain = Op.getOperand(0);
3421 SDValue Size = Op.getOperand(1);
3422 DebugLoc dl = Op.getDebugLoc();
3424 // Get the corect type for pointers.
3425 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3427 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
3428 DAG.getConstant(0, PtrVT), Size);
3429 // Construct a node for the frame pointer save index.
3430 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
3431 // Build a DYNALLOC node.
3432 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
3433 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
3434 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
3437 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
3439 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3440 // Not FP? Not a fsel.
3441 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
3442 !Op.getOperand(2).getValueType().isFloatingPoint())
3445 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3447 // Cannot handle SETEQ/SETNE.
3448 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
3450 EVT ResVT = Op.getValueType();
3451 EVT CmpVT = Op.getOperand(0).getValueType();
3452 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3453 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
3454 DebugLoc dl = Op.getDebugLoc();
3456 // If the RHS of the comparison is a 0.0, we don't need to do the
3457 // subtraction at all.
3458 if (isFloatingPointZero(RHS))
3460 default: break; // SETUO etc aren't handled by fsel.
3463 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3466 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3467 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3468 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
3471 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3474 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3475 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3476 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
3477 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
3482 default: break; // SETUO etc aren't handled by fsel.
3485 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3486 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3487 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3488 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3491 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3492 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3493 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3494 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3497 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3498 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3499 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3500 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3503 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3504 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3505 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3506 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3511 // FIXME: Split this code up when LegalizeDAGTypes lands.
3512 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
3513 DebugLoc dl) const {
3514 assert(Op.getOperand(0).getValueType().isFloatingPoint());
3515 SDValue Src = Op.getOperand(0);
3516 if (Src.getValueType() == MVT::f32)
3517 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
3520 switch (Op.getValueType().getSimpleVT().SimpleTy) {
3521 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
3523 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
3528 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
3532 // Convert the FP value to an int value through memory.
3533 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
3535 // Emit a store to the stack slot.
3536 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
3537 MachinePointerInfo(), false, false, 0);
3539 // Result is a load from the stack slot. If loading 4 bytes, make sure to
3541 if (Op.getValueType() == MVT::i32)
3542 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
3543 DAG.getConstant(4, FIPtr.getValueType()));
3544 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(),
3548 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op,
3549 SelectionDAG &DAG) const {
3550 DebugLoc dl = Op.getDebugLoc();
3551 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
3552 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
3555 if (Op.getOperand(0).getValueType() == MVT::i64) {
3556 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0));
3557 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
3558 if (Op.getValueType() == MVT::f32)
3559 FP = DAG.getNode(ISD::FP_ROUND, dl,
3560 MVT::f32, FP, DAG.getIntPtrConstant(0));
3564 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
3565 "Unhandled SINT_TO_FP type in custom expander!");
3566 // Since we only generate this in 64-bit mode, we can take advantage of
3567 // 64-bit registers. In particular, sign extend the input value into the
3568 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
3569 // then lfd it and fcfid it.
3570 MachineFunction &MF = DAG.getMachineFunction();
3571 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
3572 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
3573 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3574 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3576 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
3579 // STD the extended value into the stack slot.
3580 MachineMemOperand *MMO =
3581 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
3582 MachineMemOperand::MOStore, 8, 8);
3583 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
3585 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other),
3586 Ops, 4, MVT::i64, MMO);
3587 // Load the value as a double.
3588 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(),
3591 // FCFID it and return it.
3592 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
3593 if (Op.getValueType() == MVT::f32)
3594 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
3598 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3599 SelectionDAG &DAG) const {
3600 DebugLoc dl = Op.getDebugLoc();
3602 The rounding mode is in bits 30:31 of FPSR, and has the following
3609 FLT_ROUNDS, on the other hand, expects the following:
3616 To perform the conversion, we do:
3617 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
3620 MachineFunction &MF = DAG.getMachineFunction();
3621 EVT VT = Op.getValueType();
3622 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3623 std::vector<EVT> NodeTys;
3624 SDValue MFFSreg, InFlag;
3626 // Save FP Control Word to register
3627 NodeTys.push_back(MVT::f64); // return register
3628 NodeTys.push_back(MVT::Glue); // unused in this context
3629 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
3631 // Save FP register to stack slot
3632 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
3633 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
3634 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
3635 StackSlot, MachinePointerInfo(), false, false,0);
3637 // Load FP Control Word from low 32 bits of stack slot.
3638 SDValue Four = DAG.getConstant(4, PtrVT);
3639 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
3640 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
3643 // Transform as necessary
3645 DAG.getNode(ISD::AND, dl, MVT::i32,
3646 CWD, DAG.getConstant(3, MVT::i32));
3648 DAG.getNode(ISD::SRL, dl, MVT::i32,
3649 DAG.getNode(ISD::AND, dl, MVT::i32,
3650 DAG.getNode(ISD::XOR, dl, MVT::i32,
3651 CWD, DAG.getConstant(3, MVT::i32)),
3652 DAG.getConstant(3, MVT::i32)),
3653 DAG.getConstant(1, MVT::i32));
3656 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
3658 return DAG.getNode((VT.getSizeInBits() < 16 ?
3659 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3662 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3663 EVT VT = Op.getValueType();
3664 unsigned BitWidth = VT.getSizeInBits();
3665 DebugLoc dl = Op.getDebugLoc();
3666 assert(Op.getNumOperands() == 3 &&
3667 VT == Op.getOperand(1).getValueType() &&
3670 // Expand into a bunch of logical ops. Note that these ops
3671 // depend on the PPC behavior for oversized shift amounts.
3672 SDValue Lo = Op.getOperand(0);
3673 SDValue Hi = Op.getOperand(1);
3674 SDValue Amt = Op.getOperand(2);
3675 EVT AmtVT = Amt.getValueType();
3677 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3678 DAG.getConstant(BitWidth, AmtVT), Amt);
3679 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3680 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3681 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3682 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3683 DAG.getConstant(-BitWidth, AmtVT));
3684 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3685 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3686 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3687 SDValue OutOps[] = { OutLo, OutHi };
3688 return DAG.getMergeValues(OutOps, 2, dl);
3691 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3692 EVT VT = Op.getValueType();
3693 DebugLoc dl = Op.getDebugLoc();
3694 unsigned BitWidth = VT.getSizeInBits();
3695 assert(Op.getNumOperands() == 3 &&
3696 VT == Op.getOperand(1).getValueType() &&
3699 // Expand into a bunch of logical ops. Note that these ops
3700 // depend on the PPC behavior for oversized shift amounts.
3701 SDValue Lo = Op.getOperand(0);
3702 SDValue Hi = Op.getOperand(1);
3703 SDValue Amt = Op.getOperand(2);
3704 EVT AmtVT = Amt.getValueType();
3706 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3707 DAG.getConstant(BitWidth, AmtVT), Amt);
3708 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3709 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3710 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3711 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3712 DAG.getConstant(-BitWidth, AmtVT));
3713 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3714 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3715 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3716 SDValue OutOps[] = { OutLo, OutHi };
3717 return DAG.getMergeValues(OutOps, 2, dl);
3720 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
3721 DebugLoc dl = Op.getDebugLoc();
3722 EVT VT = Op.getValueType();
3723 unsigned BitWidth = VT.getSizeInBits();
3724 assert(Op.getNumOperands() == 3 &&
3725 VT == Op.getOperand(1).getValueType() &&
3728 // Expand into a bunch of logical ops, followed by a select_cc.
3729 SDValue Lo = Op.getOperand(0);
3730 SDValue Hi = Op.getOperand(1);
3731 SDValue Amt = Op.getOperand(2);
3732 EVT AmtVT = Amt.getValueType();
3734 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3735 DAG.getConstant(BitWidth, AmtVT), Amt);
3736 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3737 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3738 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3739 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3740 DAG.getConstant(-BitWidth, AmtVT));
3741 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3742 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3743 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
3744 Tmp4, Tmp6, ISD::SETLE);
3745 SDValue OutOps[] = { OutLo, OutHi };
3746 return DAG.getMergeValues(OutOps, 2, dl);
3749 //===----------------------------------------------------------------------===//
3750 // Vector related lowering.
3753 /// BuildSplatI - Build a canonical splati of Val with an element size of
3754 /// SplatSize. Cast the result to VT.
3755 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
3756 SelectionDAG &DAG, DebugLoc dl) {
3757 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3759 static const EVT VTys[] = { // canonical VT to use for each size.
3760 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3763 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3765 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3769 EVT CanonicalVT = VTys[SplatSize-1];
3771 // Build a canonical splat for this value.
3772 SDValue Elt = DAG.getConstant(Val, MVT::i32);
3773 SmallVector<SDValue, 8> Ops;
3774 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3775 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
3776 &Ops[0], Ops.size());
3777 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
3780 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3781 /// specified intrinsic ID.
3782 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3783 SelectionDAG &DAG, DebugLoc dl,
3784 EVT DestVT = MVT::Other) {
3785 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3786 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3787 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3790 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3791 /// specified intrinsic ID.
3792 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3793 SDValue Op2, SelectionDAG &DAG,
3794 DebugLoc dl, EVT DestVT = MVT::Other) {
3795 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3796 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3797 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3801 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3802 /// amount. The result has the specified value type.
3803 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3804 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3805 // Force LHS/RHS to be the right type.
3806 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
3807 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
3810 for (unsigned i = 0; i != 16; ++i)
3812 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
3813 return DAG.getNode(ISD::BITCAST, dl, VT, T);
3816 // If this is a case we can't handle, return null and let the default
3817 // expansion code take care of it. If we CAN select this case, and if it
3818 // selects to a single instruction, return Op. Otherwise, if we can codegen
3819 // this case more efficiently than a constant pool load, lower it to the
3820 // sequence of ops that should be used.
3821 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
3822 SelectionDAG &DAG) const {
3823 DebugLoc dl = Op.getDebugLoc();
3824 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3825 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
3827 // Check if this is a splat of a constant value.
3828 APInt APSplatBits, APSplatUndef;
3829 unsigned SplatBitSize;
3831 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
3832 HasAnyUndefs, 0, true) || SplatBitSize > 32)
3835 unsigned SplatBits = APSplatBits.getZExtValue();
3836 unsigned SplatUndef = APSplatUndef.getZExtValue();
3837 unsigned SplatSize = SplatBitSize / 8;
3839 // First, handle single instruction cases.
3842 if (SplatBits == 0) {
3843 // Canonicalize all zero vectors to be v4i32.
3844 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3845 SDValue Z = DAG.getConstant(0, MVT::i32);
3846 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
3847 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
3852 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3853 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
3855 if (SextVal >= -16 && SextVal <= 15)
3856 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
3859 // Two instruction sequences.
3861 // If this value is in the range [-32,30] and is even, use:
3862 // tmp = VSPLTI[bhw], result = add tmp, tmp
3863 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
3864 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
3865 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
3866 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3869 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
3870 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
3872 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
3873 // Make -1 and vspltisw -1:
3874 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
3876 // Make the VSLW intrinsic, computing 0x8000_0000.
3877 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
3880 // xor by OnesV to invert it.
3881 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
3882 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3885 // Check to see if this is a wide variety of vsplti*, binop self cases.
3886 static const signed char SplatCsts[] = {
3887 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
3888 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
3891 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
3892 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
3893 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
3894 int i = SplatCsts[idx];
3896 // Figure out what shift amount will be used by altivec if shifted by i in
3898 unsigned TypeShiftAmt = i & (SplatBitSize-1);
3900 // vsplti + shl self.
3901 if (SextVal == (i << (int)TypeShiftAmt)) {
3902 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3903 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3904 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
3905 Intrinsic::ppc_altivec_vslw
3907 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3908 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3911 // vsplti + srl self.
3912 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3913 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3914 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3915 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
3916 Intrinsic::ppc_altivec_vsrw
3918 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3919 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3922 // vsplti + sra self.
3923 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3924 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3925 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3926 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
3927 Intrinsic::ppc_altivec_vsraw
3929 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3930 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3933 // vsplti + rol self.
3934 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
3935 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
3936 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3937 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3938 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
3939 Intrinsic::ppc_altivec_vrlw
3941 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3942 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
3945 // t = vsplti c, result = vsldoi t, t, 1
3946 if (SextVal == ((i << 8) | (i < 0 ? 0xFF : 0))) {
3947 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3948 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
3950 // t = vsplti c, result = vsldoi t, t, 2
3951 if (SextVal == ((i << 16) | (i < 0 ? 0xFFFF : 0))) {
3952 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3953 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
3955 // t = vsplti c, result = vsldoi t, t, 3
3956 if (SextVal == ((i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
3957 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3958 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
3962 // Three instruction sequences.
3964 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
3965 if (SextVal >= 0 && SextVal <= 31) {
3966 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
3967 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3968 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
3969 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
3971 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
3972 if (SextVal >= -31 && SextVal <= 0) {
3973 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
3974 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3975 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
3976 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
3982 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3983 /// the specified operations to build the shuffle.
3984 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3985 SDValue RHS, SelectionDAG &DAG,
3987 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3988 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3989 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3992 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4004 if (OpNum == OP_COPY) {
4005 if (LHSID == (1*9+2)*9+3) return LHS;
4006 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4010 SDValue OpLHS, OpRHS;
4011 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4012 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4016 default: llvm_unreachable("Unknown i32 permute!");
4018 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
4019 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
4020 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
4021 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
4024 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
4025 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
4026 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
4027 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
4030 for (unsigned i = 0; i != 16; ++i)
4031 ShufIdxs[i] = (i&3)+0;
4034 for (unsigned i = 0; i != 16; ++i)
4035 ShufIdxs[i] = (i&3)+4;
4038 for (unsigned i = 0; i != 16; ++i)
4039 ShufIdxs[i] = (i&3)+8;
4042 for (unsigned i = 0; i != 16; ++i)
4043 ShufIdxs[i] = (i&3)+12;
4046 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
4048 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
4050 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
4052 EVT VT = OpLHS.getValueType();
4053 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
4054 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
4055 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
4056 return DAG.getNode(ISD::BITCAST, dl, VT, T);
4059 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
4060 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
4061 /// return the code it can be lowered into. Worst case, it can always be
4062 /// lowered into a vperm.
4063 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4064 SelectionDAG &DAG) const {
4065 DebugLoc dl = Op.getDebugLoc();
4066 SDValue V1 = Op.getOperand(0);
4067 SDValue V2 = Op.getOperand(1);
4068 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4069 EVT VT = Op.getValueType();
4071 // Cases that are handled by instructions that take permute immediates
4072 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
4073 // selected by the instruction selector.
4074 if (V2.getOpcode() == ISD::UNDEF) {
4075 if (PPC::isSplatShuffleMask(SVOp, 1) ||
4076 PPC::isSplatShuffleMask(SVOp, 2) ||
4077 PPC::isSplatShuffleMask(SVOp, 4) ||
4078 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
4079 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
4080 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
4081 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
4082 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
4083 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
4084 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
4085 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
4086 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
4091 // Altivec has a variety of "shuffle immediates" that take two vector inputs
4092 // and produce a fixed permutation. If any of these match, do not lower to
4094 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
4095 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
4096 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
4097 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
4098 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
4099 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
4100 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
4101 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
4102 PPC::isVMRGHShuffleMask(SVOp, 4, false))
4105 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
4106 // perfect shuffle table to emit an optimal matching sequence.
4107 SmallVector<int, 16> PermMask;
4108 SVOp->getMask(PermMask);
4110 unsigned PFIndexes[4];
4111 bool isFourElementShuffle = true;
4112 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
4113 unsigned EltNo = 8; // Start out undef.
4114 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
4115 if (PermMask[i*4+j] < 0)
4116 continue; // Undef, ignore it.
4118 unsigned ByteSource = PermMask[i*4+j];
4119 if ((ByteSource & 3) != j) {
4120 isFourElementShuffle = false;
4125 EltNo = ByteSource/4;
4126 } else if (EltNo != ByteSource/4) {
4127 isFourElementShuffle = false;
4131 PFIndexes[i] = EltNo;
4134 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
4135 // perfect shuffle vector to determine if it is cost effective to do this as
4136 // discrete instructions, or whether we should use a vperm.
4137 if (isFourElementShuffle) {
4138 // Compute the index in the perfect shuffle table.
4139 unsigned PFTableIndex =
4140 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4142 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4143 unsigned Cost = (PFEntry >> 30);
4145 // Determining when to avoid vperm is tricky. Many things affect the cost
4146 // of vperm, particularly how many times the perm mask needs to be computed.
4147 // For example, if the perm mask can be hoisted out of a loop or is already
4148 // used (perhaps because there are multiple permutes with the same shuffle
4149 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
4150 // the loop requires an extra register.
4152 // As a compromise, we only emit discrete instructions if the shuffle can be
4153 // generated in 3 or fewer operations. When we have loop information
4154 // available, if this block is within a loop, we should avoid using vperm
4155 // for 3-operation perms and use a constant pool load instead.
4157 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4160 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
4161 // vector that will get spilled to the constant pool.
4162 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
4164 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
4165 // that it is in input element units, not in bytes. Convert now.
4166 EVT EltVT = V1.getValueType().getVectorElementType();
4167 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
4169 SmallVector<SDValue, 16> ResultMask;
4170 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
4171 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
4173 for (unsigned j = 0; j != BytesPerElement; ++j)
4174 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
4178 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
4179 &ResultMask[0], ResultMask.size());
4180 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
4183 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
4184 /// altivec comparison. If it is, return true and fill in Opc/isDot with
4185 /// information about the intrinsic.
4186 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
4188 unsigned IntrinsicID =
4189 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
4192 switch (IntrinsicID) {
4193 default: return false;
4194 // Comparison predicates.
4195 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
4196 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
4197 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
4198 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
4199 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
4200 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
4201 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
4202 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
4203 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
4204 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
4205 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
4206 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
4207 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
4209 // Normal Comparisons.
4210 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
4211 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
4212 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
4213 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
4214 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
4215 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
4216 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
4217 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
4218 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
4219 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
4220 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
4221 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
4222 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
4227 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
4228 /// lower, do it, otherwise return null.
4229 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
4230 SelectionDAG &DAG) const {
4231 // If this is a lowered altivec predicate compare, CompareOpc is set to the
4232 // opcode number of the comparison.
4233 DebugLoc dl = Op.getDebugLoc();
4236 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
4237 return SDValue(); // Don't custom lower most intrinsics.
4239 // If this is a non-dot comparison, make the VCMP node and we are done.
4241 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
4242 Op.getOperand(1), Op.getOperand(2),
4243 DAG.getConstant(CompareOpc, MVT::i32));
4244 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
4247 // Create the PPCISD altivec 'dot' comparison node.
4249 Op.getOperand(2), // LHS
4250 Op.getOperand(3), // RHS
4251 DAG.getConstant(CompareOpc, MVT::i32)
4253 std::vector<EVT> VTs;
4254 VTs.push_back(Op.getOperand(2).getValueType());
4255 VTs.push_back(MVT::Glue);
4256 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
4258 // Now that we have the comparison, emit a copy from the CR to a GPR.
4259 // This is flagged to the above dot comparison.
4260 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
4261 DAG.getRegister(PPC::CR6, MVT::i32),
4262 CompNode.getValue(1));
4264 // Unpack the result based on how the target uses it.
4265 unsigned BitNo; // Bit # of CR6.
4266 bool InvertBit; // Invert result?
4267 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
4268 default: // Can't happen, don't crash on invalid number though.
4269 case 0: // Return the value of the EQ bit of CR6.
4270 BitNo = 0; InvertBit = false;
4272 case 1: // Return the inverted value of the EQ bit of CR6.
4273 BitNo = 0; InvertBit = true;
4275 case 2: // Return the value of the LT bit of CR6.
4276 BitNo = 2; InvertBit = false;
4278 case 3: // Return the inverted value of the LT bit of CR6.
4279 BitNo = 2; InvertBit = true;
4283 // Shift the bit into the low position.
4284 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
4285 DAG.getConstant(8-(3-BitNo), MVT::i32));
4287 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
4288 DAG.getConstant(1, MVT::i32));
4290 // If we are supposed to, toggle the bit.
4292 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
4293 DAG.getConstant(1, MVT::i32));
4297 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
4298 SelectionDAG &DAG) const {
4299 DebugLoc dl = Op.getDebugLoc();
4300 // Create a stack slot that is 16-byte aligned.
4301 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4302 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
4303 EVT PtrVT = getPointerTy();
4304 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4306 // Store the input value into Value#0 of the stack slot.
4307 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
4308 Op.getOperand(0), FIdx, MachinePointerInfo(),
4311 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
4315 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
4316 DebugLoc dl = Op.getDebugLoc();
4317 if (Op.getValueType() == MVT::v4i32) {
4318 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4320 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
4321 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
4323 SDValue RHSSwap = // = vrlw RHS, 16
4324 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
4326 // Shrinkify inputs to v8i16.
4327 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
4328 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
4329 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
4331 // Low parts multiplied together, generating 32-bit results (we ignore the
4333 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
4334 LHS, RHS, DAG, dl, MVT::v4i32);
4336 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
4337 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
4338 // Shift the high parts up 16 bits.
4339 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
4341 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
4342 } else if (Op.getValueType() == MVT::v8i16) {
4343 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4345 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
4347 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
4348 LHS, RHS, Zero, DAG, dl);
4349 } else if (Op.getValueType() == MVT::v16i8) {
4350 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4352 // Multiply the even 8-bit parts, producing 16-bit sums.
4353 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
4354 LHS, RHS, DAG, dl, MVT::v8i16);
4355 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
4357 // Multiply the odd 8-bit parts, producing 16-bit sums.
4358 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
4359 LHS, RHS, DAG, dl, MVT::v8i16);
4360 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
4362 // Merge the results together.
4364 for (unsigned i = 0; i != 8; ++i) {
4366 Ops[i*2+1] = 2*i+1+16;
4368 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
4370 llvm_unreachable("Unknown mul to lower!");
4374 /// LowerOperation - Provide custom lowering hooks for some operations.
4376 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4377 switch (Op.getOpcode()) {
4378 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
4379 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4380 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4381 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4382 case ISD::GlobalTLSAddress: llvm_unreachable("TLS not implemented for PPC");
4383 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4384 case ISD::SETCC: return LowerSETCC(Op, DAG);
4385 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
4387 return LowerVASTART(Op, DAG, PPCSubTarget);
4390 return LowerVAARG(Op, DAG, PPCSubTarget);
4392 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
4393 case ISD::DYNAMIC_STACKALLOC:
4394 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
4396 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4397 case ISD::FP_TO_UINT:
4398 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
4400 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4401 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4403 // Lower 64-bit shifts.
4404 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
4405 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
4406 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
4408 // Vector-related lowering.
4409 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4410 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4411 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4412 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4413 case ISD::MUL: return LowerMUL(Op, DAG);
4415 // Frame & Return address.
4416 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4417 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4422 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
4423 SmallVectorImpl<SDValue>&Results,
4424 SelectionDAG &DAG) const {
4425 DebugLoc dl = N->getDebugLoc();
4426 switch (N->getOpcode()) {
4428 assert(false && "Do not know how to custom type legalize this operation!");
4430 case ISD::FP_ROUND_INREG: {
4431 assert(N->getValueType(0) == MVT::ppcf128);
4432 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
4433 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4434 MVT::f64, N->getOperand(0),
4435 DAG.getIntPtrConstant(0));
4436 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4437 MVT::f64, N->getOperand(0),
4438 DAG.getIntPtrConstant(1));
4440 // This sequence changes FPSCR to do round-to-zero, adds the two halves
4441 // of the long double, and puts FPSCR back the way it was. We do not
4442 // actually model FPSCR.
4443 std::vector<EVT> NodeTys;
4444 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
4446 NodeTys.push_back(MVT::f64); // Return register
4447 NodeTys.push_back(MVT::Glue); // Returns a flag for later insns
4448 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4449 MFFSreg = Result.getValue(0);
4450 InFlag = Result.getValue(1);
4453 NodeTys.push_back(MVT::Glue); // Returns a flag
4454 Ops[0] = DAG.getConstant(31, MVT::i32);
4456 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
4457 InFlag = Result.getValue(0);
4460 NodeTys.push_back(MVT::Glue); // Returns a flag
4461 Ops[0] = DAG.getConstant(30, MVT::i32);
4463 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
4464 InFlag = Result.getValue(0);
4467 NodeTys.push_back(MVT::f64); // result of add
4468 NodeTys.push_back(MVT::Glue); // Returns a flag
4472 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
4473 FPreg = Result.getValue(0);
4474 InFlag = Result.getValue(1);
4477 NodeTys.push_back(MVT::f64);
4478 Ops[0] = DAG.getConstant(1, MVT::i32);
4482 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
4483 FPreg = Result.getValue(0);
4485 // We know the low half is about to be thrown away, so just use something
4487 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
4491 case ISD::FP_TO_SINT:
4492 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
4498 //===----------------------------------------------------------------------===//
4499 // Other Lowering Code
4500 //===----------------------------------------------------------------------===//
4503 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4504 bool is64bit, unsigned BinOpcode) const {
4505 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4506 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4508 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4509 MachineFunction *F = BB->getParent();
4510 MachineFunction::iterator It = BB;
4513 unsigned dest = MI->getOperand(0).getReg();
4514 unsigned ptrA = MI->getOperand(1).getReg();
4515 unsigned ptrB = MI->getOperand(2).getReg();
4516 unsigned incr = MI->getOperand(3).getReg();
4517 DebugLoc dl = MI->getDebugLoc();
4519 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4520 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4521 F->insert(It, loopMBB);
4522 F->insert(It, exitMBB);
4523 exitMBB->splice(exitMBB->begin(), BB,
4524 llvm::next(MachineBasicBlock::iterator(MI)),
4526 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4528 MachineRegisterInfo &RegInfo = F->getRegInfo();
4529 unsigned TmpReg = (!BinOpcode) ? incr :
4530 RegInfo.createVirtualRegister(
4531 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4532 (const TargetRegisterClass *) &PPC::GPRCRegClass);
4536 // fallthrough --> loopMBB
4537 BB->addSuccessor(loopMBB);
4540 // l[wd]arx dest, ptr
4541 // add r0, dest, incr
4542 // st[wd]cx. r0, ptr
4544 // fallthrough --> exitMBB
4546 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4547 .addReg(ptrA).addReg(ptrB);
4549 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
4550 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4551 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
4552 BuildMI(BB, dl, TII->get(PPC::BCC))
4553 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4554 BB->addSuccessor(loopMBB);
4555 BB->addSuccessor(exitMBB);
4564 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
4565 MachineBasicBlock *BB,
4566 bool is8bit, // operation
4567 unsigned BinOpcode) const {
4568 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4569 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4570 // In 64 bit mode we have to use 64 bits for addresses, even though the
4571 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
4572 // registers without caring whether they're 32 or 64, but here we're
4573 // doing actual arithmetic on the addresses.
4574 bool is64bit = PPCSubTarget.isPPC64();
4576 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4577 MachineFunction *F = BB->getParent();
4578 MachineFunction::iterator It = BB;
4581 unsigned dest = MI->getOperand(0).getReg();
4582 unsigned ptrA = MI->getOperand(1).getReg();
4583 unsigned ptrB = MI->getOperand(2).getReg();
4584 unsigned incr = MI->getOperand(3).getReg();
4585 DebugLoc dl = MI->getDebugLoc();
4587 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4588 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4589 F->insert(It, loopMBB);
4590 F->insert(It, exitMBB);
4591 exitMBB->splice(exitMBB->begin(), BB,
4592 llvm::next(MachineBasicBlock::iterator(MI)),
4594 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4596 MachineRegisterInfo &RegInfo = F->getRegInfo();
4597 const TargetRegisterClass *RC =
4598 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4599 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4600 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4601 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4602 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4603 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4604 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4605 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4606 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4607 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4608 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
4609 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4610 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4612 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
4616 // fallthrough --> loopMBB
4617 BB->addSuccessor(loopMBB);
4619 // The 4-byte load must be aligned, while a char or short may be
4620 // anywhere in the word. Hence all this nasty bookkeeping code.
4621 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4622 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4623 // xori shift, shift1, 24 [16]
4624 // rlwinm ptr, ptr1, 0, 0, 29
4625 // slw incr2, incr, shift
4626 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4627 // slw mask, mask2, shift
4629 // lwarx tmpDest, ptr
4630 // add tmp, tmpDest, incr2
4631 // andc tmp2, tmpDest, mask
4632 // and tmp3, tmp, mask
4633 // or tmp4, tmp3, tmp2
4636 // fallthrough --> exitMBB
4637 // srw dest, tmpDest, shift
4639 if (ptrA!=PPC::R0) {
4640 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4641 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4642 .addReg(ptrA).addReg(ptrB);
4646 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4647 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4648 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4649 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4651 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4652 .addReg(Ptr1Reg).addImm(0).addImm(61);
4654 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4655 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4656 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
4657 .addReg(incr).addReg(ShiftReg);
4659 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4661 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4662 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
4664 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4665 .addReg(Mask2Reg).addReg(ShiftReg);
4668 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4669 .addReg(PPC::R0).addReg(PtrReg);
4671 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
4672 .addReg(Incr2Reg).addReg(TmpDestReg);
4673 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4674 .addReg(TmpDestReg).addReg(MaskReg);
4675 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4676 .addReg(TmpReg).addReg(MaskReg);
4677 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4678 .addReg(Tmp3Reg).addReg(Tmp2Reg);
4679 BuildMI(BB, dl, TII->get(PPC::STWCX))
4680 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
4681 BuildMI(BB, dl, TII->get(PPC::BCC))
4682 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4683 BB->addSuccessor(loopMBB);
4684 BB->addSuccessor(exitMBB);
4689 BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
4694 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4695 MachineBasicBlock *BB) const {
4696 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4698 // To "insert" these instructions we actually have to insert their
4699 // control-flow patterns.
4700 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4701 MachineFunction::iterator It = BB;
4704 MachineFunction *F = BB->getParent();
4706 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4707 MI->getOpcode() == PPC::SELECT_CC_I8 ||
4708 MI->getOpcode() == PPC::SELECT_CC_F4 ||
4709 MI->getOpcode() == PPC::SELECT_CC_F8 ||
4710 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4712 // The incoming instruction knows the destination vreg to set, the
4713 // condition code register to branch on, the true/false values to
4714 // select between, and a branch opcode to use.
4719 // cmpTY ccX, r1, r2
4721 // fallthrough --> copy0MBB
4722 MachineBasicBlock *thisMBB = BB;
4723 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4724 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4725 unsigned SelectPred = MI->getOperand(4).getImm();
4726 DebugLoc dl = MI->getDebugLoc();
4727 F->insert(It, copy0MBB);
4728 F->insert(It, sinkMBB);
4730 // Transfer the remainder of BB and its successor edges to sinkMBB.
4731 sinkMBB->splice(sinkMBB->begin(), BB,
4732 llvm::next(MachineBasicBlock::iterator(MI)),
4734 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4736 // Next, add the true and fallthrough blocks as its successors.
4737 BB->addSuccessor(copy0MBB);
4738 BB->addSuccessor(sinkMBB);
4740 BuildMI(BB, dl, TII->get(PPC::BCC))
4741 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4744 // %FalseValue = ...
4745 // # fallthrough to sinkMBB
4748 // Update machine-CFG edges
4749 BB->addSuccessor(sinkMBB);
4752 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4755 BuildMI(*BB, BB->begin(), dl,
4756 TII->get(PPC::PHI), MI->getOperand(0).getReg())
4757 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4758 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4760 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4761 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4762 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4763 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4764 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4765 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4766 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4767 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4769 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4770 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4771 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4772 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4773 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4774 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4775 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4776 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4778 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4779 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4780 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4781 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4782 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4783 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4784 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4785 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4787 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4788 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4789 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4790 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4791 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4792 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4793 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4794 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4796 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4797 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
4798 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4799 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
4800 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4801 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
4802 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4803 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
4805 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
4806 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
4807 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
4808 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
4809 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
4810 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
4811 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
4812 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
4814 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
4815 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
4816 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
4817 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
4818 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
4819 BB = EmitAtomicBinary(MI, BB, false, 0);
4820 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
4821 BB = EmitAtomicBinary(MI, BB, true, 0);
4823 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
4824 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
4825 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
4827 unsigned dest = MI->getOperand(0).getReg();
4828 unsigned ptrA = MI->getOperand(1).getReg();
4829 unsigned ptrB = MI->getOperand(2).getReg();
4830 unsigned oldval = MI->getOperand(3).getReg();
4831 unsigned newval = MI->getOperand(4).getReg();
4832 DebugLoc dl = MI->getDebugLoc();
4834 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4835 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4836 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4837 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4838 F->insert(It, loop1MBB);
4839 F->insert(It, loop2MBB);
4840 F->insert(It, midMBB);
4841 F->insert(It, exitMBB);
4842 exitMBB->splice(exitMBB->begin(), BB,
4843 llvm::next(MachineBasicBlock::iterator(MI)),
4845 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4849 // fallthrough --> loopMBB
4850 BB->addSuccessor(loop1MBB);
4853 // l[wd]arx dest, ptr
4854 // cmp[wd] dest, oldval
4857 // st[wd]cx. newval, ptr
4861 // st[wd]cx. dest, ptr
4864 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4865 .addReg(ptrA).addReg(ptrB);
4866 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
4867 .addReg(oldval).addReg(dest);
4868 BuildMI(BB, dl, TII->get(PPC::BCC))
4869 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4870 BB->addSuccessor(loop2MBB);
4871 BB->addSuccessor(midMBB);
4874 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4875 .addReg(newval).addReg(ptrA).addReg(ptrB);
4876 BuildMI(BB, dl, TII->get(PPC::BCC))
4877 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4878 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4879 BB->addSuccessor(loop1MBB);
4880 BB->addSuccessor(exitMBB);
4883 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4884 .addReg(dest).addReg(ptrA).addReg(ptrB);
4885 BB->addSuccessor(exitMBB);
4890 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
4891 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
4892 // We must use 64-bit registers for addresses when targeting 64-bit,
4893 // since we're actually doing arithmetic on them. Other registers
4895 bool is64bit = PPCSubTarget.isPPC64();
4896 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
4898 unsigned dest = MI->getOperand(0).getReg();
4899 unsigned ptrA = MI->getOperand(1).getReg();
4900 unsigned ptrB = MI->getOperand(2).getReg();
4901 unsigned oldval = MI->getOperand(3).getReg();
4902 unsigned newval = MI->getOperand(4).getReg();
4903 DebugLoc dl = MI->getDebugLoc();
4905 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4906 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4907 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4908 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4909 F->insert(It, loop1MBB);
4910 F->insert(It, loop2MBB);
4911 F->insert(It, midMBB);
4912 F->insert(It, exitMBB);
4913 exitMBB->splice(exitMBB->begin(), BB,
4914 llvm::next(MachineBasicBlock::iterator(MI)),
4916 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4918 MachineRegisterInfo &RegInfo = F->getRegInfo();
4919 const TargetRegisterClass *RC =
4920 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4921 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4922 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4923 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4924 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4925 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
4926 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
4927 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
4928 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
4929 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4930 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4931 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4932 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4933 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4934 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4936 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
4939 // fallthrough --> loopMBB
4940 BB->addSuccessor(loop1MBB);
4942 // The 4-byte load must be aligned, while a char or short may be
4943 // anywhere in the word. Hence all this nasty bookkeeping code.
4944 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4945 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4946 // xori shift, shift1, 24 [16]
4947 // rlwinm ptr, ptr1, 0, 0, 29
4948 // slw newval2, newval, shift
4949 // slw oldval2, oldval,shift
4950 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4951 // slw mask, mask2, shift
4952 // and newval3, newval2, mask
4953 // and oldval3, oldval2, mask
4955 // lwarx tmpDest, ptr
4956 // and tmp, tmpDest, mask
4957 // cmpw tmp, oldval3
4960 // andc tmp2, tmpDest, mask
4961 // or tmp4, tmp2, newval3
4966 // stwcx. tmpDest, ptr
4968 // srw dest, tmpDest, shift
4969 if (ptrA!=PPC::R0) {
4970 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4971 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4972 .addReg(ptrA).addReg(ptrB);
4976 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4977 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4978 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4979 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4981 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4982 .addReg(Ptr1Reg).addImm(0).addImm(61);
4984 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4985 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4986 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
4987 .addReg(newval).addReg(ShiftReg);
4988 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
4989 .addReg(oldval).addReg(ShiftReg);
4991 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4993 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4994 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
4995 .addReg(Mask3Reg).addImm(65535);
4997 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4998 .addReg(Mask2Reg).addReg(ShiftReg);
4999 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
5000 .addReg(NewVal2Reg).addReg(MaskReg);
5001 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
5002 .addReg(OldVal2Reg).addReg(MaskReg);
5005 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
5006 .addReg(PPC::R0).addReg(PtrReg);
5007 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
5008 .addReg(TmpDestReg).addReg(MaskReg);
5009 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
5010 .addReg(TmpReg).addReg(OldVal3Reg);
5011 BuildMI(BB, dl, TII->get(PPC::BCC))
5012 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
5013 BB->addSuccessor(loop2MBB);
5014 BB->addSuccessor(midMBB);
5017 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
5018 .addReg(TmpDestReg).addReg(MaskReg);
5019 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
5020 .addReg(Tmp2Reg).addReg(NewVal3Reg);
5021 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
5022 .addReg(PPC::R0).addReg(PtrReg);
5023 BuildMI(BB, dl, TII->get(PPC::BCC))
5024 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
5025 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
5026 BB->addSuccessor(loop1MBB);
5027 BB->addSuccessor(exitMBB);
5030 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
5031 .addReg(PPC::R0).addReg(PtrReg);
5032 BB->addSuccessor(exitMBB);
5037 BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
5039 llvm_unreachable("Unexpected instr type to insert");
5042 MI->eraseFromParent(); // The pseudo instruction is gone now.
5046 //===----------------------------------------------------------------------===//
5047 // Target Optimization Hooks
5048 //===----------------------------------------------------------------------===//
5050 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
5051 DAGCombinerInfo &DCI) const {
5052 const TargetMachine &TM = getTargetMachine();
5053 SelectionDAG &DAG = DCI.DAG;
5054 DebugLoc dl = N->getDebugLoc();
5055 switch (N->getOpcode()) {
5058 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5059 if (C->isNullValue()) // 0 << V -> 0.
5060 return N->getOperand(0);
5064 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5065 if (C->isNullValue()) // 0 >>u V -> 0.
5066 return N->getOperand(0);
5070 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5071 if (C->isNullValue() || // 0 >>s V -> 0.
5072 C->isAllOnesValue()) // -1 >>s V -> -1.
5073 return N->getOperand(0);
5077 case ISD::SINT_TO_FP:
5078 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
5079 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
5080 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
5081 // We allow the src/dst to be either f32/f64, but the intermediate
5082 // type must be i64.
5083 if (N->getOperand(0).getValueType() == MVT::i64 &&
5084 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
5085 SDValue Val = N->getOperand(0).getOperand(0);
5086 if (Val.getValueType() == MVT::f32) {
5087 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5088 DCI.AddToWorklist(Val.getNode());
5091 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
5092 DCI.AddToWorklist(Val.getNode());
5093 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
5094 DCI.AddToWorklist(Val.getNode());
5095 if (N->getValueType(0) == MVT::f32) {
5096 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
5097 DAG.getIntPtrConstant(0));
5098 DCI.AddToWorklist(Val.getNode());
5101 } else if (N->getOperand(0).getValueType() == MVT::i32) {
5102 // If the intermediate type is i32, we can avoid the load/store here
5109 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
5110 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
5111 !cast<StoreSDNode>(N)->isTruncatingStore() &&
5112 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
5113 N->getOperand(1).getValueType() == MVT::i32 &&
5114 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
5115 SDValue Val = N->getOperand(1).getOperand(0);
5116 if (Val.getValueType() == MVT::f32) {
5117 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5118 DCI.AddToWorklist(Val.getNode());
5120 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
5121 DCI.AddToWorklist(Val.getNode());
5123 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
5124 N->getOperand(2), N->getOperand(3));
5125 DCI.AddToWorklist(Val.getNode());
5129 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
5130 if (cast<StoreSDNode>(N)->isUnindexed() &&
5131 N->getOperand(1).getOpcode() == ISD::BSWAP &&
5132 N->getOperand(1).getNode()->hasOneUse() &&
5133 (N->getOperand(1).getValueType() == MVT::i32 ||
5134 N->getOperand(1).getValueType() == MVT::i16)) {
5135 SDValue BSwapOp = N->getOperand(1).getOperand(0);
5136 // Do an any-extend to 32-bits if this is a half-word input.
5137 if (BSwapOp.getValueType() == MVT::i16)
5138 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
5141 N->getOperand(0), BSwapOp, N->getOperand(2),
5142 DAG.getValueType(N->getOperand(1).getValueType())
5145 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
5146 Ops, array_lengthof(Ops),
5147 cast<StoreSDNode>(N)->getMemoryVT(),
5148 cast<StoreSDNode>(N)->getMemOperand());
5152 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
5153 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
5154 N->getOperand(0).hasOneUse() &&
5155 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
5156 SDValue Load = N->getOperand(0);
5157 LoadSDNode *LD = cast<LoadSDNode>(Load);
5158 // Create the byte-swapping load.
5160 LD->getChain(), // Chain
5161 LD->getBasePtr(), // Ptr
5162 DAG.getValueType(N->getValueType(0)) // VT
5165 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
5166 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3,
5167 LD->getMemoryVT(), LD->getMemOperand());
5169 // If this is an i16 load, insert the truncate.
5170 SDValue ResVal = BSLoad;
5171 if (N->getValueType(0) == MVT::i16)
5172 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
5174 // First, combine the bswap away. This makes the value produced by the
5176 DCI.CombineTo(N, ResVal);
5178 // Next, combine the load away, we give it a bogus result value but a real
5179 // chain result. The result value is dead because the bswap is dead.
5180 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
5182 // Return N so it doesn't get rechecked!
5183 return SDValue(N, 0);
5187 case PPCISD::VCMP: {
5188 // If a VCMPo node already exists with exactly the same operands as this
5189 // node, use its result instead of this node (VCMPo computes both a CR6 and
5190 // a normal output).
5192 if (!N->getOperand(0).hasOneUse() &&
5193 !N->getOperand(1).hasOneUse() &&
5194 !N->getOperand(2).hasOneUse()) {
5196 // Scan all of the users of the LHS, looking for VCMPo's that match.
5197 SDNode *VCMPoNode = 0;
5199 SDNode *LHSN = N->getOperand(0).getNode();
5200 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
5202 if (UI->getOpcode() == PPCISD::VCMPo &&
5203 UI->getOperand(1) == N->getOperand(1) &&
5204 UI->getOperand(2) == N->getOperand(2) &&
5205 UI->getOperand(0) == N->getOperand(0)) {
5210 // If there is no VCMPo node, or if the flag value has a single use, don't
5212 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
5215 // Look at the (necessarily single) use of the flag value. If it has a
5216 // chain, this transformation is more complex. Note that multiple things
5217 // could use the value result, which we should ignore.
5218 SDNode *FlagUser = 0;
5219 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
5220 FlagUser == 0; ++UI) {
5221 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
5223 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
5224 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
5231 // If the user is a MFCR instruction, we know this is safe. Otherwise we
5232 // give up for right now.
5233 if (FlagUser->getOpcode() == PPCISD::MFCR)
5234 return SDValue(VCMPoNode, 0);
5239 // If this is a branch on an altivec predicate comparison, lower this so
5240 // that we don't have to do a MFCR: instead, branch directly on CR6. This
5241 // lowering is done pre-legalize, because the legalizer lowers the predicate
5242 // compare down to code that is difficult to reassemble.
5243 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
5244 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
5248 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
5249 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
5250 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
5251 assert(isDot && "Can't compare against a vector result!");
5253 // If this is a comparison against something other than 0/1, then we know
5254 // that the condition is never/always true.
5255 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
5256 if (Val != 0 && Val != 1) {
5257 if (CC == ISD::SETEQ) // Cond never true, remove branch.
5258 return N->getOperand(0);
5259 // Always !=, turn it into an unconditional branch.
5260 return DAG.getNode(ISD::BR, dl, MVT::Other,
5261 N->getOperand(0), N->getOperand(4));
5264 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
5266 // Create the PPCISD altivec 'dot' comparison node.
5267 std::vector<EVT> VTs;
5269 LHS.getOperand(2), // LHS of compare
5270 LHS.getOperand(3), // RHS of compare
5271 DAG.getConstant(CompareOpc, MVT::i32)
5273 VTs.push_back(LHS.getOperand(2).getValueType());
5274 VTs.push_back(MVT::Glue);
5275 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5277 // Unpack the result based on how the target uses it.
5278 PPC::Predicate CompOpc;
5279 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
5280 default: // Can't happen, don't crash on invalid number though.
5281 case 0: // Branch on the value of the EQ bit of CR6.
5282 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
5284 case 1: // Branch on the inverted value of the EQ bit of CR6.
5285 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
5287 case 2: // Branch on the value of the LT bit of CR6.
5288 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
5290 case 3: // Branch on the inverted value of the LT bit of CR6.
5291 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
5295 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
5296 DAG.getConstant(CompOpc, MVT::i32),
5297 DAG.getRegister(PPC::CR6, MVT::i32),
5298 N->getOperand(4), CompNode.getValue(1));
5307 //===----------------------------------------------------------------------===//
5308 // Inline Assembly Support
5309 //===----------------------------------------------------------------------===//
5311 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5315 const SelectionDAG &DAG,
5316 unsigned Depth) const {
5317 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5318 switch (Op.getOpcode()) {
5320 case PPCISD::LBRX: {
5321 // lhbrx is known to have the top bits cleared out.
5322 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
5323 KnownZero = 0xFFFF0000;
5326 case ISD::INTRINSIC_WO_CHAIN: {
5327 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
5329 case Intrinsic::ppc_altivec_vcmpbfp_p:
5330 case Intrinsic::ppc_altivec_vcmpeqfp_p:
5331 case Intrinsic::ppc_altivec_vcmpequb_p:
5332 case Intrinsic::ppc_altivec_vcmpequh_p:
5333 case Intrinsic::ppc_altivec_vcmpequw_p:
5334 case Intrinsic::ppc_altivec_vcmpgefp_p:
5335 case Intrinsic::ppc_altivec_vcmpgtfp_p:
5336 case Intrinsic::ppc_altivec_vcmpgtsb_p:
5337 case Intrinsic::ppc_altivec_vcmpgtsh_p:
5338 case Intrinsic::ppc_altivec_vcmpgtsw_p:
5339 case Intrinsic::ppc_altivec_vcmpgtub_p:
5340 case Intrinsic::ppc_altivec_vcmpgtuh_p:
5341 case Intrinsic::ppc_altivec_vcmpgtuw_p:
5342 KnownZero = ~1U; // All bits but the low one are known to be zero.
5350 /// getConstraintType - Given a constraint, return the type of
5351 /// constraint it is for this target.
5352 PPCTargetLowering::ConstraintType
5353 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
5354 if (Constraint.size() == 1) {
5355 switch (Constraint[0]) {
5362 return C_RegisterClass;
5365 return TargetLowering::getConstraintType(Constraint);
5368 /// Examine constraint type and operand type and determine a weight value.
5369 /// This object must already have been set up with the operand type
5370 /// and the current alternative constraint selected.
5371 TargetLowering::ConstraintWeight
5372 PPCTargetLowering::getSingleConstraintMatchWeight(
5373 AsmOperandInfo &info, const char *constraint) const {
5374 ConstraintWeight weight = CW_Invalid;
5375 Value *CallOperandVal = info.CallOperandVal;
5376 // If we don't have a value, we can't do a match,
5377 // but allow it at the lowest weight.
5378 if (CallOperandVal == NULL)
5380 const Type *type = CallOperandVal->getType();
5381 // Look at the constraint type.
5382 switch (*constraint) {
5384 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
5387 if (type->isIntegerTy())
5388 weight = CW_Register;
5391 if (type->isFloatTy())
5392 weight = CW_Register;
5395 if (type->isDoubleTy())
5396 weight = CW_Register;
5399 if (type->isVectorTy())
5400 weight = CW_Register;
5403 weight = CW_Register;
5409 std::pair<unsigned, const TargetRegisterClass*>
5410 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5412 if (Constraint.size() == 1) {
5413 // GCC RS6000 Constraint Letters
5414 switch (Constraint[0]) {
5417 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
5418 return std::make_pair(0U, PPC::G8RCRegisterClass);
5419 return std::make_pair(0U, PPC::GPRCRegisterClass);
5422 return std::make_pair(0U, PPC::F4RCRegisterClass);
5423 else if (VT == MVT::f64)
5424 return std::make_pair(0U, PPC::F8RCRegisterClass);
5427 return std::make_pair(0U, PPC::VRRCRegisterClass);
5429 return std::make_pair(0U, PPC::CRRCRegisterClass);
5433 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5437 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5438 /// vector. If it is invalid, don't add anything to Ops.
5439 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
5440 std::vector<SDValue>&Ops,
5441 SelectionDAG &DAG) const {
5442 SDValue Result(0,0);
5453 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
5454 if (!CST) return; // Must be an immediate to match.
5455 unsigned Value = CST->getZExtValue();
5457 default: llvm_unreachable("Unknown constraint letter!");
5458 case 'I': // "I" is a signed 16-bit constant.
5459 if ((short)Value == (int)Value)
5460 Result = DAG.getTargetConstant(Value, Op.getValueType());
5462 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
5463 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
5464 if ((short)Value == 0)
5465 Result = DAG.getTargetConstant(Value, Op.getValueType());
5467 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
5468 if ((Value >> 16) == 0)
5469 Result = DAG.getTargetConstant(Value, Op.getValueType());
5471 case 'M': // "M" is a constant that is greater than 31.
5473 Result = DAG.getTargetConstant(Value, Op.getValueType());
5475 case 'N': // "N" is a positive constant that is an exact power of two.
5476 if ((int)Value > 0 && isPowerOf2_32(Value))
5477 Result = DAG.getTargetConstant(Value, Op.getValueType());
5479 case 'O': // "O" is the constant zero.
5481 Result = DAG.getTargetConstant(Value, Op.getValueType());
5483 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
5484 if ((short)-Value == (int)-Value)
5485 Result = DAG.getTargetConstant(Value, Op.getValueType());
5492 if (Result.getNode()) {
5493 Ops.push_back(Result);
5497 // Handle standard constraint letters.
5498 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
5501 // isLegalAddressingMode - Return true if the addressing mode represented
5502 // by AM is legal for this target, for a load/store of the specified type.
5503 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5504 const Type *Ty) const {
5505 // FIXME: PPC does not allow r+i addressing modes for vectors!
5507 // PPC allows a sign-extended 16-bit immediate field.
5508 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
5511 // No global is ever allowed as a base.
5515 // PPC only support r+r,
5517 case 0: // "r+i" or just "i", depending on HasBaseReg.
5520 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
5522 // Otherwise we have r+r or r+i.
5525 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
5527 // Allow 2*r as r+r.
5530 // No other scales are supported.
5537 /// isLegalAddressImmediate - Return true if the integer value can be used
5538 /// as the offset of the target addressing mode for load / store of the
5540 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
5541 // PPC allows a sign-extended 16-bit immediate field.
5542 return (V > -(1 << 16) && V < (1 << 16)-1);
5545 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
5549 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
5550 SelectionDAG &DAG) const {
5551 MachineFunction &MF = DAG.getMachineFunction();
5552 MachineFrameInfo *MFI = MF.getFrameInfo();
5553 MFI->setReturnAddressIsTaken(true);
5555 DebugLoc dl = Op.getDebugLoc();
5556 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5558 // Make sure the function does not optimize away the store of the RA to
5560 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
5561 FuncInfo->setLRStoreRequired();
5562 bool isPPC64 = PPCSubTarget.isPPC64();
5563 bool isDarwinABI = PPCSubTarget.isDarwinABI();
5566 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5569 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
5570 isPPC64? MVT::i64 : MVT::i32);
5571 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
5572 DAG.getNode(ISD::ADD, dl, getPointerTy(),
5574 MachinePointerInfo(), false, false, 0);
5577 // Just load the return address off the stack.
5578 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
5579 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
5580 RetAddrFI, MachinePointerInfo(), false, false, 0);
5583 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
5584 SelectionDAG &DAG) const {
5585 DebugLoc dl = Op.getDebugLoc();
5586 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5588 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5589 bool isPPC64 = PtrVT == MVT::i64;
5591 MachineFunction &MF = DAG.getMachineFunction();
5592 MachineFrameInfo *MFI = MF.getFrameInfo();
5593 MFI->setFrameAddressIsTaken(true);
5594 bool is31 = (DisableFramePointerElim(MF) || MFI->hasVarSizedObjects()) &&
5595 MFI->getStackSize() &&
5596 !MF.getFunction()->hasFnAttr(Attribute::Naked);
5597 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) :
5598 (is31 ? PPC::R31 : PPC::R1);
5599 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
5602 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
5603 FrameAddr, MachinePointerInfo(), false, false, 0);
5608 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5609 // The PowerPC target isn't yet aware of offsets.
5613 /// getOptimalMemOpType - Returns the target specific optimal type for load
5614 /// and store operations as a result of memset, memcpy, and memmove
5615 /// lowering. If DstAlign is zero that means it's safe to destination
5616 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
5617 /// means there isn't a need to check it against alignment requirement,
5618 /// probably because the source does not need to be loaded. If
5619 /// 'NonScalarIntSafe' is true, that means it's safe to return a
5620 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
5621 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
5622 /// constant so it does not need to be loaded.
5623 /// It returns EVT::Other if the type should be determined using generic
5624 /// target-independent logic.
5625 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
5626 unsigned DstAlign, unsigned SrcAlign,
5627 bool NonScalarIntSafe,
5629 MachineFunction &MF) const {
5630 if (this->PPCSubTarget.isPPC64()) {