1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/Function.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/DerivedTypes.h"
38 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
39 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
42 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
43 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
47 // Use _setjmp/_longjmp instead of setjmp/longjmp.
48 setUseUnderscoreSetJmp(true);
49 setUseUnderscoreLongJmp(true);
51 // Set up the register classes.
52 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
53 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
54 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
56 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
57 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
58 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
60 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
62 // PowerPC has pre-inc load and store's.
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
64 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
65 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
66 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
67 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
69 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
70 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
71 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
72 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
74 // This is used in the ppcf128->int sequence. Note it has different semantics
75 // from FP_ROUND: that rounds to nearest, this rounds to zero.
76 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
78 // PowerPC has no SREM/UREM instructions
79 setOperationAction(ISD::SREM, MVT::i32, Expand);
80 setOperationAction(ISD::UREM, MVT::i32, Expand);
81 setOperationAction(ISD::SREM, MVT::i64, Expand);
82 setOperationAction(ISD::UREM, MVT::i64, Expand);
84 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
85 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
86 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
87 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
88 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
89 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
90 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
91 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
92 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
94 // We don't support sin/cos/sqrt/fmod/pow
95 setOperationAction(ISD::FSIN , MVT::f64, Expand);
96 setOperationAction(ISD::FCOS , MVT::f64, Expand);
97 setOperationAction(ISD::FREM , MVT::f64, Expand);
98 setOperationAction(ISD::FPOW , MVT::f64, Expand);
99 setOperationAction(ISD::FSIN , MVT::f32, Expand);
100 setOperationAction(ISD::FCOS , MVT::f32, Expand);
101 setOperationAction(ISD::FREM , MVT::f32, Expand);
102 setOperationAction(ISD::FPOW , MVT::f32, Expand);
104 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
106 // If we're enabling GP optimizations, use hardware square root
107 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
108 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
109 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
112 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
113 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
115 // PowerPC does not have BSWAP, CTPOP or CTTZ
116 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
117 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
118 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
119 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
120 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
121 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
123 // PowerPC does not have ROTR
124 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
125 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
127 // PowerPC does not have Select
128 setOperationAction(ISD::SELECT, MVT::i32, Expand);
129 setOperationAction(ISD::SELECT, MVT::i64, Expand);
130 setOperationAction(ISD::SELECT, MVT::f32, Expand);
131 setOperationAction(ISD::SELECT, MVT::f64, Expand);
133 // PowerPC wants to turn select_cc of FP into fsel when possible.
134 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
135 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
137 // PowerPC wants to optimize integer setcc a bit
138 setOperationAction(ISD::SETCC, MVT::i32, Custom);
140 // PowerPC does not have BRCOND which requires SetCC
141 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
143 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
145 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
146 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
148 // PowerPC does not have [U|S]INT_TO_FP
149 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
150 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
152 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
153 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
154 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
155 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
157 // We cannot sextinreg(i1). Expand to shifts.
158 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
160 // Support label based line numbers.
161 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
162 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
164 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
165 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
166 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
167 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
170 // We want to legalize GlobalAddress and ConstantPool nodes into the
171 // appropriate instructions to materialize the address.
172 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
173 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
174 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
175 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
176 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
177 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
178 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
179 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
181 // RET must be custom lowered, to meet ABI requirements.
182 setOperationAction(ISD::RET , MVT::Other, Custom);
185 setOperationAction(ISD::TRAP, MVT::Other, Legal);
187 // TRAMPOLINE is custom lowered.
188 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
190 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
191 setOperationAction(ISD::VASTART , MVT::Other, Custom);
193 // VAARG is custom lowered with ELF 32 ABI
194 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
195 setOperationAction(ISD::VAARG, MVT::Other, Custom);
197 setOperationAction(ISD::VAARG, MVT::Other, Expand);
199 // Use the default implementation.
200 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
201 setOperationAction(ISD::VAEND , MVT::Other, Expand);
202 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
203 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
204 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
205 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
207 // We want to custom lower some of our intrinsics.
208 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
210 // Comparisons that require checking two conditions.
211 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
212 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
213 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
214 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
215 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
216 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
217 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
218 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
219 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
220 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
221 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
222 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
224 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
225 // They also have instructions for converting between i64 and fp.
226 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
227 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
228 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
229 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
230 // This is just the low 32 bits of a (signed) fp->i64 conversion.
231 // We cannot do this with Promote because i64 is not a legal type.
232 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
234 // FIXME: disable this lowered code. This generates 64-bit register values,
235 // and we don't model the fact that the top part is clobbered by calls. We
236 // need to flag these together so that the value isn't live across a call.
237 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
239 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
240 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
243 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
244 // 64-bit PowerPC implementations can support i64 types directly
245 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
246 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
247 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
248 // 64-bit PowerPC wants to expand i128 shifts itself.
249 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
250 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
251 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
253 // 32-bit PowerPC wants to expand i64 shifts itself.
254 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
255 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
256 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
259 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
260 // First set operation action for all vector types to expand. Then we
261 // will selectively turn on ones that can be effectively codegen'd.
262 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
263 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
264 MVT VT = (MVT::SimpleValueType)i;
266 // add/sub are legal for all supported vector VT's.
267 setOperationAction(ISD::ADD , VT, Legal);
268 setOperationAction(ISD::SUB , VT, Legal);
270 // We promote all shuffles to v16i8.
271 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
272 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
274 // We promote all non-typed operations to v4i32.
275 setOperationAction(ISD::AND , VT, Promote);
276 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
277 setOperationAction(ISD::OR , VT, Promote);
278 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
279 setOperationAction(ISD::XOR , VT, Promote);
280 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
281 setOperationAction(ISD::LOAD , VT, Promote);
282 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
283 setOperationAction(ISD::SELECT, VT, Promote);
284 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
285 setOperationAction(ISD::STORE, VT, Promote);
286 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
288 // No other operations are legal.
289 setOperationAction(ISD::MUL , VT, Expand);
290 setOperationAction(ISD::SDIV, VT, Expand);
291 setOperationAction(ISD::SREM, VT, Expand);
292 setOperationAction(ISD::UDIV, VT, Expand);
293 setOperationAction(ISD::UREM, VT, Expand);
294 setOperationAction(ISD::FDIV, VT, Expand);
295 setOperationAction(ISD::FNEG, VT, Expand);
296 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
297 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
298 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
299 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
300 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
301 setOperationAction(ISD::UDIVREM, VT, Expand);
302 setOperationAction(ISD::SDIVREM, VT, Expand);
303 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
304 setOperationAction(ISD::FPOW, VT, Expand);
305 setOperationAction(ISD::CTPOP, VT, Expand);
306 setOperationAction(ISD::CTLZ, VT, Expand);
307 setOperationAction(ISD::CTTZ, VT, Expand);
310 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
311 // with merges, splats, etc.
312 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
314 setOperationAction(ISD::AND , MVT::v4i32, Legal);
315 setOperationAction(ISD::OR , MVT::v4i32, Legal);
316 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
317 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
318 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
319 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
321 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
322 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
323 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
324 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
326 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
327 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
328 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
329 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
331 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
332 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
334 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
335 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
336 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
337 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
340 setShiftAmountType(MVT::i32);
341 setBooleanContents(ZeroOrOneBooleanContent);
343 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
344 setStackPointerRegisterToSaveRestore(PPC::X1);
345 setExceptionPointerRegister(PPC::X3);
346 setExceptionSelectorRegister(PPC::X4);
348 setStackPointerRegisterToSaveRestore(PPC::R1);
349 setExceptionPointerRegister(PPC::R3);
350 setExceptionSelectorRegister(PPC::R4);
353 // We have target-specific dag combine patterns for the following nodes:
354 setTargetDAGCombine(ISD::SINT_TO_FP);
355 setTargetDAGCombine(ISD::STORE);
356 setTargetDAGCombine(ISD::BR_CC);
357 setTargetDAGCombine(ISD::BSWAP);
359 // Darwin long double math library functions have $LDBL128 appended.
360 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
361 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
362 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
363 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
364 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
365 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
366 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
367 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
368 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
369 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
370 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
373 computeRegisterProperties();
376 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
377 /// function arguments in the caller parameter area.
378 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
379 TargetMachine &TM = getTargetMachine();
380 // Darwin passes everything on 4 byte boundary.
381 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
387 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
390 case PPCISD::FSEL: return "PPCISD::FSEL";
391 case PPCISD::FCFID: return "PPCISD::FCFID";
392 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
393 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
394 case PPCISD::STFIWX: return "PPCISD::STFIWX";
395 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
396 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
397 case PPCISD::VPERM: return "PPCISD::VPERM";
398 case PPCISD::Hi: return "PPCISD::Hi";
399 case PPCISD::Lo: return "PPCISD::Lo";
400 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
401 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
402 case PPCISD::SRL: return "PPCISD::SRL";
403 case PPCISD::SRA: return "PPCISD::SRA";
404 case PPCISD::SHL: return "PPCISD::SHL";
405 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
406 case PPCISD::STD_32: return "PPCISD::STD_32";
407 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
408 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
409 case PPCISD::MTCTR: return "PPCISD::MTCTR";
410 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
411 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
412 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
413 case PPCISD::MFCR: return "PPCISD::MFCR";
414 case PPCISD::VCMP: return "PPCISD::VCMP";
415 case PPCISD::VCMPo: return "PPCISD::VCMPo";
416 case PPCISD::LBRX: return "PPCISD::LBRX";
417 case PPCISD::STBRX: return "PPCISD::STBRX";
418 case PPCISD::LARX: return "PPCISD::LARX";
419 case PPCISD::STCX: return "PPCISD::STCX";
420 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
421 case PPCISD::MFFS: return "PPCISD::MFFS";
422 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
423 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
424 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
425 case PPCISD::MTFSF: return "PPCISD::MTFSF";
426 case PPCISD::TAILCALL: return "PPCISD::TAILCALL";
427 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
431 MVT PPCTargetLowering::getSetCCResultType(MVT VT) const {
435 /// getFunctionAlignment - Return the Log2 alignment of this function.
436 unsigned PPCTargetLowering::getFunctionAlignment(const Function *F) const {
437 if (getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin())
438 return F->hasFnAttr(Attribute::OptimizeForSize) ? 2 : 4;
443 //===----------------------------------------------------------------------===//
444 // Node matching predicates, for use by the tblgen matching code.
445 //===----------------------------------------------------------------------===//
447 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
448 static bool isFloatingPointZero(SDValue Op) {
449 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
450 return CFP->getValueAPF().isZero();
451 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
452 // Maybe this has already been legalized into the constant pool?
453 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
454 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
455 return CFP->getValueAPF().isZero();
460 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
461 /// true if Op is undef or if it matches the specified value.
462 static bool isConstantOrUndef(int Op, int Val) {
463 return Op < 0 || Op == Val;
466 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
467 /// VPKUHUM instruction.
468 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
470 for (unsigned i = 0; i != 16; ++i)
471 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
474 for (unsigned i = 0; i != 8; ++i)
475 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
476 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
482 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
483 /// VPKUWUM instruction.
484 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
486 for (unsigned i = 0; i != 16; i += 2)
487 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
488 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
491 for (unsigned i = 0; i != 8; i += 2)
492 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
493 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
494 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
495 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
501 /// isVMerge - Common function, used to match vmrg* shuffles.
503 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
504 unsigned LHSStart, unsigned RHSStart) {
505 assert(N->getValueType(0) == MVT::v16i8 &&
506 "PPC only supports shuffles by bytes!");
507 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
508 "Unsupported merge size!");
510 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
511 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
512 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
513 LHSStart+j+i*UnitSize) ||
514 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
515 RHSStart+j+i*UnitSize))
521 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
522 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
523 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
526 return isVMerge(N, UnitSize, 8, 24);
527 return isVMerge(N, UnitSize, 8, 8);
530 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
531 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
532 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
535 return isVMerge(N, UnitSize, 0, 16);
536 return isVMerge(N, UnitSize, 0, 0);
540 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
541 /// amount, otherwise return -1.
542 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
543 assert(N->getValueType(0) == MVT::v16i8 &&
544 "PPC only supports shuffles by bytes!");
546 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
548 // Find the first non-undef value in the shuffle mask.
550 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
553 if (i == 16) return -1; // all undef.
555 // Otherwise, check to see if the rest of the elements are consecutively
556 // numbered from this value.
557 unsigned ShiftAmt = SVOp->getMaskElt(i);
558 if (ShiftAmt < i) return -1;
562 // Check the rest of the elements to see if they are consecutive.
563 for (++i; i != 16; ++i)
564 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
567 // Check the rest of the elements to see if they are consecutive.
568 for (++i; i != 16; ++i)
569 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
575 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
576 /// specifies a splat of a single element that is suitable for input to
577 /// VSPLTB/VSPLTH/VSPLTW.
578 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
579 assert(N->getValueType(0) == MVT::v16i8 &&
580 (EltSize == 1 || EltSize == 2 || EltSize == 4));
582 // This is a splat operation if each element of the permute is the same, and
583 // if the value doesn't reference the second vector.
584 unsigned ElementBase = N->getMaskElt(0);
586 // FIXME: Handle UNDEF elements too!
587 if (ElementBase >= 16)
590 // Check that the indices are consecutive, in the case of a multi-byte element
591 // splatted with a v16i8 mask.
592 for (unsigned i = 1; i != EltSize; ++i)
593 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
596 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
597 if (N->getMaskElt(i) < 0) continue;
598 for (unsigned j = 0; j != EltSize; ++j)
599 if (N->getMaskElt(i+j) != N->getMaskElt(j))
605 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
607 bool PPC::isAllNegativeZeroVector(SDNode *N) {
608 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
610 APInt APVal, APUndef;
614 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32))
615 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
616 return CFP->getValueAPF().isNegZero();
621 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
622 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
623 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
624 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
625 assert(isSplatShuffleMask(SVOp, EltSize));
626 return SVOp->getMaskElt(0) / EltSize;
629 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
630 /// by using a vspltis[bhw] instruction of the specified element size, return
631 /// the constant being splatted. The ByteSize field indicates the number of
632 /// bytes of each element [124] -> [bhw].
633 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
636 // If ByteSize of the splat is bigger than the element size of the
637 // build_vector, then we have a case where we are checking for a splat where
638 // multiple elements of the buildvector are folded together into a single
639 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
640 unsigned EltSize = 16/N->getNumOperands();
641 if (EltSize < ByteSize) {
642 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
643 SDValue UniquedVals[4];
644 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
646 // See if all of the elements in the buildvector agree across.
647 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
648 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
649 // If the element isn't a constant, bail fully out.
650 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
653 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
654 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
655 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
656 return SDValue(); // no match.
659 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
660 // either constant or undef values that are identical for each chunk. See
661 // if these chunks can form into a larger vspltis*.
663 // Check to see if all of the leading entries are either 0 or -1. If
664 // neither, then this won't fit into the immediate field.
665 bool LeadingZero = true;
666 bool LeadingOnes = true;
667 for (unsigned i = 0; i != Multiple-1; ++i) {
668 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
670 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
671 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
673 // Finally, check the least significant entry.
675 if (UniquedVals[Multiple-1].getNode() == 0)
676 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
677 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
679 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
682 if (UniquedVals[Multiple-1].getNode() == 0)
683 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
684 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
685 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
686 return DAG.getTargetConstant(Val, MVT::i32);
692 // Check to see if this buildvec has a single non-undef value in its elements.
693 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
694 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
695 if (OpVal.getNode() == 0)
696 OpVal = N->getOperand(i);
697 else if (OpVal != N->getOperand(i))
701 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
703 unsigned ValSizeInBytes = EltSize;
705 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
706 Value = CN->getZExtValue();
707 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
708 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
709 Value = FloatToBits(CN->getValueAPF().convertToFloat());
712 // If the splat value is larger than the element value, then we can never do
713 // this splat. The only case that we could fit the replicated bits into our
714 // immediate field for would be zero, and we prefer to use vxor for it.
715 if (ValSizeInBytes < ByteSize) return SDValue();
717 // If the element value is larger than the splat value, cut it in half and
718 // check to see if the two halves are equal. Continue doing this until we
719 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
720 while (ValSizeInBytes > ByteSize) {
721 ValSizeInBytes >>= 1;
723 // If the top half equals the bottom half, we're still ok.
724 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
725 (Value & ((1 << (8*ValSizeInBytes))-1)))
729 // Properly sign extend the value.
730 int ShAmt = (4-ByteSize)*8;
731 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
733 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
734 if (MaskVal == 0) return SDValue();
736 // Finally, if this value fits in a 5 bit sext field, return it
737 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
738 return DAG.getTargetConstant(MaskVal, MVT::i32);
742 //===----------------------------------------------------------------------===//
743 // Addressing Mode Selection
744 //===----------------------------------------------------------------------===//
746 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
747 /// or 64-bit immediate, and if the value can be accurately represented as a
748 /// sign extension from a 16-bit value. If so, this returns true and the
750 static bool isIntS16Immediate(SDNode *N, short &Imm) {
751 if (N->getOpcode() != ISD::Constant)
754 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
755 if (N->getValueType(0) == MVT::i32)
756 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
758 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
760 static bool isIntS16Immediate(SDValue Op, short &Imm) {
761 return isIntS16Immediate(Op.getNode(), Imm);
765 /// SelectAddressRegReg - Given the specified addressed, check to see if it
766 /// can be represented as an indexed [r+r] operation. Returns false if it
767 /// can be more efficiently represented with [r+imm].
768 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
770 SelectionDAG &DAG) const {
772 if (N.getOpcode() == ISD::ADD) {
773 if (isIntS16Immediate(N.getOperand(1), imm))
775 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
778 Base = N.getOperand(0);
779 Index = N.getOperand(1);
781 } else if (N.getOpcode() == ISD::OR) {
782 if (isIntS16Immediate(N.getOperand(1), imm))
783 return false; // r+i can fold it if we can.
785 // If this is an or of disjoint bitfields, we can codegen this as an add
786 // (for better address arithmetic) if the LHS and RHS of the OR are provably
788 APInt LHSKnownZero, LHSKnownOne;
789 APInt RHSKnownZero, RHSKnownOne;
790 DAG.ComputeMaskedBits(N.getOperand(0),
791 APInt::getAllOnesValue(N.getOperand(0)
792 .getValueSizeInBits()),
793 LHSKnownZero, LHSKnownOne);
795 if (LHSKnownZero.getBoolValue()) {
796 DAG.ComputeMaskedBits(N.getOperand(1),
797 APInt::getAllOnesValue(N.getOperand(1)
798 .getValueSizeInBits()),
799 RHSKnownZero, RHSKnownOne);
800 // If all of the bits are known zero on the LHS or RHS, the add won't
802 if (~(LHSKnownZero | RHSKnownZero) == 0) {
803 Base = N.getOperand(0);
804 Index = N.getOperand(1);
813 /// Returns true if the address N can be represented by a base register plus
814 /// a signed 16-bit displacement [r+imm], and if it is not better
815 /// represented as reg+reg.
816 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
818 SelectionDAG &DAG) const {
819 // FIXME dl should come from parent load or store, not from address
820 DebugLoc dl = N.getDebugLoc();
821 // If this can be more profitably realized as r+r, fail.
822 if (SelectAddressRegReg(N, Disp, Base, DAG))
825 if (N.getOpcode() == ISD::ADD) {
827 if (isIntS16Immediate(N.getOperand(1), imm)) {
828 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
829 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
830 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
832 Base = N.getOperand(0);
834 return true; // [r+i]
835 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
836 // Match LOAD (ADD (X, Lo(G))).
837 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
838 && "Cannot handle constant offsets yet!");
839 Disp = N.getOperand(1).getOperand(0); // The global address.
840 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
841 Disp.getOpcode() == ISD::TargetConstantPool ||
842 Disp.getOpcode() == ISD::TargetJumpTable);
843 Base = N.getOperand(0);
844 return true; // [&g+r]
846 } else if (N.getOpcode() == ISD::OR) {
848 if (isIntS16Immediate(N.getOperand(1), imm)) {
849 // If this is an or of disjoint bitfields, we can codegen this as an add
850 // (for better address arithmetic) if the LHS and RHS of the OR are
851 // provably disjoint.
852 APInt LHSKnownZero, LHSKnownOne;
853 DAG.ComputeMaskedBits(N.getOperand(0),
854 APInt::getAllOnesValue(N.getOperand(0)
855 .getValueSizeInBits()),
856 LHSKnownZero, LHSKnownOne);
858 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
859 // If all of the bits are known zero on the LHS or RHS, the add won't
861 Base = N.getOperand(0);
862 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
866 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
867 // Loading from a constant address.
869 // If this address fits entirely in a 16-bit sext immediate field, codegen
872 if (isIntS16Immediate(CN, Imm)) {
873 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
874 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
878 // Handle 32-bit sext immediates with LIS + addr mode.
879 if (CN->getValueType(0) == MVT::i32 ||
880 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
881 int Addr = (int)CN->getZExtValue();
883 // Otherwise, break this down into an LIS + disp.
884 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
886 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
887 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
888 Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base), 0);
893 Disp = DAG.getTargetConstant(0, getPointerTy());
894 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
895 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
898 return true; // [r+0]
901 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
902 /// represented as an indexed [r+r] operation.
903 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
905 SelectionDAG &DAG) const {
906 // Check to see if we can easily represent this as an [r+r] address. This
907 // will fail if it thinks that the address is more profitably represented as
908 // reg+imm, e.g. where imm = 0.
909 if (SelectAddressRegReg(N, Base, Index, DAG))
912 // If the operand is an addition, always emit this as [r+r], since this is
913 // better (for code size, and execution, as the memop does the add for free)
914 // than emitting an explicit add.
915 if (N.getOpcode() == ISD::ADD) {
916 Base = N.getOperand(0);
917 Index = N.getOperand(1);
921 // Otherwise, do it the hard way, using R0 as the base register.
922 Base = DAG.getRegister(PPC::R0, N.getValueType());
927 /// SelectAddressRegImmShift - Returns true if the address N can be
928 /// represented by a base register plus a signed 14-bit displacement
929 /// [r+imm*4]. Suitable for use by STD and friends.
930 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
932 SelectionDAG &DAG) const {
933 // FIXME dl should come from the parent load or store, not the address
934 DebugLoc dl = N.getDebugLoc();
935 // If this can be more profitably realized as r+r, fail.
936 if (SelectAddressRegReg(N, Disp, Base, DAG))
939 if (N.getOpcode() == ISD::ADD) {
941 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
942 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
943 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
944 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
946 Base = N.getOperand(0);
948 return true; // [r+i]
949 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
950 // Match LOAD (ADD (X, Lo(G))).
951 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
952 && "Cannot handle constant offsets yet!");
953 Disp = N.getOperand(1).getOperand(0); // The global address.
954 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
955 Disp.getOpcode() == ISD::TargetConstantPool ||
956 Disp.getOpcode() == ISD::TargetJumpTable);
957 Base = N.getOperand(0);
958 return true; // [&g+r]
960 } else if (N.getOpcode() == ISD::OR) {
962 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
963 // If this is an or of disjoint bitfields, we can codegen this as an add
964 // (for better address arithmetic) if the LHS and RHS of the OR are
965 // provably disjoint.
966 APInt LHSKnownZero, LHSKnownOne;
967 DAG.ComputeMaskedBits(N.getOperand(0),
968 APInt::getAllOnesValue(N.getOperand(0)
969 .getValueSizeInBits()),
970 LHSKnownZero, LHSKnownOne);
971 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
972 // If all of the bits are known zero on the LHS or RHS, the add won't
974 Base = N.getOperand(0);
975 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
979 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
980 // Loading from a constant address. Verify low two bits are clear.
981 if ((CN->getZExtValue() & 3) == 0) {
982 // If this address fits entirely in a 14-bit sext immediate field, codegen
985 if (isIntS16Immediate(CN, Imm)) {
986 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
987 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
991 // Fold the low-part of 32-bit absolute addresses into addr mode.
992 if (CN->getValueType(0) == MVT::i32 ||
993 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
994 int Addr = (int)CN->getZExtValue();
996 // Otherwise, break this down into an LIS + disp.
997 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
998 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
999 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1000 Base = SDValue(DAG.getTargetNode(Opc, dl, CN->getValueType(0), Base),0);
1006 Disp = DAG.getTargetConstant(0, getPointerTy());
1007 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1008 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1011 return true; // [r+0]
1015 /// getPreIndexedAddressParts - returns true by value, base pointer and
1016 /// offset pointer and addressing mode by reference if the node's address
1017 /// can be legally represented as pre-indexed load / store address.
1018 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1020 ISD::MemIndexedMode &AM,
1021 SelectionDAG &DAG) const {
1022 // Disabled by default for now.
1023 if (!EnablePPCPreinc) return false;
1027 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1028 Ptr = LD->getBasePtr();
1029 VT = LD->getMemoryVT();
1031 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1033 Ptr = ST->getBasePtr();
1034 VT = ST->getMemoryVT();
1038 // PowerPC doesn't have preinc load/store instructions for vectors.
1042 // TODO: Check reg+reg first.
1044 // LDU/STU use reg+imm*4, others use reg+imm.
1045 if (VT != MVT::i64) {
1047 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1051 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1055 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1056 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1057 // sext i32 to i64 when addr mode is r+i.
1058 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1059 LD->getExtensionType() == ISD::SEXTLOAD &&
1060 isa<ConstantSDNode>(Offset))
1068 //===----------------------------------------------------------------------===//
1069 // LowerOperation implementation
1070 //===----------------------------------------------------------------------===//
1072 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1073 SelectionDAG &DAG) {
1074 MVT PtrVT = Op.getValueType();
1075 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1076 Constant *C = CP->getConstVal();
1077 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1078 SDValue Zero = DAG.getConstant(0, PtrVT);
1079 // FIXME there isn't really any debug info here
1080 DebugLoc dl = Op.getDebugLoc();
1082 const TargetMachine &TM = DAG.getTarget();
1084 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, CPI, Zero);
1085 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, CPI, Zero);
1087 // If this is a non-darwin platform, we don't support non-static relo models
1089 if (TM.getRelocationModel() == Reloc::Static ||
1090 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1091 // Generate non-pic code that has direct accesses to the constant pool.
1092 // The address of the global is just (hi(&g)+lo(&g)).
1093 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1096 if (TM.getRelocationModel() == Reloc::PIC_) {
1097 // With PIC, the first instruction is actually "GR+hi(&G)".
1098 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1099 DAG.getNode(PPCISD::GlobalBaseReg,
1100 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1103 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1107 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
1108 MVT PtrVT = Op.getValueType();
1109 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1110 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1111 SDValue Zero = DAG.getConstant(0, PtrVT);
1112 // FIXME there isn't really any debug loc here
1113 DebugLoc dl = Op.getDebugLoc();
1115 const TargetMachine &TM = DAG.getTarget();
1117 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, JTI, Zero);
1118 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, JTI, Zero);
1120 // If this is a non-darwin platform, we don't support non-static relo models
1122 if (TM.getRelocationModel() == Reloc::Static ||
1123 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1124 // Generate non-pic code that has direct accesses to the constant pool.
1125 // The address of the global is just (hi(&g)+lo(&g)).
1126 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1129 if (TM.getRelocationModel() == Reloc::PIC_) {
1130 // With PIC, the first instruction is actually "GR+hi(&G)".
1131 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1132 DAG.getNode(PPCISD::GlobalBaseReg,
1133 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1136 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1140 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1141 SelectionDAG &DAG) {
1142 assert(0 && "TLS not implemented for PPC.");
1143 return SDValue(); // Not reached
1146 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1147 SelectionDAG &DAG) {
1148 MVT PtrVT = Op.getValueType();
1149 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1150 GlobalValue *GV = GSDN->getGlobal();
1151 SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1152 SDValue Zero = DAG.getConstant(0, PtrVT);
1153 // FIXME there isn't really any debug info here
1154 DebugLoc dl = GSDN->getDebugLoc();
1156 const TargetMachine &TM = DAG.getTarget();
1158 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero);
1159 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero);
1161 // If this is a non-darwin platform, we don't support non-static relo models
1163 if (TM.getRelocationModel() == Reloc::Static ||
1164 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1165 // Generate non-pic code that has direct accesses to globals.
1166 // The address of the global is just (hi(&g)+lo(&g)).
1167 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1170 if (TM.getRelocationModel() == Reloc::PIC_) {
1171 // With PIC, the first instruction is actually "GR+hi(&G)".
1172 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1173 DAG.getNode(PPCISD::GlobalBaseReg,
1174 DebugLoc::getUnknownLoc(), PtrVT), Hi);
1177 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1179 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1182 // If the global is weak or external, we have to go through the lazy
1184 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0);
1187 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
1188 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1189 DebugLoc dl = Op.getDebugLoc();
1191 // If we're comparing for equality to zero, expose the fact that this is
1192 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1193 // fold the new nodes.
1194 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1195 if (C->isNullValue() && CC == ISD::SETEQ) {
1196 MVT VT = Op.getOperand(0).getValueType();
1197 SDValue Zext = Op.getOperand(0);
1198 if (VT.bitsLT(MVT::i32)) {
1200 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1202 unsigned Log2b = Log2_32(VT.getSizeInBits());
1203 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1204 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1205 DAG.getConstant(Log2b, MVT::i32));
1206 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1208 // Leave comparisons against 0 and -1 alone for now, since they're usually
1209 // optimized. FIXME: revisit this when we can custom lower all setcc
1211 if (C->isAllOnesValue() || C->isNullValue())
1215 // If we have an integer seteq/setne, turn it into a compare against zero
1216 // by xor'ing the rhs with the lhs, which is faster than setting a
1217 // condition register, reading it back out, and masking the correct bit. The
1218 // normal approach here uses sub to do this instead of xor. Using xor exposes
1219 // the result to other bit-twiddling opportunities.
1220 MVT LHSVT = Op.getOperand(0).getValueType();
1221 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1222 MVT VT = Op.getValueType();
1223 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1225 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1230 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1231 int VarArgsFrameIndex,
1232 int VarArgsStackOffset,
1233 unsigned VarArgsNumGPR,
1234 unsigned VarArgsNumFPR,
1235 const PPCSubtarget &Subtarget) {
1237 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1238 return SDValue(); // Not reached
1241 SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
1242 SDValue Chain = Op.getOperand(0);
1243 SDValue Trmp = Op.getOperand(1); // trampoline
1244 SDValue FPtr = Op.getOperand(2); // nested function
1245 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1246 DebugLoc dl = Op.getDebugLoc();
1248 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1249 bool isPPC64 = (PtrVT == MVT::i64);
1250 const Type *IntPtrTy =
1251 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType();
1253 TargetLowering::ArgListTy Args;
1254 TargetLowering::ArgListEntry Entry;
1256 Entry.Ty = IntPtrTy;
1257 Entry.Node = Trmp; Args.push_back(Entry);
1259 // TrampSize == (isPPC64 ? 48 : 40);
1260 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1261 isPPC64 ? MVT::i64 : MVT::i32);
1262 Args.push_back(Entry);
1264 Entry.Node = FPtr; Args.push_back(Entry);
1265 Entry.Node = Nest; Args.push_back(Entry);
1267 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1268 std::pair<SDValue, SDValue> CallResult =
1269 LowerCallTo(Chain, Op.getValueType().getTypeForMVT(), false, false,
1270 false, false, CallingConv::C, false,
1271 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1275 { CallResult.first, CallResult.second };
1277 return DAG.getMergeValues(Ops, 2, dl);
1280 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1281 int VarArgsFrameIndex,
1282 int VarArgsStackOffset,
1283 unsigned VarArgsNumGPR,
1284 unsigned VarArgsNumFPR,
1285 const PPCSubtarget &Subtarget) {
1286 DebugLoc dl = Op.getDebugLoc();
1288 if (Subtarget.isMachoABI()) {
1289 // vastart just stores the address of the VarArgsFrameIndex slot into the
1290 // memory location argument.
1291 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1292 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1293 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1294 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0);
1297 // For ELF 32 ABI we follow the layout of the va_list struct.
1298 // We suppose the given va_list is already allocated.
1301 // char gpr; /* index into the array of 8 GPRs
1302 // * stored in the register save area
1303 // * gpr=0 corresponds to r3,
1304 // * gpr=1 to r4, etc.
1306 // char fpr; /* index into the array of 8 FPRs
1307 // * stored in the register save area
1308 // * fpr=0 corresponds to f1,
1309 // * fpr=1 to f2, etc.
1311 // char *overflow_arg_area;
1312 // /* location on stack that holds
1313 // * the next overflow argument
1315 // char *reg_save_area;
1316 // /* where r3:r10 and f1:f8 (if saved)
1322 SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1323 SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1326 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1328 SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1329 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1331 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1332 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1334 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1335 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1337 uint64_t FPROffset = 1;
1338 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1340 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1342 // Store first byte : number of int regs
1343 SDValue firstStore = DAG.getStore(Op.getOperand(0), dl, ArgGPR,
1344 Op.getOperand(1), SV, 0);
1345 uint64_t nextOffset = FPROffset;
1346 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1349 // Store second byte : number of float regs
1350 SDValue secondStore =
1351 DAG.getStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset);
1352 nextOffset += StackOffset;
1353 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1355 // Store second word : arguments given on stack
1356 SDValue thirdStore =
1357 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset);
1358 nextOffset += FrameOffset;
1359 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1361 // Store third word : arguments given in registers
1362 return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset);
1366 #include "PPCGenCallingConv.inc"
1368 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1369 /// depending on which subtarget is selected.
1370 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1371 if (Subtarget.isMachoABI()) {
1372 static const unsigned FPR[] = {
1373 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1374 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1380 static const unsigned FPR[] = {
1381 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1387 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1389 static unsigned CalculateStackSlotSize(SDValue Arg, ISD::ArgFlagsTy Flags,
1390 unsigned PtrByteSize) {
1391 MVT ArgVT = Arg.getValueType();
1392 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1393 if (Flags.isByVal())
1394 ArgSize = Flags.getByValSize();
1395 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1401 PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
1403 int &VarArgsFrameIndex,
1404 int &VarArgsStackOffset,
1405 unsigned &VarArgsNumGPR,
1406 unsigned &VarArgsNumFPR,
1407 const PPCSubtarget &Subtarget) {
1408 // TODO: add description of PPC stack frame format, or at least some docs.
1410 MachineFunction &MF = DAG.getMachineFunction();
1411 MachineFrameInfo *MFI = MF.getFrameInfo();
1412 SmallVector<SDValue, 8> ArgValues;
1413 SDValue Root = Op.getOperand(0);
1414 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1415 DebugLoc dl = Op.getDebugLoc();
1417 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1418 bool isPPC64 = PtrVT == MVT::i64;
1419 bool isMachoABI = Subtarget.isMachoABI();
1420 bool isELF32_ABI = Subtarget.isELF32_ABI();
1421 // Potential tail calls could cause overwriting of argument stack slots.
1422 unsigned CC = MF.getFunction()->getCallingConv();
1423 bool isImmutable = !(PerformTailCallOpt && (CC==CallingConv::Fast));
1424 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1426 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1427 // Area that is at least reserved in caller of this function.
1428 unsigned MinReservedArea = ArgOffset;
1430 static const unsigned GPR_32[] = { // 32-bit registers.
1431 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1432 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1434 static const unsigned GPR_64[] = { // 64-bit registers.
1435 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1436 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1439 static const unsigned *FPR = GetFPR(Subtarget);
1441 static const unsigned VR[] = {
1442 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1443 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1446 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1447 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
1448 const unsigned Num_VR_Regs = array_lengthof( VR);
1450 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1452 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1454 // In 32-bit non-varargs functions, the stack space for vectors is after the
1455 // stack space for non-vectors. We do not use this space unless we have
1456 // too many vectors to fit in registers, something that only occurs in
1457 // constructed examples:), but we have to walk the arglist to figure
1458 // that out...for the pathological case, compute VecArgOffset as the
1459 // start of the vector parameter area. Computing VecArgOffset is the
1460 // entire point of the following loop.
1461 // Altivec is not mentioned in the ppc32 Elf Supplement, so I'm not trying
1462 // to handle Elf here.
1463 unsigned VecArgOffset = ArgOffset;
1464 if (!isVarArg && !isPPC64) {
1465 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e;
1467 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
1468 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1469 ISD::ArgFlagsTy Flags =
1470 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
1472 if (Flags.isByVal()) {
1473 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1474 ObjSize = Flags.getByValSize();
1476 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1477 VecArgOffset += ArgSize;
1481 switch(ObjectVT.getSimpleVT()) {
1482 default: assert(0 && "Unhandled argument type!");
1485 VecArgOffset += isPPC64 ? 8 : 4;
1487 case MVT::i64: // PPC64
1495 // Nothing to do, we're only looking at Nonvector args here.
1500 // We've found where the vector parameter area in memory is. Skip the
1501 // first 12 parameters; these don't use that memory.
1502 VecArgOffset = ((VecArgOffset+15)/16)*16;
1503 VecArgOffset += 12*16;
1505 // Add DAG nodes to load the arguments or copy them out of registers. On
1506 // entry to a function on PPC, the arguments start after the linkage area,
1507 // although the first ones are often in registers.
1509 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
1510 // represented with two words (long long or double) must be copied to an
1511 // even GPR_idx value or to an even ArgOffset value.
1513 SmallVector<SDValue, 8> MemOps;
1514 unsigned nAltivecParamsAtEnd = 0;
1515 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues() - 1;
1516 ArgNo != e; ++ArgNo) {
1518 bool needsLoad = false;
1519 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
1520 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1521 unsigned ArgSize = ObjSize;
1522 ISD::ArgFlagsTy Flags =
1523 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
1524 // See if next argument requires stack alignment in ELF
1525 bool Align = Flags.isSplit();
1527 unsigned CurArgOffset = ArgOffset;
1529 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1530 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1531 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1532 if (isVarArg || isPPC64) {
1533 MinReservedArea = ((MinReservedArea+15)/16)*16;
1534 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
1537 } else nAltivecParamsAtEnd++;
1539 // Calculate min reserved area.
1540 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
1544 // FIXME alignment for ELF may not be right
1545 // FIXME the codegen can be much improved in some cases.
1546 // We do not have to keep everything in memory.
1547 if (Flags.isByVal()) {
1548 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1549 ObjSize = Flags.getByValSize();
1550 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1551 // Double word align in ELF
1552 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1553 // Objects of size 1 and 2 are right justified, everything else is
1554 // left justified. This means the memory address is adjusted forwards.
1555 if (ObjSize==1 || ObjSize==2) {
1556 CurArgOffset = CurArgOffset + (4 - ObjSize);
1558 // The value of the object is its address.
1559 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
1560 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1561 ArgValues.push_back(FIN);
1562 if (ObjSize==1 || ObjSize==2) {
1563 if (GPR_idx != Num_GPR_Regs) {
1564 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1565 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
1566 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
1567 NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
1568 MemOps.push_back(Store);
1570 if (isMachoABI) ArgOffset += PtrByteSize;
1572 ArgOffset += PtrByteSize;
1576 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1577 // Store whatever pieces of the object are in registers
1578 // to memory. ArgVal will be address of the beginning of
1580 if (GPR_idx != Num_GPR_Regs) {
1581 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1582 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset);
1583 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1584 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
1585 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1586 MemOps.push_back(Store);
1588 if (isMachoABI) ArgOffset += PtrByteSize;
1590 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1597 switch (ObjectVT.getSimpleVT()) {
1598 default: assert(0 && "Unhandled argument type!");
1601 // Double word align in ELF
1602 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1604 if (GPR_idx != Num_GPR_Regs) {
1605 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1606 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i32);
1610 ArgSize = PtrByteSize;
1612 // Stack align in ELF
1613 if (needsLoad && Align && isELF32_ABI)
1614 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1615 // All int arguments reserve stack space in Macho ABI.
1616 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1620 case MVT::i64: // PPC64
1621 if (GPR_idx != Num_GPR_Regs) {
1622 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
1623 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, MVT::i64);
1625 if (ObjectVT == MVT::i32) {
1626 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1627 // value to MVT::i64 and then truncate to the correct register size.
1629 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
1630 DAG.getValueType(ObjectVT));
1631 else if (Flags.isZExt())
1632 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
1633 DAG.getValueType(ObjectVT));
1635 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
1641 ArgSize = PtrByteSize;
1643 // All int arguments reserve stack space in Macho ABI.
1644 if (isMachoABI || needsLoad) ArgOffset += 8;
1649 // Every 4 bytes of argument space consumes one of the GPRs available for
1650 // argument passing.
1651 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
1653 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1656 if (FPR_idx != Num_FPR_Regs) {
1659 if (ObjectVT == MVT::f32)
1660 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
1662 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
1664 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT);
1670 // Stack align in ELF
1671 if (needsLoad && Align && isELF32_ABI)
1672 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1673 // All FP arguments reserve stack space in Macho ABI.
1674 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
1680 // Note that vector arguments in registers don't reserve stack space,
1681 // except in varargs functions.
1682 if (VR_idx != Num_VR_Regs) {
1683 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
1684 ArgVal = DAG.getCopyFromReg(Root, dl, VReg, ObjectVT);
1686 while ((ArgOffset % 16) != 0) {
1687 ArgOffset += PtrByteSize;
1688 if (GPR_idx != Num_GPR_Regs)
1692 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs);
1696 if (!isVarArg && !isPPC64) {
1697 // Vectors go after all the nonvectors.
1698 CurArgOffset = VecArgOffset;
1701 // Vectors are aligned.
1702 ArgOffset = ((ArgOffset+15)/16)*16;
1703 CurArgOffset = ArgOffset;
1711 // We need to load the argument to a virtual register if we determined above
1712 // that we ran out of physical registers of the appropriate type.
1714 int FI = MFI->CreateFixedObject(ObjSize,
1715 CurArgOffset + (ArgSize - ObjSize),
1717 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1718 ArgVal = DAG.getLoad(ObjectVT, dl, Root, FIN, NULL, 0);
1721 ArgValues.push_back(ArgVal);
1724 // Set the size that is at least reserved in caller of this function. Tail
1725 // call optimized function's reserved stack space needs to be aligned so that
1726 // taking the difference between two stack areas will result in an aligned
1728 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1729 // Add the Altivec parameters at the end, if needed.
1730 if (nAltivecParamsAtEnd) {
1731 MinReservedArea = ((MinReservedArea+15)/16)*16;
1732 MinReservedArea += 16*nAltivecParamsAtEnd;
1735 std::max(MinReservedArea,
1736 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1737 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1738 getStackAlignment();
1739 unsigned AlignMask = TargetAlign-1;
1740 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1741 FI->setMinReservedArea(MinReservedArea);
1743 // If the function takes variable number of arguments, make a frame index for
1744 // the start of the first vararg value... for expansion of llvm.va_start.
1749 VarArgsNumGPR = GPR_idx;
1750 VarArgsNumFPR = FPR_idx;
1752 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1754 depth = -(Num_GPR_Regs * PtrVT.getSizeInBits()/8 +
1755 Num_FPR_Regs * MVT(MVT::f64).getSizeInBits()/8 +
1756 PtrVT.getSizeInBits()/8);
1758 VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1765 VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1767 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1769 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1770 // stored to the VarArgsFrameIndex on the stack.
1772 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1773 SDValue Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1774 SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0);
1775 MemOps.push_back(Store);
1776 // Increment the address by four for the next argument to store
1777 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1778 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1782 // If this function is vararg, store any remaining integer argument regs
1783 // to their spots on the stack so that they may be loaded by deferencing the
1784 // result of va_next.
1785 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1789 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
1791 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1793 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, PtrVT);
1794 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1795 MemOps.push_back(Store);
1796 // Increment the address by four for the next argument to store
1797 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1798 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1801 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1804 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1805 SDValue Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1806 SDValue Store = DAG.getStore(Root, dl, Val, FIN, NULL, 0);
1807 MemOps.push_back(Store);
1808 // Increment the address by eight for the next argument to store
1809 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
1811 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1814 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1815 unsigned VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
1817 SDValue Val = DAG.getCopyFromReg(Root, dl, VReg, MVT::f64);
1818 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0);
1819 MemOps.push_back(Store);
1820 // Increment the address by eight for the next argument to store
1821 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
1823 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1828 if (!MemOps.empty())
1829 Root = DAG.getNode(ISD::TokenFactor, dl,
1830 MVT::Other, &MemOps[0], MemOps.size());
1832 ArgValues.push_back(Root);
1834 // Return the new list of results.
1835 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
1836 &ArgValues[0], ArgValues.size());
1839 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
1842 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
1847 CallSDNode *TheCall,
1848 unsigned &nAltivecParamsAtEnd) {
1849 // Count how many bytes are to be pushed on the stack, including the linkage
1850 // area, and parameter passing area. We start with 24/48 bytes, which is
1851 // prereserved space for [SP][CR][LR][3 x unused].
1852 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1853 unsigned NumOps = TheCall->getNumArgs();
1854 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1856 // Add up all the space actually used.
1857 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
1858 // they all go in registers, but we must reserve stack space for them for
1859 // possible use by the caller. In varargs or 64-bit calls, parameters are
1860 // assigned stack space in order, with padding so Altivec parameters are
1862 nAltivecParamsAtEnd = 0;
1863 for (unsigned i = 0; i != NumOps; ++i) {
1864 SDValue Arg = TheCall->getArg(i);
1865 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1866 MVT ArgVT = Arg.getValueType();
1867 // Varargs Altivec parameters are padded to a 16 byte boundary.
1868 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
1869 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
1870 if (!isVarArg && !isPPC64) {
1871 // Non-varargs Altivec parameters go after all the non-Altivec
1872 // parameters; handle those later so we know how much padding we need.
1873 nAltivecParamsAtEnd++;
1876 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
1877 NumBytes = ((NumBytes+15)/16)*16;
1879 NumBytes += CalculateStackSlotSize(Arg, Flags, PtrByteSize);
1882 // Allow for Altivec parameters at the end, if needed.
1883 if (nAltivecParamsAtEnd) {
1884 NumBytes = ((NumBytes+15)/16)*16;
1885 NumBytes += 16*nAltivecParamsAtEnd;
1888 // The prolog code of the callee may store up to 8 GPR argument registers to
1889 // the stack, allowing va_start to index over them in memory if its varargs.
1890 // Because we cannot tell if this is needed on the caller side, we have to
1891 // conservatively assume that it is needed. As such, make sure we have at
1892 // least enough stack space for the caller to store the 8 GPRs.
1893 NumBytes = std::max(NumBytes,
1894 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1896 // Tail call needs the stack to be aligned.
1897 if (CC==CallingConv::Fast && PerformTailCallOpt) {
1898 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1899 getStackAlignment();
1900 unsigned AlignMask = TargetAlign-1;
1901 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
1907 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
1908 /// adjusted to accomodate the arguments for the tailcall.
1909 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool IsTailCall,
1910 unsigned ParamSize) {
1912 if (!IsTailCall) return 0;
1914 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
1915 unsigned CallerMinReservedArea = FI->getMinReservedArea();
1916 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
1917 // Remember only if the new adjustement is bigger.
1918 if (SPDiff < FI->getTailCallSPDelta())
1919 FI->setTailCallSPDelta(SPDiff);
1924 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1925 /// following the call is a return. A function is eligible if caller/callee
1926 /// calling conventions match, currently only fastcc supports tail calls, and
1927 /// the function CALL is immediatly followed by a RET.
1929 PPCTargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
1931 SelectionDAG& DAG) const {
1932 // Variable argument functions are not supported.
1933 if (!PerformTailCallOpt || TheCall->isVarArg())
1936 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
1937 MachineFunction &MF = DAG.getMachineFunction();
1938 unsigned CallerCC = MF.getFunction()->getCallingConv();
1939 unsigned CalleeCC = TheCall->getCallingConv();
1940 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1941 // Functions containing by val parameters are not supported.
1942 for (unsigned i = 0; i != TheCall->getNumArgs(); i++) {
1943 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1944 if (Flags.isByVal()) return false;
1947 SDValue Callee = TheCall->getCallee();
1948 // Non PIC/GOT tail calls are supported.
1949 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1952 // At the moment we can only do local tail calls (in same module, hidden
1953 // or protected) if we are generating PIC.
1954 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1955 return G->getGlobal()->hasHiddenVisibility()
1956 || G->getGlobal()->hasProtectedVisibility();
1963 /// isCallCompatibleAddress - Return the immediate to use if the specified
1964 /// 32-bit value is representable in the immediate field of a BxA instruction.
1965 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
1966 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1969 int Addr = C->getZExtValue();
1970 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1971 (Addr << 6 >> 6) != Addr)
1972 return 0; // Top 6 bits have to be sext of immediate.
1974 return DAG.getConstant((int)C->getZExtValue() >> 2,
1975 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
1980 struct TailCallArgumentInfo {
1985 TailCallArgumentInfo() : FrameIdx(0) {}
1990 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
1992 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
1994 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
1995 SmallVector<SDValue, 8> &MemOpChains,
1997 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
1998 SDValue Arg = TailCallArgs[i].Arg;
1999 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2000 int FI = TailCallArgs[i].FrameIdx;
2001 // Store relative to framepointer.
2002 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2003 PseudoSourceValue::getFixedStack(FI),
2008 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2009 /// the appropriate stack slot for the tail call optimized function call.
2010 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2011 MachineFunction &MF,
2020 // Calculate the new stack slot for the return address.
2021 int SlotSize = isPPC64 ? 8 : 4;
2022 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
2024 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2026 int NewFPLoc = SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64,
2028 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc);
2030 MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2031 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2032 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2033 PseudoSourceValue::getFixedStack(NewRetAddr), 0);
2034 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2035 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2036 PseudoSourceValue::getFixedStack(NewFPIdx), 0);
2041 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2042 /// the position of the argument.
2044 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2045 SDValue Arg, int SPDiff, unsigned ArgOffset,
2046 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2047 int Offset = ArgOffset + SPDiff;
2048 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2049 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
2050 MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2051 SDValue FIN = DAG.getFrameIndex(FI, VT);
2052 TailCallArgumentInfo Info;
2054 Info.FrameIdxOp = FIN;
2056 TailCallArguments.push_back(Info);
2059 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2060 /// stack slot. Returns the chain as result and the loaded frame pointers in
2061 /// LROpOut/FPOpout. Used when tail calling.
2062 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2069 // Load the LR and FP stack slot for later adjusting.
2070 MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2071 LROpOut = getReturnAddrFrameIndex(DAG);
2072 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0);
2073 Chain = SDValue(LROpOut.getNode(), 1);
2074 FPOpOut = getFramePointerFrameIndex(DAG);
2075 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0);
2076 Chain = SDValue(FPOpOut.getNode(), 1);
2081 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2082 /// by "Src" to address "Dst" of size "Size". Alignment information is
2083 /// specified by the specific parameter attribute. The copy will be passed as
2084 /// a byval function parameter.
2085 /// Sometimes what we are copying is the end of a larger object, the part that
2086 /// does not fit in registers.
2088 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2089 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2091 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2092 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2093 false, NULL, 0, NULL, 0);
2096 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2099 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2100 SDValue Arg, SDValue PtrOff, int SPDiff,
2101 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2102 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2103 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments,
2105 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2110 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2112 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2113 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2114 DAG.getConstant(ArgOffset, PtrVT));
2116 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0));
2117 // Calculate and remember argument location.
2118 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2122 SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
2123 const PPCSubtarget &Subtarget,
2124 TargetMachine &TM) {
2125 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
2126 SDValue Chain = TheCall->getChain();
2127 bool isVarArg = TheCall->isVarArg();
2128 unsigned CC = TheCall->getCallingConv();
2129 bool isTailCall = TheCall->isTailCall()
2130 && CC == CallingConv::Fast && PerformTailCallOpt;
2131 SDValue Callee = TheCall->getCallee();
2132 unsigned NumOps = TheCall->getNumArgs();
2133 DebugLoc dl = TheCall->getDebugLoc();
2135 bool isMachoABI = Subtarget.isMachoABI();
2136 bool isELF32_ABI = Subtarget.isELF32_ABI();
2138 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2139 bool isPPC64 = PtrVT == MVT::i64;
2140 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2142 MachineFunction &MF = DAG.getMachineFunction();
2144 // Mark this function as potentially containing a function that contains a
2145 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2146 // and restoring the callers stack pointer in this functions epilog. This is
2147 // done because by tail calling the called function might overwrite the value
2148 // in this function's (MF) stack pointer stack slot 0(SP).
2149 if (PerformTailCallOpt && CC==CallingConv::Fast)
2150 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2152 unsigned nAltivecParamsAtEnd = 0;
2154 // Count how many bytes are to be pushed on the stack, including the linkage
2155 // area, and parameter passing area. We start with 24/48 bytes, which is
2156 // prereserved space for [SP][CR][LR][3 x unused].
2158 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isMachoABI, isVarArg, CC,
2159 TheCall, nAltivecParamsAtEnd);
2161 // Calculate by how many bytes the stack has to be adjusted in case of tail
2162 // call optimization.
2163 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2165 // Adjust the stack pointer for the new arguments...
2166 // These operations are automatically eliminated by the prolog/epilog pass
2167 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2168 SDValue CallSeqStart = Chain;
2170 // Load the return address and frame pointer so it can be move somewhere else
2173 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, dl);
2175 // Set up a copy of the stack pointer for use loading and storing any
2176 // arguments that may not fit in the registers available for argument
2180 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2182 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2184 // Figure out which arguments are going to go in registers, and which in
2185 // memory. Also, if this is a vararg function, floating point operations
2186 // must be stored to our stack, and loaded into integer regs as well, if
2187 // any integer regs are available for argument passing.
2188 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
2189 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2191 static const unsigned GPR_32[] = { // 32-bit registers.
2192 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2193 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2195 static const unsigned GPR_64[] = { // 64-bit registers.
2196 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2197 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2199 static const unsigned *FPR = GetFPR(Subtarget);
2201 static const unsigned VR[] = {
2202 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2203 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2205 const unsigned NumGPRs = array_lengthof(GPR_32);
2206 const unsigned NumFPRs = isMachoABI ? 13 : 8;
2207 const unsigned NumVRs = array_lengthof(VR);
2209 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
2211 std::vector<std::pair<unsigned, SDValue> > RegsToPass;
2212 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2214 SmallVector<SDValue, 8> MemOpChains;
2215 for (unsigned i = 0; i != NumOps; ++i) {
2217 SDValue Arg = TheCall->getArg(i);
2218 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
2219 // See if next argument requires stack alignment in ELF
2220 bool Align = Flags.isSplit();
2222 // PtrOff will be used to store the current argument to the stack if a
2223 // register cannot be found for it.
2226 // Stack align in ELF 32
2227 if (isELF32_ABI && Align)
2228 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
2229 StackPtr.getValueType());
2231 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
2233 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
2235 // On PPC64, promote integers to 64-bit values.
2236 if (isPPC64 && Arg.getValueType() == MVT::i32) {
2237 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
2238 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2239 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
2242 // FIXME Elf untested, what are alignment rules?
2243 // FIXME memcpy is used way more than necessary. Correctness first.
2244 if (Flags.isByVal()) {
2245 unsigned Size = Flags.getByValSize();
2246 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2);
2247 if (Size==1 || Size==2) {
2248 // Very small objects are passed right-justified.
2249 // Everything else is passed left-justified.
2250 MVT VT = (Size==1) ? MVT::i8 : MVT::i16;
2251 if (GPR_idx != NumGPRs) {
2252 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
2254 MemOpChains.push_back(Load.getValue(1));
2255 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2257 ArgOffset += PtrByteSize;
2259 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
2260 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
2261 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
2262 CallSeqStart.getNode()->getOperand(0),
2264 // This must go outside the CALLSEQ_START..END.
2265 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2266 CallSeqStart.getNode()->getOperand(1));
2267 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2268 NewCallSeqStart.getNode());
2269 Chain = CallSeqStart = NewCallSeqStart;
2270 ArgOffset += PtrByteSize;
2274 // Copy entire object into memory. There are cases where gcc-generated
2275 // code assumes it is there, even if it could be put entirely into
2276 // registers. (This is not what the doc says.)
2277 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
2278 CallSeqStart.getNode()->getOperand(0),
2280 // This must go outside the CALLSEQ_START..END.
2281 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2282 CallSeqStart.getNode()->getOperand(1));
2283 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
2284 Chain = CallSeqStart = NewCallSeqStart;
2285 // And copy the pieces of it that fit into registers.
2286 for (unsigned j=0; j<Size; j+=PtrByteSize) {
2287 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
2288 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
2289 if (GPR_idx != NumGPRs) {
2290 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, NULL, 0);
2291 MemOpChains.push_back(Load.getValue(1));
2292 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2294 ArgOffset += PtrByteSize;
2296 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
2303 switch (Arg.getValueType().getSimpleVT()) {
2304 default: assert(0 && "Unexpected ValueType for argument!");
2307 // Double word align in ELF
2308 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2);
2309 if (GPR_idx != NumGPRs) {
2310 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
2312 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2313 isPPC64, isTailCall, false, MemOpChains,
2314 TailCallArguments, dl);
2317 if (inMem || isMachoABI) {
2318 // Stack align in ELF
2319 if (isELF32_ABI && Align)
2320 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
2322 ArgOffset += PtrByteSize;
2327 if (FPR_idx != NumFPRs) {
2328 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
2331 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
2332 MemOpChains.push_back(Store);
2334 // Float varargs are always shadowed in available integer registers
2335 if (GPR_idx != NumGPRs) {
2336 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
2337 MemOpChains.push_back(Load.getValue(1));
2338 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
2341 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
2342 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
2343 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
2344 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0);
2345 MemOpChains.push_back(Load.getValue(1));
2346 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
2350 // If we have any FPRs remaining, we may also have GPRs remaining.
2351 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
2354 if (GPR_idx != NumGPRs)
2356 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
2357 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
2362 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2363 isPPC64, isTailCall, false, MemOpChains,
2364 TailCallArguments, dl);
2367 if (inMem || isMachoABI) {
2368 // Stack align in ELF
2369 if (isELF32_ABI && Align)
2370 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
2374 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
2382 // These go aligned on the stack, or in the corresponding R registers
2383 // when within range. The Darwin PPC ABI doc claims they also go in
2384 // V registers; in fact gcc does this only for arguments that are
2385 // prototyped, not for those that match the ... We do it for all
2386 // arguments, seems to work.
2387 while (ArgOffset % 16 !=0) {
2388 ArgOffset += PtrByteSize;
2389 if (GPR_idx != NumGPRs)
2392 // We could elide this store in the case where the object fits
2393 // entirely in R registers. Maybe later.
2394 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2395 DAG.getConstant(ArgOffset, PtrVT));
2396 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0);
2397 MemOpChains.push_back(Store);
2398 if (VR_idx != NumVRs) {
2399 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0);
2400 MemOpChains.push_back(Load.getValue(1));
2401 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
2404 for (unsigned i=0; i<16; i+=PtrByteSize) {
2405 if (GPR_idx == NumGPRs)
2407 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
2408 DAG.getConstant(i, PtrVT));
2409 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, NULL, 0);
2410 MemOpChains.push_back(Load.getValue(1));
2411 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2416 // Non-varargs Altivec params generally go in registers, but have
2417 // stack space allocated at the end.
2418 if (VR_idx != NumVRs) {
2419 // Doesn't have GPR space allocated.
2420 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
2421 } else if (nAltivecParamsAtEnd==0) {
2422 // We are emitting Altivec params in order.
2423 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2424 isPPC64, isTailCall, true, MemOpChains,
2425 TailCallArguments, dl);
2431 // If all Altivec parameters fit in registers, as they usually do,
2432 // they get stack space following the non-Altivec parameters. We
2433 // don't track this here because nobody below needs it.
2434 // If there are more Altivec parameters than fit in registers emit
2436 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
2438 // Offset is aligned; skip 1st 12 params which go in V registers.
2439 ArgOffset = ((ArgOffset+15)/16)*16;
2441 for (unsigned i = 0; i != NumOps; ++i) {
2442 SDValue Arg = TheCall->getArg(i);
2443 MVT ArgType = Arg.getValueType();
2444 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
2445 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
2448 // We are emitting Altivec params in order.
2449 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2450 isPPC64, isTailCall, true, MemOpChains,
2451 TailCallArguments, dl);
2458 if (!MemOpChains.empty())
2459 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2460 &MemOpChains[0], MemOpChains.size());
2462 // Build a sequence of copy-to-reg nodes chained together with token chain
2463 // and flag operands which copy the outgoing args into the appropriate regs.
2465 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2466 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2467 RegsToPass[i].second, InFlag);
2468 InFlag = Chain.getValue(1);
2471 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
2472 if (isVarArg && isELF32_ABI) {
2473 SDValue SetCR(DAG.getTargetNode(PPC::CRSET, dl, MVT::i32), 0);
2474 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
2475 InFlag = Chain.getValue(1);
2478 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2479 // might overwrite each other in case of tail call optimization.
2481 SmallVector<SDValue, 8> MemOpChains2;
2482 // Do not flag preceeding copytoreg stuff together with the following stuff.
2484 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2486 if (!MemOpChains2.empty())
2487 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2488 &MemOpChains2[0], MemOpChains2.size());
2490 // Store the return address to the appropriate stack slot.
2491 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2492 isPPC64, isMachoABI, dl);
2495 // Emit callseq_end just before tailcall node.
2497 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2498 DAG.getIntPtrConstant(0, true), InFlag);
2499 InFlag = Chain.getValue(1);
2502 std::vector<MVT> NodeTys;
2503 NodeTys.push_back(MVT::Other); // Returns a chain
2504 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
2506 SmallVector<SDValue, 8> Ops;
2507 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
2509 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2510 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2511 // node so that legalize doesn't hack it.
2512 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2513 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
2514 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
2515 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
2516 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
2517 // If this is an absolute destination address, use the munged value.
2518 Callee = SDValue(Dest, 0);
2520 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2521 // to do the call, we can't use PPCISD::CALL.
2522 SDValue MTCTROps[] = {Chain, Callee, InFlag};
2523 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2524 2 + (InFlag.getNode() != 0));
2525 InFlag = Chain.getValue(1);
2527 // Copy the callee address into R12/X12 on darwin.
2529 unsigned Reg = Callee.getValueType() == MVT::i32 ? PPC::R12 : PPC::X12;
2530 Chain = DAG.getCopyToReg(Chain, dl, Reg, Callee, InFlag);
2531 InFlag = Chain.getValue(1);
2535 NodeTys.push_back(MVT::Other);
2536 NodeTys.push_back(MVT::Flag);
2537 Ops.push_back(Chain);
2538 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
2540 // Add CTR register as callee so a bctr can be emitted later.
2542 Ops.push_back(DAG.getRegister(PPC::CTR, getPointerTy()));
2545 // If this is a direct call, pass the chain and the callee.
2546 if (Callee.getNode()) {
2547 Ops.push_back(Chain);
2548 Ops.push_back(Callee);
2550 // If this is a tail call add stack pointer delta.
2552 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2554 // Add argument registers to the end of the list so that they are known live
2556 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2557 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2558 RegsToPass[i].second.getValueType()));
2560 // When performing tail call optimization the callee pops its arguments off
2561 // the stack. Account for this here so these bytes can be pushed back on in
2562 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2563 int BytesCalleePops =
2564 (CC==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0;
2566 if (InFlag.getNode())
2567 Ops.push_back(InFlag);
2571 assert(InFlag.getNode() &&
2572 "Flag must be set. Depend on flag being set in LowerRET");
2573 Chain = DAG.getNode(PPCISD::TAILCALL, dl,
2574 TheCall->getVTList(), &Ops[0], Ops.size());
2575 return SDValue(Chain.getNode(), Op.getResNo());
2578 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
2579 InFlag = Chain.getValue(1);
2581 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2582 DAG.getIntPtrConstant(BytesCalleePops, true),
2584 if (TheCall->getValueType(0) != MVT::Other)
2585 InFlag = Chain.getValue(1);
2587 SmallVector<SDValue, 16> ResultVals;
2588 SmallVector<CCValAssign, 16> RVLocs;
2589 unsigned CallerCC = DAG.getMachineFunction().getFunction()->getCallingConv();
2590 CCState CCInfo(CallerCC, isVarArg, TM, RVLocs);
2591 CCInfo.AnalyzeCallResult(TheCall, RetCC_PPC);
2593 // Copy all of the result registers out of their specified physreg.
2594 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2595 CCValAssign &VA = RVLocs[i];
2596 MVT VT = VA.getValVT();
2597 assert(VA.isRegLoc() && "Can only return in registers!");
2598 Chain = DAG.getCopyFromReg(Chain, dl,
2599 VA.getLocReg(), VT, InFlag).getValue(1);
2600 ResultVals.push_back(Chain.getValue(0));
2601 InFlag = Chain.getValue(2);
2604 // If the function returns void, just return the chain.
2608 // Otherwise, merge everything together with a MERGE_VALUES node.
2609 ResultVals.push_back(Chain);
2610 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
2611 &ResultVals[0], ResultVals.size());
2612 return Res.getValue(Op.getResNo());
2615 SDValue PPCTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG,
2616 TargetMachine &TM) {
2617 SmallVector<CCValAssign, 16> RVLocs;
2618 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
2619 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
2620 DebugLoc dl = Op.getDebugLoc();
2621 CCState CCInfo(CC, isVarArg, TM, RVLocs);
2622 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_PPC);
2624 // If this is the first return lowered for this function, add the regs to the
2625 // liveout set for the function.
2626 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2627 for (unsigned i = 0; i != RVLocs.size(); ++i)
2628 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2631 SDValue Chain = Op.getOperand(0);
2633 Chain = GetPossiblePreceedingTailCall(Chain, PPCISD::TAILCALL);
2634 if (Chain.getOpcode() == PPCISD::TAILCALL) {
2635 SDValue TailCall = Chain;
2636 SDValue TargetAddress = TailCall.getOperand(1);
2637 SDValue StackAdjustment = TailCall.getOperand(2);
2639 assert(((TargetAddress.getOpcode() == ISD::Register &&
2640 cast<RegisterSDNode>(TargetAddress)->getReg() == PPC::CTR) ||
2641 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
2642 TargetAddress.getOpcode() == ISD::TargetGlobalAddress ||
2643 isa<ConstantSDNode>(TargetAddress)) &&
2644 "Expecting an global address, external symbol, absolute value or register");
2646 assert(StackAdjustment.getOpcode() == ISD::Constant &&
2647 "Expecting a const value");
2649 SmallVector<SDValue,8> Operands;
2650 Operands.push_back(Chain.getOperand(0));
2651 Operands.push_back(TargetAddress);
2652 Operands.push_back(StackAdjustment);
2653 // Copy registers used by the call. Last operand is a flag so it is not
2655 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
2656 Operands.push_back(Chain.getOperand(i));
2658 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Operands[0],
2664 // Copy the result values into the output registers.
2665 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2666 CCValAssign &VA = RVLocs[i];
2667 assert(VA.isRegLoc() && "Can only return in registers!");
2668 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
2669 Op.getOperand(i*2+1), Flag);
2670 Flag = Chain.getValue(1);
2674 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
2676 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
2679 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
2680 const PPCSubtarget &Subtarget) {
2681 // When we pop the dynamic allocation we need to restore the SP link.
2682 DebugLoc dl = Op.getDebugLoc();
2684 // Get the corect type for pointers.
2685 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2687 // Construct the stack pointer operand.
2688 bool IsPPC64 = Subtarget.isPPC64();
2689 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
2690 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
2692 // Get the operands for the STACKRESTORE.
2693 SDValue Chain = Op.getOperand(0);
2694 SDValue SaveSP = Op.getOperand(1);
2696 // Load the old link SP.
2697 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0);
2699 // Restore the stack pointer.
2700 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
2702 // Store the old link SP.
2703 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0);
2709 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
2710 MachineFunction &MF = DAG.getMachineFunction();
2711 bool IsPPC64 = PPCSubTarget.isPPC64();
2712 bool isMachoABI = PPCSubTarget.isMachoABI();
2713 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2715 // Get current frame pointer save index. The users of this index will be
2716 // primarily DYNALLOC instructions.
2717 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2718 int RASI = FI->getReturnAddrSaveIndex();
2720 // If the frame pointer save index hasn't been defined yet.
2722 // Find out what the fix offset of the frame pointer save area.
2723 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isMachoABI);
2724 // Allocate the frame index for frame pointer save area.
2725 RASI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, LROffset);
2727 FI->setReturnAddrSaveIndex(RASI);
2729 return DAG.getFrameIndex(RASI, PtrVT);
2733 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
2734 MachineFunction &MF = DAG.getMachineFunction();
2735 bool IsPPC64 = PPCSubTarget.isPPC64();
2736 bool isMachoABI = PPCSubTarget.isMachoABI();
2737 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2739 // Get current frame pointer save index. The users of this index will be
2740 // primarily DYNALLOC instructions.
2741 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2742 int FPSI = FI->getFramePointerSaveIndex();
2744 // If the frame pointer save index hasn't been defined yet.
2746 // Find out what the fix offset of the frame pointer save area.
2747 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
2749 // Allocate the frame index for frame pointer save area.
2750 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
2752 FI->setFramePointerSaveIndex(FPSI);
2754 return DAG.getFrameIndex(FPSI, PtrVT);
2757 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
2759 const PPCSubtarget &Subtarget) {
2761 SDValue Chain = Op.getOperand(0);
2762 SDValue Size = Op.getOperand(1);
2763 DebugLoc dl = Op.getDebugLoc();
2765 // Get the corect type for pointers.
2766 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2768 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
2769 DAG.getConstant(0, PtrVT), Size);
2770 // Construct a node for the frame pointer save index.
2771 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
2772 // Build a DYNALLOC node.
2773 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
2774 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
2775 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
2778 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
2780 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
2781 // Not FP? Not a fsel.
2782 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
2783 !Op.getOperand(2).getValueType().isFloatingPoint())
2786 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2788 // Cannot handle SETEQ/SETNE.
2789 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
2791 MVT ResVT = Op.getValueType();
2792 MVT CmpVT = Op.getOperand(0).getValueType();
2793 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2794 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
2795 DebugLoc dl = Op.getDebugLoc();
2797 // If the RHS of the comparison is a 0.0, we don't need to do the
2798 // subtraction at all.
2799 if (isFloatingPointZero(RHS))
2801 default: break; // SETUO etc aren't handled by fsel.
2804 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2807 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2808 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
2809 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
2812 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2815 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2816 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
2817 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
2818 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
2823 default: break; // SETUO etc aren't handled by fsel.
2826 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
2827 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2828 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
2829 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
2832 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
2833 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2834 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
2835 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
2838 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
2839 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2840 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
2841 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
2844 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
2845 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2846 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
2847 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
2852 // FIXME: Split this code up when LegalizeDAGTypes lands.
2853 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
2855 assert(Op.getOperand(0).getValueType().isFloatingPoint());
2856 SDValue Src = Op.getOperand(0);
2857 if (Src.getValueType() == MVT::f32)
2858 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
2861 switch (Op.getValueType().getSimpleVT()) {
2862 default: assert(0 && "Unhandled FP_TO_INT type in custom expander!");
2864 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
2869 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
2873 // Convert the FP value to an int value through memory.
2874 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
2876 // Emit a store to the stack slot.
2877 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0);
2879 // Result is a load from the stack slot. If loading 4 bytes, make sure to
2881 if (Op.getValueType() == MVT::i32)
2882 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
2883 DAG.getConstant(4, FIPtr.getValueType()));
2884 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0);
2887 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2888 DebugLoc dl = Op.getDebugLoc();
2889 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
2890 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
2893 if (Op.getOperand(0).getValueType() == MVT::i64) {
2894 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl,
2895 MVT::f64, Op.getOperand(0));
2896 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
2897 if (Op.getValueType() == MVT::f32)
2898 FP = DAG.getNode(ISD::FP_ROUND, dl,
2899 MVT::f32, FP, DAG.getIntPtrConstant(0));
2903 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
2904 "Unhandled SINT_TO_FP type in custom expander!");
2905 // Since we only generate this in 64-bit mode, we can take advantage of
2906 // 64-bit registers. In particular, sign extend the input value into the
2907 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
2908 // then lfd it and fcfid it.
2909 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2910 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
2911 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2912 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2914 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
2917 // STD the extended value into the stack slot.
2918 MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx),
2919 MachineMemOperand::MOStore, 0, 8, 8);
2920 SDValue Store = DAG.getNode(PPCISD::STD_32, dl, MVT::Other,
2921 DAG.getEntryNode(), Ext64, FIdx,
2922 DAG.getMemOperand(MO));
2923 // Load the value as a double.
2924 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0);
2926 // FCFID it and return it.
2927 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
2928 if (Op.getValueType() == MVT::f32)
2929 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
2933 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
2934 DebugLoc dl = Op.getDebugLoc();
2936 The rounding mode is in bits 30:31 of FPSR, and has the following
2943 FLT_ROUNDS, on the other hand, expects the following:
2950 To perform the conversion, we do:
2951 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
2954 MachineFunction &MF = DAG.getMachineFunction();
2955 MVT VT = Op.getValueType();
2956 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2957 std::vector<MVT> NodeTys;
2958 SDValue MFFSreg, InFlag;
2960 // Save FP Control Word to register
2961 NodeTys.push_back(MVT::f64); // return register
2962 NodeTys.push_back(MVT::Flag); // unused in this context
2963 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
2965 // Save FP register to stack slot
2966 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
2967 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
2968 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
2969 StackSlot, NULL, 0);
2971 // Load FP Control Word from low 32 bits of stack slot.
2972 SDValue Four = DAG.getConstant(4, PtrVT);
2973 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
2974 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0);
2976 // Transform as necessary
2978 DAG.getNode(ISD::AND, dl, MVT::i32,
2979 CWD, DAG.getConstant(3, MVT::i32));
2981 DAG.getNode(ISD::SRL, dl, MVT::i32,
2982 DAG.getNode(ISD::AND, dl, MVT::i32,
2983 DAG.getNode(ISD::XOR, dl, MVT::i32,
2984 CWD, DAG.getConstant(3, MVT::i32)),
2985 DAG.getConstant(3, MVT::i32)),
2986 DAG.getConstant(1, MVT::i32));
2989 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
2991 return DAG.getNode((VT.getSizeInBits() < 16 ?
2992 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
2995 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) {
2996 MVT VT = Op.getValueType();
2997 unsigned BitWidth = VT.getSizeInBits();
2998 DebugLoc dl = Op.getDebugLoc();
2999 assert(Op.getNumOperands() == 3 &&
3000 VT == Op.getOperand(1).getValueType() &&
3003 // Expand into a bunch of logical ops. Note that these ops
3004 // depend on the PPC behavior for oversized shift amounts.
3005 SDValue Lo = Op.getOperand(0);
3006 SDValue Hi = Op.getOperand(1);
3007 SDValue Amt = Op.getOperand(2);
3008 MVT AmtVT = Amt.getValueType();
3010 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3011 DAG.getConstant(BitWidth, AmtVT), Amt);
3012 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3013 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3014 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3015 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3016 DAG.getConstant(-BitWidth, AmtVT));
3017 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3018 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3019 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3020 SDValue OutOps[] = { OutLo, OutHi };
3021 return DAG.getMergeValues(OutOps, 2, dl);
3024 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) {
3025 MVT VT = Op.getValueType();
3026 DebugLoc dl = Op.getDebugLoc();
3027 unsigned BitWidth = VT.getSizeInBits();
3028 assert(Op.getNumOperands() == 3 &&
3029 VT == Op.getOperand(1).getValueType() &&
3032 // Expand into a bunch of logical ops. Note that these ops
3033 // depend on the PPC behavior for oversized shift amounts.
3034 SDValue Lo = Op.getOperand(0);
3035 SDValue Hi = Op.getOperand(1);
3036 SDValue Amt = Op.getOperand(2);
3037 MVT AmtVT = Amt.getValueType();
3039 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3040 DAG.getConstant(BitWidth, AmtVT), Amt);
3041 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3042 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3043 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3044 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3045 DAG.getConstant(-BitWidth, AmtVT));
3046 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3047 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3048 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3049 SDValue OutOps[] = { OutLo, OutHi };
3050 return DAG.getMergeValues(OutOps, 2, dl);
3053 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) {
3054 DebugLoc dl = Op.getDebugLoc();
3055 MVT VT = Op.getValueType();
3056 unsigned BitWidth = VT.getSizeInBits();
3057 assert(Op.getNumOperands() == 3 &&
3058 VT == Op.getOperand(1).getValueType() &&
3061 // Expand into a bunch of logical ops, followed by a select_cc.
3062 SDValue Lo = Op.getOperand(0);
3063 SDValue Hi = Op.getOperand(1);
3064 SDValue Amt = Op.getOperand(2);
3065 MVT AmtVT = Amt.getValueType();
3067 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3068 DAG.getConstant(BitWidth, AmtVT), Amt);
3069 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3070 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3071 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3072 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3073 DAG.getConstant(-BitWidth, AmtVT));
3074 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3075 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3076 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
3077 Tmp4, Tmp6, ISD::SETLE);
3078 SDValue OutOps[] = { OutLo, OutHi };
3079 return DAG.getMergeValues(OutOps, 2, dl);
3082 //===----------------------------------------------------------------------===//
3083 // Vector related lowering.
3086 /// BuildSplatI - Build a canonical splati of Val with an element size of
3087 /// SplatSize. Cast the result to VT.
3088 static SDValue BuildSplatI(int Val, unsigned SplatSize, MVT VT,
3089 SelectionDAG &DAG, DebugLoc dl) {
3090 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3092 static const MVT VTys[] = { // canonical VT to use for each size.
3093 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3096 MVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3098 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3102 MVT CanonicalVT = VTys[SplatSize-1];
3104 // Build a canonical splat for this value.
3105 SDValue Elt = DAG.getConstant(Val, MVT::i32);
3106 SmallVector<SDValue, 8> Ops;
3107 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3108 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
3109 &Ops[0], Ops.size());
3110 return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res);
3113 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3114 /// specified intrinsic ID.
3115 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3116 SelectionDAG &DAG, DebugLoc dl,
3117 MVT DestVT = MVT::Other) {
3118 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3119 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3120 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3123 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3124 /// specified intrinsic ID.
3125 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3126 SDValue Op2, SelectionDAG &DAG,
3127 DebugLoc dl, MVT DestVT = MVT::Other) {
3128 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3129 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3130 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3134 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3135 /// amount. The result has the specified value type.
3136 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3137 MVT VT, SelectionDAG &DAG, DebugLoc dl) {
3138 // Force LHS/RHS to be the right type.
3139 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS);
3140 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS);
3143 for (unsigned i = 0; i != 16; ++i)
3145 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
3146 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
3149 // If this is a case we can't handle, return null and let the default
3150 // expansion code take care of it. If we CAN select this case, and if it
3151 // selects to a single instruction, return Op. Otherwise, if we can codegen
3152 // this case more efficiently than a constant pool load, lower it to the
3153 // sequence of ops that should be used.
3154 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
3155 DebugLoc dl = Op.getDebugLoc();
3156 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3157 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
3159 // Check if this is a splat of a constant value.
3160 APInt APSplatBits, APSplatUndef;
3161 unsigned SplatBitSize;
3163 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
3164 HasAnyUndefs) || SplatBitSize > 32)
3167 unsigned SplatBits = APSplatBits.getZExtValue();
3168 unsigned SplatUndef = APSplatUndef.getZExtValue();
3169 unsigned SplatSize = SplatBitSize / 8;
3171 // First, handle single instruction cases.
3174 if (SplatBits == 0) {
3175 // Canonicalize all zero vectors to be v4i32.
3176 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3177 SDValue Z = DAG.getConstant(0, MVT::i32);
3178 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
3179 Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z);
3184 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3185 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
3187 if (SextVal >= -16 && SextVal <= 15)
3188 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
3191 // Two instruction sequences.
3193 // If this value is in the range [-32,30] and is even, use:
3194 // tmp = VSPLTI[bhw], result = add tmp, tmp
3195 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
3196 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
3197 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
3198 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3201 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
3202 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
3204 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
3205 // Make -1 and vspltisw -1:
3206 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
3208 // Make the VSLW intrinsic, computing 0x8000_0000.
3209 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
3212 // xor by OnesV to invert it.
3213 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
3214 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3217 // Check to see if this is a wide variety of vsplti*, binop self cases.
3218 static const signed char SplatCsts[] = {
3219 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
3220 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
3223 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
3224 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
3225 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
3226 int i = SplatCsts[idx];
3228 // Figure out what shift amount will be used by altivec if shifted by i in
3230 unsigned TypeShiftAmt = i & (SplatBitSize-1);
3232 // vsplti + shl self.
3233 if (SextVal == (i << (int)TypeShiftAmt)) {
3234 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3235 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3236 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
3237 Intrinsic::ppc_altivec_vslw
3239 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3240 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3243 // vsplti + srl self.
3244 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3245 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3246 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3247 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
3248 Intrinsic::ppc_altivec_vsrw
3250 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3251 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3254 // vsplti + sra self.
3255 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3256 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3257 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3258 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
3259 Intrinsic::ppc_altivec_vsraw
3261 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3262 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3265 // vsplti + rol self.
3266 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
3267 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
3268 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3269 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3270 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
3271 Intrinsic::ppc_altivec_vrlw
3273 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3274 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3277 // t = vsplti c, result = vsldoi t, t, 1
3278 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
3279 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3280 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
3282 // t = vsplti c, result = vsldoi t, t, 2
3283 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
3284 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3285 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
3287 // t = vsplti c, result = vsldoi t, t, 3
3288 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
3289 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3290 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
3294 // Three instruction sequences.
3296 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
3297 if (SextVal >= 0 && SextVal <= 31) {
3298 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
3299 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3300 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
3301 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3303 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
3304 if (SextVal >= -31 && SextVal <= 0) {
3305 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
3306 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3307 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
3308 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3314 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3315 /// the specified operations to build the shuffle.
3316 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3317 SDValue RHS, SelectionDAG &DAG,
3319 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3320 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3321 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3324 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3336 if (OpNum == OP_COPY) {
3337 if (LHSID == (1*9+2)*9+3) return LHS;
3338 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3342 SDValue OpLHS, OpRHS;
3343 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
3344 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
3348 default: assert(0 && "Unknown i32 permute!");
3350 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
3351 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
3352 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
3353 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
3356 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
3357 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
3358 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
3359 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
3362 for (unsigned i = 0; i != 16; ++i)
3363 ShufIdxs[i] = (i&3)+0;
3366 for (unsigned i = 0; i != 16; ++i)
3367 ShufIdxs[i] = (i&3)+4;
3370 for (unsigned i = 0; i != 16; ++i)
3371 ShufIdxs[i] = (i&3)+8;
3374 for (unsigned i = 0; i != 16; ++i)
3375 ShufIdxs[i] = (i&3)+12;
3378 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
3380 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
3382 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
3384 MVT VT = OpLHS.getValueType();
3385 OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS);
3386 OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS);
3387 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
3388 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
3391 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
3392 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
3393 /// return the code it can be lowered into. Worst case, it can always be
3394 /// lowered into a vperm.
3395 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
3396 SelectionDAG &DAG) {
3397 DebugLoc dl = Op.getDebugLoc();
3398 SDValue V1 = Op.getOperand(0);
3399 SDValue V2 = Op.getOperand(1);
3400 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
3401 MVT VT = Op.getValueType();
3403 // Cases that are handled by instructions that take permute immediates
3404 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
3405 // selected by the instruction selector.
3406 if (V2.getOpcode() == ISD::UNDEF) {
3407 if (PPC::isSplatShuffleMask(SVOp, 1) ||
3408 PPC::isSplatShuffleMask(SVOp, 2) ||
3409 PPC::isSplatShuffleMask(SVOp, 4) ||
3410 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
3411 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
3412 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
3413 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
3414 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
3415 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
3416 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
3417 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
3418 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
3423 // Altivec has a variety of "shuffle immediates" that take two vector inputs
3424 // and produce a fixed permutation. If any of these match, do not lower to
3426 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
3427 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
3428 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
3429 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
3430 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
3431 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
3432 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
3433 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
3434 PPC::isVMRGHShuffleMask(SVOp, 4, false))
3437 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
3438 // perfect shuffle table to emit an optimal matching sequence.
3439 SmallVector<int, 16> PermMask;
3440 SVOp->getMask(PermMask);
3442 unsigned PFIndexes[4];
3443 bool isFourElementShuffle = true;
3444 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
3445 unsigned EltNo = 8; // Start out undef.
3446 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
3447 if (PermMask[i*4+j] < 0)
3448 continue; // Undef, ignore it.
3450 unsigned ByteSource = PermMask[i*4+j];
3451 if ((ByteSource & 3) != j) {
3452 isFourElementShuffle = false;
3457 EltNo = ByteSource/4;
3458 } else if (EltNo != ByteSource/4) {
3459 isFourElementShuffle = false;
3463 PFIndexes[i] = EltNo;
3466 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
3467 // perfect shuffle vector to determine if it is cost effective to do this as
3468 // discrete instructions, or whether we should use a vperm.
3469 if (isFourElementShuffle) {
3470 // Compute the index in the perfect shuffle table.
3471 unsigned PFTableIndex =
3472 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3474 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3475 unsigned Cost = (PFEntry >> 30);
3477 // Determining when to avoid vperm is tricky. Many things affect the cost
3478 // of vperm, particularly how many times the perm mask needs to be computed.
3479 // For example, if the perm mask can be hoisted out of a loop or is already
3480 // used (perhaps because there are multiple permutes with the same shuffle
3481 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
3482 // the loop requires an extra register.
3484 // As a compromise, we only emit discrete instructions if the shuffle can be
3485 // generated in 3 or fewer operations. When we have loop information
3486 // available, if this block is within a loop, we should avoid using vperm
3487 // for 3-operation perms and use a constant pool load instead.
3489 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
3492 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
3493 // vector that will get spilled to the constant pool.
3494 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
3496 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
3497 // that it is in input element units, not in bytes. Convert now.
3498 MVT EltVT = V1.getValueType().getVectorElementType();
3499 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
3501 SmallVector<SDValue, 16> ResultMask;
3502 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
3503 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
3505 for (unsigned j = 0; j != BytesPerElement; ++j)
3506 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
3510 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
3511 &ResultMask[0], ResultMask.size());
3512 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
3515 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
3516 /// altivec comparison. If it is, return true and fill in Opc/isDot with
3517 /// information about the intrinsic.
3518 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
3520 unsigned IntrinsicID =
3521 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
3524 switch (IntrinsicID) {
3525 default: return false;
3526 // Comparison predicates.
3527 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
3528 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
3529 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
3530 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
3531 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
3532 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
3533 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
3534 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
3535 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
3536 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
3537 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
3538 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
3539 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
3541 // Normal Comparisons.
3542 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
3543 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
3544 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
3545 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
3546 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
3547 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
3548 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
3549 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
3550 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
3551 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
3552 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
3553 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
3554 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
3559 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
3560 /// lower, do it, otherwise return null.
3561 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
3562 SelectionDAG &DAG) {
3563 // If this is a lowered altivec predicate compare, CompareOpc is set to the
3564 // opcode number of the comparison.
3565 DebugLoc dl = Op.getDebugLoc();
3568 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
3569 return SDValue(); // Don't custom lower most intrinsics.
3571 // If this is a non-dot comparison, make the VCMP node and we are done.
3573 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
3574 Op.getOperand(1), Op.getOperand(2),
3575 DAG.getConstant(CompareOpc, MVT::i32));
3576 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp);
3579 // Create the PPCISD altivec 'dot' comparison node.
3581 Op.getOperand(2), // LHS
3582 Op.getOperand(3), // RHS
3583 DAG.getConstant(CompareOpc, MVT::i32)
3585 std::vector<MVT> VTs;
3586 VTs.push_back(Op.getOperand(2).getValueType());
3587 VTs.push_back(MVT::Flag);
3588 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
3590 // Now that we have the comparison, emit a copy from the CR to a GPR.
3591 // This is flagged to the above dot comparison.
3592 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
3593 DAG.getRegister(PPC::CR6, MVT::i32),
3594 CompNode.getValue(1));
3596 // Unpack the result based on how the target uses it.
3597 unsigned BitNo; // Bit # of CR6.
3598 bool InvertBit; // Invert result?
3599 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
3600 default: // Can't happen, don't crash on invalid number though.
3601 case 0: // Return the value of the EQ bit of CR6.
3602 BitNo = 0; InvertBit = false;
3604 case 1: // Return the inverted value of the EQ bit of CR6.
3605 BitNo = 0; InvertBit = true;
3607 case 2: // Return the value of the LT bit of CR6.
3608 BitNo = 2; InvertBit = false;
3610 case 3: // Return the inverted value of the LT bit of CR6.
3611 BitNo = 2; InvertBit = true;
3615 // Shift the bit into the low position.
3616 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
3617 DAG.getConstant(8-(3-BitNo), MVT::i32));
3619 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
3620 DAG.getConstant(1, MVT::i32));
3622 // If we are supposed to, toggle the bit.
3624 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
3625 DAG.getConstant(1, MVT::i32));
3629 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
3630 SelectionDAG &DAG) {
3631 DebugLoc dl = Op.getDebugLoc();
3632 // Create a stack slot that is 16-byte aligned.
3633 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3634 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
3635 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3636 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3638 // Store the input value into Value#0 of the stack slot.
3639 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
3640 Op.getOperand(0), FIdx, NULL, 0);
3642 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0);
3645 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
3646 DebugLoc dl = Op.getDebugLoc();
3647 if (Op.getValueType() == MVT::v4i32) {
3648 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3650 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
3651 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
3653 SDValue RHSSwap = // = vrlw RHS, 16
3654 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
3656 // Shrinkify inputs to v8i16.
3657 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS);
3658 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS);
3659 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap);
3661 // Low parts multiplied together, generating 32-bit results (we ignore the
3663 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
3664 LHS, RHS, DAG, dl, MVT::v4i32);
3666 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
3667 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
3668 // Shift the high parts up 16 bits.
3669 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
3671 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
3672 } else if (Op.getValueType() == MVT::v8i16) {
3673 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3675 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
3677 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
3678 LHS, RHS, Zero, DAG, dl);
3679 } else if (Op.getValueType() == MVT::v16i8) {
3680 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3682 // Multiply the even 8-bit parts, producing 16-bit sums.
3683 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
3684 LHS, RHS, DAG, dl, MVT::v8i16);
3685 EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts);
3687 // Multiply the odd 8-bit parts, producing 16-bit sums.
3688 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
3689 LHS, RHS, DAG, dl, MVT::v8i16);
3690 OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts);
3692 // Merge the results together.
3694 for (unsigned i = 0; i != 8; ++i) {
3696 Ops[i*2+1] = 2*i+1+16;
3698 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
3700 assert(0 && "Unknown mul to lower!");
3705 /// LowerOperation - Provide custom lowering hooks for some operations.
3707 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
3708 switch (Op.getOpcode()) {
3709 default: assert(0 && "Wasn't expecting to be able to lower this!");
3710 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3711 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3712 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3713 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3714 case ISD::SETCC: return LowerSETCC(Op, DAG);
3715 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
3717 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3718 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3721 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3722 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3724 case ISD::FORMAL_ARGUMENTS:
3725 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
3726 VarArgsStackOffset, VarArgsNumGPR,
3727 VarArgsNumFPR, PPCSubTarget);
3729 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget,
3730 getTargetMachine());
3731 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
3732 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
3733 case ISD::DYNAMIC_STACKALLOC:
3734 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
3736 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3737 case ISD::FP_TO_UINT:
3738 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
3740 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
3741 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3743 // Lower 64-bit shifts.
3744 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
3745 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
3746 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
3748 // Vector-related lowering.
3749 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3750 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3751 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3752 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
3753 case ISD::MUL: return LowerMUL(Op, DAG);
3755 // Frame & Return address.
3756 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3757 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3762 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
3763 SmallVectorImpl<SDValue>&Results,
3764 SelectionDAG &DAG) {
3765 DebugLoc dl = N->getDebugLoc();
3766 switch (N->getOpcode()) {
3768 assert(false && "Do not know how to custom type legalize this operation!");
3770 case ISD::FP_ROUND_INREG: {
3771 assert(N->getValueType(0) == MVT::ppcf128);
3772 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
3773 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
3774 MVT::f64, N->getOperand(0),
3775 DAG.getIntPtrConstant(0));
3776 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
3777 MVT::f64, N->getOperand(0),
3778 DAG.getIntPtrConstant(1));
3780 // This sequence changes FPSCR to do round-to-zero, adds the two halves
3781 // of the long double, and puts FPSCR back the way it was. We do not
3782 // actually model FPSCR.
3783 std::vector<MVT> NodeTys;
3784 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
3786 NodeTys.push_back(MVT::f64); // Return register
3787 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
3788 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
3789 MFFSreg = Result.getValue(0);
3790 InFlag = Result.getValue(1);
3793 NodeTys.push_back(MVT::Flag); // Returns a flag
3794 Ops[0] = DAG.getConstant(31, MVT::i32);
3796 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
3797 InFlag = Result.getValue(0);
3800 NodeTys.push_back(MVT::Flag); // Returns a flag
3801 Ops[0] = DAG.getConstant(30, MVT::i32);
3803 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
3804 InFlag = Result.getValue(0);
3807 NodeTys.push_back(MVT::f64); // result of add
3808 NodeTys.push_back(MVT::Flag); // Returns a flag
3812 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
3813 FPreg = Result.getValue(0);
3814 InFlag = Result.getValue(1);
3817 NodeTys.push_back(MVT::f64);
3818 Ops[0] = DAG.getConstant(1, MVT::i32);
3822 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
3823 FPreg = Result.getValue(0);
3825 // We know the low half is about to be thrown away, so just use something
3827 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
3831 case ISD::FP_TO_SINT:
3832 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
3838 //===----------------------------------------------------------------------===//
3839 // Other Lowering Code
3840 //===----------------------------------------------------------------------===//
3843 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3844 bool is64bit, unsigned BinOpcode) const {
3845 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3846 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3848 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3849 MachineFunction *F = BB->getParent();
3850 MachineFunction::iterator It = BB;
3853 unsigned dest = MI->getOperand(0).getReg();
3854 unsigned ptrA = MI->getOperand(1).getReg();
3855 unsigned ptrB = MI->getOperand(2).getReg();
3856 unsigned incr = MI->getOperand(3).getReg();
3857 DebugLoc dl = MI->getDebugLoc();
3859 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
3860 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
3861 F->insert(It, loopMBB);
3862 F->insert(It, exitMBB);
3863 exitMBB->transferSuccessors(BB);
3865 MachineRegisterInfo &RegInfo = F->getRegInfo();
3866 unsigned TmpReg = (!BinOpcode) ? incr :
3867 RegInfo.createVirtualRegister(
3868 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
3869 (const TargetRegisterClass *) &PPC::GPRCRegClass);
3873 // fallthrough --> loopMBB
3874 BB->addSuccessor(loopMBB);
3877 // l[wd]arx dest, ptr
3878 // add r0, dest, incr
3879 // st[wd]cx. r0, ptr
3881 // fallthrough --> exitMBB
3883 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
3884 .addReg(ptrA).addReg(ptrB);
3886 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
3887 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
3888 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
3889 BuildMI(BB, dl, TII->get(PPC::BCC))
3890 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
3891 BB->addSuccessor(loopMBB);
3892 BB->addSuccessor(exitMBB);
3901 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
3902 MachineBasicBlock *BB,
3903 bool is8bit, // operation
3904 unsigned BinOpcode) const {
3905 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3906 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3907 // In 64 bit mode we have to use 64 bits for addresses, even though the
3908 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
3909 // registers without caring whether they're 32 or 64, but here we're
3910 // doing actual arithmetic on the addresses.
3911 bool is64bit = PPCSubTarget.isPPC64();
3913 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3914 MachineFunction *F = BB->getParent();
3915 MachineFunction::iterator It = BB;
3918 unsigned dest = MI->getOperand(0).getReg();
3919 unsigned ptrA = MI->getOperand(1).getReg();
3920 unsigned ptrB = MI->getOperand(2).getReg();
3921 unsigned incr = MI->getOperand(3).getReg();
3922 DebugLoc dl = MI->getDebugLoc();
3924 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
3925 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
3926 F->insert(It, loopMBB);
3927 F->insert(It, exitMBB);
3928 exitMBB->transferSuccessors(BB);
3930 MachineRegisterInfo &RegInfo = F->getRegInfo();
3931 const TargetRegisterClass *RC =
3932 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
3933 (const TargetRegisterClass *) &PPC::GPRCRegClass;
3934 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
3935 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
3936 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
3937 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
3938 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
3939 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
3940 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
3941 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
3942 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
3943 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
3944 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
3946 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
3950 // fallthrough --> loopMBB
3951 BB->addSuccessor(loopMBB);
3953 // The 4-byte load must be aligned, while a char or short may be
3954 // anywhere in the word. Hence all this nasty bookkeeping code.
3955 // add ptr1, ptrA, ptrB [copy if ptrA==0]
3956 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
3957 // xori shift, shift1, 24 [16]
3958 // rlwinm ptr, ptr1, 0, 0, 29
3959 // slw incr2, incr, shift
3960 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
3961 // slw mask, mask2, shift
3963 // lwarx tmpDest, ptr
3964 // add tmp, tmpDest, incr2
3965 // andc tmp2, tmpDest, mask
3966 // and tmp3, tmp, mask
3967 // or tmp4, tmp3, tmp2
3970 // fallthrough --> exitMBB
3971 // srw dest, tmpDest, shift
3973 if (ptrA!=PPC::R0) {
3974 Ptr1Reg = RegInfo.createVirtualRegister(RC);
3975 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
3976 .addReg(ptrA).addReg(ptrB);
3980 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
3981 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
3982 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
3983 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
3985 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
3986 .addReg(Ptr1Reg).addImm(0).addImm(61);
3988 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
3989 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
3990 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
3991 .addReg(incr).addReg(ShiftReg);
3993 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
3995 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
3996 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
3998 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
3999 .addReg(Mask2Reg).addReg(ShiftReg);
4002 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4003 .addReg(PPC::R0).addReg(PtrReg);
4005 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
4006 .addReg(Incr2Reg).addReg(TmpDestReg);
4007 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4008 .addReg(TmpDestReg).addReg(MaskReg);
4009 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4010 .addReg(TmpReg).addReg(MaskReg);
4011 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4012 .addReg(Tmp3Reg).addReg(Tmp2Reg);
4013 BuildMI(BB, dl, TII->get(PPC::STWCX))
4014 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
4015 BuildMI(BB, dl, TII->get(PPC::BCC))
4016 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4017 BB->addSuccessor(loopMBB);
4018 BB->addSuccessor(exitMBB);
4023 BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
4028 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4029 MachineBasicBlock *BB) const {
4030 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4032 // To "insert" these instructions we actually have to insert their
4033 // control-flow patterns.
4034 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4035 MachineFunction::iterator It = BB;
4038 MachineFunction *F = BB->getParent();
4040 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4041 MI->getOpcode() == PPC::SELECT_CC_I8 ||
4042 MI->getOpcode() == PPC::SELECT_CC_F4 ||
4043 MI->getOpcode() == PPC::SELECT_CC_F8 ||
4044 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4046 // The incoming instruction knows the destination vreg to set, the
4047 // condition code register to branch on, the true/false values to
4048 // select between, and a branch opcode to use.
4053 // cmpTY ccX, r1, r2
4055 // fallthrough --> copy0MBB
4056 MachineBasicBlock *thisMBB = BB;
4057 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4058 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4059 unsigned SelectPred = MI->getOperand(4).getImm();
4060 DebugLoc dl = MI->getDebugLoc();
4061 BuildMI(BB, dl, TII->get(PPC::BCC))
4062 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4063 F->insert(It, copy0MBB);
4064 F->insert(It, sinkMBB);
4065 // Update machine-CFG edges by transferring all successors of the current
4066 // block to the new block which will contain the Phi node for the select.
4067 sinkMBB->transferSuccessors(BB);
4068 // Next, add the true and fallthrough blocks as its successors.
4069 BB->addSuccessor(copy0MBB);
4070 BB->addSuccessor(sinkMBB);
4073 // %FalseValue = ...
4074 // # fallthrough to sinkMBB
4077 // Update machine-CFG edges
4078 BB->addSuccessor(sinkMBB);
4081 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4084 BuildMI(BB, dl, TII->get(PPC::PHI), MI->getOperand(0).getReg())
4085 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4086 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4088 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4089 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4090 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4091 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4092 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4093 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4094 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4095 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4097 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4098 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4099 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4100 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4101 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4102 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4103 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4104 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4106 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4107 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4108 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4109 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4110 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4111 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4112 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4113 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4115 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4116 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4117 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4118 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4119 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4120 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4121 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4122 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4124 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4125 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
4126 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4127 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
4128 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4129 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
4130 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4131 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
4133 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
4134 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
4135 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
4136 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
4137 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
4138 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
4139 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
4140 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
4142 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
4143 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
4144 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
4145 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
4146 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
4147 BB = EmitAtomicBinary(MI, BB, false, 0);
4148 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
4149 BB = EmitAtomicBinary(MI, BB, true, 0);
4151 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
4152 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
4153 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
4155 unsigned dest = MI->getOperand(0).getReg();
4156 unsigned ptrA = MI->getOperand(1).getReg();
4157 unsigned ptrB = MI->getOperand(2).getReg();
4158 unsigned oldval = MI->getOperand(3).getReg();
4159 unsigned newval = MI->getOperand(4).getReg();
4160 DebugLoc dl = MI->getDebugLoc();
4162 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4163 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4164 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4165 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4166 F->insert(It, loop1MBB);
4167 F->insert(It, loop2MBB);
4168 F->insert(It, midMBB);
4169 F->insert(It, exitMBB);
4170 exitMBB->transferSuccessors(BB);
4174 // fallthrough --> loopMBB
4175 BB->addSuccessor(loop1MBB);
4178 // l[wd]arx dest, ptr
4179 // cmp[wd] dest, oldval
4182 // st[wd]cx. newval, ptr
4186 // st[wd]cx. dest, ptr
4189 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4190 .addReg(ptrA).addReg(ptrB);
4191 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
4192 .addReg(oldval).addReg(dest);
4193 BuildMI(BB, dl, TII->get(PPC::BCC))
4194 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4195 BB->addSuccessor(loop2MBB);
4196 BB->addSuccessor(midMBB);
4199 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4200 .addReg(newval).addReg(ptrA).addReg(ptrB);
4201 BuildMI(BB, dl, TII->get(PPC::BCC))
4202 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4203 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4204 BB->addSuccessor(loop1MBB);
4205 BB->addSuccessor(exitMBB);
4208 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4209 .addReg(dest).addReg(ptrA).addReg(ptrB);
4210 BB->addSuccessor(exitMBB);
4215 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
4216 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
4217 // We must use 64-bit registers for addresses when targeting 64-bit,
4218 // since we're actually doing arithmetic on them. Other registers
4220 bool is64bit = PPCSubTarget.isPPC64();
4221 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
4223 unsigned dest = MI->getOperand(0).getReg();
4224 unsigned ptrA = MI->getOperand(1).getReg();
4225 unsigned ptrB = MI->getOperand(2).getReg();
4226 unsigned oldval = MI->getOperand(3).getReg();
4227 unsigned newval = MI->getOperand(4).getReg();
4228 DebugLoc dl = MI->getDebugLoc();
4230 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4231 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4232 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4233 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4234 F->insert(It, loop1MBB);
4235 F->insert(It, loop2MBB);
4236 F->insert(It, midMBB);
4237 F->insert(It, exitMBB);
4238 exitMBB->transferSuccessors(BB);
4240 MachineRegisterInfo &RegInfo = F->getRegInfo();
4241 const TargetRegisterClass *RC =
4242 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4243 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4244 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4245 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4246 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4247 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
4248 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
4249 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
4250 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
4251 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4252 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4253 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4254 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4255 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4256 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4258 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
4261 // fallthrough --> loopMBB
4262 BB->addSuccessor(loop1MBB);
4264 // The 4-byte load must be aligned, while a char or short may be
4265 // anywhere in the word. Hence all this nasty bookkeeping code.
4266 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4267 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4268 // xori shift, shift1, 24 [16]
4269 // rlwinm ptr, ptr1, 0, 0, 29
4270 // slw newval2, newval, shift
4271 // slw oldval2, oldval,shift
4272 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4273 // slw mask, mask2, shift
4274 // and newval3, newval2, mask
4275 // and oldval3, oldval2, mask
4277 // lwarx tmpDest, ptr
4278 // and tmp, tmpDest, mask
4279 // cmpw tmp, oldval3
4282 // andc tmp2, tmpDest, mask
4283 // or tmp4, tmp2, newval3
4288 // stwcx. tmpDest, ptr
4290 // srw dest, tmpDest, shift
4291 if (ptrA!=PPC::R0) {
4292 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4293 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4294 .addReg(ptrA).addReg(ptrB);
4298 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4299 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4300 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4301 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4303 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4304 .addReg(Ptr1Reg).addImm(0).addImm(61);
4306 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4307 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4308 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
4309 .addReg(newval).addReg(ShiftReg);
4310 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
4311 .addReg(oldval).addReg(ShiftReg);
4313 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4315 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4316 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
4317 .addReg(Mask3Reg).addImm(65535);
4319 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4320 .addReg(Mask2Reg).addReg(ShiftReg);
4321 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
4322 .addReg(NewVal2Reg).addReg(MaskReg);
4323 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
4324 .addReg(OldVal2Reg).addReg(MaskReg);
4327 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4328 .addReg(PPC::R0).addReg(PtrReg);
4329 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
4330 .addReg(TmpDestReg).addReg(MaskReg);
4331 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
4332 .addReg(TmpReg).addReg(OldVal3Reg);
4333 BuildMI(BB, dl, TII->get(PPC::BCC))
4334 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4335 BB->addSuccessor(loop2MBB);
4336 BB->addSuccessor(midMBB);
4339 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
4340 .addReg(TmpDestReg).addReg(MaskReg);
4341 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
4342 .addReg(Tmp2Reg).addReg(NewVal3Reg);
4343 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
4344 .addReg(PPC::R0).addReg(PtrReg);
4345 BuildMI(BB, dl, TII->get(PPC::BCC))
4346 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4347 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4348 BB->addSuccessor(loop1MBB);
4349 BB->addSuccessor(exitMBB);
4352 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
4353 .addReg(PPC::R0).addReg(PtrReg);
4354 BB->addSuccessor(exitMBB);
4359 BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
4361 assert(0 && "Unexpected instr type to insert");
4364 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
4368 //===----------------------------------------------------------------------===//
4369 // Target Optimization Hooks
4370 //===----------------------------------------------------------------------===//
4372 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
4373 DAGCombinerInfo &DCI) const {
4374 TargetMachine &TM = getTargetMachine();
4375 SelectionDAG &DAG = DCI.DAG;
4376 DebugLoc dl = N->getDebugLoc();
4377 switch (N->getOpcode()) {
4380 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4381 if (C->getZExtValue() == 0) // 0 << V -> 0.
4382 return N->getOperand(0);
4386 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4387 if (C->getZExtValue() == 0) // 0 >>u V -> 0.
4388 return N->getOperand(0);
4392 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4393 if (C->getZExtValue() == 0 || // 0 >>s V -> 0.
4394 C->isAllOnesValue()) // -1 >>s V -> -1.
4395 return N->getOperand(0);
4399 case ISD::SINT_TO_FP:
4400 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
4401 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
4402 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
4403 // We allow the src/dst to be either f32/f64, but the intermediate
4404 // type must be i64.
4405 if (N->getOperand(0).getValueType() == MVT::i64 &&
4406 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
4407 SDValue Val = N->getOperand(0).getOperand(0);
4408 if (Val.getValueType() == MVT::f32) {
4409 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
4410 DCI.AddToWorklist(Val.getNode());
4413 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
4414 DCI.AddToWorklist(Val.getNode());
4415 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
4416 DCI.AddToWorklist(Val.getNode());
4417 if (N->getValueType(0) == MVT::f32) {
4418 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
4419 DAG.getIntPtrConstant(0));
4420 DCI.AddToWorklist(Val.getNode());
4423 } else if (N->getOperand(0).getValueType() == MVT::i32) {
4424 // If the intermediate type is i32, we can avoid the load/store here
4431 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
4432 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
4433 !cast<StoreSDNode>(N)->isTruncatingStore() &&
4434 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
4435 N->getOperand(1).getValueType() == MVT::i32 &&
4436 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
4437 SDValue Val = N->getOperand(1).getOperand(0);
4438 if (Val.getValueType() == MVT::f32) {
4439 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
4440 DCI.AddToWorklist(Val.getNode());
4442 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
4443 DCI.AddToWorklist(Val.getNode());
4445 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
4446 N->getOperand(2), N->getOperand(3));
4447 DCI.AddToWorklist(Val.getNode());
4451 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
4452 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
4453 N->getOperand(1).getNode()->hasOneUse() &&
4454 (N->getOperand(1).getValueType() == MVT::i32 ||
4455 N->getOperand(1).getValueType() == MVT::i16)) {
4456 SDValue BSwapOp = N->getOperand(1).getOperand(0);
4457 // Do an any-extend to 32-bits if this is a half-word input.
4458 if (BSwapOp.getValueType() == MVT::i16)
4459 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
4461 return DAG.getNode(PPCISD::STBRX, dl, MVT::Other, N->getOperand(0),
4462 BSwapOp, N->getOperand(2), N->getOperand(3),
4463 DAG.getValueType(N->getOperand(1).getValueType()));
4467 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
4468 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
4469 N->getOperand(0).hasOneUse() &&
4470 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
4471 SDValue Load = N->getOperand(0);
4472 LoadSDNode *LD = cast<LoadSDNode>(Load);
4473 // Create the byte-swapping load.
4474 std::vector<MVT> VTs;
4475 VTs.push_back(MVT::i32);
4476 VTs.push_back(MVT::Other);
4477 SDValue MO = DAG.getMemOperand(LD->getMemOperand());
4479 LD->getChain(), // Chain
4480 LD->getBasePtr(), // Ptr
4482 DAG.getValueType(N->getValueType(0)) // VT
4484 SDValue BSLoad = DAG.getNode(PPCISD::LBRX, dl, VTs, Ops, 4);
4486 // If this is an i16 load, insert the truncate.
4487 SDValue ResVal = BSLoad;
4488 if (N->getValueType(0) == MVT::i16)
4489 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
4491 // First, combine the bswap away. This makes the value produced by the
4493 DCI.CombineTo(N, ResVal);
4495 // Next, combine the load away, we give it a bogus result value but a real
4496 // chain result. The result value is dead because the bswap is dead.
4497 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
4499 // Return N so it doesn't get rechecked!
4500 return SDValue(N, 0);
4504 case PPCISD::VCMP: {
4505 // If a VCMPo node already exists with exactly the same operands as this
4506 // node, use its result instead of this node (VCMPo computes both a CR6 and
4507 // a normal output).
4509 if (!N->getOperand(0).hasOneUse() &&
4510 !N->getOperand(1).hasOneUse() &&
4511 !N->getOperand(2).hasOneUse()) {
4513 // Scan all of the users of the LHS, looking for VCMPo's that match.
4514 SDNode *VCMPoNode = 0;
4516 SDNode *LHSN = N->getOperand(0).getNode();
4517 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
4519 if (UI->getOpcode() == PPCISD::VCMPo &&
4520 UI->getOperand(1) == N->getOperand(1) &&
4521 UI->getOperand(2) == N->getOperand(2) &&
4522 UI->getOperand(0) == N->getOperand(0)) {
4527 // If there is no VCMPo node, or if the flag value has a single use, don't
4529 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
4532 // Look at the (necessarily single) use of the flag value. If it has a
4533 // chain, this transformation is more complex. Note that multiple things
4534 // could use the value result, which we should ignore.
4535 SDNode *FlagUser = 0;
4536 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
4537 FlagUser == 0; ++UI) {
4538 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
4540 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
4541 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
4548 // If the user is a MFCR instruction, we know this is safe. Otherwise we
4549 // give up for right now.
4550 if (FlagUser->getOpcode() == PPCISD::MFCR)
4551 return SDValue(VCMPoNode, 0);
4556 // If this is a branch on an altivec predicate comparison, lower this so
4557 // that we don't have to do a MFCR: instead, branch directly on CR6. This
4558 // lowering is done pre-legalize, because the legalizer lowers the predicate
4559 // compare down to code that is difficult to reassemble.
4560 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
4561 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
4565 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
4566 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
4567 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
4568 assert(isDot && "Can't compare against a vector result!");
4570 // If this is a comparison against something other than 0/1, then we know
4571 // that the condition is never/always true.
4572 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
4573 if (Val != 0 && Val != 1) {
4574 if (CC == ISD::SETEQ) // Cond never true, remove branch.
4575 return N->getOperand(0);
4576 // Always !=, turn it into an unconditional branch.
4577 return DAG.getNode(ISD::BR, dl, MVT::Other,
4578 N->getOperand(0), N->getOperand(4));
4581 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
4583 // Create the PPCISD altivec 'dot' comparison node.
4584 std::vector<MVT> VTs;
4586 LHS.getOperand(2), // LHS of compare
4587 LHS.getOperand(3), // RHS of compare
4588 DAG.getConstant(CompareOpc, MVT::i32)
4590 VTs.push_back(LHS.getOperand(2).getValueType());
4591 VTs.push_back(MVT::Flag);
4592 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
4594 // Unpack the result based on how the target uses it.
4595 PPC::Predicate CompOpc;
4596 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
4597 default: // Can't happen, don't crash on invalid number though.
4598 case 0: // Branch on the value of the EQ bit of CR6.
4599 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
4601 case 1: // Branch on the inverted value of the EQ bit of CR6.
4602 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
4604 case 2: // Branch on the value of the LT bit of CR6.
4605 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
4607 case 3: // Branch on the inverted value of the LT bit of CR6.
4608 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
4612 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
4613 DAG.getConstant(CompOpc, MVT::i32),
4614 DAG.getRegister(PPC::CR6, MVT::i32),
4615 N->getOperand(4), CompNode.getValue(1));
4624 //===----------------------------------------------------------------------===//
4625 // Inline Assembly Support
4626 //===----------------------------------------------------------------------===//
4628 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
4632 const SelectionDAG &DAG,
4633 unsigned Depth) const {
4634 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
4635 switch (Op.getOpcode()) {
4637 case PPCISD::LBRX: {
4638 // lhbrx is known to have the top bits cleared out.
4639 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
4640 KnownZero = 0xFFFF0000;
4643 case ISD::INTRINSIC_WO_CHAIN: {
4644 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
4646 case Intrinsic::ppc_altivec_vcmpbfp_p:
4647 case Intrinsic::ppc_altivec_vcmpeqfp_p:
4648 case Intrinsic::ppc_altivec_vcmpequb_p:
4649 case Intrinsic::ppc_altivec_vcmpequh_p:
4650 case Intrinsic::ppc_altivec_vcmpequw_p:
4651 case Intrinsic::ppc_altivec_vcmpgefp_p:
4652 case Intrinsic::ppc_altivec_vcmpgtfp_p:
4653 case Intrinsic::ppc_altivec_vcmpgtsb_p:
4654 case Intrinsic::ppc_altivec_vcmpgtsh_p:
4655 case Intrinsic::ppc_altivec_vcmpgtsw_p:
4656 case Intrinsic::ppc_altivec_vcmpgtub_p:
4657 case Intrinsic::ppc_altivec_vcmpgtuh_p:
4658 case Intrinsic::ppc_altivec_vcmpgtuw_p:
4659 KnownZero = ~1U; // All bits but the low one are known to be zero.
4667 /// getConstraintType - Given a constraint, return the type of
4668 /// constraint it is for this target.
4669 PPCTargetLowering::ConstraintType
4670 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
4671 if (Constraint.size() == 1) {
4672 switch (Constraint[0]) {
4679 return C_RegisterClass;
4682 return TargetLowering::getConstraintType(Constraint);
4685 std::pair<unsigned, const TargetRegisterClass*>
4686 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
4688 if (Constraint.size() == 1) {
4689 // GCC RS6000 Constraint Letters
4690 switch (Constraint[0]) {
4693 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
4694 return std::make_pair(0U, PPC::G8RCRegisterClass);
4695 return std::make_pair(0U, PPC::GPRCRegisterClass);
4698 return std::make_pair(0U, PPC::F4RCRegisterClass);
4699 else if (VT == MVT::f64)
4700 return std::make_pair(0U, PPC::F8RCRegisterClass);
4703 return std::make_pair(0U, PPC::VRRCRegisterClass);
4705 return std::make_pair(0U, PPC::CRRCRegisterClass);
4709 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4713 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4714 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
4715 /// it means one of the asm constraint of the inline asm instruction being
4716 /// processed is 'm'.
4717 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
4719 std::vector<SDValue>&Ops,
4720 SelectionDAG &DAG) const {
4721 SDValue Result(0,0);
4732 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
4733 if (!CST) return; // Must be an immediate to match.
4734 unsigned Value = CST->getZExtValue();
4736 default: assert(0 && "Unknown constraint letter!");
4737 case 'I': // "I" is a signed 16-bit constant.
4738 if ((short)Value == (int)Value)
4739 Result = DAG.getTargetConstant(Value, Op.getValueType());
4741 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
4742 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
4743 if ((short)Value == 0)
4744 Result = DAG.getTargetConstant(Value, Op.getValueType());
4746 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
4747 if ((Value >> 16) == 0)
4748 Result = DAG.getTargetConstant(Value, Op.getValueType());
4750 case 'M': // "M" is a constant that is greater than 31.
4752 Result = DAG.getTargetConstant(Value, Op.getValueType());
4754 case 'N': // "N" is a positive constant that is an exact power of two.
4755 if ((int)Value > 0 && isPowerOf2_32(Value))
4756 Result = DAG.getTargetConstant(Value, Op.getValueType());
4758 case 'O': // "O" is the constant zero.
4760 Result = DAG.getTargetConstant(Value, Op.getValueType());
4762 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
4763 if ((short)-Value == (int)-Value)
4764 Result = DAG.getTargetConstant(Value, Op.getValueType());
4771 if (Result.getNode()) {
4772 Ops.push_back(Result);
4776 // Handle standard constraint letters.
4777 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, hasMemory, Ops, DAG);
4780 // isLegalAddressingMode - Return true if the addressing mode represented
4781 // by AM is legal for this target, for a load/store of the specified type.
4782 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
4783 const Type *Ty) const {
4784 // FIXME: PPC does not allow r+i addressing modes for vectors!
4786 // PPC allows a sign-extended 16-bit immediate field.
4787 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
4790 // No global is ever allowed as a base.
4794 // PPC only support r+r,
4796 case 0: // "r+i" or just "i", depending on HasBaseReg.
4799 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
4801 // Otherwise we have r+r or r+i.
4804 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
4806 // Allow 2*r as r+r.
4809 // No other scales are supported.
4816 /// isLegalAddressImmediate - Return true if the integer value can be used
4817 /// as the offset of the target addressing mode for load / store of the
4819 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
4820 // PPC allows a sign-extended 16-bit immediate field.
4821 return (V > -(1 << 16) && V < (1 << 16)-1);
4824 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
4828 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
4829 DebugLoc dl = Op.getDebugLoc();
4830 // Depths > 0 not supported yet!
4831 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
4834 MachineFunction &MF = DAG.getMachineFunction();
4835 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4837 // Just load the return address off the stack.
4838 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
4840 // Make sure the function really does not optimize away the store of the RA
4842 FuncInfo->setLRStoreRequired();
4843 return DAG.getLoad(getPointerTy(), dl,
4844 DAG.getEntryNode(), RetAddrFI, NULL, 0);
4847 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
4848 DebugLoc dl = Op.getDebugLoc();
4849 // Depths > 0 not supported yet!
4850 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
4853 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4854 bool isPPC64 = PtrVT == MVT::i64;
4856 MachineFunction &MF = DAG.getMachineFunction();
4857 MachineFrameInfo *MFI = MF.getFrameInfo();
4858 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
4859 && MFI->getStackSize();
4862 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::X31 : PPC::X1,
4865 return DAG.getCopyFromReg(DAG.getEntryNode(), dl, is31 ? PPC::R31 : PPC::R1,
4870 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4871 // The PowerPC target isn't yet aware of offsets.