1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetOptions.h"
40 static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
41 CCValAssign::LocInfo &LocInfo,
42 ISD::ArgFlagsTy &ArgFlags,
44 static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
46 CCValAssign::LocInfo &LocInfo,
47 ISD::ArgFlagsTy &ArgFlags,
49 static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
51 CCValAssign::LocInfo &LocInfo,
52 ISD::ArgFlagsTy &ArgFlags,
55 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
56 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
58 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
59 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
61 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
62 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
64 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
65 if (TM.getSubtargetImpl()->isDarwin())
66 return new TargetLoweringObjectFileMachO();
68 if (TM.getSubtargetImpl()->isSVR4ABI())
69 return new PPC64LinuxTargetObjectFile();
71 return new TargetLoweringObjectFileELF();
74 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
75 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
76 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
77 PPCRegInfo = TM.getRegisterInfo();
78 PPCII = TM.getInstrInfo();
82 // Use _setjmp/_longjmp instead of setjmp/longjmp.
83 setUseUnderscoreSetJmp(true);
84 setUseUnderscoreLongJmp(true);
86 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
87 // arguments are at least 4/8 bytes aligned.
88 bool isPPC64 = Subtarget->isPPC64();
89 setMinStackArgumentAlignment(isPPC64 ? 8:4);
91 // Set up the register classes.
92 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
93 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
94 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
96 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
97 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
98 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
100 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
102 // PowerPC has pre-inc load and store's.
103 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
104 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
105 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
106 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
107 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
108 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
109 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
110 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
111 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
112 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
114 // This is used in the ppcf128->int sequence. Note it has different semantics
115 // from FP_ROUND: that rounds to nearest, this rounds to zero.
116 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
118 // We do not currently implement these libm ops for PowerPC.
119 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
120 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
121 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
122 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
123 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
124 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
126 // PowerPC has no SREM/UREM instructions
127 setOperationAction(ISD::SREM, MVT::i32, Expand);
128 setOperationAction(ISD::UREM, MVT::i32, Expand);
129 setOperationAction(ISD::SREM, MVT::i64, Expand);
130 setOperationAction(ISD::UREM, MVT::i64, Expand);
132 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
133 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
134 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
135 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
136 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
137 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
138 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
139 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
140 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
142 // We don't support sin/cos/sqrt/fmod/pow
143 setOperationAction(ISD::FSIN , MVT::f64, Expand);
144 setOperationAction(ISD::FCOS , MVT::f64, Expand);
145 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
146 setOperationAction(ISD::FREM , MVT::f64, Expand);
147 setOperationAction(ISD::FPOW , MVT::f64, Expand);
148 setOperationAction(ISD::FMA , MVT::f64, Legal);
149 setOperationAction(ISD::FSIN , MVT::f32, Expand);
150 setOperationAction(ISD::FCOS , MVT::f32, Expand);
151 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
152 setOperationAction(ISD::FREM , MVT::f32, Expand);
153 setOperationAction(ISD::FPOW , MVT::f32, Expand);
154 setOperationAction(ISD::FMA , MVT::f32, Legal);
156 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
158 // If we're enabling GP optimizations, use hardware square root
159 if (!Subtarget->hasFSQRT() &&
160 !(TM.Options.UnsafeFPMath &&
161 Subtarget->hasFRSQRTE() && Subtarget->hasFRE()))
162 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
164 if (!Subtarget->hasFSQRT() &&
165 !(TM.Options.UnsafeFPMath &&
166 Subtarget->hasFRSQRTES() && Subtarget->hasFRES()))
167 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
169 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
170 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
172 if (Subtarget->hasFPRND()) {
173 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
174 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
175 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
177 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
178 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
179 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
181 // frin does not implement "ties to even." Thus, this is safe only in
183 if (TM.Options.UnsafeFPMath) {
184 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
185 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
187 // These need to set FE_INEXACT, and use a custom inserter.
188 setOperationAction(ISD::FRINT, MVT::f64, Legal);
189 setOperationAction(ISD::FRINT, MVT::f32, Legal);
193 // PowerPC does not have BSWAP, CTPOP or CTTZ
194 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
195 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
196 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
197 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
198 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
199 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
200 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
201 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
203 if (Subtarget->hasPOPCNTD()) {
204 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
205 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
207 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
208 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
211 // PowerPC does not have ROTR
212 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
213 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
215 // PowerPC does not have Select
216 setOperationAction(ISD::SELECT, MVT::i32, Expand);
217 setOperationAction(ISD::SELECT, MVT::i64, Expand);
218 setOperationAction(ISD::SELECT, MVT::f32, Expand);
219 setOperationAction(ISD::SELECT, MVT::f64, Expand);
221 // PowerPC wants to turn select_cc of FP into fsel when possible.
222 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
223 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
225 // PowerPC wants to optimize integer setcc a bit
226 setOperationAction(ISD::SETCC, MVT::i32, Custom);
228 // PowerPC does not have BRCOND which requires SetCC
229 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
231 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
233 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
234 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
236 // PowerPC does not have [U|S]INT_TO_FP
237 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
238 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
240 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
241 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
242 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
243 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
245 // We cannot sextinreg(i1). Expand to shifts.
246 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
248 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
249 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
250 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
251 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
253 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
254 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
255 // support continuation, user-level threading, and etc.. As a result, no
256 // other SjLj exception interfaces are implemented and please don't build
257 // your own exception handling based on them.
258 // LLVM/Clang supports zero-cost DWARF exception handling.
259 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
260 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
262 // We want to legalize GlobalAddress and ConstantPool nodes into the
263 // appropriate instructions to materialize the address.
264 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
265 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
266 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
267 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
268 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
269 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
270 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
271 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
272 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
273 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
276 setOperationAction(ISD::TRAP, MVT::Other, Legal);
278 // TRAMPOLINE is custom lowered.
279 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
280 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
282 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
283 setOperationAction(ISD::VASTART , MVT::Other, Custom);
285 if (Subtarget->isSVR4ABI()) {
287 // VAARG always uses double-word chunks, so promote anything smaller.
288 setOperationAction(ISD::VAARG, MVT::i1, Promote);
289 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
290 setOperationAction(ISD::VAARG, MVT::i8, Promote);
291 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
292 setOperationAction(ISD::VAARG, MVT::i16, Promote);
293 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
294 setOperationAction(ISD::VAARG, MVT::i32, Promote);
295 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
296 setOperationAction(ISD::VAARG, MVT::Other, Expand);
298 // VAARG is custom lowered with the 32-bit SVR4 ABI.
299 setOperationAction(ISD::VAARG, MVT::Other, Custom);
300 setOperationAction(ISD::VAARG, MVT::i64, Custom);
303 setOperationAction(ISD::VAARG, MVT::Other, Expand);
305 // Use the default implementation.
306 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
307 setOperationAction(ISD::VAEND , MVT::Other, Expand);
308 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
309 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
310 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
311 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
313 // We want to custom lower some of our intrinsics.
314 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
316 // To handle counter-based loop conditions.
317 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
319 // Comparisons that require checking two conditions.
320 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
321 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
322 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
323 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
324 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
325 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
326 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
327 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
328 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
329 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
330 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
331 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
333 if (Subtarget->has64BitSupport()) {
334 // They also have instructions for converting between i64 and fp.
335 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
336 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
337 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
338 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
339 // This is just the low 32 bits of a (signed) fp->i64 conversion.
340 // We cannot do this with Promote because i64 is not a legal type.
341 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
343 if (PPCSubTarget.hasLFIWAX() || Subtarget->isPPC64())
344 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
346 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
347 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
350 // With the instructions enabled under FPCVT, we can do everything.
351 if (PPCSubTarget.hasFPCVT()) {
352 if (Subtarget->has64BitSupport()) {
353 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
354 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
355 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
356 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
359 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
361 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
362 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
365 if (Subtarget->use64BitRegs()) {
366 // 64-bit PowerPC implementations can support i64 types directly
367 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
368 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
369 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
370 // 64-bit PowerPC wants to expand i128 shifts itself.
371 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
372 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
373 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
375 // 32-bit PowerPC wants to expand i64 shifts itself.
376 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
377 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
378 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
381 if (Subtarget->hasAltivec()) {
382 // First set operation action for all vector types to expand. Then we
383 // will selectively turn on ones that can be effectively codegen'd.
384 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
385 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
386 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
388 // add/sub are legal for all supported vector VT's.
389 setOperationAction(ISD::ADD , VT, Legal);
390 setOperationAction(ISD::SUB , VT, Legal);
392 // We promote all shuffles to v16i8.
393 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
394 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
396 // We promote all non-typed operations to v4i32.
397 setOperationAction(ISD::AND , VT, Promote);
398 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
399 setOperationAction(ISD::OR , VT, Promote);
400 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
401 setOperationAction(ISD::XOR , VT, Promote);
402 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
403 setOperationAction(ISD::LOAD , VT, Promote);
404 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
405 setOperationAction(ISD::SELECT, VT, Promote);
406 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
407 setOperationAction(ISD::STORE, VT, Promote);
408 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
410 // No other operations are legal.
411 setOperationAction(ISD::MUL , VT, Expand);
412 setOperationAction(ISD::SDIV, VT, Expand);
413 setOperationAction(ISD::SREM, VT, Expand);
414 setOperationAction(ISD::UDIV, VT, Expand);
415 setOperationAction(ISD::UREM, VT, Expand);
416 setOperationAction(ISD::FDIV, VT, Expand);
417 setOperationAction(ISD::FNEG, VT, Expand);
418 setOperationAction(ISD::FSQRT, VT, Expand);
419 setOperationAction(ISD::FLOG, VT, Expand);
420 setOperationAction(ISD::FLOG10, VT, Expand);
421 setOperationAction(ISD::FLOG2, VT, Expand);
422 setOperationAction(ISD::FEXP, VT, Expand);
423 setOperationAction(ISD::FEXP2, VT, Expand);
424 setOperationAction(ISD::FSIN, VT, Expand);
425 setOperationAction(ISD::FCOS, VT, Expand);
426 setOperationAction(ISD::FABS, VT, Expand);
427 setOperationAction(ISD::FPOWI, VT, Expand);
428 setOperationAction(ISD::FFLOOR, VT, Expand);
429 setOperationAction(ISD::FCEIL, VT, Expand);
430 setOperationAction(ISD::FTRUNC, VT, Expand);
431 setOperationAction(ISD::FRINT, VT, Expand);
432 setOperationAction(ISD::FNEARBYINT, VT, Expand);
433 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
434 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
435 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
436 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
437 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
438 setOperationAction(ISD::UDIVREM, VT, Expand);
439 setOperationAction(ISD::SDIVREM, VT, Expand);
440 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
441 setOperationAction(ISD::FPOW, VT, Expand);
442 setOperationAction(ISD::CTPOP, VT, Expand);
443 setOperationAction(ISD::CTLZ, VT, Expand);
444 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
445 setOperationAction(ISD::CTTZ, VT, Expand);
446 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
447 setOperationAction(ISD::VSELECT, VT, Expand);
448 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
450 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
451 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
452 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
453 setTruncStoreAction(VT, InnerVT, Expand);
455 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
456 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
457 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
460 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
461 // with merges, splats, etc.
462 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
464 setOperationAction(ISD::AND , MVT::v4i32, Legal);
465 setOperationAction(ISD::OR , MVT::v4i32, Legal);
466 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
467 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
468 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
469 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
470 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
471 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
472 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
473 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
474 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
475 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
476 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
477 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
479 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
480 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
481 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
482 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
484 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
485 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
487 if (TM.Options.UnsafeFPMath) {
488 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
489 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
492 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
493 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
494 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
496 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
497 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
499 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
500 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
501 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
502 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
504 // Altivec does not contain unordered floating-point compare instructions
505 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
506 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
507 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
508 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
509 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
510 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
513 if (Subtarget->has64BitSupport()) {
514 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
515 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
518 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
519 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
520 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
521 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
523 setBooleanContents(ZeroOrOneBooleanContent);
524 // Altivec instructions set fields to all zeros or all ones.
525 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
528 setStackPointerRegisterToSaveRestore(PPC::X1);
529 setExceptionPointerRegister(PPC::X3);
530 setExceptionSelectorRegister(PPC::X4);
532 setStackPointerRegisterToSaveRestore(PPC::R1);
533 setExceptionPointerRegister(PPC::R3);
534 setExceptionSelectorRegister(PPC::R4);
537 // We have target-specific dag combine patterns for the following nodes:
538 setTargetDAGCombine(ISD::SINT_TO_FP);
539 setTargetDAGCombine(ISD::LOAD);
540 setTargetDAGCombine(ISD::STORE);
541 setTargetDAGCombine(ISD::BR_CC);
542 setTargetDAGCombine(ISD::BSWAP);
543 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
545 // Use reciprocal estimates.
546 if (TM.Options.UnsafeFPMath) {
547 setTargetDAGCombine(ISD::FDIV);
548 setTargetDAGCombine(ISD::FSQRT);
551 // Darwin long double math library functions have $LDBL128 appended.
552 if (Subtarget->isDarwin()) {
553 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
554 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
555 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
556 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
557 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
558 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
559 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
560 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
561 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
562 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
565 setMinFunctionAlignment(2);
566 if (PPCSubTarget.isDarwin())
567 setPrefFunctionAlignment(4);
569 if (isPPC64 && Subtarget->isJITCodeModel())
570 // Temporary workaround for the inability of PPC64 JIT to handle jump
572 setSupportJumpTables(false);
574 setInsertFencesForAtomic(true);
576 setSchedulingPreference(Sched::Hybrid);
578 computeRegisterProperties();
580 // The Freescale cores does better with aggressive inlining of memcpy and
581 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
582 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
583 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
584 MaxStoresPerMemset = 32;
585 MaxStoresPerMemsetOptSize = 16;
586 MaxStoresPerMemcpy = 32;
587 MaxStoresPerMemcpyOptSize = 8;
588 MaxStoresPerMemmove = 32;
589 MaxStoresPerMemmoveOptSize = 8;
591 setPrefFunctionAlignment(4);
595 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
596 /// function arguments in the caller parameter area.
597 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
598 const TargetMachine &TM = getTargetMachine();
599 // Darwin passes everything on 4 byte boundary.
600 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
603 // 16byte and wider vectors are passed on 16byte boundary.
604 if (VectorType *VTy = dyn_cast<VectorType>(Ty))
605 if (VTy->getBitWidth() >= 128)
608 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
609 if (PPCSubTarget.isPPC64())
615 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
618 case PPCISD::FSEL: return "PPCISD::FSEL";
619 case PPCISD::FCFID: return "PPCISD::FCFID";
620 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
621 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
622 case PPCISD::FRE: return "PPCISD::FRE";
623 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
624 case PPCISD::STFIWX: return "PPCISD::STFIWX";
625 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
626 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
627 case PPCISD::VPERM: return "PPCISD::VPERM";
628 case PPCISD::Hi: return "PPCISD::Hi";
629 case PPCISD::Lo: return "PPCISD::Lo";
630 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
631 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
632 case PPCISD::LOAD: return "PPCISD::LOAD";
633 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
634 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
635 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
636 case PPCISD::SRL: return "PPCISD::SRL";
637 case PPCISD::SRA: return "PPCISD::SRA";
638 case PPCISD::SHL: return "PPCISD::SHL";
639 case PPCISD::CALL: return "PPCISD::CALL";
640 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
641 case PPCISD::MTCTR: return "PPCISD::MTCTR";
642 case PPCISD::BCTRL: return "PPCISD::BCTRL";
643 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
644 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
645 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
646 case PPCISD::MFCR: return "PPCISD::MFCR";
647 case PPCISD::VCMP: return "PPCISD::VCMP";
648 case PPCISD::VCMPo: return "PPCISD::VCMPo";
649 case PPCISD::LBRX: return "PPCISD::LBRX";
650 case PPCISD::STBRX: return "PPCISD::STBRX";
651 case PPCISD::LARX: return "PPCISD::LARX";
652 case PPCISD::STCX: return "PPCISD::STCX";
653 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
654 case PPCISD::BDNZ: return "PPCISD::BDNZ";
655 case PPCISD::BDZ: return "PPCISD::BDZ";
656 case PPCISD::MFFS: return "PPCISD::MFFS";
657 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
658 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
659 case PPCISD::CR6SET: return "PPCISD::CR6SET";
660 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
661 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
662 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
663 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
664 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
665 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
666 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
667 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
668 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
669 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
670 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
671 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
672 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
673 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
674 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
675 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
676 case PPCISD::SC: return "PPCISD::SC";
680 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
683 return VT.changeVectorElementTypeToInteger();
686 //===----------------------------------------------------------------------===//
687 // Node matching predicates, for use by the tblgen matching code.
688 //===----------------------------------------------------------------------===//
690 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
691 static bool isFloatingPointZero(SDValue Op) {
692 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
693 return CFP->getValueAPF().isZero();
694 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
695 // Maybe this has already been legalized into the constant pool?
696 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
697 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
698 return CFP->getValueAPF().isZero();
703 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
704 /// true if Op is undef or if it matches the specified value.
705 static bool isConstantOrUndef(int Op, int Val) {
706 return Op < 0 || Op == Val;
709 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
710 /// VPKUHUM instruction.
711 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
713 for (unsigned i = 0; i != 16; ++i)
714 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
717 for (unsigned i = 0; i != 8; ++i)
718 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
719 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
725 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
726 /// VPKUWUM instruction.
727 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
729 for (unsigned i = 0; i != 16; i += 2)
730 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
731 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
734 for (unsigned i = 0; i != 8; i += 2)
735 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
736 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
737 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
738 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
744 /// isVMerge - Common function, used to match vmrg* shuffles.
746 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
747 unsigned LHSStart, unsigned RHSStart) {
748 assert(N->getValueType(0) == MVT::v16i8 &&
749 "PPC only supports shuffles by bytes!");
750 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
751 "Unsupported merge size!");
753 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
754 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
755 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
756 LHSStart+j+i*UnitSize) ||
757 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
758 RHSStart+j+i*UnitSize))
764 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
765 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
766 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
769 return isVMerge(N, UnitSize, 8, 24);
770 return isVMerge(N, UnitSize, 8, 8);
773 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
774 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
775 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
778 return isVMerge(N, UnitSize, 0, 16);
779 return isVMerge(N, UnitSize, 0, 0);
783 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
784 /// amount, otherwise return -1.
785 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
786 assert(N->getValueType(0) == MVT::v16i8 &&
787 "PPC only supports shuffles by bytes!");
789 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
791 // Find the first non-undef value in the shuffle mask.
793 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
796 if (i == 16) return -1; // all undef.
798 // Otherwise, check to see if the rest of the elements are consecutively
799 // numbered from this value.
800 unsigned ShiftAmt = SVOp->getMaskElt(i);
801 if (ShiftAmt < i) return -1;
805 // Check the rest of the elements to see if they are consecutive.
806 for (++i; i != 16; ++i)
807 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
810 // Check the rest of the elements to see if they are consecutive.
811 for (++i; i != 16; ++i)
812 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
818 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
819 /// specifies a splat of a single element that is suitable for input to
820 /// VSPLTB/VSPLTH/VSPLTW.
821 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
822 assert(N->getValueType(0) == MVT::v16i8 &&
823 (EltSize == 1 || EltSize == 2 || EltSize == 4));
825 // This is a splat operation if each element of the permute is the same, and
826 // if the value doesn't reference the second vector.
827 unsigned ElementBase = N->getMaskElt(0);
829 // FIXME: Handle UNDEF elements too!
830 if (ElementBase >= 16)
833 // Check that the indices are consecutive, in the case of a multi-byte element
834 // splatted with a v16i8 mask.
835 for (unsigned i = 1; i != EltSize; ++i)
836 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
839 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
840 if (N->getMaskElt(i) < 0) continue;
841 for (unsigned j = 0; j != EltSize; ++j)
842 if (N->getMaskElt(i+j) != N->getMaskElt(j))
848 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
850 bool PPC::isAllNegativeZeroVector(SDNode *N) {
851 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
853 APInt APVal, APUndef;
857 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
858 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
859 return CFP->getValueAPF().isNegZero();
864 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
865 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
866 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
867 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
868 assert(isSplatShuffleMask(SVOp, EltSize));
869 return SVOp->getMaskElt(0) / EltSize;
872 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
873 /// by using a vspltis[bhw] instruction of the specified element size, return
874 /// the constant being splatted. The ByteSize field indicates the number of
875 /// bytes of each element [124] -> [bhw].
876 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
879 // If ByteSize of the splat is bigger than the element size of the
880 // build_vector, then we have a case where we are checking for a splat where
881 // multiple elements of the buildvector are folded together into a single
882 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
883 unsigned EltSize = 16/N->getNumOperands();
884 if (EltSize < ByteSize) {
885 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
886 SDValue UniquedVals[4];
887 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
889 // See if all of the elements in the buildvector agree across.
890 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
891 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
892 // If the element isn't a constant, bail fully out.
893 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
896 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
897 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
898 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
899 return SDValue(); // no match.
902 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
903 // either constant or undef values that are identical for each chunk. See
904 // if these chunks can form into a larger vspltis*.
906 // Check to see if all of the leading entries are either 0 or -1. If
907 // neither, then this won't fit into the immediate field.
908 bool LeadingZero = true;
909 bool LeadingOnes = true;
910 for (unsigned i = 0; i != Multiple-1; ++i) {
911 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
913 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
914 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
916 // Finally, check the least significant entry.
918 if (UniquedVals[Multiple-1].getNode() == 0)
919 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
920 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
922 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
925 if (UniquedVals[Multiple-1].getNode() == 0)
926 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
927 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
928 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
929 return DAG.getTargetConstant(Val, MVT::i32);
935 // Check to see if this buildvec has a single non-undef value in its elements.
936 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
937 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
938 if (OpVal.getNode() == 0)
939 OpVal = N->getOperand(i);
940 else if (OpVal != N->getOperand(i))
944 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
946 unsigned ValSizeInBytes = EltSize;
948 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
949 Value = CN->getZExtValue();
950 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
951 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
952 Value = FloatToBits(CN->getValueAPF().convertToFloat());
955 // If the splat value is larger than the element value, then we can never do
956 // this splat. The only case that we could fit the replicated bits into our
957 // immediate field for would be zero, and we prefer to use vxor for it.
958 if (ValSizeInBytes < ByteSize) return SDValue();
960 // If the element value is larger than the splat value, cut it in half and
961 // check to see if the two halves are equal. Continue doing this until we
962 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
963 while (ValSizeInBytes > ByteSize) {
964 ValSizeInBytes >>= 1;
966 // If the top half equals the bottom half, we're still ok.
967 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
968 (Value & ((1 << (8*ValSizeInBytes))-1)))
972 // Properly sign extend the value.
973 int MaskVal = SignExtend32(Value, ByteSize * 8);
975 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
976 if (MaskVal == 0) return SDValue();
978 // Finally, if this value fits in a 5 bit sext field, return it
979 if (SignExtend32<5>(MaskVal) == MaskVal)
980 return DAG.getTargetConstant(MaskVal, MVT::i32);
984 //===----------------------------------------------------------------------===//
985 // Addressing Mode Selection
986 //===----------------------------------------------------------------------===//
988 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
989 /// or 64-bit immediate, and if the value can be accurately represented as a
990 /// sign extension from a 16-bit value. If so, this returns true and the
992 static bool isIntS16Immediate(SDNode *N, short &Imm) {
993 if (N->getOpcode() != ISD::Constant)
996 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
997 if (N->getValueType(0) == MVT::i32)
998 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1000 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1002 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1003 return isIntS16Immediate(Op.getNode(), Imm);
1007 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1008 /// can be represented as an indexed [r+r] operation. Returns false if it
1009 /// can be more efficiently represented with [r+imm].
1010 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1012 SelectionDAG &DAG) const {
1014 if (N.getOpcode() == ISD::ADD) {
1015 if (isIntS16Immediate(N.getOperand(1), imm))
1016 return false; // r+i
1017 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1018 return false; // r+i
1020 Base = N.getOperand(0);
1021 Index = N.getOperand(1);
1023 } else if (N.getOpcode() == ISD::OR) {
1024 if (isIntS16Immediate(N.getOperand(1), imm))
1025 return false; // r+i can fold it if we can.
1027 // If this is an or of disjoint bitfields, we can codegen this as an add
1028 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1030 APInt LHSKnownZero, LHSKnownOne;
1031 APInt RHSKnownZero, RHSKnownOne;
1032 DAG.ComputeMaskedBits(N.getOperand(0),
1033 LHSKnownZero, LHSKnownOne);
1035 if (LHSKnownZero.getBoolValue()) {
1036 DAG.ComputeMaskedBits(N.getOperand(1),
1037 RHSKnownZero, RHSKnownOne);
1038 // If all of the bits are known zero on the LHS or RHS, the add won't
1040 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1041 Base = N.getOperand(0);
1042 Index = N.getOperand(1);
1051 /// Returns true if the address N can be represented by a base register plus
1052 /// a signed 16-bit displacement [r+imm], and if it is not better
1053 /// represented as reg+reg. If Aligned is true, only accept displacements
1054 /// suitable for STD and friends, i.e. multiples of 4.
1055 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1058 bool Aligned) const {
1059 // FIXME dl should come from parent load or store, not from address
1061 // If this can be more profitably realized as r+r, fail.
1062 if (SelectAddressRegReg(N, Disp, Base, DAG))
1065 if (N.getOpcode() == ISD::ADD) {
1067 if (isIntS16Immediate(N.getOperand(1), imm) &&
1068 (!Aligned || (imm & 3) == 0)) {
1069 Disp = DAG.getTargetConstant(imm, N.getValueType());
1070 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1071 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1073 Base = N.getOperand(0);
1075 return true; // [r+i]
1076 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1077 // Match LOAD (ADD (X, Lo(G))).
1078 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1079 && "Cannot handle constant offsets yet!");
1080 Disp = N.getOperand(1).getOperand(0); // The global address.
1081 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1082 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1083 Disp.getOpcode() == ISD::TargetConstantPool ||
1084 Disp.getOpcode() == ISD::TargetJumpTable);
1085 Base = N.getOperand(0);
1086 return true; // [&g+r]
1088 } else if (N.getOpcode() == ISD::OR) {
1090 if (isIntS16Immediate(N.getOperand(1), imm) &&
1091 (!Aligned || (imm & 3) == 0)) {
1092 // If this is an or of disjoint bitfields, we can codegen this as an add
1093 // (for better address arithmetic) if the LHS and RHS of the OR are
1094 // provably disjoint.
1095 APInt LHSKnownZero, LHSKnownOne;
1096 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1098 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1099 // If all of the bits are known zero on the LHS or RHS, the add won't
1101 Base = N.getOperand(0);
1102 Disp = DAG.getTargetConstant(imm, N.getValueType());
1106 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1107 // Loading from a constant address.
1109 // If this address fits entirely in a 16-bit sext immediate field, codegen
1112 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1113 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1114 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1115 CN->getValueType(0));
1119 // Handle 32-bit sext immediates with LIS + addr mode.
1120 if ((CN->getValueType(0) == MVT::i32 ||
1121 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1122 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1123 int Addr = (int)CN->getZExtValue();
1125 // Otherwise, break this down into an LIS + disp.
1126 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1128 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1129 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1130 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1135 Disp = DAG.getTargetConstant(0, getPointerTy());
1136 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1137 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1140 return true; // [r+0]
1143 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1144 /// represented as an indexed [r+r] operation.
1145 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1147 SelectionDAG &DAG) const {
1148 // Check to see if we can easily represent this as an [r+r] address. This
1149 // will fail if it thinks that the address is more profitably represented as
1150 // reg+imm, e.g. where imm = 0.
1151 if (SelectAddressRegReg(N, Base, Index, DAG))
1154 // If the operand is an addition, always emit this as [r+r], since this is
1155 // better (for code size, and execution, as the memop does the add for free)
1156 // than emitting an explicit add.
1157 if (N.getOpcode() == ISD::ADD) {
1158 Base = N.getOperand(0);
1159 Index = N.getOperand(1);
1163 // Otherwise, do it the hard way, using R0 as the base register.
1164 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1170 /// getPreIndexedAddressParts - returns true by value, base pointer and
1171 /// offset pointer and addressing mode by reference if the node's address
1172 /// can be legally represented as pre-indexed load / store address.
1173 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1175 ISD::MemIndexedMode &AM,
1176 SelectionDAG &DAG) const {
1177 if (DisablePPCPreinc) return false;
1183 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1184 Ptr = LD->getBasePtr();
1185 VT = LD->getMemoryVT();
1186 Alignment = LD->getAlignment();
1187 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1188 Ptr = ST->getBasePtr();
1189 VT = ST->getMemoryVT();
1190 Alignment = ST->getAlignment();
1195 // PowerPC doesn't have preinc load/store instructions for vectors.
1199 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1201 // Common code will reject creating a pre-inc form if the base pointer
1202 // is a frame index, or if N is a store and the base pointer is either
1203 // the same as or a predecessor of the value being stored. Check for
1204 // those situations here, and try with swapped Base/Offset instead.
1207 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1210 SDValue Val = cast<StoreSDNode>(N)->getValue();
1211 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1216 std::swap(Base, Offset);
1222 // LDU/STU can only handle immediates that are a multiple of 4.
1223 if (VT != MVT::i64) {
1224 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1227 // LDU/STU need an address with at least 4-byte alignment.
1231 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1235 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1236 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1237 // sext i32 to i64 when addr mode is r+i.
1238 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1239 LD->getExtensionType() == ISD::SEXTLOAD &&
1240 isa<ConstantSDNode>(Offset))
1248 //===----------------------------------------------------------------------===//
1249 // LowerOperation implementation
1250 //===----------------------------------------------------------------------===//
1252 /// GetLabelAccessInfo - Return true if we should reference labels using a
1253 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1254 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1255 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1256 HiOpFlags = PPCII::MO_HA16;
1257 LoOpFlags = PPCII::MO_LO16;
1259 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1260 // non-darwin platform. We don't support PIC on other platforms yet.
1261 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1262 TM.getSubtarget<PPCSubtarget>().isDarwin();
1264 HiOpFlags |= PPCII::MO_PIC_FLAG;
1265 LoOpFlags |= PPCII::MO_PIC_FLAG;
1268 // If this is a reference to a global value that requires a non-lazy-ptr, make
1269 // sure that instruction lowering adds it.
1270 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1271 HiOpFlags |= PPCII::MO_NLP_FLAG;
1272 LoOpFlags |= PPCII::MO_NLP_FLAG;
1274 if (GV->hasHiddenVisibility()) {
1275 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1276 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1283 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1284 SelectionDAG &DAG) {
1285 EVT PtrVT = HiPart.getValueType();
1286 SDValue Zero = DAG.getConstant(0, PtrVT);
1289 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1290 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1292 // With PIC, the first instruction is actually "GR+hi(&G)".
1294 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1295 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1297 // Generate non-pic code that has direct accesses to the constant pool.
1298 // The address of the global is just (hi(&g)+lo(&g)).
1299 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1302 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1303 SelectionDAG &DAG) const {
1304 EVT PtrVT = Op.getValueType();
1305 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1306 const Constant *C = CP->getConstVal();
1308 // 64-bit SVR4 ABI code is always position-independent.
1309 // The actual address of the GlobalValue is stored in the TOC.
1310 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1311 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1312 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1313 DAG.getRegister(PPC::X2, MVT::i64));
1316 unsigned MOHiFlag, MOLoFlag;
1317 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1319 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1321 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1322 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1325 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1326 EVT PtrVT = Op.getValueType();
1327 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1329 // 64-bit SVR4 ABI code is always position-independent.
1330 // The actual address of the GlobalValue is stored in the TOC.
1331 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1332 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1333 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1334 DAG.getRegister(PPC::X2, MVT::i64));
1337 unsigned MOHiFlag, MOLoFlag;
1338 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1339 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1340 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1341 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1344 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1345 SelectionDAG &DAG) const {
1346 EVT PtrVT = Op.getValueType();
1348 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1350 unsigned MOHiFlag, MOLoFlag;
1351 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1352 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1353 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1354 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1357 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1358 SelectionDAG &DAG) const {
1360 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1362 const GlobalValue *GV = GA->getGlobal();
1363 EVT PtrVT = getPointerTy();
1364 bool is64bit = PPCSubTarget.isPPC64();
1366 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1368 if (Model == TLSModel::LocalExec) {
1369 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1370 PPCII::MO_TPREL16_HA);
1371 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1372 PPCII::MO_TPREL16_LO);
1373 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1374 is64bit ? MVT::i64 : MVT::i32);
1375 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1376 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1380 llvm_unreachable("only local-exec is currently supported for ppc32");
1382 if (Model == TLSModel::InitialExec) {
1383 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1384 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1385 SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1386 PtrVT, GOTReg, TGA);
1387 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1388 PtrVT, TGA, TPOffsetHi);
1389 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGA);
1392 if (Model == TLSModel::GeneralDynamic) {
1393 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1394 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1395 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1397 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1400 // We need a chain node, and don't have one handy. The underlying
1401 // call has no side effects, so using the function entry node
1403 SDValue Chain = DAG.getEntryNode();
1404 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1405 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1406 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1407 PtrVT, ParmReg, TGA);
1408 // The return value from GET_TLS_ADDR really is in X3 already, but
1409 // some hacks are needed here to tie everything together. The extra
1410 // copies dissolve during subsequent transforms.
1411 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1412 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1415 if (Model == TLSModel::LocalDynamic) {
1416 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1417 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1418 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1420 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1423 // We need a chain node, and don't have one handy. The underlying
1424 // call has no side effects, so using the function entry node
1426 SDValue Chain = DAG.getEntryNode();
1427 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1428 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1429 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1430 PtrVT, ParmReg, TGA);
1431 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1432 // some hacks are needed here to tie everything together. The extra
1433 // copies dissolve during subsequent transforms.
1434 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1435 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1436 Chain, ParmReg, TGA);
1437 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1440 llvm_unreachable("Unknown TLS model!");
1443 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1444 SelectionDAG &DAG) const {
1445 EVT PtrVT = Op.getValueType();
1446 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1448 const GlobalValue *GV = GSDN->getGlobal();
1450 // 64-bit SVR4 ABI code is always position-independent.
1451 // The actual address of the GlobalValue is stored in the TOC.
1452 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1453 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1454 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1455 DAG.getRegister(PPC::X2, MVT::i64));
1458 unsigned MOHiFlag, MOLoFlag;
1459 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1462 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1464 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1466 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1468 // If the global reference is actually to a non-lazy-pointer, we have to do an
1469 // extra load to get the address of the global.
1470 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1471 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1472 false, false, false, 0);
1476 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1477 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1480 // If we're comparing for equality to zero, expose the fact that this is
1481 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1482 // fold the new nodes.
1483 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1484 if (C->isNullValue() && CC == ISD::SETEQ) {
1485 EVT VT = Op.getOperand(0).getValueType();
1486 SDValue Zext = Op.getOperand(0);
1487 if (VT.bitsLT(MVT::i32)) {
1489 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1491 unsigned Log2b = Log2_32(VT.getSizeInBits());
1492 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1493 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1494 DAG.getConstant(Log2b, MVT::i32));
1495 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1497 // Leave comparisons against 0 and -1 alone for now, since they're usually
1498 // optimized. FIXME: revisit this when we can custom lower all setcc
1500 if (C->isAllOnesValue() || C->isNullValue())
1504 // If we have an integer seteq/setne, turn it into a compare against zero
1505 // by xor'ing the rhs with the lhs, which is faster than setting a
1506 // condition register, reading it back out, and masking the correct bit. The
1507 // normal approach here uses sub to do this instead of xor. Using xor exposes
1508 // the result to other bit-twiddling opportunities.
1509 EVT LHSVT = Op.getOperand(0).getValueType();
1510 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1511 EVT VT = Op.getValueType();
1512 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1514 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1519 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1520 const PPCSubtarget &Subtarget) const {
1521 SDNode *Node = Op.getNode();
1522 EVT VT = Node->getValueType(0);
1523 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1524 SDValue InChain = Node->getOperand(0);
1525 SDValue VAListPtr = Node->getOperand(1);
1526 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1529 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1532 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1533 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1535 InChain = GprIndex.getValue(1);
1537 if (VT == MVT::i64) {
1538 // Check if GprIndex is even
1539 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1540 DAG.getConstant(1, MVT::i32));
1541 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1542 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1543 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1544 DAG.getConstant(1, MVT::i32));
1545 // Align GprIndex to be even if it isn't
1546 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1550 // fpr index is 1 byte after gpr
1551 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1552 DAG.getConstant(1, MVT::i32));
1555 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1556 FprPtr, MachinePointerInfo(SV), MVT::i8,
1558 InChain = FprIndex.getValue(1);
1560 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1561 DAG.getConstant(8, MVT::i32));
1563 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1564 DAG.getConstant(4, MVT::i32));
1567 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1568 MachinePointerInfo(), false, false,
1570 InChain = OverflowArea.getValue(1);
1572 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1573 MachinePointerInfo(), false, false,
1575 InChain = RegSaveArea.getValue(1);
1577 // select overflow_area if index > 8
1578 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1579 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1581 // adjustment constant gpr_index * 4/8
1582 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1583 VT.isInteger() ? GprIndex : FprIndex,
1584 DAG.getConstant(VT.isInteger() ? 4 : 8,
1587 // OurReg = RegSaveArea + RegConstant
1588 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1591 // Floating types are 32 bytes into RegSaveArea
1592 if (VT.isFloatingPoint())
1593 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1594 DAG.getConstant(32, MVT::i32));
1596 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1597 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1598 VT.isInteger() ? GprIndex : FprIndex,
1599 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1602 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1603 VT.isInteger() ? VAListPtr : FprPtr,
1604 MachinePointerInfo(SV),
1605 MVT::i8, false, false, 0);
1607 // determine if we should load from reg_save_area or overflow_area
1608 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1610 // increase overflow_area by 4/8 if gpr/fpr > 8
1611 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1612 DAG.getConstant(VT.isInteger() ? 4 : 8,
1615 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1618 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1620 MachinePointerInfo(),
1621 MVT::i32, false, false, 0);
1623 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1624 false, false, false, 0);
1627 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1628 SelectionDAG &DAG) const {
1629 return Op.getOperand(0);
1632 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1633 SelectionDAG &DAG) const {
1634 SDValue Chain = Op.getOperand(0);
1635 SDValue Trmp = Op.getOperand(1); // trampoline
1636 SDValue FPtr = Op.getOperand(2); // nested function
1637 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1640 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1641 bool isPPC64 = (PtrVT == MVT::i64);
1643 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1646 TargetLowering::ArgListTy Args;
1647 TargetLowering::ArgListEntry Entry;
1649 Entry.Ty = IntPtrTy;
1650 Entry.Node = Trmp; Args.push_back(Entry);
1652 // TrampSize == (isPPC64 ? 48 : 40);
1653 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1654 isPPC64 ? MVT::i64 : MVT::i32);
1655 Args.push_back(Entry);
1657 Entry.Node = FPtr; Args.push_back(Entry);
1658 Entry.Node = Nest; Args.push_back(Entry);
1660 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1661 TargetLowering::CallLoweringInfo CLI(Chain,
1662 Type::getVoidTy(*DAG.getContext()),
1663 false, false, false, false, 0,
1665 /*isTailCall=*/false,
1666 /*doesNotRet=*/false,
1667 /*isReturnValueUsed=*/true,
1668 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1670 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1672 return CallResult.second;
1675 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1676 const PPCSubtarget &Subtarget) const {
1677 MachineFunction &MF = DAG.getMachineFunction();
1678 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1682 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1683 // vastart just stores the address of the VarArgsFrameIndex slot into the
1684 // memory location argument.
1685 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1686 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1687 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1688 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1689 MachinePointerInfo(SV),
1693 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1694 // We suppose the given va_list is already allocated.
1697 // char gpr; /* index into the array of 8 GPRs
1698 // * stored in the register save area
1699 // * gpr=0 corresponds to r3,
1700 // * gpr=1 to r4, etc.
1702 // char fpr; /* index into the array of 8 FPRs
1703 // * stored in the register save area
1704 // * fpr=0 corresponds to f1,
1705 // * fpr=1 to f2, etc.
1707 // char *overflow_arg_area;
1708 // /* location on stack that holds
1709 // * the next overflow argument
1711 // char *reg_save_area;
1712 // /* where r3:r10 and f1:f8 (if saved)
1718 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1719 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1722 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1724 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1726 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1729 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1730 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1732 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1733 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1735 uint64_t FPROffset = 1;
1736 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1738 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1740 // Store first byte : number of int regs
1741 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1743 MachinePointerInfo(SV),
1744 MVT::i8, false, false, 0);
1745 uint64_t nextOffset = FPROffset;
1746 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1749 // Store second byte : number of float regs
1750 SDValue secondStore =
1751 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1752 MachinePointerInfo(SV, nextOffset), MVT::i8,
1754 nextOffset += StackOffset;
1755 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1757 // Store second word : arguments given on stack
1758 SDValue thirdStore =
1759 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1760 MachinePointerInfo(SV, nextOffset),
1762 nextOffset += FrameOffset;
1763 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1765 // Store third word : arguments given in registers
1766 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1767 MachinePointerInfo(SV, nextOffset),
1772 #include "PPCGenCallingConv.inc"
1774 static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1775 CCValAssign::LocInfo &LocInfo,
1776 ISD::ArgFlagsTy &ArgFlags,
1781 static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1783 CCValAssign::LocInfo &LocInfo,
1784 ISD::ArgFlagsTy &ArgFlags,
1786 static const uint16_t ArgRegs[] = {
1787 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1788 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1790 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1792 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1794 // Skip one register if the first unallocated register has an even register
1795 // number and there are still argument registers available which have not been
1796 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1797 // need to skip a register if RegNum is odd.
1798 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1799 State.AllocateReg(ArgRegs[RegNum]);
1802 // Always return false here, as this function only makes sure that the first
1803 // unallocated register has an odd register number and does not actually
1804 // allocate a register for the current argument.
1808 static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1810 CCValAssign::LocInfo &LocInfo,
1811 ISD::ArgFlagsTy &ArgFlags,
1813 static const uint16_t ArgRegs[] = {
1814 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1818 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1820 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1822 // If there is only one Floating-point register left we need to put both f64
1823 // values of a split ppc_fp128 value on the stack.
1824 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1825 State.AllocateReg(ArgRegs[RegNum]);
1828 // Always return false here, as this function only makes sure that the two f64
1829 // values a ppc_fp128 value is split into are both passed in registers or both
1830 // passed on the stack and does not actually allocate a register for the
1831 // current argument.
1835 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1837 static const uint16_t *GetFPR() {
1838 static const uint16_t FPR[] = {
1839 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1840 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1846 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1848 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1849 unsigned PtrByteSize) {
1850 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1851 if (Flags.isByVal())
1852 ArgSize = Flags.getByValSize();
1853 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1859 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1860 CallingConv::ID CallConv, bool isVarArg,
1861 const SmallVectorImpl<ISD::InputArg>
1863 SDLoc dl, SelectionDAG &DAG,
1864 SmallVectorImpl<SDValue> &InVals)
1866 if (PPCSubTarget.isSVR4ABI()) {
1867 if (PPCSubTarget.isPPC64())
1868 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
1871 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
1874 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1880 PPCTargetLowering::LowerFormalArguments_32SVR4(
1882 CallingConv::ID CallConv, bool isVarArg,
1883 const SmallVectorImpl<ISD::InputArg>
1885 SDLoc dl, SelectionDAG &DAG,
1886 SmallVectorImpl<SDValue> &InVals) const {
1888 // 32-bit SVR4 ABI Stack Frame Layout:
1889 // +-----------------------------------+
1890 // +--> | Back chain |
1891 // | +-----------------------------------+
1892 // | | Floating-point register save area |
1893 // | +-----------------------------------+
1894 // | | General register save area |
1895 // | +-----------------------------------+
1896 // | | CR save word |
1897 // | +-----------------------------------+
1898 // | | VRSAVE save word |
1899 // | +-----------------------------------+
1900 // | | Alignment padding |
1901 // | +-----------------------------------+
1902 // | | Vector register save area |
1903 // | +-----------------------------------+
1904 // | | Local variable space |
1905 // | +-----------------------------------+
1906 // | | Parameter list area |
1907 // | +-----------------------------------+
1908 // | | LR save word |
1909 // | +-----------------------------------+
1910 // SP--> +--- | Back chain |
1911 // +-----------------------------------+
1914 // System V Application Binary Interface PowerPC Processor Supplement
1915 // AltiVec Technology Programming Interface Manual
1917 MachineFunction &MF = DAG.getMachineFunction();
1918 MachineFrameInfo *MFI = MF.getFrameInfo();
1919 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1921 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1922 // Potential tail calls could cause overwriting of argument stack slots.
1923 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1924 (CallConv == CallingConv::Fast));
1925 unsigned PtrByteSize = 4;
1927 // Assign locations to all of the incoming arguments.
1928 SmallVector<CCValAssign, 16> ArgLocs;
1929 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1930 getTargetMachine(), ArgLocs, *DAG.getContext());
1932 // Reserve space for the linkage area on the stack.
1933 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
1935 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
1937 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1938 CCValAssign &VA = ArgLocs[i];
1940 // Arguments stored in registers.
1941 if (VA.isRegLoc()) {
1942 const TargetRegisterClass *RC;
1943 EVT ValVT = VA.getValVT();
1945 switch (ValVT.getSimpleVT().SimpleTy) {
1947 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1949 RC = &PPC::GPRCRegClass;
1952 RC = &PPC::F4RCRegClass;
1955 RC = &PPC::F8RCRegClass;
1961 RC = &PPC::VRRCRegClass;
1965 // Transform the arguments stored in physical registers into virtual ones.
1966 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1967 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1969 InVals.push_back(ArgValue);
1971 // Argument stored in memory.
1972 assert(VA.isMemLoc());
1974 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1975 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1978 // Create load nodes to retrieve arguments from the stack.
1979 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1980 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1981 MachinePointerInfo(),
1982 false, false, false, 0));
1986 // Assign locations to all of the incoming aggregate by value arguments.
1987 // Aggregates passed by value are stored in the local variable space of the
1988 // caller's stack frame, right above the parameter list area.
1989 SmallVector<CCValAssign, 16> ByValArgLocs;
1990 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1991 getTargetMachine(), ByValArgLocs, *DAG.getContext());
1993 // Reserve stack space for the allocations in CCInfo.
1994 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1996 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
1998 // Area that is at least reserved in the caller of this function.
1999 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2001 // Set the size that is at least reserved in caller of this function. Tail
2002 // call optimized function's reserved stack space needs to be aligned so that
2003 // taking the difference between two stack areas will result in an aligned
2005 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2008 std::max(MinReservedArea,
2009 PPCFrameLowering::getMinCallFrameSize(false, false));
2011 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2012 getStackAlignment();
2013 unsigned AlignMask = TargetAlign-1;
2014 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2016 FI->setMinReservedArea(MinReservedArea);
2018 SmallVector<SDValue, 8> MemOps;
2020 // If the function takes variable number of arguments, make a frame index for
2021 // the start of the first vararg value... for expansion of llvm.va_start.
2023 static const uint16_t GPArgRegs[] = {
2024 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2025 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2027 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2029 static const uint16_t FPArgRegs[] = {
2030 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2033 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2035 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2037 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2040 // Make room for NumGPArgRegs and NumFPArgRegs.
2041 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2042 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2044 FuncInfo->setVarArgsStackOffset(
2045 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2046 CCInfo.getNextStackOffset(), true));
2048 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2049 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2051 // The fixed integer arguments of a variadic function are stored to the
2052 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2053 // the result of va_next.
2054 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2055 // Get an existing live-in vreg, or add a new one.
2056 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2058 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2060 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2061 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2062 MachinePointerInfo(), false, false, 0);
2063 MemOps.push_back(Store);
2064 // Increment the address by four for the next argument to store
2065 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2066 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2069 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2071 // The double arguments are stored to the VarArgsFrameIndex
2073 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2074 // Get an existing live-in vreg, or add a new one.
2075 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2077 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2079 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2080 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2081 MachinePointerInfo(), false, false, 0);
2082 MemOps.push_back(Store);
2083 // Increment the address by eight for the next argument to store
2084 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2086 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2090 if (!MemOps.empty())
2091 Chain = DAG.getNode(ISD::TokenFactor, dl,
2092 MVT::Other, &MemOps[0], MemOps.size());
2097 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2098 // value to MVT::i64 and then truncate to the correct register size.
2100 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2101 SelectionDAG &DAG, SDValue ArgVal,
2104 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2105 DAG.getValueType(ObjectVT));
2106 else if (Flags.isZExt())
2107 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2108 DAG.getValueType(ObjectVT));
2110 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2113 // Set the size that is at least reserved in caller of this function. Tail
2114 // call optimized functions' reserved stack space needs to be aligned so that
2115 // taking the difference between two stack areas will result in an aligned
2118 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2119 unsigned nAltivecParamsAtEnd,
2120 unsigned MinReservedArea,
2121 bool isPPC64) const {
2122 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2123 // Add the Altivec parameters at the end, if needed.
2124 if (nAltivecParamsAtEnd) {
2125 MinReservedArea = ((MinReservedArea+15)/16)*16;
2126 MinReservedArea += 16*nAltivecParamsAtEnd;
2129 std::max(MinReservedArea,
2130 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2131 unsigned TargetAlign
2132 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2133 getStackAlignment();
2134 unsigned AlignMask = TargetAlign-1;
2135 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2136 FI->setMinReservedArea(MinReservedArea);
2140 PPCTargetLowering::LowerFormalArguments_64SVR4(
2142 CallingConv::ID CallConv, bool isVarArg,
2143 const SmallVectorImpl<ISD::InputArg>
2145 SDLoc dl, SelectionDAG &DAG,
2146 SmallVectorImpl<SDValue> &InVals) const {
2147 // TODO: add description of PPC stack frame format, or at least some docs.
2149 MachineFunction &MF = DAG.getMachineFunction();
2150 MachineFrameInfo *MFI = MF.getFrameInfo();
2151 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2153 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2154 // Potential tail calls could cause overwriting of argument stack slots.
2155 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2156 (CallConv == CallingConv::Fast));
2157 unsigned PtrByteSize = 8;
2159 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2160 // Area that is at least reserved in caller of this function.
2161 unsigned MinReservedArea = ArgOffset;
2163 static const uint16_t GPR[] = {
2164 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2165 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2168 static const uint16_t *FPR = GetFPR();
2170 static const uint16_t VR[] = {
2171 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2172 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2175 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2176 const unsigned Num_FPR_Regs = 13;
2177 const unsigned Num_VR_Regs = array_lengthof(VR);
2179 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2181 // Add DAG nodes to load the arguments or copy them out of registers. On
2182 // entry to a function on PPC, the arguments start after the linkage area,
2183 // although the first ones are often in registers.
2185 SmallVector<SDValue, 8> MemOps;
2186 unsigned nAltivecParamsAtEnd = 0;
2187 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2188 unsigned CurArgIdx = 0;
2189 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2191 bool needsLoad = false;
2192 EVT ObjectVT = Ins[ArgNo].VT;
2193 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2194 unsigned ArgSize = ObjSize;
2195 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2196 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2197 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2199 unsigned CurArgOffset = ArgOffset;
2201 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2202 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2203 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2205 MinReservedArea = ((MinReservedArea+15)/16)*16;
2206 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2210 nAltivecParamsAtEnd++;
2212 // Calculate min reserved area.
2213 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2217 // FIXME the codegen can be much improved in some cases.
2218 // We do not have to keep everything in memory.
2219 if (Flags.isByVal()) {
2220 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2221 ObjSize = Flags.getByValSize();
2222 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2223 // Empty aggregate parameters do not take up registers. Examples:
2227 // etc. However, we have to provide a place-holder in InVals, so
2228 // pretend we have an 8-byte item at the current address for that
2231 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2232 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2233 InVals.push_back(FIN);
2236 // All aggregates smaller than 8 bytes must be passed right-justified.
2237 if (ObjSize < PtrByteSize)
2238 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2239 // The value of the object is its address.
2240 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2241 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2242 InVals.push_back(FIN);
2245 if (GPR_idx != Num_GPR_Regs) {
2246 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2247 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2250 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2251 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2252 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2253 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2254 MachinePointerInfo(FuncArg, CurArgOffset),
2255 ObjType, false, false, 0);
2257 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2258 // store the whole register as-is to the parameter save area
2259 // slot. The address of the parameter was already calculated
2260 // above (InVals.push_back(FIN)) to be the right-justified
2261 // offset within the slot. For this store, we need a new
2262 // frame index that points at the beginning of the slot.
2263 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2264 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2265 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2266 MachinePointerInfo(FuncArg, ArgOffset),
2270 MemOps.push_back(Store);
2273 // Whether we copied from a register or not, advance the offset
2274 // into the parameter save area by a full doubleword.
2275 ArgOffset += PtrByteSize;
2279 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2280 // Store whatever pieces of the object are in registers
2281 // to memory. ArgOffset will be the address of the beginning
2283 if (GPR_idx != Num_GPR_Regs) {
2285 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2286 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2287 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2288 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2289 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2290 MachinePointerInfo(FuncArg, ArgOffset),
2292 MemOps.push_back(Store);
2294 ArgOffset += PtrByteSize;
2296 ArgOffset += ArgSize - j;
2303 switch (ObjectVT.getSimpleVT().SimpleTy) {
2304 default: llvm_unreachable("Unhandled argument type!");
2307 if (GPR_idx != Num_GPR_Regs) {
2308 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2309 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2311 if (ObjectVT == MVT::i32)
2312 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2313 // value to MVT::i64 and then truncate to the correct register size.
2314 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2319 ArgSize = PtrByteSize;
2326 // Every 8 bytes of argument space consumes one of the GPRs available for
2327 // argument passing.
2328 if (GPR_idx != Num_GPR_Regs) {
2331 if (FPR_idx != Num_FPR_Regs) {
2334 if (ObjectVT == MVT::f32)
2335 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2337 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2339 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2343 ArgSize = PtrByteSize;
2352 // Note that vector arguments in registers don't reserve stack space,
2353 // except in varargs functions.
2354 if (VR_idx != Num_VR_Regs) {
2355 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2356 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2358 while ((ArgOffset % 16) != 0) {
2359 ArgOffset += PtrByteSize;
2360 if (GPR_idx != Num_GPR_Regs)
2364 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2368 // Vectors are aligned.
2369 ArgOffset = ((ArgOffset+15)/16)*16;
2370 CurArgOffset = ArgOffset;
2377 // We need to load the argument to a virtual register if we determined
2378 // above that we ran out of physical registers of the appropriate type.
2380 int FI = MFI->CreateFixedObject(ObjSize,
2381 CurArgOffset + (ArgSize - ObjSize),
2383 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2384 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2385 false, false, false, 0);
2388 InVals.push_back(ArgVal);
2391 // Set the size that is at least reserved in caller of this function. Tail
2392 // call optimized functions' reserved stack space needs to be aligned so that
2393 // taking the difference between two stack areas will result in an aligned
2395 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2397 // If the function takes variable number of arguments, make a frame index for
2398 // the start of the first vararg value... for expansion of llvm.va_start.
2400 int Depth = ArgOffset;
2402 FuncInfo->setVarArgsFrameIndex(
2403 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2404 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2406 // If this function is vararg, store any remaining integer argument regs
2407 // to their spots on the stack so that they may be loaded by deferencing the
2408 // result of va_next.
2409 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2410 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2411 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2412 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2413 MachinePointerInfo(), false, false, 0);
2414 MemOps.push_back(Store);
2415 // Increment the address by four for the next argument to store
2416 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2417 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2421 if (!MemOps.empty())
2422 Chain = DAG.getNode(ISD::TokenFactor, dl,
2423 MVT::Other, &MemOps[0], MemOps.size());
2429 PPCTargetLowering::LowerFormalArguments_Darwin(
2431 CallingConv::ID CallConv, bool isVarArg,
2432 const SmallVectorImpl<ISD::InputArg>
2434 SDLoc dl, SelectionDAG &DAG,
2435 SmallVectorImpl<SDValue> &InVals) const {
2436 // TODO: add description of PPC stack frame format, or at least some docs.
2438 MachineFunction &MF = DAG.getMachineFunction();
2439 MachineFrameInfo *MFI = MF.getFrameInfo();
2440 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2442 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2443 bool isPPC64 = PtrVT == MVT::i64;
2444 // Potential tail calls could cause overwriting of argument stack slots.
2445 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2446 (CallConv == CallingConv::Fast));
2447 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2449 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2450 // Area that is at least reserved in caller of this function.
2451 unsigned MinReservedArea = ArgOffset;
2453 static const uint16_t GPR_32[] = { // 32-bit registers.
2454 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2455 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2457 static const uint16_t GPR_64[] = { // 64-bit registers.
2458 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2459 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2462 static const uint16_t *FPR = GetFPR();
2464 static const uint16_t VR[] = {
2465 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2466 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2469 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2470 const unsigned Num_FPR_Regs = 13;
2471 const unsigned Num_VR_Regs = array_lengthof( VR);
2473 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2475 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2477 // In 32-bit non-varargs functions, the stack space for vectors is after the
2478 // stack space for non-vectors. We do not use this space unless we have
2479 // too many vectors to fit in registers, something that only occurs in
2480 // constructed examples:), but we have to walk the arglist to figure
2481 // that out...for the pathological case, compute VecArgOffset as the
2482 // start of the vector parameter area. Computing VecArgOffset is the
2483 // entire point of the following loop.
2484 unsigned VecArgOffset = ArgOffset;
2485 if (!isVarArg && !isPPC64) {
2486 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2488 EVT ObjectVT = Ins[ArgNo].VT;
2489 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2491 if (Flags.isByVal()) {
2492 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2493 unsigned ObjSize = Flags.getByValSize();
2495 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2496 VecArgOffset += ArgSize;
2500 switch(ObjectVT.getSimpleVT().SimpleTy) {
2501 default: llvm_unreachable("Unhandled argument type!");
2506 case MVT::i64: // PPC64
2508 // FIXME: We are guaranteed to be !isPPC64 at this point.
2509 // Does MVT::i64 apply?
2516 // Nothing to do, we're only looking at Nonvector args here.
2521 // We've found where the vector parameter area in memory is. Skip the
2522 // first 12 parameters; these don't use that memory.
2523 VecArgOffset = ((VecArgOffset+15)/16)*16;
2524 VecArgOffset += 12*16;
2526 // Add DAG nodes to load the arguments or copy them out of registers. On
2527 // entry to a function on PPC, the arguments start after the linkage area,
2528 // although the first ones are often in registers.
2530 SmallVector<SDValue, 8> MemOps;
2531 unsigned nAltivecParamsAtEnd = 0;
2532 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2533 unsigned CurArgIdx = 0;
2534 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2536 bool needsLoad = false;
2537 EVT ObjectVT = Ins[ArgNo].VT;
2538 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2539 unsigned ArgSize = ObjSize;
2540 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2541 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2542 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2544 unsigned CurArgOffset = ArgOffset;
2546 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2547 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2548 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2549 if (isVarArg || isPPC64) {
2550 MinReservedArea = ((MinReservedArea+15)/16)*16;
2551 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2554 } else nAltivecParamsAtEnd++;
2556 // Calculate min reserved area.
2557 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2561 // FIXME the codegen can be much improved in some cases.
2562 // We do not have to keep everything in memory.
2563 if (Flags.isByVal()) {
2564 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2565 ObjSize = Flags.getByValSize();
2566 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2567 // Objects of size 1 and 2 are right justified, everything else is
2568 // left justified. This means the memory address is adjusted forwards.
2569 if (ObjSize==1 || ObjSize==2) {
2570 CurArgOffset = CurArgOffset + (4 - ObjSize);
2572 // The value of the object is its address.
2573 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2574 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2575 InVals.push_back(FIN);
2576 if (ObjSize==1 || ObjSize==2) {
2577 if (GPR_idx != Num_GPR_Regs) {
2580 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2582 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2583 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2584 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2585 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2586 MachinePointerInfo(FuncArg,
2588 ObjType, false, false, 0);
2589 MemOps.push_back(Store);
2593 ArgOffset += PtrByteSize;
2597 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2598 // Store whatever pieces of the object are in registers
2599 // to memory. ArgOffset will be the address of the beginning
2601 if (GPR_idx != Num_GPR_Regs) {
2604 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2606 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2607 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2608 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2609 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2610 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2611 MachinePointerInfo(FuncArg, ArgOffset),
2613 MemOps.push_back(Store);
2615 ArgOffset += PtrByteSize;
2617 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2624 switch (ObjectVT.getSimpleVT().SimpleTy) {
2625 default: llvm_unreachable("Unhandled argument type!");
2628 if (GPR_idx != Num_GPR_Regs) {
2629 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2630 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2634 ArgSize = PtrByteSize;
2636 // All int arguments reserve stack space in the Darwin ABI.
2637 ArgOffset += PtrByteSize;
2641 case MVT::i64: // PPC64
2642 if (GPR_idx != Num_GPR_Regs) {
2643 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2644 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2646 if (ObjectVT == MVT::i32)
2647 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2648 // value to MVT::i64 and then truncate to the correct register size.
2649 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2654 ArgSize = PtrByteSize;
2656 // All int arguments reserve stack space in the Darwin ABI.
2662 // Every 4 bytes of argument space consumes one of the GPRs available for
2663 // argument passing.
2664 if (GPR_idx != Num_GPR_Regs) {
2666 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2669 if (FPR_idx != Num_FPR_Regs) {
2672 if (ObjectVT == MVT::f32)
2673 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2675 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2677 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2683 // All FP arguments reserve stack space in the Darwin ABI.
2684 ArgOffset += isPPC64 ? 8 : ObjSize;
2690 // Note that vector arguments in registers don't reserve stack space,
2691 // except in varargs functions.
2692 if (VR_idx != Num_VR_Regs) {
2693 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2694 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2696 while ((ArgOffset % 16) != 0) {
2697 ArgOffset += PtrByteSize;
2698 if (GPR_idx != Num_GPR_Regs)
2702 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2706 if (!isVarArg && !isPPC64) {
2707 // Vectors go after all the nonvectors.
2708 CurArgOffset = VecArgOffset;
2711 // Vectors are aligned.
2712 ArgOffset = ((ArgOffset+15)/16)*16;
2713 CurArgOffset = ArgOffset;
2721 // We need to load the argument to a virtual register if we determined above
2722 // that we ran out of physical registers of the appropriate type.
2724 int FI = MFI->CreateFixedObject(ObjSize,
2725 CurArgOffset + (ArgSize - ObjSize),
2727 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2728 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2729 false, false, false, 0);
2732 InVals.push_back(ArgVal);
2735 // Set the size that is at least reserved in caller of this function. Tail
2736 // call optimized functions' reserved stack space needs to be aligned so that
2737 // taking the difference between two stack areas will result in an aligned
2739 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
2741 // If the function takes variable number of arguments, make a frame index for
2742 // the start of the first vararg value... for expansion of llvm.va_start.
2744 int Depth = ArgOffset;
2746 FuncInfo->setVarArgsFrameIndex(
2747 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2749 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2751 // If this function is vararg, store any remaining integer argument regs
2752 // to their spots on the stack so that they may be loaded by deferencing the
2753 // result of va_next.
2754 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2758 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2760 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2762 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2763 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2764 MachinePointerInfo(), false, false, 0);
2765 MemOps.push_back(Store);
2766 // Increment the address by four for the next argument to store
2767 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2768 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2772 if (!MemOps.empty())
2773 Chain = DAG.getNode(ISD::TokenFactor, dl,
2774 MVT::Other, &MemOps[0], MemOps.size());
2779 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
2780 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
2782 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2786 const SmallVectorImpl<ISD::OutputArg>
2788 const SmallVectorImpl<SDValue> &OutVals,
2789 unsigned &nAltivecParamsAtEnd) {
2790 // Count how many bytes are to be pushed on the stack, including the linkage
2791 // area, and parameter passing area. We start with 24/48 bytes, which is
2792 // prereserved space for [SP][CR][LR][3 x unused].
2793 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2794 unsigned NumOps = Outs.size();
2795 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2797 // Add up all the space actually used.
2798 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2799 // they all go in registers, but we must reserve stack space for them for
2800 // possible use by the caller. In varargs or 64-bit calls, parameters are
2801 // assigned stack space in order, with padding so Altivec parameters are
2803 nAltivecParamsAtEnd = 0;
2804 for (unsigned i = 0; i != NumOps; ++i) {
2805 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2806 EVT ArgVT = Outs[i].VT;
2807 // Varargs Altivec parameters are padded to a 16 byte boundary.
2808 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2809 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2810 if (!isVarArg && !isPPC64) {
2811 // Non-varargs Altivec parameters go after all the non-Altivec
2812 // parameters; handle those later so we know how much padding we need.
2813 nAltivecParamsAtEnd++;
2816 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2817 NumBytes = ((NumBytes+15)/16)*16;
2819 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2822 // Allow for Altivec parameters at the end, if needed.
2823 if (nAltivecParamsAtEnd) {
2824 NumBytes = ((NumBytes+15)/16)*16;
2825 NumBytes += 16*nAltivecParamsAtEnd;
2828 // The prolog code of the callee may store up to 8 GPR argument registers to
2829 // the stack, allowing va_start to index over them in memory if its varargs.
2830 // Because we cannot tell if this is needed on the caller side, we have to
2831 // conservatively assume that it is needed. As such, make sure we have at
2832 // least enough stack space for the caller to store the 8 GPRs.
2833 NumBytes = std::max(NumBytes,
2834 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2836 // Tail call needs the stack to be aligned.
2837 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2838 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2839 getFrameLowering()->getStackAlignment();
2840 unsigned AlignMask = TargetAlign-1;
2841 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2847 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2848 /// adjusted to accommodate the arguments for the tailcall.
2849 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2850 unsigned ParamSize) {
2852 if (!isTailCall) return 0;
2854 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2855 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2856 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2857 // Remember only if the new adjustement is bigger.
2858 if (SPDiff < FI->getTailCallSPDelta())
2859 FI->setTailCallSPDelta(SPDiff);
2864 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2865 /// for tail call optimization. Targets which want to do tail call
2866 /// optimization should implement this function.
2868 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2869 CallingConv::ID CalleeCC,
2871 const SmallVectorImpl<ISD::InputArg> &Ins,
2872 SelectionDAG& DAG) const {
2873 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2876 // Variable argument functions are not supported.
2880 MachineFunction &MF = DAG.getMachineFunction();
2881 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2882 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2883 // Functions containing by val parameters are not supported.
2884 for (unsigned i = 0; i != Ins.size(); i++) {
2885 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2886 if (Flags.isByVal()) return false;
2889 // Non PIC/GOT tail calls are supported.
2890 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2893 // At the moment we can only do local tail calls (in same module, hidden
2894 // or protected) if we are generating PIC.
2895 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2896 return G->getGlobal()->hasHiddenVisibility()
2897 || G->getGlobal()->hasProtectedVisibility();
2903 /// isCallCompatibleAddress - Return the immediate to use if the specified
2904 /// 32-bit value is representable in the immediate field of a BxA instruction.
2905 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2906 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2909 int Addr = C->getZExtValue();
2910 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2911 SignExtend32<26>(Addr) != Addr)
2912 return 0; // Top 6 bits have to be sext of immediate.
2914 return DAG.getConstant((int)C->getZExtValue() >> 2,
2915 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2920 struct TailCallArgumentInfo {
2925 TailCallArgumentInfo() : FrameIdx(0) {}
2930 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2932 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2934 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2935 SmallVector<SDValue, 8> &MemOpChains,
2937 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2938 SDValue Arg = TailCallArgs[i].Arg;
2939 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2940 int FI = TailCallArgs[i].FrameIdx;
2941 // Store relative to framepointer.
2942 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2943 MachinePointerInfo::getFixedStack(FI),
2948 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2949 /// the appropriate stack slot for the tail call optimized function call.
2950 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2951 MachineFunction &MF,
2960 // Calculate the new stack slot for the return address.
2961 int SlotSize = isPPC64 ? 8 : 4;
2962 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
2964 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2965 NewRetAddrLoc, true);
2966 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2967 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2968 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2969 MachinePointerInfo::getFixedStack(NewRetAddr),
2972 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2973 // slot as the FP is never overwritten.
2976 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2977 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
2979 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2980 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2981 MachinePointerInfo::getFixedStack(NewFPIdx),
2988 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2989 /// the position of the argument.
2991 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2992 SDValue Arg, int SPDiff, unsigned ArgOffset,
2993 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2994 int Offset = ArgOffset + SPDiff;
2995 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2996 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2997 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2998 SDValue FIN = DAG.getFrameIndex(FI, VT);
2999 TailCallArgumentInfo Info;
3001 Info.FrameIdxOp = FIN;
3003 TailCallArguments.push_back(Info);
3006 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3007 /// stack slot. Returns the chain as result and the loaded frame pointers in
3008 /// LROpOut/FPOpout. Used when tail calling.
3009 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3017 // Load the LR and FP stack slot for later adjusting.
3018 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3019 LROpOut = getReturnAddrFrameIndex(DAG);
3020 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3021 false, false, false, 0);
3022 Chain = SDValue(LROpOut.getNode(), 1);
3024 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3025 // slot as the FP is never overwritten.
3027 FPOpOut = getFramePointerFrameIndex(DAG);
3028 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3029 false, false, false, 0);
3030 Chain = SDValue(FPOpOut.getNode(), 1);
3036 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3037 /// by "Src" to address "Dst" of size "Size". Alignment information is
3038 /// specified by the specific parameter attribute. The copy will be passed as
3039 /// a byval function parameter.
3040 /// Sometimes what we are copying is the end of a larger object, the part that
3041 /// does not fit in registers.
3043 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3044 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3046 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3047 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3048 false, false, MachinePointerInfo(0),
3049 MachinePointerInfo(0));
3052 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3055 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3056 SDValue Arg, SDValue PtrOff, int SPDiff,
3057 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3058 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
3059 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
3061 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3066 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3068 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3069 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3070 DAG.getConstant(ArgOffset, PtrVT));
3072 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3073 MachinePointerInfo(), false, false, 0));
3074 // Calculate and remember argument location.
3075 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3080 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3081 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3082 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3083 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
3084 MachineFunction &MF = DAG.getMachineFunction();
3086 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3087 // might overwrite each other in case of tail call optimization.
3088 SmallVector<SDValue, 8> MemOpChains2;
3089 // Do not flag preceding copytoreg stuff together with the following stuff.
3091 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3093 if (!MemOpChains2.empty())
3094 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3095 &MemOpChains2[0], MemOpChains2.size());
3097 // Store the return address to the appropriate stack slot.
3098 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3099 isPPC64, isDarwinABI, dl);
3101 // Emit callseq_end just before tailcall node.
3102 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3103 DAG.getIntPtrConstant(0, true), InFlag);
3104 InFlag = Chain.getValue(1);
3108 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3109 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3110 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
3111 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
3112 const PPCSubtarget &PPCSubTarget) {
3114 bool isPPC64 = PPCSubTarget.isPPC64();
3115 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3117 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3118 NodeTys.push_back(MVT::Other); // Returns a chain
3119 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3121 unsigned CallOpc = PPCISD::CALL;
3123 bool needIndirectCall = true;
3124 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3125 // If this is an absolute destination address, use the munged value.
3126 Callee = SDValue(Dest, 0);
3127 needIndirectCall = false;
3130 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3131 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3132 // Use indirect calls for ALL functions calls in JIT mode, since the
3133 // far-call stubs may be outside relocation limits for a BL instruction.
3134 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3135 unsigned OpFlags = 0;
3136 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3137 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3138 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3139 (G->getGlobal()->isDeclaration() ||
3140 G->getGlobal()->isWeakForLinker())) {
3141 // PC-relative references to external symbols should go through $stub,
3142 // unless we're building with the leopard linker or later, which
3143 // automatically synthesizes these stubs.
3144 OpFlags = PPCII::MO_DARWIN_STUB;
3147 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3148 // every direct call is) turn it into a TargetGlobalAddress /
3149 // TargetExternalSymbol node so that legalize doesn't hack it.
3150 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3151 Callee.getValueType(),
3153 needIndirectCall = false;
3157 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3158 unsigned char OpFlags = 0;
3160 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3161 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3162 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3163 // PC-relative references to external symbols should go through $stub,
3164 // unless we're building with the leopard linker or later, which
3165 // automatically synthesizes these stubs.
3166 OpFlags = PPCII::MO_DARWIN_STUB;
3169 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3171 needIndirectCall = false;
3174 if (needIndirectCall) {
3175 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3176 // to do the call, we can't use PPCISD::CALL.
3177 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3179 if (isSVR4ABI && isPPC64) {
3180 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3181 // entry point, but to the function descriptor (the function entry point
3182 // address is part of the function descriptor though).
3183 // The function descriptor is a three doubleword structure with the
3184 // following fields: function entry point, TOC base address and
3185 // environment pointer.
3186 // Thus for a call through a function pointer, the following actions need
3188 // 1. Save the TOC of the caller in the TOC save area of its stack
3189 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3190 // 2. Load the address of the function entry point from the function
3192 // 3. Load the TOC of the callee from the function descriptor into r2.
3193 // 4. Load the environment pointer from the function descriptor into
3195 // 5. Branch to the function entry point address.
3196 // 6. On return of the callee, the TOC of the caller needs to be
3197 // restored (this is done in FinishCall()).
3199 // All those operations are flagged together to ensure that no other
3200 // operations can be scheduled in between. E.g. without flagging the
3201 // operations together, a TOC access in the caller could be scheduled
3202 // between the load of the callee TOC and the branch to the callee, which
3203 // results in the TOC access going through the TOC of the callee instead
3204 // of going through the TOC of the caller, which leads to incorrect code.
3206 // Load the address of the function entry point from the function
3208 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3209 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
3210 InFlag.getNode() ? 3 : 2);
3211 Chain = LoadFuncPtr.getValue(1);
3212 InFlag = LoadFuncPtr.getValue(2);
3214 // Load environment pointer into r11.
3215 // Offset of the environment pointer within the function descriptor.
3216 SDValue PtrOff = DAG.getIntPtrConstant(16);
3218 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3219 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3221 Chain = LoadEnvPtr.getValue(1);
3222 InFlag = LoadEnvPtr.getValue(2);
3224 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3226 Chain = EnvVal.getValue(0);
3227 InFlag = EnvVal.getValue(1);
3229 // Load TOC of the callee into r2. We are using a target-specific load
3230 // with r2 hard coded, because the result of a target-independent load
3231 // would never go directly into r2, since r2 is a reserved register (which
3232 // prevents the register allocator from allocating it), resulting in an
3233 // additional register being allocated and an unnecessary move instruction
3235 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3236 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3238 Chain = LoadTOCPtr.getValue(0);
3239 InFlag = LoadTOCPtr.getValue(1);
3241 MTCTROps[0] = Chain;
3242 MTCTROps[1] = LoadFuncPtr;
3243 MTCTROps[2] = InFlag;
3246 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
3247 2 + (InFlag.getNode() != 0));
3248 InFlag = Chain.getValue(1);
3251 NodeTys.push_back(MVT::Other);
3252 NodeTys.push_back(MVT::Glue);
3253 Ops.push_back(Chain);
3254 CallOpc = PPCISD::BCTRL;
3256 // Add use of X11 (holding environment pointer)
3257 if (isSVR4ABI && isPPC64)
3258 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3259 // Add CTR register as callee so a bctr can be emitted later.
3261 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3264 // If this is a direct call, pass the chain and the callee.
3265 if (Callee.getNode()) {
3266 Ops.push_back(Chain);
3267 Ops.push_back(Callee);
3269 // If this is a tail call add stack pointer delta.
3271 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3273 // Add argument registers to the end of the list so that they are known live
3275 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3276 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3277 RegsToPass[i].second.getValueType()));
3283 bool isLocalCall(const SDValue &Callee)
3285 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3286 return !G->getGlobal()->isDeclaration() &&
3287 !G->getGlobal()->isWeakForLinker();
3292 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3293 CallingConv::ID CallConv, bool isVarArg,
3294 const SmallVectorImpl<ISD::InputArg> &Ins,
3295 SDLoc dl, SelectionDAG &DAG,
3296 SmallVectorImpl<SDValue> &InVals) const {
3298 SmallVector<CCValAssign, 16> RVLocs;
3299 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3300 getTargetMachine(), RVLocs, *DAG.getContext());
3301 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3303 // Copy all of the result registers out of their specified physreg.
3304 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3305 CCValAssign &VA = RVLocs[i];
3306 assert(VA.isRegLoc() && "Can only return in registers!");
3308 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3309 VA.getLocReg(), VA.getLocVT(), InFlag);
3310 Chain = Val.getValue(1);
3311 InFlag = Val.getValue(2);
3313 switch (VA.getLocInfo()) {
3314 default: llvm_unreachable("Unknown loc info!");
3315 case CCValAssign::Full: break;
3316 case CCValAssign::AExt:
3317 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3319 case CCValAssign::ZExt:
3320 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3321 DAG.getValueType(VA.getValVT()));
3322 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3324 case CCValAssign::SExt:
3325 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3326 DAG.getValueType(VA.getValVT()));
3327 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3331 InVals.push_back(Val);
3338 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3339 bool isTailCall, bool isVarArg,
3341 SmallVector<std::pair<unsigned, SDValue>, 8>
3343 SDValue InFlag, SDValue Chain,
3345 int SPDiff, unsigned NumBytes,
3346 const SmallVectorImpl<ISD::InputArg> &Ins,
3347 SmallVectorImpl<SDValue> &InVals) const {
3348 std::vector<EVT> NodeTys;
3349 SmallVector<SDValue, 8> Ops;
3350 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3351 isTailCall, RegsToPass, Ops, NodeTys,
3354 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3355 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3356 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3358 // When performing tail call optimization the callee pops its arguments off
3359 // the stack. Account for this here so these bytes can be pushed back on in
3360 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3361 int BytesCalleePops =
3362 (CallConv == CallingConv::Fast &&
3363 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3365 // Add a register mask operand representing the call-preserved registers.
3366 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3367 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3368 assert(Mask && "Missing call preserved mask for calling convention");
3369 Ops.push_back(DAG.getRegisterMask(Mask));
3371 if (InFlag.getNode())
3372 Ops.push_back(InFlag);
3376 assert(((Callee.getOpcode() == ISD::Register &&
3377 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3378 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3379 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3380 isa<ConstantSDNode>(Callee)) &&
3381 "Expecting an global address, external symbol, absolute value or register");
3383 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3386 // Add a NOP immediately after the branch instruction when using the 64-bit
3387 // SVR4 ABI. At link time, if caller and callee are in a different module and
3388 // thus have a different TOC, the call will be replaced with a call to a stub
3389 // function which saves the current TOC, loads the TOC of the callee and
3390 // branches to the callee. The NOP will be replaced with a load instruction
3391 // which restores the TOC of the caller from the TOC save slot of the current
3392 // stack frame. If caller and callee belong to the same module (and have the
3393 // same TOC), the NOP will remain unchanged.
3395 bool needsTOCRestore = false;
3396 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3397 if (CallOpc == PPCISD::BCTRL) {
3398 // This is a call through a function pointer.
3399 // Restore the caller TOC from the save area into R2.
3400 // See PrepareCall() for more information about calls through function
3401 // pointers in the 64-bit SVR4 ABI.
3402 // We are using a target-specific load with r2 hard coded, because the
3403 // result of a target-independent load would never go directly into r2,
3404 // since r2 is a reserved register (which prevents the register allocator
3405 // from allocating it), resulting in an additional register being
3406 // allocated and an unnecessary move instruction being generated.
3407 needsTOCRestore = true;
3408 } else if ((CallOpc == PPCISD::CALL) && !isLocalCall(Callee)) {
3409 // Otherwise insert NOP for non-local calls.
3410 CallOpc = PPCISD::CALL_NOP;
3414 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
3415 InFlag = Chain.getValue(1);
3417 if (needsTOCRestore) {
3418 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3419 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3420 InFlag = Chain.getValue(1);
3423 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3424 DAG.getIntPtrConstant(BytesCalleePops, true),
3427 InFlag = Chain.getValue(1);
3429 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3430 Ins, dl, DAG, InVals);
3434 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3435 SmallVectorImpl<SDValue> &InVals) const {
3436 SelectionDAG &DAG = CLI.DAG;
3438 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
3439 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
3440 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
3441 SDValue Chain = CLI.Chain;
3442 SDValue Callee = CLI.Callee;
3443 bool &isTailCall = CLI.IsTailCall;
3444 CallingConv::ID CallConv = CLI.CallConv;
3445 bool isVarArg = CLI.IsVarArg;
3448 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3451 if (PPCSubTarget.isSVR4ABI()) {
3452 if (PPCSubTarget.isPPC64())
3453 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3454 isTailCall, Outs, OutVals, Ins,
3457 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3458 isTailCall, Outs, OutVals, Ins,
3462 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3463 isTailCall, Outs, OutVals, Ins,
3468 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3469 CallingConv::ID CallConv, bool isVarArg,
3471 const SmallVectorImpl<ISD::OutputArg> &Outs,
3472 const SmallVectorImpl<SDValue> &OutVals,
3473 const SmallVectorImpl<ISD::InputArg> &Ins,
3474 SDLoc dl, SelectionDAG &DAG,
3475 SmallVectorImpl<SDValue> &InVals) const {
3476 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3477 // of the 32-bit SVR4 ABI stack frame layout.
3479 assert((CallConv == CallingConv::C ||
3480 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3482 unsigned PtrByteSize = 4;
3484 MachineFunction &MF = DAG.getMachineFunction();
3486 // Mark this function as potentially containing a function that contains a
3487 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3488 // and restoring the callers stack pointer in this functions epilog. This is
3489 // done because by tail calling the called function might overwrite the value
3490 // in this function's (MF) stack pointer stack slot 0(SP).
3491 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3492 CallConv == CallingConv::Fast)
3493 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3495 // Count how many bytes are to be pushed on the stack, including the linkage
3496 // area, parameter list area and the part of the local variable space which
3497 // contains copies of aggregates which are passed by value.
3499 // Assign locations to all of the outgoing arguments.
3500 SmallVector<CCValAssign, 16> ArgLocs;
3501 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3502 getTargetMachine(), ArgLocs, *DAG.getContext());
3504 // Reserve space for the linkage area on the stack.
3505 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3508 // Handle fixed and variable vector arguments differently.
3509 // Fixed vector arguments go into registers as long as registers are
3510 // available. Variable vector arguments always go into memory.
3511 unsigned NumArgs = Outs.size();
3513 for (unsigned i = 0; i != NumArgs; ++i) {
3514 MVT ArgVT = Outs[i].VT;
3515 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3518 if (Outs[i].IsFixed) {
3519 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3522 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3528 errs() << "Call operand #" << i << " has unhandled type "
3529 << EVT(ArgVT).getEVTString() << "\n";
3531 llvm_unreachable(0);
3535 // All arguments are treated the same.
3536 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3539 // Assign locations to all of the outgoing aggregate by value arguments.
3540 SmallVector<CCValAssign, 16> ByValArgLocs;
3541 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3542 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3544 // Reserve stack space for the allocations in CCInfo.
3545 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3547 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3549 // Size of the linkage area, parameter list area and the part of the local
3550 // space variable where copies of aggregates which are passed by value are
3552 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3554 // Calculate by how many bytes the stack has to be adjusted in case of tail
3555 // call optimization.
3556 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3558 // Adjust the stack pointer for the new arguments...
3559 // These operations are automatically eliminated by the prolog/epilog pass
3560 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3561 SDValue CallSeqStart = Chain;
3563 // Load the return address and frame pointer so it can be moved somewhere else
3566 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3569 // Set up a copy of the stack pointer for use loading and storing any
3570 // arguments that may not fit in the registers available for argument
3572 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3574 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3575 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3576 SmallVector<SDValue, 8> MemOpChains;
3578 bool seenFloatArg = false;
3579 // Walk the register/memloc assignments, inserting copies/loads.
3580 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3583 CCValAssign &VA = ArgLocs[i];
3584 SDValue Arg = OutVals[i];
3585 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3587 if (Flags.isByVal()) {
3588 // Argument is an aggregate which is passed by value, thus we need to
3589 // create a copy of it in the local variable space of the current stack
3590 // frame (which is the stack frame of the caller) and pass the address of
3591 // this copy to the callee.
3592 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3593 CCValAssign &ByValVA = ByValArgLocs[j++];
3594 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3596 // Memory reserved in the local variable space of the callers stack frame.
3597 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3599 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3600 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3602 // Create a copy of the argument in the local area of the current
3604 SDValue MemcpyCall =
3605 CreateCopyOfByValArgument(Arg, PtrOff,
3606 CallSeqStart.getNode()->getOperand(0),
3609 // This must go outside the CALLSEQ_START..END.
3610 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3611 CallSeqStart.getNode()->getOperand(1));
3612 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3613 NewCallSeqStart.getNode());
3614 Chain = CallSeqStart = NewCallSeqStart;
3616 // Pass the address of the aggregate copy on the stack either in a
3617 // physical register or in the parameter list area of the current stack
3618 // frame to the callee.
3622 if (VA.isRegLoc()) {
3623 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3624 // Put argument in a physical register.
3625 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3627 // Put argument in the parameter list area of the current stack frame.
3628 assert(VA.isMemLoc());
3629 unsigned LocMemOffset = VA.getLocMemOffset();
3632 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3633 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3635 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3636 MachinePointerInfo(),
3639 // Calculate and remember argument location.
3640 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3646 if (!MemOpChains.empty())
3647 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3648 &MemOpChains[0], MemOpChains.size());
3650 // Build a sequence of copy-to-reg nodes chained together with token chain
3651 // and flag operands which copy the outgoing args into the appropriate regs.
3653 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3654 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3655 RegsToPass[i].second, InFlag);
3656 InFlag = Chain.getValue(1);
3659 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3662 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3663 SDValue Ops[] = { Chain, InFlag };
3665 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3666 dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
3668 InFlag = Chain.getValue(1);
3672 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3673 false, TailCallArguments);
3675 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3676 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3680 // Copy an argument into memory, being careful to do this outside the
3681 // call sequence for the call to which the argument belongs.
3683 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3684 SDValue CallSeqStart,
3685 ISD::ArgFlagsTy Flags,
3688 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3689 CallSeqStart.getNode()->getOperand(0),
3691 // The MEMCPY must go outside the CALLSEQ_START..END.
3692 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3693 CallSeqStart.getNode()->getOperand(1));
3694 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3695 NewCallSeqStart.getNode());
3696 return NewCallSeqStart;
3700 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3701 CallingConv::ID CallConv, bool isVarArg,
3703 const SmallVectorImpl<ISD::OutputArg> &Outs,
3704 const SmallVectorImpl<SDValue> &OutVals,
3705 const SmallVectorImpl<ISD::InputArg> &Ins,
3706 SDLoc dl, SelectionDAG &DAG,
3707 SmallVectorImpl<SDValue> &InVals) const {
3709 unsigned NumOps = Outs.size();
3711 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3712 unsigned PtrByteSize = 8;
3714 MachineFunction &MF = DAG.getMachineFunction();
3716 // Mark this function as potentially containing a function that contains a
3717 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3718 // and restoring the callers stack pointer in this functions epilog. This is
3719 // done because by tail calling the called function might overwrite the value
3720 // in this function's (MF) stack pointer stack slot 0(SP).
3721 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3722 CallConv == CallingConv::Fast)
3723 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3725 unsigned nAltivecParamsAtEnd = 0;
3727 // Count how many bytes are to be pushed on the stack, including the linkage
3728 // area, and parameter passing area. We start with at least 48 bytes, which
3729 // is reserved space for [SP][CR][LR][3 x unused].
3730 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
3733 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
3734 Outs, OutVals, nAltivecParamsAtEnd);
3736 // Calculate by how many bytes the stack has to be adjusted in case of tail
3737 // call optimization.
3738 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3740 // To protect arguments on the stack from being clobbered in a tail call,
3741 // force all the loads to happen before doing any other lowering.
3743 Chain = DAG.getStackArgumentTokenFactor(Chain);
3745 // Adjust the stack pointer for the new arguments...
3746 // These operations are automatically eliminated by the prolog/epilog pass
3747 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3748 SDValue CallSeqStart = Chain;
3750 // Load the return address and frame pointer so it can be move somewhere else
3753 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3756 // Set up a copy of the stack pointer for use loading and storing any
3757 // arguments that may not fit in the registers available for argument
3759 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3761 // Figure out which arguments are going to go in registers, and which in
3762 // memory. Also, if this is a vararg function, floating point operations
3763 // must be stored to our stack, and loaded into integer regs as well, if
3764 // any integer regs are available for argument passing.
3765 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
3766 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3768 static const uint16_t GPR[] = {
3769 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3770 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3772 static const uint16_t *FPR = GetFPR();
3774 static const uint16_t VR[] = {
3775 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3776 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3778 const unsigned NumGPRs = array_lengthof(GPR);
3779 const unsigned NumFPRs = 13;
3780 const unsigned NumVRs = array_lengthof(VR);
3782 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3783 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3785 SmallVector<SDValue, 8> MemOpChains;
3786 for (unsigned i = 0; i != NumOps; ++i) {
3787 SDValue Arg = OutVals[i];
3788 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3790 // PtrOff will be used to store the current argument to the stack if a
3791 // register cannot be found for it.
3794 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3796 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3798 // Promote integers to 64-bit values.
3799 if (Arg.getValueType() == MVT::i32) {
3800 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3801 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3802 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3805 // FIXME memcpy is used way more than necessary. Correctness first.
3806 // Note: "by value" is code for passing a structure by value, not
3808 if (Flags.isByVal()) {
3809 // Note: Size includes alignment padding, so
3810 // struct x { short a; char b; }
3811 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
3812 // These are the proper values we need for right-justifying the
3813 // aggregate in a parameter register.
3814 unsigned Size = Flags.getByValSize();
3816 // An empty aggregate parameter takes up no storage and no
3821 // All aggregates smaller than 8 bytes must be passed right-justified.
3822 if (Size==1 || Size==2 || Size==4) {
3823 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
3824 if (GPR_idx != NumGPRs) {
3825 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3826 MachinePointerInfo(), VT,
3828 MemOpChains.push_back(Load.getValue(1));
3829 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3831 ArgOffset += PtrByteSize;
3836 if (GPR_idx == NumGPRs && Size < 8) {
3837 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3838 PtrOff.getValueType());
3839 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3840 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3843 ArgOffset += PtrByteSize;
3846 // Copy entire object into memory. There are cases where gcc-generated
3847 // code assumes it is there, even if it could be put entirely into
3848 // registers. (This is not what the doc says.)
3850 // FIXME: The above statement is likely due to a misunderstanding of the
3851 // documents. All arguments must be copied into the parameter area BY
3852 // THE CALLEE in the event that the callee takes the address of any
3853 // formal argument. That has not yet been implemented. However, it is
3854 // reasonable to use the stack area as a staging area for the register
3857 // Skip this for small aggregates, as we will use the same slot for a
3858 // right-justified copy, below.
3860 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
3864 // When a register is available, pass a small aggregate right-justified.
3865 if (Size < 8 && GPR_idx != NumGPRs) {
3866 // The easiest way to get this right-justified in a register
3867 // is to copy the structure into the rightmost portion of a
3868 // local variable slot, then load the whole slot into the
3870 // FIXME: The memcpy seems to produce pretty awful code for
3871 // small aggregates, particularly for packed ones.
3872 // FIXME: It would be preferable to use the slot in the
3873 // parameter save area instead of a new local variable.
3874 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
3875 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3876 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3880 // Load the slot into the register.
3881 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
3882 MachinePointerInfo(),
3883 false, false, false, 0);
3884 MemOpChains.push_back(Load.getValue(1));
3885 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3887 // Done with this argument.
3888 ArgOffset += PtrByteSize;
3892 // For aggregates larger than PtrByteSize, copy the pieces of the
3893 // object that fit into registers from the parameter save area.
3894 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3895 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3896 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3897 if (GPR_idx != NumGPRs) {
3898 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3899 MachinePointerInfo(),
3900 false, false, false, 0);
3901 MemOpChains.push_back(Load.getValue(1));
3902 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3903 ArgOffset += PtrByteSize;
3905 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3912 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3913 default: llvm_unreachable("Unexpected ValueType for argument!");
3916 if (GPR_idx != NumGPRs) {
3917 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3919 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3920 true, isTailCall, false, MemOpChains,
3921 TailCallArguments, dl);
3923 ArgOffset += PtrByteSize;
3927 if (FPR_idx != NumFPRs) {
3928 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3931 // A single float or an aggregate containing only a single float
3932 // must be passed right-justified in the stack doubleword, and
3933 // in the GPR, if one is available.
3935 if (Arg.getValueType().getSimpleVT().SimpleTy == MVT::f32) {
3936 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3937 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3941 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
3942 MachinePointerInfo(), false, false, 0);
3943 MemOpChains.push_back(Store);
3945 // Float varargs are always shadowed in available integer registers
3946 if (GPR_idx != NumGPRs) {
3947 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3948 MachinePointerInfo(), false, false,
3950 MemOpChains.push_back(Load.getValue(1));
3951 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3953 } else if (GPR_idx != NumGPRs)
3954 // If we have any FPRs remaining, we may also have GPRs remaining.
3957 // Single-precision floating-point values are mapped to the
3958 // second (rightmost) word of the stack doubleword.
3959 if (Arg.getValueType() == MVT::f32) {
3960 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3961 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3964 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3965 true, isTailCall, false, MemOpChains,
3966 TailCallArguments, dl);
3975 // These go aligned on the stack, or in the corresponding R registers
3976 // when within range. The Darwin PPC ABI doc claims they also go in
3977 // V registers; in fact gcc does this only for arguments that are
3978 // prototyped, not for those that match the ... We do it for all
3979 // arguments, seems to work.
3980 while (ArgOffset % 16 !=0) {
3981 ArgOffset += PtrByteSize;
3982 if (GPR_idx != NumGPRs)
3985 // We could elide this store in the case where the object fits
3986 // entirely in R registers. Maybe later.
3987 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3988 DAG.getConstant(ArgOffset, PtrVT));
3989 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3990 MachinePointerInfo(), false, false, 0);
3991 MemOpChains.push_back(Store);
3992 if (VR_idx != NumVRs) {
3993 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
3994 MachinePointerInfo(),
3995 false, false, false, 0);
3996 MemOpChains.push_back(Load.getValue(1));
3997 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4000 for (unsigned i=0; i<16; i+=PtrByteSize) {
4001 if (GPR_idx == NumGPRs)
4003 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4004 DAG.getConstant(i, PtrVT));
4005 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4006 false, false, false, 0);
4007 MemOpChains.push_back(Load.getValue(1));
4008 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4013 // Non-varargs Altivec params generally go in registers, but have
4014 // stack space allocated at the end.
4015 if (VR_idx != NumVRs) {
4016 // Doesn't have GPR space allocated.
4017 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4019 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4020 true, isTailCall, true, MemOpChains,
4021 TailCallArguments, dl);
4028 if (!MemOpChains.empty())
4029 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4030 &MemOpChains[0], MemOpChains.size());
4032 // Check if this is an indirect call (MTCTR/BCTRL).
4033 // See PrepareCall() for more information about calls through function
4034 // pointers in the 64-bit SVR4 ABI.
4036 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4037 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4038 !isBLACompatibleAddress(Callee, DAG)) {
4039 // Load r2 into a virtual register and store it to the TOC save area.
4040 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4041 // TOC save area offset.
4042 SDValue PtrOff = DAG.getIntPtrConstant(40);
4043 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4044 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4046 // R12 must contain the address of an indirect callee. This does not
4047 // mean the MTCTR instruction must use R12; it's easier to model this
4048 // as an extra parameter, so do that.
4049 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4052 // Build a sequence of copy-to-reg nodes chained together with token chain
4053 // and flag operands which copy the outgoing args into the appropriate regs.
4055 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4056 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4057 RegsToPass[i].second, InFlag);
4058 InFlag = Chain.getValue(1);
4062 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4063 FPOp, true, TailCallArguments);
4065 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4066 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4071 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4072 CallingConv::ID CallConv, bool isVarArg,
4074 const SmallVectorImpl<ISD::OutputArg> &Outs,
4075 const SmallVectorImpl<SDValue> &OutVals,
4076 const SmallVectorImpl<ISD::InputArg> &Ins,
4077 SDLoc dl, SelectionDAG &DAG,
4078 SmallVectorImpl<SDValue> &InVals) const {
4080 unsigned NumOps = Outs.size();
4082 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4083 bool isPPC64 = PtrVT == MVT::i64;
4084 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4086 MachineFunction &MF = DAG.getMachineFunction();
4088 // Mark this function as potentially containing a function that contains a
4089 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4090 // and restoring the callers stack pointer in this functions epilog. This is
4091 // done because by tail calling the called function might overwrite the value
4092 // in this function's (MF) stack pointer stack slot 0(SP).
4093 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4094 CallConv == CallingConv::Fast)
4095 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4097 unsigned nAltivecParamsAtEnd = 0;
4099 // Count how many bytes are to be pushed on the stack, including the linkage
4100 // area, and parameter passing area. We start with 24/48 bytes, which is
4101 // prereserved space for [SP][CR][LR][3 x unused].
4103 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4105 nAltivecParamsAtEnd);
4107 // Calculate by how many bytes the stack has to be adjusted in case of tail
4108 // call optimization.
4109 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4111 // To protect arguments on the stack from being clobbered in a tail call,
4112 // force all the loads to happen before doing any other lowering.
4114 Chain = DAG.getStackArgumentTokenFactor(Chain);
4116 // Adjust the stack pointer for the new arguments...
4117 // These operations are automatically eliminated by the prolog/epilog pass
4118 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
4119 SDValue CallSeqStart = Chain;
4121 // Load the return address and frame pointer so it can be move somewhere else
4124 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4127 // Set up a copy of the stack pointer for use loading and storing any
4128 // arguments that may not fit in the registers available for argument
4132 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4134 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4136 // Figure out which arguments are going to go in registers, and which in
4137 // memory. Also, if this is a vararg function, floating point operations
4138 // must be stored to our stack, and loaded into integer regs as well, if
4139 // any integer regs are available for argument passing.
4140 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4141 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4143 static const uint16_t GPR_32[] = { // 32-bit registers.
4144 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4145 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4147 static const uint16_t GPR_64[] = { // 64-bit registers.
4148 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4149 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4151 static const uint16_t *FPR = GetFPR();
4153 static const uint16_t VR[] = {
4154 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4155 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4157 const unsigned NumGPRs = array_lengthof(GPR_32);
4158 const unsigned NumFPRs = 13;
4159 const unsigned NumVRs = array_lengthof(VR);
4161 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4163 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4164 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4166 SmallVector<SDValue, 8> MemOpChains;
4167 for (unsigned i = 0; i != NumOps; ++i) {
4168 SDValue Arg = OutVals[i];
4169 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4171 // PtrOff will be used to store the current argument to the stack if a
4172 // register cannot be found for it.
4175 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4177 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4179 // On PPC64, promote integers to 64-bit values.
4180 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4181 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4182 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4183 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4186 // FIXME memcpy is used way more than necessary. Correctness first.
4187 // Note: "by value" is code for passing a structure by value, not
4189 if (Flags.isByVal()) {
4190 unsigned Size = Flags.getByValSize();
4191 // Very small objects are passed right-justified. Everything else is
4192 // passed left-justified.
4193 if (Size==1 || Size==2) {
4194 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4195 if (GPR_idx != NumGPRs) {
4196 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4197 MachinePointerInfo(), VT,
4199 MemOpChains.push_back(Load.getValue(1));
4200 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4202 ArgOffset += PtrByteSize;
4204 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4205 PtrOff.getValueType());
4206 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4207 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4210 ArgOffset += PtrByteSize;
4214 // Copy entire object into memory. There are cases where gcc-generated
4215 // code assumes it is there, even if it could be put entirely into
4216 // registers. (This is not what the doc says.)
4217 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4221 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4222 // copy the pieces of the object that fit into registers from the
4223 // parameter save area.
4224 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4225 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4226 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4227 if (GPR_idx != NumGPRs) {
4228 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4229 MachinePointerInfo(),
4230 false, false, false, 0);
4231 MemOpChains.push_back(Load.getValue(1));
4232 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4233 ArgOffset += PtrByteSize;
4235 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4242 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
4243 default: llvm_unreachable("Unexpected ValueType for argument!");
4246 if (GPR_idx != NumGPRs) {
4247 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4249 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4250 isPPC64, isTailCall, false, MemOpChains,
4251 TailCallArguments, dl);
4253 ArgOffset += PtrByteSize;
4257 if (FPR_idx != NumFPRs) {
4258 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4261 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4262 MachinePointerInfo(), false, false, 0);
4263 MemOpChains.push_back(Store);
4265 // Float varargs are always shadowed in available integer registers
4266 if (GPR_idx != NumGPRs) {
4267 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4268 MachinePointerInfo(), false, false,
4270 MemOpChains.push_back(Load.getValue(1));
4271 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4273 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4274 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4275 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4276 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4277 MachinePointerInfo(),
4278 false, false, false, 0);
4279 MemOpChains.push_back(Load.getValue(1));
4280 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4283 // If we have any FPRs remaining, we may also have GPRs remaining.
4284 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4286 if (GPR_idx != NumGPRs)
4288 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4289 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4293 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4294 isPPC64, isTailCall, false, MemOpChains,
4295 TailCallArguments, dl);
4299 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4306 // These go aligned on the stack, or in the corresponding R registers
4307 // when within range. The Darwin PPC ABI doc claims they also go in
4308 // V registers; in fact gcc does this only for arguments that are
4309 // prototyped, not for those that match the ... We do it for all
4310 // arguments, seems to work.
4311 while (ArgOffset % 16 !=0) {
4312 ArgOffset += PtrByteSize;
4313 if (GPR_idx != NumGPRs)
4316 // We could elide this store in the case where the object fits
4317 // entirely in R registers. Maybe later.
4318 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4319 DAG.getConstant(ArgOffset, PtrVT));
4320 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4321 MachinePointerInfo(), false, false, 0);
4322 MemOpChains.push_back(Store);
4323 if (VR_idx != NumVRs) {
4324 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4325 MachinePointerInfo(),
4326 false, false, false, 0);
4327 MemOpChains.push_back(Load.getValue(1));
4328 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4331 for (unsigned i=0; i<16; i+=PtrByteSize) {
4332 if (GPR_idx == NumGPRs)
4334 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4335 DAG.getConstant(i, PtrVT));
4336 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4337 false, false, false, 0);
4338 MemOpChains.push_back(Load.getValue(1));
4339 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4344 // Non-varargs Altivec params generally go in registers, but have
4345 // stack space allocated at the end.
4346 if (VR_idx != NumVRs) {
4347 // Doesn't have GPR space allocated.
4348 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4349 } else if (nAltivecParamsAtEnd==0) {
4350 // We are emitting Altivec params in order.
4351 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4352 isPPC64, isTailCall, true, MemOpChains,
4353 TailCallArguments, dl);
4359 // If all Altivec parameters fit in registers, as they usually do,
4360 // they get stack space following the non-Altivec parameters. We
4361 // don't track this here because nobody below needs it.
4362 // If there are more Altivec parameters than fit in registers emit
4364 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4366 // Offset is aligned; skip 1st 12 params which go in V registers.
4367 ArgOffset = ((ArgOffset+15)/16)*16;
4369 for (unsigned i = 0; i != NumOps; ++i) {
4370 SDValue Arg = OutVals[i];
4371 EVT ArgType = Outs[i].VT;
4372 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4373 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4376 // We are emitting Altivec params in order.
4377 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4378 isPPC64, isTailCall, true, MemOpChains,
4379 TailCallArguments, dl);
4386 if (!MemOpChains.empty())
4387 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4388 &MemOpChains[0], MemOpChains.size());
4390 // On Darwin, R12 must contain the address of an indirect callee. This does
4391 // not mean the MTCTR instruction must use R12; it's easier to model this as
4392 // an extra parameter, so do that.
4394 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4395 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4396 !isBLACompatibleAddress(Callee, DAG))
4397 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4398 PPC::R12), Callee));
4400 // Build a sequence of copy-to-reg nodes chained together with token chain
4401 // and flag operands which copy the outgoing args into the appropriate regs.
4403 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4404 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4405 RegsToPass[i].second, InFlag);
4406 InFlag = Chain.getValue(1);
4410 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4411 FPOp, true, TailCallArguments);
4413 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4414 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4419 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4420 MachineFunction &MF, bool isVarArg,
4421 const SmallVectorImpl<ISD::OutputArg> &Outs,
4422 LLVMContext &Context) const {
4423 SmallVector<CCValAssign, 16> RVLocs;
4424 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4426 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4430 PPCTargetLowering::LowerReturn(SDValue Chain,
4431 CallingConv::ID CallConv, bool isVarArg,
4432 const SmallVectorImpl<ISD::OutputArg> &Outs,
4433 const SmallVectorImpl<SDValue> &OutVals,
4434 SDLoc dl, SelectionDAG &DAG) const {
4436 SmallVector<CCValAssign, 16> RVLocs;
4437 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4438 getTargetMachine(), RVLocs, *DAG.getContext());
4439 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4442 SmallVector<SDValue, 4> RetOps(1, Chain);
4444 // Copy the result values into the output registers.
4445 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4446 CCValAssign &VA = RVLocs[i];
4447 assert(VA.isRegLoc() && "Can only return in registers!");
4449 SDValue Arg = OutVals[i];
4451 switch (VA.getLocInfo()) {
4452 default: llvm_unreachable("Unknown loc info!");
4453 case CCValAssign::Full: break;
4454 case CCValAssign::AExt:
4455 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4457 case CCValAssign::ZExt:
4458 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4460 case CCValAssign::SExt:
4461 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4465 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4466 Flag = Chain.getValue(1);
4467 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4470 RetOps[0] = Chain; // Update chain.
4472 // Add the flag if we have it.
4474 RetOps.push_back(Flag);
4476 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4477 &RetOps[0], RetOps.size());
4480 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4481 const PPCSubtarget &Subtarget) const {
4482 // When we pop the dynamic allocation we need to restore the SP link.
4485 // Get the corect type for pointers.
4486 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4488 // Construct the stack pointer operand.
4489 bool isPPC64 = Subtarget.isPPC64();
4490 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4491 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4493 // Get the operands for the STACKRESTORE.
4494 SDValue Chain = Op.getOperand(0);
4495 SDValue SaveSP = Op.getOperand(1);
4497 // Load the old link SP.
4498 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4499 MachinePointerInfo(),
4500 false, false, false, 0);
4502 // Restore the stack pointer.
4503 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4505 // Store the old link SP.
4506 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4513 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4514 MachineFunction &MF = DAG.getMachineFunction();
4515 bool isPPC64 = PPCSubTarget.isPPC64();
4516 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4517 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4519 // Get current frame pointer save index. The users of this index will be
4520 // primarily DYNALLOC instructions.
4521 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4522 int RASI = FI->getReturnAddrSaveIndex();
4524 // If the frame pointer save index hasn't been defined yet.
4526 // Find out what the fix offset of the frame pointer save area.
4527 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4528 // Allocate the frame index for frame pointer save area.
4529 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4531 FI->setReturnAddrSaveIndex(RASI);
4533 return DAG.getFrameIndex(RASI, PtrVT);
4537 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4538 MachineFunction &MF = DAG.getMachineFunction();
4539 bool isPPC64 = PPCSubTarget.isPPC64();
4540 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4541 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4543 // Get current frame pointer save index. The users of this index will be
4544 // primarily DYNALLOC instructions.
4545 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4546 int FPSI = FI->getFramePointerSaveIndex();
4548 // If the frame pointer save index hasn't been defined yet.
4550 // Find out what the fix offset of the frame pointer save area.
4551 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4554 // Allocate the frame index for frame pointer save area.
4555 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4557 FI->setFramePointerSaveIndex(FPSI);
4559 return DAG.getFrameIndex(FPSI, PtrVT);
4562 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4564 const PPCSubtarget &Subtarget) const {
4566 SDValue Chain = Op.getOperand(0);
4567 SDValue Size = Op.getOperand(1);
4570 // Get the corect type for pointers.
4571 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4573 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4574 DAG.getConstant(0, PtrVT), Size);
4575 // Construct a node for the frame pointer save index.
4576 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4577 // Build a DYNALLOC node.
4578 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4579 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4580 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
4583 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4584 SelectionDAG &DAG) const {
4586 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4587 DAG.getVTList(MVT::i32, MVT::Other),
4588 Op.getOperand(0), Op.getOperand(1));
4591 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4592 SelectionDAG &DAG) const {
4594 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4595 Op.getOperand(0), Op.getOperand(1));
4598 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4600 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4601 // Not FP? Not a fsel.
4602 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4603 !Op.getOperand(2).getValueType().isFloatingPoint())
4606 // We might be able to do better than this under some circumstances, but in
4607 // general, fsel-based lowering of select is a finite-math-only optimization.
4608 // For more information, see section F.3 of the 2.06 ISA specification.
4609 if (!DAG.getTarget().Options.NoInfsFPMath ||
4610 !DAG.getTarget().Options.NoNaNsFPMath)
4613 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4615 EVT ResVT = Op.getValueType();
4616 EVT CmpVT = Op.getOperand(0).getValueType();
4617 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4618 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4621 // If the RHS of the comparison is a 0.0, we don't need to do the
4622 // subtraction at all.
4624 if (isFloatingPointZero(RHS))
4626 default: break; // SETUO etc aren't handled by fsel.
4630 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4631 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4632 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4633 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4634 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4635 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4636 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
4639 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4642 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4643 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4644 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4647 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4650 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4651 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4652 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4653 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4658 default: break; // SETUO etc aren't handled by fsel.
4662 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4663 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4664 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4665 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4666 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4667 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4668 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4669 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
4672 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4673 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4674 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4675 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4678 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4679 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4680 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4681 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4684 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4685 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4686 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4687 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4690 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4691 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4692 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4693 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4698 // FIXME: Split this code up when LegalizeDAGTypes lands.
4699 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
4701 assert(Op.getOperand(0).getValueType().isFloatingPoint());
4702 SDValue Src = Op.getOperand(0);
4703 if (Src.getValueType() == MVT::f32)
4704 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4707 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4708 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
4710 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4711 (PPCSubTarget.hasFPCVT() ? PPCISD::FCTIWUZ :
4716 assert((Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT()) &&
4717 "i64 FP_TO_UINT is supported only with FPCVT");
4718 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
4724 // Convert the FP value to an int value through memory.
4725 bool i32Stack = Op.getValueType() == MVT::i32 && PPCSubTarget.hasSTFIWX() &&
4726 (Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT());
4727 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
4728 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
4729 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
4731 // Emit a store to the stack slot.
4734 MachineFunction &MF = DAG.getMachineFunction();
4735 MachineMemOperand *MMO =
4736 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
4737 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
4738 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
4739 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
4742 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
4743 MPI, false, false, 0);
4745 // Result is a load from the stack slot. If loading 4 bytes, make sure to
4747 if (Op.getValueType() == MVT::i32 && !i32Stack) {
4748 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
4749 DAG.getConstant(4, FIPtr.getValueType()));
4750 MPI = MachinePointerInfo();
4753 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
4754 false, false, false, 0);
4757 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
4758 SelectionDAG &DAG) const {
4760 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
4761 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4764 assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) &&
4765 "UINT_TO_FP is supported only with FPCVT");
4767 // If we have FCFIDS, then use it when converting to single-precision.
4768 // Otherwise, convert to double-precision and then round.
4769 unsigned FCFOp = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4770 (Op.getOpcode() == ISD::UINT_TO_FP ?
4771 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
4772 (Op.getOpcode() == ISD::UINT_TO_FP ?
4773 PPCISD::FCFIDU : PPCISD::FCFID);
4774 MVT FCFTy = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4775 MVT::f32 : MVT::f64;
4777 if (Op.getOperand(0).getValueType() == MVT::i64) {
4778 SDValue SINT = Op.getOperand(0);
4779 // When converting to single-precision, we actually need to convert
4780 // to double-precision first and then round to single-precision.
4781 // To avoid double-rounding effects during that operation, we have
4782 // to prepare the input operand. Bits that might be truncated when
4783 // converting to double-precision are replaced by a bit that won't
4784 // be lost at this stage, but is below the single-precision rounding
4787 // However, if -enable-unsafe-fp-math is in effect, accept double
4788 // rounding to avoid the extra overhead.
4789 if (Op.getValueType() == MVT::f32 &&
4790 !PPCSubTarget.hasFPCVT() &&
4791 !DAG.getTarget().Options.UnsafeFPMath) {
4793 // Twiddle input to make sure the low 11 bits are zero. (If this
4794 // is the case, we are guaranteed the value will fit into the 53 bit
4795 // mantissa of an IEEE double-precision value without rounding.)
4796 // If any of those low 11 bits were not zero originally, make sure
4797 // bit 12 (value 2048) is set instead, so that the final rounding
4798 // to single-precision gets the correct result.
4799 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4800 SINT, DAG.getConstant(2047, MVT::i64));
4801 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4802 Round, DAG.getConstant(2047, MVT::i64));
4803 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4804 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4805 Round, DAG.getConstant(-2048, MVT::i64));
4807 // However, we cannot use that value unconditionally: if the magnitude
4808 // of the input value is small, the bit-twiddling we did above might
4809 // end up visibly changing the output. Fortunately, in that case, we
4810 // don't need to twiddle bits since the original input will convert
4811 // exactly to double-precision floating-point already. Therefore,
4812 // construct a conditional to use the original value if the top 11
4813 // bits are all sign-bit copies, and use the rounded value computed
4815 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4816 SINT, DAG.getConstant(53, MVT::i32));
4817 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4818 Cond, DAG.getConstant(1, MVT::i64));
4819 Cond = DAG.getSetCC(dl, MVT::i32,
4820 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4822 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4825 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4826 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
4828 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4829 FP = DAG.getNode(ISD::FP_ROUND, dl,
4830 MVT::f32, FP, DAG.getIntPtrConstant(0));
4834 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
4835 "Unhandled INT_TO_FP type in custom expander!");
4836 // Since we only generate this in 64-bit mode, we can take advantage of
4837 // 64-bit registers. In particular, sign extend the input value into the
4838 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
4839 // then lfd it and fcfid it.
4840 MachineFunction &MF = DAG.getMachineFunction();
4841 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
4842 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4845 if (PPCSubTarget.hasLFIWAX() || PPCSubTarget.hasFPCVT()) {
4846 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
4847 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4849 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
4850 MachinePointerInfo::getFixedStack(FrameIdx),
4853 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
4854 "Expected an i32 store");
4855 MachineMemOperand *MMO =
4856 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
4857 MachineMemOperand::MOLoad, 4, 4);
4858 SDValue Ops[] = { Store, FIdx };
4859 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
4860 PPCISD::LFIWZX : PPCISD::LFIWAX,
4861 dl, DAG.getVTList(MVT::f64, MVT::Other),
4862 Ops, 2, MVT::i32, MMO);
4864 assert(PPCSubTarget.isPPC64() &&
4865 "i32->FP without LFIWAX supported only on PPC64");
4867 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
4868 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4870 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
4873 // STD the extended value into the stack slot.
4874 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
4875 MachinePointerInfo::getFixedStack(FrameIdx),
4878 // Load the value as a double.
4879 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
4880 MachinePointerInfo::getFixedStack(FrameIdx),
4881 false, false, false, 0);
4884 // FCFID it and return it.
4885 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
4886 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4887 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
4891 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4892 SelectionDAG &DAG) const {
4895 The rounding mode is in bits 30:31 of FPSR, and has the following
4902 FLT_ROUNDS, on the other hand, expects the following:
4909 To perform the conversion, we do:
4910 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
4913 MachineFunction &MF = DAG.getMachineFunction();
4914 EVT VT = Op.getValueType();
4915 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4916 SDValue MFFSreg, InFlag;
4918 // Save FP Control Word to register
4920 MVT::f64, // return register
4921 MVT::Glue // unused in this context
4923 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4925 // Save FP register to stack slot
4926 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
4927 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
4928 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
4929 StackSlot, MachinePointerInfo(), false, false,0);
4931 // Load FP Control Word from low 32 bits of stack slot.
4932 SDValue Four = DAG.getConstant(4, PtrVT);
4933 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
4934 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
4935 false, false, false, 0);
4937 // Transform as necessary
4939 DAG.getNode(ISD::AND, dl, MVT::i32,
4940 CWD, DAG.getConstant(3, MVT::i32));
4942 DAG.getNode(ISD::SRL, dl, MVT::i32,
4943 DAG.getNode(ISD::AND, dl, MVT::i32,
4944 DAG.getNode(ISD::XOR, dl, MVT::i32,
4945 CWD, DAG.getConstant(3, MVT::i32)),
4946 DAG.getConstant(3, MVT::i32)),
4947 DAG.getConstant(1, MVT::i32));
4950 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
4952 return DAG.getNode((VT.getSizeInBits() < 16 ?
4953 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
4956 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
4957 EVT VT = Op.getValueType();
4958 unsigned BitWidth = VT.getSizeInBits();
4960 assert(Op.getNumOperands() == 3 &&
4961 VT == Op.getOperand(1).getValueType() &&
4964 // Expand into a bunch of logical ops. Note that these ops
4965 // depend on the PPC behavior for oversized shift amounts.
4966 SDValue Lo = Op.getOperand(0);
4967 SDValue Hi = Op.getOperand(1);
4968 SDValue Amt = Op.getOperand(2);
4969 EVT AmtVT = Amt.getValueType();
4971 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
4972 DAG.getConstant(BitWidth, AmtVT), Amt);
4973 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
4974 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
4975 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
4976 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
4977 DAG.getConstant(-BitWidth, AmtVT));
4978 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
4979 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
4980 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
4981 SDValue OutOps[] = { OutLo, OutHi };
4982 return DAG.getMergeValues(OutOps, 2, dl);
4985 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
4986 EVT VT = Op.getValueType();
4988 unsigned BitWidth = VT.getSizeInBits();
4989 assert(Op.getNumOperands() == 3 &&
4990 VT == Op.getOperand(1).getValueType() &&
4993 // Expand into a bunch of logical ops. Note that these ops
4994 // depend on the PPC behavior for oversized shift amounts.
4995 SDValue Lo = Op.getOperand(0);
4996 SDValue Hi = Op.getOperand(1);
4997 SDValue Amt = Op.getOperand(2);
4998 EVT AmtVT = Amt.getValueType();
5000 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5001 DAG.getConstant(BitWidth, AmtVT), Amt);
5002 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5003 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5004 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5005 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5006 DAG.getConstant(-BitWidth, AmtVT));
5007 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5008 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5009 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5010 SDValue OutOps[] = { OutLo, OutHi };
5011 return DAG.getMergeValues(OutOps, 2, dl);
5014 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5016 EVT VT = Op.getValueType();
5017 unsigned BitWidth = VT.getSizeInBits();
5018 assert(Op.getNumOperands() == 3 &&
5019 VT == Op.getOperand(1).getValueType() &&
5022 // Expand into a bunch of logical ops, followed by a select_cc.
5023 SDValue Lo = Op.getOperand(0);
5024 SDValue Hi = Op.getOperand(1);
5025 SDValue Amt = Op.getOperand(2);
5026 EVT AmtVT = Amt.getValueType();
5028 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5029 DAG.getConstant(BitWidth, AmtVT), Amt);
5030 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5031 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5032 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5033 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5034 DAG.getConstant(-BitWidth, AmtVT));
5035 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5036 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5037 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5038 Tmp4, Tmp6, ISD::SETLE);
5039 SDValue OutOps[] = { OutLo, OutHi };
5040 return DAG.getMergeValues(OutOps, 2, dl);
5043 //===----------------------------------------------------------------------===//
5044 // Vector related lowering.
5047 /// BuildSplatI - Build a canonical splati of Val with an element size of
5048 /// SplatSize. Cast the result to VT.
5049 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5050 SelectionDAG &DAG, SDLoc dl) {
5051 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5053 static const EVT VTys[] = { // canonical VT to use for each size.
5054 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5057 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5059 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5063 EVT CanonicalVT = VTys[SplatSize-1];
5065 // Build a canonical splat for this value.
5066 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5067 SmallVector<SDValue, 8> Ops;
5068 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5069 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
5070 &Ops[0], Ops.size());
5071 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5074 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5075 /// specified intrinsic ID.
5076 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5077 SelectionDAG &DAG, SDLoc dl,
5078 EVT DestVT = MVT::Other) {
5079 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5080 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5081 DAG.getConstant(IID, MVT::i32), Op);
5084 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5085 /// specified intrinsic ID.
5086 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5087 SelectionDAG &DAG, SDLoc dl,
5088 EVT DestVT = MVT::Other) {
5089 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5090 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5091 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5094 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5095 /// specified intrinsic ID.
5096 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5097 SDValue Op2, SelectionDAG &DAG,
5098 SDLoc dl, EVT DestVT = MVT::Other) {
5099 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5100 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5101 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5105 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5106 /// amount. The result has the specified value type.
5107 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5108 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5109 // Force LHS/RHS to be the right type.
5110 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5111 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5114 for (unsigned i = 0; i != 16; ++i)
5116 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5117 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5120 // If this is a case we can't handle, return null and let the default
5121 // expansion code take care of it. If we CAN select this case, and if it
5122 // selects to a single instruction, return Op. Otherwise, if we can codegen
5123 // this case more efficiently than a constant pool load, lower it to the
5124 // sequence of ops that should be used.
5125 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5126 SelectionDAG &DAG) const {
5128 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5129 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5131 // Check if this is a splat of a constant value.
5132 APInt APSplatBits, APSplatUndef;
5133 unsigned SplatBitSize;
5135 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5136 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5139 unsigned SplatBits = APSplatBits.getZExtValue();
5140 unsigned SplatUndef = APSplatUndef.getZExtValue();
5141 unsigned SplatSize = SplatBitSize / 8;
5143 // First, handle single instruction cases.
5146 if (SplatBits == 0) {
5147 // Canonicalize all zero vectors to be v4i32.
5148 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5149 SDValue Z = DAG.getConstant(0, MVT::i32);
5150 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5151 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5156 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5157 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5159 if (SextVal >= -16 && SextVal <= 15)
5160 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5163 // Two instruction sequences.
5165 // If this value is in the range [-32,30] and is even, use:
5166 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5167 // If this value is in the range [17,31] and is odd, use:
5168 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5169 // If this value is in the range [-31,-17] and is odd, use:
5170 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5171 // Note the last two are three-instruction sequences.
5172 if (SextVal >= -32 && SextVal <= 31) {
5173 // To avoid having these optimizations undone by constant folding,
5174 // we convert to a pseudo that will be expanded later into one of
5176 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5177 EVT VT = Op.getValueType();
5178 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5179 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5180 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5183 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5184 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5186 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5187 // Make -1 and vspltisw -1:
5188 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5190 // Make the VSLW intrinsic, computing 0x8000_0000.
5191 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5194 // xor by OnesV to invert it.
5195 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5196 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5199 // Check to see if this is a wide variety of vsplti*, binop self cases.
5200 static const signed char SplatCsts[] = {
5201 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5202 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5205 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5206 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5207 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5208 int i = SplatCsts[idx];
5210 // Figure out what shift amount will be used by altivec if shifted by i in
5212 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5214 // vsplti + shl self.
5215 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5216 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5217 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5218 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5219 Intrinsic::ppc_altivec_vslw
5221 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5222 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5225 // vsplti + srl self.
5226 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5227 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5228 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5229 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5230 Intrinsic::ppc_altivec_vsrw
5232 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5233 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5236 // vsplti + sra self.
5237 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5238 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5239 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5240 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5241 Intrinsic::ppc_altivec_vsraw
5243 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5244 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5247 // vsplti + rol self.
5248 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5249 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5250 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5251 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5252 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5253 Intrinsic::ppc_altivec_vrlw
5255 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5256 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5259 // t = vsplti c, result = vsldoi t, t, 1
5260 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5261 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5262 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5264 // t = vsplti c, result = vsldoi t, t, 2
5265 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5266 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5267 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5269 // t = vsplti c, result = vsldoi t, t, 3
5270 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5271 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5272 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5279 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5280 /// the specified operations to build the shuffle.
5281 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5282 SDValue RHS, SelectionDAG &DAG,
5284 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5285 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5286 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5289 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5301 if (OpNum == OP_COPY) {
5302 if (LHSID == (1*9+2)*9+3) return LHS;
5303 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5307 SDValue OpLHS, OpRHS;
5308 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5309 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5313 default: llvm_unreachable("Unknown i32 permute!");
5315 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5316 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5317 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5318 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5321 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5322 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5323 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5324 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5327 for (unsigned i = 0; i != 16; ++i)
5328 ShufIdxs[i] = (i&3)+0;
5331 for (unsigned i = 0; i != 16; ++i)
5332 ShufIdxs[i] = (i&3)+4;
5335 for (unsigned i = 0; i != 16; ++i)
5336 ShufIdxs[i] = (i&3)+8;
5339 for (unsigned i = 0; i != 16; ++i)
5340 ShufIdxs[i] = (i&3)+12;
5343 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5345 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5347 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5349 EVT VT = OpLHS.getValueType();
5350 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5351 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5352 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5353 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5356 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5357 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5358 /// return the code it can be lowered into. Worst case, it can always be
5359 /// lowered into a vperm.
5360 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5361 SelectionDAG &DAG) const {
5363 SDValue V1 = Op.getOperand(0);
5364 SDValue V2 = Op.getOperand(1);
5365 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5366 EVT VT = Op.getValueType();
5368 // Cases that are handled by instructions that take permute immediates
5369 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5370 // selected by the instruction selector.
5371 if (V2.getOpcode() == ISD::UNDEF) {
5372 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5373 PPC::isSplatShuffleMask(SVOp, 2) ||
5374 PPC::isSplatShuffleMask(SVOp, 4) ||
5375 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5376 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5377 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5378 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5379 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5380 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5381 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5382 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5383 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5388 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5389 // and produce a fixed permutation. If any of these match, do not lower to
5391 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5392 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5393 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5394 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5395 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5396 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5397 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5398 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5399 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5402 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5403 // perfect shuffle table to emit an optimal matching sequence.
5404 ArrayRef<int> PermMask = SVOp->getMask();
5406 unsigned PFIndexes[4];
5407 bool isFourElementShuffle = true;
5408 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5409 unsigned EltNo = 8; // Start out undef.
5410 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5411 if (PermMask[i*4+j] < 0)
5412 continue; // Undef, ignore it.
5414 unsigned ByteSource = PermMask[i*4+j];
5415 if ((ByteSource & 3) != j) {
5416 isFourElementShuffle = false;
5421 EltNo = ByteSource/4;
5422 } else if (EltNo != ByteSource/4) {
5423 isFourElementShuffle = false;
5427 PFIndexes[i] = EltNo;
5430 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5431 // perfect shuffle vector to determine if it is cost effective to do this as
5432 // discrete instructions, or whether we should use a vperm.
5433 if (isFourElementShuffle) {
5434 // Compute the index in the perfect shuffle table.
5435 unsigned PFTableIndex =
5436 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5438 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5439 unsigned Cost = (PFEntry >> 30);
5441 // Determining when to avoid vperm is tricky. Many things affect the cost
5442 // of vperm, particularly how many times the perm mask needs to be computed.
5443 // For example, if the perm mask can be hoisted out of a loop or is already
5444 // used (perhaps because there are multiple permutes with the same shuffle
5445 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5446 // the loop requires an extra register.
5448 // As a compromise, we only emit discrete instructions if the shuffle can be
5449 // generated in 3 or fewer operations. When we have loop information
5450 // available, if this block is within a loop, we should avoid using vperm
5451 // for 3-operation perms and use a constant pool load instead.
5453 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5456 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5457 // vector that will get spilled to the constant pool.
5458 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5460 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5461 // that it is in input element units, not in bytes. Convert now.
5462 EVT EltVT = V1.getValueType().getVectorElementType();
5463 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5465 SmallVector<SDValue, 16> ResultMask;
5466 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5467 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5469 for (unsigned j = 0; j != BytesPerElement; ++j)
5470 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5474 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5475 &ResultMask[0], ResultMask.size());
5476 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5479 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5480 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5481 /// information about the intrinsic.
5482 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5484 unsigned IntrinsicID =
5485 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5488 switch (IntrinsicID) {
5489 default: return false;
5490 // Comparison predicates.
5491 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5492 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5493 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5494 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5495 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5496 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5497 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5498 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5499 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5500 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5501 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5502 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5503 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5505 // Normal Comparisons.
5506 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5507 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5508 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5509 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5510 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5511 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5512 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5513 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5514 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5515 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5516 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5517 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5518 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5523 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5524 /// lower, do it, otherwise return null.
5525 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5526 SelectionDAG &DAG) const {
5527 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5528 // opcode number of the comparison.
5532 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5533 return SDValue(); // Don't custom lower most intrinsics.
5535 // If this is a non-dot comparison, make the VCMP node and we are done.
5537 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5538 Op.getOperand(1), Op.getOperand(2),
5539 DAG.getConstant(CompareOpc, MVT::i32));
5540 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5543 // Create the PPCISD altivec 'dot' comparison node.
5545 Op.getOperand(2), // LHS
5546 Op.getOperand(3), // RHS
5547 DAG.getConstant(CompareOpc, MVT::i32)
5549 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5550 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5552 // Now that we have the comparison, emit a copy from the CR to a GPR.
5553 // This is flagged to the above dot comparison.
5554 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
5555 DAG.getRegister(PPC::CR6, MVT::i32),
5556 CompNode.getValue(1));
5558 // Unpack the result based on how the target uses it.
5559 unsigned BitNo; // Bit # of CR6.
5560 bool InvertBit; // Invert result?
5561 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5562 default: // Can't happen, don't crash on invalid number though.
5563 case 0: // Return the value of the EQ bit of CR6.
5564 BitNo = 0; InvertBit = false;
5566 case 1: // Return the inverted value of the EQ bit of CR6.
5567 BitNo = 0; InvertBit = true;
5569 case 2: // Return the value of the LT bit of CR6.
5570 BitNo = 2; InvertBit = false;
5572 case 3: // Return the inverted value of the LT bit of CR6.
5573 BitNo = 2; InvertBit = true;
5577 // Shift the bit into the low position.
5578 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5579 DAG.getConstant(8-(3-BitNo), MVT::i32));
5581 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5582 DAG.getConstant(1, MVT::i32));
5584 // If we are supposed to, toggle the bit.
5586 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5587 DAG.getConstant(1, MVT::i32));
5591 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5592 SelectionDAG &DAG) const {
5594 // Create a stack slot that is 16-byte aligned.
5595 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5596 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5597 EVT PtrVT = getPointerTy();
5598 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5600 // Store the input value into Value#0 of the stack slot.
5601 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5602 Op.getOperand(0), FIdx, MachinePointerInfo(),
5605 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5606 false, false, false, 0);
5609 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5611 if (Op.getValueType() == MVT::v4i32) {
5612 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5614 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5615 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5617 SDValue RHSSwap = // = vrlw RHS, 16
5618 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
5620 // Shrinkify inputs to v8i16.
5621 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5622 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5623 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5625 // Low parts multiplied together, generating 32-bit results (we ignore the
5627 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
5628 LHS, RHS, DAG, dl, MVT::v4i32);
5630 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
5631 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5632 // Shift the high parts up 16 bits.
5633 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
5635 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5636 } else if (Op.getValueType() == MVT::v8i16) {
5637 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5639 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5641 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
5642 LHS, RHS, Zero, DAG, dl);
5643 } else if (Op.getValueType() == MVT::v16i8) {
5644 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5646 // Multiply the even 8-bit parts, producing 16-bit sums.
5647 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
5648 LHS, RHS, DAG, dl, MVT::v8i16);
5649 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5651 // Multiply the odd 8-bit parts, producing 16-bit sums.
5652 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
5653 LHS, RHS, DAG, dl, MVT::v8i16);
5654 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5656 // Merge the results together.
5658 for (unsigned i = 0; i != 8; ++i) {
5660 Ops[i*2+1] = 2*i+1+16;
5662 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5664 llvm_unreachable("Unknown mul to lower!");
5668 /// LowerOperation - Provide custom lowering hooks for some operations.
5670 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5671 switch (Op.getOpcode()) {
5672 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
5673 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5674 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5675 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5676 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5677 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5678 case ISD::SETCC: return LowerSETCC(Op, DAG);
5679 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
5680 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
5682 return LowerVASTART(Op, DAG, PPCSubTarget);
5685 return LowerVAARG(Op, DAG, PPCSubTarget);
5687 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
5688 case ISD::DYNAMIC_STACKALLOC:
5689 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
5691 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
5692 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
5694 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5695 case ISD::FP_TO_UINT:
5696 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
5698 case ISD::UINT_TO_FP:
5699 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
5700 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5702 // Lower 64-bit shifts.
5703 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
5704 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
5705 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
5707 // Vector-related lowering.
5708 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5709 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5710 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5711 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5712 case ISD::MUL: return LowerMUL(Op, DAG);
5714 // For counter-based loop handling.
5715 case ISD::INTRINSIC_W_CHAIN: return SDValue();
5717 // Frame & Return address.
5718 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5719 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5723 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
5724 SmallVectorImpl<SDValue>&Results,
5725 SelectionDAG &DAG) const {
5726 const TargetMachine &TM = getTargetMachine();
5728 switch (N->getOpcode()) {
5730 llvm_unreachable("Do not know how to custom type legalize this operation!");
5731 case ISD::INTRINSIC_W_CHAIN: {
5732 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
5733 Intrinsic::ppc_is_decremented_ctr_nonzero)
5736 assert(N->getValueType(0) == MVT::i1 &&
5737 "Unexpected result type for CTR decrement intrinsic");
5738 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
5739 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
5740 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
5743 Results.push_back(NewInt);
5744 Results.push_back(NewInt.getValue(1));
5748 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
5749 || TM.getSubtarget<PPCSubtarget>().isPPC64())
5752 EVT VT = N->getValueType(0);
5754 if (VT == MVT::i64) {
5755 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
5757 Results.push_back(NewNode);
5758 Results.push_back(NewNode.getValue(1));
5762 case ISD::FP_ROUND_INREG: {
5763 assert(N->getValueType(0) == MVT::ppcf128);
5764 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5765 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5766 MVT::f64, N->getOperand(0),
5767 DAG.getIntPtrConstant(0));
5768 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5769 MVT::f64, N->getOperand(0),
5770 DAG.getIntPtrConstant(1));
5772 // Add the two halves of the long double in round-to-zero mode.
5773 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
5775 // We know the low half is about to be thrown away, so just use something
5777 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5781 case ISD::FP_TO_SINT:
5782 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
5788 //===----------------------------------------------------------------------===//
5789 // Other Lowering Code
5790 //===----------------------------------------------------------------------===//
5793 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5794 bool is64bit, unsigned BinOpcode) const {
5795 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5796 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5798 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5799 MachineFunction *F = BB->getParent();
5800 MachineFunction::iterator It = BB;
5803 unsigned dest = MI->getOperand(0).getReg();
5804 unsigned ptrA = MI->getOperand(1).getReg();
5805 unsigned ptrB = MI->getOperand(2).getReg();
5806 unsigned incr = MI->getOperand(3).getReg();
5807 DebugLoc dl = MI->getDebugLoc();
5809 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5810 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5811 F->insert(It, loopMBB);
5812 F->insert(It, exitMBB);
5813 exitMBB->splice(exitMBB->begin(), BB,
5814 llvm::next(MachineBasicBlock::iterator(MI)),
5816 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5818 MachineRegisterInfo &RegInfo = F->getRegInfo();
5819 unsigned TmpReg = (!BinOpcode) ? incr :
5820 RegInfo.createVirtualRegister(
5821 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5822 (const TargetRegisterClass *) &PPC::GPRCRegClass);
5826 // fallthrough --> loopMBB
5827 BB->addSuccessor(loopMBB);
5830 // l[wd]arx dest, ptr
5831 // add r0, dest, incr
5832 // st[wd]cx. r0, ptr
5834 // fallthrough --> exitMBB
5836 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5837 .addReg(ptrA).addReg(ptrB);
5839 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
5840 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5841 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
5842 BuildMI(BB, dl, TII->get(PPC::BCC))
5843 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5844 BB->addSuccessor(loopMBB);
5845 BB->addSuccessor(exitMBB);
5854 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
5855 MachineBasicBlock *BB,
5856 bool is8bit, // operation
5857 unsigned BinOpcode) const {
5858 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5859 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5860 // In 64 bit mode we have to use 64 bits for addresses, even though the
5861 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
5862 // registers without caring whether they're 32 or 64, but here we're
5863 // doing actual arithmetic on the addresses.
5864 bool is64bit = PPCSubTarget.isPPC64();
5865 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
5867 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5868 MachineFunction *F = BB->getParent();
5869 MachineFunction::iterator It = BB;
5872 unsigned dest = MI->getOperand(0).getReg();
5873 unsigned ptrA = MI->getOperand(1).getReg();
5874 unsigned ptrB = MI->getOperand(2).getReg();
5875 unsigned incr = MI->getOperand(3).getReg();
5876 DebugLoc dl = MI->getDebugLoc();
5878 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5879 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5880 F->insert(It, loopMBB);
5881 F->insert(It, exitMBB);
5882 exitMBB->splice(exitMBB->begin(), BB,
5883 llvm::next(MachineBasicBlock::iterator(MI)),
5885 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5887 MachineRegisterInfo &RegInfo = F->getRegInfo();
5888 const TargetRegisterClass *RC =
5889 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5890 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5891 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5892 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5893 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5894 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
5895 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
5896 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
5897 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
5898 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
5899 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
5900 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
5901 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
5903 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
5907 // fallthrough --> loopMBB
5908 BB->addSuccessor(loopMBB);
5910 // The 4-byte load must be aligned, while a char or short may be
5911 // anywhere in the word. Hence all this nasty bookkeeping code.
5912 // add ptr1, ptrA, ptrB [copy if ptrA==0]
5913 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
5914 // xori shift, shift1, 24 [16]
5915 // rlwinm ptr, ptr1, 0, 0, 29
5916 // slw incr2, incr, shift
5917 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
5918 // slw mask, mask2, shift
5920 // lwarx tmpDest, ptr
5921 // add tmp, tmpDest, incr2
5922 // andc tmp2, tmpDest, mask
5923 // and tmp3, tmp, mask
5924 // or tmp4, tmp3, tmp2
5927 // fallthrough --> exitMBB
5928 // srw dest, tmpDest, shift
5929 if (ptrA != ZeroReg) {
5930 Ptr1Reg = RegInfo.createVirtualRegister(RC);
5931 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
5932 .addReg(ptrA).addReg(ptrB);
5936 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5937 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
5938 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5939 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
5941 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
5942 .addReg(Ptr1Reg).addImm(0).addImm(61);
5944 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
5945 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
5946 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
5947 .addReg(incr).addReg(ShiftReg);
5949 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
5951 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
5952 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
5954 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
5955 .addReg(Mask2Reg).addReg(ShiftReg);
5958 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
5959 .addReg(ZeroReg).addReg(PtrReg);
5961 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
5962 .addReg(Incr2Reg).addReg(TmpDestReg);
5963 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
5964 .addReg(TmpDestReg).addReg(MaskReg);
5965 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
5966 .addReg(TmpReg).addReg(MaskReg);
5967 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
5968 .addReg(Tmp3Reg).addReg(Tmp2Reg);
5969 BuildMI(BB, dl, TII->get(PPC::STWCX))
5970 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
5971 BuildMI(BB, dl, TII->get(PPC::BCC))
5972 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5973 BB->addSuccessor(loopMBB);
5974 BB->addSuccessor(exitMBB);
5979 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
5984 llvm::MachineBasicBlock*
5985 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
5986 MachineBasicBlock *MBB) const {
5987 DebugLoc DL = MI->getDebugLoc();
5988 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5990 MachineFunction *MF = MBB->getParent();
5991 MachineRegisterInfo &MRI = MF->getRegInfo();
5993 const BasicBlock *BB = MBB->getBasicBlock();
5994 MachineFunction::iterator I = MBB;
5998 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
5999 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6001 unsigned DstReg = MI->getOperand(0).getReg();
6002 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6003 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6004 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6005 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6007 MVT PVT = getPointerTy();
6008 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6009 "Invalid Pointer Size!");
6010 // For v = setjmp(buf), we generate
6013 // SjLjSetup mainMBB
6019 // buf[LabelOffset] = LR
6023 // v = phi(main, restore)
6026 MachineBasicBlock *thisMBB = MBB;
6027 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6028 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6029 MF->insert(I, mainMBB);
6030 MF->insert(I, sinkMBB);
6032 MachineInstrBuilder MIB;
6034 // Transfer the remainder of BB and its successor edges to sinkMBB.
6035 sinkMBB->splice(sinkMBB->begin(), MBB,
6036 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
6037 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6039 // Note that the structure of the jmp_buf used here is not compatible
6040 // with that used by libc, and is not designed to be. Specifically, it
6041 // stores only those 'reserved' registers that LLVM does not otherwise
6042 // understand how to spill. Also, by convention, by the time this
6043 // intrinsic is called, Clang has already stored the frame address in the
6044 // first slot of the buffer and stack address in the third. Following the
6045 // X86 target code, we'll store the jump address in the second slot. We also
6046 // need to save the TOC pointer (R2) to handle jumps between shared
6047 // libraries, and that will be stored in the fourth slot. The thread
6048 // identifier (R13) is not affected.
6051 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6052 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6054 // Prepare IP either in reg.
6055 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6056 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6057 unsigned BufReg = MI->getOperand(1).getReg();
6059 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) {
6060 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6065 MIB.setMemRefs(MMOBegin, MMOEnd);
6069 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6070 MIB.addRegMask(PPCRegInfo->getNoPreservedMask());
6072 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6074 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6076 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6078 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6079 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6083 MIB = BuildMI(mainMBB, DL,
6084 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6087 if (PPCSubTarget.isPPC64()) {
6088 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6090 .addImm(LabelOffset)
6093 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6095 .addImm(LabelOffset)
6099 MIB.setMemRefs(MMOBegin, MMOEnd);
6101 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6102 mainMBB->addSuccessor(sinkMBB);
6105 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6106 TII->get(PPC::PHI), DstReg)
6107 .addReg(mainDstReg).addMBB(mainMBB)
6108 .addReg(restoreDstReg).addMBB(thisMBB);
6110 MI->eraseFromParent();
6115 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6116 MachineBasicBlock *MBB) const {
6117 DebugLoc DL = MI->getDebugLoc();
6118 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6120 MachineFunction *MF = MBB->getParent();
6121 MachineRegisterInfo &MRI = MF->getRegInfo();
6124 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6125 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6127 MVT PVT = getPointerTy();
6128 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6129 "Invalid Pointer Size!");
6131 const TargetRegisterClass *RC =
6132 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6133 unsigned Tmp = MRI.createVirtualRegister(RC);
6134 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6135 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6136 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6138 MachineInstrBuilder MIB;
6140 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6141 const int64_t SPOffset = 2 * PVT.getStoreSize();
6142 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6144 unsigned BufReg = MI->getOperand(0).getReg();
6146 // Reload FP (the jumped-to function may not have had a
6147 // frame pointer, and if so, then its r31 will be restored
6149 if (PVT == MVT::i64) {
6150 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6154 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6158 MIB.setMemRefs(MMOBegin, MMOEnd);
6161 if (PVT == MVT::i64) {
6162 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6163 .addImm(LabelOffset)
6166 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6167 .addImm(LabelOffset)
6170 MIB.setMemRefs(MMOBegin, MMOEnd);
6173 if (PVT == MVT::i64) {
6174 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6178 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6182 MIB.setMemRefs(MMOBegin, MMOEnd);
6184 // FIXME: When we also support base pointers, that register must also be
6188 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6189 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6193 MIB.setMemRefs(MMOBegin, MMOEnd);
6197 BuildMI(*MBB, MI, DL,
6198 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6199 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6201 MI->eraseFromParent();
6206 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6207 MachineBasicBlock *BB) const {
6208 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6209 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6210 return emitEHSjLjSetJmp(MI, BB);
6211 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6212 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6213 return emitEHSjLjLongJmp(MI, BB);
6216 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6218 // To "insert" these instructions we actually have to insert their
6219 // control-flow patterns.
6220 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6221 MachineFunction::iterator It = BB;
6224 MachineFunction *F = BB->getParent();
6226 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6227 MI->getOpcode() == PPC::SELECT_CC_I8)) {
6228 SmallVector<MachineOperand, 2> Cond;
6229 Cond.push_back(MI->getOperand(4));
6230 Cond.push_back(MI->getOperand(1));
6232 DebugLoc dl = MI->getDebugLoc();
6233 PPCII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(), Cond,
6234 MI->getOperand(2).getReg(), MI->getOperand(3).getReg());
6235 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6236 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6237 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6238 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6239 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
6242 // The incoming instruction knows the destination vreg to set, the
6243 // condition code register to branch on, the true/false values to
6244 // select between, and a branch opcode to use.
6249 // cmpTY ccX, r1, r2
6251 // fallthrough --> copy0MBB
6252 MachineBasicBlock *thisMBB = BB;
6253 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6254 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6255 unsigned SelectPred = MI->getOperand(4).getImm();
6256 DebugLoc dl = MI->getDebugLoc();
6257 F->insert(It, copy0MBB);
6258 F->insert(It, sinkMBB);
6260 // Transfer the remainder of BB and its successor edges to sinkMBB.
6261 sinkMBB->splice(sinkMBB->begin(), BB,
6262 llvm::next(MachineBasicBlock::iterator(MI)),
6264 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6266 // Next, add the true and fallthrough blocks as its successors.
6267 BB->addSuccessor(copy0MBB);
6268 BB->addSuccessor(sinkMBB);
6270 BuildMI(BB, dl, TII->get(PPC::BCC))
6271 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6274 // %FalseValue = ...
6275 // # fallthrough to sinkMBB
6278 // Update machine-CFG edges
6279 BB->addSuccessor(sinkMBB);
6282 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6285 BuildMI(*BB, BB->begin(), dl,
6286 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6287 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6288 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6290 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6291 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6292 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6293 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6294 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6295 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6296 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6297 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6299 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6300 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6301 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6302 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6303 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6304 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6305 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6306 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6308 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6309 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6310 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6311 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6312 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6313 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6314 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6315 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6317 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6318 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6319 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6320 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6321 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6322 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6323 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6324 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6326 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6327 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6328 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6329 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6330 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6331 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6332 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6333 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6335 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6336 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6337 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6338 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6339 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6340 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6341 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6342 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6344 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6345 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6346 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6347 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6348 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6349 BB = EmitAtomicBinary(MI, BB, false, 0);
6350 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6351 BB = EmitAtomicBinary(MI, BB, true, 0);
6353 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6354 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6355 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6357 unsigned dest = MI->getOperand(0).getReg();
6358 unsigned ptrA = MI->getOperand(1).getReg();
6359 unsigned ptrB = MI->getOperand(2).getReg();
6360 unsigned oldval = MI->getOperand(3).getReg();
6361 unsigned newval = MI->getOperand(4).getReg();
6362 DebugLoc dl = MI->getDebugLoc();
6364 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6365 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6366 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6367 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6368 F->insert(It, loop1MBB);
6369 F->insert(It, loop2MBB);
6370 F->insert(It, midMBB);
6371 F->insert(It, exitMBB);
6372 exitMBB->splice(exitMBB->begin(), BB,
6373 llvm::next(MachineBasicBlock::iterator(MI)),
6375 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6379 // fallthrough --> loopMBB
6380 BB->addSuccessor(loop1MBB);
6383 // l[wd]arx dest, ptr
6384 // cmp[wd] dest, oldval
6387 // st[wd]cx. newval, ptr
6391 // st[wd]cx. dest, ptr
6394 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6395 .addReg(ptrA).addReg(ptrB);
6396 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6397 .addReg(oldval).addReg(dest);
6398 BuildMI(BB, dl, TII->get(PPC::BCC))
6399 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6400 BB->addSuccessor(loop2MBB);
6401 BB->addSuccessor(midMBB);
6404 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6405 .addReg(newval).addReg(ptrA).addReg(ptrB);
6406 BuildMI(BB, dl, TII->get(PPC::BCC))
6407 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6408 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6409 BB->addSuccessor(loop1MBB);
6410 BB->addSuccessor(exitMBB);
6413 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6414 .addReg(dest).addReg(ptrA).addReg(ptrB);
6415 BB->addSuccessor(exitMBB);
6420 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6421 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6422 // We must use 64-bit registers for addresses when targeting 64-bit,
6423 // since we're actually doing arithmetic on them. Other registers
6425 bool is64bit = PPCSubTarget.isPPC64();
6426 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6428 unsigned dest = MI->getOperand(0).getReg();
6429 unsigned ptrA = MI->getOperand(1).getReg();
6430 unsigned ptrB = MI->getOperand(2).getReg();
6431 unsigned oldval = MI->getOperand(3).getReg();
6432 unsigned newval = MI->getOperand(4).getReg();
6433 DebugLoc dl = MI->getDebugLoc();
6435 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6436 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6437 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6438 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6439 F->insert(It, loop1MBB);
6440 F->insert(It, loop2MBB);
6441 F->insert(It, midMBB);
6442 F->insert(It, exitMBB);
6443 exitMBB->splice(exitMBB->begin(), BB,
6444 llvm::next(MachineBasicBlock::iterator(MI)),
6446 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6448 MachineRegisterInfo &RegInfo = F->getRegInfo();
6449 const TargetRegisterClass *RC =
6450 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6451 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6452 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6453 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6454 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6455 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6456 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6457 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6458 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6459 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6460 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6461 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6462 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6463 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6464 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6466 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6467 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6470 // fallthrough --> loopMBB
6471 BB->addSuccessor(loop1MBB);
6473 // The 4-byte load must be aligned, while a char or short may be
6474 // anywhere in the word. Hence all this nasty bookkeeping code.
6475 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6476 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6477 // xori shift, shift1, 24 [16]
6478 // rlwinm ptr, ptr1, 0, 0, 29
6479 // slw newval2, newval, shift
6480 // slw oldval2, oldval,shift
6481 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6482 // slw mask, mask2, shift
6483 // and newval3, newval2, mask
6484 // and oldval3, oldval2, mask
6486 // lwarx tmpDest, ptr
6487 // and tmp, tmpDest, mask
6488 // cmpw tmp, oldval3
6491 // andc tmp2, tmpDest, mask
6492 // or tmp4, tmp2, newval3
6497 // stwcx. tmpDest, ptr
6499 // srw dest, tmpDest, shift
6500 if (ptrA != ZeroReg) {
6501 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6502 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6503 .addReg(ptrA).addReg(ptrB);
6507 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6508 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6509 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6510 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6512 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6513 .addReg(Ptr1Reg).addImm(0).addImm(61);
6515 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6516 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6517 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6518 .addReg(newval).addReg(ShiftReg);
6519 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6520 .addReg(oldval).addReg(ShiftReg);
6522 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6524 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6525 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6526 .addReg(Mask3Reg).addImm(65535);
6528 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6529 .addReg(Mask2Reg).addReg(ShiftReg);
6530 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6531 .addReg(NewVal2Reg).addReg(MaskReg);
6532 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6533 .addReg(OldVal2Reg).addReg(MaskReg);
6536 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6537 .addReg(ZeroReg).addReg(PtrReg);
6538 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6539 .addReg(TmpDestReg).addReg(MaskReg);
6540 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6541 .addReg(TmpReg).addReg(OldVal3Reg);
6542 BuildMI(BB, dl, TII->get(PPC::BCC))
6543 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6544 BB->addSuccessor(loop2MBB);
6545 BB->addSuccessor(midMBB);
6548 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6549 .addReg(TmpDestReg).addReg(MaskReg);
6550 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6551 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6552 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6553 .addReg(ZeroReg).addReg(PtrReg);
6554 BuildMI(BB, dl, TII->get(PPC::BCC))
6555 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6556 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6557 BB->addSuccessor(loop1MBB);
6558 BB->addSuccessor(exitMBB);
6561 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
6562 .addReg(ZeroReg).addReg(PtrReg);
6563 BB->addSuccessor(exitMBB);
6568 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
6570 } else if (MI->getOpcode() == PPC::FADDrtz) {
6571 // This pseudo performs an FADD with rounding mode temporarily forced
6572 // to round-to-zero. We emit this via custom inserter since the FPSCR
6573 // is not modeled at the SelectionDAG level.
6574 unsigned Dest = MI->getOperand(0).getReg();
6575 unsigned Src1 = MI->getOperand(1).getReg();
6576 unsigned Src2 = MI->getOperand(2).getReg();
6577 DebugLoc dl = MI->getDebugLoc();
6579 MachineRegisterInfo &RegInfo = F->getRegInfo();
6580 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
6582 // Save FPSCR value.
6583 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
6585 // Set rounding mode to round-to-zero.
6586 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
6587 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
6589 // Perform addition.
6590 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
6592 // Restore FPSCR value.
6593 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
6594 } else if (MI->getOpcode() == PPC::FRINDrint ||
6595 MI->getOpcode() == PPC::FRINSrint) {
6596 bool isf32 = MI->getOpcode() == PPC::FRINSrint;
6597 unsigned Dest = MI->getOperand(0).getReg();
6598 unsigned Src = MI->getOperand(1).getReg();
6599 DebugLoc dl = MI->getDebugLoc();
6601 MachineRegisterInfo &RegInfo = F->getRegInfo();
6602 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
6604 // Perform the rounding.
6605 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FRINS : PPC::FRIND), Dest)
6608 // Compare the results.
6609 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FCMPUS : PPC::FCMPUD), CRReg)
6610 .addReg(Dest).addReg(Src);
6612 // If the results were not equal, then set the FPSCR XX bit.
6613 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6614 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6615 F->insert(It, midMBB);
6616 F->insert(It, exitMBB);
6617 exitMBB->splice(exitMBB->begin(), BB,
6618 llvm::next(MachineBasicBlock::iterator(MI)),
6620 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6622 BuildMI(*BB, MI, dl, TII->get(PPC::BCC))
6623 .addImm(PPC::PRED_EQ).addReg(CRReg).addMBB(exitMBB);
6625 BB->addSuccessor(midMBB);
6626 BB->addSuccessor(exitMBB);
6630 // Set the FPSCR XX bit (FE_INEXACT). Note that we cannot just set
6631 // the FI bit here because that will not automatically set XX also,
6632 // and XX is what libm interprets as the FE_INEXACT flag.
6633 BuildMI(BB, dl, TII->get(PPC::MTFSB1)).addImm(/* 38 - 32 = */ 6);
6634 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6636 BB->addSuccessor(exitMBB);
6640 llvm_unreachable("Unexpected instr type to insert");
6643 MI->eraseFromParent(); // The pseudo instruction is gone now.
6647 //===----------------------------------------------------------------------===//
6648 // Target Optimization Hooks
6649 //===----------------------------------------------------------------------===//
6651 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
6652 DAGCombinerInfo &DCI) const {
6653 if (DCI.isAfterLegalizeVectorOps())
6656 EVT VT = Op.getValueType();
6658 if ((VT == MVT::f32 && PPCSubTarget.hasFRES()) ||
6659 (VT == MVT::f64 && PPCSubTarget.hasFRE()) ||
6660 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6662 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6663 // For the reciprocal, we need to find the zero of the function:
6664 // F(X) = A X - 1 [which has a zero at X = 1/A]
6666 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
6667 // does not require additional intermediate precision]
6669 // Convergence is quadratic, so we essentially double the number of digits
6670 // correct after every iteration. The minimum architected relative
6671 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6672 // 23 digits and double has 52 digits.
6673 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6674 if (VT.getScalarType() == MVT::f64)
6677 SelectionDAG &DAG = DCI.DAG;
6681 DAG.getConstantFP(1.0, VT.getScalarType());
6682 if (VT.isVector()) {
6683 assert(VT.getVectorNumElements() == 4 &&
6684 "Unknown vector type");
6685 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6686 FPOne, FPOne, FPOne, FPOne);
6689 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
6690 DCI.AddToWorklist(Est.getNode());
6692 // Newton iterations: Est = Est + Est (1 - Arg * Est)
6693 for (int i = 0; i < Iterations; ++i) {
6694 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
6695 DCI.AddToWorklist(NewEst.getNode());
6697 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
6698 DCI.AddToWorklist(NewEst.getNode());
6700 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6701 DCI.AddToWorklist(NewEst.getNode());
6703 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
6704 DCI.AddToWorklist(Est.getNode());
6713 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
6714 DAGCombinerInfo &DCI) const {
6715 if (DCI.isAfterLegalizeVectorOps())
6718 EVT VT = Op.getValueType();
6720 if ((VT == MVT::f32 && PPCSubTarget.hasFRSQRTES()) ||
6721 (VT == MVT::f64 && PPCSubTarget.hasFRSQRTE()) ||
6722 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6724 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6725 // For the reciprocal sqrt, we need to find the zero of the function:
6726 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
6728 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
6729 // As a result, we precompute A/2 prior to the iteration loop.
6731 // Convergence is quadratic, so we essentially double the number of digits
6732 // correct after every iteration. The minimum architected relative
6733 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6734 // 23 digits and double has 52 digits.
6735 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6736 if (VT.getScalarType() == MVT::f64)
6739 SelectionDAG &DAG = DCI.DAG;
6742 SDValue FPThreeHalves =
6743 DAG.getConstantFP(1.5, VT.getScalarType());
6744 if (VT.isVector()) {
6745 assert(VT.getVectorNumElements() == 4 &&
6746 "Unknown vector type");
6747 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6748 FPThreeHalves, FPThreeHalves,
6749 FPThreeHalves, FPThreeHalves);
6752 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
6753 DCI.AddToWorklist(Est.getNode());
6755 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
6756 // this entire sequence requires only one FP constant.
6757 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
6758 DCI.AddToWorklist(HalfArg.getNode());
6760 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
6761 DCI.AddToWorklist(HalfArg.getNode());
6763 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
6764 for (int i = 0; i < Iterations; ++i) {
6765 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
6766 DCI.AddToWorklist(NewEst.getNode());
6768 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
6769 DCI.AddToWorklist(NewEst.getNode());
6771 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
6772 DCI.AddToWorklist(NewEst.getNode());
6774 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6775 DCI.AddToWorklist(Est.getNode());
6784 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
6785 // not enforce equality of the chain operands.
6786 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
6787 unsigned Bytes, int Dist,
6788 SelectionDAG &DAG) {
6789 EVT VT = LS->getMemoryVT();
6790 if (VT.getSizeInBits() / 8 != Bytes)
6793 SDValue Loc = LS->getBasePtr();
6794 SDValue BaseLoc = Base->getBasePtr();
6795 if (Loc.getOpcode() == ISD::FrameIndex) {
6796 if (BaseLoc.getOpcode() != ISD::FrameIndex)
6798 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6799 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
6800 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
6801 int FS = MFI->getObjectSize(FI);
6802 int BFS = MFI->getObjectSize(BFI);
6803 if (FS != BFS || FS != (int)Bytes) return false;
6804 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
6808 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
6809 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
6812 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6813 const GlobalValue *GV1 = NULL;
6814 const GlobalValue *GV2 = NULL;
6815 int64_t Offset1 = 0;
6816 int64_t Offset2 = 0;
6817 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
6818 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
6819 if (isGA1 && isGA2 && GV1 == GV2)
6820 return Offset1 == (Offset2 + Dist*Bytes);
6824 // Return true is there is a nearyby consecutive load to the one provided
6825 // (regardless of alignment). We search up and down the chain, looking though
6826 // token factors and other loads (but nothing else). As a result, a true
6827 // results indicates that it is safe to create a new consecutive load adjacent
6828 // to the load provided.
6829 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
6830 SDValue Chain = LD->getChain();
6831 EVT VT = LD->getMemoryVT();
6833 SmallSet<SDNode *, 16> LoadRoots;
6834 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
6835 SmallSet<SDNode *, 16> Visited;
6837 // First, search up the chain, branching to follow all token-factor operands.
6838 // If we find a consecutive load, then we're done, otherwise, record all
6839 // nodes just above the top-level loads and token factors.
6840 while (!Queue.empty()) {
6841 SDNode *ChainNext = Queue.pop_back_val();
6842 if (!Visited.insert(ChainNext))
6845 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
6846 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
6849 if (!Visited.count(ChainLD->getChain().getNode()))
6850 Queue.push_back(ChainLD->getChain().getNode());
6851 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
6852 for (SDNode::op_iterator O = ChainNext->op_begin(),
6853 OE = ChainNext->op_end(); O != OE; ++O)
6854 if (!Visited.count(O->getNode()))
6855 Queue.push_back(O->getNode());
6857 LoadRoots.insert(ChainNext);
6860 // Second, search down the chain, starting from the top-level nodes recorded
6861 // in the first phase. These top-level nodes are the nodes just above all
6862 // loads and token factors. Starting with their uses, recursively look though
6863 // all loads (just the chain uses) and token factors to find a consecutive
6868 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
6869 IE = LoadRoots.end(); I != IE; ++I) {
6870 Queue.push_back(*I);
6872 while (!Queue.empty()) {
6873 SDNode *LoadRoot = Queue.pop_back_val();
6874 if (!Visited.insert(LoadRoot))
6877 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
6878 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
6881 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
6882 UE = LoadRoot->use_end(); UI != UE; ++UI)
6883 if (((isa<LoadSDNode>(*UI) &&
6884 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
6885 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
6886 Queue.push_back(*UI);
6893 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
6894 DAGCombinerInfo &DCI) const {
6895 const TargetMachine &TM = getTargetMachine();
6896 SelectionDAG &DAG = DCI.DAG;
6898 switch (N->getOpcode()) {
6901 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6902 if (C->isNullValue()) // 0 << V -> 0.
6903 return N->getOperand(0);
6907 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6908 if (C->isNullValue()) // 0 >>u V -> 0.
6909 return N->getOperand(0);
6913 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6914 if (C->isNullValue() || // 0 >>s V -> 0.
6915 C->isAllOnesValue()) // -1 >>s V -> -1.
6916 return N->getOperand(0);
6920 assert(TM.Options.UnsafeFPMath &&
6921 "Reciprocal estimates require UnsafeFPMath");
6923 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
6925 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
6926 if (RV.getNode() != 0) {
6927 DCI.AddToWorklist(RV.getNode());
6928 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6929 N->getOperand(0), RV);
6931 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
6932 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
6934 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
6936 if (RV.getNode() != 0) {
6937 DCI.AddToWorklist(RV.getNode());
6938 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
6939 N->getValueType(0), RV);
6940 DCI.AddToWorklist(RV.getNode());
6941 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6942 N->getOperand(0), RV);
6944 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
6945 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
6947 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
6949 if (RV.getNode() != 0) {
6950 DCI.AddToWorklist(RV.getNode());
6951 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
6952 N->getValueType(0), RV,
6953 N->getOperand(1).getOperand(1));
6954 DCI.AddToWorklist(RV.getNode());
6955 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6956 N->getOperand(0), RV);
6960 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
6961 if (RV.getNode() != 0) {
6962 DCI.AddToWorklist(RV.getNode());
6963 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6964 N->getOperand(0), RV);
6970 assert(TM.Options.UnsafeFPMath &&
6971 "Reciprocal estimates require UnsafeFPMath");
6973 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
6975 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
6976 if (RV.getNode() != 0) {
6977 DCI.AddToWorklist(RV.getNode());
6978 RV = DAGCombineFastRecip(RV, DCI);
6979 if (RV.getNode() != 0)
6985 case ISD::SINT_TO_FP:
6986 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
6987 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
6988 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
6989 // We allow the src/dst to be either f32/f64, but the intermediate
6990 // type must be i64.
6991 if (N->getOperand(0).getValueType() == MVT::i64 &&
6992 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
6993 SDValue Val = N->getOperand(0).getOperand(0);
6994 if (Val.getValueType() == MVT::f32) {
6995 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
6996 DCI.AddToWorklist(Val.getNode());
6999 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
7000 DCI.AddToWorklist(Val.getNode());
7001 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
7002 DCI.AddToWorklist(Val.getNode());
7003 if (N->getValueType(0) == MVT::f32) {
7004 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
7005 DAG.getIntPtrConstant(0));
7006 DCI.AddToWorklist(Val.getNode());
7009 } else if (N->getOperand(0).getValueType() == MVT::i32) {
7010 // If the intermediate type is i32, we can avoid the load/store here
7017 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
7018 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
7019 !cast<StoreSDNode>(N)->isTruncatingStore() &&
7020 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
7021 N->getOperand(1).getValueType() == MVT::i32 &&
7022 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
7023 SDValue Val = N->getOperand(1).getOperand(0);
7024 if (Val.getValueType() == MVT::f32) {
7025 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7026 DCI.AddToWorklist(Val.getNode());
7028 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
7029 DCI.AddToWorklist(Val.getNode());
7032 N->getOperand(0), Val, N->getOperand(2),
7033 DAG.getValueType(N->getOperand(1).getValueType())
7036 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
7037 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
7038 cast<StoreSDNode>(N)->getMemoryVT(),
7039 cast<StoreSDNode>(N)->getMemOperand());
7040 DCI.AddToWorklist(Val.getNode());
7044 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
7045 if (cast<StoreSDNode>(N)->isUnindexed() &&
7046 N->getOperand(1).getOpcode() == ISD::BSWAP &&
7047 N->getOperand(1).getNode()->hasOneUse() &&
7048 (N->getOperand(1).getValueType() == MVT::i32 ||
7049 N->getOperand(1).getValueType() == MVT::i16 ||
7050 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7051 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7052 N->getOperand(1).getValueType() == MVT::i64))) {
7053 SDValue BSwapOp = N->getOperand(1).getOperand(0);
7054 // Do an any-extend to 32-bits if this is a half-word input.
7055 if (BSwapOp.getValueType() == MVT::i16)
7056 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
7059 N->getOperand(0), BSwapOp, N->getOperand(2),
7060 DAG.getValueType(N->getOperand(1).getValueType())
7063 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
7064 Ops, array_lengthof(Ops),
7065 cast<StoreSDNode>(N)->getMemoryVT(),
7066 cast<StoreSDNode>(N)->getMemOperand());
7070 LoadSDNode *LD = cast<LoadSDNode>(N);
7071 EVT VT = LD->getValueType(0);
7072 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
7073 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
7074 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
7075 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
7076 DCI.getDAGCombineLevel() == AfterLegalizeTypes &&
7077 LD->getAlignment() < ABIAlignment) {
7078 // This is a type-legal unaligned Altivec load.
7079 SDValue Chain = LD->getChain();
7080 SDValue Ptr = LD->getBasePtr();
7082 // This implements the loading of unaligned vectors as described in
7083 // the venerable Apple Velocity Engine overview. Specifically:
7084 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
7085 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
7087 // The general idea is to expand a sequence of one or more unaligned
7088 // loads into a alignment-based permutation-control instruction (lvsl),
7089 // a series of regular vector loads (which always truncate their
7090 // input address to an aligned address), and a series of permutations.
7091 // The results of these permutations are the requested loaded values.
7092 // The trick is that the last "extra" load is not taken from the address
7093 // you might suspect (sizeof(vector) bytes after the last requested
7094 // load), but rather sizeof(vector) - 1 bytes after the last
7095 // requested vector. The point of this is to avoid a page fault if the
7096 // base address happend to be aligned. This works because if the base
7097 // address is aligned, then adding less than a full vector length will
7098 // cause the last vector in the sequence to be (re)loaded. Otherwise,
7099 // the next vector will be fetched as you might suspect was necessary.
7101 // We might be able to reuse the permutation generation from
7102 // a different base address offset from this one by an aligned amount.
7103 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
7104 // optimization later.
7105 SDValue PermCntl = BuildIntrinsicOp(Intrinsic::ppc_altivec_lvsl, Ptr,
7106 DAG, dl, MVT::v16i8);
7108 // Refine the alignment of the original load (a "new" load created here
7109 // which was identical to the first except for the alignment would be
7110 // merged with the existing node regardless).
7111 MachineFunction &MF = DAG.getMachineFunction();
7112 MachineMemOperand *MMO =
7113 MF.getMachineMemOperand(LD->getPointerInfo(),
7114 LD->getMemOperand()->getFlags(),
7115 LD->getMemoryVT().getStoreSize(),
7117 LD->refineAlignment(MMO);
7118 SDValue BaseLoad = SDValue(LD, 0);
7120 // Note that the value of IncOffset (which is provided to the next
7121 // load's pointer info offset value, and thus used to calculate the
7122 // alignment), and the value of IncValue (which is actually used to
7123 // increment the pointer value) are different! This is because we
7124 // require the next load to appear to be aligned, even though it
7125 // is actually offset from the base pointer by a lesser amount.
7126 int IncOffset = VT.getSizeInBits() / 8;
7127 int IncValue = IncOffset;
7129 // Walk (both up and down) the chain looking for another load at the real
7130 // (aligned) offset (the alignment of the other load does not matter in
7131 // this case). If found, then do not use the offset reduction trick, as
7132 // that will prevent the loads from being later combined (as they would
7133 // otherwise be duplicates).
7134 if (!findConsecutiveLoad(LD, DAG))
7137 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
7138 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
7141 DAG.getLoad(VT, dl, Chain, Ptr,
7142 LD->getPointerInfo().getWithOffset(IncOffset),
7143 LD->isVolatile(), LD->isNonTemporal(),
7144 LD->isInvariant(), ABIAlignment);
7146 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
7147 BaseLoad.getValue(1), ExtraLoad.getValue(1));
7149 if (BaseLoad.getValueType() != MVT::v4i32)
7150 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
7152 if (ExtraLoad.getValueType() != MVT::v4i32)
7153 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
7155 SDValue Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
7156 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
7158 if (VT != MVT::v4i32)
7159 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
7161 // Now we need to be really careful about how we update the users of the
7162 // original load. We cannot just call DCI.CombineTo (or
7163 // DAG.ReplaceAllUsesWith for that matter), because the load still has
7164 // uses created here (the permutation for example) that need to stay.
7165 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
7167 SDUse &Use = UI.getUse();
7169 // Note: BaseLoad is checked here because it might not be N, but a
7171 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
7172 User == TF.getNode() || Use.getResNo() > 1) {
7177 SDValue To = Use.getResNo() ? TF : Perm;
7180 SmallVector<SDValue, 8> Ops;
7181 for (SDNode::op_iterator O = User->op_begin(),
7182 OE = User->op_end(); O != OE; ++O) {
7189 DAG.UpdateNodeOperands(User, Ops.data(), Ops.size());
7192 return SDValue(N, 0);
7196 case ISD::INTRINSIC_WO_CHAIN:
7197 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() ==
7198 Intrinsic::ppc_altivec_lvsl &&
7199 N->getOperand(1)->getOpcode() == ISD::ADD) {
7200 SDValue Add = N->getOperand(1);
7202 if (DAG.MaskedValueIsZero(Add->getOperand(1),
7203 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
7204 Add.getValueType().getScalarType().getSizeInBits()))) {
7205 SDNode *BasePtr = Add->getOperand(0).getNode();
7206 for (SDNode::use_iterator UI = BasePtr->use_begin(),
7207 UE = BasePtr->use_end(); UI != UE; ++UI) {
7208 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7209 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
7210 Intrinsic::ppc_altivec_lvsl) {
7211 // We've found another LVSL, and this address if an aligned
7212 // multiple of that one. The results will be the same, so use the
7213 // one we've just found instead.
7215 return SDValue(*UI, 0);
7221 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
7222 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
7223 N->getOperand(0).hasOneUse() &&
7224 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
7225 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7226 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7227 N->getValueType(0) == MVT::i64))) {
7228 SDValue Load = N->getOperand(0);
7229 LoadSDNode *LD = cast<LoadSDNode>(Load);
7230 // Create the byte-swapping load.
7232 LD->getChain(), // Chain
7233 LD->getBasePtr(), // Ptr
7234 DAG.getValueType(N->getValueType(0)) // VT
7237 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
7238 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
7239 MVT::i64 : MVT::i32, MVT::Other),
7240 Ops, 3, LD->getMemoryVT(), LD->getMemOperand());
7242 // If this is an i16 load, insert the truncate.
7243 SDValue ResVal = BSLoad;
7244 if (N->getValueType(0) == MVT::i16)
7245 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
7247 // First, combine the bswap away. This makes the value produced by the
7249 DCI.CombineTo(N, ResVal);
7251 // Next, combine the load away, we give it a bogus result value but a real
7252 // chain result. The result value is dead because the bswap is dead.
7253 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
7255 // Return N so it doesn't get rechecked!
7256 return SDValue(N, 0);
7260 case PPCISD::VCMP: {
7261 // If a VCMPo node already exists with exactly the same operands as this
7262 // node, use its result instead of this node (VCMPo computes both a CR6 and
7263 // a normal output).
7265 if (!N->getOperand(0).hasOneUse() &&
7266 !N->getOperand(1).hasOneUse() &&
7267 !N->getOperand(2).hasOneUse()) {
7269 // Scan all of the users of the LHS, looking for VCMPo's that match.
7270 SDNode *VCMPoNode = 0;
7272 SDNode *LHSN = N->getOperand(0).getNode();
7273 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
7275 if (UI->getOpcode() == PPCISD::VCMPo &&
7276 UI->getOperand(1) == N->getOperand(1) &&
7277 UI->getOperand(2) == N->getOperand(2) &&
7278 UI->getOperand(0) == N->getOperand(0)) {
7283 // If there is no VCMPo node, or if the flag value has a single use, don't
7285 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
7288 // Look at the (necessarily single) use of the flag value. If it has a
7289 // chain, this transformation is more complex. Note that multiple things
7290 // could use the value result, which we should ignore.
7291 SDNode *FlagUser = 0;
7292 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
7293 FlagUser == 0; ++UI) {
7294 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
7296 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
7297 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
7304 // If the user is a MFCR instruction, we know this is safe. Otherwise we
7305 // give up for right now.
7306 if (FlagUser->getOpcode() == PPCISD::MFCR)
7307 return SDValue(VCMPoNode, 0);
7312 // If this is a branch on an altivec predicate comparison, lower this so
7313 // that we don't have to do a MFCR: instead, branch directly on CR6. This
7314 // lowering is done pre-legalize, because the legalizer lowers the predicate
7315 // compare down to code that is difficult to reassemble.
7316 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
7317 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
7319 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
7320 // value. If so, pass-through the AND to get to the intrinsic.
7321 if (LHS.getOpcode() == ISD::AND &&
7322 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7323 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
7324 Intrinsic::ppc_is_decremented_ctr_nonzero &&
7325 isa<ConstantSDNode>(LHS.getOperand(1)) &&
7326 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
7328 LHS = LHS.getOperand(0);
7330 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7331 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
7332 Intrinsic::ppc_is_decremented_ctr_nonzero &&
7333 isa<ConstantSDNode>(RHS)) {
7334 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
7335 "Counter decrement comparison is not EQ or NE");
7337 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7338 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
7339 (CC == ISD::SETNE && !Val);
7341 // We now need to make the intrinsic dead (it cannot be instruction
7343 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
7344 assert(LHS.getNode()->hasOneUse() &&
7345 "Counter decrement has more than one use");
7347 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
7348 N->getOperand(0), N->getOperand(4));
7354 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7355 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
7356 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
7357 assert(isDot && "Can't compare against a vector result!");
7359 // If this is a comparison against something other than 0/1, then we know
7360 // that the condition is never/always true.
7361 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7362 if (Val != 0 && Val != 1) {
7363 if (CC == ISD::SETEQ) // Cond never true, remove branch.
7364 return N->getOperand(0);
7365 // Always !=, turn it into an unconditional branch.
7366 return DAG.getNode(ISD::BR, dl, MVT::Other,
7367 N->getOperand(0), N->getOperand(4));
7370 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
7372 // Create the PPCISD altivec 'dot' comparison node.
7374 LHS.getOperand(2), // LHS of compare
7375 LHS.getOperand(3), // RHS of compare
7376 DAG.getConstant(CompareOpc, MVT::i32)
7378 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
7379 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
7381 // Unpack the result based on how the target uses it.
7382 PPC::Predicate CompOpc;
7383 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
7384 default: // Can't happen, don't crash on invalid number though.
7385 case 0: // Branch on the value of the EQ bit of CR6.
7386 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
7388 case 1: // Branch on the inverted value of the EQ bit of CR6.
7389 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
7391 case 2: // Branch on the value of the LT bit of CR6.
7392 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
7394 case 3: // Branch on the inverted value of the LT bit of CR6.
7395 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
7399 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
7400 DAG.getConstant(CompOpc, MVT::i32),
7401 DAG.getRegister(PPC::CR6, MVT::i32),
7402 N->getOperand(4), CompNode.getValue(1));
7411 //===----------------------------------------------------------------------===//
7412 // Inline Assembly Support
7413 //===----------------------------------------------------------------------===//
7415 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7418 const SelectionDAG &DAG,
7419 unsigned Depth) const {
7420 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
7421 switch (Op.getOpcode()) {
7423 case PPCISD::LBRX: {
7424 // lhbrx is known to have the top bits cleared out.
7425 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
7426 KnownZero = 0xFFFF0000;
7429 case ISD::INTRINSIC_WO_CHAIN: {
7430 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
7432 case Intrinsic::ppc_altivec_vcmpbfp_p:
7433 case Intrinsic::ppc_altivec_vcmpeqfp_p:
7434 case Intrinsic::ppc_altivec_vcmpequb_p:
7435 case Intrinsic::ppc_altivec_vcmpequh_p:
7436 case Intrinsic::ppc_altivec_vcmpequw_p:
7437 case Intrinsic::ppc_altivec_vcmpgefp_p:
7438 case Intrinsic::ppc_altivec_vcmpgtfp_p:
7439 case Intrinsic::ppc_altivec_vcmpgtsb_p:
7440 case Intrinsic::ppc_altivec_vcmpgtsh_p:
7441 case Intrinsic::ppc_altivec_vcmpgtsw_p:
7442 case Intrinsic::ppc_altivec_vcmpgtub_p:
7443 case Intrinsic::ppc_altivec_vcmpgtuh_p:
7444 case Intrinsic::ppc_altivec_vcmpgtuw_p:
7445 KnownZero = ~1U; // All bits but the low one are known to be zero.
7453 /// getConstraintType - Given a constraint, return the type of
7454 /// constraint it is for this target.
7455 PPCTargetLowering::ConstraintType
7456 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
7457 if (Constraint.size() == 1) {
7458 switch (Constraint[0]) {
7465 return C_RegisterClass;
7467 // FIXME: While Z does indicate a memory constraint, it specifically
7468 // indicates an r+r address (used in conjunction with the 'y' modifier
7469 // in the replacement string). Currently, we're forcing the base
7470 // register to be r0 in the asm printer (which is interpreted as zero)
7471 // and forming the complete address in the second register. This is
7476 return TargetLowering::getConstraintType(Constraint);
7479 /// Examine constraint type and operand type and determine a weight value.
7480 /// This object must already have been set up with the operand type
7481 /// and the current alternative constraint selected.
7482 TargetLowering::ConstraintWeight
7483 PPCTargetLowering::getSingleConstraintMatchWeight(
7484 AsmOperandInfo &info, const char *constraint) const {
7485 ConstraintWeight weight = CW_Invalid;
7486 Value *CallOperandVal = info.CallOperandVal;
7487 // If we don't have a value, we can't do a match,
7488 // but allow it at the lowest weight.
7489 if (CallOperandVal == NULL)
7491 Type *type = CallOperandVal->getType();
7492 // Look at the constraint type.
7493 switch (*constraint) {
7495 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
7498 if (type->isIntegerTy())
7499 weight = CW_Register;
7502 if (type->isFloatTy())
7503 weight = CW_Register;
7506 if (type->isDoubleTy())
7507 weight = CW_Register;
7510 if (type->isVectorTy())
7511 weight = CW_Register;
7514 weight = CW_Register;
7523 std::pair<unsigned, const TargetRegisterClass*>
7524 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7526 if (Constraint.size() == 1) {
7527 // GCC RS6000 Constraint Letters
7528 switch (Constraint[0]) {
7530 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7531 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
7532 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
7534 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7535 return std::make_pair(0U, &PPC::G8RCRegClass);
7536 return std::make_pair(0U, &PPC::GPRCRegClass);
7538 if (VT == MVT::f32 || VT == MVT::i32)
7539 return std::make_pair(0U, &PPC::F4RCRegClass);
7540 if (VT == MVT::f64 || VT == MVT::i64)
7541 return std::make_pair(0U, &PPC::F8RCRegClass);
7544 return std::make_pair(0U, &PPC::VRRCRegClass);
7546 return std::make_pair(0U, &PPC::CRRCRegClass);
7550 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7554 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7555 /// vector. If it is invalid, don't add anything to Ops.
7556 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7557 std::string &Constraint,
7558 std::vector<SDValue>&Ops,
7559 SelectionDAG &DAG) const {
7560 SDValue Result(0,0);
7562 // Only support length 1 constraints.
7563 if (Constraint.length() > 1) return;
7565 char Letter = Constraint[0];
7576 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
7577 if (!CST) return; // Must be an immediate to match.
7578 unsigned Value = CST->getZExtValue();
7580 default: llvm_unreachable("Unknown constraint letter!");
7581 case 'I': // "I" is a signed 16-bit constant.
7582 if ((short)Value == (int)Value)
7583 Result = DAG.getTargetConstant(Value, Op.getValueType());
7585 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
7586 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
7587 if ((short)Value == 0)
7588 Result = DAG.getTargetConstant(Value, Op.getValueType());
7590 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
7591 if ((Value >> 16) == 0)
7592 Result = DAG.getTargetConstant(Value, Op.getValueType());
7594 case 'M': // "M" is a constant that is greater than 31.
7596 Result = DAG.getTargetConstant(Value, Op.getValueType());
7598 case 'N': // "N" is a positive constant that is an exact power of two.
7599 if ((int)Value > 0 && isPowerOf2_32(Value))
7600 Result = DAG.getTargetConstant(Value, Op.getValueType());
7602 case 'O': // "O" is the constant zero.
7604 Result = DAG.getTargetConstant(Value, Op.getValueType());
7606 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
7607 if ((short)-Value == (int)-Value)
7608 Result = DAG.getTargetConstant(Value, Op.getValueType());
7615 if (Result.getNode()) {
7616 Ops.push_back(Result);
7620 // Handle standard constraint letters.
7621 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7624 // isLegalAddressingMode - Return true if the addressing mode represented
7625 // by AM is legal for this target, for a load/store of the specified type.
7626 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
7628 // FIXME: PPC does not allow r+i addressing modes for vectors!
7630 // PPC allows a sign-extended 16-bit immediate field.
7631 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
7634 // No global is ever allowed as a base.
7638 // PPC only support r+r,
7640 case 0: // "r+i" or just "i", depending on HasBaseReg.
7643 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
7645 // Otherwise we have r+r or r+i.
7648 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
7650 // Allow 2*r as r+r.
7653 // No other scales are supported.
7660 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
7661 SelectionDAG &DAG) const {
7662 MachineFunction &MF = DAG.getMachineFunction();
7663 MachineFrameInfo *MFI = MF.getFrameInfo();
7664 MFI->setReturnAddressIsTaken(true);
7667 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7669 // Make sure the function does not optimize away the store of the RA to
7671 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
7672 FuncInfo->setLRStoreRequired();
7673 bool isPPC64 = PPCSubTarget.isPPC64();
7674 bool isDarwinABI = PPCSubTarget.isDarwinABI();
7677 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7680 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
7681 isPPC64? MVT::i64 : MVT::i32);
7682 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7683 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7685 MachinePointerInfo(), false, false, false, 0);
7688 // Just load the return address off the stack.
7689 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
7690 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7691 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
7694 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
7695 SelectionDAG &DAG) const {
7697 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7699 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
7700 bool isPPC64 = PtrVT == MVT::i64;
7702 MachineFunction &MF = DAG.getMachineFunction();
7703 MachineFrameInfo *MFI = MF.getFrameInfo();
7704 MFI->setFrameAddressIsTaken(true);
7706 // Naked functions never have a frame pointer, and so we use r1. For all
7707 // other functions, this decision must be delayed until during PEI.
7709 if (MF.getFunction()->getAttributes().hasAttribute(
7710 AttributeSet::FunctionIndex, Attribute::Naked))
7711 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
7713 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
7715 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
7718 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
7719 FrameAddr, MachinePointerInfo(), false, false,
7725 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7726 // The PowerPC target isn't yet aware of offsets.
7730 /// getOptimalMemOpType - Returns the target specific optimal type for load
7731 /// and store operations as a result of memset, memcpy, and memmove
7732 /// lowering. If DstAlign is zero that means it's safe to destination
7733 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
7734 /// means there isn't a need to check it against alignment requirement,
7735 /// probably because the source does not need to be loaded. If 'IsMemset' is
7736 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
7737 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
7738 /// source is constant so it does not need to be loaded.
7739 /// It returns EVT::Other if the type should be determined using generic
7740 /// target-independent logic.
7741 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
7742 unsigned DstAlign, unsigned SrcAlign,
7743 bool IsMemset, bool ZeroMemset,
7745 MachineFunction &MF) const {
7746 if (this->PPCSubTarget.isPPC64()) {
7753 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
7755 if (DisablePPCUnaligned)
7758 // PowerPC supports unaligned memory access for simple non-vector types.
7759 // Although accessing unaligned addresses is not as efficient as accessing
7760 // aligned addresses, it is generally more efficient than manual expansion,
7761 // and generally only traps for software emulation when crossing page
7767 if (VT.getSimpleVT().isVector())
7770 if (VT == MVT::ppcf128)
7779 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
7780 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
7781 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
7782 /// is expanded to mul + add.
7783 bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const {
7787 switch (VT.getSimpleVT().SimpleTy) {
7799 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
7801 return TargetLowering::getSchedulingPreference(N);