1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetOptions.h"
40 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
41 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
43 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
44 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
46 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
47 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
49 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
50 if (TM.getSubtargetImpl()->isDarwin())
51 return new TargetLoweringObjectFileMachO();
53 if (TM.getSubtargetImpl()->isSVR4ABI())
54 return new PPC64LinuxTargetObjectFile();
56 return new TargetLoweringObjectFileELF();
59 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
60 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
61 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
65 // Use _setjmp/_longjmp instead of setjmp/longjmp.
66 setUseUnderscoreSetJmp(true);
67 setUseUnderscoreLongJmp(true);
69 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
70 // arguments are at least 4/8 bytes aligned.
71 bool isPPC64 = Subtarget->isPPC64();
72 setMinStackArgumentAlignment(isPPC64 ? 8:4);
74 // Set up the register classes.
75 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
76 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
77 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
79 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
80 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
85 // PowerPC has pre-inc load and store's.
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
97 // This is used in the ppcf128->int sequence. Note it has different semantics
98 // from FP_ROUND: that rounds to nearest, this rounds to zero.
99 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
101 // We do not currently implement these libm ops for PowerPC.
102 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
103 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
104 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
105 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
106 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
107 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
109 // PowerPC has no SREM/UREM instructions
110 setOperationAction(ISD::SREM, MVT::i32, Expand);
111 setOperationAction(ISD::UREM, MVT::i32, Expand);
112 setOperationAction(ISD::SREM, MVT::i64, Expand);
113 setOperationAction(ISD::UREM, MVT::i64, Expand);
115 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
116 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
117 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
118 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
119 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
121 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
122 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
123 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
125 // We don't support sin/cos/sqrt/fmod/pow
126 setOperationAction(ISD::FSIN , MVT::f64, Expand);
127 setOperationAction(ISD::FCOS , MVT::f64, Expand);
128 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
129 setOperationAction(ISD::FREM , MVT::f64, Expand);
130 setOperationAction(ISD::FPOW , MVT::f64, Expand);
131 setOperationAction(ISD::FMA , MVT::f64, Legal);
132 setOperationAction(ISD::FSIN , MVT::f32, Expand);
133 setOperationAction(ISD::FCOS , MVT::f32, Expand);
134 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
135 setOperationAction(ISD::FREM , MVT::f32, Expand);
136 setOperationAction(ISD::FPOW , MVT::f32, Expand);
137 setOperationAction(ISD::FMA , MVT::f32, Legal);
139 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
141 // If we're enabling GP optimizations, use hardware square root
142 if (!Subtarget->hasFSQRT() &&
143 !(TM.Options.UnsafeFPMath &&
144 Subtarget->hasFRSQRTE() && Subtarget->hasFRE()))
145 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
147 if (!Subtarget->hasFSQRT() &&
148 !(TM.Options.UnsafeFPMath &&
149 Subtarget->hasFRSQRTES() && Subtarget->hasFRES()))
150 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
152 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
153 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
155 if (Subtarget->hasFPRND()) {
156 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
157 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
158 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
160 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
161 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
162 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
164 // frin does not implement "ties to even." Thus, this is safe only in
166 if (TM.Options.UnsafeFPMath) {
167 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
168 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
170 // These need to set FE_INEXACT, and use a custom inserter.
171 setOperationAction(ISD::FRINT, MVT::f64, Legal);
172 setOperationAction(ISD::FRINT, MVT::f32, Legal);
176 // PowerPC does not have BSWAP, CTPOP or CTTZ
177 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
178 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
179 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
180 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
181 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
182 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
183 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
184 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
186 if (Subtarget->hasPOPCNTD()) {
187 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
188 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
190 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
191 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
194 // PowerPC does not have ROTR
195 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
196 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
198 // PowerPC does not have Select
199 setOperationAction(ISD::SELECT, MVT::i32, Expand);
200 setOperationAction(ISD::SELECT, MVT::i64, Expand);
201 setOperationAction(ISD::SELECT, MVT::f32, Expand);
202 setOperationAction(ISD::SELECT, MVT::f64, Expand);
204 // PowerPC wants to turn select_cc of FP into fsel when possible.
205 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
206 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
208 // PowerPC wants to optimize integer setcc a bit
209 setOperationAction(ISD::SETCC, MVT::i32, Custom);
211 // PowerPC does not have BRCOND which requires SetCC
212 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
214 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
216 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
217 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
219 // PowerPC does not have [U|S]INT_TO_FP
220 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
221 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
223 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
224 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
225 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
226 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
228 // We cannot sextinreg(i1). Expand to shifts.
229 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
231 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
232 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
233 // support continuation, user-level threading, and etc.. As a result, no
234 // other SjLj exception interfaces are implemented and please don't build
235 // your own exception handling based on them.
236 // LLVM/Clang supports zero-cost DWARF exception handling.
237 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
238 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
240 // We want to legalize GlobalAddress and ConstantPool nodes into the
241 // appropriate instructions to materialize the address.
242 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
243 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
244 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
245 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
246 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
247 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
248 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
249 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
250 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
251 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
254 setOperationAction(ISD::TRAP, MVT::Other, Legal);
256 // TRAMPOLINE is custom lowered.
257 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
258 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
260 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
261 setOperationAction(ISD::VASTART , MVT::Other, Custom);
263 if (Subtarget->isSVR4ABI()) {
265 // VAARG always uses double-word chunks, so promote anything smaller.
266 setOperationAction(ISD::VAARG, MVT::i1, Promote);
267 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
268 setOperationAction(ISD::VAARG, MVT::i8, Promote);
269 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
270 setOperationAction(ISD::VAARG, MVT::i16, Promote);
271 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
272 setOperationAction(ISD::VAARG, MVT::i32, Promote);
273 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
274 setOperationAction(ISD::VAARG, MVT::Other, Expand);
276 // VAARG is custom lowered with the 32-bit SVR4 ABI.
277 setOperationAction(ISD::VAARG, MVT::Other, Custom);
278 setOperationAction(ISD::VAARG, MVT::i64, Custom);
281 setOperationAction(ISD::VAARG, MVT::Other, Expand);
283 // Use the default implementation.
284 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
285 setOperationAction(ISD::VAEND , MVT::Other, Expand);
286 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
287 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
288 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
289 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
291 // We want to custom lower some of our intrinsics.
292 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
294 // To handle counter-based loop conditions.
295 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
297 // Comparisons that require checking two conditions.
298 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
299 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
300 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
301 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
302 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
303 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
304 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
305 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
306 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
307 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
308 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
309 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
311 if (Subtarget->has64BitSupport()) {
312 // They also have instructions for converting between i64 and fp.
313 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
314 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
315 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
316 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
317 // This is just the low 32 bits of a (signed) fp->i64 conversion.
318 // We cannot do this with Promote because i64 is not a legal type.
319 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
321 if (PPCSubTarget.hasLFIWAX() || Subtarget->isPPC64())
322 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
324 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
325 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
328 // With the instructions enabled under FPCVT, we can do everything.
329 if (PPCSubTarget.hasFPCVT()) {
330 if (Subtarget->has64BitSupport()) {
331 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
332 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
333 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
334 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
337 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
338 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
339 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
340 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
343 if (Subtarget->use64BitRegs()) {
344 // 64-bit PowerPC implementations can support i64 types directly
345 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
346 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
347 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
348 // 64-bit PowerPC wants to expand i128 shifts itself.
349 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
350 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
351 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
353 // 32-bit PowerPC wants to expand i64 shifts itself.
354 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
355 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
356 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
359 if (Subtarget->hasAltivec()) {
360 // First set operation action for all vector types to expand. Then we
361 // will selectively turn on ones that can be effectively codegen'd.
362 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
363 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
364 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
366 // add/sub are legal for all supported vector VT's.
367 setOperationAction(ISD::ADD , VT, Legal);
368 setOperationAction(ISD::SUB , VT, Legal);
370 // We promote all shuffles to v16i8.
371 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
372 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
374 // We promote all non-typed operations to v4i32.
375 setOperationAction(ISD::AND , VT, Promote);
376 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
377 setOperationAction(ISD::OR , VT, Promote);
378 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
379 setOperationAction(ISD::XOR , VT, Promote);
380 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
381 setOperationAction(ISD::LOAD , VT, Promote);
382 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
383 setOperationAction(ISD::SELECT, VT, Promote);
384 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
385 setOperationAction(ISD::STORE, VT, Promote);
386 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
388 // No other operations are legal.
389 setOperationAction(ISD::MUL , VT, Expand);
390 setOperationAction(ISD::SDIV, VT, Expand);
391 setOperationAction(ISD::SREM, VT, Expand);
392 setOperationAction(ISD::UDIV, VT, Expand);
393 setOperationAction(ISD::UREM, VT, Expand);
394 setOperationAction(ISD::FDIV, VT, Expand);
395 setOperationAction(ISD::FREM, VT, Expand);
396 setOperationAction(ISD::FNEG, VT, Expand);
397 setOperationAction(ISD::FSQRT, VT, Expand);
398 setOperationAction(ISD::FLOG, VT, Expand);
399 setOperationAction(ISD::FLOG10, VT, Expand);
400 setOperationAction(ISD::FLOG2, VT, Expand);
401 setOperationAction(ISD::FEXP, VT, Expand);
402 setOperationAction(ISD::FEXP2, VT, Expand);
403 setOperationAction(ISD::FSIN, VT, Expand);
404 setOperationAction(ISD::FCOS, VT, Expand);
405 setOperationAction(ISD::FABS, VT, Expand);
406 setOperationAction(ISD::FPOWI, VT, Expand);
407 setOperationAction(ISD::FFLOOR, VT, Expand);
408 setOperationAction(ISD::FCEIL, VT, Expand);
409 setOperationAction(ISD::FTRUNC, VT, Expand);
410 setOperationAction(ISD::FRINT, VT, Expand);
411 setOperationAction(ISD::FNEARBYINT, VT, Expand);
412 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
413 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
414 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
415 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
416 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
417 setOperationAction(ISD::UDIVREM, VT, Expand);
418 setOperationAction(ISD::SDIVREM, VT, Expand);
419 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
420 setOperationAction(ISD::FPOW, VT, Expand);
421 setOperationAction(ISD::CTPOP, VT, Expand);
422 setOperationAction(ISD::CTLZ, VT, Expand);
423 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
424 setOperationAction(ISD::CTTZ, VT, Expand);
425 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
426 setOperationAction(ISD::VSELECT, VT, Expand);
427 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
429 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
430 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
431 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
432 setTruncStoreAction(VT, InnerVT, Expand);
434 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
435 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
436 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
439 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
440 // with merges, splats, etc.
441 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
443 setOperationAction(ISD::AND , MVT::v4i32, Legal);
444 setOperationAction(ISD::OR , MVT::v4i32, Legal);
445 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
446 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
447 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
448 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
449 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
450 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
451 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
452 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
453 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
454 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
455 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
456 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
458 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
459 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
460 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
461 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
463 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
464 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
466 if (TM.Options.UnsafeFPMath) {
467 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
468 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
471 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
472 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
473 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
475 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
476 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
478 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
479 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
480 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
481 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
483 // Altivec does not contain unordered floating-point compare instructions
484 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
485 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
486 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
487 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
488 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
489 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
491 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
492 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
495 if (Subtarget->has64BitSupport()) {
496 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
497 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
500 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
501 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
502 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
503 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
505 setBooleanContents(ZeroOrOneBooleanContent);
506 // Altivec instructions set fields to all zeros or all ones.
507 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
510 setStackPointerRegisterToSaveRestore(PPC::X1);
511 setExceptionPointerRegister(PPC::X3);
512 setExceptionSelectorRegister(PPC::X4);
514 setStackPointerRegisterToSaveRestore(PPC::R1);
515 setExceptionPointerRegister(PPC::R3);
516 setExceptionSelectorRegister(PPC::R4);
519 // We have target-specific dag combine patterns for the following nodes:
520 setTargetDAGCombine(ISD::SINT_TO_FP);
521 setTargetDAGCombine(ISD::LOAD);
522 setTargetDAGCombine(ISD::STORE);
523 setTargetDAGCombine(ISD::BR_CC);
524 setTargetDAGCombine(ISD::BSWAP);
525 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
527 // Use reciprocal estimates.
528 if (TM.Options.UnsafeFPMath) {
529 setTargetDAGCombine(ISD::FDIV);
530 setTargetDAGCombine(ISD::FSQRT);
533 // Darwin long double math library functions have $LDBL128 appended.
534 if (Subtarget->isDarwin()) {
535 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
536 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
537 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
538 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
539 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
540 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
541 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
542 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
543 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
544 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
547 setMinFunctionAlignment(2);
548 if (PPCSubTarget.isDarwin())
549 setPrefFunctionAlignment(4);
551 if (isPPC64 && Subtarget->isJITCodeModel())
552 // Temporary workaround for the inability of PPC64 JIT to handle jump
554 setSupportJumpTables(false);
556 setInsertFencesForAtomic(true);
558 setSchedulingPreference(Sched::Hybrid);
560 computeRegisterProperties();
562 // The Freescale cores does better with aggressive inlining of memcpy and
563 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
564 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
565 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
566 MaxStoresPerMemset = 32;
567 MaxStoresPerMemsetOptSize = 16;
568 MaxStoresPerMemcpy = 32;
569 MaxStoresPerMemcpyOptSize = 8;
570 MaxStoresPerMemmove = 32;
571 MaxStoresPerMemmoveOptSize = 8;
573 setPrefFunctionAlignment(4);
577 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
578 /// function arguments in the caller parameter area.
579 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
580 const TargetMachine &TM = getTargetMachine();
581 // Darwin passes everything on 4 byte boundary.
582 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
585 // 16byte and wider vectors are passed on 16byte boundary.
586 if (VectorType *VTy = dyn_cast<VectorType>(Ty))
587 if (VTy->getBitWidth() >= 128)
590 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
591 if (PPCSubTarget.isPPC64())
597 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
600 case PPCISD::FSEL: return "PPCISD::FSEL";
601 case PPCISD::FCFID: return "PPCISD::FCFID";
602 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
603 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
604 case PPCISD::FRE: return "PPCISD::FRE";
605 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
606 case PPCISD::STFIWX: return "PPCISD::STFIWX";
607 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
608 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
609 case PPCISD::VPERM: return "PPCISD::VPERM";
610 case PPCISD::Hi: return "PPCISD::Hi";
611 case PPCISD::Lo: return "PPCISD::Lo";
612 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
613 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
614 case PPCISD::LOAD: return "PPCISD::LOAD";
615 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
616 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
617 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
618 case PPCISD::SRL: return "PPCISD::SRL";
619 case PPCISD::SRA: return "PPCISD::SRA";
620 case PPCISD::SHL: return "PPCISD::SHL";
621 case PPCISD::CALL: return "PPCISD::CALL";
622 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
623 case PPCISD::MTCTR: return "PPCISD::MTCTR";
624 case PPCISD::BCTRL: return "PPCISD::BCTRL";
625 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
626 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
627 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
628 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
629 case PPCISD::VCMP: return "PPCISD::VCMP";
630 case PPCISD::VCMPo: return "PPCISD::VCMPo";
631 case PPCISD::LBRX: return "PPCISD::LBRX";
632 case PPCISD::STBRX: return "PPCISD::STBRX";
633 case PPCISD::LARX: return "PPCISD::LARX";
634 case PPCISD::STCX: return "PPCISD::STCX";
635 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
636 case PPCISD::BDNZ: return "PPCISD::BDNZ";
637 case PPCISD::BDZ: return "PPCISD::BDZ";
638 case PPCISD::MFFS: return "PPCISD::MFFS";
639 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
640 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
641 case PPCISD::CR6SET: return "PPCISD::CR6SET";
642 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
643 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
644 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
645 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
646 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
647 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
648 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
649 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
650 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
651 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
652 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
653 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
654 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
655 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
656 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
657 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
658 case PPCISD::SC: return "PPCISD::SC";
662 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
665 return VT.changeVectorElementTypeToInteger();
668 //===----------------------------------------------------------------------===//
669 // Node matching predicates, for use by the tblgen matching code.
670 //===----------------------------------------------------------------------===//
672 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
673 static bool isFloatingPointZero(SDValue Op) {
674 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
675 return CFP->getValueAPF().isZero();
676 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
677 // Maybe this has already been legalized into the constant pool?
678 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
679 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
680 return CFP->getValueAPF().isZero();
685 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
686 /// true if Op is undef or if it matches the specified value.
687 static bool isConstantOrUndef(int Op, int Val) {
688 return Op < 0 || Op == Val;
691 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
692 /// VPKUHUM instruction.
693 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
695 for (unsigned i = 0; i != 16; ++i)
696 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
699 for (unsigned i = 0; i != 8; ++i)
700 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
701 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
707 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
708 /// VPKUWUM instruction.
709 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
711 for (unsigned i = 0; i != 16; i += 2)
712 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
713 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
716 for (unsigned i = 0; i != 8; i += 2)
717 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
718 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
719 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
720 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
726 /// isVMerge - Common function, used to match vmrg* shuffles.
728 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
729 unsigned LHSStart, unsigned RHSStart) {
730 assert(N->getValueType(0) == MVT::v16i8 &&
731 "PPC only supports shuffles by bytes!");
732 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
733 "Unsupported merge size!");
735 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
736 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
737 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
738 LHSStart+j+i*UnitSize) ||
739 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
740 RHSStart+j+i*UnitSize))
746 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
747 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
748 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
751 return isVMerge(N, UnitSize, 8, 24);
752 return isVMerge(N, UnitSize, 8, 8);
755 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
756 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
757 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
760 return isVMerge(N, UnitSize, 0, 16);
761 return isVMerge(N, UnitSize, 0, 0);
765 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
766 /// amount, otherwise return -1.
767 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
768 assert(N->getValueType(0) == MVT::v16i8 &&
769 "PPC only supports shuffles by bytes!");
771 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
773 // Find the first non-undef value in the shuffle mask.
775 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
778 if (i == 16) return -1; // all undef.
780 // Otherwise, check to see if the rest of the elements are consecutively
781 // numbered from this value.
782 unsigned ShiftAmt = SVOp->getMaskElt(i);
783 if (ShiftAmt < i) return -1;
787 // Check the rest of the elements to see if they are consecutive.
788 for (++i; i != 16; ++i)
789 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
792 // Check the rest of the elements to see if they are consecutive.
793 for (++i; i != 16; ++i)
794 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
800 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
801 /// specifies a splat of a single element that is suitable for input to
802 /// VSPLTB/VSPLTH/VSPLTW.
803 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
804 assert(N->getValueType(0) == MVT::v16i8 &&
805 (EltSize == 1 || EltSize == 2 || EltSize == 4));
807 // This is a splat operation if each element of the permute is the same, and
808 // if the value doesn't reference the second vector.
809 unsigned ElementBase = N->getMaskElt(0);
811 // FIXME: Handle UNDEF elements too!
812 if (ElementBase >= 16)
815 // Check that the indices are consecutive, in the case of a multi-byte element
816 // splatted with a v16i8 mask.
817 for (unsigned i = 1; i != EltSize; ++i)
818 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
821 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
822 if (N->getMaskElt(i) < 0) continue;
823 for (unsigned j = 0; j != EltSize; ++j)
824 if (N->getMaskElt(i+j) != N->getMaskElt(j))
830 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
832 bool PPC::isAllNegativeZeroVector(SDNode *N) {
833 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
835 APInt APVal, APUndef;
839 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
840 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
841 return CFP->getValueAPF().isNegZero();
846 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
847 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
848 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
849 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
850 assert(isSplatShuffleMask(SVOp, EltSize));
851 return SVOp->getMaskElt(0) / EltSize;
854 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
855 /// by using a vspltis[bhw] instruction of the specified element size, return
856 /// the constant being splatted. The ByteSize field indicates the number of
857 /// bytes of each element [124] -> [bhw].
858 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
861 // If ByteSize of the splat is bigger than the element size of the
862 // build_vector, then we have a case where we are checking for a splat where
863 // multiple elements of the buildvector are folded together into a single
864 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
865 unsigned EltSize = 16/N->getNumOperands();
866 if (EltSize < ByteSize) {
867 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
868 SDValue UniquedVals[4];
869 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
871 // See if all of the elements in the buildvector agree across.
872 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
873 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
874 // If the element isn't a constant, bail fully out.
875 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
878 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
879 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
880 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
881 return SDValue(); // no match.
884 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
885 // either constant or undef values that are identical for each chunk. See
886 // if these chunks can form into a larger vspltis*.
888 // Check to see if all of the leading entries are either 0 or -1. If
889 // neither, then this won't fit into the immediate field.
890 bool LeadingZero = true;
891 bool LeadingOnes = true;
892 for (unsigned i = 0; i != Multiple-1; ++i) {
893 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
895 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
896 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
898 // Finally, check the least significant entry.
900 if (UniquedVals[Multiple-1].getNode() == 0)
901 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
902 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
904 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
907 if (UniquedVals[Multiple-1].getNode() == 0)
908 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
909 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
910 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
911 return DAG.getTargetConstant(Val, MVT::i32);
917 // Check to see if this buildvec has a single non-undef value in its elements.
918 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
919 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
920 if (OpVal.getNode() == 0)
921 OpVal = N->getOperand(i);
922 else if (OpVal != N->getOperand(i))
926 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
928 unsigned ValSizeInBytes = EltSize;
930 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
931 Value = CN->getZExtValue();
932 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
933 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
934 Value = FloatToBits(CN->getValueAPF().convertToFloat());
937 // If the splat value is larger than the element value, then we can never do
938 // this splat. The only case that we could fit the replicated bits into our
939 // immediate field for would be zero, and we prefer to use vxor for it.
940 if (ValSizeInBytes < ByteSize) return SDValue();
942 // If the element value is larger than the splat value, cut it in half and
943 // check to see if the two halves are equal. Continue doing this until we
944 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
945 while (ValSizeInBytes > ByteSize) {
946 ValSizeInBytes >>= 1;
948 // If the top half equals the bottom half, we're still ok.
949 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
950 (Value & ((1 << (8*ValSizeInBytes))-1)))
954 // Properly sign extend the value.
955 int MaskVal = SignExtend32(Value, ByteSize * 8);
957 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
958 if (MaskVal == 0) return SDValue();
960 // Finally, if this value fits in a 5 bit sext field, return it
961 if (SignExtend32<5>(MaskVal) == MaskVal)
962 return DAG.getTargetConstant(MaskVal, MVT::i32);
966 //===----------------------------------------------------------------------===//
967 // Addressing Mode Selection
968 //===----------------------------------------------------------------------===//
970 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
971 /// or 64-bit immediate, and if the value can be accurately represented as a
972 /// sign extension from a 16-bit value. If so, this returns true and the
974 static bool isIntS16Immediate(SDNode *N, short &Imm) {
975 if (N->getOpcode() != ISD::Constant)
978 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
979 if (N->getValueType(0) == MVT::i32)
980 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
982 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
984 static bool isIntS16Immediate(SDValue Op, short &Imm) {
985 return isIntS16Immediate(Op.getNode(), Imm);
989 /// SelectAddressRegReg - Given the specified addressed, check to see if it
990 /// can be represented as an indexed [r+r] operation. Returns false if it
991 /// can be more efficiently represented with [r+imm].
992 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
994 SelectionDAG &DAG) const {
996 if (N.getOpcode() == ISD::ADD) {
997 if (isIntS16Immediate(N.getOperand(1), imm))
999 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1000 return false; // r+i
1002 Base = N.getOperand(0);
1003 Index = N.getOperand(1);
1005 } else if (N.getOpcode() == ISD::OR) {
1006 if (isIntS16Immediate(N.getOperand(1), imm))
1007 return false; // r+i can fold it if we can.
1009 // If this is an or of disjoint bitfields, we can codegen this as an add
1010 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1012 APInt LHSKnownZero, LHSKnownOne;
1013 APInt RHSKnownZero, RHSKnownOne;
1014 DAG.ComputeMaskedBits(N.getOperand(0),
1015 LHSKnownZero, LHSKnownOne);
1017 if (LHSKnownZero.getBoolValue()) {
1018 DAG.ComputeMaskedBits(N.getOperand(1),
1019 RHSKnownZero, RHSKnownOne);
1020 // If all of the bits are known zero on the LHS or RHS, the add won't
1022 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1023 Base = N.getOperand(0);
1024 Index = N.getOperand(1);
1033 // If we happen to be doing an i64 load or store into a stack slot that has
1034 // less than a 4-byte alignment, then the frame-index elimination may need to
1035 // use an indexed load or store instruction (because the offset may not be a
1036 // multiple of 4). The extra register needed to hold the offset comes from the
1037 // register scavenger, and it is possible that the scavenger will need to use
1038 // an emergency spill slot. As a result, we need to make sure that a spill slot
1039 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1041 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1042 // FIXME: This does not handle the LWA case.
1046 // This should not be needed for negative FIs, which come from argument
1047 // lowering, because the ABI should guarentee the necessary alignment.
1051 MachineFunction &MF = DAG.getMachineFunction();
1052 MachineFrameInfo *MFI = MF.getFrameInfo();
1054 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1058 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1059 FuncInfo->setHasNonRISpills();
1062 /// Returns true if the address N can be represented by a base register plus
1063 /// a signed 16-bit displacement [r+imm], and if it is not better
1064 /// represented as reg+reg. If Aligned is true, only accept displacements
1065 /// suitable for STD and friends, i.e. multiples of 4.
1066 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1069 bool Aligned) const {
1070 // FIXME dl should come from parent load or store, not from address
1072 // If this can be more profitably realized as r+r, fail.
1073 if (SelectAddressRegReg(N, Disp, Base, DAG))
1076 if (N.getOpcode() == ISD::ADD) {
1078 if (isIntS16Immediate(N.getOperand(1), imm) &&
1079 (!Aligned || (imm & 3) == 0)) {
1080 Disp = DAG.getTargetConstant(imm, N.getValueType());
1081 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1082 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1083 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1085 Base = N.getOperand(0);
1087 return true; // [r+i]
1088 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1089 // Match LOAD (ADD (X, Lo(G))).
1090 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1091 && "Cannot handle constant offsets yet!");
1092 Disp = N.getOperand(1).getOperand(0); // The global address.
1093 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1094 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1095 Disp.getOpcode() == ISD::TargetConstantPool ||
1096 Disp.getOpcode() == ISD::TargetJumpTable);
1097 Base = N.getOperand(0);
1098 return true; // [&g+r]
1100 } else if (N.getOpcode() == ISD::OR) {
1102 if (isIntS16Immediate(N.getOperand(1), imm) &&
1103 (!Aligned || (imm & 3) == 0)) {
1104 // If this is an or of disjoint bitfields, we can codegen this as an add
1105 // (for better address arithmetic) if the LHS and RHS of the OR are
1106 // provably disjoint.
1107 APInt LHSKnownZero, LHSKnownOne;
1108 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1110 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1111 // If all of the bits are known zero on the LHS or RHS, the add won't
1113 Base = N.getOperand(0);
1114 Disp = DAG.getTargetConstant(imm, N.getValueType());
1118 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1119 // Loading from a constant address.
1121 // If this address fits entirely in a 16-bit sext immediate field, codegen
1124 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1125 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1126 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1127 CN->getValueType(0));
1131 // Handle 32-bit sext immediates with LIS + addr mode.
1132 if ((CN->getValueType(0) == MVT::i32 ||
1133 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1134 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1135 int Addr = (int)CN->getZExtValue();
1137 // Otherwise, break this down into an LIS + disp.
1138 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1140 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1141 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1142 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1147 Disp = DAG.getTargetConstant(0, getPointerTy());
1148 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1149 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1150 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1153 return true; // [r+0]
1156 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1157 /// represented as an indexed [r+r] operation.
1158 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1160 SelectionDAG &DAG) const {
1161 // Check to see if we can easily represent this as an [r+r] address. This
1162 // will fail if it thinks that the address is more profitably represented as
1163 // reg+imm, e.g. where imm = 0.
1164 if (SelectAddressRegReg(N, Base, Index, DAG))
1167 // If the operand is an addition, always emit this as [r+r], since this is
1168 // better (for code size, and execution, as the memop does the add for free)
1169 // than emitting an explicit add.
1170 if (N.getOpcode() == ISD::ADD) {
1171 Base = N.getOperand(0);
1172 Index = N.getOperand(1);
1176 // Otherwise, do it the hard way, using R0 as the base register.
1177 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1183 /// getPreIndexedAddressParts - returns true by value, base pointer and
1184 /// offset pointer and addressing mode by reference if the node's address
1185 /// can be legally represented as pre-indexed load / store address.
1186 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1188 ISD::MemIndexedMode &AM,
1189 SelectionDAG &DAG) const {
1190 if (DisablePPCPreinc) return false;
1196 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1197 Ptr = LD->getBasePtr();
1198 VT = LD->getMemoryVT();
1199 Alignment = LD->getAlignment();
1200 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1201 Ptr = ST->getBasePtr();
1202 VT = ST->getMemoryVT();
1203 Alignment = ST->getAlignment();
1208 // PowerPC doesn't have preinc load/store instructions for vectors.
1212 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1214 // Common code will reject creating a pre-inc form if the base pointer
1215 // is a frame index, or if N is a store and the base pointer is either
1216 // the same as or a predecessor of the value being stored. Check for
1217 // those situations here, and try with swapped Base/Offset instead.
1220 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1223 SDValue Val = cast<StoreSDNode>(N)->getValue();
1224 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1229 std::swap(Base, Offset);
1235 // LDU/STU can only handle immediates that are a multiple of 4.
1236 if (VT != MVT::i64) {
1237 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1240 // LDU/STU need an address with at least 4-byte alignment.
1244 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1248 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1249 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1250 // sext i32 to i64 when addr mode is r+i.
1251 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1252 LD->getExtensionType() == ISD::SEXTLOAD &&
1253 isa<ConstantSDNode>(Offset))
1261 //===----------------------------------------------------------------------===//
1262 // LowerOperation implementation
1263 //===----------------------------------------------------------------------===//
1265 /// GetLabelAccessInfo - Return true if we should reference labels using a
1266 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1267 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1268 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1269 HiOpFlags = PPCII::MO_HA;
1270 LoOpFlags = PPCII::MO_LO;
1272 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1273 // non-darwin platform. We don't support PIC on other platforms yet.
1274 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1275 TM.getSubtarget<PPCSubtarget>().isDarwin();
1277 HiOpFlags |= PPCII::MO_PIC_FLAG;
1278 LoOpFlags |= PPCII::MO_PIC_FLAG;
1281 // If this is a reference to a global value that requires a non-lazy-ptr, make
1282 // sure that instruction lowering adds it.
1283 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1284 HiOpFlags |= PPCII::MO_NLP_FLAG;
1285 LoOpFlags |= PPCII::MO_NLP_FLAG;
1287 if (GV->hasHiddenVisibility()) {
1288 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1289 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1296 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1297 SelectionDAG &DAG) {
1298 EVT PtrVT = HiPart.getValueType();
1299 SDValue Zero = DAG.getConstant(0, PtrVT);
1302 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1303 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1305 // With PIC, the first instruction is actually "GR+hi(&G)".
1307 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1308 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1310 // Generate non-pic code that has direct accesses to the constant pool.
1311 // The address of the global is just (hi(&g)+lo(&g)).
1312 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1315 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1316 SelectionDAG &DAG) const {
1317 EVT PtrVT = Op.getValueType();
1318 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1319 const Constant *C = CP->getConstVal();
1321 // 64-bit SVR4 ABI code is always position-independent.
1322 // The actual address of the GlobalValue is stored in the TOC.
1323 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1324 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1325 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1326 DAG.getRegister(PPC::X2, MVT::i64));
1329 unsigned MOHiFlag, MOLoFlag;
1330 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1332 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1334 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1335 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1338 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1339 EVT PtrVT = Op.getValueType();
1340 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1342 // 64-bit SVR4 ABI code is always position-independent.
1343 // The actual address of the GlobalValue is stored in the TOC.
1344 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1345 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1346 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1347 DAG.getRegister(PPC::X2, MVT::i64));
1350 unsigned MOHiFlag, MOLoFlag;
1351 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1352 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1353 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1354 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1357 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1358 SelectionDAG &DAG) const {
1359 EVT PtrVT = Op.getValueType();
1361 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1363 unsigned MOHiFlag, MOLoFlag;
1364 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1365 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1366 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1367 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1370 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1371 SelectionDAG &DAG) const {
1373 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1375 const GlobalValue *GV = GA->getGlobal();
1376 EVT PtrVT = getPointerTy();
1377 bool is64bit = PPCSubTarget.isPPC64();
1379 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1381 if (Model == TLSModel::LocalExec) {
1382 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1383 PPCII::MO_TPREL_HA);
1384 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1385 PPCII::MO_TPREL_LO);
1386 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1387 is64bit ? MVT::i64 : MVT::i32);
1388 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1389 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1393 llvm_unreachable("only local-exec is currently supported for ppc32");
1395 if (Model == TLSModel::InitialExec) {
1396 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1397 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1399 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1400 SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1401 PtrVT, GOTReg, TGA);
1402 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1403 PtrVT, TGA, TPOffsetHi);
1404 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1407 if (Model == TLSModel::GeneralDynamic) {
1408 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1409 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1410 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1412 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1415 // We need a chain node, and don't have one handy. The underlying
1416 // call has no side effects, so using the function entry node
1418 SDValue Chain = DAG.getEntryNode();
1419 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1420 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1421 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1422 PtrVT, ParmReg, TGA);
1423 // The return value from GET_TLS_ADDR really is in X3 already, but
1424 // some hacks are needed here to tie everything together. The extra
1425 // copies dissolve during subsequent transforms.
1426 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1427 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1430 if (Model == TLSModel::LocalDynamic) {
1431 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1432 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1433 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1435 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1438 // We need a chain node, and don't have one handy. The underlying
1439 // call has no side effects, so using the function entry node
1441 SDValue Chain = DAG.getEntryNode();
1442 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1443 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1444 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1445 PtrVT, ParmReg, TGA);
1446 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1447 // some hacks are needed here to tie everything together. The extra
1448 // copies dissolve during subsequent transforms.
1449 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1450 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1451 Chain, ParmReg, TGA);
1452 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1455 llvm_unreachable("Unknown TLS model!");
1458 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1459 SelectionDAG &DAG) const {
1460 EVT PtrVT = Op.getValueType();
1461 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1463 const GlobalValue *GV = GSDN->getGlobal();
1465 // 64-bit SVR4 ABI code is always position-independent.
1466 // The actual address of the GlobalValue is stored in the TOC.
1467 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1468 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1469 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1470 DAG.getRegister(PPC::X2, MVT::i64));
1473 unsigned MOHiFlag, MOLoFlag;
1474 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1477 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1479 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1481 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1483 // If the global reference is actually to a non-lazy-pointer, we have to do an
1484 // extra load to get the address of the global.
1485 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1486 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1487 false, false, false, 0);
1491 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1492 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1495 // If we're comparing for equality to zero, expose the fact that this is
1496 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1497 // fold the new nodes.
1498 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1499 if (C->isNullValue() && CC == ISD::SETEQ) {
1500 EVT VT = Op.getOperand(0).getValueType();
1501 SDValue Zext = Op.getOperand(0);
1502 if (VT.bitsLT(MVT::i32)) {
1504 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1506 unsigned Log2b = Log2_32(VT.getSizeInBits());
1507 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1508 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1509 DAG.getConstant(Log2b, MVT::i32));
1510 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1512 // Leave comparisons against 0 and -1 alone for now, since they're usually
1513 // optimized. FIXME: revisit this when we can custom lower all setcc
1515 if (C->isAllOnesValue() || C->isNullValue())
1519 // If we have an integer seteq/setne, turn it into a compare against zero
1520 // by xor'ing the rhs with the lhs, which is faster than setting a
1521 // condition register, reading it back out, and masking the correct bit. The
1522 // normal approach here uses sub to do this instead of xor. Using xor exposes
1523 // the result to other bit-twiddling opportunities.
1524 EVT LHSVT = Op.getOperand(0).getValueType();
1525 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1526 EVT VT = Op.getValueType();
1527 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1529 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1534 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1535 const PPCSubtarget &Subtarget) const {
1536 SDNode *Node = Op.getNode();
1537 EVT VT = Node->getValueType(0);
1538 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1539 SDValue InChain = Node->getOperand(0);
1540 SDValue VAListPtr = Node->getOperand(1);
1541 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1544 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1547 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1548 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1550 InChain = GprIndex.getValue(1);
1552 if (VT == MVT::i64) {
1553 // Check if GprIndex is even
1554 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1555 DAG.getConstant(1, MVT::i32));
1556 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1557 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1558 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1559 DAG.getConstant(1, MVT::i32));
1560 // Align GprIndex to be even if it isn't
1561 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1565 // fpr index is 1 byte after gpr
1566 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1567 DAG.getConstant(1, MVT::i32));
1570 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1571 FprPtr, MachinePointerInfo(SV), MVT::i8,
1573 InChain = FprIndex.getValue(1);
1575 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1576 DAG.getConstant(8, MVT::i32));
1578 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1579 DAG.getConstant(4, MVT::i32));
1582 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1583 MachinePointerInfo(), false, false,
1585 InChain = OverflowArea.getValue(1);
1587 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1588 MachinePointerInfo(), false, false,
1590 InChain = RegSaveArea.getValue(1);
1592 // select overflow_area if index > 8
1593 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1594 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1596 // adjustment constant gpr_index * 4/8
1597 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1598 VT.isInteger() ? GprIndex : FprIndex,
1599 DAG.getConstant(VT.isInteger() ? 4 : 8,
1602 // OurReg = RegSaveArea + RegConstant
1603 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1606 // Floating types are 32 bytes into RegSaveArea
1607 if (VT.isFloatingPoint())
1608 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1609 DAG.getConstant(32, MVT::i32));
1611 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1612 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1613 VT.isInteger() ? GprIndex : FprIndex,
1614 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1617 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1618 VT.isInteger() ? VAListPtr : FprPtr,
1619 MachinePointerInfo(SV),
1620 MVT::i8, false, false, 0);
1622 // determine if we should load from reg_save_area or overflow_area
1623 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1625 // increase overflow_area by 4/8 if gpr/fpr > 8
1626 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1627 DAG.getConstant(VT.isInteger() ? 4 : 8,
1630 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1633 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1635 MachinePointerInfo(),
1636 MVT::i32, false, false, 0);
1638 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1639 false, false, false, 0);
1642 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1643 SelectionDAG &DAG) const {
1644 return Op.getOperand(0);
1647 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1648 SelectionDAG &DAG) const {
1649 SDValue Chain = Op.getOperand(0);
1650 SDValue Trmp = Op.getOperand(1); // trampoline
1651 SDValue FPtr = Op.getOperand(2); // nested function
1652 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1655 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1656 bool isPPC64 = (PtrVT == MVT::i64);
1658 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1661 TargetLowering::ArgListTy Args;
1662 TargetLowering::ArgListEntry Entry;
1664 Entry.Ty = IntPtrTy;
1665 Entry.Node = Trmp; Args.push_back(Entry);
1667 // TrampSize == (isPPC64 ? 48 : 40);
1668 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1669 isPPC64 ? MVT::i64 : MVT::i32);
1670 Args.push_back(Entry);
1672 Entry.Node = FPtr; Args.push_back(Entry);
1673 Entry.Node = Nest; Args.push_back(Entry);
1675 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1676 TargetLowering::CallLoweringInfo CLI(Chain,
1677 Type::getVoidTy(*DAG.getContext()),
1678 false, false, false, false, 0,
1680 /*isTailCall=*/false,
1681 /*doesNotRet=*/false,
1682 /*isReturnValueUsed=*/true,
1683 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1685 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1687 return CallResult.second;
1690 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1691 const PPCSubtarget &Subtarget) const {
1692 MachineFunction &MF = DAG.getMachineFunction();
1693 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1697 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1698 // vastart just stores the address of the VarArgsFrameIndex slot into the
1699 // memory location argument.
1700 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1701 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1702 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1703 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1704 MachinePointerInfo(SV),
1708 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1709 // We suppose the given va_list is already allocated.
1712 // char gpr; /* index into the array of 8 GPRs
1713 // * stored in the register save area
1714 // * gpr=0 corresponds to r3,
1715 // * gpr=1 to r4, etc.
1717 // char fpr; /* index into the array of 8 FPRs
1718 // * stored in the register save area
1719 // * fpr=0 corresponds to f1,
1720 // * fpr=1 to f2, etc.
1722 // char *overflow_arg_area;
1723 // /* location on stack that holds
1724 // * the next overflow argument
1726 // char *reg_save_area;
1727 // /* where r3:r10 and f1:f8 (if saved)
1733 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1734 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1737 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1739 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1741 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1744 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1745 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1747 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1748 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1750 uint64_t FPROffset = 1;
1751 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1753 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1755 // Store first byte : number of int regs
1756 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1758 MachinePointerInfo(SV),
1759 MVT::i8, false, false, 0);
1760 uint64_t nextOffset = FPROffset;
1761 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1764 // Store second byte : number of float regs
1765 SDValue secondStore =
1766 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1767 MachinePointerInfo(SV, nextOffset), MVT::i8,
1769 nextOffset += StackOffset;
1770 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1772 // Store second word : arguments given on stack
1773 SDValue thirdStore =
1774 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1775 MachinePointerInfo(SV, nextOffset),
1777 nextOffset += FrameOffset;
1778 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1780 // Store third word : arguments given in registers
1781 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1782 MachinePointerInfo(SV, nextOffset),
1787 #include "PPCGenCallingConv.inc"
1789 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1790 CCValAssign::LocInfo &LocInfo,
1791 ISD::ArgFlagsTy &ArgFlags,
1796 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1798 CCValAssign::LocInfo &LocInfo,
1799 ISD::ArgFlagsTy &ArgFlags,
1801 static const uint16_t ArgRegs[] = {
1802 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1803 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1805 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1807 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1809 // Skip one register if the first unallocated register has an even register
1810 // number and there are still argument registers available which have not been
1811 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1812 // need to skip a register if RegNum is odd.
1813 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1814 State.AllocateReg(ArgRegs[RegNum]);
1817 // Always return false here, as this function only makes sure that the first
1818 // unallocated register has an odd register number and does not actually
1819 // allocate a register for the current argument.
1823 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1825 CCValAssign::LocInfo &LocInfo,
1826 ISD::ArgFlagsTy &ArgFlags,
1828 static const uint16_t ArgRegs[] = {
1829 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1833 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1835 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1837 // If there is only one Floating-point register left we need to put both f64
1838 // values of a split ppc_fp128 value on the stack.
1839 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1840 State.AllocateReg(ArgRegs[RegNum]);
1843 // Always return false here, as this function only makes sure that the two f64
1844 // values a ppc_fp128 value is split into are both passed in registers or both
1845 // passed on the stack and does not actually allocate a register for the
1846 // current argument.
1850 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1852 static const uint16_t *GetFPR() {
1853 static const uint16_t FPR[] = {
1854 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1855 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1861 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1863 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1864 unsigned PtrByteSize) {
1865 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1866 if (Flags.isByVal())
1867 ArgSize = Flags.getByValSize();
1868 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1874 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1875 CallingConv::ID CallConv, bool isVarArg,
1876 const SmallVectorImpl<ISD::InputArg>
1878 SDLoc dl, SelectionDAG &DAG,
1879 SmallVectorImpl<SDValue> &InVals)
1881 if (PPCSubTarget.isSVR4ABI()) {
1882 if (PPCSubTarget.isPPC64())
1883 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
1886 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
1889 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1895 PPCTargetLowering::LowerFormalArguments_32SVR4(
1897 CallingConv::ID CallConv, bool isVarArg,
1898 const SmallVectorImpl<ISD::InputArg>
1900 SDLoc dl, SelectionDAG &DAG,
1901 SmallVectorImpl<SDValue> &InVals) const {
1903 // 32-bit SVR4 ABI Stack Frame Layout:
1904 // +-----------------------------------+
1905 // +--> | Back chain |
1906 // | +-----------------------------------+
1907 // | | Floating-point register save area |
1908 // | +-----------------------------------+
1909 // | | General register save area |
1910 // | +-----------------------------------+
1911 // | | CR save word |
1912 // | +-----------------------------------+
1913 // | | VRSAVE save word |
1914 // | +-----------------------------------+
1915 // | | Alignment padding |
1916 // | +-----------------------------------+
1917 // | | Vector register save area |
1918 // | +-----------------------------------+
1919 // | | Local variable space |
1920 // | +-----------------------------------+
1921 // | | Parameter list area |
1922 // | +-----------------------------------+
1923 // | | LR save word |
1924 // | +-----------------------------------+
1925 // SP--> +--- | Back chain |
1926 // +-----------------------------------+
1929 // System V Application Binary Interface PowerPC Processor Supplement
1930 // AltiVec Technology Programming Interface Manual
1932 MachineFunction &MF = DAG.getMachineFunction();
1933 MachineFrameInfo *MFI = MF.getFrameInfo();
1934 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1936 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1937 // Potential tail calls could cause overwriting of argument stack slots.
1938 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1939 (CallConv == CallingConv::Fast));
1940 unsigned PtrByteSize = 4;
1942 // Assign locations to all of the incoming arguments.
1943 SmallVector<CCValAssign, 16> ArgLocs;
1944 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1945 getTargetMachine(), ArgLocs, *DAG.getContext());
1947 // Reserve space for the linkage area on the stack.
1948 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
1950 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
1952 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1953 CCValAssign &VA = ArgLocs[i];
1955 // Arguments stored in registers.
1956 if (VA.isRegLoc()) {
1957 const TargetRegisterClass *RC;
1958 EVT ValVT = VA.getValVT();
1960 switch (ValVT.getSimpleVT().SimpleTy) {
1962 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1964 RC = &PPC::GPRCRegClass;
1967 RC = &PPC::F4RCRegClass;
1970 RC = &PPC::F8RCRegClass;
1976 RC = &PPC::VRRCRegClass;
1980 // Transform the arguments stored in physical registers into virtual ones.
1981 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1982 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1984 InVals.push_back(ArgValue);
1986 // Argument stored in memory.
1987 assert(VA.isMemLoc());
1989 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1990 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1993 // Create load nodes to retrieve arguments from the stack.
1994 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1995 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1996 MachinePointerInfo(),
1997 false, false, false, 0));
2001 // Assign locations to all of the incoming aggregate by value arguments.
2002 // Aggregates passed by value are stored in the local variable space of the
2003 // caller's stack frame, right above the parameter list area.
2004 SmallVector<CCValAssign, 16> ByValArgLocs;
2005 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2006 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2008 // Reserve stack space for the allocations in CCInfo.
2009 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2011 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2013 // Area that is at least reserved in the caller of this function.
2014 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2016 // Set the size that is at least reserved in caller of this function. Tail
2017 // call optimized function's reserved stack space needs to be aligned so that
2018 // taking the difference between two stack areas will result in an aligned
2020 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2023 std::max(MinReservedArea,
2024 PPCFrameLowering::getMinCallFrameSize(false, false));
2026 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2027 getStackAlignment();
2028 unsigned AlignMask = TargetAlign-1;
2029 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2031 FI->setMinReservedArea(MinReservedArea);
2033 SmallVector<SDValue, 8> MemOps;
2035 // If the function takes variable number of arguments, make a frame index for
2036 // the start of the first vararg value... for expansion of llvm.va_start.
2038 static const uint16_t GPArgRegs[] = {
2039 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2040 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2042 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2044 static const uint16_t FPArgRegs[] = {
2045 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2048 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2050 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2052 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2055 // Make room for NumGPArgRegs and NumFPArgRegs.
2056 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2057 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2059 FuncInfo->setVarArgsStackOffset(
2060 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2061 CCInfo.getNextStackOffset(), true));
2063 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2064 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2066 // The fixed integer arguments of a variadic function are stored to the
2067 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2068 // the result of va_next.
2069 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2070 // Get an existing live-in vreg, or add a new one.
2071 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2073 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2075 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2076 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2077 MachinePointerInfo(), false, false, 0);
2078 MemOps.push_back(Store);
2079 // Increment the address by four for the next argument to store
2080 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2081 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2084 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2086 // The double arguments are stored to the VarArgsFrameIndex
2088 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2089 // Get an existing live-in vreg, or add a new one.
2090 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2092 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2094 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2095 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2096 MachinePointerInfo(), false, false, 0);
2097 MemOps.push_back(Store);
2098 // Increment the address by eight for the next argument to store
2099 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2101 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2105 if (!MemOps.empty())
2106 Chain = DAG.getNode(ISD::TokenFactor, dl,
2107 MVT::Other, &MemOps[0], MemOps.size());
2112 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2113 // value to MVT::i64 and then truncate to the correct register size.
2115 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2116 SelectionDAG &DAG, SDValue ArgVal,
2119 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2120 DAG.getValueType(ObjectVT));
2121 else if (Flags.isZExt())
2122 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2123 DAG.getValueType(ObjectVT));
2125 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2128 // Set the size that is at least reserved in caller of this function. Tail
2129 // call optimized functions' reserved stack space needs to be aligned so that
2130 // taking the difference between two stack areas will result in an aligned
2133 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2134 unsigned nAltivecParamsAtEnd,
2135 unsigned MinReservedArea,
2136 bool isPPC64) const {
2137 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2138 // Add the Altivec parameters at the end, if needed.
2139 if (nAltivecParamsAtEnd) {
2140 MinReservedArea = ((MinReservedArea+15)/16)*16;
2141 MinReservedArea += 16*nAltivecParamsAtEnd;
2144 std::max(MinReservedArea,
2145 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2146 unsigned TargetAlign
2147 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2148 getStackAlignment();
2149 unsigned AlignMask = TargetAlign-1;
2150 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2151 FI->setMinReservedArea(MinReservedArea);
2155 PPCTargetLowering::LowerFormalArguments_64SVR4(
2157 CallingConv::ID CallConv, bool isVarArg,
2158 const SmallVectorImpl<ISD::InputArg>
2160 SDLoc dl, SelectionDAG &DAG,
2161 SmallVectorImpl<SDValue> &InVals) const {
2162 // TODO: add description of PPC stack frame format, or at least some docs.
2164 MachineFunction &MF = DAG.getMachineFunction();
2165 MachineFrameInfo *MFI = MF.getFrameInfo();
2166 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2168 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2169 // Potential tail calls could cause overwriting of argument stack slots.
2170 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2171 (CallConv == CallingConv::Fast));
2172 unsigned PtrByteSize = 8;
2174 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2175 // Area that is at least reserved in caller of this function.
2176 unsigned MinReservedArea = ArgOffset;
2178 static const uint16_t GPR[] = {
2179 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2180 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2183 static const uint16_t *FPR = GetFPR();
2185 static const uint16_t VR[] = {
2186 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2187 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2190 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2191 const unsigned Num_FPR_Regs = 13;
2192 const unsigned Num_VR_Regs = array_lengthof(VR);
2194 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2196 // Add DAG nodes to load the arguments or copy them out of registers. On
2197 // entry to a function on PPC, the arguments start after the linkage area,
2198 // although the first ones are often in registers.
2200 SmallVector<SDValue, 8> MemOps;
2201 unsigned nAltivecParamsAtEnd = 0;
2202 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2203 unsigned CurArgIdx = 0;
2204 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2206 bool needsLoad = false;
2207 EVT ObjectVT = Ins[ArgNo].VT;
2208 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2209 unsigned ArgSize = ObjSize;
2210 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2211 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2212 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2214 unsigned CurArgOffset = ArgOffset;
2216 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2217 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2218 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2220 MinReservedArea = ((MinReservedArea+15)/16)*16;
2221 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2225 nAltivecParamsAtEnd++;
2227 // Calculate min reserved area.
2228 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2232 // FIXME the codegen can be much improved in some cases.
2233 // We do not have to keep everything in memory.
2234 if (Flags.isByVal()) {
2235 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2236 ObjSize = Flags.getByValSize();
2237 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2238 // Empty aggregate parameters do not take up registers. Examples:
2242 // etc. However, we have to provide a place-holder in InVals, so
2243 // pretend we have an 8-byte item at the current address for that
2246 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2247 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2248 InVals.push_back(FIN);
2251 // All aggregates smaller than 8 bytes must be passed right-justified.
2252 if (ObjSize < PtrByteSize)
2253 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2254 // The value of the object is its address.
2255 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2256 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2257 InVals.push_back(FIN);
2260 if (GPR_idx != Num_GPR_Regs) {
2261 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2262 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2265 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2266 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2267 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2268 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2269 MachinePointerInfo(FuncArg, CurArgOffset),
2270 ObjType, false, false, 0);
2272 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2273 // store the whole register as-is to the parameter save area
2274 // slot. The address of the parameter was already calculated
2275 // above (InVals.push_back(FIN)) to be the right-justified
2276 // offset within the slot. For this store, we need a new
2277 // frame index that points at the beginning of the slot.
2278 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2279 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2280 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2281 MachinePointerInfo(FuncArg, ArgOffset),
2285 MemOps.push_back(Store);
2288 // Whether we copied from a register or not, advance the offset
2289 // into the parameter save area by a full doubleword.
2290 ArgOffset += PtrByteSize;
2294 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2295 // Store whatever pieces of the object are in registers
2296 // to memory. ArgOffset will be the address of the beginning
2298 if (GPR_idx != Num_GPR_Regs) {
2300 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2301 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2302 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2303 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2304 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2305 MachinePointerInfo(FuncArg, ArgOffset),
2307 MemOps.push_back(Store);
2309 ArgOffset += PtrByteSize;
2311 ArgOffset += ArgSize - j;
2318 switch (ObjectVT.getSimpleVT().SimpleTy) {
2319 default: llvm_unreachable("Unhandled argument type!");
2322 if (GPR_idx != Num_GPR_Regs) {
2323 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2324 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2326 if (ObjectVT == MVT::i32)
2327 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2328 // value to MVT::i64 and then truncate to the correct register size.
2329 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2334 ArgSize = PtrByteSize;
2341 // Every 8 bytes of argument space consumes one of the GPRs available for
2342 // argument passing.
2343 if (GPR_idx != Num_GPR_Regs) {
2346 if (FPR_idx != Num_FPR_Regs) {
2349 if (ObjectVT == MVT::f32)
2350 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2352 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2354 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2358 ArgSize = PtrByteSize;
2367 // Note that vector arguments in registers don't reserve stack space,
2368 // except in varargs functions.
2369 if (VR_idx != Num_VR_Regs) {
2370 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2371 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2373 while ((ArgOffset % 16) != 0) {
2374 ArgOffset += PtrByteSize;
2375 if (GPR_idx != Num_GPR_Regs)
2379 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2383 // Vectors are aligned.
2384 ArgOffset = ((ArgOffset+15)/16)*16;
2385 CurArgOffset = ArgOffset;
2392 // We need to load the argument to a virtual register if we determined
2393 // above that we ran out of physical registers of the appropriate type.
2395 int FI = MFI->CreateFixedObject(ObjSize,
2396 CurArgOffset + (ArgSize - ObjSize),
2398 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2399 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2400 false, false, false, 0);
2403 InVals.push_back(ArgVal);
2406 // Set the size that is at least reserved in caller of this function. Tail
2407 // call optimized functions' reserved stack space needs to be aligned so that
2408 // taking the difference between two stack areas will result in an aligned
2410 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2412 // If the function takes variable number of arguments, make a frame index for
2413 // the start of the first vararg value... for expansion of llvm.va_start.
2415 int Depth = ArgOffset;
2417 FuncInfo->setVarArgsFrameIndex(
2418 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2419 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2421 // If this function is vararg, store any remaining integer argument regs
2422 // to their spots on the stack so that they may be loaded by deferencing the
2423 // result of va_next.
2424 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2425 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2426 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2427 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2428 MachinePointerInfo(), false, false, 0);
2429 MemOps.push_back(Store);
2430 // Increment the address by four for the next argument to store
2431 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2432 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2436 if (!MemOps.empty())
2437 Chain = DAG.getNode(ISD::TokenFactor, dl,
2438 MVT::Other, &MemOps[0], MemOps.size());
2444 PPCTargetLowering::LowerFormalArguments_Darwin(
2446 CallingConv::ID CallConv, bool isVarArg,
2447 const SmallVectorImpl<ISD::InputArg>
2449 SDLoc dl, SelectionDAG &DAG,
2450 SmallVectorImpl<SDValue> &InVals) const {
2451 // TODO: add description of PPC stack frame format, or at least some docs.
2453 MachineFunction &MF = DAG.getMachineFunction();
2454 MachineFrameInfo *MFI = MF.getFrameInfo();
2455 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2457 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2458 bool isPPC64 = PtrVT == MVT::i64;
2459 // Potential tail calls could cause overwriting of argument stack slots.
2460 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2461 (CallConv == CallingConv::Fast));
2462 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2464 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2465 // Area that is at least reserved in caller of this function.
2466 unsigned MinReservedArea = ArgOffset;
2468 static const uint16_t GPR_32[] = { // 32-bit registers.
2469 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2470 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2472 static const uint16_t GPR_64[] = { // 64-bit registers.
2473 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2474 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2477 static const uint16_t *FPR = GetFPR();
2479 static const uint16_t VR[] = {
2480 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2481 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2484 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2485 const unsigned Num_FPR_Regs = 13;
2486 const unsigned Num_VR_Regs = array_lengthof( VR);
2488 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2490 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2492 // In 32-bit non-varargs functions, the stack space for vectors is after the
2493 // stack space for non-vectors. We do not use this space unless we have
2494 // too many vectors to fit in registers, something that only occurs in
2495 // constructed examples:), but we have to walk the arglist to figure
2496 // that out...for the pathological case, compute VecArgOffset as the
2497 // start of the vector parameter area. Computing VecArgOffset is the
2498 // entire point of the following loop.
2499 unsigned VecArgOffset = ArgOffset;
2500 if (!isVarArg && !isPPC64) {
2501 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2503 EVT ObjectVT = Ins[ArgNo].VT;
2504 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2506 if (Flags.isByVal()) {
2507 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2508 unsigned ObjSize = Flags.getByValSize();
2510 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2511 VecArgOffset += ArgSize;
2515 switch(ObjectVT.getSimpleVT().SimpleTy) {
2516 default: llvm_unreachable("Unhandled argument type!");
2521 case MVT::i64: // PPC64
2523 // FIXME: We are guaranteed to be !isPPC64 at this point.
2524 // Does MVT::i64 apply?
2531 // Nothing to do, we're only looking at Nonvector args here.
2536 // We've found where the vector parameter area in memory is. Skip the
2537 // first 12 parameters; these don't use that memory.
2538 VecArgOffset = ((VecArgOffset+15)/16)*16;
2539 VecArgOffset += 12*16;
2541 // Add DAG nodes to load the arguments or copy them out of registers. On
2542 // entry to a function on PPC, the arguments start after the linkage area,
2543 // although the first ones are often in registers.
2545 SmallVector<SDValue, 8> MemOps;
2546 unsigned nAltivecParamsAtEnd = 0;
2547 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2548 unsigned CurArgIdx = 0;
2549 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2551 bool needsLoad = false;
2552 EVT ObjectVT = Ins[ArgNo].VT;
2553 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2554 unsigned ArgSize = ObjSize;
2555 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2556 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2557 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2559 unsigned CurArgOffset = ArgOffset;
2561 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2562 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2563 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2564 if (isVarArg || isPPC64) {
2565 MinReservedArea = ((MinReservedArea+15)/16)*16;
2566 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2569 } else nAltivecParamsAtEnd++;
2571 // Calculate min reserved area.
2572 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2576 // FIXME the codegen can be much improved in some cases.
2577 // We do not have to keep everything in memory.
2578 if (Flags.isByVal()) {
2579 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2580 ObjSize = Flags.getByValSize();
2581 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2582 // Objects of size 1 and 2 are right justified, everything else is
2583 // left justified. This means the memory address is adjusted forwards.
2584 if (ObjSize==1 || ObjSize==2) {
2585 CurArgOffset = CurArgOffset + (4 - ObjSize);
2587 // The value of the object is its address.
2588 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2589 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2590 InVals.push_back(FIN);
2591 if (ObjSize==1 || ObjSize==2) {
2592 if (GPR_idx != Num_GPR_Regs) {
2595 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2597 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2598 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2599 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2600 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2601 MachinePointerInfo(FuncArg,
2603 ObjType, false, false, 0);
2604 MemOps.push_back(Store);
2608 ArgOffset += PtrByteSize;
2612 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2613 // Store whatever pieces of the object are in registers
2614 // to memory. ArgOffset will be the address of the beginning
2616 if (GPR_idx != Num_GPR_Regs) {
2619 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2621 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2622 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2623 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2624 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2625 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2626 MachinePointerInfo(FuncArg, ArgOffset),
2628 MemOps.push_back(Store);
2630 ArgOffset += PtrByteSize;
2632 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2639 switch (ObjectVT.getSimpleVT().SimpleTy) {
2640 default: llvm_unreachable("Unhandled argument type!");
2643 if (GPR_idx != Num_GPR_Regs) {
2644 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2645 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2649 ArgSize = PtrByteSize;
2651 // All int arguments reserve stack space in the Darwin ABI.
2652 ArgOffset += PtrByteSize;
2656 case MVT::i64: // PPC64
2657 if (GPR_idx != Num_GPR_Regs) {
2658 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2659 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2661 if (ObjectVT == MVT::i32)
2662 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2663 // value to MVT::i64 and then truncate to the correct register size.
2664 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2669 ArgSize = PtrByteSize;
2671 // All int arguments reserve stack space in the Darwin ABI.
2677 // Every 4 bytes of argument space consumes one of the GPRs available for
2678 // argument passing.
2679 if (GPR_idx != Num_GPR_Regs) {
2681 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2684 if (FPR_idx != Num_FPR_Regs) {
2687 if (ObjectVT == MVT::f32)
2688 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2690 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2692 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2698 // All FP arguments reserve stack space in the Darwin ABI.
2699 ArgOffset += isPPC64 ? 8 : ObjSize;
2705 // Note that vector arguments in registers don't reserve stack space,
2706 // except in varargs functions.
2707 if (VR_idx != Num_VR_Regs) {
2708 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2709 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2711 while ((ArgOffset % 16) != 0) {
2712 ArgOffset += PtrByteSize;
2713 if (GPR_idx != Num_GPR_Regs)
2717 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2721 if (!isVarArg && !isPPC64) {
2722 // Vectors go after all the nonvectors.
2723 CurArgOffset = VecArgOffset;
2726 // Vectors are aligned.
2727 ArgOffset = ((ArgOffset+15)/16)*16;
2728 CurArgOffset = ArgOffset;
2736 // We need to load the argument to a virtual register if we determined above
2737 // that we ran out of physical registers of the appropriate type.
2739 int FI = MFI->CreateFixedObject(ObjSize,
2740 CurArgOffset + (ArgSize - ObjSize),
2742 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2743 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2744 false, false, false, 0);
2747 InVals.push_back(ArgVal);
2750 // Set the size that is at least reserved in caller of this function. Tail
2751 // call optimized functions' reserved stack space needs to be aligned so that
2752 // taking the difference between two stack areas will result in an aligned
2754 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
2756 // If the function takes variable number of arguments, make a frame index for
2757 // the start of the first vararg value... for expansion of llvm.va_start.
2759 int Depth = ArgOffset;
2761 FuncInfo->setVarArgsFrameIndex(
2762 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2764 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2766 // If this function is vararg, store any remaining integer argument regs
2767 // to their spots on the stack so that they may be loaded by deferencing the
2768 // result of va_next.
2769 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2773 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2775 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2777 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2778 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2779 MachinePointerInfo(), false, false, 0);
2780 MemOps.push_back(Store);
2781 // Increment the address by four for the next argument to store
2782 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2783 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2787 if (!MemOps.empty())
2788 Chain = DAG.getNode(ISD::TokenFactor, dl,
2789 MVT::Other, &MemOps[0], MemOps.size());
2794 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
2795 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
2797 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2801 const SmallVectorImpl<ISD::OutputArg>
2803 const SmallVectorImpl<SDValue> &OutVals,
2804 unsigned &nAltivecParamsAtEnd) {
2805 // Count how many bytes are to be pushed on the stack, including the linkage
2806 // area, and parameter passing area. We start with 24/48 bytes, which is
2807 // prereserved space for [SP][CR][LR][3 x unused].
2808 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2809 unsigned NumOps = Outs.size();
2810 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2812 // Add up all the space actually used.
2813 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2814 // they all go in registers, but we must reserve stack space for them for
2815 // possible use by the caller. In varargs or 64-bit calls, parameters are
2816 // assigned stack space in order, with padding so Altivec parameters are
2818 nAltivecParamsAtEnd = 0;
2819 for (unsigned i = 0; i != NumOps; ++i) {
2820 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2821 EVT ArgVT = Outs[i].VT;
2822 // Varargs Altivec parameters are padded to a 16 byte boundary.
2823 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2824 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2825 if (!isVarArg && !isPPC64) {
2826 // Non-varargs Altivec parameters go after all the non-Altivec
2827 // parameters; handle those later so we know how much padding we need.
2828 nAltivecParamsAtEnd++;
2831 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2832 NumBytes = ((NumBytes+15)/16)*16;
2834 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2837 // Allow for Altivec parameters at the end, if needed.
2838 if (nAltivecParamsAtEnd) {
2839 NumBytes = ((NumBytes+15)/16)*16;
2840 NumBytes += 16*nAltivecParamsAtEnd;
2843 // The prolog code of the callee may store up to 8 GPR argument registers to
2844 // the stack, allowing va_start to index over them in memory if its varargs.
2845 // Because we cannot tell if this is needed on the caller side, we have to
2846 // conservatively assume that it is needed. As such, make sure we have at
2847 // least enough stack space for the caller to store the 8 GPRs.
2848 NumBytes = std::max(NumBytes,
2849 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2851 // Tail call needs the stack to be aligned.
2852 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2853 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2854 getFrameLowering()->getStackAlignment();
2855 unsigned AlignMask = TargetAlign-1;
2856 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2862 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2863 /// adjusted to accommodate the arguments for the tailcall.
2864 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2865 unsigned ParamSize) {
2867 if (!isTailCall) return 0;
2869 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2870 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2871 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2872 // Remember only if the new adjustement is bigger.
2873 if (SPDiff < FI->getTailCallSPDelta())
2874 FI->setTailCallSPDelta(SPDiff);
2879 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2880 /// for tail call optimization. Targets which want to do tail call
2881 /// optimization should implement this function.
2883 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2884 CallingConv::ID CalleeCC,
2886 const SmallVectorImpl<ISD::InputArg> &Ins,
2887 SelectionDAG& DAG) const {
2888 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2891 // Variable argument functions are not supported.
2895 MachineFunction &MF = DAG.getMachineFunction();
2896 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2897 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2898 // Functions containing by val parameters are not supported.
2899 for (unsigned i = 0; i != Ins.size(); i++) {
2900 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2901 if (Flags.isByVal()) return false;
2904 // Non PIC/GOT tail calls are supported.
2905 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2908 // At the moment we can only do local tail calls (in same module, hidden
2909 // or protected) if we are generating PIC.
2910 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2911 return G->getGlobal()->hasHiddenVisibility()
2912 || G->getGlobal()->hasProtectedVisibility();
2918 /// isCallCompatibleAddress - Return the immediate to use if the specified
2919 /// 32-bit value is representable in the immediate field of a BxA instruction.
2920 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2921 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2924 int Addr = C->getZExtValue();
2925 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2926 SignExtend32<26>(Addr) != Addr)
2927 return 0; // Top 6 bits have to be sext of immediate.
2929 return DAG.getConstant((int)C->getZExtValue() >> 2,
2930 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2935 struct TailCallArgumentInfo {
2940 TailCallArgumentInfo() : FrameIdx(0) {}
2945 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2947 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2949 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2950 SmallVector<SDValue, 8> &MemOpChains,
2952 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2953 SDValue Arg = TailCallArgs[i].Arg;
2954 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2955 int FI = TailCallArgs[i].FrameIdx;
2956 // Store relative to framepointer.
2957 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2958 MachinePointerInfo::getFixedStack(FI),
2963 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2964 /// the appropriate stack slot for the tail call optimized function call.
2965 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2966 MachineFunction &MF,
2975 // Calculate the new stack slot for the return address.
2976 int SlotSize = isPPC64 ? 8 : 4;
2977 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
2979 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2980 NewRetAddrLoc, true);
2981 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2982 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2983 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2984 MachinePointerInfo::getFixedStack(NewRetAddr),
2987 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2988 // slot as the FP is never overwritten.
2991 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2992 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
2994 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2995 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2996 MachinePointerInfo::getFixedStack(NewFPIdx),
3003 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3004 /// the position of the argument.
3006 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3007 SDValue Arg, int SPDiff, unsigned ArgOffset,
3008 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
3009 int Offset = ArgOffset + SPDiff;
3010 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3011 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3012 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3013 SDValue FIN = DAG.getFrameIndex(FI, VT);
3014 TailCallArgumentInfo Info;
3016 Info.FrameIdxOp = FIN;
3018 TailCallArguments.push_back(Info);
3021 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3022 /// stack slot. Returns the chain as result and the loaded frame pointers in
3023 /// LROpOut/FPOpout. Used when tail calling.
3024 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3032 // Load the LR and FP stack slot for later adjusting.
3033 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3034 LROpOut = getReturnAddrFrameIndex(DAG);
3035 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3036 false, false, false, 0);
3037 Chain = SDValue(LROpOut.getNode(), 1);
3039 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3040 // slot as the FP is never overwritten.
3042 FPOpOut = getFramePointerFrameIndex(DAG);
3043 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3044 false, false, false, 0);
3045 Chain = SDValue(FPOpOut.getNode(), 1);
3051 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3052 /// by "Src" to address "Dst" of size "Size". Alignment information is
3053 /// specified by the specific parameter attribute. The copy will be passed as
3054 /// a byval function parameter.
3055 /// Sometimes what we are copying is the end of a larger object, the part that
3056 /// does not fit in registers.
3058 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3059 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3061 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3062 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3063 false, false, MachinePointerInfo(0),
3064 MachinePointerInfo(0));
3067 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3070 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3071 SDValue Arg, SDValue PtrOff, int SPDiff,
3072 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3073 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
3074 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
3076 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3081 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3083 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3084 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3085 DAG.getConstant(ArgOffset, PtrVT));
3087 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3088 MachinePointerInfo(), false, false, 0));
3089 // Calculate and remember argument location.
3090 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3095 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3096 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3097 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3098 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
3099 MachineFunction &MF = DAG.getMachineFunction();
3101 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3102 // might overwrite each other in case of tail call optimization.
3103 SmallVector<SDValue, 8> MemOpChains2;
3104 // Do not flag preceding copytoreg stuff together with the following stuff.
3106 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3108 if (!MemOpChains2.empty())
3109 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3110 &MemOpChains2[0], MemOpChains2.size());
3112 // Store the return address to the appropriate stack slot.
3113 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3114 isPPC64, isDarwinABI, dl);
3116 // Emit callseq_end just before tailcall node.
3117 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3118 DAG.getIntPtrConstant(0, true), InFlag, dl);
3119 InFlag = Chain.getValue(1);
3123 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3124 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3125 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
3126 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
3127 const PPCSubtarget &PPCSubTarget) {
3129 bool isPPC64 = PPCSubTarget.isPPC64();
3130 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3132 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3133 NodeTys.push_back(MVT::Other); // Returns a chain
3134 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3136 unsigned CallOpc = PPCISD::CALL;
3138 bool needIndirectCall = true;
3139 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3140 // If this is an absolute destination address, use the munged value.
3141 Callee = SDValue(Dest, 0);
3142 needIndirectCall = false;
3145 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3146 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3147 // Use indirect calls for ALL functions calls in JIT mode, since the
3148 // far-call stubs may be outside relocation limits for a BL instruction.
3149 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3150 unsigned OpFlags = 0;
3151 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3152 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3153 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3154 (G->getGlobal()->isDeclaration() ||
3155 G->getGlobal()->isWeakForLinker())) {
3156 // PC-relative references to external symbols should go through $stub,
3157 // unless we're building with the leopard linker or later, which
3158 // automatically synthesizes these stubs.
3159 OpFlags = PPCII::MO_DARWIN_STUB;
3162 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3163 // every direct call is) turn it into a TargetGlobalAddress /
3164 // TargetExternalSymbol node so that legalize doesn't hack it.
3165 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3166 Callee.getValueType(),
3168 needIndirectCall = false;
3172 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3173 unsigned char OpFlags = 0;
3175 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3176 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3177 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3178 // PC-relative references to external symbols should go through $stub,
3179 // unless we're building with the leopard linker or later, which
3180 // automatically synthesizes these stubs.
3181 OpFlags = PPCII::MO_DARWIN_STUB;
3184 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3186 needIndirectCall = false;
3189 if (needIndirectCall) {
3190 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3191 // to do the call, we can't use PPCISD::CALL.
3192 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3194 if (isSVR4ABI && isPPC64) {
3195 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3196 // entry point, but to the function descriptor (the function entry point
3197 // address is part of the function descriptor though).
3198 // The function descriptor is a three doubleword structure with the
3199 // following fields: function entry point, TOC base address and
3200 // environment pointer.
3201 // Thus for a call through a function pointer, the following actions need
3203 // 1. Save the TOC of the caller in the TOC save area of its stack
3204 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3205 // 2. Load the address of the function entry point from the function
3207 // 3. Load the TOC of the callee from the function descriptor into r2.
3208 // 4. Load the environment pointer from the function descriptor into
3210 // 5. Branch to the function entry point address.
3211 // 6. On return of the callee, the TOC of the caller needs to be
3212 // restored (this is done in FinishCall()).
3214 // All those operations are flagged together to ensure that no other
3215 // operations can be scheduled in between. E.g. without flagging the
3216 // operations together, a TOC access in the caller could be scheduled
3217 // between the load of the callee TOC and the branch to the callee, which
3218 // results in the TOC access going through the TOC of the callee instead
3219 // of going through the TOC of the caller, which leads to incorrect code.
3221 // Load the address of the function entry point from the function
3223 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3224 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
3225 InFlag.getNode() ? 3 : 2);
3226 Chain = LoadFuncPtr.getValue(1);
3227 InFlag = LoadFuncPtr.getValue(2);
3229 // Load environment pointer into r11.
3230 // Offset of the environment pointer within the function descriptor.
3231 SDValue PtrOff = DAG.getIntPtrConstant(16);
3233 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3234 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3236 Chain = LoadEnvPtr.getValue(1);
3237 InFlag = LoadEnvPtr.getValue(2);
3239 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3241 Chain = EnvVal.getValue(0);
3242 InFlag = EnvVal.getValue(1);
3244 // Load TOC of the callee into r2. We are using a target-specific load
3245 // with r2 hard coded, because the result of a target-independent load
3246 // would never go directly into r2, since r2 is a reserved register (which
3247 // prevents the register allocator from allocating it), resulting in an
3248 // additional register being allocated and an unnecessary move instruction
3250 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3251 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3253 Chain = LoadTOCPtr.getValue(0);
3254 InFlag = LoadTOCPtr.getValue(1);
3256 MTCTROps[0] = Chain;
3257 MTCTROps[1] = LoadFuncPtr;
3258 MTCTROps[2] = InFlag;
3261 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
3262 2 + (InFlag.getNode() != 0));
3263 InFlag = Chain.getValue(1);
3266 NodeTys.push_back(MVT::Other);
3267 NodeTys.push_back(MVT::Glue);
3268 Ops.push_back(Chain);
3269 CallOpc = PPCISD::BCTRL;
3271 // Add use of X11 (holding environment pointer)
3272 if (isSVR4ABI && isPPC64)
3273 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3274 // Add CTR register as callee so a bctr can be emitted later.
3276 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3279 // If this is a direct call, pass the chain and the callee.
3280 if (Callee.getNode()) {
3281 Ops.push_back(Chain);
3282 Ops.push_back(Callee);
3284 // If this is a tail call add stack pointer delta.
3286 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3288 // Add argument registers to the end of the list so that they are known live
3290 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3291 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3292 RegsToPass[i].second.getValueType()));
3298 bool isLocalCall(const SDValue &Callee)
3300 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3301 return !G->getGlobal()->isDeclaration() &&
3302 !G->getGlobal()->isWeakForLinker();
3307 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3308 CallingConv::ID CallConv, bool isVarArg,
3309 const SmallVectorImpl<ISD::InputArg> &Ins,
3310 SDLoc dl, SelectionDAG &DAG,
3311 SmallVectorImpl<SDValue> &InVals) const {
3313 SmallVector<CCValAssign, 16> RVLocs;
3314 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3315 getTargetMachine(), RVLocs, *DAG.getContext());
3316 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3318 // Copy all of the result registers out of their specified physreg.
3319 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3320 CCValAssign &VA = RVLocs[i];
3321 assert(VA.isRegLoc() && "Can only return in registers!");
3323 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3324 VA.getLocReg(), VA.getLocVT(), InFlag);
3325 Chain = Val.getValue(1);
3326 InFlag = Val.getValue(2);
3328 switch (VA.getLocInfo()) {
3329 default: llvm_unreachable("Unknown loc info!");
3330 case CCValAssign::Full: break;
3331 case CCValAssign::AExt:
3332 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3334 case CCValAssign::ZExt:
3335 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3336 DAG.getValueType(VA.getValVT()));
3337 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3339 case CCValAssign::SExt:
3340 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3341 DAG.getValueType(VA.getValVT()));
3342 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3346 InVals.push_back(Val);
3353 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3354 bool isTailCall, bool isVarArg,
3356 SmallVector<std::pair<unsigned, SDValue>, 8>
3358 SDValue InFlag, SDValue Chain,
3360 int SPDiff, unsigned NumBytes,
3361 const SmallVectorImpl<ISD::InputArg> &Ins,
3362 SmallVectorImpl<SDValue> &InVals) const {
3363 std::vector<EVT> NodeTys;
3364 SmallVector<SDValue, 8> Ops;
3365 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3366 isTailCall, RegsToPass, Ops, NodeTys,
3369 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3370 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3371 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3373 // When performing tail call optimization the callee pops its arguments off
3374 // the stack. Account for this here so these bytes can be pushed back on in
3375 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3376 int BytesCalleePops =
3377 (CallConv == CallingConv::Fast &&
3378 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3380 // Add a register mask operand representing the call-preserved registers.
3381 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3382 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3383 assert(Mask && "Missing call preserved mask for calling convention");
3384 Ops.push_back(DAG.getRegisterMask(Mask));
3386 if (InFlag.getNode())
3387 Ops.push_back(InFlag);
3391 assert(((Callee.getOpcode() == ISD::Register &&
3392 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3393 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3394 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3395 isa<ConstantSDNode>(Callee)) &&
3396 "Expecting an global address, external symbol, absolute value or register");
3398 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3401 // Add a NOP immediately after the branch instruction when using the 64-bit
3402 // SVR4 ABI. At link time, if caller and callee are in a different module and
3403 // thus have a different TOC, the call will be replaced with a call to a stub
3404 // function which saves the current TOC, loads the TOC of the callee and
3405 // branches to the callee. The NOP will be replaced with a load instruction
3406 // which restores the TOC of the caller from the TOC save slot of the current
3407 // stack frame. If caller and callee belong to the same module (and have the
3408 // same TOC), the NOP will remain unchanged.
3410 bool needsTOCRestore = false;
3411 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3412 if (CallOpc == PPCISD::BCTRL) {
3413 // This is a call through a function pointer.
3414 // Restore the caller TOC from the save area into R2.
3415 // See PrepareCall() for more information about calls through function
3416 // pointers in the 64-bit SVR4 ABI.
3417 // We are using a target-specific load with r2 hard coded, because the
3418 // result of a target-independent load would never go directly into r2,
3419 // since r2 is a reserved register (which prevents the register allocator
3420 // from allocating it), resulting in an additional register being
3421 // allocated and an unnecessary move instruction being generated.
3422 needsTOCRestore = true;
3423 } else if ((CallOpc == PPCISD::CALL) && !isLocalCall(Callee)) {
3424 // Otherwise insert NOP for non-local calls.
3425 CallOpc = PPCISD::CALL_NOP;
3429 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
3430 InFlag = Chain.getValue(1);
3432 if (needsTOCRestore) {
3433 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3434 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3435 InFlag = Chain.getValue(1);
3438 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3439 DAG.getIntPtrConstant(BytesCalleePops, true),
3442 InFlag = Chain.getValue(1);
3444 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3445 Ins, dl, DAG, InVals);
3449 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3450 SmallVectorImpl<SDValue> &InVals) const {
3451 SelectionDAG &DAG = CLI.DAG;
3453 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
3454 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
3455 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
3456 SDValue Chain = CLI.Chain;
3457 SDValue Callee = CLI.Callee;
3458 bool &isTailCall = CLI.IsTailCall;
3459 CallingConv::ID CallConv = CLI.CallConv;
3460 bool isVarArg = CLI.IsVarArg;
3463 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3466 if (PPCSubTarget.isSVR4ABI()) {
3467 if (PPCSubTarget.isPPC64())
3468 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3469 isTailCall, Outs, OutVals, Ins,
3472 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3473 isTailCall, Outs, OutVals, Ins,
3477 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3478 isTailCall, Outs, OutVals, Ins,
3483 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3484 CallingConv::ID CallConv, bool isVarArg,
3486 const SmallVectorImpl<ISD::OutputArg> &Outs,
3487 const SmallVectorImpl<SDValue> &OutVals,
3488 const SmallVectorImpl<ISD::InputArg> &Ins,
3489 SDLoc dl, SelectionDAG &DAG,
3490 SmallVectorImpl<SDValue> &InVals) const {
3491 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3492 // of the 32-bit SVR4 ABI stack frame layout.
3494 assert((CallConv == CallingConv::C ||
3495 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3497 unsigned PtrByteSize = 4;
3499 MachineFunction &MF = DAG.getMachineFunction();
3501 // Mark this function as potentially containing a function that contains a
3502 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3503 // and restoring the callers stack pointer in this functions epilog. This is
3504 // done because by tail calling the called function might overwrite the value
3505 // in this function's (MF) stack pointer stack slot 0(SP).
3506 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3507 CallConv == CallingConv::Fast)
3508 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3510 // Count how many bytes are to be pushed on the stack, including the linkage
3511 // area, parameter list area and the part of the local variable space which
3512 // contains copies of aggregates which are passed by value.
3514 // Assign locations to all of the outgoing arguments.
3515 SmallVector<CCValAssign, 16> ArgLocs;
3516 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3517 getTargetMachine(), ArgLocs, *DAG.getContext());
3519 // Reserve space for the linkage area on the stack.
3520 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3523 // Handle fixed and variable vector arguments differently.
3524 // Fixed vector arguments go into registers as long as registers are
3525 // available. Variable vector arguments always go into memory.
3526 unsigned NumArgs = Outs.size();
3528 for (unsigned i = 0; i != NumArgs; ++i) {
3529 MVT ArgVT = Outs[i].VT;
3530 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3533 if (Outs[i].IsFixed) {
3534 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3537 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3543 errs() << "Call operand #" << i << " has unhandled type "
3544 << EVT(ArgVT).getEVTString() << "\n";
3546 llvm_unreachable(0);
3550 // All arguments are treated the same.
3551 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3554 // Assign locations to all of the outgoing aggregate by value arguments.
3555 SmallVector<CCValAssign, 16> ByValArgLocs;
3556 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3557 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3559 // Reserve stack space for the allocations in CCInfo.
3560 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3562 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3564 // Size of the linkage area, parameter list area and the part of the local
3565 // space variable where copies of aggregates which are passed by value are
3567 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3569 // Calculate by how many bytes the stack has to be adjusted in case of tail
3570 // call optimization.
3571 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3573 // Adjust the stack pointer for the new arguments...
3574 // These operations are automatically eliminated by the prolog/epilog pass
3575 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3577 SDValue CallSeqStart = Chain;
3579 // Load the return address and frame pointer so it can be moved somewhere else
3582 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3585 // Set up a copy of the stack pointer for use loading and storing any
3586 // arguments that may not fit in the registers available for argument
3588 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3590 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3591 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3592 SmallVector<SDValue, 8> MemOpChains;
3594 bool seenFloatArg = false;
3595 // Walk the register/memloc assignments, inserting copies/loads.
3596 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3599 CCValAssign &VA = ArgLocs[i];
3600 SDValue Arg = OutVals[i];
3601 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3603 if (Flags.isByVal()) {
3604 // Argument is an aggregate which is passed by value, thus we need to
3605 // create a copy of it in the local variable space of the current stack
3606 // frame (which is the stack frame of the caller) and pass the address of
3607 // this copy to the callee.
3608 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3609 CCValAssign &ByValVA = ByValArgLocs[j++];
3610 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3612 // Memory reserved in the local variable space of the callers stack frame.
3613 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3615 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3616 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3618 // Create a copy of the argument in the local area of the current
3620 SDValue MemcpyCall =
3621 CreateCopyOfByValArgument(Arg, PtrOff,
3622 CallSeqStart.getNode()->getOperand(0),
3625 // This must go outside the CALLSEQ_START..END.
3626 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3627 CallSeqStart.getNode()->getOperand(1),
3629 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3630 NewCallSeqStart.getNode());
3631 Chain = CallSeqStart = NewCallSeqStart;
3633 // Pass the address of the aggregate copy on the stack either in a
3634 // physical register or in the parameter list area of the current stack
3635 // frame to the callee.
3639 if (VA.isRegLoc()) {
3640 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3641 // Put argument in a physical register.
3642 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3644 // Put argument in the parameter list area of the current stack frame.
3645 assert(VA.isMemLoc());
3646 unsigned LocMemOffset = VA.getLocMemOffset();
3649 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3650 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3652 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3653 MachinePointerInfo(),
3656 // Calculate and remember argument location.
3657 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3663 if (!MemOpChains.empty())
3664 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3665 &MemOpChains[0], MemOpChains.size());
3667 // Build a sequence of copy-to-reg nodes chained together with token chain
3668 // and flag operands which copy the outgoing args into the appropriate regs.
3670 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3671 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3672 RegsToPass[i].second, InFlag);
3673 InFlag = Chain.getValue(1);
3676 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3679 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3680 SDValue Ops[] = { Chain, InFlag };
3682 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3683 dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
3685 InFlag = Chain.getValue(1);
3689 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3690 false, TailCallArguments);
3692 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3693 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3697 // Copy an argument into memory, being careful to do this outside the
3698 // call sequence for the call to which the argument belongs.
3700 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3701 SDValue CallSeqStart,
3702 ISD::ArgFlagsTy Flags,
3705 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3706 CallSeqStart.getNode()->getOperand(0),
3708 // The MEMCPY must go outside the CALLSEQ_START..END.
3709 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3710 CallSeqStart.getNode()->getOperand(1),
3712 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3713 NewCallSeqStart.getNode());
3714 return NewCallSeqStart;
3718 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3719 CallingConv::ID CallConv, bool isVarArg,
3721 const SmallVectorImpl<ISD::OutputArg> &Outs,
3722 const SmallVectorImpl<SDValue> &OutVals,
3723 const SmallVectorImpl<ISD::InputArg> &Ins,
3724 SDLoc dl, SelectionDAG &DAG,
3725 SmallVectorImpl<SDValue> &InVals) const {
3727 unsigned NumOps = Outs.size();
3729 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3730 unsigned PtrByteSize = 8;
3732 MachineFunction &MF = DAG.getMachineFunction();
3734 // Mark this function as potentially containing a function that contains a
3735 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3736 // and restoring the callers stack pointer in this functions epilog. This is
3737 // done because by tail calling the called function might overwrite the value
3738 // in this function's (MF) stack pointer stack slot 0(SP).
3739 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3740 CallConv == CallingConv::Fast)
3741 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3743 unsigned nAltivecParamsAtEnd = 0;
3745 // Count how many bytes are to be pushed on the stack, including the linkage
3746 // area, and parameter passing area. We start with at least 48 bytes, which
3747 // is reserved space for [SP][CR][LR][3 x unused].
3748 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
3751 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
3752 Outs, OutVals, nAltivecParamsAtEnd);
3754 // Calculate by how many bytes the stack has to be adjusted in case of tail
3755 // call optimization.
3756 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3758 // To protect arguments on the stack from being clobbered in a tail call,
3759 // force all the loads to happen before doing any other lowering.
3761 Chain = DAG.getStackArgumentTokenFactor(Chain);
3763 // Adjust the stack pointer for the new arguments...
3764 // These operations are automatically eliminated by the prolog/epilog pass
3765 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3767 SDValue CallSeqStart = Chain;
3769 // Load the return address and frame pointer so it can be move somewhere else
3772 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3775 // Set up a copy of the stack pointer for use loading and storing any
3776 // arguments that may not fit in the registers available for argument
3778 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3780 // Figure out which arguments are going to go in registers, and which in
3781 // memory. Also, if this is a vararg function, floating point operations
3782 // must be stored to our stack, and loaded into integer regs as well, if
3783 // any integer regs are available for argument passing.
3784 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
3785 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3787 static const uint16_t GPR[] = {
3788 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3789 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3791 static const uint16_t *FPR = GetFPR();
3793 static const uint16_t VR[] = {
3794 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3795 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3797 const unsigned NumGPRs = array_lengthof(GPR);
3798 const unsigned NumFPRs = 13;
3799 const unsigned NumVRs = array_lengthof(VR);
3801 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3802 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3804 SmallVector<SDValue, 8> MemOpChains;
3805 for (unsigned i = 0; i != NumOps; ++i) {
3806 SDValue Arg = OutVals[i];
3807 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3809 // PtrOff will be used to store the current argument to the stack if a
3810 // register cannot be found for it.
3813 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3815 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3817 // Promote integers to 64-bit values.
3818 if (Arg.getValueType() == MVT::i32) {
3819 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3820 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3821 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3824 // FIXME memcpy is used way more than necessary. Correctness first.
3825 // Note: "by value" is code for passing a structure by value, not
3827 if (Flags.isByVal()) {
3828 // Note: Size includes alignment padding, so
3829 // struct x { short a; char b; }
3830 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
3831 // These are the proper values we need for right-justifying the
3832 // aggregate in a parameter register.
3833 unsigned Size = Flags.getByValSize();
3835 // An empty aggregate parameter takes up no storage and no
3840 // All aggregates smaller than 8 bytes must be passed right-justified.
3841 if (Size==1 || Size==2 || Size==4) {
3842 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
3843 if (GPR_idx != NumGPRs) {
3844 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3845 MachinePointerInfo(), VT,
3847 MemOpChains.push_back(Load.getValue(1));
3848 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3850 ArgOffset += PtrByteSize;
3855 if (GPR_idx == NumGPRs && Size < 8) {
3856 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3857 PtrOff.getValueType());
3858 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3859 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3862 ArgOffset += PtrByteSize;
3865 // Copy entire object into memory. There are cases where gcc-generated
3866 // code assumes it is there, even if it could be put entirely into
3867 // registers. (This is not what the doc says.)
3869 // FIXME: The above statement is likely due to a misunderstanding of the
3870 // documents. All arguments must be copied into the parameter area BY
3871 // THE CALLEE in the event that the callee takes the address of any
3872 // formal argument. That has not yet been implemented. However, it is
3873 // reasonable to use the stack area as a staging area for the register
3876 // Skip this for small aggregates, as we will use the same slot for a
3877 // right-justified copy, below.
3879 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
3883 // When a register is available, pass a small aggregate right-justified.
3884 if (Size < 8 && GPR_idx != NumGPRs) {
3885 // The easiest way to get this right-justified in a register
3886 // is to copy the structure into the rightmost portion of a
3887 // local variable slot, then load the whole slot into the
3889 // FIXME: The memcpy seems to produce pretty awful code for
3890 // small aggregates, particularly for packed ones.
3891 // FIXME: It would be preferable to use the slot in the
3892 // parameter save area instead of a new local variable.
3893 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
3894 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3895 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3899 // Load the slot into the register.
3900 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
3901 MachinePointerInfo(),
3902 false, false, false, 0);
3903 MemOpChains.push_back(Load.getValue(1));
3904 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3906 // Done with this argument.
3907 ArgOffset += PtrByteSize;
3911 // For aggregates larger than PtrByteSize, copy the pieces of the
3912 // object that fit into registers from the parameter save area.
3913 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3914 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3915 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3916 if (GPR_idx != NumGPRs) {
3917 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3918 MachinePointerInfo(),
3919 false, false, false, 0);
3920 MemOpChains.push_back(Load.getValue(1));
3921 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3922 ArgOffset += PtrByteSize;
3924 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3931 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3932 default: llvm_unreachable("Unexpected ValueType for argument!");
3935 if (GPR_idx != NumGPRs) {
3936 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3938 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3939 true, isTailCall, false, MemOpChains,
3940 TailCallArguments, dl);
3942 ArgOffset += PtrByteSize;
3946 if (FPR_idx != NumFPRs) {
3947 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3950 // A single float or an aggregate containing only a single float
3951 // must be passed right-justified in the stack doubleword, and
3952 // in the GPR, if one is available.
3954 if (Arg.getValueType().getSimpleVT().SimpleTy == MVT::f32) {
3955 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3956 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3960 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
3961 MachinePointerInfo(), false, false, 0);
3962 MemOpChains.push_back(Store);
3964 // Float varargs are always shadowed in available integer registers
3965 if (GPR_idx != NumGPRs) {
3966 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3967 MachinePointerInfo(), false, false,
3969 MemOpChains.push_back(Load.getValue(1));
3970 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3972 } else if (GPR_idx != NumGPRs)
3973 // If we have any FPRs remaining, we may also have GPRs remaining.
3976 // Single-precision floating-point values are mapped to the
3977 // second (rightmost) word of the stack doubleword.
3978 if (Arg.getValueType() == MVT::f32) {
3979 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3980 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3983 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3984 true, isTailCall, false, MemOpChains,
3985 TailCallArguments, dl);
3994 // These go aligned on the stack, or in the corresponding R registers
3995 // when within range. The Darwin PPC ABI doc claims they also go in
3996 // V registers; in fact gcc does this only for arguments that are
3997 // prototyped, not for those that match the ... We do it for all
3998 // arguments, seems to work.
3999 while (ArgOffset % 16 !=0) {
4000 ArgOffset += PtrByteSize;
4001 if (GPR_idx != NumGPRs)
4004 // We could elide this store in the case where the object fits
4005 // entirely in R registers. Maybe later.
4006 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4007 DAG.getConstant(ArgOffset, PtrVT));
4008 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4009 MachinePointerInfo(), false, false, 0);
4010 MemOpChains.push_back(Store);
4011 if (VR_idx != NumVRs) {
4012 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4013 MachinePointerInfo(),
4014 false, false, false, 0);
4015 MemOpChains.push_back(Load.getValue(1));
4016 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4019 for (unsigned i=0; i<16; i+=PtrByteSize) {
4020 if (GPR_idx == NumGPRs)
4022 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4023 DAG.getConstant(i, PtrVT));
4024 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4025 false, false, false, 0);
4026 MemOpChains.push_back(Load.getValue(1));
4027 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4032 // Non-varargs Altivec params generally go in registers, but have
4033 // stack space allocated at the end.
4034 if (VR_idx != NumVRs) {
4035 // Doesn't have GPR space allocated.
4036 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4038 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4039 true, isTailCall, true, MemOpChains,
4040 TailCallArguments, dl);
4047 if (!MemOpChains.empty())
4048 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4049 &MemOpChains[0], MemOpChains.size());
4051 // Check if this is an indirect call (MTCTR/BCTRL).
4052 // See PrepareCall() for more information about calls through function
4053 // pointers in the 64-bit SVR4 ABI.
4055 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4056 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4057 !isBLACompatibleAddress(Callee, DAG)) {
4058 // Load r2 into a virtual register and store it to the TOC save area.
4059 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4060 // TOC save area offset.
4061 SDValue PtrOff = DAG.getIntPtrConstant(40);
4062 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4063 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4065 // R12 must contain the address of an indirect callee. This does not
4066 // mean the MTCTR instruction must use R12; it's easier to model this
4067 // as an extra parameter, so do that.
4068 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4071 // Build a sequence of copy-to-reg nodes chained together with token chain
4072 // and flag operands which copy the outgoing args into the appropriate regs.
4074 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4075 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4076 RegsToPass[i].second, InFlag);
4077 InFlag = Chain.getValue(1);
4081 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4082 FPOp, true, TailCallArguments);
4084 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4085 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4090 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4091 CallingConv::ID CallConv, bool isVarArg,
4093 const SmallVectorImpl<ISD::OutputArg> &Outs,
4094 const SmallVectorImpl<SDValue> &OutVals,
4095 const SmallVectorImpl<ISD::InputArg> &Ins,
4096 SDLoc dl, SelectionDAG &DAG,
4097 SmallVectorImpl<SDValue> &InVals) const {
4099 unsigned NumOps = Outs.size();
4101 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4102 bool isPPC64 = PtrVT == MVT::i64;
4103 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4105 MachineFunction &MF = DAG.getMachineFunction();
4107 // Mark this function as potentially containing a function that contains a
4108 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4109 // and restoring the callers stack pointer in this functions epilog. This is
4110 // done because by tail calling the called function might overwrite the value
4111 // in this function's (MF) stack pointer stack slot 0(SP).
4112 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4113 CallConv == CallingConv::Fast)
4114 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4116 unsigned nAltivecParamsAtEnd = 0;
4118 // Count how many bytes are to be pushed on the stack, including the linkage
4119 // area, and parameter passing area. We start with 24/48 bytes, which is
4120 // prereserved space for [SP][CR][LR][3 x unused].
4122 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4124 nAltivecParamsAtEnd);
4126 // Calculate by how many bytes the stack has to be adjusted in case of tail
4127 // call optimization.
4128 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4130 // To protect arguments on the stack from being clobbered in a tail call,
4131 // force all the loads to happen before doing any other lowering.
4133 Chain = DAG.getStackArgumentTokenFactor(Chain);
4135 // Adjust the stack pointer for the new arguments...
4136 // These operations are automatically eliminated by the prolog/epilog pass
4137 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4139 SDValue CallSeqStart = Chain;
4141 // Load the return address and frame pointer so it can be move somewhere else
4144 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4147 // Set up a copy of the stack pointer for use loading and storing any
4148 // arguments that may not fit in the registers available for argument
4152 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4154 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4156 // Figure out which arguments are going to go in registers, and which in
4157 // memory. Also, if this is a vararg function, floating point operations
4158 // must be stored to our stack, and loaded into integer regs as well, if
4159 // any integer regs are available for argument passing.
4160 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4161 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4163 static const uint16_t GPR_32[] = { // 32-bit registers.
4164 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4165 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4167 static const uint16_t GPR_64[] = { // 64-bit registers.
4168 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4169 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4171 static const uint16_t *FPR = GetFPR();
4173 static const uint16_t VR[] = {
4174 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4175 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4177 const unsigned NumGPRs = array_lengthof(GPR_32);
4178 const unsigned NumFPRs = 13;
4179 const unsigned NumVRs = array_lengthof(VR);
4181 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4183 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4184 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4186 SmallVector<SDValue, 8> MemOpChains;
4187 for (unsigned i = 0; i != NumOps; ++i) {
4188 SDValue Arg = OutVals[i];
4189 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4191 // PtrOff will be used to store the current argument to the stack if a
4192 // register cannot be found for it.
4195 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4197 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4199 // On PPC64, promote integers to 64-bit values.
4200 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4201 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4202 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4203 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4206 // FIXME memcpy is used way more than necessary. Correctness first.
4207 // Note: "by value" is code for passing a structure by value, not
4209 if (Flags.isByVal()) {
4210 unsigned Size = Flags.getByValSize();
4211 // Very small objects are passed right-justified. Everything else is
4212 // passed left-justified.
4213 if (Size==1 || Size==2) {
4214 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4215 if (GPR_idx != NumGPRs) {
4216 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4217 MachinePointerInfo(), VT,
4219 MemOpChains.push_back(Load.getValue(1));
4220 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4222 ArgOffset += PtrByteSize;
4224 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4225 PtrOff.getValueType());
4226 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4227 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4230 ArgOffset += PtrByteSize;
4234 // Copy entire object into memory. There are cases where gcc-generated
4235 // code assumes it is there, even if it could be put entirely into
4236 // registers. (This is not what the doc says.)
4237 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4241 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4242 // copy the pieces of the object that fit into registers from the
4243 // parameter save area.
4244 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4245 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4246 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4247 if (GPR_idx != NumGPRs) {
4248 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4249 MachinePointerInfo(),
4250 false, false, false, 0);
4251 MemOpChains.push_back(Load.getValue(1));
4252 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4253 ArgOffset += PtrByteSize;
4255 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4262 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
4263 default: llvm_unreachable("Unexpected ValueType for argument!");
4266 if (GPR_idx != NumGPRs) {
4267 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4269 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4270 isPPC64, isTailCall, false, MemOpChains,
4271 TailCallArguments, dl);
4273 ArgOffset += PtrByteSize;
4277 if (FPR_idx != NumFPRs) {
4278 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4281 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4282 MachinePointerInfo(), false, false, 0);
4283 MemOpChains.push_back(Store);
4285 // Float varargs are always shadowed in available integer registers
4286 if (GPR_idx != NumGPRs) {
4287 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4288 MachinePointerInfo(), false, false,
4290 MemOpChains.push_back(Load.getValue(1));
4291 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4293 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4294 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4295 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4296 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4297 MachinePointerInfo(),
4298 false, false, false, 0);
4299 MemOpChains.push_back(Load.getValue(1));
4300 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4303 // If we have any FPRs remaining, we may also have GPRs remaining.
4304 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4306 if (GPR_idx != NumGPRs)
4308 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4309 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4313 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4314 isPPC64, isTailCall, false, MemOpChains,
4315 TailCallArguments, dl);
4319 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4326 // These go aligned on the stack, or in the corresponding R registers
4327 // when within range. The Darwin PPC ABI doc claims they also go in
4328 // V registers; in fact gcc does this only for arguments that are
4329 // prototyped, not for those that match the ... We do it for all
4330 // arguments, seems to work.
4331 while (ArgOffset % 16 !=0) {
4332 ArgOffset += PtrByteSize;
4333 if (GPR_idx != NumGPRs)
4336 // We could elide this store in the case where the object fits
4337 // entirely in R registers. Maybe later.
4338 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4339 DAG.getConstant(ArgOffset, PtrVT));
4340 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4341 MachinePointerInfo(), false, false, 0);
4342 MemOpChains.push_back(Store);
4343 if (VR_idx != NumVRs) {
4344 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4345 MachinePointerInfo(),
4346 false, false, false, 0);
4347 MemOpChains.push_back(Load.getValue(1));
4348 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4351 for (unsigned i=0; i<16; i+=PtrByteSize) {
4352 if (GPR_idx == NumGPRs)
4354 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4355 DAG.getConstant(i, PtrVT));
4356 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4357 false, false, false, 0);
4358 MemOpChains.push_back(Load.getValue(1));
4359 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4364 // Non-varargs Altivec params generally go in registers, but have
4365 // stack space allocated at the end.
4366 if (VR_idx != NumVRs) {
4367 // Doesn't have GPR space allocated.
4368 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4369 } else if (nAltivecParamsAtEnd==0) {
4370 // We are emitting Altivec params in order.
4371 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4372 isPPC64, isTailCall, true, MemOpChains,
4373 TailCallArguments, dl);
4379 // If all Altivec parameters fit in registers, as they usually do,
4380 // they get stack space following the non-Altivec parameters. We
4381 // don't track this here because nobody below needs it.
4382 // If there are more Altivec parameters than fit in registers emit
4384 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4386 // Offset is aligned; skip 1st 12 params which go in V registers.
4387 ArgOffset = ((ArgOffset+15)/16)*16;
4389 for (unsigned i = 0; i != NumOps; ++i) {
4390 SDValue Arg = OutVals[i];
4391 EVT ArgType = Outs[i].VT;
4392 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4393 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4396 // We are emitting Altivec params in order.
4397 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4398 isPPC64, isTailCall, true, MemOpChains,
4399 TailCallArguments, dl);
4406 if (!MemOpChains.empty())
4407 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4408 &MemOpChains[0], MemOpChains.size());
4410 // On Darwin, R12 must contain the address of an indirect callee. This does
4411 // not mean the MTCTR instruction must use R12; it's easier to model this as
4412 // an extra parameter, so do that.
4414 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4415 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4416 !isBLACompatibleAddress(Callee, DAG))
4417 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4418 PPC::R12), Callee));
4420 // Build a sequence of copy-to-reg nodes chained together with token chain
4421 // and flag operands which copy the outgoing args into the appropriate regs.
4423 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4424 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4425 RegsToPass[i].second, InFlag);
4426 InFlag = Chain.getValue(1);
4430 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4431 FPOp, true, TailCallArguments);
4433 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4434 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4439 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4440 MachineFunction &MF, bool isVarArg,
4441 const SmallVectorImpl<ISD::OutputArg> &Outs,
4442 LLVMContext &Context) const {
4443 SmallVector<CCValAssign, 16> RVLocs;
4444 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4446 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4450 PPCTargetLowering::LowerReturn(SDValue Chain,
4451 CallingConv::ID CallConv, bool isVarArg,
4452 const SmallVectorImpl<ISD::OutputArg> &Outs,
4453 const SmallVectorImpl<SDValue> &OutVals,
4454 SDLoc dl, SelectionDAG &DAG) const {
4456 SmallVector<CCValAssign, 16> RVLocs;
4457 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4458 getTargetMachine(), RVLocs, *DAG.getContext());
4459 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4462 SmallVector<SDValue, 4> RetOps(1, Chain);
4464 // Copy the result values into the output registers.
4465 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4466 CCValAssign &VA = RVLocs[i];
4467 assert(VA.isRegLoc() && "Can only return in registers!");
4469 SDValue Arg = OutVals[i];
4471 switch (VA.getLocInfo()) {
4472 default: llvm_unreachable("Unknown loc info!");
4473 case CCValAssign::Full: break;
4474 case CCValAssign::AExt:
4475 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4477 case CCValAssign::ZExt:
4478 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4480 case CCValAssign::SExt:
4481 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4485 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4486 Flag = Chain.getValue(1);
4487 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4490 RetOps[0] = Chain; // Update chain.
4492 // Add the flag if we have it.
4494 RetOps.push_back(Flag);
4496 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4497 &RetOps[0], RetOps.size());
4500 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4501 const PPCSubtarget &Subtarget) const {
4502 // When we pop the dynamic allocation we need to restore the SP link.
4505 // Get the corect type for pointers.
4506 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4508 // Construct the stack pointer operand.
4509 bool isPPC64 = Subtarget.isPPC64();
4510 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4511 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4513 // Get the operands for the STACKRESTORE.
4514 SDValue Chain = Op.getOperand(0);
4515 SDValue SaveSP = Op.getOperand(1);
4517 // Load the old link SP.
4518 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4519 MachinePointerInfo(),
4520 false, false, false, 0);
4522 // Restore the stack pointer.
4523 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4525 // Store the old link SP.
4526 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4533 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4534 MachineFunction &MF = DAG.getMachineFunction();
4535 bool isPPC64 = PPCSubTarget.isPPC64();
4536 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4537 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4539 // Get current frame pointer save index. The users of this index will be
4540 // primarily DYNALLOC instructions.
4541 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4542 int RASI = FI->getReturnAddrSaveIndex();
4544 // If the frame pointer save index hasn't been defined yet.
4546 // Find out what the fix offset of the frame pointer save area.
4547 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4548 // Allocate the frame index for frame pointer save area.
4549 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4551 FI->setReturnAddrSaveIndex(RASI);
4553 return DAG.getFrameIndex(RASI, PtrVT);
4557 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4558 MachineFunction &MF = DAG.getMachineFunction();
4559 bool isPPC64 = PPCSubTarget.isPPC64();
4560 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4561 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4563 // Get current frame pointer save index. The users of this index will be
4564 // primarily DYNALLOC instructions.
4565 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4566 int FPSI = FI->getFramePointerSaveIndex();
4568 // If the frame pointer save index hasn't been defined yet.
4570 // Find out what the fix offset of the frame pointer save area.
4571 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4574 // Allocate the frame index for frame pointer save area.
4575 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4577 FI->setFramePointerSaveIndex(FPSI);
4579 return DAG.getFrameIndex(FPSI, PtrVT);
4582 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4584 const PPCSubtarget &Subtarget) const {
4586 SDValue Chain = Op.getOperand(0);
4587 SDValue Size = Op.getOperand(1);
4590 // Get the corect type for pointers.
4591 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4593 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4594 DAG.getConstant(0, PtrVT), Size);
4595 // Construct a node for the frame pointer save index.
4596 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4597 // Build a DYNALLOC node.
4598 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4599 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4600 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
4603 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4604 SelectionDAG &DAG) const {
4606 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4607 DAG.getVTList(MVT::i32, MVT::Other),
4608 Op.getOperand(0), Op.getOperand(1));
4611 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4612 SelectionDAG &DAG) const {
4614 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4615 Op.getOperand(0), Op.getOperand(1));
4618 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4620 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4621 // Not FP? Not a fsel.
4622 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4623 !Op.getOperand(2).getValueType().isFloatingPoint())
4626 // We might be able to do better than this under some circumstances, but in
4627 // general, fsel-based lowering of select is a finite-math-only optimization.
4628 // For more information, see section F.3 of the 2.06 ISA specification.
4629 if (!DAG.getTarget().Options.NoInfsFPMath ||
4630 !DAG.getTarget().Options.NoNaNsFPMath)
4633 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4635 EVT ResVT = Op.getValueType();
4636 EVT CmpVT = Op.getOperand(0).getValueType();
4637 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4638 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4641 // If the RHS of the comparison is a 0.0, we don't need to do the
4642 // subtraction at all.
4644 if (isFloatingPointZero(RHS))
4646 default: break; // SETUO etc aren't handled by fsel.
4650 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4651 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4652 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4653 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4654 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4655 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4656 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
4659 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4662 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4663 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4664 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4667 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4670 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4671 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4672 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4673 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4678 default: break; // SETUO etc aren't handled by fsel.
4682 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4683 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4684 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4685 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4686 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4687 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4688 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4689 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
4692 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4693 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4694 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4695 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4698 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4699 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4700 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4701 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4704 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4705 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4706 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4707 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4710 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4711 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4712 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4713 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4718 // FIXME: Split this code up when LegalizeDAGTypes lands.
4719 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
4721 assert(Op.getOperand(0).getValueType().isFloatingPoint());
4722 SDValue Src = Op.getOperand(0);
4724 // If we have a long double here, it must be that we have an undef of
4725 // that type. In this case return an undef of the target type.
4726 if (Src.getValueType() == MVT::ppcf128) {
4727 assert(Src.getOpcode() == ISD::UNDEF && "Unhandled ppcf128!");
4728 return DAG.getNode(ISD::UNDEF, dl,
4729 Op.getValueType().getSimpleVT().SimpleTy);
4732 if (Src.getValueType() == MVT::f32)
4733 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4736 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4737 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
4739 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4740 (PPCSubTarget.hasFPCVT() ? PPCISD::FCTIWUZ :
4745 assert((Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT()) &&
4746 "i64 FP_TO_UINT is supported only with FPCVT");
4747 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
4753 // Convert the FP value to an int value through memory.
4754 bool i32Stack = Op.getValueType() == MVT::i32 && PPCSubTarget.hasSTFIWX() &&
4755 (Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT());
4756 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
4757 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
4758 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
4760 // Emit a store to the stack slot.
4763 MachineFunction &MF = DAG.getMachineFunction();
4764 MachineMemOperand *MMO =
4765 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
4766 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
4767 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
4768 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
4771 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
4772 MPI, false, false, 0);
4774 // Result is a load from the stack slot. If loading 4 bytes, make sure to
4776 if (Op.getValueType() == MVT::i32 && !i32Stack) {
4777 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
4778 DAG.getConstant(4, FIPtr.getValueType()));
4779 MPI = MachinePointerInfo();
4782 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
4783 false, false, false, 0);
4786 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
4787 SelectionDAG &DAG) const {
4789 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
4790 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4793 assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) &&
4794 "UINT_TO_FP is supported only with FPCVT");
4796 // If we have FCFIDS, then use it when converting to single-precision.
4797 // Otherwise, convert to double-precision and then round.
4798 unsigned FCFOp = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4799 (Op.getOpcode() == ISD::UINT_TO_FP ?
4800 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
4801 (Op.getOpcode() == ISD::UINT_TO_FP ?
4802 PPCISD::FCFIDU : PPCISD::FCFID);
4803 MVT FCFTy = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4804 MVT::f32 : MVT::f64;
4806 if (Op.getOperand(0).getValueType() == MVT::i64) {
4807 SDValue SINT = Op.getOperand(0);
4808 // When converting to single-precision, we actually need to convert
4809 // to double-precision first and then round to single-precision.
4810 // To avoid double-rounding effects during that operation, we have
4811 // to prepare the input operand. Bits that might be truncated when
4812 // converting to double-precision are replaced by a bit that won't
4813 // be lost at this stage, but is below the single-precision rounding
4816 // However, if -enable-unsafe-fp-math is in effect, accept double
4817 // rounding to avoid the extra overhead.
4818 if (Op.getValueType() == MVT::f32 &&
4819 !PPCSubTarget.hasFPCVT() &&
4820 !DAG.getTarget().Options.UnsafeFPMath) {
4822 // Twiddle input to make sure the low 11 bits are zero. (If this
4823 // is the case, we are guaranteed the value will fit into the 53 bit
4824 // mantissa of an IEEE double-precision value without rounding.)
4825 // If any of those low 11 bits were not zero originally, make sure
4826 // bit 12 (value 2048) is set instead, so that the final rounding
4827 // to single-precision gets the correct result.
4828 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4829 SINT, DAG.getConstant(2047, MVT::i64));
4830 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4831 Round, DAG.getConstant(2047, MVT::i64));
4832 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4833 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4834 Round, DAG.getConstant(-2048, MVT::i64));
4836 // However, we cannot use that value unconditionally: if the magnitude
4837 // of the input value is small, the bit-twiddling we did above might
4838 // end up visibly changing the output. Fortunately, in that case, we
4839 // don't need to twiddle bits since the original input will convert
4840 // exactly to double-precision floating-point already. Therefore,
4841 // construct a conditional to use the original value if the top 11
4842 // bits are all sign-bit copies, and use the rounded value computed
4844 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4845 SINT, DAG.getConstant(53, MVT::i32));
4846 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4847 Cond, DAG.getConstant(1, MVT::i64));
4848 Cond = DAG.getSetCC(dl, MVT::i32,
4849 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4851 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4854 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4855 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
4857 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4858 FP = DAG.getNode(ISD::FP_ROUND, dl,
4859 MVT::f32, FP, DAG.getIntPtrConstant(0));
4863 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
4864 "Unhandled INT_TO_FP type in custom expander!");
4865 // Since we only generate this in 64-bit mode, we can take advantage of
4866 // 64-bit registers. In particular, sign extend the input value into the
4867 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
4868 // then lfd it and fcfid it.
4869 MachineFunction &MF = DAG.getMachineFunction();
4870 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
4871 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4874 if (PPCSubTarget.hasLFIWAX() || PPCSubTarget.hasFPCVT()) {
4875 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
4876 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4878 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
4879 MachinePointerInfo::getFixedStack(FrameIdx),
4882 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
4883 "Expected an i32 store");
4884 MachineMemOperand *MMO =
4885 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
4886 MachineMemOperand::MOLoad, 4, 4);
4887 SDValue Ops[] = { Store, FIdx };
4888 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
4889 PPCISD::LFIWZX : PPCISD::LFIWAX,
4890 dl, DAG.getVTList(MVT::f64, MVT::Other),
4891 Ops, 2, MVT::i32, MMO);
4893 assert(PPCSubTarget.isPPC64() &&
4894 "i32->FP without LFIWAX supported only on PPC64");
4896 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
4897 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4899 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
4902 // STD the extended value into the stack slot.
4903 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
4904 MachinePointerInfo::getFixedStack(FrameIdx),
4907 // Load the value as a double.
4908 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
4909 MachinePointerInfo::getFixedStack(FrameIdx),
4910 false, false, false, 0);
4913 // FCFID it and return it.
4914 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
4915 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4916 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
4920 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4921 SelectionDAG &DAG) const {
4924 The rounding mode is in bits 30:31 of FPSR, and has the following
4931 FLT_ROUNDS, on the other hand, expects the following:
4938 To perform the conversion, we do:
4939 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
4942 MachineFunction &MF = DAG.getMachineFunction();
4943 EVT VT = Op.getValueType();
4944 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4945 SDValue MFFSreg, InFlag;
4947 // Save FP Control Word to register
4949 MVT::f64, // return register
4950 MVT::Glue // unused in this context
4952 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4954 // Save FP register to stack slot
4955 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
4956 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
4957 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
4958 StackSlot, MachinePointerInfo(), false, false,0);
4960 // Load FP Control Word from low 32 bits of stack slot.
4961 SDValue Four = DAG.getConstant(4, PtrVT);
4962 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
4963 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
4964 false, false, false, 0);
4966 // Transform as necessary
4968 DAG.getNode(ISD::AND, dl, MVT::i32,
4969 CWD, DAG.getConstant(3, MVT::i32));
4971 DAG.getNode(ISD::SRL, dl, MVT::i32,
4972 DAG.getNode(ISD::AND, dl, MVT::i32,
4973 DAG.getNode(ISD::XOR, dl, MVT::i32,
4974 CWD, DAG.getConstant(3, MVT::i32)),
4975 DAG.getConstant(3, MVT::i32)),
4976 DAG.getConstant(1, MVT::i32));
4979 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
4981 return DAG.getNode((VT.getSizeInBits() < 16 ?
4982 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
4985 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
4986 EVT VT = Op.getValueType();
4987 unsigned BitWidth = VT.getSizeInBits();
4989 assert(Op.getNumOperands() == 3 &&
4990 VT == Op.getOperand(1).getValueType() &&
4993 // Expand into a bunch of logical ops. Note that these ops
4994 // depend on the PPC behavior for oversized shift amounts.
4995 SDValue Lo = Op.getOperand(0);
4996 SDValue Hi = Op.getOperand(1);
4997 SDValue Amt = Op.getOperand(2);
4998 EVT AmtVT = Amt.getValueType();
5000 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5001 DAG.getConstant(BitWidth, AmtVT), Amt);
5002 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5003 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5004 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5005 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5006 DAG.getConstant(-BitWidth, AmtVT));
5007 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5008 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5009 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5010 SDValue OutOps[] = { OutLo, OutHi };
5011 return DAG.getMergeValues(OutOps, 2, dl);
5014 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5015 EVT VT = Op.getValueType();
5017 unsigned BitWidth = VT.getSizeInBits();
5018 assert(Op.getNumOperands() == 3 &&
5019 VT == Op.getOperand(1).getValueType() &&
5022 // Expand into a bunch of logical ops. Note that these ops
5023 // depend on the PPC behavior for oversized shift amounts.
5024 SDValue Lo = Op.getOperand(0);
5025 SDValue Hi = Op.getOperand(1);
5026 SDValue Amt = Op.getOperand(2);
5027 EVT AmtVT = Amt.getValueType();
5029 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5030 DAG.getConstant(BitWidth, AmtVT), Amt);
5031 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5032 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5033 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5034 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5035 DAG.getConstant(-BitWidth, AmtVT));
5036 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5037 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5038 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5039 SDValue OutOps[] = { OutLo, OutHi };
5040 return DAG.getMergeValues(OutOps, 2, dl);
5043 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5045 EVT VT = Op.getValueType();
5046 unsigned BitWidth = VT.getSizeInBits();
5047 assert(Op.getNumOperands() == 3 &&
5048 VT == Op.getOperand(1).getValueType() &&
5051 // Expand into a bunch of logical ops, followed by a select_cc.
5052 SDValue Lo = Op.getOperand(0);
5053 SDValue Hi = Op.getOperand(1);
5054 SDValue Amt = Op.getOperand(2);
5055 EVT AmtVT = Amt.getValueType();
5057 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5058 DAG.getConstant(BitWidth, AmtVT), Amt);
5059 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5060 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5061 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5062 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5063 DAG.getConstant(-BitWidth, AmtVT));
5064 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5065 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5066 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5067 Tmp4, Tmp6, ISD::SETLE);
5068 SDValue OutOps[] = { OutLo, OutHi };
5069 return DAG.getMergeValues(OutOps, 2, dl);
5072 //===----------------------------------------------------------------------===//
5073 // Vector related lowering.
5076 /// BuildSplatI - Build a canonical splati of Val with an element size of
5077 /// SplatSize. Cast the result to VT.
5078 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5079 SelectionDAG &DAG, SDLoc dl) {
5080 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5082 static const EVT VTys[] = { // canonical VT to use for each size.
5083 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5086 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5088 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5092 EVT CanonicalVT = VTys[SplatSize-1];
5094 // Build a canonical splat for this value.
5095 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5096 SmallVector<SDValue, 8> Ops;
5097 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5098 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
5099 &Ops[0], Ops.size());
5100 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5103 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5104 /// specified intrinsic ID.
5105 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5106 SelectionDAG &DAG, SDLoc dl,
5107 EVT DestVT = MVT::Other) {
5108 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5109 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5110 DAG.getConstant(IID, MVT::i32), Op);
5113 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5114 /// specified intrinsic ID.
5115 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5116 SelectionDAG &DAG, SDLoc dl,
5117 EVT DestVT = MVT::Other) {
5118 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5119 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5120 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5123 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5124 /// specified intrinsic ID.
5125 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5126 SDValue Op2, SelectionDAG &DAG,
5127 SDLoc dl, EVT DestVT = MVT::Other) {
5128 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5129 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5130 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5134 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5135 /// amount. The result has the specified value type.
5136 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5137 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5138 // Force LHS/RHS to be the right type.
5139 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5140 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5143 for (unsigned i = 0; i != 16; ++i)
5145 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5146 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5149 // If this is a case we can't handle, return null and let the default
5150 // expansion code take care of it. If we CAN select this case, and if it
5151 // selects to a single instruction, return Op. Otherwise, if we can codegen
5152 // this case more efficiently than a constant pool load, lower it to the
5153 // sequence of ops that should be used.
5154 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5155 SelectionDAG &DAG) const {
5157 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5158 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5160 // Check if this is a splat of a constant value.
5161 APInt APSplatBits, APSplatUndef;
5162 unsigned SplatBitSize;
5164 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5165 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5168 unsigned SplatBits = APSplatBits.getZExtValue();
5169 unsigned SplatUndef = APSplatUndef.getZExtValue();
5170 unsigned SplatSize = SplatBitSize / 8;
5172 // First, handle single instruction cases.
5175 if (SplatBits == 0) {
5176 // Canonicalize all zero vectors to be v4i32.
5177 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5178 SDValue Z = DAG.getConstant(0, MVT::i32);
5179 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5180 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5185 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5186 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5188 if (SextVal >= -16 && SextVal <= 15)
5189 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5192 // Two instruction sequences.
5194 // If this value is in the range [-32,30] and is even, use:
5195 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5196 // If this value is in the range [17,31] and is odd, use:
5197 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5198 // If this value is in the range [-31,-17] and is odd, use:
5199 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5200 // Note the last two are three-instruction sequences.
5201 if (SextVal >= -32 && SextVal <= 31) {
5202 // To avoid having these optimizations undone by constant folding,
5203 // we convert to a pseudo that will be expanded later into one of
5205 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5206 EVT VT = Op.getValueType();
5207 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5208 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5209 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5212 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5213 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5215 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5216 // Make -1 and vspltisw -1:
5217 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5219 // Make the VSLW intrinsic, computing 0x8000_0000.
5220 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5223 // xor by OnesV to invert it.
5224 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5225 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5228 // Check to see if this is a wide variety of vsplti*, binop self cases.
5229 static const signed char SplatCsts[] = {
5230 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5231 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5234 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5235 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5236 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5237 int i = SplatCsts[idx];
5239 // Figure out what shift amount will be used by altivec if shifted by i in
5241 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5243 // vsplti + shl self.
5244 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5245 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5246 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5247 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5248 Intrinsic::ppc_altivec_vslw
5250 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5251 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5254 // vsplti + srl self.
5255 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5256 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5257 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5258 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5259 Intrinsic::ppc_altivec_vsrw
5261 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5262 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5265 // vsplti + sra self.
5266 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5267 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5268 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5269 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5270 Intrinsic::ppc_altivec_vsraw
5272 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5273 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5276 // vsplti + rol self.
5277 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5278 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5279 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5280 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5281 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5282 Intrinsic::ppc_altivec_vrlw
5284 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5285 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5288 // t = vsplti c, result = vsldoi t, t, 1
5289 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5290 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5291 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5293 // t = vsplti c, result = vsldoi t, t, 2
5294 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5295 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5296 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5298 // t = vsplti c, result = vsldoi t, t, 3
5299 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5300 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5301 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5308 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5309 /// the specified operations to build the shuffle.
5310 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5311 SDValue RHS, SelectionDAG &DAG,
5313 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5314 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5315 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5318 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5330 if (OpNum == OP_COPY) {
5331 if (LHSID == (1*9+2)*9+3) return LHS;
5332 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5336 SDValue OpLHS, OpRHS;
5337 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5338 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5342 default: llvm_unreachable("Unknown i32 permute!");
5344 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5345 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5346 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5347 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5350 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5351 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5352 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5353 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5356 for (unsigned i = 0; i != 16; ++i)
5357 ShufIdxs[i] = (i&3)+0;
5360 for (unsigned i = 0; i != 16; ++i)
5361 ShufIdxs[i] = (i&3)+4;
5364 for (unsigned i = 0; i != 16; ++i)
5365 ShufIdxs[i] = (i&3)+8;
5368 for (unsigned i = 0; i != 16; ++i)
5369 ShufIdxs[i] = (i&3)+12;
5372 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5374 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5376 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5378 EVT VT = OpLHS.getValueType();
5379 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5380 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5381 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5382 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5385 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5386 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5387 /// return the code it can be lowered into. Worst case, it can always be
5388 /// lowered into a vperm.
5389 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5390 SelectionDAG &DAG) const {
5392 SDValue V1 = Op.getOperand(0);
5393 SDValue V2 = Op.getOperand(1);
5394 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5395 EVT VT = Op.getValueType();
5397 // Cases that are handled by instructions that take permute immediates
5398 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5399 // selected by the instruction selector.
5400 if (V2.getOpcode() == ISD::UNDEF) {
5401 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5402 PPC::isSplatShuffleMask(SVOp, 2) ||
5403 PPC::isSplatShuffleMask(SVOp, 4) ||
5404 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5405 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5406 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5407 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5408 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5409 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5410 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5411 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5412 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5417 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5418 // and produce a fixed permutation. If any of these match, do not lower to
5420 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5421 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5422 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5423 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5424 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5425 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5426 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5427 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5428 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5431 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5432 // perfect shuffle table to emit an optimal matching sequence.
5433 ArrayRef<int> PermMask = SVOp->getMask();
5435 unsigned PFIndexes[4];
5436 bool isFourElementShuffle = true;
5437 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5438 unsigned EltNo = 8; // Start out undef.
5439 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5440 if (PermMask[i*4+j] < 0)
5441 continue; // Undef, ignore it.
5443 unsigned ByteSource = PermMask[i*4+j];
5444 if ((ByteSource & 3) != j) {
5445 isFourElementShuffle = false;
5450 EltNo = ByteSource/4;
5451 } else if (EltNo != ByteSource/4) {
5452 isFourElementShuffle = false;
5456 PFIndexes[i] = EltNo;
5459 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5460 // perfect shuffle vector to determine if it is cost effective to do this as
5461 // discrete instructions, or whether we should use a vperm.
5462 if (isFourElementShuffle) {
5463 // Compute the index in the perfect shuffle table.
5464 unsigned PFTableIndex =
5465 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5467 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5468 unsigned Cost = (PFEntry >> 30);
5470 // Determining when to avoid vperm is tricky. Many things affect the cost
5471 // of vperm, particularly how many times the perm mask needs to be computed.
5472 // For example, if the perm mask can be hoisted out of a loop or is already
5473 // used (perhaps because there are multiple permutes with the same shuffle
5474 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5475 // the loop requires an extra register.
5477 // As a compromise, we only emit discrete instructions if the shuffle can be
5478 // generated in 3 or fewer operations. When we have loop information
5479 // available, if this block is within a loop, we should avoid using vperm
5480 // for 3-operation perms and use a constant pool load instead.
5482 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5485 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5486 // vector that will get spilled to the constant pool.
5487 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5489 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5490 // that it is in input element units, not in bytes. Convert now.
5491 EVT EltVT = V1.getValueType().getVectorElementType();
5492 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5494 SmallVector<SDValue, 16> ResultMask;
5495 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5496 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5498 for (unsigned j = 0; j != BytesPerElement; ++j)
5499 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5503 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5504 &ResultMask[0], ResultMask.size());
5505 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5508 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5509 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5510 /// information about the intrinsic.
5511 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5513 unsigned IntrinsicID =
5514 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5517 switch (IntrinsicID) {
5518 default: return false;
5519 // Comparison predicates.
5520 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5521 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5522 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5523 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5524 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5525 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5526 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5527 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5528 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5529 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5530 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5531 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5532 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5534 // Normal Comparisons.
5535 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5536 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5537 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5538 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5539 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5540 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5541 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5542 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5543 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5544 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5545 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5546 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5547 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5552 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5553 /// lower, do it, otherwise return null.
5554 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5555 SelectionDAG &DAG) const {
5556 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5557 // opcode number of the comparison.
5561 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5562 return SDValue(); // Don't custom lower most intrinsics.
5564 // If this is a non-dot comparison, make the VCMP node and we are done.
5566 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5567 Op.getOperand(1), Op.getOperand(2),
5568 DAG.getConstant(CompareOpc, MVT::i32));
5569 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5572 // Create the PPCISD altivec 'dot' comparison node.
5574 Op.getOperand(2), // LHS
5575 Op.getOperand(3), // RHS
5576 DAG.getConstant(CompareOpc, MVT::i32)
5578 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5579 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5581 // Now that we have the comparison, emit a copy from the CR to a GPR.
5582 // This is flagged to the above dot comparison.
5583 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5584 DAG.getRegister(PPC::CR6, MVT::i32),
5585 CompNode.getValue(1));
5587 // Unpack the result based on how the target uses it.
5588 unsigned BitNo; // Bit # of CR6.
5589 bool InvertBit; // Invert result?
5590 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5591 default: // Can't happen, don't crash on invalid number though.
5592 case 0: // Return the value of the EQ bit of CR6.
5593 BitNo = 0; InvertBit = false;
5595 case 1: // Return the inverted value of the EQ bit of CR6.
5596 BitNo = 0; InvertBit = true;
5598 case 2: // Return the value of the LT bit of CR6.
5599 BitNo = 2; InvertBit = false;
5601 case 3: // Return the inverted value of the LT bit of CR6.
5602 BitNo = 2; InvertBit = true;
5606 // Shift the bit into the low position.
5607 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5608 DAG.getConstant(8-(3-BitNo), MVT::i32));
5610 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5611 DAG.getConstant(1, MVT::i32));
5613 // If we are supposed to, toggle the bit.
5615 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5616 DAG.getConstant(1, MVT::i32));
5620 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5621 SelectionDAG &DAG) const {
5623 // Create a stack slot that is 16-byte aligned.
5624 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5625 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5626 EVT PtrVT = getPointerTy();
5627 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5629 // Store the input value into Value#0 of the stack slot.
5630 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5631 Op.getOperand(0), FIdx, MachinePointerInfo(),
5634 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5635 false, false, false, 0);
5638 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5640 if (Op.getValueType() == MVT::v4i32) {
5641 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5643 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5644 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5646 SDValue RHSSwap = // = vrlw RHS, 16
5647 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
5649 // Shrinkify inputs to v8i16.
5650 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5651 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5652 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5654 // Low parts multiplied together, generating 32-bit results (we ignore the
5656 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
5657 LHS, RHS, DAG, dl, MVT::v4i32);
5659 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
5660 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5661 // Shift the high parts up 16 bits.
5662 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
5664 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5665 } else if (Op.getValueType() == MVT::v8i16) {
5666 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5668 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5670 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
5671 LHS, RHS, Zero, DAG, dl);
5672 } else if (Op.getValueType() == MVT::v16i8) {
5673 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5675 // Multiply the even 8-bit parts, producing 16-bit sums.
5676 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
5677 LHS, RHS, DAG, dl, MVT::v8i16);
5678 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5680 // Multiply the odd 8-bit parts, producing 16-bit sums.
5681 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
5682 LHS, RHS, DAG, dl, MVT::v8i16);
5683 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5685 // Merge the results together.
5687 for (unsigned i = 0; i != 8; ++i) {
5689 Ops[i*2+1] = 2*i+1+16;
5691 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5693 llvm_unreachable("Unknown mul to lower!");
5697 /// LowerOperation - Provide custom lowering hooks for some operations.
5699 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5700 switch (Op.getOpcode()) {
5701 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
5702 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5703 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5704 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5705 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5706 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5707 case ISD::SETCC: return LowerSETCC(Op, DAG);
5708 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
5709 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
5711 return LowerVASTART(Op, DAG, PPCSubTarget);
5714 return LowerVAARG(Op, DAG, PPCSubTarget);
5716 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
5717 case ISD::DYNAMIC_STACKALLOC:
5718 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
5720 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
5721 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
5723 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5724 case ISD::FP_TO_UINT:
5725 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
5727 case ISD::UINT_TO_FP:
5728 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
5729 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5731 // Lower 64-bit shifts.
5732 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
5733 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
5734 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
5736 // Vector-related lowering.
5737 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5738 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5739 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5740 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5741 case ISD::MUL: return LowerMUL(Op, DAG);
5743 // For counter-based loop handling.
5744 case ISD::INTRINSIC_W_CHAIN: return SDValue();
5746 // Frame & Return address.
5747 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5748 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5752 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
5753 SmallVectorImpl<SDValue>&Results,
5754 SelectionDAG &DAG) const {
5755 const TargetMachine &TM = getTargetMachine();
5757 switch (N->getOpcode()) {
5759 llvm_unreachable("Do not know how to custom type legalize this operation!");
5760 case ISD::INTRINSIC_W_CHAIN: {
5761 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
5762 Intrinsic::ppc_is_decremented_ctr_nonzero)
5765 assert(N->getValueType(0) == MVT::i1 &&
5766 "Unexpected result type for CTR decrement intrinsic");
5767 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
5768 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
5769 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
5772 Results.push_back(NewInt);
5773 Results.push_back(NewInt.getValue(1));
5777 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
5778 || TM.getSubtarget<PPCSubtarget>().isPPC64())
5781 EVT VT = N->getValueType(0);
5783 if (VT == MVT::i64) {
5784 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
5786 Results.push_back(NewNode);
5787 Results.push_back(NewNode.getValue(1));
5791 case ISD::FP_ROUND_INREG: {
5792 assert(N->getValueType(0) == MVT::ppcf128);
5793 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5794 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5795 MVT::f64, N->getOperand(0),
5796 DAG.getIntPtrConstant(0));
5797 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5798 MVT::f64, N->getOperand(0),
5799 DAG.getIntPtrConstant(1));
5801 // Add the two halves of the long double in round-to-zero mode.
5802 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
5804 // We know the low half is about to be thrown away, so just use something
5806 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5810 case ISD::FP_TO_SINT:
5811 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
5817 //===----------------------------------------------------------------------===//
5818 // Other Lowering Code
5819 //===----------------------------------------------------------------------===//
5822 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5823 bool is64bit, unsigned BinOpcode) const {
5824 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5825 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5827 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5828 MachineFunction *F = BB->getParent();
5829 MachineFunction::iterator It = BB;
5832 unsigned dest = MI->getOperand(0).getReg();
5833 unsigned ptrA = MI->getOperand(1).getReg();
5834 unsigned ptrB = MI->getOperand(2).getReg();
5835 unsigned incr = MI->getOperand(3).getReg();
5836 DebugLoc dl = MI->getDebugLoc();
5838 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5839 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5840 F->insert(It, loopMBB);
5841 F->insert(It, exitMBB);
5842 exitMBB->splice(exitMBB->begin(), BB,
5843 llvm::next(MachineBasicBlock::iterator(MI)),
5845 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5847 MachineRegisterInfo &RegInfo = F->getRegInfo();
5848 unsigned TmpReg = (!BinOpcode) ? incr :
5849 RegInfo.createVirtualRegister(
5850 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5851 (const TargetRegisterClass *) &PPC::GPRCRegClass);
5855 // fallthrough --> loopMBB
5856 BB->addSuccessor(loopMBB);
5859 // l[wd]arx dest, ptr
5860 // add r0, dest, incr
5861 // st[wd]cx. r0, ptr
5863 // fallthrough --> exitMBB
5865 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5866 .addReg(ptrA).addReg(ptrB);
5868 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
5869 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5870 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
5871 BuildMI(BB, dl, TII->get(PPC::BCC))
5872 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5873 BB->addSuccessor(loopMBB);
5874 BB->addSuccessor(exitMBB);
5883 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
5884 MachineBasicBlock *BB,
5885 bool is8bit, // operation
5886 unsigned BinOpcode) const {
5887 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5888 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5889 // In 64 bit mode we have to use 64 bits for addresses, even though the
5890 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
5891 // registers without caring whether they're 32 or 64, but here we're
5892 // doing actual arithmetic on the addresses.
5893 bool is64bit = PPCSubTarget.isPPC64();
5894 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
5896 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5897 MachineFunction *F = BB->getParent();
5898 MachineFunction::iterator It = BB;
5901 unsigned dest = MI->getOperand(0).getReg();
5902 unsigned ptrA = MI->getOperand(1).getReg();
5903 unsigned ptrB = MI->getOperand(2).getReg();
5904 unsigned incr = MI->getOperand(3).getReg();
5905 DebugLoc dl = MI->getDebugLoc();
5907 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5908 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5909 F->insert(It, loopMBB);
5910 F->insert(It, exitMBB);
5911 exitMBB->splice(exitMBB->begin(), BB,
5912 llvm::next(MachineBasicBlock::iterator(MI)),
5914 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5916 MachineRegisterInfo &RegInfo = F->getRegInfo();
5917 const TargetRegisterClass *RC =
5918 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5919 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5920 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5921 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5922 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5923 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
5924 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
5925 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
5926 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
5927 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
5928 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
5929 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
5930 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
5932 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
5936 // fallthrough --> loopMBB
5937 BB->addSuccessor(loopMBB);
5939 // The 4-byte load must be aligned, while a char or short may be
5940 // anywhere in the word. Hence all this nasty bookkeeping code.
5941 // add ptr1, ptrA, ptrB [copy if ptrA==0]
5942 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
5943 // xori shift, shift1, 24 [16]
5944 // rlwinm ptr, ptr1, 0, 0, 29
5945 // slw incr2, incr, shift
5946 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
5947 // slw mask, mask2, shift
5949 // lwarx tmpDest, ptr
5950 // add tmp, tmpDest, incr2
5951 // andc tmp2, tmpDest, mask
5952 // and tmp3, tmp, mask
5953 // or tmp4, tmp3, tmp2
5956 // fallthrough --> exitMBB
5957 // srw dest, tmpDest, shift
5958 if (ptrA != ZeroReg) {
5959 Ptr1Reg = RegInfo.createVirtualRegister(RC);
5960 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
5961 .addReg(ptrA).addReg(ptrB);
5965 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5966 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
5967 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5968 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
5970 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
5971 .addReg(Ptr1Reg).addImm(0).addImm(61);
5973 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
5974 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
5975 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
5976 .addReg(incr).addReg(ShiftReg);
5978 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
5980 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
5981 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
5983 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
5984 .addReg(Mask2Reg).addReg(ShiftReg);
5987 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
5988 .addReg(ZeroReg).addReg(PtrReg);
5990 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
5991 .addReg(Incr2Reg).addReg(TmpDestReg);
5992 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
5993 .addReg(TmpDestReg).addReg(MaskReg);
5994 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
5995 .addReg(TmpReg).addReg(MaskReg);
5996 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
5997 .addReg(Tmp3Reg).addReg(Tmp2Reg);
5998 BuildMI(BB, dl, TII->get(PPC::STWCX))
5999 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6000 BuildMI(BB, dl, TII->get(PPC::BCC))
6001 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6002 BB->addSuccessor(loopMBB);
6003 BB->addSuccessor(exitMBB);
6008 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6013 llvm::MachineBasicBlock*
6014 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6015 MachineBasicBlock *MBB) const {
6016 DebugLoc DL = MI->getDebugLoc();
6017 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6019 MachineFunction *MF = MBB->getParent();
6020 MachineRegisterInfo &MRI = MF->getRegInfo();
6022 const BasicBlock *BB = MBB->getBasicBlock();
6023 MachineFunction::iterator I = MBB;
6027 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6028 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6030 unsigned DstReg = MI->getOperand(0).getReg();
6031 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6032 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6033 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6034 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6036 MVT PVT = getPointerTy();
6037 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6038 "Invalid Pointer Size!");
6039 // For v = setjmp(buf), we generate
6042 // SjLjSetup mainMBB
6048 // buf[LabelOffset] = LR
6052 // v = phi(main, restore)
6055 MachineBasicBlock *thisMBB = MBB;
6056 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6057 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6058 MF->insert(I, mainMBB);
6059 MF->insert(I, sinkMBB);
6061 MachineInstrBuilder MIB;
6063 // Transfer the remainder of BB and its successor edges to sinkMBB.
6064 sinkMBB->splice(sinkMBB->begin(), MBB,
6065 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
6066 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6068 // Note that the structure of the jmp_buf used here is not compatible
6069 // with that used by libc, and is not designed to be. Specifically, it
6070 // stores only those 'reserved' registers that LLVM does not otherwise
6071 // understand how to spill. Also, by convention, by the time this
6072 // intrinsic is called, Clang has already stored the frame address in the
6073 // first slot of the buffer and stack address in the third. Following the
6074 // X86 target code, we'll store the jump address in the second slot. We also
6075 // need to save the TOC pointer (R2) to handle jumps between shared
6076 // libraries, and that will be stored in the fourth slot. The thread
6077 // identifier (R13) is not affected.
6080 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6081 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6083 // Prepare IP either in reg.
6084 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6085 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6086 unsigned BufReg = MI->getOperand(1).getReg();
6088 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) {
6089 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6094 MIB.setMemRefs(MMOBegin, MMOEnd);
6098 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6099 const PPCRegisterInfo *TRI =
6100 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6101 MIB.addRegMask(TRI->getNoPreservedMask());
6103 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6105 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6107 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6109 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6110 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6114 MIB = BuildMI(mainMBB, DL,
6115 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6118 if (PPCSubTarget.isPPC64()) {
6119 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6121 .addImm(LabelOffset)
6124 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6126 .addImm(LabelOffset)
6130 MIB.setMemRefs(MMOBegin, MMOEnd);
6132 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6133 mainMBB->addSuccessor(sinkMBB);
6136 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6137 TII->get(PPC::PHI), DstReg)
6138 .addReg(mainDstReg).addMBB(mainMBB)
6139 .addReg(restoreDstReg).addMBB(thisMBB);
6141 MI->eraseFromParent();
6146 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6147 MachineBasicBlock *MBB) const {
6148 DebugLoc DL = MI->getDebugLoc();
6149 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6151 MachineFunction *MF = MBB->getParent();
6152 MachineRegisterInfo &MRI = MF->getRegInfo();
6155 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6156 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6158 MVT PVT = getPointerTy();
6159 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6160 "Invalid Pointer Size!");
6162 const TargetRegisterClass *RC =
6163 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6164 unsigned Tmp = MRI.createVirtualRegister(RC);
6165 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6166 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6167 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6169 MachineInstrBuilder MIB;
6171 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6172 const int64_t SPOffset = 2 * PVT.getStoreSize();
6173 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6175 unsigned BufReg = MI->getOperand(0).getReg();
6177 // Reload FP (the jumped-to function may not have had a
6178 // frame pointer, and if so, then its r31 will be restored
6180 if (PVT == MVT::i64) {
6181 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6185 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6189 MIB.setMemRefs(MMOBegin, MMOEnd);
6192 if (PVT == MVT::i64) {
6193 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6194 .addImm(LabelOffset)
6197 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6198 .addImm(LabelOffset)
6201 MIB.setMemRefs(MMOBegin, MMOEnd);
6204 if (PVT == MVT::i64) {
6205 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6209 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6213 MIB.setMemRefs(MMOBegin, MMOEnd);
6215 // FIXME: When we also support base pointers, that register must also be
6219 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6220 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6224 MIB.setMemRefs(MMOBegin, MMOEnd);
6228 BuildMI(*MBB, MI, DL,
6229 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6230 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6232 MI->eraseFromParent();
6237 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6238 MachineBasicBlock *BB) const {
6239 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6240 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6241 return emitEHSjLjSetJmp(MI, BB);
6242 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6243 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6244 return emitEHSjLjLongJmp(MI, BB);
6247 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6249 // To "insert" these instructions we actually have to insert their
6250 // control-flow patterns.
6251 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6252 MachineFunction::iterator It = BB;
6255 MachineFunction *F = BB->getParent();
6257 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6258 MI->getOpcode() == PPC::SELECT_CC_I8)) {
6259 SmallVector<MachineOperand, 2> Cond;
6260 Cond.push_back(MI->getOperand(4));
6261 Cond.push_back(MI->getOperand(1));
6263 DebugLoc dl = MI->getDebugLoc();
6264 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6265 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6266 Cond, MI->getOperand(2).getReg(),
6267 MI->getOperand(3).getReg());
6268 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6269 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6270 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6271 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6272 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
6275 // The incoming instruction knows the destination vreg to set, the
6276 // condition code register to branch on, the true/false values to
6277 // select between, and a branch opcode to use.
6282 // cmpTY ccX, r1, r2
6284 // fallthrough --> copy0MBB
6285 MachineBasicBlock *thisMBB = BB;
6286 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6287 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6288 unsigned SelectPred = MI->getOperand(4).getImm();
6289 DebugLoc dl = MI->getDebugLoc();
6290 F->insert(It, copy0MBB);
6291 F->insert(It, sinkMBB);
6293 // Transfer the remainder of BB and its successor edges to sinkMBB.
6294 sinkMBB->splice(sinkMBB->begin(), BB,
6295 llvm::next(MachineBasicBlock::iterator(MI)),
6297 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6299 // Next, add the true and fallthrough blocks as its successors.
6300 BB->addSuccessor(copy0MBB);
6301 BB->addSuccessor(sinkMBB);
6303 BuildMI(BB, dl, TII->get(PPC::BCC))
6304 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6307 // %FalseValue = ...
6308 // # fallthrough to sinkMBB
6311 // Update machine-CFG edges
6312 BB->addSuccessor(sinkMBB);
6315 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6318 BuildMI(*BB, BB->begin(), dl,
6319 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6320 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6321 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6323 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6324 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6325 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6326 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6327 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6328 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6329 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6330 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6332 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6333 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6334 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6335 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6336 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6337 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6338 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6339 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6341 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6342 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6343 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6344 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6345 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6346 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6347 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6348 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6350 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6351 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6352 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6353 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6354 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6355 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6356 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6357 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6359 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6360 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6361 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6362 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6363 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6364 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6365 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6366 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6368 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6369 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6370 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6371 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6372 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6373 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6374 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6375 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6377 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6378 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6379 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6380 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6381 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6382 BB = EmitAtomicBinary(MI, BB, false, 0);
6383 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6384 BB = EmitAtomicBinary(MI, BB, true, 0);
6386 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6387 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6388 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6390 unsigned dest = MI->getOperand(0).getReg();
6391 unsigned ptrA = MI->getOperand(1).getReg();
6392 unsigned ptrB = MI->getOperand(2).getReg();
6393 unsigned oldval = MI->getOperand(3).getReg();
6394 unsigned newval = MI->getOperand(4).getReg();
6395 DebugLoc dl = MI->getDebugLoc();
6397 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6398 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6399 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6400 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6401 F->insert(It, loop1MBB);
6402 F->insert(It, loop2MBB);
6403 F->insert(It, midMBB);
6404 F->insert(It, exitMBB);
6405 exitMBB->splice(exitMBB->begin(), BB,
6406 llvm::next(MachineBasicBlock::iterator(MI)),
6408 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6412 // fallthrough --> loopMBB
6413 BB->addSuccessor(loop1MBB);
6416 // l[wd]arx dest, ptr
6417 // cmp[wd] dest, oldval
6420 // st[wd]cx. newval, ptr
6424 // st[wd]cx. dest, ptr
6427 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6428 .addReg(ptrA).addReg(ptrB);
6429 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6430 .addReg(oldval).addReg(dest);
6431 BuildMI(BB, dl, TII->get(PPC::BCC))
6432 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6433 BB->addSuccessor(loop2MBB);
6434 BB->addSuccessor(midMBB);
6437 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6438 .addReg(newval).addReg(ptrA).addReg(ptrB);
6439 BuildMI(BB, dl, TII->get(PPC::BCC))
6440 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6441 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6442 BB->addSuccessor(loop1MBB);
6443 BB->addSuccessor(exitMBB);
6446 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6447 .addReg(dest).addReg(ptrA).addReg(ptrB);
6448 BB->addSuccessor(exitMBB);
6453 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6454 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6455 // We must use 64-bit registers for addresses when targeting 64-bit,
6456 // since we're actually doing arithmetic on them. Other registers
6458 bool is64bit = PPCSubTarget.isPPC64();
6459 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6461 unsigned dest = MI->getOperand(0).getReg();
6462 unsigned ptrA = MI->getOperand(1).getReg();
6463 unsigned ptrB = MI->getOperand(2).getReg();
6464 unsigned oldval = MI->getOperand(3).getReg();
6465 unsigned newval = MI->getOperand(4).getReg();
6466 DebugLoc dl = MI->getDebugLoc();
6468 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6469 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6470 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6471 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6472 F->insert(It, loop1MBB);
6473 F->insert(It, loop2MBB);
6474 F->insert(It, midMBB);
6475 F->insert(It, exitMBB);
6476 exitMBB->splice(exitMBB->begin(), BB,
6477 llvm::next(MachineBasicBlock::iterator(MI)),
6479 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6481 MachineRegisterInfo &RegInfo = F->getRegInfo();
6482 const TargetRegisterClass *RC =
6483 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6484 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6485 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6486 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6487 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6488 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6489 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6490 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6491 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6492 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6493 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6494 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6495 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6496 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6497 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6499 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6500 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6503 // fallthrough --> loopMBB
6504 BB->addSuccessor(loop1MBB);
6506 // The 4-byte load must be aligned, while a char or short may be
6507 // anywhere in the word. Hence all this nasty bookkeeping code.
6508 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6509 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6510 // xori shift, shift1, 24 [16]
6511 // rlwinm ptr, ptr1, 0, 0, 29
6512 // slw newval2, newval, shift
6513 // slw oldval2, oldval,shift
6514 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6515 // slw mask, mask2, shift
6516 // and newval3, newval2, mask
6517 // and oldval3, oldval2, mask
6519 // lwarx tmpDest, ptr
6520 // and tmp, tmpDest, mask
6521 // cmpw tmp, oldval3
6524 // andc tmp2, tmpDest, mask
6525 // or tmp4, tmp2, newval3
6530 // stwcx. tmpDest, ptr
6532 // srw dest, tmpDest, shift
6533 if (ptrA != ZeroReg) {
6534 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6535 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6536 .addReg(ptrA).addReg(ptrB);
6540 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6541 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6542 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6543 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6545 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6546 .addReg(Ptr1Reg).addImm(0).addImm(61);
6548 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6549 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6550 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6551 .addReg(newval).addReg(ShiftReg);
6552 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6553 .addReg(oldval).addReg(ShiftReg);
6555 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6557 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6558 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6559 .addReg(Mask3Reg).addImm(65535);
6561 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6562 .addReg(Mask2Reg).addReg(ShiftReg);
6563 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6564 .addReg(NewVal2Reg).addReg(MaskReg);
6565 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6566 .addReg(OldVal2Reg).addReg(MaskReg);
6569 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6570 .addReg(ZeroReg).addReg(PtrReg);
6571 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6572 .addReg(TmpDestReg).addReg(MaskReg);
6573 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6574 .addReg(TmpReg).addReg(OldVal3Reg);
6575 BuildMI(BB, dl, TII->get(PPC::BCC))
6576 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6577 BB->addSuccessor(loop2MBB);
6578 BB->addSuccessor(midMBB);
6581 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6582 .addReg(TmpDestReg).addReg(MaskReg);
6583 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6584 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6585 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6586 .addReg(ZeroReg).addReg(PtrReg);
6587 BuildMI(BB, dl, TII->get(PPC::BCC))
6588 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6589 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6590 BB->addSuccessor(loop1MBB);
6591 BB->addSuccessor(exitMBB);
6594 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
6595 .addReg(ZeroReg).addReg(PtrReg);
6596 BB->addSuccessor(exitMBB);
6601 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
6603 } else if (MI->getOpcode() == PPC::FADDrtz) {
6604 // This pseudo performs an FADD with rounding mode temporarily forced
6605 // to round-to-zero. We emit this via custom inserter since the FPSCR
6606 // is not modeled at the SelectionDAG level.
6607 unsigned Dest = MI->getOperand(0).getReg();
6608 unsigned Src1 = MI->getOperand(1).getReg();
6609 unsigned Src2 = MI->getOperand(2).getReg();
6610 DebugLoc dl = MI->getDebugLoc();
6612 MachineRegisterInfo &RegInfo = F->getRegInfo();
6613 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
6615 // Save FPSCR value.
6616 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
6618 // Set rounding mode to round-to-zero.
6619 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
6620 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
6622 // Perform addition.
6623 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
6625 // Restore FPSCR value.
6626 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
6627 } else if (MI->getOpcode() == PPC::FRINDrint ||
6628 MI->getOpcode() == PPC::FRINSrint) {
6629 bool isf32 = MI->getOpcode() == PPC::FRINSrint;
6630 unsigned Dest = MI->getOperand(0).getReg();
6631 unsigned Src = MI->getOperand(1).getReg();
6632 DebugLoc dl = MI->getDebugLoc();
6634 MachineRegisterInfo &RegInfo = F->getRegInfo();
6635 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
6637 // Perform the rounding.
6638 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FRINS : PPC::FRIND), Dest)
6641 // Compare the results.
6642 BuildMI(*BB, MI, dl, TII->get(isf32 ? PPC::FCMPUS : PPC::FCMPUD), CRReg)
6643 .addReg(Dest).addReg(Src);
6645 // If the results were not equal, then set the FPSCR XX bit.
6646 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6647 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6648 F->insert(It, midMBB);
6649 F->insert(It, exitMBB);
6650 exitMBB->splice(exitMBB->begin(), BB,
6651 llvm::next(MachineBasicBlock::iterator(MI)),
6653 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6655 BuildMI(*BB, MI, dl, TII->get(PPC::BCC))
6656 .addImm(PPC::PRED_EQ).addReg(CRReg).addMBB(exitMBB);
6658 BB->addSuccessor(midMBB);
6659 BB->addSuccessor(exitMBB);
6663 // Set the FPSCR XX bit (FE_INEXACT). Note that we cannot just set
6664 // the FI bit here because that will not automatically set XX also,
6665 // and XX is what libm interprets as the FE_INEXACT flag.
6666 BuildMI(BB, dl, TII->get(PPC::MTFSB1)).addImm(/* 38 - 32 = */ 6);
6667 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6669 BB->addSuccessor(exitMBB);
6673 llvm_unreachable("Unexpected instr type to insert");
6676 MI->eraseFromParent(); // The pseudo instruction is gone now.
6680 //===----------------------------------------------------------------------===//
6681 // Target Optimization Hooks
6682 //===----------------------------------------------------------------------===//
6684 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
6685 DAGCombinerInfo &DCI) const {
6686 if (DCI.isAfterLegalizeVectorOps())
6689 EVT VT = Op.getValueType();
6691 if ((VT == MVT::f32 && PPCSubTarget.hasFRES()) ||
6692 (VT == MVT::f64 && PPCSubTarget.hasFRE()) ||
6693 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6695 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6696 // For the reciprocal, we need to find the zero of the function:
6697 // F(X) = A X - 1 [which has a zero at X = 1/A]
6699 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
6700 // does not require additional intermediate precision]
6702 // Convergence is quadratic, so we essentially double the number of digits
6703 // correct after every iteration. The minimum architected relative
6704 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6705 // 23 digits and double has 52 digits.
6706 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6707 if (VT.getScalarType() == MVT::f64)
6710 SelectionDAG &DAG = DCI.DAG;
6714 DAG.getConstantFP(1.0, VT.getScalarType());
6715 if (VT.isVector()) {
6716 assert(VT.getVectorNumElements() == 4 &&
6717 "Unknown vector type");
6718 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6719 FPOne, FPOne, FPOne, FPOne);
6722 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
6723 DCI.AddToWorklist(Est.getNode());
6725 // Newton iterations: Est = Est + Est (1 - Arg * Est)
6726 for (int i = 0; i < Iterations; ++i) {
6727 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
6728 DCI.AddToWorklist(NewEst.getNode());
6730 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
6731 DCI.AddToWorklist(NewEst.getNode());
6733 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6734 DCI.AddToWorklist(NewEst.getNode());
6736 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
6737 DCI.AddToWorklist(Est.getNode());
6746 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
6747 DAGCombinerInfo &DCI) const {
6748 if (DCI.isAfterLegalizeVectorOps())
6751 EVT VT = Op.getValueType();
6753 if ((VT == MVT::f32 && PPCSubTarget.hasFRSQRTES()) ||
6754 (VT == MVT::f64 && PPCSubTarget.hasFRSQRTE()) ||
6755 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6757 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6758 // For the reciprocal sqrt, we need to find the zero of the function:
6759 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
6761 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
6762 // As a result, we precompute A/2 prior to the iteration loop.
6764 // Convergence is quadratic, so we essentially double the number of digits
6765 // correct after every iteration. The minimum architected relative
6766 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6767 // 23 digits and double has 52 digits.
6768 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6769 if (VT.getScalarType() == MVT::f64)
6772 SelectionDAG &DAG = DCI.DAG;
6775 SDValue FPThreeHalves =
6776 DAG.getConstantFP(1.5, VT.getScalarType());
6777 if (VT.isVector()) {
6778 assert(VT.getVectorNumElements() == 4 &&
6779 "Unknown vector type");
6780 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6781 FPThreeHalves, FPThreeHalves,
6782 FPThreeHalves, FPThreeHalves);
6785 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
6786 DCI.AddToWorklist(Est.getNode());
6788 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
6789 // this entire sequence requires only one FP constant.
6790 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
6791 DCI.AddToWorklist(HalfArg.getNode());
6793 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
6794 DCI.AddToWorklist(HalfArg.getNode());
6796 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
6797 for (int i = 0; i < Iterations; ++i) {
6798 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
6799 DCI.AddToWorklist(NewEst.getNode());
6801 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
6802 DCI.AddToWorklist(NewEst.getNode());
6804 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
6805 DCI.AddToWorklist(NewEst.getNode());
6807 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6808 DCI.AddToWorklist(Est.getNode());
6817 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
6818 // not enforce equality of the chain operands.
6819 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
6820 unsigned Bytes, int Dist,
6821 SelectionDAG &DAG) {
6822 EVT VT = LS->getMemoryVT();
6823 if (VT.getSizeInBits() / 8 != Bytes)
6826 SDValue Loc = LS->getBasePtr();
6827 SDValue BaseLoc = Base->getBasePtr();
6828 if (Loc.getOpcode() == ISD::FrameIndex) {
6829 if (BaseLoc.getOpcode() != ISD::FrameIndex)
6831 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6832 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
6833 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
6834 int FS = MFI->getObjectSize(FI);
6835 int BFS = MFI->getObjectSize(BFI);
6836 if (FS != BFS || FS != (int)Bytes) return false;
6837 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
6841 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
6842 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
6845 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6846 const GlobalValue *GV1 = NULL;
6847 const GlobalValue *GV2 = NULL;
6848 int64_t Offset1 = 0;
6849 int64_t Offset2 = 0;
6850 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
6851 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
6852 if (isGA1 && isGA2 && GV1 == GV2)
6853 return Offset1 == (Offset2 + Dist*Bytes);
6857 // Return true is there is a nearyby consecutive load to the one provided
6858 // (regardless of alignment). We search up and down the chain, looking though
6859 // token factors and other loads (but nothing else). As a result, a true
6860 // results indicates that it is safe to create a new consecutive load adjacent
6861 // to the load provided.
6862 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
6863 SDValue Chain = LD->getChain();
6864 EVT VT = LD->getMemoryVT();
6866 SmallSet<SDNode *, 16> LoadRoots;
6867 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
6868 SmallSet<SDNode *, 16> Visited;
6870 // First, search up the chain, branching to follow all token-factor operands.
6871 // If we find a consecutive load, then we're done, otherwise, record all
6872 // nodes just above the top-level loads and token factors.
6873 while (!Queue.empty()) {
6874 SDNode *ChainNext = Queue.pop_back_val();
6875 if (!Visited.insert(ChainNext))
6878 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
6879 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
6882 if (!Visited.count(ChainLD->getChain().getNode()))
6883 Queue.push_back(ChainLD->getChain().getNode());
6884 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
6885 for (SDNode::op_iterator O = ChainNext->op_begin(),
6886 OE = ChainNext->op_end(); O != OE; ++O)
6887 if (!Visited.count(O->getNode()))
6888 Queue.push_back(O->getNode());
6890 LoadRoots.insert(ChainNext);
6893 // Second, search down the chain, starting from the top-level nodes recorded
6894 // in the first phase. These top-level nodes are the nodes just above all
6895 // loads and token factors. Starting with their uses, recursively look though
6896 // all loads (just the chain uses) and token factors to find a consecutive
6901 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
6902 IE = LoadRoots.end(); I != IE; ++I) {
6903 Queue.push_back(*I);
6905 while (!Queue.empty()) {
6906 SDNode *LoadRoot = Queue.pop_back_val();
6907 if (!Visited.insert(LoadRoot))
6910 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
6911 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
6914 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
6915 UE = LoadRoot->use_end(); UI != UE; ++UI)
6916 if (((isa<LoadSDNode>(*UI) &&
6917 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
6918 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
6919 Queue.push_back(*UI);
6926 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
6927 DAGCombinerInfo &DCI) const {
6928 const TargetMachine &TM = getTargetMachine();
6929 SelectionDAG &DAG = DCI.DAG;
6931 switch (N->getOpcode()) {
6934 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6935 if (C->isNullValue()) // 0 << V -> 0.
6936 return N->getOperand(0);
6940 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6941 if (C->isNullValue()) // 0 >>u V -> 0.
6942 return N->getOperand(0);
6946 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6947 if (C->isNullValue() || // 0 >>s V -> 0.
6948 C->isAllOnesValue()) // -1 >>s V -> -1.
6949 return N->getOperand(0);
6953 assert(TM.Options.UnsafeFPMath &&
6954 "Reciprocal estimates require UnsafeFPMath");
6956 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
6958 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
6959 if (RV.getNode() != 0) {
6960 DCI.AddToWorklist(RV.getNode());
6961 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6962 N->getOperand(0), RV);
6964 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
6965 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
6967 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
6969 if (RV.getNode() != 0) {
6970 DCI.AddToWorklist(RV.getNode());
6971 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
6972 N->getValueType(0), RV);
6973 DCI.AddToWorklist(RV.getNode());
6974 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6975 N->getOperand(0), RV);
6977 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
6978 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
6980 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
6982 if (RV.getNode() != 0) {
6983 DCI.AddToWorklist(RV.getNode());
6984 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
6985 N->getValueType(0), RV,
6986 N->getOperand(1).getOperand(1));
6987 DCI.AddToWorklist(RV.getNode());
6988 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6989 N->getOperand(0), RV);
6993 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
6994 if (RV.getNode() != 0) {
6995 DCI.AddToWorklist(RV.getNode());
6996 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
6997 N->getOperand(0), RV);
7003 assert(TM.Options.UnsafeFPMath &&
7004 "Reciprocal estimates require UnsafeFPMath");
7006 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
7008 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
7009 if (RV.getNode() != 0) {
7010 DCI.AddToWorklist(RV.getNode());
7011 RV = DAGCombineFastRecip(RV, DCI);
7012 if (RV.getNode() != 0)
7018 case ISD::SINT_TO_FP:
7019 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
7020 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
7021 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
7022 // We allow the src/dst to be either f32/f64, but the intermediate
7023 // type must be i64.
7024 if (N->getOperand(0).getValueType() == MVT::i64 &&
7025 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
7026 SDValue Val = N->getOperand(0).getOperand(0);
7027 if (Val.getValueType() == MVT::f32) {
7028 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7029 DCI.AddToWorklist(Val.getNode());
7032 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
7033 DCI.AddToWorklist(Val.getNode());
7034 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
7035 DCI.AddToWorklist(Val.getNode());
7036 if (N->getValueType(0) == MVT::f32) {
7037 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
7038 DAG.getIntPtrConstant(0));
7039 DCI.AddToWorklist(Val.getNode());
7042 } else if (N->getOperand(0).getValueType() == MVT::i32) {
7043 // If the intermediate type is i32, we can avoid the load/store here
7050 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
7051 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
7052 !cast<StoreSDNode>(N)->isTruncatingStore() &&
7053 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
7054 N->getOperand(1).getValueType() == MVT::i32 &&
7055 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
7056 SDValue Val = N->getOperand(1).getOperand(0);
7057 if (Val.getValueType() == MVT::f32) {
7058 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7059 DCI.AddToWorklist(Val.getNode());
7061 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
7062 DCI.AddToWorklist(Val.getNode());
7065 N->getOperand(0), Val, N->getOperand(2),
7066 DAG.getValueType(N->getOperand(1).getValueType())
7069 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
7070 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
7071 cast<StoreSDNode>(N)->getMemoryVT(),
7072 cast<StoreSDNode>(N)->getMemOperand());
7073 DCI.AddToWorklist(Val.getNode());
7077 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
7078 if (cast<StoreSDNode>(N)->isUnindexed() &&
7079 N->getOperand(1).getOpcode() == ISD::BSWAP &&
7080 N->getOperand(1).getNode()->hasOneUse() &&
7081 (N->getOperand(1).getValueType() == MVT::i32 ||
7082 N->getOperand(1).getValueType() == MVT::i16 ||
7083 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7084 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7085 N->getOperand(1).getValueType() == MVT::i64))) {
7086 SDValue BSwapOp = N->getOperand(1).getOperand(0);
7087 // Do an any-extend to 32-bits if this is a half-word input.
7088 if (BSwapOp.getValueType() == MVT::i16)
7089 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
7092 N->getOperand(0), BSwapOp, N->getOperand(2),
7093 DAG.getValueType(N->getOperand(1).getValueType())
7096 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
7097 Ops, array_lengthof(Ops),
7098 cast<StoreSDNode>(N)->getMemoryVT(),
7099 cast<StoreSDNode>(N)->getMemOperand());
7103 LoadSDNode *LD = cast<LoadSDNode>(N);
7104 EVT VT = LD->getValueType(0);
7105 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
7106 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
7107 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
7108 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
7109 DCI.getDAGCombineLevel() == AfterLegalizeTypes &&
7110 LD->getAlignment() < ABIAlignment) {
7111 // This is a type-legal unaligned Altivec load.
7112 SDValue Chain = LD->getChain();
7113 SDValue Ptr = LD->getBasePtr();
7115 // This implements the loading of unaligned vectors as described in
7116 // the venerable Apple Velocity Engine overview. Specifically:
7117 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
7118 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
7120 // The general idea is to expand a sequence of one or more unaligned
7121 // loads into a alignment-based permutation-control instruction (lvsl),
7122 // a series of regular vector loads (which always truncate their
7123 // input address to an aligned address), and a series of permutations.
7124 // The results of these permutations are the requested loaded values.
7125 // The trick is that the last "extra" load is not taken from the address
7126 // you might suspect (sizeof(vector) bytes after the last requested
7127 // load), but rather sizeof(vector) - 1 bytes after the last
7128 // requested vector. The point of this is to avoid a page fault if the
7129 // base address happend to be aligned. This works because if the base
7130 // address is aligned, then adding less than a full vector length will
7131 // cause the last vector in the sequence to be (re)loaded. Otherwise,
7132 // the next vector will be fetched as you might suspect was necessary.
7134 // We might be able to reuse the permutation generation from
7135 // a different base address offset from this one by an aligned amount.
7136 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
7137 // optimization later.
7138 SDValue PermCntl = BuildIntrinsicOp(Intrinsic::ppc_altivec_lvsl, Ptr,
7139 DAG, dl, MVT::v16i8);
7141 // Refine the alignment of the original load (a "new" load created here
7142 // which was identical to the first except for the alignment would be
7143 // merged with the existing node regardless).
7144 MachineFunction &MF = DAG.getMachineFunction();
7145 MachineMemOperand *MMO =
7146 MF.getMachineMemOperand(LD->getPointerInfo(),
7147 LD->getMemOperand()->getFlags(),
7148 LD->getMemoryVT().getStoreSize(),
7150 LD->refineAlignment(MMO);
7151 SDValue BaseLoad = SDValue(LD, 0);
7153 // Note that the value of IncOffset (which is provided to the next
7154 // load's pointer info offset value, and thus used to calculate the
7155 // alignment), and the value of IncValue (which is actually used to
7156 // increment the pointer value) are different! This is because we
7157 // require the next load to appear to be aligned, even though it
7158 // is actually offset from the base pointer by a lesser amount.
7159 int IncOffset = VT.getSizeInBits() / 8;
7160 int IncValue = IncOffset;
7162 // Walk (both up and down) the chain looking for another load at the real
7163 // (aligned) offset (the alignment of the other load does not matter in
7164 // this case). If found, then do not use the offset reduction trick, as
7165 // that will prevent the loads from being later combined (as they would
7166 // otherwise be duplicates).
7167 if (!findConsecutiveLoad(LD, DAG))
7170 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
7171 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
7174 DAG.getLoad(VT, dl, Chain, Ptr,
7175 LD->getPointerInfo().getWithOffset(IncOffset),
7176 LD->isVolatile(), LD->isNonTemporal(),
7177 LD->isInvariant(), ABIAlignment);
7179 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
7180 BaseLoad.getValue(1), ExtraLoad.getValue(1));
7182 if (BaseLoad.getValueType() != MVT::v4i32)
7183 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
7185 if (ExtraLoad.getValueType() != MVT::v4i32)
7186 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
7188 SDValue Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
7189 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
7191 if (VT != MVT::v4i32)
7192 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
7194 // Now we need to be really careful about how we update the users of the
7195 // original load. We cannot just call DCI.CombineTo (or
7196 // DAG.ReplaceAllUsesWith for that matter), because the load still has
7197 // uses created here (the permutation for example) that need to stay.
7198 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
7200 SDUse &Use = UI.getUse();
7202 // Note: BaseLoad is checked here because it might not be N, but a
7204 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
7205 User == TF.getNode() || Use.getResNo() > 1) {
7210 SDValue To = Use.getResNo() ? TF : Perm;
7213 SmallVector<SDValue, 8> Ops;
7214 for (SDNode::op_iterator O = User->op_begin(),
7215 OE = User->op_end(); O != OE; ++O) {
7222 DAG.UpdateNodeOperands(User, Ops.data(), Ops.size());
7225 return SDValue(N, 0);
7229 case ISD::INTRINSIC_WO_CHAIN:
7230 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() ==
7231 Intrinsic::ppc_altivec_lvsl &&
7232 N->getOperand(1)->getOpcode() == ISD::ADD) {
7233 SDValue Add = N->getOperand(1);
7235 if (DAG.MaskedValueIsZero(Add->getOperand(1),
7236 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
7237 Add.getValueType().getScalarType().getSizeInBits()))) {
7238 SDNode *BasePtr = Add->getOperand(0).getNode();
7239 for (SDNode::use_iterator UI = BasePtr->use_begin(),
7240 UE = BasePtr->use_end(); UI != UE; ++UI) {
7241 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7242 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
7243 Intrinsic::ppc_altivec_lvsl) {
7244 // We've found another LVSL, and this address if an aligned
7245 // multiple of that one. The results will be the same, so use the
7246 // one we've just found instead.
7248 return SDValue(*UI, 0);
7254 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
7255 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
7256 N->getOperand(0).hasOneUse() &&
7257 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
7258 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7259 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7260 N->getValueType(0) == MVT::i64))) {
7261 SDValue Load = N->getOperand(0);
7262 LoadSDNode *LD = cast<LoadSDNode>(Load);
7263 // Create the byte-swapping load.
7265 LD->getChain(), // Chain
7266 LD->getBasePtr(), // Ptr
7267 DAG.getValueType(N->getValueType(0)) // VT
7270 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
7271 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
7272 MVT::i64 : MVT::i32, MVT::Other),
7273 Ops, 3, LD->getMemoryVT(), LD->getMemOperand());
7275 // If this is an i16 load, insert the truncate.
7276 SDValue ResVal = BSLoad;
7277 if (N->getValueType(0) == MVT::i16)
7278 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
7280 // First, combine the bswap away. This makes the value produced by the
7282 DCI.CombineTo(N, ResVal);
7284 // Next, combine the load away, we give it a bogus result value but a real
7285 // chain result. The result value is dead because the bswap is dead.
7286 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
7288 // Return N so it doesn't get rechecked!
7289 return SDValue(N, 0);
7293 case PPCISD::VCMP: {
7294 // If a VCMPo node already exists with exactly the same operands as this
7295 // node, use its result instead of this node (VCMPo computes both a CR6 and
7296 // a normal output).
7298 if (!N->getOperand(0).hasOneUse() &&
7299 !N->getOperand(1).hasOneUse() &&
7300 !N->getOperand(2).hasOneUse()) {
7302 // Scan all of the users of the LHS, looking for VCMPo's that match.
7303 SDNode *VCMPoNode = 0;
7305 SDNode *LHSN = N->getOperand(0).getNode();
7306 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
7308 if (UI->getOpcode() == PPCISD::VCMPo &&
7309 UI->getOperand(1) == N->getOperand(1) &&
7310 UI->getOperand(2) == N->getOperand(2) &&
7311 UI->getOperand(0) == N->getOperand(0)) {
7316 // If there is no VCMPo node, or if the flag value has a single use, don't
7318 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
7321 // Look at the (necessarily single) use of the flag value. If it has a
7322 // chain, this transformation is more complex. Note that multiple things
7323 // could use the value result, which we should ignore.
7324 SDNode *FlagUser = 0;
7325 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
7326 FlagUser == 0; ++UI) {
7327 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
7329 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
7330 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
7337 // If the user is a MFOCRF instruction, we know this is safe.
7338 // Otherwise we give up for right now.
7339 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
7340 return SDValue(VCMPoNode, 0);
7345 // If this is a branch on an altivec predicate comparison, lower this so
7346 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
7347 // lowering is done pre-legalize, because the legalizer lowers the predicate
7348 // compare down to code that is difficult to reassemble.
7349 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
7350 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
7352 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
7353 // value. If so, pass-through the AND to get to the intrinsic.
7354 if (LHS.getOpcode() == ISD::AND &&
7355 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7356 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
7357 Intrinsic::ppc_is_decremented_ctr_nonzero &&
7358 isa<ConstantSDNode>(LHS.getOperand(1)) &&
7359 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
7361 LHS = LHS.getOperand(0);
7363 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7364 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
7365 Intrinsic::ppc_is_decremented_ctr_nonzero &&
7366 isa<ConstantSDNode>(RHS)) {
7367 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
7368 "Counter decrement comparison is not EQ or NE");
7370 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7371 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
7372 (CC == ISD::SETNE && !Val);
7374 // We now need to make the intrinsic dead (it cannot be instruction
7376 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
7377 assert(LHS.getNode()->hasOneUse() &&
7378 "Counter decrement has more than one use");
7380 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
7381 N->getOperand(0), N->getOperand(4));
7387 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7388 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
7389 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
7390 assert(isDot && "Can't compare against a vector result!");
7392 // If this is a comparison against something other than 0/1, then we know
7393 // that the condition is never/always true.
7394 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7395 if (Val != 0 && Val != 1) {
7396 if (CC == ISD::SETEQ) // Cond never true, remove branch.
7397 return N->getOperand(0);
7398 // Always !=, turn it into an unconditional branch.
7399 return DAG.getNode(ISD::BR, dl, MVT::Other,
7400 N->getOperand(0), N->getOperand(4));
7403 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
7405 // Create the PPCISD altivec 'dot' comparison node.
7407 LHS.getOperand(2), // LHS of compare
7408 LHS.getOperand(3), // RHS of compare
7409 DAG.getConstant(CompareOpc, MVT::i32)
7411 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
7412 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
7414 // Unpack the result based on how the target uses it.
7415 PPC::Predicate CompOpc;
7416 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
7417 default: // Can't happen, don't crash on invalid number though.
7418 case 0: // Branch on the value of the EQ bit of CR6.
7419 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
7421 case 1: // Branch on the inverted value of the EQ bit of CR6.
7422 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
7424 case 2: // Branch on the value of the LT bit of CR6.
7425 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
7427 case 3: // Branch on the inverted value of the LT bit of CR6.
7428 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
7432 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
7433 DAG.getConstant(CompOpc, MVT::i32),
7434 DAG.getRegister(PPC::CR6, MVT::i32),
7435 N->getOperand(4), CompNode.getValue(1));
7444 //===----------------------------------------------------------------------===//
7445 // Inline Assembly Support
7446 //===----------------------------------------------------------------------===//
7448 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7451 const SelectionDAG &DAG,
7452 unsigned Depth) const {
7453 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
7454 switch (Op.getOpcode()) {
7456 case PPCISD::LBRX: {
7457 // lhbrx is known to have the top bits cleared out.
7458 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
7459 KnownZero = 0xFFFF0000;
7462 case ISD::INTRINSIC_WO_CHAIN: {
7463 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
7465 case Intrinsic::ppc_altivec_vcmpbfp_p:
7466 case Intrinsic::ppc_altivec_vcmpeqfp_p:
7467 case Intrinsic::ppc_altivec_vcmpequb_p:
7468 case Intrinsic::ppc_altivec_vcmpequh_p:
7469 case Intrinsic::ppc_altivec_vcmpequw_p:
7470 case Intrinsic::ppc_altivec_vcmpgefp_p:
7471 case Intrinsic::ppc_altivec_vcmpgtfp_p:
7472 case Intrinsic::ppc_altivec_vcmpgtsb_p:
7473 case Intrinsic::ppc_altivec_vcmpgtsh_p:
7474 case Intrinsic::ppc_altivec_vcmpgtsw_p:
7475 case Intrinsic::ppc_altivec_vcmpgtub_p:
7476 case Intrinsic::ppc_altivec_vcmpgtuh_p:
7477 case Intrinsic::ppc_altivec_vcmpgtuw_p:
7478 KnownZero = ~1U; // All bits but the low one are known to be zero.
7486 /// getConstraintType - Given a constraint, return the type of
7487 /// constraint it is for this target.
7488 PPCTargetLowering::ConstraintType
7489 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
7490 if (Constraint.size() == 1) {
7491 switch (Constraint[0]) {
7498 return C_RegisterClass;
7500 // FIXME: While Z does indicate a memory constraint, it specifically
7501 // indicates an r+r address (used in conjunction with the 'y' modifier
7502 // in the replacement string). Currently, we're forcing the base
7503 // register to be r0 in the asm printer (which is interpreted as zero)
7504 // and forming the complete address in the second register. This is
7509 return TargetLowering::getConstraintType(Constraint);
7512 /// Examine constraint type and operand type and determine a weight value.
7513 /// This object must already have been set up with the operand type
7514 /// and the current alternative constraint selected.
7515 TargetLowering::ConstraintWeight
7516 PPCTargetLowering::getSingleConstraintMatchWeight(
7517 AsmOperandInfo &info, const char *constraint) const {
7518 ConstraintWeight weight = CW_Invalid;
7519 Value *CallOperandVal = info.CallOperandVal;
7520 // If we don't have a value, we can't do a match,
7521 // but allow it at the lowest weight.
7522 if (CallOperandVal == NULL)
7524 Type *type = CallOperandVal->getType();
7525 // Look at the constraint type.
7526 switch (*constraint) {
7528 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
7531 if (type->isIntegerTy())
7532 weight = CW_Register;
7535 if (type->isFloatTy())
7536 weight = CW_Register;
7539 if (type->isDoubleTy())
7540 weight = CW_Register;
7543 if (type->isVectorTy())
7544 weight = CW_Register;
7547 weight = CW_Register;
7556 std::pair<unsigned, const TargetRegisterClass*>
7557 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7559 if (Constraint.size() == 1) {
7560 // GCC RS6000 Constraint Letters
7561 switch (Constraint[0]) {
7563 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7564 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
7565 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
7567 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7568 return std::make_pair(0U, &PPC::G8RCRegClass);
7569 return std::make_pair(0U, &PPC::GPRCRegClass);
7571 if (VT == MVT::f32 || VT == MVT::i32)
7572 return std::make_pair(0U, &PPC::F4RCRegClass);
7573 if (VT == MVT::f64 || VT == MVT::i64)
7574 return std::make_pair(0U, &PPC::F8RCRegClass);
7577 return std::make_pair(0U, &PPC::VRRCRegClass);
7579 return std::make_pair(0U, &PPC::CRRCRegClass);
7583 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7587 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7588 /// vector. If it is invalid, don't add anything to Ops.
7589 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7590 std::string &Constraint,
7591 std::vector<SDValue>&Ops,
7592 SelectionDAG &DAG) const {
7593 SDValue Result(0,0);
7595 // Only support length 1 constraints.
7596 if (Constraint.length() > 1) return;
7598 char Letter = Constraint[0];
7609 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
7610 if (!CST) return; // Must be an immediate to match.
7611 unsigned Value = CST->getZExtValue();
7613 default: llvm_unreachable("Unknown constraint letter!");
7614 case 'I': // "I" is a signed 16-bit constant.
7615 if ((short)Value == (int)Value)
7616 Result = DAG.getTargetConstant(Value, Op.getValueType());
7618 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
7619 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
7620 if ((short)Value == 0)
7621 Result = DAG.getTargetConstant(Value, Op.getValueType());
7623 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
7624 if ((Value >> 16) == 0)
7625 Result = DAG.getTargetConstant(Value, Op.getValueType());
7627 case 'M': // "M" is a constant that is greater than 31.
7629 Result = DAG.getTargetConstant(Value, Op.getValueType());
7631 case 'N': // "N" is a positive constant that is an exact power of two.
7632 if ((int)Value > 0 && isPowerOf2_32(Value))
7633 Result = DAG.getTargetConstant(Value, Op.getValueType());
7635 case 'O': // "O" is the constant zero.
7637 Result = DAG.getTargetConstant(Value, Op.getValueType());
7639 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
7640 if ((short)-Value == (int)-Value)
7641 Result = DAG.getTargetConstant(Value, Op.getValueType());
7648 if (Result.getNode()) {
7649 Ops.push_back(Result);
7653 // Handle standard constraint letters.
7654 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7657 // isLegalAddressingMode - Return true if the addressing mode represented
7658 // by AM is legal for this target, for a load/store of the specified type.
7659 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
7661 // FIXME: PPC does not allow r+i addressing modes for vectors!
7663 // PPC allows a sign-extended 16-bit immediate field.
7664 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
7667 // No global is ever allowed as a base.
7671 // PPC only support r+r,
7673 case 0: // "r+i" or just "i", depending on HasBaseReg.
7676 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
7678 // Otherwise we have r+r or r+i.
7681 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
7683 // Allow 2*r as r+r.
7686 // No other scales are supported.
7693 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
7694 SelectionDAG &DAG) const {
7695 MachineFunction &MF = DAG.getMachineFunction();
7696 MachineFrameInfo *MFI = MF.getFrameInfo();
7697 MFI->setReturnAddressIsTaken(true);
7700 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7702 // Make sure the function does not optimize away the store of the RA to
7704 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
7705 FuncInfo->setLRStoreRequired();
7706 bool isPPC64 = PPCSubTarget.isPPC64();
7707 bool isDarwinABI = PPCSubTarget.isDarwinABI();
7710 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7713 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
7714 isPPC64? MVT::i64 : MVT::i32);
7715 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7716 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7718 MachinePointerInfo(), false, false, false, 0);
7721 // Just load the return address off the stack.
7722 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
7723 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7724 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
7727 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
7728 SelectionDAG &DAG) const {
7730 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7732 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
7733 bool isPPC64 = PtrVT == MVT::i64;
7735 MachineFunction &MF = DAG.getMachineFunction();
7736 MachineFrameInfo *MFI = MF.getFrameInfo();
7737 MFI->setFrameAddressIsTaken(true);
7739 // Naked functions never have a frame pointer, and so we use r1. For all
7740 // other functions, this decision must be delayed until during PEI.
7742 if (MF.getFunction()->getAttributes().hasAttribute(
7743 AttributeSet::FunctionIndex, Attribute::Naked))
7744 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
7746 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
7748 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
7751 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
7752 FrameAddr, MachinePointerInfo(), false, false,
7758 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7759 // The PowerPC target isn't yet aware of offsets.
7763 /// getOptimalMemOpType - Returns the target specific optimal type for load
7764 /// and store operations as a result of memset, memcpy, and memmove
7765 /// lowering. If DstAlign is zero that means it's safe to destination
7766 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
7767 /// means there isn't a need to check it against alignment requirement,
7768 /// probably because the source does not need to be loaded. If 'IsMemset' is
7769 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
7770 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
7771 /// source is constant so it does not need to be loaded.
7772 /// It returns EVT::Other if the type should be determined using generic
7773 /// target-independent logic.
7774 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
7775 unsigned DstAlign, unsigned SrcAlign,
7776 bool IsMemset, bool ZeroMemset,
7778 MachineFunction &MF) const {
7779 if (this->PPCSubTarget.isPPC64()) {
7786 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
7788 if (DisablePPCUnaligned)
7791 // PowerPC supports unaligned memory access for simple non-vector types.
7792 // Although accessing unaligned addresses is not as efficient as accessing
7793 // aligned addresses, it is generally more efficient than manual expansion,
7794 // and generally only traps for software emulation when crossing page
7800 if (VT.getSimpleVT().isVector())
7803 if (VT == MVT::ppcf128)
7812 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
7813 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
7814 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
7815 /// is expanded to mul + add.
7816 bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const {
7820 switch (VT.getSimpleVT().SimpleTy) {
7832 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
7834 return TargetLowering::getSchedulingPreference(N);