1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCTargetMachine.h"
16 #include "PPCPerfectShuffle.h"
17 #include "llvm/ADT/VectorExtras.h"
18 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Function.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Target/TargetOptions.h"
31 PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
32 : TargetLowering(TM) {
34 // Fold away setcc operations if possible.
35 setSetCCIsExpensive();
38 // Use _setjmp/_longjmp instead of setjmp/longjmp.
39 setUseUnderscoreSetJmpLongJmp(true);
41 // Set up the register classes.
42 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
43 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
44 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
46 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
47 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
49 // PowerPC has no intrinsics for these particular operations
50 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
51 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
52 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
54 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
55 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
56 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
58 // PowerPC has no SREM/UREM instructions
59 setOperationAction(ISD::SREM, MVT::i32, Expand);
60 setOperationAction(ISD::UREM, MVT::i32, Expand);
61 setOperationAction(ISD::SREM, MVT::i64, Expand);
62 setOperationAction(ISD::UREM, MVT::i64, Expand);
64 // We don't support sin/cos/sqrt/fmod
65 setOperationAction(ISD::FSIN , MVT::f64, Expand);
66 setOperationAction(ISD::FCOS , MVT::f64, Expand);
67 setOperationAction(ISD::FREM , MVT::f64, Expand);
68 setOperationAction(ISD::FSIN , MVT::f32, Expand);
69 setOperationAction(ISD::FCOS , MVT::f32, Expand);
70 setOperationAction(ISD::FREM , MVT::f32, Expand);
72 // If we're enabling GP optimizations, use hardware square root
73 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
74 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
75 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
78 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
79 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
81 // PowerPC does not have BSWAP, CTPOP or CTTZ
82 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
83 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
84 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
85 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
86 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
87 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
89 // PowerPC does not have ROTR
90 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
92 // PowerPC does not have Select
93 setOperationAction(ISD::SELECT, MVT::i32, Expand);
94 setOperationAction(ISD::SELECT, MVT::i64, Expand);
95 setOperationAction(ISD::SELECT, MVT::f32, Expand);
96 setOperationAction(ISD::SELECT, MVT::f64, Expand);
98 // PowerPC wants to turn select_cc of FP into fsel when possible.
99 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
100 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
102 // PowerPC wants to optimize integer setcc a bit
103 setOperationAction(ISD::SETCC, MVT::i32, Custom);
105 // PowerPC does not have BRCOND which requires SetCC
106 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
108 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
109 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
111 // PowerPC does not have [U|S]INT_TO_FP
112 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
113 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
115 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
116 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
117 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
118 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
120 // PowerPC does not have truncstore for i1.
121 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
123 // We cannot sextinreg(i1). Expand to shifts.
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
127 // Support label based line numbers.
128 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
129 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
130 // FIXME - use subtarget debug flags
131 if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
132 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
134 // We want to legalize GlobalAddress and ConstantPool nodes into the
135 // appropriate instructions to materialize the address.
136 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
137 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
138 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
139 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
140 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
141 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
143 // RET must be custom lowered, to meet ABI requirements
144 setOperationAction(ISD::RET , MVT::Other, Custom);
146 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
147 setOperationAction(ISD::VASTART , MVT::Other, Custom);
149 // Use the default implementation.
150 setOperationAction(ISD::VAARG , MVT::Other, Expand);
151 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
152 setOperationAction(ISD::VAEND , MVT::Other, Expand);
153 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
154 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
155 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
157 // We want to custom lower some of our intrinsics.
158 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
160 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
161 // They also have instructions for converting between i64 and fp.
162 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
163 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
165 // FIXME: disable this lowered code. This generates 64-bit register values,
166 // and we don't model the fact that the top part is clobbered by calls. We
167 // need to flag these together so that the value isn't live across a call.
168 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
170 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
171 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
173 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
174 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
177 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
178 // 64 bit PowerPC implementations can support i64 types directly
179 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
180 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
181 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
183 // 32 bit PowerPC wants to expand i64 shifts itself.
184 setOperationAction(ISD::SHL, MVT::i64, Custom);
185 setOperationAction(ISD::SRL, MVT::i64, Custom);
186 setOperationAction(ISD::SRA, MVT::i64, Custom);
189 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
190 // First set operation action for all vector types to expand. Then we
191 // will selectively turn on ones that can be effectively codegen'd.
192 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
193 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
194 // add/sub are legal for all supported vector VT's.
195 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
196 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
198 // We promote all shuffles to v16i8.
199 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
200 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
202 // We promote all non-typed operations to v4i32.
203 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
204 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
205 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
206 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
207 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
208 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
209 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
210 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
211 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
212 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
213 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
214 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
216 // No other operations are legal.
217 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
218 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
219 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
220 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
221 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
222 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
223 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
224 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
225 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
227 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
230 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
231 // with merges, splats, etc.
232 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
234 setOperationAction(ISD::AND , MVT::v4i32, Legal);
235 setOperationAction(ISD::OR , MVT::v4i32, Legal);
236 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
237 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
238 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
239 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
241 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
242 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
243 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
244 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
246 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
247 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
248 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
249 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
251 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
252 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
254 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
255 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
256 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
257 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
260 setSetCCResultType(MVT::i32);
261 setShiftAmountType(MVT::i32);
262 setSetCCResultContents(ZeroOrOneSetCCResult);
263 setStackPointerRegisterToSaveRestore(PPC::R1);
265 // We have target-specific dag combine patterns for the following nodes:
266 setTargetDAGCombine(ISD::SINT_TO_FP);
267 setTargetDAGCombine(ISD::STORE);
268 setTargetDAGCombine(ISD::BR_CC);
269 setTargetDAGCombine(ISD::BSWAP);
271 computeRegisterProperties();
274 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
277 case PPCISD::FSEL: return "PPCISD::FSEL";
278 case PPCISD::FCFID: return "PPCISD::FCFID";
279 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
280 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
281 case PPCISD::STFIWX: return "PPCISD::STFIWX";
282 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
283 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
284 case PPCISD::VPERM: return "PPCISD::VPERM";
285 case PPCISD::Hi: return "PPCISD::Hi";
286 case PPCISD::Lo: return "PPCISD::Lo";
287 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
288 case PPCISD::SRL: return "PPCISD::SRL";
289 case PPCISD::SRA: return "PPCISD::SRA";
290 case PPCISD::SHL: return "PPCISD::SHL";
291 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
292 case PPCISD::STD_32: return "PPCISD::STD_32";
293 case PPCISD::CALL: return "PPCISD::CALL";
294 case PPCISD::MTCTR: return "PPCISD::MTCTR";
295 case PPCISD::BCTRL: return "PPCISD::BCTRL";
296 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
297 case PPCISD::MFCR: return "PPCISD::MFCR";
298 case PPCISD::VCMP: return "PPCISD::VCMP";
299 case PPCISD::VCMPo: return "PPCISD::VCMPo";
300 case PPCISD::LBRX: return "PPCISD::LBRX";
301 case PPCISD::STBRX: return "PPCISD::STBRX";
302 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
306 //===----------------------------------------------------------------------===//
307 // Node matching predicates, for use by the tblgen matching code.
308 //===----------------------------------------------------------------------===//
310 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
311 static bool isFloatingPointZero(SDOperand Op) {
312 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
313 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
314 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
315 // Maybe this has already been legalized into the constant pool?
316 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
317 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
318 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
323 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
324 /// true if Op is undef or if it matches the specified value.
325 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
326 return Op.getOpcode() == ISD::UNDEF ||
327 cast<ConstantSDNode>(Op)->getValue() == Val;
330 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
331 /// VPKUHUM instruction.
332 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
334 for (unsigned i = 0; i != 16; ++i)
335 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
338 for (unsigned i = 0; i != 8; ++i)
339 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
340 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
346 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
347 /// VPKUWUM instruction.
348 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
350 for (unsigned i = 0; i != 16; i += 2)
351 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
352 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
355 for (unsigned i = 0; i != 8; i += 2)
356 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
357 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
358 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
359 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
365 /// isVMerge - Common function, used to match vmrg* shuffles.
367 static bool isVMerge(SDNode *N, unsigned UnitSize,
368 unsigned LHSStart, unsigned RHSStart) {
369 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
370 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
371 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
372 "Unsupported merge size!");
374 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
375 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
376 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
377 LHSStart+j+i*UnitSize) ||
378 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
379 RHSStart+j+i*UnitSize))
385 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
386 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
387 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
389 return isVMerge(N, UnitSize, 8, 24);
390 return isVMerge(N, UnitSize, 8, 8);
393 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
394 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
395 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
397 return isVMerge(N, UnitSize, 0, 16);
398 return isVMerge(N, UnitSize, 0, 0);
402 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
403 /// amount, otherwise return -1.
404 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
405 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
406 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
407 // Find the first non-undef value in the shuffle mask.
409 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
412 if (i == 16) return -1; // all undef.
414 // Otherwise, check to see if the rest of the elements are consequtively
415 // numbered from this value.
416 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
417 if (ShiftAmt < i) return -1;
421 // Check the rest of the elements to see if they are consequtive.
422 for (++i; i != 16; ++i)
423 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
426 // Check the rest of the elements to see if they are consequtive.
427 for (++i; i != 16; ++i)
428 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
435 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
436 /// specifies a splat of a single element that is suitable for input to
437 /// VSPLTB/VSPLTH/VSPLTW.
438 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
439 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
440 N->getNumOperands() == 16 &&
441 (EltSize == 1 || EltSize == 2 || EltSize == 4));
443 // This is a splat operation if each element of the permute is the same, and
444 // if the value doesn't reference the second vector.
445 unsigned ElementBase = 0;
446 SDOperand Elt = N->getOperand(0);
447 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
448 ElementBase = EltV->getValue();
450 return false; // FIXME: Handle UNDEF elements too!
452 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
455 // Check that they are consequtive.
456 for (unsigned i = 1; i != EltSize; ++i) {
457 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
458 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
462 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
463 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
464 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
465 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
466 "Invalid VECTOR_SHUFFLE mask!");
467 for (unsigned j = 0; j != EltSize; ++j)
468 if (N->getOperand(i+j) != N->getOperand(j))
475 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
476 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
477 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
478 assert(isSplatShuffleMask(N, EltSize));
479 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
482 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
483 /// by using a vspltis[bhw] instruction of the specified element size, return
484 /// the constant being splatted. The ByteSize field indicates the number of
485 /// bytes of each element [124] -> [bhw].
486 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
487 SDOperand OpVal(0, 0);
489 // If ByteSize of the splat is bigger than the element size of the
490 // build_vector, then we have a case where we are checking for a splat where
491 // multiple elements of the buildvector are folded together into a single
492 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
493 unsigned EltSize = 16/N->getNumOperands();
494 if (EltSize < ByteSize) {
495 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
496 SDOperand UniquedVals[4];
497 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
499 // See if all of the elements in the buildvector agree across.
500 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
501 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
502 // If the element isn't a constant, bail fully out.
503 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
506 if (UniquedVals[i&(Multiple-1)].Val == 0)
507 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
508 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
509 return SDOperand(); // no match.
512 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
513 // either constant or undef values that are identical for each chunk. See
514 // if these chunks can form into a larger vspltis*.
516 // Check to see if all of the leading entries are either 0 or -1. If
517 // neither, then this won't fit into the immediate field.
518 bool LeadingZero = true;
519 bool LeadingOnes = true;
520 for (unsigned i = 0; i != Multiple-1; ++i) {
521 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
523 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
524 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
526 // Finally, check the least significant entry.
528 if (UniquedVals[Multiple-1].Val == 0)
529 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
530 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
532 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
535 if (UniquedVals[Multiple-1].Val == 0)
536 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
537 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
538 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
539 return DAG.getTargetConstant(Val, MVT::i32);
545 // Check to see if this buildvec has a single non-undef value in its elements.
546 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
547 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
549 OpVal = N->getOperand(i);
550 else if (OpVal != N->getOperand(i))
554 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
556 unsigned ValSizeInBytes = 0;
558 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
559 Value = CN->getValue();
560 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
561 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
562 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
563 Value = FloatToBits(CN->getValue());
567 // If the splat value is larger than the element value, then we can never do
568 // this splat. The only case that we could fit the replicated bits into our
569 // immediate field for would be zero, and we prefer to use vxor for it.
570 if (ValSizeInBytes < ByteSize) return SDOperand();
572 // If the element value is larger than the splat value, cut it in half and
573 // check to see if the two halves are equal. Continue doing this until we
574 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
575 while (ValSizeInBytes > ByteSize) {
576 ValSizeInBytes >>= 1;
578 // If the top half equals the bottom half, we're still ok.
579 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
580 (Value & ((1 << (8*ValSizeInBytes))-1)))
584 // Properly sign extend the value.
585 int ShAmt = (4-ByteSize)*8;
586 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
588 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
589 if (MaskVal == 0) return SDOperand();
591 // Finally, if this value fits in a 5 bit sext field, return it
592 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
593 return DAG.getTargetConstant(MaskVal, MVT::i32);
597 //===----------------------------------------------------------------------===//
598 // LowerOperation implementation
599 //===----------------------------------------------------------------------===//
601 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
602 MVT::ValueType PtrVT = Op.getValueType();
603 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
604 Constant *C = CP->get();
605 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
606 SDOperand Zero = DAG.getConstant(0, PtrVT);
608 const TargetMachine &TM = DAG.getTarget();
610 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
611 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
613 // If this is a non-darwin platform, we don't support non-static relo models
615 if (TM.getRelocationModel() == Reloc::Static ||
616 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
617 // Generate non-pic code that has direct accesses to the constant pool.
618 // The address of the global is just (hi(&g)+lo(&g)).
619 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
622 if (TM.getRelocationModel() == Reloc::PIC) {
623 // With PIC, the first instruction is actually "GR+hi(&G)".
624 Hi = DAG.getNode(ISD::ADD, PtrVT,
625 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
628 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
632 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
633 MVT::ValueType PtrVT = Op.getValueType();
634 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
635 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
636 SDOperand Zero = DAG.getConstant(0, PtrVT);
638 const TargetMachine &TM = DAG.getTarget();
640 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
641 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
643 // If this is a non-darwin platform, we don't support non-static relo models
645 if (TM.getRelocationModel() == Reloc::Static ||
646 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
647 // Generate non-pic code that has direct accesses to the constant pool.
648 // The address of the global is just (hi(&g)+lo(&g)).
649 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
652 if (TM.getRelocationModel() == Reloc::PIC) {
653 // With PIC, the first instruction is actually "GR+hi(&G)".
654 Hi = DAG.getNode(ISD::ADD, PtrVT,
655 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
658 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
662 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
663 MVT::ValueType PtrVT = Op.getValueType();
664 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
665 GlobalValue *GV = GSDN->getGlobal();
666 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
667 SDOperand Zero = DAG.getConstant(0, PtrVT);
669 const TargetMachine &TM = DAG.getTarget();
671 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
672 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
674 // If this is a non-darwin platform, we don't support non-static relo models
676 if (TM.getRelocationModel() == Reloc::Static ||
677 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
678 // Generate non-pic code that has direct accesses to globals.
679 // The address of the global is just (hi(&g)+lo(&g)).
680 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
683 if (TM.getRelocationModel() == Reloc::PIC) {
684 // With PIC, the first instruction is actually "GR+hi(&G)".
685 Hi = DAG.getNode(ISD::ADD, PtrVT,
686 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
689 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
691 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() &&
692 (!GV->isExternal() || GV->hasNotBeenReadFromBytecode()))
695 // If the global is weak or external, we have to go through the lazy
697 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
700 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
701 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
703 // If we're comparing for equality to zero, expose the fact that this is
704 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
705 // fold the new nodes.
706 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
707 if (C->isNullValue() && CC == ISD::SETEQ) {
708 MVT::ValueType VT = Op.getOperand(0).getValueType();
709 SDOperand Zext = Op.getOperand(0);
712 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
714 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
715 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
716 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
717 DAG.getConstant(Log2b, MVT::i32));
718 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
720 // Leave comparisons against 0 and -1 alone for now, since they're usually
721 // optimized. FIXME: revisit this when we can custom lower all setcc
723 if (C->isAllOnesValue() || C->isNullValue())
727 // If we have an integer seteq/setne, turn it into a compare against zero
728 // by subtracting the rhs from the lhs, which is faster than setting a
729 // condition register, reading it back out, and masking the correct bit.
730 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
731 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
732 MVT::ValueType VT = Op.getValueType();
733 SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0),
735 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
740 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
741 unsigned VarArgsFrameIndex) {
742 // vastart just stores the address of the VarArgsFrameIndex slot into the
743 // memory location argument.
744 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
745 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
746 Op.getOperand(1), Op.getOperand(2));
749 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
750 int &VarArgsFrameIndex) {
751 // TODO: add description of PPC stack frame format, or at least some docs.
753 MachineFunction &MF = DAG.getMachineFunction();
754 MachineFrameInfo *MFI = MF.getFrameInfo();
755 SSARegMap *RegMap = MF.getSSARegMap();
756 std::vector<SDOperand> ArgValues;
757 SDOperand Root = Op.getOperand(0);
759 unsigned ArgOffset = 24;
760 const unsigned Num_GPR_Regs = 8;
761 const unsigned Num_FPR_Regs = 13;
762 const unsigned Num_VR_Regs = 12;
763 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
765 static const unsigned GPR_32[] = { // 32-bit registers.
766 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
767 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
769 static const unsigned GPR_64[] = { // 64-bit registers.
770 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
771 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
773 static const unsigned FPR[] = {
774 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
775 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
777 static const unsigned VR[] = {
778 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
779 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
782 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
783 bool isPPC64 = PtrVT == MVT::i64;
784 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
786 // Add DAG nodes to load the arguments or copy them out of registers. On
787 // entry to a function on PPC, the arguments start at offset 24, although the
788 // first ones are often in registers.
789 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
791 bool needsLoad = false;
792 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
793 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
795 unsigned CurArgOffset = ArgOffset;
797 default: assert(0 && "Unhandled argument type!");
799 // All int arguments reserve stack space.
800 ArgOffset += isPPC64 ? 8 : 4;
802 if (GPR_idx != Num_GPR_Regs) {
803 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
804 MF.addLiveIn(GPR[GPR_idx], VReg);
805 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
811 case MVT::i64: // PPC64
812 // All int arguments reserve stack space.
815 if (GPR_idx != Num_GPR_Regs) {
816 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
817 MF.addLiveIn(GPR[GPR_idx], VReg);
818 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
826 // All FP arguments reserve stack space.
827 ArgOffset += ObjSize;
829 // Every 4 bytes of argument space consumes one of the GPRs available for
831 if (GPR_idx != Num_GPR_Regs) {
833 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs)
836 if (FPR_idx != Num_FPR_Regs) {
838 if (ObjectVT == MVT::f32)
839 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
841 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
842 MF.addLiveIn(FPR[FPR_idx], VReg);
843 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
853 // Note that vector arguments in registers don't reserve stack space.
854 if (VR_idx != Num_VR_Regs) {
855 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass);
856 MF.addLiveIn(VR[VR_idx], VReg);
857 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
860 // This should be simple, but requires getting 16-byte aligned stack
862 assert(0 && "Loading VR argument not implemented yet!");
868 // We need to load the argument to a virtual register if we determined above
869 // that we ran out of physical registers of the appropriate type
871 // If the argument is actually used, emit a load from the right stack
873 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
874 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
875 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
876 ArgVal = DAG.getLoad(ObjectVT, Root, FIN,
877 DAG.getSrcValue(NULL));
879 // Don't emit a dead load.
880 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
884 ArgValues.push_back(ArgVal);
887 // If the function takes variable number of arguments, make a frame index for
888 // the start of the first vararg value... for expansion of llvm.va_start.
889 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
891 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
893 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
894 // If this function is vararg, store any remaining integer argument regs
895 // to their spots on the stack so that they may be loaded by deferencing the
896 // result of va_next.
897 std::vector<SDOperand> MemOps;
898 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
899 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
900 MF.addLiveIn(GPR[GPR_idx], VReg);
901 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
902 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
903 Val, FIN, DAG.getSrcValue(NULL));
904 MemOps.push_back(Store);
905 // Increment the address by four for the next argument to store
906 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
907 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
910 Root = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
913 ArgValues.push_back(Root);
915 // Return the new list of results.
916 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
917 Op.Val->value_end());
918 return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
921 /// isCallCompatibleAddress - Return the immediate to use if the specified
922 /// 32-bit value is representable in the immediate field of a BxA instruction.
923 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
924 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
927 int Addr = C->getValue();
928 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
929 (Addr << 6 >> 6) != Addr)
930 return 0; // Top 6 bits have to be sext of immediate.
932 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
936 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
937 SDOperand Chain = Op.getOperand(0);
938 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
939 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
940 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
941 SDOperand Callee = Op.getOperand(4);
942 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
944 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
945 bool isPPC64 = PtrVT == MVT::i64;
946 unsigned PtrByteSize = isPPC64 ? 8 : 4;
949 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
950 // SelectExpr to use to put the arguments in the appropriate registers.
951 std::vector<SDOperand> args_to_use;
953 // Count how many bytes are to be pushed on the stack, including the linkage
954 // area, and parameter passing area. We start with 24/48 bytes, which is
955 // prereserved space for [SP][CR][LR][3 x unused].
956 unsigned NumBytes = 6*PtrByteSize;
958 // Add up all the space actually used.
959 for (unsigned i = 0; i != NumOps; ++i)
960 NumBytes += MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
962 // The prolog code of the callee may store up to 8 GPR argument registers to
963 // the stack, allowing va_start to index over them in memory if its varargs.
964 // Because we cannot tell if this is needed on the caller side, we have to
965 // conservatively assume that it is needed. As such, make sure we have at
966 // least enough stack space for the caller to store the 8 GPRs.
967 if (NumBytes < 6*PtrByteSize+8*PtrByteSize)
968 NumBytes = 6*PtrByteSize+8*PtrByteSize;
970 // Adjust the stack pointer for the new arguments...
971 // These operations are automatically eliminated by the prolog/epilog pass
972 Chain = DAG.getCALLSEQ_START(Chain,
973 DAG.getConstant(NumBytes, PtrVT));
975 // Set up a copy of the stack pointer for use loading and storing any
976 // arguments that may not fit in the registers available for argument
980 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
982 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
984 // Figure out which arguments are going to go in registers, and which in
985 // memory. Also, if this is a vararg function, floating point operations
986 // must be stored to our stack, and loaded into integer regs as well, if
987 // any integer regs are available for argument passing.
988 unsigned ArgOffset = 6*PtrByteSize;
989 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
990 static const unsigned GPR_32[] = { // 32-bit registers.
991 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
992 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
994 static const unsigned GPR_64[] = { // 64-bit registers.
995 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
996 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
998 static const unsigned FPR[] = {
999 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1000 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1002 static const unsigned VR[] = {
1003 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1004 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1006 const unsigned NumGPRs = sizeof(GPR_32)/sizeof(GPR_32[0]);
1007 const unsigned NumFPRs = sizeof(FPR)/sizeof(FPR[0]);
1008 const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]);
1010 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1012 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1013 std::vector<SDOperand> MemOpChains;
1014 for (unsigned i = 0; i != NumOps; ++i) {
1015 SDOperand Arg = Op.getOperand(5+2*i);
1017 // PtrOff will be used to store the current argument to the stack if a
1018 // register cannot be found for it.
1019 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1020 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1022 // On PPC64, promote integers to 64-bit values.
1023 if (isPPC64 && Arg.getValueType() == MVT::i32) {
1024 unsigned ExtOp = ISD::ZERO_EXTEND;
1025 if (cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue())
1026 ExtOp = ISD::SIGN_EXTEND;
1027 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1030 switch (Arg.getValueType()) {
1031 default: assert(0 && "Unexpected ValueType for argument!");
1034 if (GPR_idx != NumGPRs) {
1035 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
1037 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1038 Arg, PtrOff, DAG.getSrcValue(NULL)));
1040 ArgOffset += PtrByteSize;
1044 if (FPR_idx != NumFPRs) {
1045 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1048 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
1050 DAG.getSrcValue(NULL));
1051 MemOpChains.push_back(Store);
1053 // Float varargs are always shadowed in available integer registers
1054 if (GPR_idx != NumGPRs) {
1055 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff,
1056 DAG.getSrcValue(NULL));
1057 MemOpChains.push_back(Load.getValue(1));
1058 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1060 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) {
1061 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1062 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
1063 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff,
1064 DAG.getSrcValue(NULL));
1065 MemOpChains.push_back(Load.getValue(1));
1066 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1069 // If we have any FPRs remaining, we may also have GPRs remaining.
1070 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1072 if (GPR_idx != NumGPRs)
1074 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64)
1078 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1079 Arg, PtrOff, DAG.getSrcValue(NULL)));
1084 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1090 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1091 assert(VR_idx != NumVRs &&
1092 "Don't support passing more than 12 vector args yet!");
1093 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1097 if (!MemOpChains.empty())
1098 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOpChains);
1100 // Build a sequence of copy-to-reg nodes chained together with token chain
1101 // and flag operands which copy the outgoing args into the appropriate regs.
1103 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1104 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1106 InFlag = Chain.getValue(1);
1109 std::vector<MVT::ValueType> NodeTys;
1110 NodeTys.push_back(MVT::Other); // Returns a chain
1111 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1113 std::vector<SDOperand> Ops;
1114 unsigned CallOpc = PPCISD::CALL;
1116 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1117 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1118 // node so that legalize doesn't hack it.
1119 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1120 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1121 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1122 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1123 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1124 // If this is an absolute destination address, use the munged value.
1125 Callee = SDOperand(Dest, 0);
1127 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1128 // to do the call, we can't use PPCISD::CALL.
1129 Ops.push_back(Chain);
1130 Ops.push_back(Callee);
1133 Ops.push_back(InFlag);
1134 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, Ops);
1135 InFlag = Chain.getValue(1);
1137 // Copy the callee address into R12 on darwin.
1138 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1139 InFlag = Chain.getValue(1);
1142 NodeTys.push_back(MVT::Other);
1143 NodeTys.push_back(MVT::Flag);
1145 Ops.push_back(Chain);
1146 CallOpc = PPCISD::BCTRL;
1150 // If this is a direct call, pass the chain and the callee.
1152 Ops.push_back(Chain);
1153 Ops.push_back(Callee);
1156 // Add argument registers to the end of the list so that they are known live
1158 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1159 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1160 RegsToPass[i].second.getValueType()));
1163 Ops.push_back(InFlag);
1164 Chain = DAG.getNode(CallOpc, NodeTys, Ops);
1165 InFlag = Chain.getValue(1);
1167 std::vector<SDOperand> ResultVals;
1170 // If the call has results, copy the values out of the ret val registers.
1171 switch (Op.Val->getValueType(0)) {
1172 default: assert(0 && "Unexpected ret value!");
1173 case MVT::Other: break;
1175 if (Op.Val->getValueType(1) == MVT::i32) {
1176 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1);
1177 ResultVals.push_back(Chain.getValue(0));
1178 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32,
1179 Chain.getValue(2)).getValue(1);
1180 ResultVals.push_back(Chain.getValue(0));
1181 NodeTys.push_back(MVT::i32);
1183 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1184 ResultVals.push_back(Chain.getValue(0));
1186 NodeTys.push_back(MVT::i32);
1189 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
1190 ResultVals.push_back(Chain.getValue(0));
1191 NodeTys.push_back(MVT::i64);
1195 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1196 InFlag).getValue(1);
1197 ResultVals.push_back(Chain.getValue(0));
1198 NodeTys.push_back(Op.Val->getValueType(0));
1204 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1205 InFlag).getValue(1);
1206 ResultVals.push_back(Chain.getValue(0));
1207 NodeTys.push_back(Op.Val->getValueType(0));
1211 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1212 DAG.getConstant(NumBytes, PtrVT));
1213 NodeTys.push_back(MVT::Other);
1215 // If the function returns void, just return the chain.
1216 if (ResultVals.empty())
1219 // Otherwise, merge everything together with a MERGE_VALUES node.
1220 ResultVals.push_back(Chain);
1221 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys, ResultVals);
1222 return Res.getValue(Op.ResNo);
1225 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
1227 switch(Op.getNumOperands()) {
1229 assert(0 && "Do not know how to return this many arguments!");
1232 return SDOperand(); // ret void is legal
1234 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
1236 if (ArgVT == MVT::i32) {
1238 } else if (ArgVT == MVT::i64) {
1240 } else if (MVT::isFloatingPoint(ArgVT)) {
1243 assert(MVT::isVector(ArgVT));
1247 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
1250 // If we haven't noted the R3/F1 are live out, do so now.
1251 if (DAG.getMachineFunction().liveout_empty())
1252 DAG.getMachineFunction().addLiveOut(ArgReg);
1256 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3),
1258 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
1259 // If we haven't noted the R3+R4 are live out, do so now.
1260 if (DAG.getMachineFunction().liveout_empty()) {
1261 DAG.getMachineFunction().addLiveOut(PPC::R3);
1262 DAG.getMachineFunction().addLiveOut(PPC::R4);
1266 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
1269 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
1271 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
1272 // Not FP? Not a fsel.
1273 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
1274 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
1277 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1279 // Cannot handle SETEQ/SETNE.
1280 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
1282 MVT::ValueType ResVT = Op.getValueType();
1283 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
1284 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1285 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
1287 // If the RHS of the comparison is a 0.0, we don't need to do the
1288 // subtraction at all.
1289 if (isFloatingPointZero(RHS))
1291 default: break; // SETUO etc aren't handled by fsel.
1295 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1299 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1300 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1301 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
1305 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1309 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1310 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1311 return DAG.getNode(PPCISD::FSEL, ResVT,
1312 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
1317 default: break; // SETUO etc aren't handled by fsel.
1321 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1322 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1323 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1324 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1328 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1329 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1330 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1331 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1335 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1336 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1337 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1338 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1342 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1343 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1344 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1345 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1350 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
1351 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
1352 SDOperand Src = Op.getOperand(0);
1353 if (Src.getValueType() == MVT::f32)
1354 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
1357 switch (Op.getValueType()) {
1358 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
1360 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
1363 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
1367 // Convert the FP value to an int value through memory.
1368 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
1369 if (Op.getValueType() == MVT::i32)
1370 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
1374 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1375 if (Op.getOperand(0).getValueType() == MVT::i64) {
1376 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
1377 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
1378 if (Op.getValueType() == MVT::f32)
1379 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1383 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
1384 "Unhandled SINT_TO_FP type in custom expander!");
1385 // Since we only generate this in 64-bit mode, we can take advantage of
1386 // 64-bit registers. In particular, sign extend the input value into the
1387 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
1388 // then lfd it and fcfid it.
1389 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
1390 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
1391 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
1393 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
1396 // STD the extended value into the stack slot.
1397 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
1398 DAG.getEntryNode(), Ext64, FIdx,
1399 DAG.getSrcValue(NULL));
1400 // Load the value as a double.
1401 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL));
1403 // FCFID it and return it.
1404 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
1405 if (Op.getValueType() == MVT::f32)
1406 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1410 static SDOperand LowerSHL(SDOperand Op, SelectionDAG &DAG,
1411 MVT::ValueType PtrVT) {
1412 assert(Op.getValueType() == MVT::i64 &&
1413 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
1414 // The generic code does a fine job expanding shift by a constant.
1415 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
1417 // Otherwise, expand into a bunch of logical ops. Note that these ops
1418 // depend on the PPC behavior for oversized shift amounts.
1419 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1420 DAG.getConstant(0, PtrVT));
1421 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1422 DAG.getConstant(1, PtrVT));
1423 SDOperand Amt = Op.getOperand(1);
1425 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1426 DAG.getConstant(32, MVT::i32), Amt);
1427 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
1428 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
1429 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1430 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1431 DAG.getConstant(-32U, MVT::i32));
1432 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
1433 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1434 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
1435 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
1438 static SDOperand LowerSRL(SDOperand Op, SelectionDAG &DAG,
1439 MVT::ValueType PtrVT) {
1440 assert(Op.getValueType() == MVT::i64 &&
1441 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
1442 // The generic code does a fine job expanding shift by a constant.
1443 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
1445 // Otherwise, expand into a bunch of logical ops. Note that these ops
1446 // depend on the PPC behavior for oversized shift amounts.
1447 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1448 DAG.getConstant(0, PtrVT));
1449 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1450 DAG.getConstant(1, PtrVT));
1451 SDOperand Amt = Op.getOperand(1);
1453 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1454 DAG.getConstant(32, MVT::i32), Amt);
1455 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1456 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1457 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1458 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1459 DAG.getConstant(-32U, MVT::i32));
1460 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
1461 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1462 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
1463 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
1466 static SDOperand LowerSRA(SDOperand Op, SelectionDAG &DAG,
1467 MVT::ValueType PtrVT) {
1468 assert(Op.getValueType() == MVT::i64 &&
1469 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
1470 // The generic code does a fine job expanding shift by a constant.
1471 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
1473 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
1474 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1475 DAG.getConstant(0, PtrVT));
1476 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1477 DAG.getConstant(1, PtrVT));
1478 SDOperand Amt = Op.getOperand(1);
1480 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1481 DAG.getConstant(32, MVT::i32), Amt);
1482 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1483 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1484 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1485 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1486 DAG.getConstant(-32U, MVT::i32));
1487 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
1488 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
1489 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
1490 Tmp4, Tmp6, ISD::SETLE);
1491 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
1494 //===----------------------------------------------------------------------===//
1495 // Vector related lowering.
1498 // If this is a vector of constants or undefs, get the bits. A bit in
1499 // UndefBits is set if the corresponding element of the vector is an
1500 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1501 // zero. Return true if this is not an array of constants, false if it is.
1503 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
1504 uint64_t UndefBits[2]) {
1505 // Start with zero'd results.
1506 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
1508 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
1509 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
1510 SDOperand OpVal = BV->getOperand(i);
1512 unsigned PartNo = i >= e/2; // In the upper 128 bits?
1513 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
1515 uint64_t EltBits = 0;
1516 if (OpVal.getOpcode() == ISD::UNDEF) {
1517 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
1518 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
1520 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1521 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
1522 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1523 assert(CN->getValueType(0) == MVT::f32 &&
1524 "Only one legal FP vector type!");
1525 EltBits = FloatToBits(CN->getValue());
1527 // Nonconstant element.
1531 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
1534 //printf("%llx %llx %llx %llx\n",
1535 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
1539 // If this is a splat (repetition) of a value across the whole vector, return
1540 // the smallest size that splats it. For example, "0x01010101010101..." is a
1541 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1542 // SplatSize = 1 byte.
1543 static bool isConstantSplat(const uint64_t Bits128[2],
1544 const uint64_t Undef128[2],
1545 unsigned &SplatBits, unsigned &SplatUndef,
1546 unsigned &SplatSize) {
1548 // Don't let undefs prevent splats from matching. See if the top 64-bits are
1549 // the same as the lower 64-bits, ignoring undefs.
1550 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
1551 return false; // Can't be a splat if two pieces don't match.
1553 uint64_t Bits64 = Bits128[0] | Bits128[1];
1554 uint64_t Undef64 = Undef128[0] & Undef128[1];
1556 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
1558 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
1559 return false; // Can't be a splat if two pieces don't match.
1561 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
1562 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
1564 // If the top 16-bits are different than the lower 16-bits, ignoring
1565 // undefs, we have an i32 splat.
1566 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
1568 SplatUndef = Undef32;
1573 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
1574 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
1576 // If the top 8-bits are different than the lower 8-bits, ignoring
1577 // undefs, we have an i16 splat.
1578 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
1580 SplatUndef = Undef16;
1585 // Otherwise, we have an 8-bit splat.
1586 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
1587 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
1592 /// BuildSplatI - Build a canonical splati of Val with an element size of
1593 /// SplatSize. Cast the result to VT.
1594 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
1595 SelectionDAG &DAG) {
1596 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
1598 // Force vspltis[hw] -1 to vspltisb -1.
1599 if (Val == -1) SplatSize = 1;
1601 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
1602 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
1604 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
1606 // Build a canonical splat for this value.
1607 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT));
1608 std::vector<SDOperand> Ops(MVT::getVectorNumElements(CanonicalVT), Elt);
1609 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops);
1610 return DAG.getNode(ISD::BIT_CONVERT, VT, Res);
1613 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
1614 /// specified intrinsic ID.
1615 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
1617 MVT::ValueType DestVT = MVT::Other) {
1618 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
1619 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1620 DAG.getConstant(IID, MVT::i32), LHS, RHS);
1623 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
1624 /// specified intrinsic ID.
1625 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
1626 SDOperand Op2, SelectionDAG &DAG,
1627 MVT::ValueType DestVT = MVT::Other) {
1628 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
1629 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1630 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
1634 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
1635 /// amount. The result has the specified value type.
1636 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
1637 MVT::ValueType VT, SelectionDAG &DAG) {
1638 // Force LHS/RHS to be the right type.
1639 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
1640 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
1642 std::vector<SDOperand> Ops;
1643 for (unsigned i = 0; i != 16; ++i)
1644 Ops.push_back(DAG.getConstant(i+Amt, MVT::i32));
1645 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
1646 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
1647 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
1650 // If this is a case we can't handle, return null and let the default
1651 // expansion code take care of it. If we CAN select this case, and if it
1652 // selects to a single instruction, return Op. Otherwise, if we can codegen
1653 // this case more efficiently than a constant pool load, lower it to the
1654 // sequence of ops that should be used.
1655 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
1656 // If this is a vector of constants or undefs, get the bits. A bit in
1657 // UndefBits is set if the corresponding element of the vector is an
1658 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1660 uint64_t VectorBits[2];
1661 uint64_t UndefBits[2];
1662 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
1663 return SDOperand(); // Not a constant vector.
1665 // If this is a splat (repetition) of a value across the whole vector, return
1666 // the smallest size that splats it. For example, "0x01010101010101..." is a
1667 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1668 // SplatSize = 1 byte.
1669 unsigned SplatBits, SplatUndef, SplatSize;
1670 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
1671 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
1673 // First, handle single instruction cases.
1676 if (SplatBits == 0) {
1677 // Canonicalize all zero vectors to be v4i32.
1678 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
1679 SDOperand Z = DAG.getConstant(0, MVT::i32);
1680 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
1681 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
1686 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
1687 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
1688 if (SextVal >= -16 && SextVal <= 15)
1689 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
1692 // Two instruction sequences.
1694 // If this value is in the range [-32,30] and is even, use:
1695 // tmp = VSPLTI[bhw], result = add tmp, tmp
1696 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
1697 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
1698 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
1701 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
1702 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
1704 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
1705 // Make -1 and vspltisw -1:
1706 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
1708 // Make the VSLW intrinsic, computing 0x8000_0000.
1709 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
1712 // xor by OnesV to invert it.
1713 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
1714 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
1717 // Check to see if this is a wide variety of vsplti*, binop self cases.
1718 unsigned SplatBitSize = SplatSize*8;
1719 static const char SplatCsts[] = {
1720 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
1721 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
1723 for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){
1724 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
1725 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
1726 int i = SplatCsts[idx];
1728 // Figure out what shift amount will be used by altivec if shifted by i in
1730 unsigned TypeShiftAmt = i & (SplatBitSize-1);
1732 // vsplti + shl self.
1733 if (SextVal == (i << (int)TypeShiftAmt)) {
1734 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1735 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1736 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
1737 Intrinsic::ppc_altivec_vslw
1739 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1742 // vsplti + srl self.
1743 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
1744 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1745 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1746 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
1747 Intrinsic::ppc_altivec_vsrw
1749 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1752 // vsplti + sra self.
1753 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
1754 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1755 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1756 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
1757 Intrinsic::ppc_altivec_vsraw
1759 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1762 // vsplti + rol self.
1763 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
1764 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
1765 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1766 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1767 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
1768 Intrinsic::ppc_altivec_vrlw
1770 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1773 // t = vsplti c, result = vsldoi t, t, 1
1774 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
1775 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1776 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
1778 // t = vsplti c, result = vsldoi t, t, 2
1779 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
1780 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1781 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
1783 // t = vsplti c, result = vsldoi t, t, 3
1784 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
1785 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1786 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
1790 // Three instruction sequences.
1792 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
1793 if (SextVal >= 0 && SextVal <= 31) {
1794 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, Op.getValueType(),DAG);
1795 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
1796 return DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
1798 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
1799 if (SextVal >= -31 && SextVal <= 0) {
1800 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, Op.getValueType(),DAG);
1801 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
1802 return DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
1809 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
1810 /// the specified operations to build the shuffle.
1811 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
1812 SDOperand RHS, SelectionDAG &DAG) {
1813 unsigned OpNum = (PFEntry >> 26) & 0x0F;
1814 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
1815 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
1818 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
1830 if (OpNum == OP_COPY) {
1831 if (LHSID == (1*9+2)*9+3) return LHS;
1832 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
1836 SDOperand OpLHS, OpRHS;
1837 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
1838 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
1840 unsigned ShufIdxs[16];
1842 default: assert(0 && "Unknown i32 permute!");
1844 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
1845 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
1846 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
1847 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
1850 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
1851 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
1852 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
1853 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
1856 for (unsigned i = 0; i != 16; ++i)
1857 ShufIdxs[i] = (i&3)+0;
1860 for (unsigned i = 0; i != 16; ++i)
1861 ShufIdxs[i] = (i&3)+4;
1864 for (unsigned i = 0; i != 16; ++i)
1865 ShufIdxs[i] = (i&3)+8;
1868 for (unsigned i = 0; i != 16; ++i)
1869 ShufIdxs[i] = (i&3)+12;
1872 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
1874 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
1876 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
1878 std::vector<SDOperand> Ops;
1879 for (unsigned i = 0; i != 16; ++i)
1880 Ops.push_back(DAG.getConstant(ShufIdxs[i], MVT::i32));
1882 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
1883 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
1886 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
1887 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
1888 /// return the code it can be lowered into. Worst case, it can always be
1889 /// lowered into a vperm.
1890 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
1891 SDOperand V1 = Op.getOperand(0);
1892 SDOperand V2 = Op.getOperand(1);
1893 SDOperand PermMask = Op.getOperand(2);
1895 // Cases that are handled by instructions that take permute immediates
1896 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
1897 // selected by the instruction selector.
1898 if (V2.getOpcode() == ISD::UNDEF) {
1899 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
1900 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
1901 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
1902 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
1903 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
1904 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
1905 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
1906 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
1907 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
1908 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
1909 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
1910 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
1915 // Altivec has a variety of "shuffle immediates" that take two vector inputs
1916 // and produce a fixed permutation. If any of these match, do not lower to
1918 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
1919 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
1920 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
1921 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
1922 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
1923 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
1924 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
1925 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
1926 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
1929 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
1930 // perfect shuffle table to emit an optimal matching sequence.
1931 unsigned PFIndexes[4];
1932 bool isFourElementShuffle = true;
1933 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
1934 unsigned EltNo = 8; // Start out undef.
1935 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
1936 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
1937 continue; // Undef, ignore it.
1939 unsigned ByteSource =
1940 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
1941 if ((ByteSource & 3) != j) {
1942 isFourElementShuffle = false;
1947 EltNo = ByteSource/4;
1948 } else if (EltNo != ByteSource/4) {
1949 isFourElementShuffle = false;
1953 PFIndexes[i] = EltNo;
1956 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
1957 // perfect shuffle vector to determine if it is cost effective to do this as
1958 // discrete instructions, or whether we should use a vperm.
1959 if (isFourElementShuffle) {
1960 // Compute the index in the perfect shuffle table.
1961 unsigned PFTableIndex =
1962 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
1964 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
1965 unsigned Cost = (PFEntry >> 30);
1967 // Determining when to avoid vperm is tricky. Many things affect the cost
1968 // of vperm, particularly how many times the perm mask needs to be computed.
1969 // For example, if the perm mask can be hoisted out of a loop or is already
1970 // used (perhaps because there are multiple permutes with the same shuffle
1971 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
1972 // the loop requires an extra register.
1974 // As a compromise, we only emit discrete instructions if the shuffle can be
1975 // generated in 3 or fewer operations. When we have loop information
1976 // available, if this block is within a loop, we should avoid using vperm
1977 // for 3-operation perms and use a constant pool load instead.
1979 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
1982 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
1983 // vector that will get spilled to the constant pool.
1984 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
1986 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
1987 // that it is in input element units, not in bytes. Convert now.
1988 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
1989 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
1991 std::vector<SDOperand> ResultMask;
1992 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
1994 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
1997 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
1999 for (unsigned j = 0; j != BytesPerElement; ++j)
2000 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
2004 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask);
2005 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
2008 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
2009 /// altivec comparison. If it is, return true and fill in Opc/isDot with
2010 /// information about the intrinsic.
2011 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
2013 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
2016 switch (IntrinsicID) {
2017 default: return false;
2018 // Comparison predicates.
2019 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
2020 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
2021 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
2022 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
2023 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
2024 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
2025 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
2026 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
2027 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
2028 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
2029 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
2030 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
2031 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
2033 // Normal Comparisons.
2034 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
2035 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
2036 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
2037 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
2038 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
2039 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
2040 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
2041 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
2042 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
2043 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
2044 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
2045 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
2046 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
2051 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
2052 /// lower, do it, otherwise return null.
2053 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
2054 // If this is a lowered altivec predicate compare, CompareOpc is set to the
2055 // opcode number of the comparison.
2058 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
2059 return SDOperand(); // Don't custom lower most intrinsics.
2061 // If this is a non-dot comparison, make the VCMP node and we are done.
2063 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
2064 Op.getOperand(1), Op.getOperand(2),
2065 DAG.getConstant(CompareOpc, MVT::i32));
2066 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
2069 // Create the PPCISD altivec 'dot' comparison node.
2070 std::vector<SDOperand> Ops;
2071 std::vector<MVT::ValueType> VTs;
2072 Ops.push_back(Op.getOperand(2)); // LHS
2073 Ops.push_back(Op.getOperand(3)); // RHS
2074 Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32));
2075 VTs.push_back(Op.getOperand(2).getValueType());
2076 VTs.push_back(MVT::Flag);
2077 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops);
2079 // Now that we have the comparison, emit a copy from the CR to a GPR.
2080 // This is flagged to the above dot comparison.
2081 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
2082 DAG.getRegister(PPC::CR6, MVT::i32),
2083 CompNode.getValue(1));
2085 // Unpack the result based on how the target uses it.
2086 unsigned BitNo; // Bit # of CR6.
2087 bool InvertBit; // Invert result?
2088 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
2089 default: // Can't happen, don't crash on invalid number though.
2090 case 0: // Return the value of the EQ bit of CR6.
2091 BitNo = 0; InvertBit = false;
2093 case 1: // Return the inverted value of the EQ bit of CR6.
2094 BitNo = 0; InvertBit = true;
2096 case 2: // Return the value of the LT bit of CR6.
2097 BitNo = 2; InvertBit = false;
2099 case 3: // Return the inverted value of the LT bit of CR6.
2100 BitNo = 2; InvertBit = true;
2104 // Shift the bit into the low position.
2105 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
2106 DAG.getConstant(8-(3-BitNo), MVT::i32));
2108 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
2109 DAG.getConstant(1, MVT::i32));
2111 // If we are supposed to, toggle the bit.
2113 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
2114 DAG.getConstant(1, MVT::i32));
2118 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2119 // Create a stack slot that is 16-byte aligned.
2120 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2121 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
2122 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
2124 // Store the input value into Value#0 of the stack slot.
2125 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
2126 Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
2128 return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL));
2131 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
2132 if (Op.getValueType() == MVT::v4i32) {
2133 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2135 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
2136 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
2138 SDOperand RHSSwap = // = vrlw RHS, 16
2139 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
2141 // Shrinkify inputs to v8i16.
2142 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
2143 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
2144 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
2146 // Low parts multiplied together, generating 32-bit results (we ignore the
2148 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
2149 LHS, RHS, DAG, MVT::v4i32);
2151 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
2152 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
2153 // Shift the high parts up 16 bits.
2154 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
2155 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
2156 } else if (Op.getValueType() == MVT::v8i16) {
2157 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2159 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
2161 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
2162 LHS, RHS, Zero, DAG);
2163 } else if (Op.getValueType() == MVT::v16i8) {
2164 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2166 // Multiply the even 8-bit parts, producing 16-bit sums.
2167 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
2168 LHS, RHS, DAG, MVT::v8i16);
2169 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
2171 // Multiply the odd 8-bit parts, producing 16-bit sums.
2172 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
2173 LHS, RHS, DAG, MVT::v8i16);
2174 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
2176 // Merge the results together.
2177 std::vector<SDOperand> Ops;
2178 for (unsigned i = 0; i != 8; ++i) {
2179 Ops.push_back(DAG.getConstant(2*i+1, MVT::i8));
2180 Ops.push_back(DAG.getConstant(2*i+1+16, MVT::i8));
2183 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
2184 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
2186 assert(0 && "Unknown mul to lower!");
2191 /// LowerOperation - Provide custom lowering hooks for some operations.
2193 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2194 switch (Op.getOpcode()) {
2195 default: assert(0 && "Wasn't expecting to be able to lower this!");
2196 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2197 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2198 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2199 case ISD::SETCC: return LowerSETCC(Op, DAG);
2200 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2201 case ISD::FORMAL_ARGUMENTS:
2202 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex);
2203 case ISD::CALL: return LowerCALL(Op, DAG);
2204 case ISD::RET: return LowerRET(Op, DAG);
2206 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2207 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
2208 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
2210 // Lower 64-bit shifts.
2211 case ISD::SHL: return LowerSHL(Op, DAG, getPointerTy());
2212 case ISD::SRL: return LowerSRL(Op, DAG, getPointerTy());
2213 case ISD::SRA: return LowerSRA(Op, DAG, getPointerTy());
2215 // Vector-related lowering.
2216 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2217 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2218 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2219 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2220 case ISD::MUL: return LowerMUL(Op, DAG);
2225 //===----------------------------------------------------------------------===//
2226 // Other Lowering Code
2227 //===----------------------------------------------------------------------===//
2230 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2231 MachineBasicBlock *BB) {
2232 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
2233 MI->getOpcode() == PPC::SELECT_CC_I8 ||
2234 MI->getOpcode() == PPC::SELECT_CC_F4 ||
2235 MI->getOpcode() == PPC::SELECT_CC_F8 ||
2236 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
2237 "Unexpected instr type to insert");
2239 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2240 // control-flow pattern. The incoming instruction knows the destination vreg
2241 // to set, the condition code register to branch on, the true/false values to
2242 // select between, and a branch opcode to use.
2243 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2244 ilist<MachineBasicBlock>::iterator It = BB;
2250 // cmpTY ccX, r1, r2
2252 // fallthrough --> copy0MBB
2253 MachineBasicBlock *thisMBB = BB;
2254 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2255 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2256 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
2257 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
2258 MachineFunction *F = BB->getParent();
2259 F->getBasicBlockList().insert(It, copy0MBB);
2260 F->getBasicBlockList().insert(It, sinkMBB);
2261 // Update machine-CFG edges by first adding all successors of the current
2262 // block to the new block which will contain the Phi node for the select.
2263 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2264 e = BB->succ_end(); i != e; ++i)
2265 sinkMBB->addSuccessor(*i);
2266 // Next, remove all successors of the current block, and add the true
2267 // and fallthrough blocks as its successors.
2268 while(!BB->succ_empty())
2269 BB->removeSuccessor(BB->succ_begin());
2270 BB->addSuccessor(copy0MBB);
2271 BB->addSuccessor(sinkMBB);
2274 // %FalseValue = ...
2275 // # fallthrough to sinkMBB
2278 // Update machine-CFG edges
2279 BB->addSuccessor(sinkMBB);
2282 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2285 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
2286 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
2287 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2289 delete MI; // The pseudo instruction is gone now.
2293 //===----------------------------------------------------------------------===//
2294 // Target Optimization Hooks
2295 //===----------------------------------------------------------------------===//
2297 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
2298 DAGCombinerInfo &DCI) const {
2299 TargetMachine &TM = getTargetMachine();
2300 SelectionDAG &DAG = DCI.DAG;
2301 switch (N->getOpcode()) {
2303 case ISD::SINT_TO_FP:
2304 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
2305 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
2306 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
2307 // We allow the src/dst to be either f32/f64, but the intermediate
2308 // type must be i64.
2309 if (N->getOperand(0).getValueType() == MVT::i64) {
2310 SDOperand Val = N->getOperand(0).getOperand(0);
2311 if (Val.getValueType() == MVT::f32) {
2312 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2313 DCI.AddToWorklist(Val.Val);
2316 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
2317 DCI.AddToWorklist(Val.Val);
2318 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
2319 DCI.AddToWorklist(Val.Val);
2320 if (N->getValueType(0) == MVT::f32) {
2321 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
2322 DCI.AddToWorklist(Val.Val);
2325 } else if (N->getOperand(0).getValueType() == MVT::i32) {
2326 // If the intermediate type is i32, we can avoid the load/store here
2333 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
2334 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
2335 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
2336 N->getOperand(1).getValueType() == MVT::i32) {
2337 SDOperand Val = N->getOperand(1).getOperand(0);
2338 if (Val.getValueType() == MVT::f32) {
2339 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2340 DCI.AddToWorklist(Val.Val);
2342 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
2343 DCI.AddToWorklist(Val.Val);
2345 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
2346 N->getOperand(2), N->getOperand(3));
2347 DCI.AddToWorklist(Val.Val);
2351 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
2352 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
2353 N->getOperand(1).Val->hasOneUse() &&
2354 (N->getOperand(1).getValueType() == MVT::i32 ||
2355 N->getOperand(1).getValueType() == MVT::i16)) {
2356 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
2357 // Do an any-extend to 32-bits if this is a half-word input.
2358 if (BSwapOp.getValueType() == MVT::i16)
2359 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
2361 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
2362 N->getOperand(2), N->getOperand(3),
2363 DAG.getValueType(N->getOperand(1).getValueType()));
2367 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
2368 if (N->getOperand(0).getOpcode() == ISD::LOAD &&
2369 N->getOperand(0).hasOneUse() &&
2370 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
2371 SDOperand Load = N->getOperand(0);
2372 // Create the byte-swapping load.
2373 std::vector<MVT::ValueType> VTs;
2374 VTs.push_back(MVT::i32);
2375 VTs.push_back(MVT::Other);
2376 std::vector<SDOperand> Ops;
2377 Ops.push_back(Load.getOperand(0)); // Chain
2378 Ops.push_back(Load.getOperand(1)); // Ptr
2379 Ops.push_back(Load.getOperand(2)); // SrcValue
2380 Ops.push_back(DAG.getValueType(N->getValueType(0))); // VT
2381 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops);
2383 // If this is an i16 load, insert the truncate.
2384 SDOperand ResVal = BSLoad;
2385 if (N->getValueType(0) == MVT::i16)
2386 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
2388 // First, combine the bswap away. This makes the value produced by the
2390 DCI.CombineTo(N, ResVal);
2392 // Next, combine the load away, we give it a bogus result value but a real
2393 // chain result. The result value is dead because the bswap is dead.
2394 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
2396 // Return N so it doesn't get rechecked!
2397 return SDOperand(N, 0);
2401 case PPCISD::VCMP: {
2402 // If a VCMPo node already exists with exactly the same operands as this
2403 // node, use its result instead of this node (VCMPo computes both a CR6 and
2404 // a normal output).
2406 if (!N->getOperand(0).hasOneUse() &&
2407 !N->getOperand(1).hasOneUse() &&
2408 !N->getOperand(2).hasOneUse()) {
2410 // Scan all of the users of the LHS, looking for VCMPo's that match.
2411 SDNode *VCMPoNode = 0;
2413 SDNode *LHSN = N->getOperand(0).Val;
2414 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
2416 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
2417 (*UI)->getOperand(1) == N->getOperand(1) &&
2418 (*UI)->getOperand(2) == N->getOperand(2) &&
2419 (*UI)->getOperand(0) == N->getOperand(0)) {
2424 // If there is no VCMPo node, or if the flag value has a single use, don't
2426 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
2429 // Look at the (necessarily single) use of the flag value. If it has a
2430 // chain, this transformation is more complex. Note that multiple things
2431 // could use the value result, which we should ignore.
2432 SDNode *FlagUser = 0;
2433 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
2434 FlagUser == 0; ++UI) {
2435 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
2437 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2438 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
2445 // If the user is a MFCR instruction, we know this is safe. Otherwise we
2446 // give up for right now.
2447 if (FlagUser->getOpcode() == PPCISD::MFCR)
2448 return SDOperand(VCMPoNode, 0);
2453 // If this is a branch on an altivec predicate comparison, lower this so
2454 // that we don't have to do a MFCR: instead, branch directly on CR6. This
2455 // lowering is done pre-legalize, because the legalizer lowers the predicate
2456 // compare down to code that is difficult to reassemble.
2457 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
2458 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
2462 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2463 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
2464 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
2465 assert(isDot && "Can't compare against a vector result!");
2467 // If this is a comparison against something other than 0/1, then we know
2468 // that the condition is never/always true.
2469 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
2470 if (Val != 0 && Val != 1) {
2471 if (CC == ISD::SETEQ) // Cond never true, remove branch.
2472 return N->getOperand(0);
2473 // Always !=, turn it into an unconditional branch.
2474 return DAG.getNode(ISD::BR, MVT::Other,
2475 N->getOperand(0), N->getOperand(4));
2478 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
2480 // Create the PPCISD altivec 'dot' comparison node.
2481 std::vector<SDOperand> Ops;
2482 std::vector<MVT::ValueType> VTs;
2483 Ops.push_back(LHS.getOperand(2)); // LHS of compare
2484 Ops.push_back(LHS.getOperand(3)); // RHS of compare
2485 Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32));
2486 VTs.push_back(LHS.getOperand(2).getValueType());
2487 VTs.push_back(MVT::Flag);
2488 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops);
2490 // Unpack the result based on how the target uses it.
2492 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
2493 default: // Can't happen, don't crash on invalid number though.
2494 case 0: // Branch on the value of the EQ bit of CR6.
2495 CompOpc = BranchOnWhenPredTrue ? PPC::BEQ : PPC::BNE;
2497 case 1: // Branch on the inverted value of the EQ bit of CR6.
2498 CompOpc = BranchOnWhenPredTrue ? PPC::BNE : PPC::BEQ;
2500 case 2: // Branch on the value of the LT bit of CR6.
2501 CompOpc = BranchOnWhenPredTrue ? PPC::BLT : PPC::BGE;
2503 case 3: // Branch on the inverted value of the LT bit of CR6.
2504 CompOpc = BranchOnWhenPredTrue ? PPC::BGE : PPC::BLT;
2508 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
2509 DAG.getRegister(PPC::CR6, MVT::i32),
2510 DAG.getConstant(CompOpc, MVT::i32),
2511 N->getOperand(4), CompNode.getValue(1));
2520 //===----------------------------------------------------------------------===//
2521 // Inline Assembly Support
2522 //===----------------------------------------------------------------------===//
2524 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
2526 uint64_t &KnownZero,
2528 unsigned Depth) const {
2531 switch (Op.getOpcode()) {
2533 case PPCISD::LBRX: {
2534 // lhbrx is known to have the top bits cleared out.
2535 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
2536 KnownZero = 0xFFFF0000;
2539 case ISD::INTRINSIC_WO_CHAIN: {
2540 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
2542 case Intrinsic::ppc_altivec_vcmpbfp_p:
2543 case Intrinsic::ppc_altivec_vcmpeqfp_p:
2544 case Intrinsic::ppc_altivec_vcmpequb_p:
2545 case Intrinsic::ppc_altivec_vcmpequh_p:
2546 case Intrinsic::ppc_altivec_vcmpequw_p:
2547 case Intrinsic::ppc_altivec_vcmpgefp_p:
2548 case Intrinsic::ppc_altivec_vcmpgtfp_p:
2549 case Intrinsic::ppc_altivec_vcmpgtsb_p:
2550 case Intrinsic::ppc_altivec_vcmpgtsh_p:
2551 case Intrinsic::ppc_altivec_vcmpgtsw_p:
2552 case Intrinsic::ppc_altivec_vcmpgtub_p:
2553 case Intrinsic::ppc_altivec_vcmpgtuh_p:
2554 case Intrinsic::ppc_altivec_vcmpgtuw_p:
2555 KnownZero = ~1U; // All bits but the low one are known to be zero.
2563 /// getConstraintType - Given a constraint letter, return the type of
2564 /// constraint it is for this target.
2565 PPCTargetLowering::ConstraintType
2566 PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
2567 switch (ConstraintLetter) {
2574 return C_RegisterClass;
2576 return TargetLowering::getConstraintType(ConstraintLetter);
2580 std::vector<unsigned> PPCTargetLowering::
2581 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2582 MVT::ValueType VT) const {
2583 if (Constraint.size() == 1) {
2584 switch (Constraint[0]) { // GCC RS6000 Constraint Letters
2585 default: break; // Unknown constriant letter
2587 return make_vector<unsigned>(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 ,
2588 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
2589 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
2590 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
2591 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
2592 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
2593 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
2594 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
2597 return make_vector<unsigned>(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 ,
2598 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
2599 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
2600 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
2601 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
2602 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
2603 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
2604 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
2607 return make_vector<unsigned>(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 ,
2608 PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 ,
2609 PPC::F8 , PPC::F9 , PPC::F10, PPC::F11,
2610 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
2611 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
2612 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
2613 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
2614 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
2617 return make_vector<unsigned>(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 ,
2618 PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
2619 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11,
2620 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
2621 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
2622 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
2623 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
2624 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
2627 return make_vector<unsigned>(PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
2628 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7,
2633 return std::vector<unsigned>();
2636 // isOperandValidForConstraint
2637 bool PPCTargetLowering::
2638 isOperandValidForConstraint(SDOperand Op, char Letter) {
2649 if (!isa<ConstantSDNode>(Op)) return false; // Must be an immediate.
2650 unsigned Value = cast<ConstantSDNode>(Op)->getValue();
2652 default: assert(0 && "Unknown constraint letter!");
2653 case 'I': // "I" is a signed 16-bit constant.
2654 return (short)Value == (int)Value;
2655 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
2656 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
2657 return (short)Value == 0;
2658 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
2659 return (Value >> 16) == 0;
2660 case 'M': // "M" is a constant that is greater than 31.
2662 case 'N': // "N" is a positive constant that is an exact power of two.
2663 return (int)Value > 0 && isPowerOf2_32(Value);
2664 case 'O': // "O" is the constant zero.
2666 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
2667 return (short)-Value == (int)-Value;
2673 // Handle standard constraint letters.
2674 return TargetLowering::isOperandValidForConstraint(Op, Letter);
2677 /// isLegalAddressImmediate - Return true if the integer value can be used
2678 /// as the offset of the target addressing mode.
2679 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const {
2680 // PPC allows a sign-extended 16-bit immediate field.
2681 return (V > -(1 << 16) && V < (1 << 16)-1);