1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
45 // FIXME: Remove this once soft-float is supported.
46 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
47 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
49 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
50 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
52 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
53 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
55 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
56 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
58 // FIXME: Remove this once the bug has been fixed!
59 extern cl::opt<bool> ANDIGlueBug;
61 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
62 const PPCSubtarget &STI)
63 : TargetLowering(TM), Subtarget(STI) {
64 // Use _setjmp/_longjmp instead of setjmp/longjmp.
65 setUseUnderscoreSetJmp(true);
66 setUseUnderscoreLongJmp(true);
68 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
69 // arguments are at least 4/8 bytes aligned.
70 bool isPPC64 = Subtarget.isPPC64();
71 setMinStackArgumentAlignment(isPPC64 ? 8:4);
73 // Set up the register classes.
74 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
75 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
76 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
78 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
79 for (MVT VT : MVT::integer_valuetypes()) {
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
84 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
86 // PowerPC has pre-inc load and store's.
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
102 if (Subtarget.useCRBits()) {
103 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
105 if (isPPC64 || Subtarget.hasFPCVT()) {
106 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
107 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
108 isPPC64 ? MVT::i64 : MVT::i32);
109 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
110 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
111 isPPC64 ? MVT::i64 : MVT::i32);
113 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
114 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
117 // PowerPC does not support direct load / store of condition registers
118 setOperationAction(ISD::LOAD, MVT::i1, Custom);
119 setOperationAction(ISD::STORE, MVT::i1, Custom);
121 // FIXME: Remove this once the ANDI glue bug is fixed:
123 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
125 for (MVT VT : MVT::integer_valuetypes()) {
126 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
127 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
128 setTruncStoreAction(VT, MVT::i1, Expand);
131 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
134 // This is used in the ppcf128->int sequence. Note it has different semantics
135 // from FP_ROUND: that rounds to nearest, this rounds to zero.
136 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
138 // We do not currently implement these libm ops for PowerPC.
139 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
144 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
146 // PowerPC has no SREM/UREM instructions
147 setOperationAction(ISD::SREM, MVT::i32, Expand);
148 setOperationAction(ISD::UREM, MVT::i32, Expand);
149 setOperationAction(ISD::SREM, MVT::i64, Expand);
150 setOperationAction(ISD::UREM, MVT::i64, Expand);
152 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
153 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
155 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
157 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
159 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
160 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
162 // We don't support sin/cos/sqrt/fmod/pow
163 setOperationAction(ISD::FSIN , MVT::f64, Expand);
164 setOperationAction(ISD::FCOS , MVT::f64, Expand);
165 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
166 setOperationAction(ISD::FREM , MVT::f64, Expand);
167 setOperationAction(ISD::FPOW , MVT::f64, Expand);
168 setOperationAction(ISD::FMA , MVT::f64, Legal);
169 setOperationAction(ISD::FSIN , MVT::f32, Expand);
170 setOperationAction(ISD::FCOS , MVT::f32, Expand);
171 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
172 setOperationAction(ISD::FREM , MVT::f32, Expand);
173 setOperationAction(ISD::FPOW , MVT::f32, Expand);
174 setOperationAction(ISD::FMA , MVT::f32, Legal);
176 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
178 // If we're enabling GP optimizations, use hardware square root
179 if (!Subtarget.hasFSQRT() &&
180 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
182 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
184 if (!Subtarget.hasFSQRT() &&
185 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
186 Subtarget.hasFRES()))
187 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
189 if (Subtarget.hasFCPSGN()) {
190 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
191 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
194 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
197 if (Subtarget.hasFPRND()) {
198 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
199 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
200 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
201 setOperationAction(ISD::FROUND, MVT::f64, Legal);
203 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
204 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
205 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
206 setOperationAction(ISD::FROUND, MVT::f32, Legal);
209 // PowerPC does not have BSWAP, CTPOP or CTTZ
210 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
212 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
214 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
216 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
217 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
219 if (Subtarget.hasPOPCNTD()) {
220 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
221 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
223 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
224 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
227 // PowerPC does not have ROTR
228 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
229 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
231 if (!Subtarget.useCRBits()) {
232 // PowerPC does not have Select
233 setOperationAction(ISD::SELECT, MVT::i32, Expand);
234 setOperationAction(ISD::SELECT, MVT::i64, Expand);
235 setOperationAction(ISD::SELECT, MVT::f32, Expand);
236 setOperationAction(ISD::SELECT, MVT::f64, Expand);
239 // PowerPC wants to turn select_cc of FP into fsel when possible.
240 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
241 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
243 // PowerPC wants to optimize integer setcc a bit
244 if (!Subtarget.useCRBits())
245 setOperationAction(ISD::SETCC, MVT::i32, Custom);
247 // PowerPC does not have BRCOND which requires SetCC
248 if (!Subtarget.useCRBits())
249 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
251 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
253 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
254 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
256 // PowerPC does not have [U|S]INT_TO_FP
257 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
258 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
262 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
263 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
265 // We cannot sextinreg(i1). Expand to shifts.
266 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
268 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
269 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
270 // support continuation, user-level threading, and etc.. As a result, no
271 // other SjLj exception interfaces are implemented and please don't build
272 // your own exception handling based on them.
273 // LLVM/Clang supports zero-cost DWARF exception handling.
274 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
275 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
277 // We want to legalize GlobalAddress and ConstantPool nodes into the
278 // appropriate instructions to materialize the address.
279 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
280 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
281 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
282 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
283 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
284 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
285 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
286 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
287 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
288 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
291 setOperationAction(ISD::TRAP, MVT::Other, Legal);
293 // TRAMPOLINE is custom lowered.
294 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
295 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
297 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
298 setOperationAction(ISD::VASTART , MVT::Other, Custom);
300 if (Subtarget.isSVR4ABI()) {
302 // VAARG always uses double-word chunks, so promote anything smaller.
303 setOperationAction(ISD::VAARG, MVT::i1, Promote);
304 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
305 setOperationAction(ISD::VAARG, MVT::i8, Promote);
306 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
307 setOperationAction(ISD::VAARG, MVT::i16, Promote);
308 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
309 setOperationAction(ISD::VAARG, MVT::i32, Promote);
310 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
311 setOperationAction(ISD::VAARG, MVT::Other, Expand);
313 // VAARG is custom lowered with the 32-bit SVR4 ABI.
314 setOperationAction(ISD::VAARG, MVT::Other, Custom);
315 setOperationAction(ISD::VAARG, MVT::i64, Custom);
318 setOperationAction(ISD::VAARG, MVT::Other, Expand);
320 if (Subtarget.isSVR4ABI() && !isPPC64)
321 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
322 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
324 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
326 // Use the default implementation.
327 setOperationAction(ISD::VAEND , MVT::Other, Expand);
328 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
329 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
331 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
333 // We want to custom lower some of our intrinsics.
334 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
336 // To handle counter-based loop conditions.
337 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
339 // Comparisons that require checking two conditions.
340 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
341 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
343 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
345 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
347 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
349 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
351 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
353 if (Subtarget.has64BitSupport()) {
354 // They also have instructions for converting between i64 and fp.
355 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
356 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
357 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
358 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
359 // This is just the low 32 bits of a (signed) fp->i64 conversion.
360 // We cannot do this with Promote because i64 is not a legal type.
361 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
363 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
364 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
366 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
367 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
370 // With the instructions enabled under FPCVT, we can do everything.
371 if (Subtarget.hasFPCVT()) {
372 if (Subtarget.has64BitSupport()) {
373 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
374 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
375 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
376 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
379 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
380 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
381 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
382 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
385 if (Subtarget.use64BitRegs()) {
386 // 64-bit PowerPC implementations can support i64 types directly
387 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
388 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
389 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
390 // 64-bit PowerPC wants to expand i128 shifts itself.
391 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
393 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
395 // 32-bit PowerPC wants to expand i64 shifts itself.
396 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
398 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
401 if (Subtarget.hasAltivec()) {
402 // First set operation action for all vector types to expand. Then we
403 // will selectively turn on ones that can be effectively codegen'd.
404 for (MVT VT : MVT::vector_valuetypes()) {
405 // add/sub are legal for all supported vector VT's.
406 setOperationAction(ISD::ADD, VT, Legal);
407 setOperationAction(ISD::SUB, VT, Legal);
409 // Vector instructions introduced in P8
410 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
411 setOperationAction(ISD::CTPOP, VT, Legal);
412 setOperationAction(ISD::CTLZ, VT, Legal);
415 setOperationAction(ISD::CTPOP, VT, Expand);
416 setOperationAction(ISD::CTLZ, VT, Expand);
419 // We promote all shuffles to v16i8.
420 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
421 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
423 // We promote all non-typed operations to v4i32.
424 setOperationAction(ISD::AND , VT, Promote);
425 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
426 setOperationAction(ISD::OR , VT, Promote);
427 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
428 setOperationAction(ISD::XOR , VT, Promote);
429 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
430 setOperationAction(ISD::LOAD , VT, Promote);
431 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
432 setOperationAction(ISD::SELECT, VT, Promote);
433 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
434 setOperationAction(ISD::SELECT_CC, VT, Promote);
435 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
436 setOperationAction(ISD::STORE, VT, Promote);
437 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
439 // No other operations are legal.
440 setOperationAction(ISD::MUL , VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::SREM, VT, Expand);
443 setOperationAction(ISD::UDIV, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
445 setOperationAction(ISD::FDIV, VT, Expand);
446 setOperationAction(ISD::FREM, VT, Expand);
447 setOperationAction(ISD::FNEG, VT, Expand);
448 setOperationAction(ISD::FSQRT, VT, Expand);
449 setOperationAction(ISD::FLOG, VT, Expand);
450 setOperationAction(ISD::FLOG10, VT, Expand);
451 setOperationAction(ISD::FLOG2, VT, Expand);
452 setOperationAction(ISD::FEXP, VT, Expand);
453 setOperationAction(ISD::FEXP2, VT, Expand);
454 setOperationAction(ISD::FSIN, VT, Expand);
455 setOperationAction(ISD::FCOS, VT, Expand);
456 setOperationAction(ISD::FABS, VT, Expand);
457 setOperationAction(ISD::FPOWI, VT, Expand);
458 setOperationAction(ISD::FFLOOR, VT, Expand);
459 setOperationAction(ISD::FCEIL, VT, Expand);
460 setOperationAction(ISD::FTRUNC, VT, Expand);
461 setOperationAction(ISD::FRINT, VT, Expand);
462 setOperationAction(ISD::FNEARBYINT, VT, Expand);
463 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
464 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
465 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
466 setOperationAction(ISD::MULHU, VT, Expand);
467 setOperationAction(ISD::MULHS, VT, Expand);
468 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
469 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
470 setOperationAction(ISD::UDIVREM, VT, Expand);
471 setOperationAction(ISD::SDIVREM, VT, Expand);
472 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
473 setOperationAction(ISD::FPOW, VT, Expand);
474 setOperationAction(ISD::BSWAP, VT, Expand);
475 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
476 setOperationAction(ISD::CTTZ, VT, Expand);
477 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
478 setOperationAction(ISD::VSELECT, VT, Expand);
479 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
481 for (MVT InnerVT : MVT::vector_valuetypes()) {
482 setTruncStoreAction(VT, InnerVT, Expand);
483 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
484 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
485 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
489 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
490 // with merges, splats, etc.
491 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
493 setOperationAction(ISD::AND , MVT::v4i32, Legal);
494 setOperationAction(ISD::OR , MVT::v4i32, Legal);
495 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
496 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
497 setOperationAction(ISD::SELECT, MVT::v4i32,
498 Subtarget.useCRBits() ? Legal : Expand);
499 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
500 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
501 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
502 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
503 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
504 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
505 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
506 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
507 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
509 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
510 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
511 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
512 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
514 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
515 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
517 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
518 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
519 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
522 if (Subtarget.hasP8Altivec())
523 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
525 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
527 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
528 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
530 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
531 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
533 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
534 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
535 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
536 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
538 // Altivec does not contain unordered floating-point compare instructions
539 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
540 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
541 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
542 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
544 if (Subtarget.hasVSX()) {
545 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
546 if (Subtarget.hasP8Vector())
547 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
548 if (Subtarget.hasDirectMove()) {
549 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
550 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
551 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
552 // FIXME: this is causing bootstrap failures, disable temporarily
553 //setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
555 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
557 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
558 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
559 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
560 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
561 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
563 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
565 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
566 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
568 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
569 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
571 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
572 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
573 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
574 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
575 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
577 // Share the Altivec comparison restrictions.
578 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
579 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
580 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
581 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
583 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
584 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
586 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
588 if (Subtarget.hasP8Vector())
589 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
591 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
593 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
594 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
595 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
597 if (Subtarget.hasP8Altivec()) {
598 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
599 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
600 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
602 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
605 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
606 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
607 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
609 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
611 // VSX v2i64 only supports non-arithmetic operations.
612 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
613 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
616 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
617 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
618 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
619 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
621 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
623 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
624 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
625 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
626 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
628 // Vector operation legalization checks the result type of
629 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
630 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
631 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
632 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
633 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
635 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
638 if (Subtarget.hasP8Altivec()) {
639 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
640 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
644 if (Subtarget.hasQPX()) {
645 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
646 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
647 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
648 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
650 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
651 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand);
653 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
654 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
656 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
657 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
659 if (!Subtarget.useCRBits())
660 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
661 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
663 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);
664 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
665 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
666 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
667 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
668 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
669 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
671 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
672 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
674 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
675 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
676 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
678 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
679 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
680 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
681 setOperationAction(ISD::FCOS , MVT::v4f64, Expand);
682 setOperationAction(ISD::FPOWI , MVT::v4f64, Expand);
683 setOperationAction(ISD::FPOW , MVT::v4f64, Expand);
684 setOperationAction(ISD::FLOG , MVT::v4f64, Expand);
685 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
686 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand);
687 setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
688 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
690 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
691 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
693 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
694 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
696 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
698 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
699 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
700 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
701 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
703 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
704 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
706 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
707 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
709 if (!Subtarget.useCRBits())
710 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
711 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
713 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
714 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
715 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
716 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
717 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
718 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
719 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
721 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
722 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
724 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
725 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
726 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
727 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
728 setOperationAction(ISD::FPOWI , MVT::v4f32, Expand);
729 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
730 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
731 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
732 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
733 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
734 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
736 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
737 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
739 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
740 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
742 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
744 setOperationAction(ISD::AND , MVT::v4i1, Legal);
745 setOperationAction(ISD::OR , MVT::v4i1, Legal);
746 setOperationAction(ISD::XOR , MVT::v4i1, Legal);
748 if (!Subtarget.useCRBits())
749 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
750 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
752 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
753 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
755 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);
756 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
757 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
758 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand);
759 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
760 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
761 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
763 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
764 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
766 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
768 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
769 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
770 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
771 setOperationAction(ISD::FROUND, MVT::v4f64, Legal);
773 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
774 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
775 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
776 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
778 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
779 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
781 // These need to set FE_INEXACT, and so cannot be vectorized here.
782 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
783 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
785 if (TM.Options.UnsafeFPMath) {
786 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
787 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
789 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
790 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
792 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
793 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
795 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
796 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
800 if (Subtarget.has64BitSupport())
801 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
803 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
806 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
807 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
810 setBooleanContents(ZeroOrOneBooleanContent);
812 if (Subtarget.hasAltivec()) {
813 // Altivec instructions set fields to all zeros or all ones.
814 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
818 // These libcalls are not available in 32-bit.
819 setLibcallName(RTLIB::SHL_I128, nullptr);
820 setLibcallName(RTLIB::SRL_I128, nullptr);
821 setLibcallName(RTLIB::SRA_I128, nullptr);
825 setStackPointerRegisterToSaveRestore(PPC::X1);
826 setExceptionPointerRegister(PPC::X3);
827 setExceptionSelectorRegister(PPC::X4);
829 setStackPointerRegisterToSaveRestore(PPC::R1);
830 setExceptionPointerRegister(PPC::R3);
831 setExceptionSelectorRegister(PPC::R4);
834 // We have target-specific dag combine patterns for the following nodes:
835 setTargetDAGCombine(ISD::SINT_TO_FP);
836 if (Subtarget.hasFPCVT())
837 setTargetDAGCombine(ISD::UINT_TO_FP);
838 setTargetDAGCombine(ISD::LOAD);
839 setTargetDAGCombine(ISD::STORE);
840 setTargetDAGCombine(ISD::BR_CC);
841 if (Subtarget.useCRBits())
842 setTargetDAGCombine(ISD::BRCOND);
843 setTargetDAGCombine(ISD::BSWAP);
844 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
845 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
846 setTargetDAGCombine(ISD::INTRINSIC_VOID);
848 setTargetDAGCombine(ISD::SIGN_EXTEND);
849 setTargetDAGCombine(ISD::ZERO_EXTEND);
850 setTargetDAGCombine(ISD::ANY_EXTEND);
852 if (Subtarget.useCRBits()) {
853 setTargetDAGCombine(ISD::TRUNCATE);
854 setTargetDAGCombine(ISD::SETCC);
855 setTargetDAGCombine(ISD::SELECT_CC);
858 // Use reciprocal estimates.
859 if (TM.Options.UnsafeFPMath) {
860 setTargetDAGCombine(ISD::FDIV);
861 setTargetDAGCombine(ISD::FSQRT);
864 // Darwin long double math library functions have $LDBL128 appended.
865 if (Subtarget.isDarwin()) {
866 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
867 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
868 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
869 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
870 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
871 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
872 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
873 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
874 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
875 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
878 // With 32 condition bits, we don't need to sink (and duplicate) compares
879 // aggressively in CodeGenPrep.
880 if (Subtarget.useCRBits()) {
881 setHasMultipleConditionRegisters();
882 setJumpIsExpensive();
885 setMinFunctionAlignment(2);
886 if (Subtarget.isDarwin())
887 setPrefFunctionAlignment(4);
889 switch (Subtarget.getDarwinDirective()) {
893 case PPC::DIR_E500mc:
902 setPrefFunctionAlignment(4);
903 setPrefLoopAlignment(4);
907 setInsertFencesForAtomic(true);
909 if (Subtarget.enableMachineScheduler())
910 setSchedulingPreference(Sched::Source);
912 setSchedulingPreference(Sched::Hybrid);
914 computeRegisterProperties(STI.getRegisterInfo());
916 // The Freescale cores do better with aggressive inlining of memcpy and
917 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
918 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
919 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
920 MaxStoresPerMemset = 32;
921 MaxStoresPerMemsetOptSize = 16;
922 MaxStoresPerMemcpy = 32;
923 MaxStoresPerMemcpyOptSize = 8;
924 MaxStoresPerMemmove = 32;
925 MaxStoresPerMemmoveOptSize = 8;
926 } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) {
927 // The A2 also benefits from (very) aggressive inlining of memcpy and
928 // friends. The overhead of a the function call, even when warm, can be
929 // over one hundred cycles.
930 MaxStoresPerMemset = 128;
931 MaxStoresPerMemcpy = 128;
932 MaxStoresPerMemmove = 128;
936 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
937 /// the desired ByVal argument alignment.
938 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
939 unsigned MaxMaxAlign) {
940 if (MaxAlign == MaxMaxAlign)
942 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
943 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
945 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
947 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
948 unsigned EltAlign = 0;
949 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
950 if (EltAlign > MaxAlign)
952 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
953 for (auto *EltTy : STy->elements()) {
954 unsigned EltAlign = 0;
955 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
956 if (EltAlign > MaxAlign)
958 if (MaxAlign == MaxMaxAlign)
964 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
965 /// function arguments in the caller parameter area.
966 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
967 const DataLayout &DL) const {
968 // Darwin passes everything on 4 byte boundary.
969 if (Subtarget.isDarwin())
972 // 16byte and wider vectors are passed on 16byte boundary.
973 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
974 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
975 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
976 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
980 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
981 switch ((PPCISD::NodeType)Opcode) {
982 case PPCISD::FIRST_NUMBER: break;
983 case PPCISD::FSEL: return "PPCISD::FSEL";
984 case PPCISD::FCFID: return "PPCISD::FCFID";
985 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
986 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
987 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
988 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
989 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
990 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
991 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
992 case PPCISD::FRE: return "PPCISD::FRE";
993 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
994 case PPCISD::STFIWX: return "PPCISD::STFIWX";
995 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
996 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
997 case PPCISD::VPERM: return "PPCISD::VPERM";
998 case PPCISD::CMPB: return "PPCISD::CMPB";
999 case PPCISD::Hi: return "PPCISD::Hi";
1000 case PPCISD::Lo: return "PPCISD::Lo";
1001 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1002 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1003 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1004 case PPCISD::SRL: return "PPCISD::SRL";
1005 case PPCISD::SRA: return "PPCISD::SRA";
1006 case PPCISD::SHL: return "PPCISD::SHL";
1007 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1008 case PPCISD::CALL: return "PPCISD::CALL";
1009 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1010 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1011 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1012 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1013 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1014 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1015 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1016 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1017 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1018 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1019 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1020 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1021 case PPCISD::ANDIo_1_EQ_BIT: return "PPCISD::ANDIo_1_EQ_BIT";
1022 case PPCISD::ANDIo_1_GT_BIT: return "PPCISD::ANDIo_1_GT_BIT";
1023 case PPCISD::VCMP: return "PPCISD::VCMP";
1024 case PPCISD::VCMPo: return "PPCISD::VCMPo";
1025 case PPCISD::LBRX: return "PPCISD::LBRX";
1026 case PPCISD::STBRX: return "PPCISD::STBRX";
1027 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1028 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1029 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1030 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1031 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1032 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1033 case PPCISD::BDZ: return "PPCISD::BDZ";
1034 case PPCISD::MFFS: return "PPCISD::MFFS";
1035 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1036 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1037 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1038 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1039 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1040 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1041 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1042 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1043 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1044 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1045 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1046 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1047 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1048 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1049 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1050 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1051 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1052 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1053 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1054 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1055 case PPCISD::SC: return "PPCISD::SC";
1056 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1057 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1058 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1059 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1060 case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1061 case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1062 case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1063 case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1064 case PPCISD::QBFLT: return "PPCISD::QBFLT";
1065 case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1070 EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1073 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1075 if (Subtarget.hasQPX())
1076 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
1078 return VT.changeVectorElementTypeToInteger();
1081 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1082 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1086 //===----------------------------------------------------------------------===//
1087 // Node matching predicates, for use by the tblgen matching code.
1088 //===----------------------------------------------------------------------===//
1090 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1091 static bool isFloatingPointZero(SDValue Op) {
1092 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1093 return CFP->getValueAPF().isZero();
1094 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1095 // Maybe this has already been legalized into the constant pool?
1096 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1097 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1098 return CFP->getValueAPF().isZero();
1103 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1104 /// true if Op is undef or if it matches the specified value.
1105 static bool isConstantOrUndef(int Op, int Val) {
1106 return Op < 0 || Op == Val;
1109 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1110 /// VPKUHUM instruction.
1111 /// The ShuffleKind distinguishes between big-endian operations with
1112 /// two different inputs (0), either-endian operations with two identical
1113 /// inputs (1), and little-endian operations with two different inputs (2).
1114 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1115 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1116 SelectionDAG &DAG) {
1117 bool IsLE = DAG.getDataLayout().isLittleEndian();
1118 if (ShuffleKind == 0) {
1121 for (unsigned i = 0; i != 16; ++i)
1122 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1124 } else if (ShuffleKind == 2) {
1127 for (unsigned i = 0; i != 16; ++i)
1128 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1130 } else if (ShuffleKind == 1) {
1131 unsigned j = IsLE ? 0 : 1;
1132 for (unsigned i = 0; i != 8; ++i)
1133 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1134 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1140 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1141 /// VPKUWUM instruction.
1142 /// The ShuffleKind distinguishes between big-endian operations with
1143 /// two different inputs (0), either-endian operations with two identical
1144 /// inputs (1), and little-endian operations with two different inputs (2).
1145 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1146 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1147 SelectionDAG &DAG) {
1148 bool IsLE = DAG.getDataLayout().isLittleEndian();
1149 if (ShuffleKind == 0) {
1152 for (unsigned i = 0; i != 16; i += 2)
1153 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1154 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1156 } else if (ShuffleKind == 2) {
1159 for (unsigned i = 0; i != 16; i += 2)
1160 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1161 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1163 } else if (ShuffleKind == 1) {
1164 unsigned j = IsLE ? 0 : 2;
1165 for (unsigned i = 0; i != 8; i += 2)
1166 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1167 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1168 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1169 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1175 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1176 /// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1177 /// current subtarget.
1179 /// The ShuffleKind distinguishes between big-endian operations with
1180 /// two different inputs (0), either-endian operations with two identical
1181 /// inputs (1), and little-endian operations with two different inputs (2).
1182 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1183 bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1184 SelectionDAG &DAG) {
1185 const PPCSubtarget& Subtarget =
1186 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1187 if (!Subtarget.hasP8Vector())
1190 bool IsLE = DAG.getDataLayout().isLittleEndian();
1191 if (ShuffleKind == 0) {
1194 for (unsigned i = 0; i != 16; i += 4)
1195 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1196 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1197 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1198 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1200 } else if (ShuffleKind == 2) {
1203 for (unsigned i = 0; i != 16; i += 4)
1204 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1205 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1206 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1207 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1209 } else if (ShuffleKind == 1) {
1210 unsigned j = IsLE ? 0 : 4;
1211 for (unsigned i = 0; i != 8; i += 4)
1212 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1213 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1214 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1215 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1216 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1217 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1218 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1219 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1225 /// isVMerge - Common function, used to match vmrg* shuffles.
1227 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1228 unsigned LHSStart, unsigned RHSStart) {
1229 if (N->getValueType(0) != MVT::v16i8)
1231 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1232 "Unsupported merge size!");
1234 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1235 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1236 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1237 LHSStart+j+i*UnitSize) ||
1238 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1239 RHSStart+j+i*UnitSize))
1245 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1246 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1247 /// The ShuffleKind distinguishes between big-endian merges with two
1248 /// different inputs (0), either-endian merges with two identical inputs (1),
1249 /// and little-endian merges with two different inputs (2). For the latter,
1250 /// the input operands are swapped (see PPCInstrAltivec.td).
1251 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1252 unsigned ShuffleKind, SelectionDAG &DAG) {
1253 if (DAG.getDataLayout().isLittleEndian()) {
1254 if (ShuffleKind == 1) // unary
1255 return isVMerge(N, UnitSize, 0, 0);
1256 else if (ShuffleKind == 2) // swapped
1257 return isVMerge(N, UnitSize, 0, 16);
1261 if (ShuffleKind == 1) // unary
1262 return isVMerge(N, UnitSize, 8, 8);
1263 else if (ShuffleKind == 0) // normal
1264 return isVMerge(N, UnitSize, 8, 24);
1270 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1271 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1272 /// The ShuffleKind distinguishes between big-endian merges with two
1273 /// different inputs (0), either-endian merges with two identical inputs (1),
1274 /// and little-endian merges with two different inputs (2). For the latter,
1275 /// the input operands are swapped (see PPCInstrAltivec.td).
1276 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1277 unsigned ShuffleKind, SelectionDAG &DAG) {
1278 if (DAG.getDataLayout().isLittleEndian()) {
1279 if (ShuffleKind == 1) // unary
1280 return isVMerge(N, UnitSize, 8, 8);
1281 else if (ShuffleKind == 2) // swapped
1282 return isVMerge(N, UnitSize, 8, 24);
1286 if (ShuffleKind == 1) // unary
1287 return isVMerge(N, UnitSize, 0, 0);
1288 else if (ShuffleKind == 0) // normal
1289 return isVMerge(N, UnitSize, 0, 16);
1296 * \brief Common function used to match vmrgew and vmrgow shuffles
1298 * The indexOffset determines whether to look for even or odd words in
1299 * the shuffle mask. This is based on the of the endianness of the target
1302 * - Use offset of 0 to check for odd elements
1303 * - Use offset of 4 to check for even elements
1305 * - Use offset of 0 to check for even elements
1306 * - Use offset of 4 to check for odd elements
1307 * A detailed description of the vector element ordering for little endian and
1308 * big endian can be found at
1309 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1310 * Targeting your applications - what little endian and big endian IBM XL C/C++
1311 * compiler differences mean to you
1313 * The mask to the shuffle vector instruction specifies the indices of the
1314 * elements from the two input vectors to place in the result. The elements are
1315 * numbered in array-access order, starting with the first vector. These vectors
1316 * are always of type v16i8, thus each vector will contain 16 elements of size
1317 * 8. More info on the shuffle vector can be found in the
1318 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1319 * Language Reference.
1321 * The RHSStartValue indicates whether the same input vectors are used (unary)
1322 * or two different input vectors are used, based on the following:
1323 * - If the instruction uses the same vector for both inputs, the range of the
1324 * indices will be 0 to 15. In this case, the RHSStart value passed should
1326 * - If the instruction has two different vectors then the range of the
1327 * indices will be 0 to 31. In this case, the RHSStart value passed should
1328 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1329 * to 31 specify elements in the second vector).
1331 * \param[in] N The shuffle vector SD Node to analyze
1332 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1333 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1334 * vector to the shuffle_vector instruction
1335 * \return true iff this shuffle vector represents an even or odd word merge
1337 static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1338 unsigned RHSStartValue) {
1339 if (N->getValueType(0) != MVT::v16i8)
1342 for (unsigned i = 0; i < 2; ++i)
1343 for (unsigned j = 0; j < 4; ++j)
1344 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1345 i*RHSStartValue+j+IndexOffset) ||
1346 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1347 i*RHSStartValue+j+IndexOffset+8))
1353 * \brief Determine if the specified shuffle mask is suitable for the vmrgew or
1354 * vmrgow instructions.
1356 * \param[in] N The shuffle vector SD Node to analyze
1357 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1358 * \param[in] ShuffleKind Identify the type of merge:
1359 * - 0 = big-endian merge with two different inputs;
1360 * - 1 = either-endian merge with two identical inputs;
1361 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1362 * little-endian merges).
1363 * \param[in] DAG The current SelectionDAG
1364 * \return true iff this shuffle mask
1366 bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1367 unsigned ShuffleKind, SelectionDAG &DAG) {
1368 if (DAG.getDataLayout().isLittleEndian()) {
1369 unsigned indexOffset = CheckEven ? 4 : 0;
1370 if (ShuffleKind == 1) // Unary
1371 return isVMerge(N, indexOffset, 0);
1372 else if (ShuffleKind == 2) // swapped
1373 return isVMerge(N, indexOffset, 16);
1378 unsigned indexOffset = CheckEven ? 0 : 4;
1379 if (ShuffleKind == 1) // Unary
1380 return isVMerge(N, indexOffset, 0);
1381 else if (ShuffleKind == 0) // Normal
1382 return isVMerge(N, indexOffset, 16);
1389 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1390 /// amount, otherwise return -1.
1391 /// The ShuffleKind distinguishes between big-endian operations with two
1392 /// different inputs (0), either-endian operations with two identical inputs
1393 /// (1), and little-endian operations with two different inputs (2). For the
1394 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1395 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1396 SelectionDAG &DAG) {
1397 if (N->getValueType(0) != MVT::v16i8)
1400 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1402 // Find the first non-undef value in the shuffle mask.
1404 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1407 if (i == 16) return -1; // all undef.
1409 // Otherwise, check to see if the rest of the elements are consecutively
1410 // numbered from this value.
1411 unsigned ShiftAmt = SVOp->getMaskElt(i);
1412 if (ShiftAmt < i) return -1;
1415 bool isLE = DAG.getDataLayout().isLittleEndian();
1417 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1418 // Check the rest of the elements to see if they are consecutive.
1419 for (++i; i != 16; ++i)
1420 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1422 } else if (ShuffleKind == 1) {
1423 // Check the rest of the elements to see if they are consecutive.
1424 for (++i; i != 16; ++i)
1425 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1431 ShiftAmt = 16 - ShiftAmt;
1436 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1437 /// specifies a splat of a single element that is suitable for input to
1438 /// VSPLTB/VSPLTH/VSPLTW.
1439 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1440 assert(N->getValueType(0) == MVT::v16i8 &&
1441 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1443 // The consecutive indices need to specify an element, not part of two
1444 // different elements. So abandon ship early if this isn't the case.
1445 if (N->getMaskElt(0) % EltSize != 0)
1448 // This is a splat operation if each element of the permute is the same, and
1449 // if the value doesn't reference the second vector.
1450 unsigned ElementBase = N->getMaskElt(0);
1452 // FIXME: Handle UNDEF elements too!
1453 if (ElementBase >= 16)
1456 // Check that the indices are consecutive, in the case of a multi-byte element
1457 // splatted with a v16i8 mask.
1458 for (unsigned i = 1; i != EltSize; ++i)
1459 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1462 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1463 if (N->getMaskElt(i) < 0) continue;
1464 for (unsigned j = 0; j != EltSize; ++j)
1465 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1471 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1472 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1473 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1474 SelectionDAG &DAG) {
1475 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1476 assert(isSplatShuffleMask(SVOp, EltSize));
1477 if (DAG.getDataLayout().isLittleEndian())
1478 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1480 return SVOp->getMaskElt(0) / EltSize;
1483 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1484 /// by using a vspltis[bhw] instruction of the specified element size, return
1485 /// the constant being splatted. The ByteSize field indicates the number of
1486 /// bytes of each element [124] -> [bhw].
1487 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1488 SDValue OpVal(nullptr, 0);
1490 // If ByteSize of the splat is bigger than the element size of the
1491 // build_vector, then we have a case where we are checking for a splat where
1492 // multiple elements of the buildvector are folded together into a single
1493 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1494 unsigned EltSize = 16/N->getNumOperands();
1495 if (EltSize < ByteSize) {
1496 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1497 SDValue UniquedVals[4];
1498 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1500 // See if all of the elements in the buildvector agree across.
1501 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1502 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1503 // If the element isn't a constant, bail fully out.
1504 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1507 if (!UniquedVals[i&(Multiple-1)].getNode())
1508 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1509 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1510 return SDValue(); // no match.
1513 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1514 // either constant or undef values that are identical for each chunk. See
1515 // if these chunks can form into a larger vspltis*.
1517 // Check to see if all of the leading entries are either 0 or -1. If
1518 // neither, then this won't fit into the immediate field.
1519 bool LeadingZero = true;
1520 bool LeadingOnes = true;
1521 for (unsigned i = 0; i != Multiple-1; ++i) {
1522 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1524 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1525 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1527 // Finally, check the least significant entry.
1529 if (!UniquedVals[Multiple-1].getNode())
1530 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
1531 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1532 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
1533 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1536 if (!UniquedVals[Multiple-1].getNode())
1537 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
1538 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1539 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1540 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1546 // Check to see if this buildvec has a single non-undef value in its elements.
1547 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1548 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1549 if (!OpVal.getNode())
1550 OpVal = N->getOperand(i);
1551 else if (OpVal != N->getOperand(i))
1555 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1557 unsigned ValSizeInBytes = EltSize;
1559 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1560 Value = CN->getZExtValue();
1561 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1562 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1563 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1566 // If the splat value is larger than the element value, then we can never do
1567 // this splat. The only case that we could fit the replicated bits into our
1568 // immediate field for would be zero, and we prefer to use vxor for it.
1569 if (ValSizeInBytes < ByteSize) return SDValue();
1571 // If the element value is larger than the splat value, check if it consists
1572 // of a repeated bit pattern of size ByteSize.
1573 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
1576 // Properly sign extend the value.
1577 int MaskVal = SignExtend32(Value, ByteSize * 8);
1579 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1580 if (MaskVal == 0) return SDValue();
1582 // Finally, if this value fits in a 5 bit sext field, return it
1583 if (SignExtend32<5>(MaskVal) == MaskVal)
1584 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
1588 /// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
1589 /// amount, otherwise return -1.
1590 int PPC::isQVALIGNIShuffleMask(SDNode *N) {
1591 EVT VT = N->getValueType(0);
1592 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
1595 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1597 // Find the first non-undef value in the shuffle mask.
1599 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
1602 if (i == 4) return -1; // all undef.
1604 // Otherwise, check to see if the rest of the elements are consecutively
1605 // numbered from this value.
1606 unsigned ShiftAmt = SVOp->getMaskElt(i);
1607 if (ShiftAmt < i) return -1;
1610 // Check the rest of the elements to see if they are consecutive.
1611 for (++i; i != 4; ++i)
1612 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1618 //===----------------------------------------------------------------------===//
1619 // Addressing Mode Selection
1620 //===----------------------------------------------------------------------===//
1622 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1623 /// or 64-bit immediate, and if the value can be accurately represented as a
1624 /// sign extension from a 16-bit value. If so, this returns true and the
1626 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1627 if (!isa<ConstantSDNode>(N))
1630 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1631 if (N->getValueType(0) == MVT::i32)
1632 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1634 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1636 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1637 return isIntS16Immediate(Op.getNode(), Imm);
1640 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1641 /// can be represented as an indexed [r+r] operation. Returns false if it
1642 /// can be more efficiently represented with [r+imm].
1643 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1645 SelectionDAG &DAG) const {
1647 if (N.getOpcode() == ISD::ADD) {
1648 if (isIntS16Immediate(N.getOperand(1), imm))
1649 return false; // r+i
1650 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1651 return false; // r+i
1653 Base = N.getOperand(0);
1654 Index = N.getOperand(1);
1656 } else if (N.getOpcode() == ISD::OR) {
1657 if (isIntS16Immediate(N.getOperand(1), imm))
1658 return false; // r+i can fold it if we can.
1660 // If this is an or of disjoint bitfields, we can codegen this as an add
1661 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1663 APInt LHSKnownZero, LHSKnownOne;
1664 APInt RHSKnownZero, RHSKnownOne;
1665 DAG.computeKnownBits(N.getOperand(0),
1666 LHSKnownZero, LHSKnownOne);
1668 if (LHSKnownZero.getBoolValue()) {
1669 DAG.computeKnownBits(N.getOperand(1),
1670 RHSKnownZero, RHSKnownOne);
1671 // If all of the bits are known zero on the LHS or RHS, the add won't
1673 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1674 Base = N.getOperand(0);
1675 Index = N.getOperand(1);
1684 // If we happen to be doing an i64 load or store into a stack slot that has
1685 // less than a 4-byte alignment, then the frame-index elimination may need to
1686 // use an indexed load or store instruction (because the offset may not be a
1687 // multiple of 4). The extra register needed to hold the offset comes from the
1688 // register scavenger, and it is possible that the scavenger will need to use
1689 // an emergency spill slot. As a result, we need to make sure that a spill slot
1690 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1692 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1693 // FIXME: This does not handle the LWA case.
1697 // NOTE: We'll exclude negative FIs here, which come from argument
1698 // lowering, because there are no known test cases triggering this problem
1699 // using packed structures (or similar). We can remove this exclusion if
1700 // we find such a test case. The reason why this is so test-case driven is
1701 // because this entire 'fixup' is only to prevent crashes (from the
1702 // register scavenger) on not-really-valid inputs. For example, if we have:
1704 // %b = bitcast i1* %a to i64*
1705 // store i64* a, i64 b
1706 // then the store should really be marked as 'align 1', but is not. If it
1707 // were marked as 'align 1' then the indexed form would have been
1708 // instruction-selected initially, and the problem this 'fixup' is preventing
1709 // won't happen regardless.
1713 MachineFunction &MF = DAG.getMachineFunction();
1714 MachineFrameInfo *MFI = MF.getFrameInfo();
1716 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1720 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1721 FuncInfo->setHasNonRISpills();
1724 /// Returns true if the address N can be represented by a base register plus
1725 /// a signed 16-bit displacement [r+imm], and if it is not better
1726 /// represented as reg+reg. If Aligned is true, only accept displacements
1727 /// suitable for STD and friends, i.e. multiples of 4.
1728 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1731 bool Aligned) const {
1732 // FIXME dl should come from parent load or store, not from address
1734 // If this can be more profitably realized as r+r, fail.
1735 if (SelectAddressRegReg(N, Disp, Base, DAG))
1738 if (N.getOpcode() == ISD::ADD) {
1740 if (isIntS16Immediate(N.getOperand(1), imm) &&
1741 (!Aligned || (imm & 3) == 0)) {
1742 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1743 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1744 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1745 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1747 Base = N.getOperand(0);
1749 return true; // [r+i]
1750 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1751 // Match LOAD (ADD (X, Lo(G))).
1752 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1753 && "Cannot handle constant offsets yet!");
1754 Disp = N.getOperand(1).getOperand(0); // The global address.
1755 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1756 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1757 Disp.getOpcode() == ISD::TargetConstantPool ||
1758 Disp.getOpcode() == ISD::TargetJumpTable);
1759 Base = N.getOperand(0);
1760 return true; // [&g+r]
1762 } else if (N.getOpcode() == ISD::OR) {
1764 if (isIntS16Immediate(N.getOperand(1), imm) &&
1765 (!Aligned || (imm & 3) == 0)) {
1766 // If this is an or of disjoint bitfields, we can codegen this as an add
1767 // (for better address arithmetic) if the LHS and RHS of the OR are
1768 // provably disjoint.
1769 APInt LHSKnownZero, LHSKnownOne;
1770 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1772 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1773 // If all of the bits are known zero on the LHS or RHS, the add won't
1775 if (FrameIndexSDNode *FI =
1776 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1777 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1778 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1780 Base = N.getOperand(0);
1782 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1786 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1787 // Loading from a constant address.
1789 // If this address fits entirely in a 16-bit sext immediate field, codegen
1792 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1793 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
1794 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1795 CN->getValueType(0));
1799 // Handle 32-bit sext immediates with LIS + addr mode.
1800 if ((CN->getValueType(0) == MVT::i32 ||
1801 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1802 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1803 int Addr = (int)CN->getZExtValue();
1805 // Otherwise, break this down into an LIS + disp.
1806 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
1808 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
1810 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1811 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1816 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
1817 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1818 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1819 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1822 return true; // [r+0]
1825 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1826 /// represented as an indexed [r+r] operation.
1827 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1829 SelectionDAG &DAG) const {
1830 // Check to see if we can easily represent this as an [r+r] address. This
1831 // will fail if it thinks that the address is more profitably represented as
1832 // reg+imm, e.g. where imm = 0.
1833 if (SelectAddressRegReg(N, Base, Index, DAG))
1836 // If the operand is an addition, always emit this as [r+r], since this is
1837 // better (for code size, and execution, as the memop does the add for free)
1838 // than emitting an explicit add.
1839 if (N.getOpcode() == ISD::ADD) {
1840 Base = N.getOperand(0);
1841 Index = N.getOperand(1);
1845 // Otherwise, do it the hard way, using R0 as the base register.
1846 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1852 /// getPreIndexedAddressParts - returns true by value, base pointer and
1853 /// offset pointer and addressing mode by reference if the node's address
1854 /// can be legally represented as pre-indexed load / store address.
1855 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1857 ISD::MemIndexedMode &AM,
1858 SelectionDAG &DAG) const {
1859 if (DisablePPCPreinc) return false;
1865 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1866 Ptr = LD->getBasePtr();
1867 VT = LD->getMemoryVT();
1868 Alignment = LD->getAlignment();
1869 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1870 Ptr = ST->getBasePtr();
1871 VT = ST->getMemoryVT();
1872 Alignment = ST->getAlignment();
1877 // PowerPC doesn't have preinc load/store instructions for vectors (except
1878 // for QPX, which does have preinc r+r forms).
1879 if (VT.isVector()) {
1880 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
1882 } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
1888 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1890 // Common code will reject creating a pre-inc form if the base pointer
1891 // is a frame index, or if N is a store and the base pointer is either
1892 // the same as or a predecessor of the value being stored. Check for
1893 // those situations here, and try with swapped Base/Offset instead.
1896 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1899 SDValue Val = cast<StoreSDNode>(N)->getValue();
1900 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1905 std::swap(Base, Offset);
1911 // LDU/STU can only handle immediates that are a multiple of 4.
1912 if (VT != MVT::i64) {
1913 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1916 // LDU/STU need an address with at least 4-byte alignment.
1920 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1924 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1925 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1926 // sext i32 to i64 when addr mode is r+i.
1927 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1928 LD->getExtensionType() == ISD::SEXTLOAD &&
1929 isa<ConstantSDNode>(Offset))
1937 //===----------------------------------------------------------------------===//
1938 // LowerOperation implementation
1939 //===----------------------------------------------------------------------===//
1941 /// GetLabelAccessInfo - Return true if we should reference labels using a
1942 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1943 static bool GetLabelAccessInfo(const TargetMachine &TM,
1944 const PPCSubtarget &Subtarget,
1945 unsigned &HiOpFlags, unsigned &LoOpFlags,
1946 const GlobalValue *GV = nullptr) {
1947 HiOpFlags = PPCII::MO_HA;
1948 LoOpFlags = PPCII::MO_LO;
1950 // Don't use the pic base if not in PIC relocation model.
1951 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1954 HiOpFlags |= PPCII::MO_PIC_FLAG;
1955 LoOpFlags |= PPCII::MO_PIC_FLAG;
1958 // If this is a reference to a global value that requires a non-lazy-ptr, make
1959 // sure that instruction lowering adds it.
1960 if (GV && Subtarget.hasLazyResolverStub(GV)) {
1961 HiOpFlags |= PPCII::MO_NLP_FLAG;
1962 LoOpFlags |= PPCII::MO_NLP_FLAG;
1964 if (GV->hasHiddenVisibility()) {
1965 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1966 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1973 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1974 SelectionDAG &DAG) {
1976 EVT PtrVT = HiPart.getValueType();
1977 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
1979 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1980 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1982 // With PIC, the first instruction is actually "GR+hi(&G)".
1984 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1985 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1987 // Generate non-pic code that has direct accesses to the constant pool.
1988 // The address of the global is just (hi(&g)+lo(&g)).
1989 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1992 static void setUsesTOCBasePtr(MachineFunction &MF) {
1993 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1994 FuncInfo->setUsesTOCBasePtr();
1997 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
1998 setUsesTOCBasePtr(DAG.getMachineFunction());
2001 static SDValue getTOCEntry(SelectionDAG &DAG, SDLoc dl, bool Is64Bit,
2003 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2004 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
2005 DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
2007 SDValue Ops[] = { GA, Reg };
2008 return DAG.getMemIntrinsicNode(
2009 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
2010 MachinePointerInfo::getGOT(DAG.getMachineFunction()), 0, false, true,
2014 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2015 SelectionDAG &DAG) const {
2016 EVT PtrVT = Op.getValueType();
2017 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2018 const Constant *C = CP->getConstVal();
2020 // 64-bit SVR4 ABI code is always position-independent.
2021 // The actual address of the GlobalValue is stored in the TOC.
2022 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2023 setUsesTOCBasePtr(DAG);
2024 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
2025 return getTOCEntry(DAG, SDLoc(CP), true, GA);
2028 unsigned MOHiFlag, MOLoFlag;
2030 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2032 if (isPIC && Subtarget.isSVR4ABI()) {
2033 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
2034 PPCII::MO_PIC_FLAG);
2035 return getTOCEntry(DAG, SDLoc(CP), false, GA);
2039 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
2041 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
2042 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
2045 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2046 EVT PtrVT = Op.getValueType();
2047 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2049 // 64-bit SVR4 ABI code is always position-independent.
2050 // The actual address of the GlobalValue is stored in the TOC.
2051 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2052 setUsesTOCBasePtr(DAG);
2053 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2054 return getTOCEntry(DAG, SDLoc(JT), true, GA);
2057 unsigned MOHiFlag, MOLoFlag;
2059 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2061 if (isPIC && Subtarget.isSVR4ABI()) {
2062 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2063 PPCII::MO_PIC_FLAG);
2064 return getTOCEntry(DAG, SDLoc(GA), false, GA);
2067 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
2068 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
2069 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
2072 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2073 SelectionDAG &DAG) const {
2074 EVT PtrVT = Op.getValueType();
2075 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2076 const BlockAddress *BA = BASDN->getBlockAddress();
2078 // 64-bit SVR4 ABI code is always position-independent.
2079 // The actual BlockAddress is stored in the TOC.
2080 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2081 setUsesTOCBasePtr(DAG);
2082 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
2083 return getTOCEntry(DAG, SDLoc(BASDN), true, GA);
2086 unsigned MOHiFlag, MOLoFlag;
2088 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2089 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
2090 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
2091 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
2094 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2095 SelectionDAG &DAG) const {
2097 // FIXME: TLS addresses currently use medium model code sequences,
2098 // which is the most useful form. Eventually support for small and
2099 // large models could be added if users need it, at the cost of
2100 // additional complexity.
2101 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2102 if (DAG.getTarget().Options.EmulatedTLS)
2103 return LowerToTLSEmulatedModel(GA, DAG);
2106 const GlobalValue *GV = GA->getGlobal();
2107 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2108 bool is64bit = Subtarget.isPPC64();
2109 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
2110 PICLevel::Level picLevel = M->getPICLevel();
2112 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
2114 if (Model == TLSModel::LocalExec) {
2115 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2116 PPCII::MO_TPREL_HA);
2117 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2118 PPCII::MO_TPREL_LO);
2119 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
2120 is64bit ? MVT::i64 : MVT::i32);
2121 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
2122 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
2125 if (Model == TLSModel::InitialExec) {
2126 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2127 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2131 setUsesTOCBasePtr(DAG);
2132 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2133 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
2134 PtrVT, GOTReg, TGA);
2136 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
2137 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
2138 PtrVT, TGA, GOTPtr);
2139 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
2142 if (Model == TLSModel::GeneralDynamic) {
2143 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2146 setUsesTOCBasePtr(DAG);
2147 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2148 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
2151 if (picLevel == PICLevel::Small)
2152 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2154 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2156 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
2160 if (Model == TLSModel::LocalDynamic) {
2161 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2164 setUsesTOCBasePtr(DAG);
2165 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2166 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2169 if (picLevel == PICLevel::Small)
2170 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2172 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2174 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2175 PtrVT, GOTPtr, TGA, TGA);
2176 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2177 PtrVT, TLSAddr, TGA);
2178 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2181 llvm_unreachable("Unknown TLS model!");
2184 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2185 SelectionDAG &DAG) const {
2186 EVT PtrVT = Op.getValueType();
2187 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2189 const GlobalValue *GV = GSDN->getGlobal();
2191 // 64-bit SVR4 ABI code is always position-independent.
2192 // The actual address of the GlobalValue is stored in the TOC.
2193 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2194 setUsesTOCBasePtr(DAG);
2195 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2196 return getTOCEntry(DAG, DL, true, GA);
2199 unsigned MOHiFlag, MOLoFlag;
2201 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag, GV);
2203 if (isPIC && Subtarget.isSVR4ABI()) {
2204 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2206 PPCII::MO_PIC_FLAG);
2207 return getTOCEntry(DAG, DL, false, GA);
2211 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2213 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2215 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
2217 // If the global reference is actually to a non-lazy-pointer, we have to do an
2218 // extra load to get the address of the global.
2219 if (MOHiFlag & PPCII::MO_NLP_FLAG)
2220 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
2221 false, false, false, 0);
2225 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2226 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2229 if (Op.getValueType() == MVT::v2i64) {
2230 // When the operands themselves are v2i64 values, we need to do something
2231 // special because VSX has no underlying comparison operations for these.
2232 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2233 // Equality can be handled by casting to the legal type for Altivec
2234 // comparisons, everything else needs to be expanded.
2235 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2236 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2237 DAG.getSetCC(dl, MVT::v4i32,
2238 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2239 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2246 // We handle most of these in the usual way.
2250 // If we're comparing for equality to zero, expose the fact that this is
2251 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
2252 // fold the new nodes.
2253 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2254 if (C->isNullValue() && CC == ISD::SETEQ) {
2255 EVT VT = Op.getOperand(0).getValueType();
2256 SDValue Zext = Op.getOperand(0);
2257 if (VT.bitsLT(MVT::i32)) {
2259 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
2261 unsigned Log2b = Log2_32(VT.getSizeInBits());
2262 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
2263 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
2264 DAG.getConstant(Log2b, dl, MVT::i32));
2265 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
2267 // Leave comparisons against 0 and -1 alone for now, since they're usually
2268 // optimized. FIXME: revisit this when we can custom lower all setcc
2270 if (C->isAllOnesValue() || C->isNullValue())
2274 // If we have an integer seteq/setne, turn it into a compare against zero
2275 // by xor'ing the rhs with the lhs, which is faster than setting a
2276 // condition register, reading it back out, and masking the correct bit. The
2277 // normal approach here uses sub to do this instead of xor. Using xor exposes
2278 // the result to other bit-twiddling opportunities.
2279 EVT LHSVT = Op.getOperand(0).getValueType();
2280 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2281 EVT VT = Op.getValueType();
2282 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2284 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
2289 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
2290 const PPCSubtarget &Subtarget) const {
2291 SDNode *Node = Op.getNode();
2292 EVT VT = Node->getValueType(0);
2293 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2294 SDValue InChain = Node->getOperand(0);
2295 SDValue VAListPtr = Node->getOperand(1);
2296 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2299 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
2302 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2303 VAListPtr, MachinePointerInfo(SV), MVT::i8,
2304 false, false, false, 0);
2305 InChain = GprIndex.getValue(1);
2307 if (VT == MVT::i64) {
2308 // Check if GprIndex is even
2309 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2310 DAG.getConstant(1, dl, MVT::i32));
2311 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2312 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
2313 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2314 DAG.getConstant(1, dl, MVT::i32));
2315 // Align GprIndex to be even if it isn't
2316 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2320 // fpr index is 1 byte after gpr
2321 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2322 DAG.getConstant(1, dl, MVT::i32));
2325 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2326 FprPtr, MachinePointerInfo(SV), MVT::i8,
2327 false, false, false, 0);
2328 InChain = FprIndex.getValue(1);
2330 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2331 DAG.getConstant(8, dl, MVT::i32));
2333 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2334 DAG.getConstant(4, dl, MVT::i32));
2337 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
2338 MachinePointerInfo(), false, false,
2340 InChain = OverflowArea.getValue(1);
2342 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
2343 MachinePointerInfo(), false, false,
2345 InChain = RegSaveArea.getValue(1);
2347 // select overflow_area if index > 8
2348 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
2349 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
2351 // adjustment constant gpr_index * 4/8
2352 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
2353 VT.isInteger() ? GprIndex : FprIndex,
2354 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
2357 // OurReg = RegSaveArea + RegConstant
2358 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2361 // Floating types are 32 bytes into RegSaveArea
2362 if (VT.isFloatingPoint())
2363 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2364 DAG.getConstant(32, dl, MVT::i32));
2366 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
2367 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2368 VT.isInteger() ? GprIndex : FprIndex,
2369 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
2372 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
2373 VT.isInteger() ? VAListPtr : FprPtr,
2374 MachinePointerInfo(SV),
2375 MVT::i8, false, false, 0);
2377 // determine if we should load from reg_save_area or overflow_area
2378 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
2380 // increase overflow_area by 4/8 if gpr/fpr > 8
2381 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2382 DAG.getConstant(VT.isInteger() ? 4 : 8,
2385 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2388 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
2390 MachinePointerInfo(),
2391 MVT::i32, false, false, 0);
2393 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
2394 false, false, false, 0);
2397 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2398 const PPCSubtarget &Subtarget) const {
2399 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2401 // We have to copy the entire va_list struct:
2402 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2403 return DAG.getMemcpy(Op.getOperand(0), Op,
2404 Op.getOperand(1), Op.getOperand(2),
2405 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
2406 false, MachinePointerInfo(), MachinePointerInfo());
2409 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2410 SelectionDAG &DAG) const {
2411 return Op.getOperand(0);
2414 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2415 SelectionDAG &DAG) const {
2416 SDValue Chain = Op.getOperand(0);
2417 SDValue Trmp = Op.getOperand(1); // trampoline
2418 SDValue FPtr = Op.getOperand(2); // nested function
2419 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2422 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2423 bool isPPC64 = (PtrVT == MVT::i64);
2424 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
2426 TargetLowering::ArgListTy Args;
2427 TargetLowering::ArgListEntry Entry;
2429 Entry.Ty = IntPtrTy;
2430 Entry.Node = Trmp; Args.push_back(Entry);
2432 // TrampSize == (isPPC64 ? 48 : 40);
2433 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
2434 isPPC64 ? MVT::i64 : MVT::i32);
2435 Args.push_back(Entry);
2437 Entry.Node = FPtr; Args.push_back(Entry);
2438 Entry.Node = Nest; Args.push_back(Entry);
2440 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2441 TargetLowering::CallLoweringInfo CLI(DAG);
2442 CLI.setDebugLoc(dl).setChain(Chain)
2443 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2444 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2445 std::move(Args), 0);
2447 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2448 return CallResult.second;
2451 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2452 const PPCSubtarget &Subtarget) const {
2453 MachineFunction &MF = DAG.getMachineFunction();
2454 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2458 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2459 // vastart just stores the address of the VarArgsFrameIndex slot into the
2460 // memory location argument.
2461 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2462 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2463 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2464 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2465 MachinePointerInfo(SV),
2469 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2470 // We suppose the given va_list is already allocated.
2473 // char gpr; /* index into the array of 8 GPRs
2474 // * stored in the register save area
2475 // * gpr=0 corresponds to r3,
2476 // * gpr=1 to r4, etc.
2478 // char fpr; /* index into the array of 8 FPRs
2479 // * stored in the register save area
2480 // * fpr=0 corresponds to f1,
2481 // * fpr=1 to f2, etc.
2483 // char *overflow_arg_area;
2484 // /* location on stack that holds
2485 // * the next overflow argument
2487 // char *reg_save_area;
2488 // /* where r3:r10 and f1:f8 (if saved)
2493 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
2494 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
2496 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2498 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2500 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2503 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2504 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
2506 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2507 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
2509 uint64_t FPROffset = 1;
2510 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
2512 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2514 // Store first byte : number of int regs
2515 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2517 MachinePointerInfo(SV),
2518 MVT::i8, false, false, 0);
2519 uint64_t nextOffset = FPROffset;
2520 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2523 // Store second byte : number of float regs
2524 SDValue secondStore =
2525 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2526 MachinePointerInfo(SV, nextOffset), MVT::i8,
2528 nextOffset += StackOffset;
2529 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2531 // Store second word : arguments given on stack
2532 SDValue thirdStore =
2533 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2534 MachinePointerInfo(SV, nextOffset),
2536 nextOffset += FrameOffset;
2537 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2539 // Store third word : arguments given in registers
2540 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2541 MachinePointerInfo(SV, nextOffset),
2546 #include "PPCGenCallingConv.inc"
2548 // Function whose sole purpose is to kill compiler warnings
2549 // stemming from unused functions included from PPCGenCallingConv.inc.
2550 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2551 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2554 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2555 CCValAssign::LocInfo &LocInfo,
2556 ISD::ArgFlagsTy &ArgFlags,
2561 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2563 CCValAssign::LocInfo &LocInfo,
2564 ISD::ArgFlagsTy &ArgFlags,
2566 static const MCPhysReg ArgRegs[] = {
2567 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2568 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2570 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2572 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2574 // Skip one register if the first unallocated register has an even register
2575 // number and there are still argument registers available which have not been
2576 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2577 // need to skip a register if RegNum is odd.
2578 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2579 State.AllocateReg(ArgRegs[RegNum]);
2582 // Always return false here, as this function only makes sure that the first
2583 // unallocated register has an odd register number and does not actually
2584 // allocate a register for the current argument.
2588 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2590 CCValAssign::LocInfo &LocInfo,
2591 ISD::ArgFlagsTy &ArgFlags,
2593 static const MCPhysReg ArgRegs[] = {
2594 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2598 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2600 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2602 // If there is only one Floating-point register left we need to put both f64
2603 // values of a split ppc_fp128 value on the stack.
2604 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2605 State.AllocateReg(ArgRegs[RegNum]);
2608 // Always return false here, as this function only makes sure that the two f64
2609 // values a ppc_fp128 value is split into are both passed in registers or both
2610 // passed on the stack and does not actually allocate a register for the
2611 // current argument.
2615 /// FPR - The set of FP registers that should be allocated for arguments,
2617 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
2618 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
2619 PPC::F11, PPC::F12, PPC::F13};
2621 /// QFPR - The set of QPX registers that should be allocated for arguments.
2622 static const MCPhysReg QFPR[] = {
2623 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
2624 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
2626 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2628 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2629 unsigned PtrByteSize) {
2630 unsigned ArgSize = ArgVT.getStoreSize();
2631 if (Flags.isByVal())
2632 ArgSize = Flags.getByValSize();
2634 // Round up to multiples of the pointer size, except for array members,
2635 // which are always packed.
2636 if (!Flags.isInConsecutiveRegs())
2637 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2642 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2644 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2645 ISD::ArgFlagsTy Flags,
2646 unsigned PtrByteSize) {
2647 unsigned Align = PtrByteSize;
2649 // Altivec parameters are padded to a 16 byte boundary.
2650 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2651 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2652 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2653 ArgVT == MVT::v1i128)
2655 // QPX vector types stored in double-precision are padded to a 32 byte
2657 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
2660 // ByVal parameters are aligned as requested.
2661 if (Flags.isByVal()) {
2662 unsigned BVAlign = Flags.getByValAlign();
2663 if (BVAlign > PtrByteSize) {
2664 if (BVAlign % PtrByteSize != 0)
2666 "ByVal alignment is not a multiple of the pointer size");
2672 // Array members are always packed to their original alignment.
2673 if (Flags.isInConsecutiveRegs()) {
2674 // If the array member was split into multiple registers, the first
2675 // needs to be aligned to the size of the full type. (Except for
2676 // ppcf128, which is only aligned as its f64 components.)
2677 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2678 Align = OrigVT.getStoreSize();
2680 Align = ArgVT.getStoreSize();
2686 /// CalculateStackSlotUsed - Return whether this argument will use its
2687 /// stack slot (instead of being passed in registers). ArgOffset,
2688 /// AvailableFPRs, and AvailableVRs must hold the current argument
2689 /// position, and will be updated to account for this argument.
2690 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2691 ISD::ArgFlagsTy Flags,
2692 unsigned PtrByteSize,
2693 unsigned LinkageSize,
2694 unsigned ParamAreaSize,
2695 unsigned &ArgOffset,
2696 unsigned &AvailableFPRs,
2697 unsigned &AvailableVRs, bool HasQPX) {
2698 bool UseMemory = false;
2700 // Respect alignment of argument on the stack.
2702 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2703 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2704 // If there's no space left in the argument save area, we must
2705 // use memory (this check also catches zero-sized arguments).
2706 if (ArgOffset >= LinkageSize + ParamAreaSize)
2709 // Allocate argument on the stack.
2710 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2711 if (Flags.isInConsecutiveRegsLast())
2712 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2713 // If we overran the argument save area, we must use memory
2714 // (this check catches arguments passed partially in memory)
2715 if (ArgOffset > LinkageSize + ParamAreaSize)
2718 // However, if the argument is actually passed in an FPR or a VR,
2719 // we don't use memory after all.
2720 if (!Flags.isByVal()) {
2721 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
2722 // QPX registers overlap with the scalar FP registers.
2723 (HasQPX && (ArgVT == MVT::v4f32 ||
2724 ArgVT == MVT::v4f64 ||
2725 ArgVT == MVT::v4i1)))
2726 if (AvailableFPRs > 0) {
2730 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2731 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2732 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2733 ArgVT == MVT::v1i128)
2734 if (AvailableVRs > 0) {
2743 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2744 /// ensure minimum alignment required for target.
2745 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2746 unsigned NumBytes) {
2747 unsigned TargetAlign = Lowering->getStackAlignment();
2748 unsigned AlignMask = TargetAlign - 1;
2749 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2754 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2755 CallingConv::ID CallConv, bool isVarArg,
2756 const SmallVectorImpl<ISD::InputArg>
2758 SDLoc dl, SelectionDAG &DAG,
2759 SmallVectorImpl<SDValue> &InVals)
2761 if (Subtarget.isSVR4ABI()) {
2762 if (Subtarget.isPPC64())
2763 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2766 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2769 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2775 PPCTargetLowering::LowerFormalArguments_32SVR4(
2777 CallingConv::ID CallConv, bool isVarArg,
2778 const SmallVectorImpl<ISD::InputArg>
2780 SDLoc dl, SelectionDAG &DAG,
2781 SmallVectorImpl<SDValue> &InVals) const {
2783 // 32-bit SVR4 ABI Stack Frame Layout:
2784 // +-----------------------------------+
2785 // +--> | Back chain |
2786 // | +-----------------------------------+
2787 // | | Floating-point register save area |
2788 // | +-----------------------------------+
2789 // | | General register save area |
2790 // | +-----------------------------------+
2791 // | | CR save word |
2792 // | +-----------------------------------+
2793 // | | VRSAVE save word |
2794 // | +-----------------------------------+
2795 // | | Alignment padding |
2796 // | +-----------------------------------+
2797 // | | Vector register save area |
2798 // | +-----------------------------------+
2799 // | | Local variable space |
2800 // | +-----------------------------------+
2801 // | | Parameter list area |
2802 // | +-----------------------------------+
2803 // | | LR save word |
2804 // | +-----------------------------------+
2805 // SP--> +--- | Back chain |
2806 // +-----------------------------------+
2809 // System V Application Binary Interface PowerPC Processor Supplement
2810 // AltiVec Technology Programming Interface Manual
2812 MachineFunction &MF = DAG.getMachineFunction();
2813 MachineFrameInfo *MFI = MF.getFrameInfo();
2814 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2816 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2817 // Potential tail calls could cause overwriting of argument stack slots.
2818 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2819 (CallConv == CallingConv::Fast));
2820 unsigned PtrByteSize = 4;
2822 // Assign locations to all of the incoming arguments.
2823 SmallVector<CCValAssign, 16> ArgLocs;
2824 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2827 // Reserve space for the linkage area on the stack.
2828 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
2829 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2831 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2833 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2834 CCValAssign &VA = ArgLocs[i];
2836 // Arguments stored in registers.
2837 if (VA.isRegLoc()) {
2838 const TargetRegisterClass *RC;
2839 EVT ValVT = VA.getValVT();
2841 switch (ValVT.getSimpleVT().SimpleTy) {
2843 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2846 RC = &PPC::GPRCRegClass;
2849 if (Subtarget.hasP8Vector())
2850 RC = &PPC::VSSRCRegClass;
2852 RC = &PPC::F4RCRegClass;
2855 if (Subtarget.hasVSX())
2856 RC = &PPC::VSFRCRegClass;
2858 RC = &PPC::F8RCRegClass;
2863 RC = &PPC::VRRCRegClass;
2866 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
2870 RC = &PPC::VSHRCRegClass;
2873 RC = &PPC::QFRCRegClass;
2876 RC = &PPC::QBRCRegClass;
2880 // Transform the arguments stored in physical registers into virtual ones.
2881 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2882 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2883 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2885 if (ValVT == MVT::i1)
2886 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2888 InVals.push_back(ArgValue);
2890 // Argument stored in memory.
2891 assert(VA.isMemLoc());
2893 unsigned ArgSize = VA.getLocVT().getStoreSize();
2894 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2897 // Create load nodes to retrieve arguments from the stack.
2898 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2899 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2900 MachinePointerInfo(),
2901 false, false, false, 0));
2905 // Assign locations to all of the incoming aggregate by value arguments.
2906 // Aggregates passed by value are stored in the local variable space of the
2907 // caller's stack frame, right above the parameter list area.
2908 SmallVector<CCValAssign, 16> ByValArgLocs;
2909 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2910 ByValArgLocs, *DAG.getContext());
2912 // Reserve stack space for the allocations in CCInfo.
2913 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2915 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2917 // Area that is at least reserved in the caller of this function.
2918 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2919 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2921 // Set the size that is at least reserved in caller of this function. Tail
2922 // call optimized function's reserved stack space needs to be aligned so that
2923 // taking the difference between two stack areas will result in an aligned
2926 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2927 FuncInfo->setMinReservedArea(MinReservedArea);
2929 SmallVector<SDValue, 8> MemOps;
2931 // If the function takes variable number of arguments, make a frame index for
2932 // the start of the first vararg value... for expansion of llvm.va_start.
2934 static const MCPhysReg GPArgRegs[] = {
2935 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2936 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2938 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2940 static const MCPhysReg FPArgRegs[] = {
2941 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2944 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2945 if (DisablePPCFloatInVariadic)
2948 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
2949 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
2951 // Make room for NumGPArgRegs and NumFPArgRegs.
2952 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2953 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2955 FuncInfo->setVarArgsStackOffset(
2956 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2957 CCInfo.getNextStackOffset(), true));
2959 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2960 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2962 // The fixed integer arguments of a variadic function are stored to the
2963 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2964 // the result of va_next.
2965 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2966 // Get an existing live-in vreg, or add a new one.
2967 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2969 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2971 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2972 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2973 MachinePointerInfo(), false, false, 0);
2974 MemOps.push_back(Store);
2975 // Increment the address by four for the next argument to store
2976 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
2977 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2980 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2982 // The double arguments are stored to the VarArgsFrameIndex
2984 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2985 // Get an existing live-in vreg, or add a new one.
2986 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2988 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2990 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2991 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2992 MachinePointerInfo(), false, false, 0);
2993 MemOps.push_back(Store);
2994 // Increment the address by eight for the next argument to store
2995 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
2997 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3001 if (!MemOps.empty())
3002 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3007 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3008 // value to MVT::i64 and then truncate to the correct register size.
3010 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
3011 SelectionDAG &DAG, SDValue ArgVal,
3014 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
3015 DAG.getValueType(ObjectVT));
3016 else if (Flags.isZExt())
3017 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3018 DAG.getValueType(ObjectVT));
3020 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3024 PPCTargetLowering::LowerFormalArguments_64SVR4(
3026 CallingConv::ID CallConv, bool isVarArg,
3027 const SmallVectorImpl<ISD::InputArg>
3029 SDLoc dl, SelectionDAG &DAG,
3030 SmallVectorImpl<SDValue> &InVals) const {
3031 // TODO: add description of PPC stack frame format, or at least some docs.
3033 bool isELFv2ABI = Subtarget.isELFv2ABI();
3034 bool isLittleEndian = Subtarget.isLittleEndian();
3035 MachineFunction &MF = DAG.getMachineFunction();
3036 MachineFrameInfo *MFI = MF.getFrameInfo();
3037 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3039 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
3040 "fastcc not supported on varargs functions");
3042 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
3043 // Potential tail calls could cause overwriting of argument stack slots.
3044 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3045 (CallConv == CallingConv::Fast));
3046 unsigned PtrByteSize = 8;
3047 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3049 static const MCPhysReg GPR[] = {
3050 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3051 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3053 static const MCPhysReg VR[] = {
3054 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3055 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3057 static const MCPhysReg VSRH[] = {
3058 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
3059 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
3062 const unsigned Num_GPR_Regs = array_lengthof(GPR);
3063 const unsigned Num_FPR_Regs = 13;
3064 const unsigned Num_VR_Regs = array_lengthof(VR);
3065 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3067 // Do a first pass over the arguments to determine whether the ABI
3068 // guarantees that our caller has allocated the parameter save area
3069 // on its stack frame. In the ELFv1 ABI, this is always the case;
3070 // in the ELFv2 ABI, it is true if this is a vararg function or if
3071 // any parameter is located in a stack slot.
3073 bool HasParameterArea = !isELFv2ABI || isVarArg;
3074 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3075 unsigned NumBytes = LinkageSize;
3076 unsigned AvailableFPRs = Num_FPR_Regs;
3077 unsigned AvailableVRs = Num_VR_Regs;
3078 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3079 if (Ins[i].Flags.isNest())
3082 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3083 PtrByteSize, LinkageSize, ParamAreaSize,
3084 NumBytes, AvailableFPRs, AvailableVRs,
3085 Subtarget.hasQPX()))
3086 HasParameterArea = true;
3089 // Add DAG nodes to load the arguments or copy them out of registers. On
3090 // entry to a function on PPC, the arguments start after the linkage area,
3091 // although the first ones are often in registers.
3093 unsigned ArgOffset = LinkageSize;
3094 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3095 unsigned &QFPR_idx = FPR_idx;
3096 SmallVector<SDValue, 8> MemOps;
3097 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3098 unsigned CurArgIdx = 0;
3099 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3101 bool needsLoad = false;
3102 EVT ObjectVT = Ins[ArgNo].VT;
3103 EVT OrigVT = Ins[ArgNo].ArgVT;
3104 unsigned ObjSize = ObjectVT.getStoreSize();
3105 unsigned ArgSize = ObjSize;
3106 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3107 if (Ins[ArgNo].isOrigArg()) {
3108 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3109 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3111 // We re-align the argument offset for each argument, except when using the
3112 // fast calling convention, when we need to make sure we do that only when
3113 // we'll actually use a stack slot.
3114 unsigned CurArgOffset, Align;
3115 auto ComputeArgOffset = [&]() {
3116 /* Respect alignment of argument on the stack. */
3117 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
3118 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3119 CurArgOffset = ArgOffset;
3122 if (CallConv != CallingConv::Fast) {
3125 /* Compute GPR index associated with argument offset. */
3126 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3127 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
3130 // FIXME the codegen can be much improved in some cases.
3131 // We do not have to keep everything in memory.
3132 if (Flags.isByVal()) {
3133 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3135 if (CallConv == CallingConv::Fast)
3138 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3139 ObjSize = Flags.getByValSize();
3140 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3141 // Empty aggregate parameters do not take up registers. Examples:
3145 // etc. However, we have to provide a place-holder in InVals, so
3146 // pretend we have an 8-byte item at the current address for that
3149 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3150 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3151 InVals.push_back(FIN);
3155 // Create a stack object covering all stack doublewords occupied
3156 // by the argument. If the argument is (fully or partially) on
3157 // the stack, or if the argument is fully in registers but the
3158 // caller has allocated the parameter save anyway, we can refer
3159 // directly to the caller's stack frame. Otherwise, create a
3160 // local copy in our own frame.
3162 if (HasParameterArea ||
3163 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
3164 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
3166 FI = MFI->CreateStackObject(ArgSize, Align, false);
3167 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3169 // Handle aggregates smaller than 8 bytes.
3170 if (ObjSize < PtrByteSize) {
3171 // The value of the object is its address, which differs from the
3172 // address of the enclosing doubleword on big-endian systems.
3174 if (!isLittleEndian) {
3175 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
3176 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3178 InVals.push_back(Arg);
3180 if (GPR_idx != Num_GPR_Regs) {
3181 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3182 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3185 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3186 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3187 (ObjSize == 2 ? MVT::i16 : MVT::i32));
3188 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3189 MachinePointerInfo(FuncArg),
3190 ObjType, false, false, 0);
3192 // For sizes that don't fit a truncating store (3, 5, 6, 7),
3193 // store the whole register as-is to the parameter save area
3195 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3196 MachinePointerInfo(FuncArg),
3200 MemOps.push_back(Store);
3202 // Whether we copied from a register or not, advance the offset
3203 // into the parameter save area by a full doubleword.
3204 ArgOffset += PtrByteSize;
3208 // The value of the object is its address, which is the address of
3209 // its first stack doubleword.
3210 InVals.push_back(FIN);
3212 // Store whatever pieces of the object are in registers to memory.
3213 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3214 if (GPR_idx == Num_GPR_Regs)
3217 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3218 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3221 SDValue Off = DAG.getConstant(j, dl, PtrVT);
3222 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3224 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
3225 MachinePointerInfo(FuncArg, j),
3227 MemOps.push_back(Store);
3230 ArgOffset += ArgSize;
3234 switch (ObjectVT.getSimpleVT().SimpleTy) {
3235 default: llvm_unreachable("Unhandled argument type!");
3239 if (Flags.isNest()) {
3240 // The 'nest' parameter, if any, is passed in R11.
3241 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
3242 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3244 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3245 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3250 // These can be scalar arguments or elements of an integer array type
3251 // passed directly. Clang may use those instead of "byval" aggregate
3252 // types to avoid forcing arguments to memory unnecessarily.
3253 if (GPR_idx != Num_GPR_Regs) {
3254 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3255 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3257 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3258 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3259 // value to MVT::i64 and then truncate to the correct register size.
3260 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3262 if (CallConv == CallingConv::Fast)
3266 ArgSize = PtrByteSize;
3268 if (CallConv != CallingConv::Fast || needsLoad)
3274 // These can be scalar arguments or elements of a float array type
3275 // passed directly. The latter are used to implement ELFv2 homogenous
3276 // float aggregates.
3277 if (FPR_idx != Num_FPR_Regs) {
3280 if (ObjectVT == MVT::f32)
3281 VReg = MF.addLiveIn(FPR[FPR_idx],
3282 Subtarget.hasP8Vector()
3283 ? &PPC::VSSRCRegClass
3284 : &PPC::F4RCRegClass);
3286 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3287 ? &PPC::VSFRCRegClass
3288 : &PPC::F8RCRegClass);
3290 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3292 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3293 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3294 // once we support fp <-> gpr moves.
3296 // This can only ever happen in the presence of f32 array types,
3297 // since otherwise we never run out of FPRs before running out
3299 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3300 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3302 if (ObjectVT == MVT::f32) {
3303 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3304 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3305 DAG.getConstant(32, dl, MVT::i32));
3306 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3309 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3311 if (CallConv == CallingConv::Fast)
3317 // When passing an array of floats, the array occupies consecutive
3318 // space in the argument area; only round up to the next doubleword
3319 // at the end of the array. Otherwise, each float takes 8 bytes.
3320 if (CallConv != CallingConv::Fast || needsLoad) {
3321 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3322 ArgOffset += ArgSize;
3323 if (Flags.isInConsecutiveRegsLast())
3324 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3334 if (!Subtarget.hasQPX()) {
3335 // These can be scalar arguments or elements of a vector array type
3336 // passed directly. The latter are used to implement ELFv2 homogenous
3337 // vector aggregates.
3338 if (VR_idx != Num_VR_Regs) {
3339 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
3340 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
3341 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3342 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3345 if (CallConv == CallingConv::Fast)
3350 if (CallConv != CallingConv::Fast || needsLoad)
3355 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
3356 "Invalid QPX parameter type");
3361 // QPX vectors are treated like their scalar floating-point subregisters
3362 // (except that they're larger).
3363 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3364 if (QFPR_idx != Num_QFPR_Regs) {
3365 const TargetRegisterClass *RC;
3366 switch (ObjectVT.getSimpleVT().SimpleTy) {
3367 case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3368 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3369 default: RC = &PPC::QBRCRegClass; break;
3372 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3373 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3376 if (CallConv == CallingConv::Fast)
3380 if (CallConv != CallingConv::Fast || needsLoad)
3385 // We need to load the argument to a virtual register if we determined
3386 // above that we ran out of physical registers of the appropriate type.
3388 if (ObjSize < ArgSize && !isLittleEndian)
3389 CurArgOffset += ArgSize - ObjSize;
3390 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
3391 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3392 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3393 false, false, false, 0);
3396 InVals.push_back(ArgVal);
3399 // Area that is at least reserved in the caller of this function.
3400 unsigned MinReservedArea;
3401 if (HasParameterArea)
3402 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
3404 MinReservedArea = LinkageSize;
3406 // Set the size that is at least reserved in caller of this function. Tail
3407 // call optimized functions' reserved stack space needs to be aligned so that
3408 // taking the difference between two stack areas will result in an aligned
3411 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3412 FuncInfo->setMinReservedArea(MinReservedArea);
3414 // If the function takes variable number of arguments, make a frame index for
3415 // the start of the first vararg value... for expansion of llvm.va_start.
3417 int Depth = ArgOffset;
3419 FuncInfo->setVarArgsFrameIndex(
3420 MFI->CreateFixedObject(PtrByteSize, Depth, true));
3421 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3423 // If this function is vararg, store any remaining integer argument regs
3424 // to their spots on the stack so that they may be loaded by deferencing the
3425 // result of va_next.
3426 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3427 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
3428 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3429 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3430 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3431 MachinePointerInfo(), false, false, 0);
3432 MemOps.push_back(Store);
3433 // Increment the address by four for the next argument to store
3434 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
3435 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3439 if (!MemOps.empty())
3440 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3446 PPCTargetLowering::LowerFormalArguments_Darwin(
3448 CallingConv::ID CallConv, bool isVarArg,
3449 const SmallVectorImpl<ISD::InputArg>
3451 SDLoc dl, SelectionDAG &DAG,
3452 SmallVectorImpl<SDValue> &InVals) const {
3453 // TODO: add description of PPC stack frame format, or at least some docs.
3455 MachineFunction &MF = DAG.getMachineFunction();
3456 MachineFrameInfo *MFI = MF.getFrameInfo();
3457 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3459 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
3460 bool isPPC64 = PtrVT == MVT::i64;
3461 // Potential tail calls could cause overwriting of argument stack slots.
3462 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3463 (CallConv == CallingConv::Fast));
3464 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3465 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3466 unsigned ArgOffset = LinkageSize;
3467 // Area that is at least reserved in caller of this function.
3468 unsigned MinReservedArea = ArgOffset;
3470 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3471 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3472 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3474 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3475 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3476 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3478 static const MCPhysReg VR[] = {
3479 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3480 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3483 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3484 const unsigned Num_FPR_Regs = 13;
3485 const unsigned Num_VR_Regs = array_lengthof( VR);
3487 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3489 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3491 // In 32-bit non-varargs functions, the stack space for vectors is after the
3492 // stack space for non-vectors. We do not use this space unless we have
3493 // too many vectors to fit in registers, something that only occurs in
3494 // constructed examples:), but we have to walk the arglist to figure
3495 // that out...for the pathological case, compute VecArgOffset as the
3496 // start of the vector parameter area. Computing VecArgOffset is the
3497 // entire point of the following loop.
3498 unsigned VecArgOffset = ArgOffset;
3499 if (!isVarArg && !isPPC64) {
3500 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3502 EVT ObjectVT = Ins[ArgNo].VT;
3503 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3505 if (Flags.isByVal()) {
3506 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3507 unsigned ObjSize = Flags.getByValSize();
3509 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3510 VecArgOffset += ArgSize;
3514 switch(ObjectVT.getSimpleVT().SimpleTy) {
3515 default: llvm_unreachable("Unhandled argument type!");
3521 case MVT::i64: // PPC64
3523 // FIXME: We are guaranteed to be !isPPC64 at this point.
3524 // Does MVT::i64 apply?
3531 // Nothing to do, we're only looking at Nonvector args here.
3536 // We've found where the vector parameter area in memory is. Skip the
3537 // first 12 parameters; these don't use that memory.
3538 VecArgOffset = ((VecArgOffset+15)/16)*16;
3539 VecArgOffset += 12*16;
3541 // Add DAG nodes to load the arguments or copy them out of registers. On
3542 // entry to a function on PPC, the arguments start after the linkage area,
3543 // although the first ones are often in registers.
3545 SmallVector<SDValue, 8> MemOps;
3546 unsigned nAltivecParamsAtEnd = 0;
3547 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3548 unsigned CurArgIdx = 0;
3549 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3551 bool needsLoad = false;
3552 EVT ObjectVT = Ins[ArgNo].VT;
3553 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3554 unsigned ArgSize = ObjSize;
3555 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3556 if (Ins[ArgNo].isOrigArg()) {
3557 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3558 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3560 unsigned CurArgOffset = ArgOffset;
3562 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3563 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3564 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3565 if (isVarArg || isPPC64) {
3566 MinReservedArea = ((MinReservedArea+15)/16)*16;
3567 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3570 } else nAltivecParamsAtEnd++;
3572 // Calculate min reserved area.
3573 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3577 // FIXME the codegen can be much improved in some cases.
3578 // We do not have to keep everything in memory.
3579 if (Flags.isByVal()) {
3580 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3582 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3583 ObjSize = Flags.getByValSize();
3584 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3585 // Objects of size 1 and 2 are right justified, everything else is
3586 // left justified. This means the memory address is adjusted forwards.
3587 if (ObjSize==1 || ObjSize==2) {
3588 CurArgOffset = CurArgOffset + (4 - ObjSize);
3590 // The value of the object is its address.
3591 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3592 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3593 InVals.push_back(FIN);
3594 if (ObjSize==1 || ObjSize==2) {
3595 if (GPR_idx != Num_GPR_Regs) {
3598 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3600 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3601 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3602 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3603 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3604 MachinePointerInfo(FuncArg),
3605 ObjType, false, false, 0);
3606 MemOps.push_back(Store);
3610 ArgOffset += PtrByteSize;
3614 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3615 // Store whatever pieces of the object are in registers
3616 // to memory. ArgOffset will be the address of the beginning
3618 if (GPR_idx != Num_GPR_Regs) {
3621 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3623 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3624 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3625 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3626 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3627 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3628 MachinePointerInfo(FuncArg, j),
3630 MemOps.push_back(Store);
3632 ArgOffset += PtrByteSize;
3634 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3641 switch (ObjectVT.getSimpleVT().SimpleTy) {
3642 default: llvm_unreachable("Unhandled argument type!");
3646 if (GPR_idx != Num_GPR_Regs) {
3647 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3648 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3650 if (ObjectVT == MVT::i1)
3651 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3656 ArgSize = PtrByteSize;
3658 // All int arguments reserve stack space in the Darwin ABI.
3659 ArgOffset += PtrByteSize;
3663 case MVT::i64: // PPC64
3664 if (GPR_idx != Num_GPR_Regs) {
3665 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3666 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3668 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3669 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3670 // value to MVT::i64 and then truncate to the correct register size.
3671 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3676 ArgSize = PtrByteSize;
3678 // All int arguments reserve stack space in the Darwin ABI.
3684 // Every 4 bytes of argument space consumes one of the GPRs available for
3685 // argument passing.
3686 if (GPR_idx != Num_GPR_Regs) {
3688 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3691 if (FPR_idx != Num_FPR_Regs) {
3694 if (ObjectVT == MVT::f32)
3695 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3697 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3699 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3705 // All FP arguments reserve stack space in the Darwin ABI.
3706 ArgOffset += isPPC64 ? 8 : ObjSize;
3712 // Note that vector arguments in registers don't reserve stack space,
3713 // except in varargs functions.
3714 if (VR_idx != Num_VR_Regs) {
3715 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3716 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3718 while ((ArgOffset % 16) != 0) {
3719 ArgOffset += PtrByteSize;
3720 if (GPR_idx != Num_GPR_Regs)
3724 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3728 if (!isVarArg && !isPPC64) {
3729 // Vectors go after all the nonvectors.
3730 CurArgOffset = VecArgOffset;
3733 // Vectors are aligned.
3734 ArgOffset = ((ArgOffset+15)/16)*16;
3735 CurArgOffset = ArgOffset;
3743 // We need to load the argument to a virtual register if we determined above
3744 // that we ran out of physical registers of the appropriate type.
3746 int FI = MFI->CreateFixedObject(ObjSize,
3747 CurArgOffset + (ArgSize - ObjSize),
3749 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3750 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3751 false, false, false, 0);
3754 InVals.push_back(ArgVal);
3757 // Allow for Altivec parameters at the end, if needed.
3758 if (nAltivecParamsAtEnd) {
3759 MinReservedArea = ((MinReservedArea+15)/16)*16;
3760 MinReservedArea += 16*nAltivecParamsAtEnd;
3763 // Area that is at least reserved in the caller of this function.
3764 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3766 // Set the size that is at least reserved in caller of this function. Tail
3767 // call optimized functions' reserved stack space needs to be aligned so that
3768 // taking the difference between two stack areas will result in an aligned
3771 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3772 FuncInfo->setMinReservedArea(MinReservedArea);
3774 // If the function takes variable number of arguments, make a frame index for
3775 // the start of the first vararg value... for expansion of llvm.va_start.
3777 int Depth = ArgOffset;
3779 FuncInfo->setVarArgsFrameIndex(
3780 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3782 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3784 // If this function is vararg, store any remaining integer argument regs
3785 // to their spots on the stack so that they may be loaded by deferencing the
3786 // result of va_next.
3787 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3791 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3793 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3795 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3796 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3797 MachinePointerInfo(), false, false, 0);
3798 MemOps.push_back(Store);
3799 // Increment the address by four for the next argument to store
3800 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3801 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3805 if (!MemOps.empty())
3806 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3811 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3812 /// adjusted to accommodate the arguments for the tailcall.
3813 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3814 unsigned ParamSize) {
3816 if (!isTailCall) return 0;
3818 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3819 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3820 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3821 // Remember only if the new adjustement is bigger.
3822 if (SPDiff < FI->getTailCallSPDelta())
3823 FI->setTailCallSPDelta(SPDiff);
3828 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3829 /// for tail call optimization. Targets which want to do tail call
3830 /// optimization should implement this function.
3832 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3833 CallingConv::ID CalleeCC,
3835 const SmallVectorImpl<ISD::InputArg> &Ins,
3836 SelectionDAG& DAG) const {
3837 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3840 // Variable argument functions are not supported.
3844 MachineFunction &MF = DAG.getMachineFunction();
3845 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3846 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3847 // Functions containing by val parameters are not supported.
3848 for (unsigned i = 0; i != Ins.size(); i++) {
3849 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3850 if (Flags.isByVal()) return false;
3853 // Non-PIC/GOT tail calls are supported.
3854 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3857 // At the moment we can only do local tail calls (in same module, hidden
3858 // or protected) if we are generating PIC.
3859 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3860 return G->getGlobal()->hasHiddenVisibility()
3861 || G->getGlobal()->hasProtectedVisibility();
3867 /// isCallCompatibleAddress - Return the immediate to use if the specified
3868 /// 32-bit value is representable in the immediate field of a BxA instruction.
3869 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3870 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3871 if (!C) return nullptr;
3873 int Addr = C->getZExtValue();
3874 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3875 SignExtend32<26>(Addr) != Addr)
3876 return nullptr; // Top 6 bits have to be sext of immediate.
3878 return DAG.getConstant((int)C->getZExtValue() >> 2, SDLoc(Op),
3879 DAG.getTargetLoweringInfo().getPointerTy(
3880 DAG.getDataLayout())).getNode();
3885 struct TailCallArgumentInfo {
3890 TailCallArgumentInfo() : FrameIdx(0) {}
3894 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3896 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3898 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3899 SmallVectorImpl<SDValue> &MemOpChains,
3901 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3902 SDValue Arg = TailCallArgs[i].Arg;
3903 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3904 int FI = TailCallArgs[i].FrameIdx;
3905 // Store relative to framepointer.
3906 MemOpChains.push_back(DAG.getStore(
3907 Chain, dl, Arg, FIN,
3908 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
3913 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3914 /// the appropriate stack slot for the tail call optimized function call.
3915 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3916 MachineFunction &MF,
3925 // Calculate the new stack slot for the return address.
3926 int SlotSize = isPPC64 ? 8 : 4;
3927 const PPCFrameLowering *FL =
3928 MF.getSubtarget<PPCSubtarget>().getFrameLowering();
3929 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
3930 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3931 NewRetAddrLoc, true);
3932 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3933 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3934 Chain = DAG.getStore(
3935 Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3936 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), NewRetAddr),
3939 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3940 // slot as the FP is never overwritten.
3942 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
3943 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3945 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3946 Chain = DAG.getStore(
3947 Chain, dl, OldFP, NewFramePtrIdx,
3948 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), NewFPIdx),
3955 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3956 /// the position of the argument.
3958 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3959 SDValue Arg, int SPDiff, unsigned ArgOffset,
3960 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3961 int Offset = ArgOffset + SPDiff;
3962 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3963 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3964 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3965 SDValue FIN = DAG.getFrameIndex(FI, VT);
3966 TailCallArgumentInfo Info;
3968 Info.FrameIdxOp = FIN;
3970 TailCallArguments.push_back(Info);
3973 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3974 /// stack slot. Returns the chain as result and the loaded frame pointers in
3975 /// LROpOut/FPOpout. Used when tail calling.
3976 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3984 // Load the LR and FP stack slot for later adjusting.
3985 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3986 LROpOut = getReturnAddrFrameIndex(DAG);
3987 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3988 false, false, false, 0);
3989 Chain = SDValue(LROpOut.getNode(), 1);
3991 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3992 // slot as the FP is never overwritten.
3994 FPOpOut = getFramePointerFrameIndex(DAG);
3995 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3996 false, false, false, 0);
3997 Chain = SDValue(FPOpOut.getNode(), 1);
4003 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
4004 /// by "Src" to address "Dst" of size "Size". Alignment information is
4005 /// specified by the specific parameter attribute. The copy will be passed as
4006 /// a byval function parameter.
4007 /// Sometimes what we are copying is the end of a larger object, the part that
4008 /// does not fit in registers.
4010 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
4011 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
4013 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
4014 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
4015 false, false, false, MachinePointerInfo(),
4016 MachinePointerInfo());
4019 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
4022 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
4023 SDValue Arg, SDValue PtrOff, int SPDiff,
4024 unsigned ArgOffset, bool isPPC64, bool isTailCall,
4025 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
4026 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
4028 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4033 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4035 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4036 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4037 DAG.getConstant(ArgOffset, dl, PtrVT));
4039 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4040 MachinePointerInfo(), false, false, 0));
4041 // Calculate and remember argument location.
4042 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
4047 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
4048 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
4049 SDValue LROp, SDValue FPOp, bool isDarwinABI,
4050 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
4051 MachineFunction &MF = DAG.getMachineFunction();
4053 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
4054 // might overwrite each other in case of tail call optimization.
4055 SmallVector<SDValue, 8> MemOpChains2;
4056 // Do not flag preceding copytoreg stuff together with the following stuff.
4058 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
4060 if (!MemOpChains2.empty())
4061 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4063 // Store the return address to the appropriate stack slot.
4064 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
4065 isPPC64, isDarwinABI, dl);
4067 // Emit callseq_end just before tailcall node.
4068 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4069 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4070 InFlag = Chain.getValue(1);
4073 // Is this global address that of a function that can be called by name? (as
4074 // opposed to something that must hold a descriptor for an indirect call).
4075 static bool isFunctionGlobalAddress(SDValue Callee) {
4076 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
4077 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
4078 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
4081 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
4088 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
4089 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
4090 bool isTailCall, bool IsPatchPoint, bool hasNest,
4091 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
4092 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
4093 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
4095 bool isPPC64 = Subtarget.isPPC64();
4096 bool isSVR4ABI = Subtarget.isSVR4ABI();
4097 bool isELFv2ABI = Subtarget.isELFv2ABI();
4099 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4100 NodeTys.push_back(MVT::Other); // Returns a chain
4101 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
4103 unsigned CallOpc = PPCISD::CALL;
4105 bool needIndirectCall = true;
4106 if (!isSVR4ABI || !isPPC64)
4107 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
4108 // If this is an absolute destination address, use the munged value.
4109 Callee = SDValue(Dest, 0);
4110 needIndirectCall = false;
4113 if (isFunctionGlobalAddress(Callee)) {
4114 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
4115 // A call to a TLS address is actually an indirect call to a
4116 // thread-specific pointer.
4117 unsigned OpFlags = 0;
4118 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4119 (Subtarget.getTargetTriple().isMacOSX() &&
4120 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
4121 !G->getGlobal()->isStrongDefinitionForLinker()) ||
4122 (Subtarget.isTargetELF() && !isPPC64 &&
4123 !G->getGlobal()->hasLocalLinkage() &&
4124 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4125 // PC-relative references to external symbols should go through $stub,
4126 // unless we're building with the leopard linker or later, which
4127 // automatically synthesizes these stubs.
4128 OpFlags = PPCII::MO_PLT_OR_STUB;
4131 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
4132 // every direct call is) turn it into a TargetGlobalAddress /
4133 // TargetExternalSymbol node so that legalize doesn't hack it.
4134 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
4135 Callee.getValueType(), 0, OpFlags);
4136 needIndirectCall = false;
4139 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
4140 unsigned char OpFlags = 0;
4142 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4143 (Subtarget.getTargetTriple().isMacOSX() &&
4144 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
4145 (Subtarget.isTargetELF() && !isPPC64 &&
4146 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4147 // PC-relative references to external symbols should go through $stub,
4148 // unless we're building with the leopard linker or later, which
4149 // automatically synthesizes these stubs.
4150 OpFlags = PPCII::MO_PLT_OR_STUB;
4153 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
4155 needIndirectCall = false;
4159 // We'll form an invalid direct call when lowering a patchpoint; the full
4160 // sequence for an indirect call is complicated, and many of the
4161 // instructions introduced might have side effects (and, thus, can't be
4162 // removed later). The call itself will be removed as soon as the
4163 // argument/return lowering is complete, so the fact that it has the wrong
4164 // kind of operands should not really matter.
4165 needIndirectCall = false;
4168 if (needIndirectCall) {
4169 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
4170 // to do the call, we can't use PPCISD::CALL.
4171 SDValue MTCTROps[] = {Chain, Callee, InFlag};
4173 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
4174 // Function pointers in the 64-bit SVR4 ABI do not point to the function
4175 // entry point, but to the function descriptor (the function entry point
4176 // address is part of the function descriptor though).
4177 // The function descriptor is a three doubleword structure with the
4178 // following fields: function entry point, TOC base address and
4179 // environment pointer.
4180 // Thus for a call through a function pointer, the following actions need
4182 // 1. Save the TOC of the caller in the TOC save area of its stack
4183 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
4184 // 2. Load the address of the function entry point from the function
4186 // 3. Load the TOC of the callee from the function descriptor into r2.
4187 // 4. Load the environment pointer from the function descriptor into
4189 // 5. Branch to the function entry point address.
4190 // 6. On return of the callee, the TOC of the caller needs to be
4191 // restored (this is done in FinishCall()).
4193 // The loads are scheduled at the beginning of the call sequence, and the
4194 // register copies are flagged together to ensure that no other
4195 // operations can be scheduled in between. E.g. without flagging the
4196 // copies together, a TOC access in the caller could be scheduled between
4197 // the assignment of the callee TOC and the branch to the callee, which
4198 // results in the TOC access going through the TOC of the callee instead
4199 // of going through the TOC of the caller, which leads to incorrect code.
4201 // Load the address of the function entry point from the function
4203 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
4204 if (LDChain.getValueType() == MVT::Glue)
4205 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
4207 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
4209 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
4210 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
4211 false, false, LoadsInv, 8);
4213 // Load environment pointer into r11.
4214 SDValue PtrOff = DAG.getIntPtrConstant(16, dl);
4215 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
4216 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
4217 MPI.getWithOffset(16), false, false,
4220 SDValue TOCOff = DAG.getIntPtrConstant(8, dl);
4221 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
4222 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
4223 MPI.getWithOffset(8), false, false,
4226 setUsesTOCBasePtr(DAG);
4227 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
4229 Chain = TOCVal.getValue(0);
4230 InFlag = TOCVal.getValue(1);
4232 // If the function call has an explicit 'nest' parameter, it takes the
4233 // place of the environment pointer.
4235 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
4238 Chain = EnvVal.getValue(0);
4239 InFlag = EnvVal.getValue(1);
4242 MTCTROps[0] = Chain;
4243 MTCTROps[1] = LoadFuncPtr;
4244 MTCTROps[2] = InFlag;
4247 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
4248 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
4249 InFlag = Chain.getValue(1);
4252 NodeTys.push_back(MVT::Other);
4253 NodeTys.push_back(MVT::Glue);
4254 Ops.push_back(Chain);
4255 CallOpc = PPCISD::BCTRL;
4256 Callee.setNode(nullptr);
4257 // Add use of X11 (holding environment pointer)
4258 if (isSVR4ABI && isPPC64 && !isELFv2ABI && !hasNest)
4259 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
4260 // Add CTR register as callee so a bctr can be emitted later.
4262 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
4265 // If this is a direct call, pass the chain and the callee.
4266 if (Callee.getNode()) {
4267 Ops.push_back(Chain);
4268 Ops.push_back(Callee);
4270 // If this is a tail call add stack pointer delta.
4272 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
4274 // Add argument registers to the end of the list so that they are known live
4276 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4277 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4278 RegsToPass[i].second.getValueType()));
4280 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
4282 if (isSVR4ABI && isPPC64 && !IsPatchPoint) {
4283 setUsesTOCBasePtr(DAG);
4284 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
4291 bool isLocalCall(const SDValue &Callee)
4293 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4294 return G->getGlobal()->isStrongDefinitionForLinker();
4299 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
4300 CallingConv::ID CallConv, bool isVarArg,
4301 const SmallVectorImpl<ISD::InputArg> &Ins,
4302 SDLoc dl, SelectionDAG &DAG,
4303 SmallVectorImpl<SDValue> &InVals) const {
4305 SmallVector<CCValAssign, 16> RVLocs;
4306 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
4308 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
4310 // Copy all of the result registers out of their specified physreg.
4311 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4312 CCValAssign &VA = RVLocs[i];
4313 assert(VA.isRegLoc() && "Can only return in registers!");
4315 SDValue Val = DAG.getCopyFromReg(Chain, dl,
4316 VA.getLocReg(), VA.getLocVT(), InFlag);
4317 Chain = Val.getValue(1);
4318 InFlag = Val.getValue(2);
4320 switch (VA.getLocInfo()) {
4321 default: llvm_unreachable("Unknown loc info!");
4322 case CCValAssign::Full: break;
4323 case CCValAssign::AExt:
4324 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4326 case CCValAssign::ZExt:
4327 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
4328 DAG.getValueType(VA.getValVT()));
4329 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4331 case CCValAssign::SExt:
4332 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
4333 DAG.getValueType(VA.getValVT()));
4334 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4338 InVals.push_back(Val);
4345 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
4346 bool isTailCall, bool isVarArg, bool IsPatchPoint,
4347 bool hasNest, SelectionDAG &DAG,
4348 SmallVector<std::pair<unsigned, SDValue>, 8>
4350 SDValue InFlag, SDValue Chain,
4351 SDValue CallSeqStart, SDValue &Callee,
4352 int SPDiff, unsigned NumBytes,
4353 const SmallVectorImpl<ISD::InputArg> &Ins,
4354 SmallVectorImpl<SDValue> &InVals,
4355 ImmutableCallSite *CS) const {
4357 std::vector<EVT> NodeTys;
4358 SmallVector<SDValue, 8> Ops;
4359 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
4360 SPDiff, isTailCall, IsPatchPoint, hasNest,
4361 RegsToPass, Ops, NodeTys, CS, Subtarget);
4363 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
4364 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
4365 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
4367 // When performing tail call optimization the callee pops its arguments off
4368 // the stack. Account for this here so these bytes can be pushed back on in
4369 // PPCFrameLowering::eliminateCallFramePseudoInstr.
4370 int BytesCalleePops =
4371 (CallConv == CallingConv::Fast &&
4372 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
4374 // Add a register mask operand representing the call-preserved registers.
4375 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4376 const uint32_t *Mask =
4377 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
4378 assert(Mask && "Missing call preserved mask for calling convention");
4379 Ops.push_back(DAG.getRegisterMask(Mask));
4381 if (InFlag.getNode())
4382 Ops.push_back(InFlag);
4386 assert(((Callee.getOpcode() == ISD::Register &&
4387 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
4388 Callee.getOpcode() == ISD::TargetExternalSymbol ||
4389 Callee.getOpcode() == ISD::TargetGlobalAddress ||
4390 isa<ConstantSDNode>(Callee)) &&
4391 "Expecting an global address, external symbol, absolute value or register");
4393 DAG.getMachineFunction().getFrameInfo()->setHasTailCall();
4394 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
4397 // Add a NOP immediately after the branch instruction when using the 64-bit
4398 // SVR4 ABI. At link time, if caller and callee are in a different module and
4399 // thus have a different TOC, the call will be replaced with a call to a stub
4400 // function which saves the current TOC, loads the TOC of the callee and
4401 // branches to the callee. The NOP will be replaced with a load instruction
4402 // which restores the TOC of the caller from the TOC save slot of the current
4403 // stack frame. If caller and callee belong to the same module (and have the
4404 // same TOC), the NOP will remain unchanged.
4406 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
4408 if (CallOpc == PPCISD::BCTRL) {
4409 // This is a call through a function pointer.
4410 // Restore the caller TOC from the save area into R2.
4411 // See PrepareCall() for more information about calls through function
4412 // pointers in the 64-bit SVR4 ABI.
4413 // We are using a target-specific load with r2 hard coded, because the
4414 // result of a target-independent load would never go directly into r2,
4415 // since r2 is a reserved register (which prevents the register allocator
4416 // from allocating it), resulting in an additional register being
4417 // allocated and an unnecessary move instruction being generated.
4418 CallOpc = PPCISD::BCTRL_LOAD_TOC;
4420 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4421 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
4422 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
4423 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
4424 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
4426 // The address needs to go after the chain input but before the flag (or
4427 // any other variadic arguments).
4428 Ops.insert(std::next(Ops.begin()), AddTOC);
4429 } else if ((CallOpc == PPCISD::CALL) &&
4430 (!isLocalCall(Callee) ||
4431 DAG.getTarget().getRelocationModel() == Reloc::PIC_))
4432 // Otherwise insert NOP for non-local calls.
4433 CallOpc = PPCISD::CALL_NOP;
4436 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
4437 InFlag = Chain.getValue(1);
4439 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4440 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
4443 InFlag = Chain.getValue(1);
4445 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
4446 Ins, dl, DAG, InVals);
4450 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
4451 SmallVectorImpl<SDValue> &InVals) const {
4452 SelectionDAG &DAG = CLI.DAG;
4454 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
4455 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4456 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4457 SDValue Chain = CLI.Chain;
4458 SDValue Callee = CLI.Callee;
4459 bool &isTailCall = CLI.IsTailCall;
4460 CallingConv::ID CallConv = CLI.CallConv;
4461 bool isVarArg = CLI.IsVarArg;
4462 bool IsPatchPoint = CLI.IsPatchPoint;
4463 ImmutableCallSite *CS = CLI.CS;
4466 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
4469 if (!isTailCall && CS && CS->isMustTailCall())
4470 report_fatal_error("failed to perform tail call elimination on a call "
4471 "site marked musttail");
4473 if (Subtarget.isSVR4ABI()) {
4474 if (Subtarget.isPPC64())
4475 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4476 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4477 dl, DAG, InVals, CS);
4479 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4480 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4481 dl, DAG, InVals, CS);
4484 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4485 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4486 dl, DAG, InVals, CS);
4490 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4491 CallingConv::ID CallConv, bool isVarArg,
4492 bool isTailCall, bool IsPatchPoint,
4493 const SmallVectorImpl<ISD::OutputArg> &Outs,
4494 const SmallVectorImpl<SDValue> &OutVals,
4495 const SmallVectorImpl<ISD::InputArg> &Ins,
4496 SDLoc dl, SelectionDAG &DAG,
4497 SmallVectorImpl<SDValue> &InVals,
4498 ImmutableCallSite *CS) const {
4499 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4500 // of the 32-bit SVR4 ABI stack frame layout.
4502 assert((CallConv == CallingConv::C ||
4503 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4505 unsigned PtrByteSize = 4;
4507 MachineFunction &MF = DAG.getMachineFunction();
4509 // Mark this function as potentially containing a function that contains a
4510 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4511 // and restoring the callers stack pointer in this functions epilog. This is
4512 // done because by tail calling the called function might overwrite the value
4513 // in this function's (MF) stack pointer stack slot 0(SP).
4514 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4515 CallConv == CallingConv::Fast)
4516 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4518 // Count how many bytes are to be pushed on the stack, including the linkage
4519 // area, parameter list area and the part of the local variable space which
4520 // contains copies of aggregates which are passed by value.
4522 // Assign locations to all of the outgoing arguments.
4523 SmallVector<CCValAssign, 16> ArgLocs;
4524 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4527 // Reserve space for the linkage area on the stack.
4528 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
4532 // Handle fixed and variable vector arguments differently.
4533 // Fixed vector arguments go into registers as long as registers are
4534 // available. Variable vector arguments always go into memory.
4535 unsigned NumArgs = Outs.size();
4537 for (unsigned i = 0; i != NumArgs; ++i) {
4538 MVT ArgVT = Outs[i].VT;
4539 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4542 if (Outs[i].IsFixed) {
4543 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4546 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4552 errs() << "Call operand #" << i << " has unhandled type "
4553 << EVT(ArgVT).getEVTString() << "\n";
4555 llvm_unreachable(nullptr);
4559 // All arguments are treated the same.
4560 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4563 // Assign locations to all of the outgoing aggregate by value arguments.
4564 SmallVector<CCValAssign, 16> ByValArgLocs;
4565 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4566 ByValArgLocs, *DAG.getContext());
4568 // Reserve stack space for the allocations in CCInfo.
4569 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4571 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4573 // Size of the linkage area, parameter list area and the part of the local
4574 // space variable where copies of aggregates which are passed by value are
4576 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4578 // Calculate by how many bytes the stack has to be adjusted in case of tail
4579 // call optimization.
4580 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4582 // Adjust the stack pointer for the new arguments...
4583 // These operations are automatically eliminated by the prolog/epilog pass
4584 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4586 SDValue CallSeqStart = Chain;
4588 // Load the return address and frame pointer so it can be moved somewhere else
4591 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4594 // Set up a copy of the stack pointer for use loading and storing any
4595 // arguments that may not fit in the registers available for argument
4597 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4599 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4600 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4601 SmallVector<SDValue, 8> MemOpChains;
4603 bool seenFloatArg = false;
4604 // Walk the register/memloc assignments, inserting copies/loads.
4605 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4608 CCValAssign &VA = ArgLocs[i];
4609 SDValue Arg = OutVals[i];
4610 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4612 if (Flags.isByVal()) {
4613 // Argument is an aggregate which is passed by value, thus we need to
4614 // create a copy of it in the local variable space of the current stack
4615 // frame (which is the stack frame of the caller) and pass the address of
4616 // this copy to the callee.
4617 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4618 CCValAssign &ByValVA = ByValArgLocs[j++];
4619 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4621 // Memory reserved in the local variable space of the callers stack frame.
4622 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4624 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4625 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4628 // Create a copy of the argument in the local area of the current
4630 SDValue MemcpyCall =
4631 CreateCopyOfByValArgument(Arg, PtrOff,
4632 CallSeqStart.getNode()->getOperand(0),
4635 // This must go outside the CALLSEQ_START..END.
4636 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4637 CallSeqStart.getNode()->getOperand(1),
4639 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4640 NewCallSeqStart.getNode());
4641 Chain = CallSeqStart = NewCallSeqStart;
4643 // Pass the address of the aggregate copy on the stack either in a
4644 // physical register or in the parameter list area of the current stack
4645 // frame to the callee.
4649 if (VA.isRegLoc()) {
4650 if (Arg.getValueType() == MVT::i1)
4651 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4653 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4654 // Put argument in a physical register.
4655 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4657 // Put argument in the parameter list area of the current stack frame.
4658 assert(VA.isMemLoc());
4659 unsigned LocMemOffset = VA.getLocMemOffset();
4662 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4663 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4666 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4667 MachinePointerInfo(),
4670 // Calculate and remember argument location.
4671 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4677 if (!MemOpChains.empty())
4678 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4680 // Build a sequence of copy-to-reg nodes chained together with token chain
4681 // and flag operands which copy the outgoing args into the appropriate regs.
4683 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4684 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4685 RegsToPass[i].second, InFlag);
4686 InFlag = Chain.getValue(1);
4689 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4692 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4693 SDValue Ops[] = { Chain, InFlag };
4695 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4696 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4698 InFlag = Chain.getValue(1);
4702 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4703 false, TailCallArguments);
4705 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
4706 /* unused except on PPC64 ELFv1 */ false, DAG,
4707 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4708 NumBytes, Ins, InVals, CS);
4711 // Copy an argument into memory, being careful to do this outside the
4712 // call sequence for the call to which the argument belongs.
4714 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4715 SDValue CallSeqStart,
4716 ISD::ArgFlagsTy Flags,
4719 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4720 CallSeqStart.getNode()->getOperand(0),
4722 // The MEMCPY must go outside the CALLSEQ_START..END.
4723 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4724 CallSeqStart.getNode()->getOperand(1),
4726 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4727 NewCallSeqStart.getNode());
4728 return NewCallSeqStart;
4732 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4733 CallingConv::ID CallConv, bool isVarArg,
4734 bool isTailCall, bool IsPatchPoint,
4735 const SmallVectorImpl<ISD::OutputArg> &Outs,
4736 const SmallVectorImpl<SDValue> &OutVals,
4737 const SmallVectorImpl<ISD::InputArg> &Ins,
4738 SDLoc dl, SelectionDAG &DAG,
4739 SmallVectorImpl<SDValue> &InVals,
4740 ImmutableCallSite *CS) const {
4742 bool isELFv2ABI = Subtarget.isELFv2ABI();
4743 bool isLittleEndian = Subtarget.isLittleEndian();
4744 unsigned NumOps = Outs.size();
4745 bool hasNest = false;
4747 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4748 unsigned PtrByteSize = 8;
4750 MachineFunction &MF = DAG.getMachineFunction();
4752 // Mark this function as potentially containing a function that contains a
4753 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4754 // and restoring the callers stack pointer in this functions epilog. This is
4755 // done because by tail calling the called function might overwrite the value
4756 // in this function's (MF) stack pointer stack slot 0(SP).
4757 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4758 CallConv == CallingConv::Fast)
4759 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4761 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
4762 "fastcc not supported on varargs functions");
4764 // Count how many bytes are to be pushed on the stack, including the linkage
4765 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4766 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4767 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4768 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4769 unsigned NumBytes = LinkageSize;
4770 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4771 unsigned &QFPR_idx = FPR_idx;
4773 static const MCPhysReg GPR[] = {
4774 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4775 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4777 static const MCPhysReg VR[] = {
4778 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4779 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4781 static const MCPhysReg VSRH[] = {
4782 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4783 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4786 const unsigned NumGPRs = array_lengthof(GPR);
4787 const unsigned NumFPRs = 13;
4788 const unsigned NumVRs = array_lengthof(VR);
4789 const unsigned NumQFPRs = NumFPRs;
4791 // When using the fast calling convention, we don't provide backing for
4792 // arguments that will be in registers.
4793 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
4795 // Add up all the space actually used.
4796 for (unsigned i = 0; i != NumOps; ++i) {
4797 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4798 EVT ArgVT = Outs[i].VT;
4799 EVT OrigVT = Outs[i].ArgVT;
4804 if (CallConv == CallingConv::Fast) {
4805 if (Flags.isByVal())
4806 NumGPRsUsed += (Flags.getByValSize()+7)/8;
4808 switch (ArgVT.getSimpleVT().SimpleTy) {
4809 default: llvm_unreachable("Unexpected ValueType for argument!");
4813 if (++NumGPRsUsed <= NumGPRs)
4822 if (++NumVRsUsed <= NumVRs)
4826 // When using QPX, this is handled like a FP register, otherwise, it
4827 // is an Altivec register.
4828 if (Subtarget.hasQPX()) {
4829 if (++NumFPRsUsed <= NumFPRs)
4832 if (++NumVRsUsed <= NumVRs)
4838 case MVT::v4f64: // QPX
4839 case MVT::v4i1: // QPX
4840 if (++NumFPRsUsed <= NumFPRs)
4846 /* Respect alignment of argument on the stack. */
4848 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4849 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4851 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4852 if (Flags.isInConsecutiveRegsLast())
4853 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4856 unsigned NumBytesActuallyUsed = NumBytes;
4858 // The prolog code of the callee may store up to 8 GPR argument registers to
4859 // the stack, allowing va_start to index over them in memory if its varargs.
4860 // Because we cannot tell if this is needed on the caller side, we have to
4861 // conservatively assume that it is needed. As such, make sure we have at
4862 // least enough stack space for the caller to store the 8 GPRs.
4863 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4864 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4866 // Tail call needs the stack to be aligned.
4867 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4868 CallConv == CallingConv::Fast)
4869 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4871 // Calculate by how many bytes the stack has to be adjusted in case of tail
4872 // call optimization.
4873 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4875 // To protect arguments on the stack from being clobbered in a tail call,
4876 // force all the loads to happen before doing any other lowering.
4878 Chain = DAG.getStackArgumentTokenFactor(Chain);
4880 // Adjust the stack pointer for the new arguments...
4881 // These operations are automatically eliminated by the prolog/epilog pass
4882 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4884 SDValue CallSeqStart = Chain;
4886 // Load the return address and frame pointer so it can be move somewhere else
4889 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4892 // Set up a copy of the stack pointer for use loading and storing any
4893 // arguments that may not fit in the registers available for argument
4895 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4897 // Figure out which arguments are going to go in registers, and which in
4898 // memory. Also, if this is a vararg function, floating point operations
4899 // must be stored to our stack, and loaded into integer regs as well, if
4900 // any integer regs are available for argument passing.
4901 unsigned ArgOffset = LinkageSize;
4903 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4904 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4906 SmallVector<SDValue, 8> MemOpChains;
4907 for (unsigned i = 0; i != NumOps; ++i) {
4908 SDValue Arg = OutVals[i];
4909 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4910 EVT ArgVT = Outs[i].VT;
4911 EVT OrigVT = Outs[i].ArgVT;
4913 // PtrOff will be used to store the current argument to the stack if a
4914 // register cannot be found for it.
4917 // We re-align the argument offset for each argument, except when using the
4918 // fast calling convention, when we need to make sure we do that only when
4919 // we'll actually use a stack slot.
4920 auto ComputePtrOff = [&]() {
4921 /* Respect alignment of argument on the stack. */
4923 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4924 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4926 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
4928 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4931 if (CallConv != CallingConv::Fast) {
4934 /* Compute GPR index associated with argument offset. */
4935 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4936 GPR_idx = std::min(GPR_idx, NumGPRs);
4939 // Promote integers to 64-bit values.
4940 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4941 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4942 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4943 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4946 // FIXME memcpy is used way more than necessary. Correctness first.
4947 // Note: "by value" is code for passing a structure by value, not
4949 if (Flags.isByVal()) {
4950 // Note: Size includes alignment padding, so
4951 // struct x { short a; char b; }
4952 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4953 // These are the proper values we need for right-justifying the
4954 // aggregate in a parameter register.
4955 unsigned Size = Flags.getByValSize();
4957 // An empty aggregate parameter takes up no storage and no
4962 if (CallConv == CallingConv::Fast)
4965 // All aggregates smaller than 8 bytes must be passed right-justified.
4966 if (Size==1 || Size==2 || Size==4) {
4967 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4968 if (GPR_idx != NumGPRs) {
4969 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4970 MachinePointerInfo(), VT,
4971 false, false, false, 0);
4972 MemOpChains.push_back(Load.getValue(1));
4973 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4975 ArgOffset += PtrByteSize;
4980 if (GPR_idx == NumGPRs && Size < 8) {
4981 SDValue AddPtr = PtrOff;
4982 if (!isLittleEndian) {
4983 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
4984 PtrOff.getValueType());
4985 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4987 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4990 ArgOffset += PtrByteSize;
4993 // Copy entire object into memory. There are cases where gcc-generated
4994 // code assumes it is there, even if it could be put entirely into
4995 // registers. (This is not what the doc says.)
4997 // FIXME: The above statement is likely due to a misunderstanding of the
4998 // documents. All arguments must be copied into the parameter area BY
4999 // THE CALLEE in the event that the callee takes the address of any
5000 // formal argument. That has not yet been implemented. However, it is
5001 // reasonable to use the stack area as a staging area for the register
5004 // Skip this for small aggregates, as we will use the same slot for a
5005 // right-justified copy, below.
5007 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5011 // When a register is available, pass a small aggregate right-justified.
5012 if (Size < 8 && GPR_idx != NumGPRs) {
5013 // The easiest way to get this right-justified in a register
5014 // is to copy the structure into the rightmost portion of a
5015 // local variable slot, then load the whole slot into the
5017 // FIXME: The memcpy seems to produce pretty awful code for
5018 // small aggregates, particularly for packed ones.
5019 // FIXME: It would be preferable to use the slot in the
5020 // parameter save area instead of a new local variable.
5021 SDValue AddPtr = PtrOff;
5022 if (!isLittleEndian) {
5023 SDValue Const = DAG.getConstant(8 - Size, dl, PtrOff.getValueType());
5024 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5026 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5030 // Load the slot into the register.
5031 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
5032 MachinePointerInfo(),
5033 false, false, false, 0);
5034 MemOpChains.push_back(Load.getValue(1));
5035 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5037 // Done with this argument.
5038 ArgOffset += PtrByteSize;
5042 // For aggregates larger than PtrByteSize, copy the pieces of the
5043 // object that fit into registers from the parameter save area.
5044 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5045 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5046 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5047 if (GPR_idx != NumGPRs) {
5048 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5049 MachinePointerInfo(),
5050 false, false, false, 0);
5051 MemOpChains.push_back(Load.getValue(1));
5052 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5053 ArgOffset += PtrByteSize;
5055 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5062 switch (Arg.getSimpleValueType().SimpleTy) {
5063 default: llvm_unreachable("Unexpected ValueType for argument!");
5067 if (Flags.isNest()) {
5068 // The 'nest' parameter, if any, is passed in R11.
5069 RegsToPass.push_back(std::make_pair(PPC::X11, Arg));
5074 // These can be scalar arguments or elements of an integer array type
5075 // passed directly. Clang may use those instead of "byval" aggregate
5076 // types to avoid forcing arguments to memory unnecessarily.
5077 if (GPR_idx != NumGPRs) {
5078 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5080 if (CallConv == CallingConv::Fast)
5083 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5084 true, isTailCall, false, MemOpChains,
5085 TailCallArguments, dl);
5086 if (CallConv == CallingConv::Fast)
5087 ArgOffset += PtrByteSize;
5089 if (CallConv != CallingConv::Fast)
5090 ArgOffset += PtrByteSize;
5094 // These can be scalar arguments or elements of a float array type
5095 // passed directly. The latter are used to implement ELFv2 homogenous
5096 // float aggregates.
5098 // Named arguments go into FPRs first, and once they overflow, the
5099 // remaining arguments go into GPRs and then the parameter save area.
5100 // Unnamed arguments for vararg functions always go to GPRs and
5101 // then the parameter save area. For now, put all arguments to vararg
5102 // routines always in both locations (FPR *and* GPR or stack slot).
5103 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
5104 bool NeededLoad = false;
5106 // First load the argument into the next available FPR.
5107 if (FPR_idx != NumFPRs)
5108 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5110 // Next, load the argument into GPR or stack slot if needed.
5111 if (!NeedGPROrStack)
5113 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
5114 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
5115 // once we support fp <-> gpr moves.
5117 // In the non-vararg case, this can only ever happen in the
5118 // presence of f32 array types, since otherwise we never run
5119 // out of FPRs before running out of GPRs.
5122 // Double values are always passed in a single GPR.
5123 if (Arg.getValueType() != MVT::f32) {
5124 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
5126 // Non-array float values are extended and passed in a GPR.
5127 } else if (!Flags.isInConsecutiveRegs()) {
5128 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5129 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5131 // If we have an array of floats, we collect every odd element
5132 // together with its predecessor into one GPR.
5133 } else if (ArgOffset % PtrByteSize != 0) {
5135 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
5136 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5137 if (!isLittleEndian)
5139 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5141 // The final element, if even, goes into the first half of a GPR.
5142 } else if (Flags.isInConsecutiveRegsLast()) {
5143 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5144 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5145 if (!isLittleEndian)
5146 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
5147 DAG.getConstant(32, dl, MVT::i32));
5149 // Non-final even elements are skipped; they will be handled
5150 // together the with subsequent argument on the next go-around.
5154 if (ArgVal.getNode())
5155 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
5157 if (CallConv == CallingConv::Fast)
5160 // Single-precision floating-point values are mapped to the
5161 // second (rightmost) word of the stack doubleword.
5162 if (Arg.getValueType() == MVT::f32 &&
5163 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
5164 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5165 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5168 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5169 true, isTailCall, false, MemOpChains,
5170 TailCallArguments, dl);
5174 // When passing an array of floats, the array occupies consecutive
5175 // space in the argument area; only round up to the next doubleword
5176 // at the end of the array. Otherwise, each float takes 8 bytes.
5177 if (CallConv != CallingConv::Fast || NeededLoad) {
5178 ArgOffset += (Arg.getValueType() == MVT::f32 &&
5179 Flags.isInConsecutiveRegs()) ? 4 : 8;
5180 if (Flags.isInConsecutiveRegsLast())
5181 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
5192 if (!Subtarget.hasQPX()) {
5193 // These can be scalar arguments or elements of a vector array type
5194 // passed directly. The latter are used to implement ELFv2 homogenous
5195 // vector aggregates.
5197 // For a varargs call, named arguments go into VRs or on the stack as
5198 // usual; unnamed arguments always go to the stack or the corresponding
5199 // GPRs when within range. For now, we always put the value in both
5200 // locations (or even all three).
5202 // We could elide this store in the case where the object fits
5203 // entirely in R registers. Maybe later.
5204 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5205 MachinePointerInfo(), false, false, 0);
5206 MemOpChains.push_back(Store);
5207 if (VR_idx != NumVRs) {
5208 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5209 MachinePointerInfo(),
5210 false, false, false, 0);
5211 MemOpChains.push_back(Load.getValue(1));
5213 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5214 Arg.getSimpleValueType() == MVT::v2i64) ?
5215 VSRH[VR_idx] : VR[VR_idx];
5218 RegsToPass.push_back(std::make_pair(VReg, Load));
5221 for (unsigned i=0; i<16; i+=PtrByteSize) {
5222 if (GPR_idx == NumGPRs)
5224 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5225 DAG.getConstant(i, dl, PtrVT));
5226 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5227 false, false, false, 0);
5228 MemOpChains.push_back(Load.getValue(1));
5229 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5234 // Non-varargs Altivec params go into VRs or on the stack.
5235 if (VR_idx != NumVRs) {
5236 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5237 Arg.getSimpleValueType() == MVT::v2i64) ?
5238 VSRH[VR_idx] : VR[VR_idx];
5241 RegsToPass.push_back(std::make_pair(VReg, Arg));
5243 if (CallConv == CallingConv::Fast)
5246 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5247 true, isTailCall, true, MemOpChains,
5248 TailCallArguments, dl);
5249 if (CallConv == CallingConv::Fast)
5253 if (CallConv != CallingConv::Fast)
5258 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
5259 "Invalid QPX parameter type");
5264 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;
5266 // We could elide this store in the case where the object fits
5267 // entirely in R registers. Maybe later.
5268 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5269 MachinePointerInfo(), false, false, 0);
5270 MemOpChains.push_back(Store);
5271 if (QFPR_idx != NumQFPRs) {
5272 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl,
5273 Store, PtrOff, MachinePointerInfo(),
5274 false, false, false, 0);
5275 MemOpChains.push_back(Load.getValue(1));
5276 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Load));
5278 ArgOffset += (IsF32 ? 16 : 32);
5279 for (unsigned i = 0; i < (IsF32 ? 16U : 32U); i += PtrByteSize) {
5280 if (GPR_idx == NumGPRs)
5282 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5283 DAG.getConstant(i, dl, PtrVT));
5284 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5285 false, false, false, 0);
5286 MemOpChains.push_back(Load.getValue(1));
5287 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5292 // Non-varargs QPX params go into registers or on the stack.
5293 if (QFPR_idx != NumQFPRs) {
5294 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Arg));
5296 if (CallConv == CallingConv::Fast)
5299 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5300 true, isTailCall, true, MemOpChains,
5301 TailCallArguments, dl);
5302 if (CallConv == CallingConv::Fast)
5303 ArgOffset += (IsF32 ? 16 : 32);
5306 if (CallConv != CallingConv::Fast)
5307 ArgOffset += (IsF32 ? 16 : 32);
5313 assert(NumBytesActuallyUsed == ArgOffset);
5314 (void)NumBytesActuallyUsed;
5316 if (!MemOpChains.empty())
5317 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5319 // Check if this is an indirect call (MTCTR/BCTRL).
5320 // See PrepareCall() for more information about calls through function
5321 // pointers in the 64-bit SVR4 ABI.
5322 if (!isTailCall && !IsPatchPoint &&
5323 !isFunctionGlobalAddress(Callee) &&
5324 !isa<ExternalSymbolSDNode>(Callee)) {
5325 // Load r2 into a virtual register and store it to the TOC save area.
5326 setUsesTOCBasePtr(DAG);
5327 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
5328 // TOC save area offset.
5329 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5330 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5331 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5332 Chain = DAG.getStore(
5333 Val.getValue(1), dl, Val, AddPtr,
5334 MachinePointerInfo::getStack(DAG.getMachineFunction(), TOCSaveOffset),
5336 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
5337 // This does not mean the MTCTR instruction must use R12; it's easier
5338 // to model this as an extra parameter, so do that.
5339 if (isELFv2ABI && !IsPatchPoint)
5340 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
5343 // Build a sequence of copy-to-reg nodes chained together with token chain
5344 // and flag operands which copy the outgoing args into the appropriate regs.
5346 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5347 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5348 RegsToPass[i].second, InFlag);
5349 InFlag = Chain.getValue(1);
5353 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
5354 FPOp, true, TailCallArguments);
5356 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, hasNest,
5357 DAG, RegsToPass, InFlag, Chain, CallSeqStart, Callee,
5358 SPDiff, NumBytes, Ins, InVals, CS);
5362 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
5363 CallingConv::ID CallConv, bool isVarArg,
5364 bool isTailCall, bool IsPatchPoint,
5365 const SmallVectorImpl<ISD::OutputArg> &Outs,
5366 const SmallVectorImpl<SDValue> &OutVals,
5367 const SmallVectorImpl<ISD::InputArg> &Ins,
5368 SDLoc dl, SelectionDAG &DAG,
5369 SmallVectorImpl<SDValue> &InVals,
5370 ImmutableCallSite *CS) const {
5372 unsigned NumOps = Outs.size();
5374 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5375 bool isPPC64 = PtrVT == MVT::i64;
5376 unsigned PtrByteSize = isPPC64 ? 8 : 4;
5378 MachineFunction &MF = DAG.getMachineFunction();
5380 // Mark this function as potentially containing a function that contains a
5381 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5382 // and restoring the callers stack pointer in this functions epilog. This is
5383 // done because by tail calling the called function might overwrite the value
5384 // in this function's (MF) stack pointer stack slot 0(SP).
5385 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5386 CallConv == CallingConv::Fast)
5387 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5389 // Count how many bytes are to be pushed on the stack, including the linkage
5390 // area, and parameter passing area. We start with 24/48 bytes, which is
5391 // prereserved space for [SP][CR][LR][3 x unused].
5392 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5393 unsigned NumBytes = LinkageSize;
5395 // Add up all the space actually used.
5396 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
5397 // they all go in registers, but we must reserve stack space for them for
5398 // possible use by the caller. In varargs or 64-bit calls, parameters are
5399 // assigned stack space in order, with padding so Altivec parameters are
5401 unsigned nAltivecParamsAtEnd = 0;
5402 for (unsigned i = 0; i != NumOps; ++i) {
5403 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5404 EVT ArgVT = Outs[i].VT;
5405 // Varargs Altivec parameters are padded to a 16 byte boundary.
5406 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
5407 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
5408 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
5409 if (!isVarArg && !isPPC64) {
5410 // Non-varargs Altivec parameters go after all the non-Altivec
5411 // parameters; handle those later so we know how much padding we need.
5412 nAltivecParamsAtEnd++;
5415 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
5416 NumBytes = ((NumBytes+15)/16)*16;
5418 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
5421 // Allow for Altivec parameters at the end, if needed.
5422 if (nAltivecParamsAtEnd) {
5423 NumBytes = ((NumBytes+15)/16)*16;
5424 NumBytes += 16*nAltivecParamsAtEnd;
5427 // The prolog code of the callee may store up to 8 GPR argument registers to
5428 // the stack, allowing va_start to index over them in memory if its varargs.
5429 // Because we cannot tell if this is needed on the caller side, we have to
5430 // conservatively assume that it is needed. As such, make sure we have at
5431 // least enough stack space for the caller to store the 8 GPRs.
5432 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
5434 // Tail call needs the stack to be aligned.
5435 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5436 CallConv == CallingConv::Fast)
5437 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
5439 // Calculate by how many bytes the stack has to be adjusted in case of tail
5440 // call optimization.
5441 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5443 // To protect arguments on the stack from being clobbered in a tail call,
5444 // force all the loads to happen before doing any other lowering.
5446 Chain = DAG.getStackArgumentTokenFactor(Chain);
5448 // Adjust the stack pointer for the new arguments...
5449 // These operations are automatically eliminated by the prolog/epilog pass
5450 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5452 SDValue CallSeqStart = Chain;
5454 // Load the return address and frame pointer so it can be move somewhere else
5457 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
5460 // Set up a copy of the stack pointer for use loading and storing any
5461 // arguments that may not fit in the registers available for argument
5465 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5467 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5469 // Figure out which arguments are going to go in registers, and which in
5470 // memory. Also, if this is a vararg function, floating point operations
5471 // must be stored to our stack, and loaded into integer regs as well, if
5472 // any integer regs are available for argument passing.
5473 unsigned ArgOffset = LinkageSize;
5474 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5476 static const MCPhysReg GPR_32[] = { // 32-bit registers.
5477 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
5478 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
5480 static const MCPhysReg GPR_64[] = { // 64-bit registers.
5481 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5482 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5484 static const MCPhysReg VR[] = {
5485 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5486 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5488 const unsigned NumGPRs = array_lengthof(GPR_32);
5489 const unsigned NumFPRs = 13;
5490 const unsigned NumVRs = array_lengthof(VR);
5492 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
5494 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5495 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5497 SmallVector<SDValue, 8> MemOpChains;
5498 for (unsigned i = 0; i != NumOps; ++i) {
5499 SDValue Arg = OutVals[i];
5500 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5502 // PtrOff will be used to store the current argument to the stack if a
5503 // register cannot be found for it.
5506 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
5508 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5510 // On PPC64, promote integers to 64-bit values.
5511 if (isPPC64 && Arg.getValueType() == MVT::i32) {
5512 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
5513 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5514 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
5517 // FIXME memcpy is used way more than necessary. Correctness first.
5518 // Note: "by value" is code for passing a structure by value, not
5520 if (Flags.isByVal()) {
5521 unsigned Size = Flags.getByValSize();
5522 // Very small objects are passed right-justified. Everything else is
5523 // passed left-justified.
5524 if (Size==1 || Size==2) {
5525 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
5526 if (GPR_idx != NumGPRs) {
5527 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5528 MachinePointerInfo(), VT,
5529 false, false, false, 0);
5530 MemOpChains.push_back(Load.getValue(1));
5531 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5533 ArgOffset += PtrByteSize;
5535 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
5536 PtrOff.getValueType());
5537 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5538 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5541 ArgOffset += PtrByteSize;
5545 // Copy entire object into memory. There are cases where gcc-generated
5546 // code assumes it is there, even if it could be put entirely into
5547 // registers. (This is not what the doc says.)
5548 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5552 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5553 // copy the pieces of the object that fit into registers from the
5554 // parameter save area.
5555 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5556 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5557 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5558 if (GPR_idx != NumGPRs) {
5559 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5560 MachinePointerInfo(),
5561 false, false, false, 0);
5562 MemOpChains.push_back(Load.getValue(1));
5563 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5564 ArgOffset += PtrByteSize;
5566 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5573 switch (Arg.getSimpleValueType().SimpleTy) {
5574 default: llvm_unreachable("Unexpected ValueType for argument!");
5578 if (GPR_idx != NumGPRs) {
5579 if (Arg.getValueType() == MVT::i1)
5580 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5582 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5584 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5585 isPPC64, isTailCall, false, MemOpChains,
5586 TailCallArguments, dl);
5588 ArgOffset += PtrByteSize;
5592 if (FPR_idx != NumFPRs) {
5593 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5596 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5597 MachinePointerInfo(), false, false, 0);
5598 MemOpChains.push_back(Store);
5600 // Float varargs are always shadowed in available integer registers
5601 if (GPR_idx != NumGPRs) {
5602 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5603 MachinePointerInfo(), false, false,
5605 MemOpChains.push_back(Load.getValue(1));
5606 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5608 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5609 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5610 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5611 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5612 MachinePointerInfo(),
5613 false, false, false, 0);
5614 MemOpChains.push_back(Load.getValue(1));
5615 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5618 // If we have any FPRs remaining, we may also have GPRs remaining.
5619 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5621 if (GPR_idx != NumGPRs)
5623 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5624 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5628 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5629 isPPC64, isTailCall, false, MemOpChains,
5630 TailCallArguments, dl);
5634 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5641 // These go aligned on the stack, or in the corresponding R registers
5642 // when within range. The Darwin PPC ABI doc claims they also go in
5643 // V registers; in fact gcc does this only for arguments that are
5644 // prototyped, not for those that match the ... We do it for all
5645 // arguments, seems to work.
5646 while (ArgOffset % 16 !=0) {
5647 ArgOffset += PtrByteSize;
5648 if (GPR_idx != NumGPRs)
5651 // We could elide this store in the case where the object fits
5652 // entirely in R registers. Maybe later.
5653 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5654 DAG.getConstant(ArgOffset, dl, PtrVT));
5655 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5656 MachinePointerInfo(), false, false, 0);
5657 MemOpChains.push_back(Store);
5658 if (VR_idx != NumVRs) {
5659 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5660 MachinePointerInfo(),
5661 false, false, false, 0);
5662 MemOpChains.push_back(Load.getValue(1));
5663 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5666 for (unsigned i=0; i<16; i+=PtrByteSize) {
5667 if (GPR_idx == NumGPRs)
5669 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5670 DAG.getConstant(i, dl, PtrVT));
5671 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5672 false, false, false, 0);
5673 MemOpChains.push_back(Load.getValue(1));
5674 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5679 // Non-varargs Altivec params generally go in registers, but have
5680 // stack space allocated at the end.
5681 if (VR_idx != NumVRs) {
5682 // Doesn't have GPR space allocated.
5683 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5684 } else if (nAltivecParamsAtEnd==0) {
5685 // We are emitting Altivec params in order.
5686 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5687 isPPC64, isTailCall, true, MemOpChains,
5688 TailCallArguments, dl);
5694 // If all Altivec parameters fit in registers, as they usually do,
5695 // they get stack space following the non-Altivec parameters. We
5696 // don't track this here because nobody below needs it.
5697 // If there are more Altivec parameters than fit in registers emit
5699 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5701 // Offset is aligned; skip 1st 12 params which go in V registers.
5702 ArgOffset = ((ArgOffset+15)/16)*16;
5704 for (unsigned i = 0; i != NumOps; ++i) {
5705 SDValue Arg = OutVals[i];
5706 EVT ArgType = Outs[i].VT;
5707 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5708 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5711 // We are emitting Altivec params in order.
5712 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5713 isPPC64, isTailCall, true, MemOpChains,
5714 TailCallArguments, dl);
5721 if (!MemOpChains.empty())
5722 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5724 // On Darwin, R12 must contain the address of an indirect callee. This does
5725 // not mean the MTCTR instruction must use R12; it's easier to model this as
5726 // an extra parameter, so do that.
5728 !isFunctionGlobalAddress(Callee) &&
5729 !isa<ExternalSymbolSDNode>(Callee) &&
5730 !isBLACompatibleAddress(Callee, DAG))
5731 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5732 PPC::R12), Callee));
5734 // Build a sequence of copy-to-reg nodes chained together with token chain
5735 // and flag operands which copy the outgoing args into the appropriate regs.
5737 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5738 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5739 RegsToPass[i].second, InFlag);
5740 InFlag = Chain.getValue(1);
5744 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5745 FPOp, true, TailCallArguments);
5747 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
5748 /* unused except on PPC64 ELFv1 */ false, DAG,
5749 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5750 NumBytes, Ins, InVals, CS);
5754 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5755 MachineFunction &MF, bool isVarArg,
5756 const SmallVectorImpl<ISD::OutputArg> &Outs,
5757 LLVMContext &Context) const {
5758 SmallVector<CCValAssign, 16> RVLocs;
5759 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5760 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5764 PPCTargetLowering::LowerReturn(SDValue Chain,
5765 CallingConv::ID CallConv, bool isVarArg,
5766 const SmallVectorImpl<ISD::OutputArg> &Outs,
5767 const SmallVectorImpl<SDValue> &OutVals,
5768 SDLoc dl, SelectionDAG &DAG) const {
5770 SmallVector<CCValAssign, 16> RVLocs;
5771 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5773 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5776 SmallVector<SDValue, 4> RetOps(1, Chain);
5778 // Copy the result values into the output registers.
5779 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5780 CCValAssign &VA = RVLocs[i];
5781 assert(VA.isRegLoc() && "Can only return in registers!");
5783 SDValue Arg = OutVals[i];
5785 switch (VA.getLocInfo()) {
5786 default: llvm_unreachable("Unknown loc info!");
5787 case CCValAssign::Full: break;
5788 case CCValAssign::AExt:
5789 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5791 case CCValAssign::ZExt:
5792 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5794 case CCValAssign::SExt:
5795 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5799 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5800 Flag = Chain.getValue(1);
5801 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5804 RetOps[0] = Chain; // Update chain.
5806 // Add the flag if we have it.
5808 RetOps.push_back(Flag);
5810 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5813 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5814 const PPCSubtarget &Subtarget) const {
5815 // When we pop the dynamic allocation we need to restore the SP link.
5818 // Get the corect type for pointers.
5819 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5821 // Construct the stack pointer operand.
5822 bool isPPC64 = Subtarget.isPPC64();
5823 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5824 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5826 // Get the operands for the STACKRESTORE.
5827 SDValue Chain = Op.getOperand(0);
5828 SDValue SaveSP = Op.getOperand(1);
5830 // Load the old link SP.
5831 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5832 MachinePointerInfo(),
5833 false, false, false, 0);
5835 // Restore the stack pointer.
5836 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5838 // Store the old link SP.
5839 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5843 SDValue PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG &DAG) const {
5844 MachineFunction &MF = DAG.getMachineFunction();
5845 bool isPPC64 = Subtarget.isPPC64();
5846 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
5848 // Get current frame pointer save index. The users of this index will be
5849 // primarily DYNALLOC instructions.
5850 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5851 int RASI = FI->getReturnAddrSaveIndex();
5853 // If the frame pointer save index hasn't been defined yet.
5855 // Find out what the fix offset of the frame pointer save area.
5856 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset();
5857 // Allocate the frame index for frame pointer save area.
5858 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5860 FI->setReturnAddrSaveIndex(RASI);
5862 return DAG.getFrameIndex(RASI, PtrVT);
5866 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5867 MachineFunction &MF = DAG.getMachineFunction();
5868 bool isPPC64 = Subtarget.isPPC64();
5869 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
5871 // Get current frame pointer save index. The users of this index will be
5872 // primarily DYNALLOC instructions.
5873 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5874 int FPSI = FI->getFramePointerSaveIndex();
5876 // If the frame pointer save index hasn't been defined yet.
5878 // Find out what the fix offset of the frame pointer save area.
5879 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset();
5880 // Allocate the frame index for frame pointer save area.
5881 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5883 FI->setFramePointerSaveIndex(FPSI);
5885 return DAG.getFrameIndex(FPSI, PtrVT);
5888 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5890 const PPCSubtarget &Subtarget) const {
5892 SDValue Chain = Op.getOperand(0);
5893 SDValue Size = Op.getOperand(1);
5896 // Get the corect type for pointers.
5897 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5899 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5900 DAG.getConstant(0, dl, PtrVT), Size);
5901 // Construct a node for the frame pointer save index.
5902 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5903 // Build a DYNALLOC node.
5904 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5905 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5906 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5909 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5910 SelectionDAG &DAG) const {
5912 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5913 DAG.getVTList(MVT::i32, MVT::Other),
5914 Op.getOperand(0), Op.getOperand(1));
5917 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5918 SelectionDAG &DAG) const {
5920 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5921 Op.getOperand(0), Op.getOperand(1));
5924 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5925 if (Op.getValueType().isVector())
5926 return LowerVectorLoad(Op, DAG);
5928 assert(Op.getValueType() == MVT::i1 &&
5929 "Custom lowering only for i1 loads");
5931 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5934 LoadSDNode *LD = cast<LoadSDNode>(Op);
5936 SDValue Chain = LD->getChain();
5937 SDValue BasePtr = LD->getBasePtr();
5938 MachineMemOperand *MMO = LD->getMemOperand();
5941 DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(DAG.getDataLayout()), Chain,
5942 BasePtr, MVT::i8, MMO);
5943 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5945 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5946 return DAG.getMergeValues(Ops, dl);
5949 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5950 if (Op.getOperand(1).getValueType().isVector())
5951 return LowerVectorStore(Op, DAG);
5953 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5954 "Custom lowering only for i1 stores");
5956 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5959 StoreSDNode *ST = cast<StoreSDNode>(Op);
5961 SDValue Chain = ST->getChain();
5962 SDValue BasePtr = ST->getBasePtr();
5963 SDValue Value = ST->getValue();
5964 MachineMemOperand *MMO = ST->getMemOperand();
5966 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(DAG.getDataLayout()),
5968 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5971 // FIXME: Remove this once the ANDI glue bug is fixed:
5972 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5973 assert(Op.getValueType() == MVT::i1 &&
5974 "Custom lowering only for i1 results");
5977 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5981 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5983 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5984 // Not FP? Not a fsel.
5985 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5986 !Op.getOperand(2).getValueType().isFloatingPoint())
5989 // We might be able to do better than this under some circumstances, but in
5990 // general, fsel-based lowering of select is a finite-math-only optimization.
5991 // For more information, see section F.3 of the 2.06 ISA specification.
5992 if (!DAG.getTarget().Options.NoInfsFPMath ||
5993 !DAG.getTarget().Options.NoNaNsFPMath)
5995 // TODO: Propagate flags from the select rather than global settings.
5997 Flags.setNoInfs(true);
5998 Flags.setNoNaNs(true);
6000 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
6002 EVT ResVT = Op.getValueType();
6003 EVT CmpVT = Op.getOperand(0).getValueType();
6004 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6005 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
6008 // If the RHS of the comparison is a 0.0, we don't need to do the
6009 // subtraction at all.
6011 if (isFloatingPointZero(RHS))
6013 default: break; // SETUO etc aren't handled by fsel.
6017 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6018 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6019 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6020 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6021 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6022 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6023 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
6026 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6029 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6030 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6031 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6034 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6037 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6038 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6039 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6040 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
6045 default: break; // SETUO etc aren't handled by fsel.
6049 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6050 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6051 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6052 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6053 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6054 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6055 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6056 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
6059 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6060 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6061 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6062 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6065 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6066 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6067 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6068 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6071 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, &Flags);
6072 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6073 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6074 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6077 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, &Flags);
6078 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6079 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6080 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6085 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
6088 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6089 SDValue Src = Op.getOperand(0);
6090 if (Src.getValueType() == MVT::f32)
6091 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6094 switch (Op.getSimpleValueType().SimpleTy) {
6095 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6098 Op.getOpcode() == ISD::FP_TO_SINT
6100 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6104 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6105 "i64 FP_TO_UINT is supported only with FPCVT");
6106 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6112 // Convert the FP value to an int value through memory.
6113 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
6114 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
6115 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
6116 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
6117 MachinePointerInfo MPI =
6118 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
6120 // Emit a store to the stack slot.
6123 MachineFunction &MF = DAG.getMachineFunction();
6124 MachineMemOperand *MMO =
6125 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
6126 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
6127 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
6128 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
6130 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
6131 MPI, false, false, 0);
6133 // Result is a load from the stack slot. If loading 4 bytes, make sure to
6135 if (Op.getValueType() == MVT::i32 && !i32Stack) {
6136 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
6137 DAG.getConstant(4, dl, FIPtr.getValueType()));
6138 MPI = MPI.getWithOffset(4);
6146 /// \brief Custom lowers floating point to integer conversions to use
6147 /// the direct move instructions available in ISA 2.07 to avoid the
6148 /// need for load/store combinations.
6149 SDValue PPCTargetLowering::LowerFP_TO_INTDirectMove(SDValue Op,
6152 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6153 SDValue Src = Op.getOperand(0);
6155 if (Src.getValueType() == MVT::f32)
6156 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6159 switch (Op.getSimpleValueType().SimpleTy) {
6160 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6163 Op.getOpcode() == ISD::FP_TO_SINT
6165 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6167 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp);
6170 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6171 "i64 FP_TO_UINT is supported only with FPCVT");
6172 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6175 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp);
6181 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
6183 if (Subtarget.hasDirectMove() && Subtarget.isPPC64())
6184 return LowerFP_TO_INTDirectMove(Op, DAG, dl);
6187 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6189 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6190 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6194 // We're trying to insert a regular store, S, and then a load, L. If the
6195 // incoming value, O, is a load, we might just be able to have our load use the
6196 // address used by O. However, we don't know if anything else will store to
6197 // that address before we can load from it. To prevent this situation, we need
6198 // to insert our load, L, into the chain as a peer of O. To do this, we give L
6199 // the same chain operand as O, we create a token factor from the chain results
6200 // of O and L, and we replace all uses of O's chain result with that token
6201 // factor (see spliceIntoChain below for this last part).
6202 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
6205 ISD::LoadExtType ET) const {
6207 if (ET == ISD::NON_EXTLOAD &&
6208 (Op.getOpcode() == ISD::FP_TO_UINT ||
6209 Op.getOpcode() == ISD::FP_TO_SINT) &&
6210 isOperationLegalOrCustom(Op.getOpcode(),
6211 Op.getOperand(0).getValueType())) {
6213 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6217 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
6218 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
6219 LD->isNonTemporal())
6221 if (LD->getMemoryVT() != MemVT)
6224 RLI.Ptr = LD->getBasePtr();
6225 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
6226 assert(LD->getAddressingMode() == ISD::PRE_INC &&
6227 "Non-pre-inc AM on PPC?");
6228 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
6232 RLI.Chain = LD->getChain();
6233 RLI.MPI = LD->getPointerInfo();
6234 RLI.IsInvariant = LD->isInvariant();
6235 RLI.Alignment = LD->getAlignment();
6236 RLI.AAInfo = LD->getAAInfo();
6237 RLI.Ranges = LD->getRanges();
6239 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
6243 // Given the head of the old chain, ResChain, insert a token factor containing
6244 // it and NewResChain, and make users of ResChain now be users of that token
6246 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
6247 SDValue NewResChain,
6248 SelectionDAG &DAG) const {
6252 SDLoc dl(NewResChain);
6254 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6255 NewResChain, DAG.getUNDEF(MVT::Other));
6256 assert(TF.getNode() != NewResChain.getNode() &&
6257 "A new TF really is required here");
6259 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
6260 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
6263 /// \brief Custom lowers integer to floating point conversions to use
6264 /// the direct move instructions available in ISA 2.07 to avoid the
6265 /// need for load/store combinations.
6266 SDValue PPCTargetLowering::LowerINT_TO_FPDirectMove(SDValue Op,
6269 assert((Op.getValueType() == MVT::f32 ||
6270 Op.getValueType() == MVT::f64) &&
6271 "Invalid floating point type as target of conversion");
6272 assert(Subtarget.hasFPCVT() &&
6273 "Int to FP conversions with direct moves require FPCVT");
6275 SDValue Src = Op.getOperand(0);
6276 bool SinglePrec = Op.getValueType() == MVT::f32;
6277 bool WordInt = Src.getSimpleValueType().SimpleTy == MVT::i32;
6278 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP;
6279 unsigned ConvOp = Signed ? (SinglePrec ? PPCISD::FCFIDS : PPCISD::FCFID) :
6280 (SinglePrec ? PPCISD::FCFIDUS : PPCISD::FCFIDU);
6283 FP = DAG.getNode(Signed ? PPCISD::MTVSRA : PPCISD::MTVSRZ,
6285 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6288 FP = DAG.getNode(PPCISD::MTVSRA, dl, MVT::f64, Src);
6289 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6295 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
6296 SelectionDAG &DAG) const {
6299 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) {
6300 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64)
6303 SDValue Value = Op.getOperand(0);
6304 // The values are now known to be -1 (false) or 1 (true). To convert this
6305 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
6306 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
6307 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
6309 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
6310 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64, FPHalfs, FPHalfs,
6313 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
6315 if (Op.getValueType() != MVT::v4f64)
6316 Value = DAG.getNode(ISD::FP_ROUND, dl,
6317 Op.getValueType(), Value,
6318 DAG.getIntPtrConstant(1, dl));
6322 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
6323 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
6326 if (Op.getOperand(0).getValueType() == MVT::i1)
6327 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
6328 DAG.getConstantFP(1.0, dl, Op.getValueType()),
6329 DAG.getConstantFP(0.0, dl, Op.getValueType()));
6331 // If we have direct moves, we can do all the conversion, skip the store/load
6332 // however, without FPCVT we can't do most conversions.
6333 if (Subtarget.hasDirectMove() && Subtarget.isPPC64() && Subtarget.hasFPCVT())
6334 return LowerINT_TO_FPDirectMove(Op, DAG, dl);
6336 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
6337 "UINT_TO_FP is supported only with FPCVT");
6339 // If we have FCFIDS, then use it when converting to single-precision.
6340 // Otherwise, convert to double-precision and then round.
6341 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6342 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
6344 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
6346 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6350 if (Op.getOperand(0).getValueType() == MVT::i64) {
6351 SDValue SINT = Op.getOperand(0);
6352 // When converting to single-precision, we actually need to convert
6353 // to double-precision first and then round to single-precision.
6354 // To avoid double-rounding effects during that operation, we have
6355 // to prepare the input operand. Bits that might be truncated when
6356 // converting to double-precision are replaced by a bit that won't
6357 // be lost at this stage, but is below the single-precision rounding
6360 // However, if -enable-unsafe-fp-math is in effect, accept double
6361 // rounding to avoid the extra overhead.
6362 if (Op.getValueType() == MVT::f32 &&
6363 !Subtarget.hasFPCVT() &&
6364 !DAG.getTarget().Options.UnsafeFPMath) {
6366 // Twiddle input to make sure the low 11 bits are zero. (If this
6367 // is the case, we are guaranteed the value will fit into the 53 bit
6368 // mantissa of an IEEE double-precision value without rounding.)
6369 // If any of those low 11 bits were not zero originally, make sure
6370 // bit 12 (value 2048) is set instead, so that the final rounding
6371 // to single-precision gets the correct result.
6372 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6373 SINT, DAG.getConstant(2047, dl, MVT::i64));
6374 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
6375 Round, DAG.getConstant(2047, dl, MVT::i64));
6376 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
6377 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6378 Round, DAG.getConstant(-2048, dl, MVT::i64));
6380 // However, we cannot use that value unconditionally: if the magnitude
6381 // of the input value is small, the bit-twiddling we did above might
6382 // end up visibly changing the output. Fortunately, in that case, we
6383 // don't need to twiddle bits since the original input will convert
6384 // exactly to double-precision floating-point already. Therefore,
6385 // construct a conditional to use the original value if the top 11
6386 // bits are all sign-bit copies, and use the rounded value computed
6388 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
6389 SINT, DAG.getConstant(53, dl, MVT::i32));
6390 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
6391 Cond, DAG.getConstant(1, dl, MVT::i64));
6392 Cond = DAG.getSetCC(dl, MVT::i32,
6393 Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT);
6395 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
6401 MachineFunction &MF = DAG.getMachineFunction();
6402 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
6403 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6404 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6406 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6407 } else if (Subtarget.hasLFIWAX() &&
6408 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
6409 MachineMemOperand *MMO =
6410 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6411 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6412 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6413 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
6414 DAG.getVTList(MVT::f64, MVT::Other),
6415 Ops, MVT::i32, MMO);
6416 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6417 } else if (Subtarget.hasFPCVT() &&
6418 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
6419 MachineMemOperand *MMO =
6420 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6421 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6422 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6423 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
6424 DAG.getVTList(MVT::f64, MVT::Other),
6425 Ops, MVT::i32, MMO);
6426 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6427 } else if (((Subtarget.hasLFIWAX() &&
6428 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
6429 (Subtarget.hasFPCVT() &&
6430 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
6431 SINT.getOperand(0).getValueType() == MVT::i32) {
6432 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6433 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
6435 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6436 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6438 SDValue Store = DAG.getStore(
6439 DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
6440 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6443 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6444 "Expected an i32 store");
6449 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6452 MachineMemOperand *MMO =
6453 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6454 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6455 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6456 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
6457 PPCISD::LFIWZX : PPCISD::LFIWAX,
6458 dl, DAG.getVTList(MVT::f64, MVT::Other),
6459 Ops, MVT::i32, MMO);
6461 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
6463 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
6465 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6466 FP = DAG.getNode(ISD::FP_ROUND, dl,
6467 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
6471 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
6472 "Unhandled INT_TO_FP type in custom expander!");
6473 // Since we only generate this in 64-bit mode, we can take advantage of
6474 // 64-bit registers. In particular, sign extend the input value into the
6475 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
6476 // then lfd it and fcfid it.
6477 MachineFunction &MF = DAG.getMachineFunction();
6478 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6479 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
6482 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
6485 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
6487 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6488 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6490 SDValue Store = DAG.getStore(
6491 DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
6492 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6495 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6496 "Expected an i32 store");
6501 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6505 MachineMemOperand *MMO =
6506 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6507 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6508 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6509 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
6510 PPCISD::LFIWZX : PPCISD::LFIWAX,
6511 dl, DAG.getVTList(MVT::f64, MVT::Other),
6512 Ops, MVT::i32, MMO);
6514 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
6516 assert(Subtarget.isPPC64() &&
6517 "i32->FP without LFIWAX supported only on PPC64");
6519 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
6520 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6522 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
6525 // STD the extended value into the stack slot.
6526 SDValue Store = DAG.getStore(
6527 DAG.getEntryNode(), dl, Ext64, FIdx,
6528 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6531 // Load the value as a double.
6533 MVT::f64, dl, Store, FIdx,
6534 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6535 false, false, false, 0);
6538 // FCFID it and return it.
6539 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
6540 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6541 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
6542 DAG.getIntPtrConstant(0, dl));
6546 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
6547 SelectionDAG &DAG) const {
6550 The rounding mode is in bits 30:31 of FPSR, and has the following
6557 FLT_ROUNDS, on the other hand, expects the following:
6564 To perform the conversion, we do:
6565 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
6568 MachineFunction &MF = DAG.getMachineFunction();
6569 EVT VT = Op.getValueType();
6570 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
6572 // Save FP Control Word to register
6574 MVT::f64, // return register
6575 MVT::Glue // unused in this context
6577 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
6579 // Save FP register to stack slot
6580 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
6581 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
6582 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
6583 StackSlot, MachinePointerInfo(), false, false,0);
6585 // Load FP Control Word from low 32 bits of stack slot.
6586 SDValue Four = DAG.getConstant(4, dl, PtrVT);
6587 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
6588 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
6589 false, false, false, 0);
6591 // Transform as necessary
6593 DAG.getNode(ISD::AND, dl, MVT::i32,
6594 CWD, DAG.getConstant(3, dl, MVT::i32));
6596 DAG.getNode(ISD::SRL, dl, MVT::i32,
6597 DAG.getNode(ISD::AND, dl, MVT::i32,
6598 DAG.getNode(ISD::XOR, dl, MVT::i32,
6599 CWD, DAG.getConstant(3, dl, MVT::i32)),
6600 DAG.getConstant(3, dl, MVT::i32)),
6601 DAG.getConstant(1, dl, MVT::i32));
6604 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
6606 return DAG.getNode((VT.getSizeInBits() < 16 ?
6607 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6610 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6611 EVT VT = Op.getValueType();
6612 unsigned BitWidth = VT.getSizeInBits();
6614 assert(Op.getNumOperands() == 3 &&
6615 VT == Op.getOperand(1).getValueType() &&
6618 // Expand into a bunch of logical ops. Note that these ops
6619 // depend on the PPC behavior for oversized shift amounts.
6620 SDValue Lo = Op.getOperand(0);
6621 SDValue Hi = Op.getOperand(1);
6622 SDValue Amt = Op.getOperand(2);
6623 EVT AmtVT = Amt.getValueType();
6625 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6626 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6627 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
6628 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
6629 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
6630 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6631 DAG.getConstant(-BitWidth, dl, AmtVT));
6632 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
6633 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6634 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
6635 SDValue OutOps[] = { OutLo, OutHi };
6636 return DAG.getMergeValues(OutOps, dl);
6639 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6640 EVT VT = Op.getValueType();
6642 unsigned BitWidth = VT.getSizeInBits();
6643 assert(Op.getNumOperands() == 3 &&
6644 VT == Op.getOperand(1).getValueType() &&
6647 // Expand into a bunch of logical ops. Note that these ops
6648 // depend on the PPC behavior for oversized shift amounts.
6649 SDValue Lo = Op.getOperand(0);
6650 SDValue Hi = Op.getOperand(1);
6651 SDValue Amt = Op.getOperand(2);
6652 EVT AmtVT = Amt.getValueType();
6654 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6655 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6656 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6657 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6658 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6659 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6660 DAG.getConstant(-BitWidth, dl, AmtVT));
6661 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
6662 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6663 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
6664 SDValue OutOps[] = { OutLo, OutHi };
6665 return DAG.getMergeValues(OutOps, dl);
6668 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6670 EVT VT = Op.getValueType();
6671 unsigned BitWidth = VT.getSizeInBits();
6672 assert(Op.getNumOperands() == 3 &&
6673 VT == Op.getOperand(1).getValueType() &&
6676 // Expand into a bunch of logical ops, followed by a select_cc.
6677 SDValue Lo = Op.getOperand(0);
6678 SDValue Hi = Op.getOperand(1);
6679 SDValue Amt = Op.getOperand(2);
6680 EVT AmtVT = Amt.getValueType();
6682 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6683 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6684 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6685 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6686 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6687 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6688 DAG.getConstant(-BitWidth, dl, AmtVT));
6689 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
6690 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
6691 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, dl, AmtVT),
6692 Tmp4, Tmp6, ISD::SETLE);
6693 SDValue OutOps[] = { OutLo, OutHi };
6694 return DAG.getMergeValues(OutOps, dl);
6697 //===----------------------------------------------------------------------===//
6698 // Vector related lowering.
6701 /// BuildSplatI - Build a canonical splati of Val with an element size of
6702 /// SplatSize. Cast the result to VT.
6703 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6704 SelectionDAG &DAG, SDLoc dl) {
6705 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
6707 static const MVT VTys[] = { // canonical VT to use for each size.
6708 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6711 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
6713 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
6717 EVT CanonicalVT = VTys[SplatSize-1];
6719 // Build a canonical splat for this value.
6720 SDValue Elt = DAG.getConstant(Val, dl, MVT::i32);
6721 SmallVector<SDValue, 8> Ops;
6722 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
6723 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
6724 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
6727 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
6728 /// specified intrinsic ID.
6729 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6730 SelectionDAG &DAG, SDLoc dl,
6731 EVT DestVT = MVT::Other) {
6732 if (DestVT == MVT::Other) DestVT = Op.getValueType();
6733 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6734 DAG.getConstant(IID, dl, MVT::i32), Op);
6737 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
6738 /// specified intrinsic ID.
6739 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6740 SelectionDAG &DAG, SDLoc dl,
6741 EVT DestVT = MVT::Other) {
6742 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
6743 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6744 DAG.getConstant(IID, dl, MVT::i32), LHS, RHS);
6747 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
6748 /// specified intrinsic ID.
6749 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6750 SDValue Op2, SelectionDAG &DAG,
6751 SDLoc dl, EVT DestVT = MVT::Other) {
6752 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6753 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6754 DAG.getConstant(IID, dl, MVT::i32), Op0, Op1, Op2);
6757 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6758 /// amount. The result has the specified value type.
6759 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6760 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6761 // Force LHS/RHS to be the right type.
6762 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6763 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6766 for (unsigned i = 0; i != 16; ++i)
6768 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6769 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6772 // If this is a case we can't handle, return null and let the default
6773 // expansion code take care of it. If we CAN select this case, and if it
6774 // selects to a single instruction, return Op. Otherwise, if we can codegen
6775 // this case more efficiently than a constant pool load, lower it to the
6776 // sequence of ops that should be used.
6777 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6778 SelectionDAG &DAG) const {
6780 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6781 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6783 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) {
6784 // We first build an i32 vector, load it into a QPX register,
6785 // then convert it to a floating-point vector and compare it
6786 // to a zero vector to get the boolean result.
6787 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6788 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6789 MachinePointerInfo PtrInfo =
6790 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6791 EVT PtrVT = getPointerTy(DAG.getDataLayout());
6792 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6794 assert(BVN->getNumOperands() == 4 &&
6795 "BUILD_VECTOR for v4i1 does not have 4 operands");
6797 bool IsConst = true;
6798 for (unsigned i = 0; i < 4; ++i) {
6799 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6800 if (!isa<ConstantSDNode>(BVN->getOperand(i))) {
6808 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), 1.0);
6810 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), -1.0);
6812 SmallVector<Constant*, 4> CV(4, NegOne);
6813 for (unsigned i = 0; i < 4; ++i) {
6814 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF)
6815 CV[i] = UndefValue::get(Type::getFloatTy(*DAG.getContext()));
6816 else if (cast<ConstantSDNode>(BVN->getOperand(i))->
6817 getConstantIntValue()->isZero())
6823 Constant *CP = ConstantVector::get(CV);
6824 SDValue CPIdx = DAG.getConstantPool(CP, getPointerTy(DAG.getDataLayout()),
6825 16 /* alignment */);
6827 SmallVector<SDValue, 2> Ops;
6828 Ops.push_back(DAG.getEntryNode());
6829 Ops.push_back(CPIdx);
6831 SmallVector<EVT, 2> ValueVTs;
6832 ValueVTs.push_back(MVT::v4i1);
6833 ValueVTs.push_back(MVT::Other); // chain
6834 SDVTList VTs = DAG.getVTList(ValueVTs);
6836 return DAG.getMemIntrinsicNode(
6837 PPCISD::QVLFSb, dl, VTs, Ops, MVT::v4f32,
6838 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
6841 SmallVector<SDValue, 4> Stores;
6842 for (unsigned i = 0; i < 4; ++i) {
6843 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6845 unsigned Offset = 4*i;
6846 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
6847 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
6849 unsigned StoreSize = BVN->getOperand(i).getValueType().getStoreSize();
6850 if (StoreSize > 4) {
6851 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
6852 BVN->getOperand(i), Idx,
6853 PtrInfo.getWithOffset(Offset),
6854 MVT::i32, false, false, 0));
6856 SDValue StoreValue = BVN->getOperand(i);
6858 StoreValue = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, StoreValue);
6860 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
6862 PtrInfo.getWithOffset(Offset),
6868 if (!Stores.empty())
6869 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
6871 StoreChain = DAG.getEntryNode();
6873 // Now load from v4i32 into the QPX register; this will extend it to
6874 // v4i64 but not yet convert it to a floating point. Nevertheless, this
6875 // is typed as v4f64 because the QPX register integer states are not
6876 // explicitly represented.
6878 SmallVector<SDValue, 2> Ops;
6879 Ops.push_back(StoreChain);
6880 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvlfiwz, dl, MVT::i32));
6881 Ops.push_back(FIdx);
6883 SmallVector<EVT, 2> ValueVTs;
6884 ValueVTs.push_back(MVT::v4f64);
6885 ValueVTs.push_back(MVT::Other); // chain
6886 SDVTList VTs = DAG.getVTList(ValueVTs);
6888 SDValue LoadedVect = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN,
6889 dl, VTs, Ops, MVT::v4i32, PtrInfo);
6890 LoadedVect = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
6891 DAG.getConstant(Intrinsic::ppc_qpx_qvfcfidu, dl, MVT::i32),
6894 SDValue FPZeros = DAG.getConstantFP(0.0, dl, MVT::f64);
6895 FPZeros = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6896 FPZeros, FPZeros, FPZeros, FPZeros);
6898 return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ);
6901 // All other QPX vectors are handled by generic code.
6902 if (Subtarget.hasQPX())
6905 // Check if this is a splat of a constant value.
6906 APInt APSplatBits, APSplatUndef;
6907 unsigned SplatBitSize;
6909 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6910 HasAnyUndefs, 0, !Subtarget.isLittleEndian()) ||
6914 unsigned SplatBits = APSplatBits.getZExtValue();
6915 unsigned SplatUndef = APSplatUndef.getZExtValue();
6916 unsigned SplatSize = SplatBitSize / 8;
6918 // First, handle single instruction cases.
6921 if (SplatBits == 0) {
6922 // Canonicalize all zero vectors to be v4i32.
6923 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6924 SDValue Z = DAG.getConstant(0, dl, MVT::i32);
6925 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6926 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6931 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6932 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6934 if (SextVal >= -16 && SextVal <= 15)
6935 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6937 // Two instruction sequences.
6939 // If this value is in the range [-32,30] and is even, use:
6940 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6941 // If this value is in the range [17,31] and is odd, use:
6942 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6943 // If this value is in the range [-31,-17] and is odd, use:
6944 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6945 // Note the last two are three-instruction sequences.
6946 if (SextVal >= -32 && SextVal <= 31) {
6947 // To avoid having these optimizations undone by constant folding,
6948 // we convert to a pseudo that will be expanded later into one of
6950 SDValue Elt = DAG.getConstant(SextVal, dl, MVT::i32);
6951 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6952 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6953 SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32);
6954 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6955 if (VT == Op.getValueType())
6958 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6961 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6962 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6964 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6965 // Make -1 and vspltisw -1:
6966 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6968 // Make the VSLW intrinsic, computing 0x8000_0000.
6969 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6972 // xor by OnesV to invert it.
6973 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6974 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6977 // Check to see if this is a wide variety of vsplti*, binop self cases.
6978 static const signed char SplatCsts[] = {
6979 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6980 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6983 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6984 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6985 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6986 int i = SplatCsts[idx];
6988 // Figure out what shift amount will be used by altivec if shifted by i in
6990 unsigned TypeShiftAmt = i & (SplatBitSize-1);
6992 // vsplti + shl self.
6993 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
6994 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6995 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6996 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
6997 Intrinsic::ppc_altivec_vslw
6999 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7000 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7003 // vsplti + srl self.
7004 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
7005 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7006 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7007 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
7008 Intrinsic::ppc_altivec_vsrw
7010 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7011 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7014 // vsplti + sra self.
7015 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
7016 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7017 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7018 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
7019 Intrinsic::ppc_altivec_vsraw
7021 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7022 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7025 // vsplti + rol self.
7026 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
7027 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
7028 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7029 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7030 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
7031 Intrinsic::ppc_altivec_vrlw
7033 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7034 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7037 // t = vsplti c, result = vsldoi t, t, 1
7038 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
7039 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7040 unsigned Amt = Subtarget.isLittleEndian() ? 15 : 1;
7041 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7043 // t = vsplti c, result = vsldoi t, t, 2
7044 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
7045 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7046 unsigned Amt = Subtarget.isLittleEndian() ? 14 : 2;
7047 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7049 // t = vsplti c, result = vsldoi t, t, 3
7050 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
7051 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7052 unsigned Amt = Subtarget.isLittleEndian() ? 13 : 3;
7053 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7060 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
7061 /// the specified operations to build the shuffle.
7062 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
7063 SDValue RHS, SelectionDAG &DAG,
7065 unsigned OpNum = (PFEntry >> 26) & 0x0F;
7066 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
7067 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
7070 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
7082 if (OpNum == OP_COPY) {
7083 if (LHSID == (1*9+2)*9+3) return LHS;
7084 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
7088 SDValue OpLHS, OpRHS;
7089 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
7090 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
7094 default: llvm_unreachable("Unknown i32 permute!");
7096 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
7097 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
7098 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
7099 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
7102 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
7103 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
7104 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
7105 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
7108 for (unsigned i = 0; i != 16; ++i)
7109 ShufIdxs[i] = (i&3)+0;
7112 for (unsigned i = 0; i != 16; ++i)
7113 ShufIdxs[i] = (i&3)+4;
7116 for (unsigned i = 0; i != 16; ++i)
7117 ShufIdxs[i] = (i&3)+8;
7120 for (unsigned i = 0; i != 16; ++i)
7121 ShufIdxs[i] = (i&3)+12;
7124 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
7126 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
7128 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
7130 EVT VT = OpLHS.getValueType();
7131 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
7132 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
7133 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
7134 return DAG.getNode(ISD::BITCAST, dl, VT, T);
7137 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
7138 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
7139 /// return the code it can be lowered into. Worst case, it can always be
7140 /// lowered into a vperm.
7141 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
7142 SelectionDAG &DAG) const {
7144 SDValue V1 = Op.getOperand(0);
7145 SDValue V2 = Op.getOperand(1);
7146 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7147 EVT VT = Op.getValueType();
7148 bool isLittleEndian = Subtarget.isLittleEndian();
7150 if (Subtarget.hasQPX()) {
7151 if (VT.getVectorNumElements() != 4)
7154 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7156 int AlignIdx = PPC::isQVALIGNIShuffleMask(SVOp);
7157 if (AlignIdx != -1) {
7158 return DAG.getNode(PPCISD::QVALIGNI, dl, VT, V1, V2,
7159 DAG.getConstant(AlignIdx, dl, MVT::i32));
7160 } else if (SVOp->isSplat()) {
7161 int SplatIdx = SVOp->getSplatIndex();
7162 if (SplatIdx >= 4) {
7167 // FIXME: If SplatIdx == 0 and the input came from a load, then there is
7170 return DAG.getNode(PPCISD::QVESPLATI, dl, VT, V1,
7171 DAG.getConstant(SplatIdx, dl, MVT::i32));
7174 // Lower this into a qvgpci/qvfperm pair.
7176 // Compute the qvgpci literal
7178 for (unsigned i = 0; i < 4; ++i) {
7179 int m = SVOp->getMaskElt(i);
7180 unsigned mm = m >= 0 ? (unsigned) m : i;
7181 idx |= mm << (3-i)*3;
7184 SDValue V3 = DAG.getNode(PPCISD::QVGPCI, dl, MVT::v4f64,
7185 DAG.getConstant(idx, dl, MVT::i32));
7186 return DAG.getNode(PPCISD::QVFPERM, dl, VT, V1, V2, V3);
7189 // Cases that are handled by instructions that take permute immediates
7190 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
7191 // selected by the instruction selector.
7192 if (V2.getOpcode() == ISD::UNDEF) {
7193 if (PPC::isSplatShuffleMask(SVOp, 1) ||
7194 PPC::isSplatShuffleMask(SVOp, 2) ||
7195 PPC::isSplatShuffleMask(SVOp, 4) ||
7196 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
7197 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
7198 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
7199 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
7200 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
7201 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
7202 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
7203 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
7204 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG) ||
7205 (Subtarget.hasP8Altivec() && (
7206 PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
7207 PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
7208 PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)))) {
7213 // Altivec has a variety of "shuffle immediates" that take two vector inputs
7214 // and produce a fixed permutation. If any of these match, do not lower to
7216 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
7217 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7218 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7219 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
7220 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7221 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7222 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7223 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7224 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7225 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7226 (Subtarget.hasP8Altivec() && (
7227 PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7228 PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
7229 PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))))
7232 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
7233 // perfect shuffle table to emit an optimal matching sequence.
7234 ArrayRef<int> PermMask = SVOp->getMask();
7236 unsigned PFIndexes[4];
7237 bool isFourElementShuffle = true;
7238 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
7239 unsigned EltNo = 8; // Start out undef.
7240 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
7241 if (PermMask[i*4+j] < 0)
7242 continue; // Undef, ignore it.
7244 unsigned ByteSource = PermMask[i*4+j];
7245 if ((ByteSource & 3) != j) {
7246 isFourElementShuffle = false;
7251 EltNo = ByteSource/4;
7252 } else if (EltNo != ByteSource/4) {
7253 isFourElementShuffle = false;
7257 PFIndexes[i] = EltNo;
7260 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
7261 // perfect shuffle vector to determine if it is cost effective to do this as
7262 // discrete instructions, or whether we should use a vperm.
7263 // For now, we skip this for little endian until such time as we have a
7264 // little-endian perfect shuffle table.
7265 if (isFourElementShuffle && !isLittleEndian) {
7266 // Compute the index in the perfect shuffle table.
7267 unsigned PFTableIndex =
7268 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
7270 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
7271 unsigned Cost = (PFEntry >> 30);
7273 // Determining when to avoid vperm is tricky. Many things affect the cost
7274 // of vperm, particularly how many times the perm mask needs to be computed.
7275 // For example, if the perm mask can be hoisted out of a loop or is already
7276 // used (perhaps because there are multiple permutes with the same shuffle
7277 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
7278 // the loop requires an extra register.
7280 // As a compromise, we only emit discrete instructions if the shuffle can be
7281 // generated in 3 or fewer operations. When we have loop information
7282 // available, if this block is within a loop, we should avoid using vperm
7283 // for 3-operation perms and use a constant pool load instead.
7285 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
7288 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
7289 // vector that will get spilled to the constant pool.
7290 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7292 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
7293 // that it is in input element units, not in bytes. Convert now.
7295 // For little endian, the order of the input vectors is reversed, and
7296 // the permutation mask is complemented with respect to 31. This is
7297 // necessary to produce proper semantics with the big-endian-biased vperm
7299 EVT EltVT = V1.getValueType().getVectorElementType();
7300 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
7302 SmallVector<SDValue, 16> ResultMask;
7303 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
7304 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
7306 for (unsigned j = 0; j != BytesPerElement; ++j)
7308 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement + j),
7311 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement + j, dl,
7315 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
7318 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7321 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7325 /// getVectorCompareInfo - Given an intrinsic, return false if it is not a
7326 /// vector comparison. If it is, return true and fill in Opc/isDot with
7327 /// information about the intrinsic.
7328 static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc,
7329 bool &isDot, const PPCSubtarget &Subtarget) {
7330 unsigned IntrinsicID =
7331 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
7334 switch (IntrinsicID) {
7335 default: return false;
7336 // Comparison predicates.
7337 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
7338 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
7339 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
7340 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
7341 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
7342 case Intrinsic::ppc_altivec_vcmpequd_p:
7343 if (Subtarget.hasP8Altivec()) {
7350 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
7351 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
7352 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
7353 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
7354 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
7355 case Intrinsic::ppc_altivec_vcmpgtsd_p:
7356 if (Subtarget.hasP8Altivec()) {
7363 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
7364 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
7365 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
7366 case Intrinsic::ppc_altivec_vcmpgtud_p:
7367 if (Subtarget.hasP8Altivec()) {
7374 // VSX predicate comparisons use the same infrastructure
7375 case Intrinsic::ppc_vsx_xvcmpeqdp_p:
7376 case Intrinsic::ppc_vsx_xvcmpgedp_p:
7377 case Intrinsic::ppc_vsx_xvcmpgtdp_p:
7378 case Intrinsic::ppc_vsx_xvcmpeqsp_p:
7379 case Intrinsic::ppc_vsx_xvcmpgesp_p:
7380 case Intrinsic::ppc_vsx_xvcmpgtsp_p:
7381 if (Subtarget.hasVSX()) {
7382 switch (IntrinsicID) {
7383 case Intrinsic::ppc_vsx_xvcmpeqdp_p: CompareOpc = 99; break;
7384 case Intrinsic::ppc_vsx_xvcmpgedp_p: CompareOpc = 115; break;
7385 case Intrinsic::ppc_vsx_xvcmpgtdp_p: CompareOpc = 107; break;
7386 case Intrinsic::ppc_vsx_xvcmpeqsp_p: CompareOpc = 67; break;
7387 case Intrinsic::ppc_vsx_xvcmpgesp_p: CompareOpc = 83; break;
7388 case Intrinsic::ppc_vsx_xvcmpgtsp_p: CompareOpc = 75; break;
7397 // Normal Comparisons.
7398 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
7399 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
7400 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
7401 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
7402 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
7403 case Intrinsic::ppc_altivec_vcmpequd:
7404 if (Subtarget.hasP8Altivec()) {
7411 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
7412 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
7413 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
7414 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
7415 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
7416 case Intrinsic::ppc_altivec_vcmpgtsd:
7417 if (Subtarget.hasP8Altivec()) {
7424 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
7425 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
7426 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
7427 case Intrinsic::ppc_altivec_vcmpgtud:
7428 if (Subtarget.hasP8Altivec()) {
7439 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
7440 /// lower, do it, otherwise return null.
7441 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
7442 SelectionDAG &DAG) const {
7443 // If this is a lowered altivec predicate compare, CompareOpc is set to the
7444 // opcode number of the comparison.
7448 if (!getVectorCompareInfo(Op, CompareOpc, isDot, Subtarget))
7449 return SDValue(); // Don't custom lower most intrinsics.
7451 // If this is a non-dot comparison, make the VCMP node and we are done.
7453 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
7454 Op.getOperand(1), Op.getOperand(2),
7455 DAG.getConstant(CompareOpc, dl, MVT::i32));
7456 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
7459 // Create the PPCISD altivec 'dot' comparison node.
7461 Op.getOperand(2), // LHS
7462 Op.getOperand(3), // RHS
7463 DAG.getConstant(CompareOpc, dl, MVT::i32)
7465 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
7466 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
7468 // Now that we have the comparison, emit a copy from the CR to a GPR.
7469 // This is flagged to the above dot comparison.
7470 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
7471 DAG.getRegister(PPC::CR6, MVT::i32),
7472 CompNode.getValue(1));
7474 // Unpack the result based on how the target uses it.
7475 unsigned BitNo; // Bit # of CR6.
7476 bool InvertBit; // Invert result?
7477 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
7478 default: // Can't happen, don't crash on invalid number though.
7479 case 0: // Return the value of the EQ bit of CR6.
7480 BitNo = 0; InvertBit = false;
7482 case 1: // Return the inverted value of the EQ bit of CR6.
7483 BitNo = 0; InvertBit = true;
7485 case 2: // Return the value of the LT bit of CR6.
7486 BitNo = 2; InvertBit = false;
7488 case 3: // Return the inverted value of the LT bit of CR6.
7489 BitNo = 2; InvertBit = true;
7493 // Shift the bit into the low position.
7494 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
7495 DAG.getConstant(8 - (3 - BitNo), dl, MVT::i32));
7497 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
7498 DAG.getConstant(1, dl, MVT::i32));
7500 // If we are supposed to, toggle the bit.
7502 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
7503 DAG.getConstant(1, dl, MVT::i32));
7507 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
7508 SelectionDAG &DAG) const {
7510 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
7511 // instructions), but for smaller types, we need to first extend up to v2i32
7512 // before doing going farther.
7513 if (Op.getValueType() == MVT::v2i64) {
7514 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
7515 if (ExtVT != MVT::v2i32) {
7516 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
7517 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
7518 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
7519 ExtVT.getVectorElementType(), 4)));
7520 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
7521 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
7522 DAG.getValueType(MVT::v2i32));
7531 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
7532 SelectionDAG &DAG) const {
7534 // Create a stack slot that is 16-byte aligned.
7535 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7536 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7537 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7538 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7540 // Store the input value into Value#0 of the stack slot.
7541 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
7542 Op.getOperand(0), FIdx, MachinePointerInfo(),
7545 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
7546 false, false, false, 0);
7549 SDValue PPCTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7550 SelectionDAG &DAG) const {
7552 SDNode *N = Op.getNode();
7554 assert(N->getOperand(0).getValueType() == MVT::v4i1 &&
7555 "Unknown extract_vector_elt type");
7557 SDValue Value = N->getOperand(0);
7559 // The first part of this is like the store lowering except that we don't
7560 // need to track the chain.
7562 // The values are now known to be -1 (false) or 1 (true). To convert this
7563 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7564 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7565 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7567 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7568 // understand how to form the extending load.
7569 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7570 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7571 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7573 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7575 // Now convert to an integer and store.
7576 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7577 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7580 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7581 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7582 MachinePointerInfo PtrInfo =
7583 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
7584 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7585 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7587 SDValue StoreChain = DAG.getEntryNode();
7588 SmallVector<SDValue, 2> Ops;
7589 Ops.push_back(StoreChain);
7590 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7591 Ops.push_back(Value);
7592 Ops.push_back(FIdx);
7594 SmallVector<EVT, 2> ValueVTs;
7595 ValueVTs.push_back(MVT::Other); // chain
7596 SDVTList VTs = DAG.getVTList(ValueVTs);
7598 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7599 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7601 // Extract the value requested.
7602 unsigned Offset = 4*cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7603 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7604 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7606 SDValue IntVal = DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7607 PtrInfo.getWithOffset(Offset),
7608 false, false, false, 0);
7610 if (!Subtarget.useCRBits())
7613 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, IntVal);
7616 /// Lowering for QPX v4i1 loads
7617 SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
7618 SelectionDAG &DAG) const {
7620 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
7621 SDValue LoadChain = LN->getChain();
7622 SDValue BasePtr = LN->getBasePtr();
7624 if (Op.getValueType() == MVT::v4f64 ||
7625 Op.getValueType() == MVT::v4f32) {
7626 EVT MemVT = LN->getMemoryVT();
7627 unsigned Alignment = LN->getAlignment();
7629 // If this load is properly aligned, then it is legal.
7630 if (Alignment >= MemVT.getStoreSize())
7633 EVT ScalarVT = Op.getValueType().getScalarType(),
7634 ScalarMemVT = MemVT.getScalarType();
7635 unsigned Stride = ScalarMemVT.getStoreSize();
7637 SmallVector<SDValue, 8> Vals, LoadChains;
7638 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7640 if (ScalarVT != ScalarMemVT)
7642 DAG.getExtLoad(LN->getExtensionType(), dl, ScalarVT, LoadChain,
7644 LN->getPointerInfo().getWithOffset(Idx*Stride),
7645 ScalarMemVT, LN->isVolatile(), LN->isNonTemporal(),
7646 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7650 DAG.getLoad(ScalarVT, dl, LoadChain, BasePtr,
7651 LN->getPointerInfo().getWithOffset(Idx*Stride),
7652 LN->isVolatile(), LN->isNonTemporal(),
7653 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7656 if (Idx == 0 && LN->isIndexed()) {
7657 assert(LN->getAddressingMode() == ISD::PRE_INC &&
7658 "Unknown addressing mode on vector load");
7659 Load = DAG.getIndexedLoad(Load, dl, BasePtr, LN->getOffset(),
7660 LN->getAddressingMode());
7663 Vals.push_back(Load);
7664 LoadChains.push_back(Load.getValue(1));
7666 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7667 DAG.getConstant(Stride, dl,
7668 BasePtr.getValueType()));
7671 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7672 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
7673 Op.getValueType(), Vals);
7675 if (LN->isIndexed()) {
7676 SDValue RetOps[] = { Value, Vals[0].getValue(1), TF };
7677 return DAG.getMergeValues(RetOps, dl);
7680 SDValue RetOps[] = { Value, TF };
7681 return DAG.getMergeValues(RetOps, dl);
7684 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower");
7685 assert(LN->isUnindexed() && "Indexed v4i1 loads are not supported");
7687 // To lower v4i1 from a byte array, we load the byte elements of the
7688 // vector and then reuse the BUILD_VECTOR logic.
7690 SmallVector<SDValue, 4> VectElmts, VectElmtChains;
7691 for (unsigned i = 0; i < 4; ++i) {
7692 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7693 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7695 VectElmts.push_back(DAG.getExtLoad(ISD::EXTLOAD,
7696 dl, MVT::i32, LoadChain, Idx,
7697 LN->getPointerInfo().getWithOffset(i),
7698 MVT::i8 /* memory type */,
7699 LN->isVolatile(), LN->isNonTemporal(),
7701 1 /* alignment */, LN->getAAInfo()));
7702 VectElmtChains.push_back(VectElmts[i].getValue(1));
7705 LoadChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, VectElmtChains);
7706 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i1, VectElmts);
7708 SDValue RVals[] = { Value, LoadChain };
7709 return DAG.getMergeValues(RVals, dl);
7712 /// Lowering for QPX v4i1 stores
7713 SDValue PPCTargetLowering::LowerVectorStore(SDValue Op,
7714 SelectionDAG &DAG) const {
7716 StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
7717 SDValue StoreChain = SN->getChain();
7718 SDValue BasePtr = SN->getBasePtr();
7719 SDValue Value = SN->getValue();
7721 if (Value.getValueType() == MVT::v4f64 ||
7722 Value.getValueType() == MVT::v4f32) {
7723 EVT MemVT = SN->getMemoryVT();
7724 unsigned Alignment = SN->getAlignment();
7726 // If this store is properly aligned, then it is legal.
7727 if (Alignment >= MemVT.getStoreSize())
7730 EVT ScalarVT = Value.getValueType().getScalarType(),
7731 ScalarMemVT = MemVT.getScalarType();
7732 unsigned Stride = ScalarMemVT.getStoreSize();
7734 SmallVector<SDValue, 8> Stores;
7735 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7736 SDValue Ex = DAG.getNode(
7737 ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, Value,
7738 DAG.getConstant(Idx, dl, getVectorIdxTy(DAG.getDataLayout())));
7740 if (ScalarVT != ScalarMemVT)
7742 DAG.getTruncStore(StoreChain, dl, Ex, BasePtr,
7743 SN->getPointerInfo().getWithOffset(Idx*Stride),
7744 ScalarMemVT, SN->isVolatile(), SN->isNonTemporal(),
7745 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7748 DAG.getStore(StoreChain, dl, Ex, BasePtr,
7749 SN->getPointerInfo().getWithOffset(Idx*Stride),
7750 SN->isVolatile(), SN->isNonTemporal(),
7751 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7753 if (Idx == 0 && SN->isIndexed()) {
7754 assert(SN->getAddressingMode() == ISD::PRE_INC &&
7755 "Unknown addressing mode on vector store");
7756 Store = DAG.getIndexedStore(Store, dl, BasePtr, SN->getOffset(),
7757 SN->getAddressingMode());
7760 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7761 DAG.getConstant(Stride, dl,
7762 BasePtr.getValueType()));
7763 Stores.push_back(Store);
7766 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7768 if (SN->isIndexed()) {
7769 SDValue RetOps[] = { TF, Stores[0].getValue(1) };
7770 return DAG.getMergeValues(RetOps, dl);
7776 assert(SN->isUnindexed() && "Indexed v4i1 stores are not supported");
7777 assert(Value.getValueType() == MVT::v4i1 && "Unknown store to lower");
7779 // The values are now known to be -1 (false) or 1 (true). To convert this
7780 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7781 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7782 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7784 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7785 // understand how to form the extending load.
7786 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7787 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7788 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7790 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7792 // Now convert to an integer and store.
7793 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7794 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7797 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7798 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7799 MachinePointerInfo PtrInfo =
7800 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
7801 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7802 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7804 SmallVector<SDValue, 2> Ops;
7805 Ops.push_back(StoreChain);
7806 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7807 Ops.push_back(Value);
7808 Ops.push_back(FIdx);
7810 SmallVector<EVT, 2> ValueVTs;
7811 ValueVTs.push_back(MVT::Other); // chain
7812 SDVTList VTs = DAG.getVTList(ValueVTs);
7814 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7815 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7817 // Move data into the byte array.
7818 SmallVector<SDValue, 4> Loads, LoadChains;
7819 for (unsigned i = 0; i < 4; ++i) {
7820 unsigned Offset = 4*i;
7821 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7822 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7824 Loads.push_back(DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7825 PtrInfo.getWithOffset(Offset),
7826 false, false, false, 0));
7827 LoadChains.push_back(Loads[i].getValue(1));
7830 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7832 SmallVector<SDValue, 4> Stores;
7833 for (unsigned i = 0; i < 4; ++i) {
7834 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7835 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7837 Stores.push_back(DAG.getTruncStore(
7838 StoreChain, dl, Loads[i], Idx, SN->getPointerInfo().getWithOffset(i),
7839 MVT::i8 /* memory type */, SN->isNonTemporal(), SN->isVolatile(),
7840 1 /* alignment */, SN->getAAInfo()));
7843 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7848 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
7850 if (Op.getValueType() == MVT::v4i32) {
7851 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7853 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
7854 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
7856 SDValue RHSSwap = // = vrlw RHS, 16
7857 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
7859 // Shrinkify inputs to v8i16.
7860 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
7861 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
7862 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
7864 // Low parts multiplied together, generating 32-bit results (we ignore the
7866 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
7867 LHS, RHS, DAG, dl, MVT::v4i32);
7869 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
7870 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
7871 // Shift the high parts up 16 bits.
7872 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
7874 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
7875 } else if (Op.getValueType() == MVT::v8i16) {
7876 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7878 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
7880 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
7881 LHS, RHS, Zero, DAG, dl);
7882 } else if (Op.getValueType() == MVT::v16i8) {
7883 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7884 bool isLittleEndian = Subtarget.isLittleEndian();
7886 // Multiply the even 8-bit parts, producing 16-bit sums.
7887 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
7888 LHS, RHS, DAG, dl, MVT::v8i16);
7889 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
7891 // Multiply the odd 8-bit parts, producing 16-bit sums.
7892 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
7893 LHS, RHS, DAG, dl, MVT::v8i16);
7894 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
7896 // Merge the results together. Because vmuleub and vmuloub are
7897 // instructions with a big-endian bias, we must reverse the
7898 // element numbering and reverse the meaning of "odd" and "even"
7899 // when generating little endian code.
7901 for (unsigned i = 0; i != 8; ++i) {
7902 if (isLittleEndian) {
7904 Ops[i*2+1] = 2*i+16;
7907 Ops[i*2+1] = 2*i+1+16;
7911 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
7913 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
7915 llvm_unreachable("Unknown mul to lower!");
7919 /// LowerOperation - Provide custom lowering hooks for some operations.
7921 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7922 switch (Op.getOpcode()) {
7923 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
7924 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7925 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7926 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7927 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7928 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7929 case ISD::SETCC: return LowerSETCC(Op, DAG);
7930 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
7931 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
7933 return LowerVASTART(Op, DAG, Subtarget);
7936 return LowerVAARG(Op, DAG, Subtarget);
7939 return LowerVACOPY(Op, DAG, Subtarget);
7941 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
7942 case ISD::DYNAMIC_STACKALLOC:
7943 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
7945 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
7946 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
7948 case ISD::LOAD: return LowerLOAD(Op, DAG);
7949 case ISD::STORE: return LowerSTORE(Op, DAG);
7950 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
7951 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
7952 case ISD::FP_TO_UINT:
7953 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
7955 case ISD::UINT_TO_FP:
7956 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
7957 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7959 // Lower 64-bit shifts.
7960 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
7961 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
7962 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
7964 // Vector-related lowering.
7965 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7966 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7967 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7968 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7969 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
7970 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7971 case ISD::MUL: return LowerMUL(Op, DAG);
7973 // For counter-based loop handling.
7974 case ISD::INTRINSIC_W_CHAIN: return SDValue();
7976 // Frame & Return address.
7977 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7978 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7982 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
7983 SmallVectorImpl<SDValue>&Results,
7984 SelectionDAG &DAG) const {
7986 switch (N->getOpcode()) {
7988 llvm_unreachable("Do not know how to custom type legalize this operation!");
7989 case ISD::READCYCLECOUNTER: {
7990 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7991 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
7993 Results.push_back(RTB);
7994 Results.push_back(RTB.getValue(1));
7995 Results.push_back(RTB.getValue(2));
7998 case ISD::INTRINSIC_W_CHAIN: {
7999 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
8000 Intrinsic::ppc_is_decremented_ctr_nonzero)
8003 assert(N->getValueType(0) == MVT::i1 &&
8004 "Unexpected result type for CTR decrement intrinsic");
8005 EVT SVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
8006 N->getValueType(0));
8007 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
8008 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
8011 Results.push_back(NewInt);
8012 Results.push_back(NewInt.getValue(1));
8016 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
8019 EVT VT = N->getValueType(0);
8021 if (VT == MVT::i64) {
8022 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
8024 Results.push_back(NewNode);
8025 Results.push_back(NewNode.getValue(1));
8029 case ISD::FP_ROUND_INREG: {
8030 assert(N->getValueType(0) == MVT::ppcf128);
8031 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
8032 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
8033 MVT::f64, N->getOperand(0),
8034 DAG.getIntPtrConstant(0, dl));
8035 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
8036 MVT::f64, N->getOperand(0),
8037 DAG.getIntPtrConstant(1, dl));
8039 // Add the two halves of the long double in round-to-zero mode.
8040 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
8042 // We know the low half is about to be thrown away, so just use something
8044 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
8048 case ISD::FP_TO_SINT:
8049 case ISD::FP_TO_UINT:
8050 // LowerFP_TO_INT() can only handle f32 and f64.
8051 if (N->getOperand(0).getValueType() == MVT::ppcf128)
8053 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
8058 //===----------------------------------------------------------------------===//
8059 // Other Lowering Code
8060 //===----------------------------------------------------------------------===//
8062 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
8063 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8064 Function *Func = Intrinsic::getDeclaration(M, Id);
8065 return Builder.CreateCall(Func, {});
8068 // The mappings for emitLeading/TrailingFence is taken from
8069 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
8070 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
8071 AtomicOrdering Ord, bool IsStore,
8072 bool IsLoad) const {
8073 if (Ord == SequentiallyConsistent)
8074 return callIntrinsic(Builder, Intrinsic::ppc_sync);
8075 if (isAtLeastRelease(Ord))
8076 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8080 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
8081 AtomicOrdering Ord, bool IsStore,
8082 bool IsLoad) const {
8083 if (IsLoad && isAtLeastAcquire(Ord))
8084 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8085 // FIXME: this is too conservative, a dependent branch + isync is enough.
8086 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
8087 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
8088 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
8093 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
8094 unsigned AtomicSize,
8095 unsigned BinOpcode) const {
8096 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8097 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8099 auto LoadMnemonic = PPC::LDARX;
8100 auto StoreMnemonic = PPC::STDCX;
8101 switch (AtomicSize) {
8103 llvm_unreachable("Unexpected size of atomic entity");
8105 LoadMnemonic = PPC::LBARX;
8106 StoreMnemonic = PPC::STBCX;
8107 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8110 LoadMnemonic = PPC::LHARX;
8111 StoreMnemonic = PPC::STHCX;
8112 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8115 LoadMnemonic = PPC::LWARX;
8116 StoreMnemonic = PPC::STWCX;
8119 LoadMnemonic = PPC::LDARX;
8120 StoreMnemonic = PPC::STDCX;
8124 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8125 MachineFunction *F = BB->getParent();
8126 MachineFunction::iterator It = BB;
8129 unsigned dest = MI->getOperand(0).getReg();
8130 unsigned ptrA = MI->getOperand(1).getReg();
8131 unsigned ptrB = MI->getOperand(2).getReg();
8132 unsigned incr = MI->getOperand(3).getReg();
8133 DebugLoc dl = MI->getDebugLoc();
8135 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8136 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8137 F->insert(It, loopMBB);
8138 F->insert(It, exitMBB);
8139 exitMBB->splice(exitMBB->begin(), BB,
8140 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8141 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8143 MachineRegisterInfo &RegInfo = F->getRegInfo();
8144 unsigned TmpReg = (!BinOpcode) ? incr :
8145 RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass
8146 : &PPC::GPRCRegClass);
8150 // fallthrough --> loopMBB
8151 BB->addSuccessor(loopMBB);
8154 // l[wd]arx dest, ptr
8155 // add r0, dest, incr
8156 // st[wd]cx. r0, ptr
8158 // fallthrough --> exitMBB
8160 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8161 .addReg(ptrA).addReg(ptrB);
8163 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
8164 BuildMI(BB, dl, TII->get(StoreMnemonic))
8165 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
8166 BuildMI(BB, dl, TII->get(PPC::BCC))
8167 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8168 BB->addSuccessor(loopMBB);
8169 BB->addSuccessor(exitMBB);
8178 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
8179 MachineBasicBlock *BB,
8180 bool is8bit, // operation
8181 unsigned BinOpcode) const {
8182 // If we support part-word atomic mnemonics, just use them
8183 if (Subtarget.hasPartwordAtomics())
8184 return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode);
8186 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8187 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8188 // In 64 bit mode we have to use 64 bits for addresses, even though the
8189 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
8190 // registers without caring whether they're 32 or 64, but here we're
8191 // doing actual arithmetic on the addresses.
8192 bool is64bit = Subtarget.isPPC64();
8193 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8195 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8196 MachineFunction *F = BB->getParent();
8197 MachineFunction::iterator It = BB;
8200 unsigned dest = MI->getOperand(0).getReg();
8201 unsigned ptrA = MI->getOperand(1).getReg();
8202 unsigned ptrB = MI->getOperand(2).getReg();
8203 unsigned incr = MI->getOperand(3).getReg();
8204 DebugLoc dl = MI->getDebugLoc();
8206 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8207 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8208 F->insert(It, loopMBB);
8209 F->insert(It, exitMBB);
8210 exitMBB->splice(exitMBB->begin(), BB,
8211 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8212 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8214 MachineRegisterInfo &RegInfo = F->getRegInfo();
8215 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8216 : &PPC::GPRCRegClass;
8217 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8218 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8219 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8220 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
8221 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8222 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8223 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8224 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8225 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
8226 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8227 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8229 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
8233 // fallthrough --> loopMBB
8234 BB->addSuccessor(loopMBB);
8236 // The 4-byte load must be aligned, while a char or short may be
8237 // anywhere in the word. Hence all this nasty bookkeeping code.
8238 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8239 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8240 // xori shift, shift1, 24 [16]
8241 // rlwinm ptr, ptr1, 0, 0, 29
8242 // slw incr2, incr, shift
8243 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8244 // slw mask, mask2, shift
8246 // lwarx tmpDest, ptr
8247 // add tmp, tmpDest, incr2
8248 // andc tmp2, tmpDest, mask
8249 // and tmp3, tmp, mask
8250 // or tmp4, tmp3, tmp2
8253 // fallthrough --> exitMBB
8254 // srw dest, tmpDest, shift
8255 if (ptrA != ZeroReg) {
8256 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8257 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8258 .addReg(ptrA).addReg(ptrB);
8262 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8263 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8264 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8265 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8267 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8268 .addReg(Ptr1Reg).addImm(0).addImm(61);
8270 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8271 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8272 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
8273 .addReg(incr).addReg(ShiftReg);
8275 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
8277 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
8278 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
8280 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
8281 .addReg(Mask2Reg).addReg(ShiftReg);
8284 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
8285 .addReg(ZeroReg).addReg(PtrReg);
8287 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
8288 .addReg(Incr2Reg).addReg(TmpDestReg);
8289 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
8290 .addReg(TmpDestReg).addReg(MaskReg);
8291 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
8292 .addReg(TmpReg).addReg(MaskReg);
8293 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
8294 .addReg(Tmp3Reg).addReg(Tmp2Reg);
8295 BuildMI(BB, dl, TII->get(PPC::STWCX))
8296 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
8297 BuildMI(BB, dl, TII->get(PPC::BCC))
8298 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8299 BB->addSuccessor(loopMBB);
8300 BB->addSuccessor(exitMBB);
8305 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
8310 llvm::MachineBasicBlock*
8311 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
8312 MachineBasicBlock *MBB) const {
8313 DebugLoc DL = MI->getDebugLoc();
8314 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8316 MachineFunction *MF = MBB->getParent();
8317 MachineRegisterInfo &MRI = MF->getRegInfo();
8319 const BasicBlock *BB = MBB->getBasicBlock();
8320 MachineFunction::iterator I = MBB;
8324 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8325 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8327 unsigned DstReg = MI->getOperand(0).getReg();
8328 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
8329 assert(RC->hasType(MVT::i32) && "Invalid destination!");
8330 unsigned mainDstReg = MRI.createVirtualRegister(RC);
8331 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
8333 MVT PVT = getPointerTy(MF->getDataLayout());
8334 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8335 "Invalid Pointer Size!");
8336 // For v = setjmp(buf), we generate
8339 // SjLjSetup mainMBB
8345 // buf[LabelOffset] = LR
8349 // v = phi(main, restore)
8352 MachineBasicBlock *thisMBB = MBB;
8353 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
8354 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
8355 MF->insert(I, mainMBB);
8356 MF->insert(I, sinkMBB);
8358 MachineInstrBuilder MIB;
8360 // Transfer the remainder of BB and its successor edges to sinkMBB.
8361 sinkMBB->splice(sinkMBB->begin(), MBB,
8362 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
8363 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
8365 // Note that the structure of the jmp_buf used here is not compatible
8366 // with that used by libc, and is not designed to be. Specifically, it
8367 // stores only those 'reserved' registers that LLVM does not otherwise
8368 // understand how to spill. Also, by convention, by the time this
8369 // intrinsic is called, Clang has already stored the frame address in the
8370 // first slot of the buffer and stack address in the third. Following the
8371 // X86 target code, we'll store the jump address in the second slot. We also
8372 // need to save the TOC pointer (R2) to handle jumps between shared
8373 // libraries, and that will be stored in the fourth slot. The thread
8374 // identifier (R13) is not affected.
8377 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8378 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8379 const int64_t BPOffset = 4 * PVT.getStoreSize();
8381 // Prepare IP either in reg.
8382 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
8383 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
8384 unsigned BufReg = MI->getOperand(1).getReg();
8386 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
8387 setUsesTOCBasePtr(*MBB->getParent());
8388 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
8392 MIB.setMemRefs(MMOBegin, MMOEnd);
8395 // Naked functions never have a base pointer, and so we use r1. For all
8396 // other functions, this decision must be delayed until during PEI.
8398 if (MF->getFunction()->hasFnAttribute(Attribute::Naked))
8399 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
8401 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
8403 MIB = BuildMI(*thisMBB, MI, DL,
8404 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
8408 MIB.setMemRefs(MMOBegin, MMOEnd);
8411 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
8412 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
8413 MIB.addRegMask(TRI->getNoPreservedMask());
8415 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
8417 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
8419 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
8421 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
8422 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
8427 BuildMI(mainMBB, DL,
8428 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
8431 if (Subtarget.isPPC64()) {
8432 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
8434 .addImm(LabelOffset)
8437 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
8439 .addImm(LabelOffset)
8443 MIB.setMemRefs(MMOBegin, MMOEnd);
8445 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
8446 mainMBB->addSuccessor(sinkMBB);
8449 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
8450 TII->get(PPC::PHI), DstReg)
8451 .addReg(mainDstReg).addMBB(mainMBB)
8452 .addReg(restoreDstReg).addMBB(thisMBB);
8454 MI->eraseFromParent();
8459 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
8460 MachineBasicBlock *MBB) const {
8461 DebugLoc DL = MI->getDebugLoc();
8462 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8464 MachineFunction *MF = MBB->getParent();
8465 MachineRegisterInfo &MRI = MF->getRegInfo();
8468 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8469 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8471 MVT PVT = getPointerTy(MF->getDataLayout());
8472 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8473 "Invalid Pointer Size!");
8475 const TargetRegisterClass *RC =
8476 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
8477 unsigned Tmp = MRI.createVirtualRegister(RC);
8478 // Since FP is only updated here but NOT referenced, it's treated as GPR.
8479 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
8480 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
8484 : (Subtarget.isSVR4ABI() &&
8485 MF->getTarget().getRelocationModel() == Reloc::PIC_
8489 MachineInstrBuilder MIB;
8491 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8492 const int64_t SPOffset = 2 * PVT.getStoreSize();
8493 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8494 const int64_t BPOffset = 4 * PVT.getStoreSize();
8496 unsigned BufReg = MI->getOperand(0).getReg();
8498 // Reload FP (the jumped-to function may not have had a
8499 // frame pointer, and if so, then its r31 will be restored
8501 if (PVT == MVT::i64) {
8502 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
8506 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
8510 MIB.setMemRefs(MMOBegin, MMOEnd);
8513 if (PVT == MVT::i64) {
8514 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
8515 .addImm(LabelOffset)
8518 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
8519 .addImm(LabelOffset)
8522 MIB.setMemRefs(MMOBegin, MMOEnd);
8525 if (PVT == MVT::i64) {
8526 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
8530 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
8534 MIB.setMemRefs(MMOBegin, MMOEnd);
8537 if (PVT == MVT::i64) {
8538 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
8542 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
8546 MIB.setMemRefs(MMOBegin, MMOEnd);
8549 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
8550 setUsesTOCBasePtr(*MBB->getParent());
8551 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
8555 MIB.setMemRefs(MMOBegin, MMOEnd);
8559 BuildMI(*MBB, MI, DL,
8560 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
8561 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
8563 MI->eraseFromParent();
8568 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8569 MachineBasicBlock *BB) const {
8570 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
8571 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8572 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
8573 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8574 // Call lowering should have added an r2 operand to indicate a dependence
8575 // on the TOC base pointer value. It can't however, because there is no
8576 // way to mark the dependence as implicit there, and so the stackmap code
8577 // will confuse it with a regular operand. Instead, add the dependence
8579 setUsesTOCBasePtr(*BB->getParent());
8580 MI->addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
8583 return emitPatchPoint(MI, BB);
8586 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
8587 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
8588 return emitEHSjLjSetJmp(MI, BB);
8589 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
8590 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
8591 return emitEHSjLjLongJmp(MI, BB);
8594 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8596 // To "insert" these instructions we actually have to insert their
8597 // control-flow patterns.
8598 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8599 MachineFunction::iterator It = BB;
8602 MachineFunction *F = BB->getParent();
8604 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8605 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8606 MI->getOpcode() == PPC::SELECT_I4 ||
8607 MI->getOpcode() == PPC::SELECT_I8)) {
8608 SmallVector<MachineOperand, 2> Cond;
8609 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8610 MI->getOpcode() == PPC::SELECT_CC_I8)
8611 Cond.push_back(MI->getOperand(4));
8613 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
8614 Cond.push_back(MI->getOperand(1));
8616 DebugLoc dl = MI->getDebugLoc();
8617 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
8618 Cond, MI->getOperand(2).getReg(),
8619 MI->getOperand(3).getReg());
8620 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8621 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8622 MI->getOpcode() == PPC::SELECT_CC_F4 ||
8623 MI->getOpcode() == PPC::SELECT_CC_F8 ||
8624 MI->getOpcode() == PPC::SELECT_CC_QFRC ||
8625 MI->getOpcode() == PPC::SELECT_CC_QSRC ||
8626 MI->getOpcode() == PPC::SELECT_CC_QBRC ||
8627 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
8628 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
8629 MI->getOpcode() == PPC::SELECT_CC_VSSRC ||
8630 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
8631 MI->getOpcode() == PPC::SELECT_I4 ||
8632 MI->getOpcode() == PPC::SELECT_I8 ||
8633 MI->getOpcode() == PPC::SELECT_F4 ||
8634 MI->getOpcode() == PPC::SELECT_F8 ||
8635 MI->getOpcode() == PPC::SELECT_QFRC ||
8636 MI->getOpcode() == PPC::SELECT_QSRC ||
8637 MI->getOpcode() == PPC::SELECT_QBRC ||
8638 MI->getOpcode() == PPC::SELECT_VRRC ||
8639 MI->getOpcode() == PPC::SELECT_VSFRC ||
8640 MI->getOpcode() == PPC::SELECT_VSSRC ||
8641 MI->getOpcode() == PPC::SELECT_VSRC) {
8642 // The incoming instruction knows the destination vreg to set, the
8643 // condition code register to branch on, the true/false values to
8644 // select between, and a branch opcode to use.
8649 // cmpTY ccX, r1, r2
8651 // fallthrough --> copy0MBB
8652 MachineBasicBlock *thisMBB = BB;
8653 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8654 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8655 DebugLoc dl = MI->getDebugLoc();
8656 F->insert(It, copy0MBB);
8657 F->insert(It, sinkMBB);
8659 // Transfer the remainder of BB and its successor edges to sinkMBB.
8660 sinkMBB->splice(sinkMBB->begin(), BB,
8661 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8662 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8664 // Next, add the true and fallthrough blocks as its successors.
8665 BB->addSuccessor(copy0MBB);
8666 BB->addSuccessor(sinkMBB);
8668 if (MI->getOpcode() == PPC::SELECT_I4 ||
8669 MI->getOpcode() == PPC::SELECT_I8 ||
8670 MI->getOpcode() == PPC::SELECT_F4 ||
8671 MI->getOpcode() == PPC::SELECT_F8 ||
8672 MI->getOpcode() == PPC::SELECT_QFRC ||
8673 MI->getOpcode() == PPC::SELECT_QSRC ||
8674 MI->getOpcode() == PPC::SELECT_QBRC ||
8675 MI->getOpcode() == PPC::SELECT_VRRC ||
8676 MI->getOpcode() == PPC::SELECT_VSFRC ||
8677 MI->getOpcode() == PPC::SELECT_VSSRC ||
8678 MI->getOpcode() == PPC::SELECT_VSRC) {
8679 BuildMI(BB, dl, TII->get(PPC::BC))
8680 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8682 unsigned SelectPred = MI->getOperand(4).getImm();
8683 BuildMI(BB, dl, TII->get(PPC::BCC))
8684 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8688 // %FalseValue = ...
8689 // # fallthrough to sinkMBB
8692 // Update machine-CFG edges
8693 BB->addSuccessor(sinkMBB);
8696 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8699 BuildMI(*BB, BB->begin(), dl,
8700 TII->get(PPC::PHI), MI->getOperand(0).getReg())
8701 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
8702 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8703 } else if (MI->getOpcode() == PPC::ReadTB) {
8704 // To read the 64-bit time-base register on a 32-bit target, we read the
8705 // two halves. Should the counter have wrapped while it was being read, we
8706 // need to try again.
8709 // mfspr Rx,TBU # load from TBU
8710 // mfspr Ry,TB # load from TB
8711 // mfspr Rz,TBU # load from TBU
8712 // cmpw crX,Rx,Rz # check if 'old'='new'
8713 // bne readLoop # branch if they're not equal
8716 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
8717 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8718 DebugLoc dl = MI->getDebugLoc();
8719 F->insert(It, readMBB);
8720 F->insert(It, sinkMBB);
8722 // Transfer the remainder of BB and its successor edges to sinkMBB.
8723 sinkMBB->splice(sinkMBB->begin(), BB,
8724 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8725 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8727 BB->addSuccessor(readMBB);
8730 MachineRegisterInfo &RegInfo = F->getRegInfo();
8731 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
8732 unsigned LoReg = MI->getOperand(0).getReg();
8733 unsigned HiReg = MI->getOperand(1).getReg();
8735 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
8736 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
8737 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
8739 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
8741 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
8742 .addReg(HiReg).addReg(ReadAgainReg);
8743 BuildMI(BB, dl, TII->get(PPC::BCC))
8744 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
8746 BB->addSuccessor(readMBB);
8747 BB->addSuccessor(sinkMBB);
8749 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
8750 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
8751 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
8752 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
8753 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
8754 BB = EmitAtomicBinary(MI, BB, 4, PPC::ADD4);
8755 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
8756 BB = EmitAtomicBinary(MI, BB, 8, PPC::ADD8);
8758 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
8759 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
8760 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
8761 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
8762 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
8763 BB = EmitAtomicBinary(MI, BB, 4, PPC::AND);
8764 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
8765 BB = EmitAtomicBinary(MI, BB, 8, PPC::AND8);
8767 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
8768 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
8769 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
8770 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
8771 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
8772 BB = EmitAtomicBinary(MI, BB, 4, PPC::OR);
8773 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
8774 BB = EmitAtomicBinary(MI, BB, 8, PPC::OR8);
8776 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
8777 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
8778 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
8779 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
8780 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
8781 BB = EmitAtomicBinary(MI, BB, 4, PPC::XOR);
8782 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
8783 BB = EmitAtomicBinary(MI, BB, 8, PPC::XOR8);
8785 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
8786 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
8787 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
8788 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
8789 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
8790 BB = EmitAtomicBinary(MI, BB, 4, PPC::NAND);
8791 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
8792 BB = EmitAtomicBinary(MI, BB, 8, PPC::NAND8);
8794 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
8795 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
8796 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
8797 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
8798 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
8799 BB = EmitAtomicBinary(MI, BB, 4, PPC::SUBF);
8800 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
8801 BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8);
8803 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
8804 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
8805 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
8806 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
8807 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
8808 BB = EmitAtomicBinary(MI, BB, 4, 0);
8809 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
8810 BB = EmitAtomicBinary(MI, BB, 8, 0);
8812 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
8813 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 ||
8814 (Subtarget.hasPartwordAtomics() &&
8815 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) ||
8816 (Subtarget.hasPartwordAtomics() &&
8817 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) {
8818 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
8820 auto LoadMnemonic = PPC::LDARX;
8821 auto StoreMnemonic = PPC::STDCX;
8822 switch(MI->getOpcode()) {
8824 llvm_unreachable("Compare and swap of unknown size");
8825 case PPC::ATOMIC_CMP_SWAP_I8:
8826 LoadMnemonic = PPC::LBARX;
8827 StoreMnemonic = PPC::STBCX;
8828 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8830 case PPC::ATOMIC_CMP_SWAP_I16:
8831 LoadMnemonic = PPC::LHARX;
8832 StoreMnemonic = PPC::STHCX;
8833 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8835 case PPC::ATOMIC_CMP_SWAP_I32:
8836 LoadMnemonic = PPC::LWARX;
8837 StoreMnemonic = PPC::STWCX;
8839 case PPC::ATOMIC_CMP_SWAP_I64:
8840 LoadMnemonic = PPC::LDARX;
8841 StoreMnemonic = PPC::STDCX;
8844 unsigned dest = MI->getOperand(0).getReg();
8845 unsigned ptrA = MI->getOperand(1).getReg();
8846 unsigned ptrB = MI->getOperand(2).getReg();
8847 unsigned oldval = MI->getOperand(3).getReg();
8848 unsigned newval = MI->getOperand(4).getReg();
8849 DebugLoc dl = MI->getDebugLoc();
8851 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8852 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8853 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8854 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8855 F->insert(It, loop1MBB);
8856 F->insert(It, loop2MBB);
8857 F->insert(It, midMBB);
8858 F->insert(It, exitMBB);
8859 exitMBB->splice(exitMBB->begin(), BB,
8860 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8861 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8865 // fallthrough --> loopMBB
8866 BB->addSuccessor(loop1MBB);
8869 // l[bhwd]arx dest, ptr
8870 // cmp[wd] dest, oldval
8873 // st[bhwd]cx. newval, ptr
8877 // st[bhwd]cx. dest, ptr
8880 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8881 .addReg(ptrA).addReg(ptrB);
8882 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
8883 .addReg(oldval).addReg(dest);
8884 BuildMI(BB, dl, TII->get(PPC::BCC))
8885 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
8886 BB->addSuccessor(loop2MBB);
8887 BB->addSuccessor(midMBB);
8890 BuildMI(BB, dl, TII->get(StoreMnemonic))
8891 .addReg(newval).addReg(ptrA).addReg(ptrB);
8892 BuildMI(BB, dl, TII->get(PPC::BCC))
8893 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
8894 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
8895 BB->addSuccessor(loop1MBB);
8896 BB->addSuccessor(exitMBB);
8899 BuildMI(BB, dl, TII->get(StoreMnemonic))
8900 .addReg(dest).addReg(ptrA).addReg(ptrB);
8901 BB->addSuccessor(exitMBB);
8906 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
8907 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
8908 // We must use 64-bit registers for addresses when targeting 64-bit,
8909 // since we're actually doing arithmetic on them. Other registers
8911 bool is64bit = Subtarget.isPPC64();
8912 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
8914 unsigned dest = MI->getOperand(0).getReg();
8915 unsigned ptrA = MI->getOperand(1).getReg();
8916 unsigned ptrB = MI->getOperand(2).getReg();
8917 unsigned oldval = MI->getOperand(3).getReg();
8918 unsigned newval = MI->getOperand(4).getReg();
8919 DebugLoc dl = MI->getDebugLoc();
8921 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8922 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8923 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8924 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8925 F->insert(It, loop1MBB);
8926 F->insert(It, loop2MBB);
8927 F->insert(It, midMBB);
8928 F->insert(It, exitMBB);
8929 exitMBB->splice(exitMBB->begin(), BB,
8930 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8931 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8933 MachineRegisterInfo &RegInfo = F->getRegInfo();
8934 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8935 : &PPC::GPRCRegClass;
8936 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8937 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8938 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8939 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
8940 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
8941 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
8942 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
8943 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8944 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8945 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8946 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8947 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8948 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8950 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
8951 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8954 // fallthrough --> loopMBB
8955 BB->addSuccessor(loop1MBB);
8957 // The 4-byte load must be aligned, while a char or short may be
8958 // anywhere in the word. Hence all this nasty bookkeeping code.
8959 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8960 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8961 // xori shift, shift1, 24 [16]
8962 // rlwinm ptr, ptr1, 0, 0, 29
8963 // slw newval2, newval, shift
8964 // slw oldval2, oldval,shift
8965 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8966 // slw mask, mask2, shift
8967 // and newval3, newval2, mask
8968 // and oldval3, oldval2, mask
8970 // lwarx tmpDest, ptr
8971 // and tmp, tmpDest, mask
8972 // cmpw tmp, oldval3
8975 // andc tmp2, tmpDest, mask
8976 // or tmp4, tmp2, newval3
8981 // stwcx. tmpDest, ptr
8983 // srw dest, tmpDest, shift
8984 if (ptrA != ZeroReg) {
8985 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8986 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8987 .addReg(ptrA).addReg(ptrB);
8991 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8992 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8993 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8994 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8996 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8997 .addReg(Ptr1Reg).addImm(0).addImm(61);
8999 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
9000 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
9001 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
9002 .addReg(newval).addReg(ShiftReg);
9003 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
9004 .addReg(oldval).addReg(ShiftReg);
9006 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
9008 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
9009 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
9010 .addReg(Mask3Reg).addImm(65535);
9012 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
9013 .addReg(Mask2Reg).addReg(ShiftReg);
9014 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
9015 .addReg(NewVal2Reg).addReg(MaskReg);
9016 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
9017 .addReg(OldVal2Reg).addReg(MaskReg);
9020 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
9021 .addReg(ZeroReg).addReg(PtrReg);
9022 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
9023 .addReg(TmpDestReg).addReg(MaskReg);
9024 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
9025 .addReg(TmpReg).addReg(OldVal3Reg);
9026 BuildMI(BB, dl, TII->get(PPC::BCC))
9027 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
9028 BB->addSuccessor(loop2MBB);
9029 BB->addSuccessor(midMBB);
9032 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
9033 .addReg(TmpDestReg).addReg(MaskReg);
9034 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
9035 .addReg(Tmp2Reg).addReg(NewVal3Reg);
9036 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
9037 .addReg(ZeroReg).addReg(PtrReg);
9038 BuildMI(BB, dl, TII->get(PPC::BCC))
9039 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
9040 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
9041 BB->addSuccessor(loop1MBB);
9042 BB->addSuccessor(exitMBB);
9045 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
9046 .addReg(ZeroReg).addReg(PtrReg);
9047 BB->addSuccessor(exitMBB);
9052 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
9054 } else if (MI->getOpcode() == PPC::FADDrtz) {
9055 // This pseudo performs an FADD with rounding mode temporarily forced
9056 // to round-to-zero. We emit this via custom inserter since the FPSCR
9057 // is not modeled at the SelectionDAG level.
9058 unsigned Dest = MI->getOperand(0).getReg();
9059 unsigned Src1 = MI->getOperand(1).getReg();
9060 unsigned Src2 = MI->getOperand(2).getReg();
9061 DebugLoc dl = MI->getDebugLoc();
9063 MachineRegisterInfo &RegInfo = F->getRegInfo();
9064 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
9066 // Save FPSCR value.
9067 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
9069 // Set rounding mode to round-to-zero.
9070 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
9071 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
9073 // Perform addition.
9074 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
9076 // Restore FPSCR value.
9077 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
9078 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9079 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
9080 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9081 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
9082 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9083 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
9084 PPC::ANDIo8 : PPC::ANDIo;
9085 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9086 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
9088 MachineRegisterInfo &RegInfo = F->getRegInfo();
9089 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
9090 &PPC::GPRCRegClass :
9091 &PPC::G8RCRegClass);
9093 DebugLoc dl = MI->getDebugLoc();
9094 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
9095 .addReg(MI->getOperand(1).getReg()).addImm(1);
9096 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
9097 MI->getOperand(0).getReg())
9098 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
9099 } else if (MI->getOpcode() == PPC::TCHECK_RET) {
9100 DebugLoc Dl = MI->getDebugLoc();
9101 MachineRegisterInfo &RegInfo = F->getRegInfo();
9102 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
9103 BuildMI(*BB, MI, Dl, TII->get(PPC::TCHECK), CRReg);
9106 llvm_unreachable("Unexpected instr type to insert");
9109 MI->eraseFromParent(); // The pseudo instruction is gone now.
9113 //===----------------------------------------------------------------------===//
9114 // Target Optimization Hooks
9115 //===----------------------------------------------------------------------===//
9117 static std::string getRecipOp(const char *Base, EVT VT) {
9118 std::string RecipOp(Base);
9119 if (VT.getScalarType() == MVT::f64)
9125 RecipOp = "vec-" + RecipOp;
9130 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
9131 DAGCombinerInfo &DCI,
9132 unsigned &RefinementSteps,
9133 bool &UseOneConstNR) const {
9134 EVT VT = Operand.getValueType();
9135 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
9136 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
9137 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9138 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9139 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9140 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9141 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
9142 std::string RecipOp = getRecipOp("sqrt", VT);
9143 if (!Recips.isEnabled(RecipOp))
9146 RefinementSteps = Recips.getRefinementSteps(RecipOp);
9147 UseOneConstNR = true;
9148 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
9153 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
9154 DAGCombinerInfo &DCI,
9155 unsigned &RefinementSteps) const {
9156 EVT VT = Operand.getValueType();
9157 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
9158 (VT == MVT::f64 && Subtarget.hasFRE()) ||
9159 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9160 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9161 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9162 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9163 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
9164 std::string RecipOp = getRecipOp("div", VT);
9165 if (!Recips.isEnabled(RecipOp))
9168 RefinementSteps = Recips.getRefinementSteps(RecipOp);
9169 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
9174 unsigned PPCTargetLowering::combineRepeatedFPDivisors() const {
9175 // Note: This functionality is used only when unsafe-fp-math is enabled, and
9176 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
9177 // enabled for division), this functionality is redundant with the default
9178 // combiner logic (once the division -> reciprocal/multiply transformation
9179 // has taken place). As a result, this matters more for older cores than for
9182 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9183 // reciprocal if there are two or more FDIVs (for embedded cores with only
9184 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
9185 switch (Subtarget.getDarwinDirective()) {
9190 case PPC::DIR_E500mc:
9191 case PPC::DIR_E5500:
9196 // isConsecutiveLSLoc needs to work even if all adds have not yet been
9197 // collapsed, and so we need to look through chains of them.
9198 static void getBaseWithConstantOffset(SDValue Loc, SDValue &Base,
9199 int64_t& Offset, SelectionDAG &DAG) {
9200 if (DAG.isBaseWithConstantOffset(Loc)) {
9201 Base = Loc.getOperand(0);
9202 Offset += cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue();
9204 // The base might itself be a base plus an offset, and if so, accumulate
9206 getBaseWithConstantOffset(Loc.getOperand(0), Base, Offset, DAG);
9210 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
9211 unsigned Bytes, int Dist,
9212 SelectionDAG &DAG) {
9213 if (VT.getSizeInBits() / 8 != Bytes)
9216 SDValue BaseLoc = Base->getBasePtr();
9217 if (Loc.getOpcode() == ISD::FrameIndex) {
9218 if (BaseLoc.getOpcode() != ISD::FrameIndex)
9220 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9221 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
9222 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
9223 int FS = MFI->getObjectSize(FI);
9224 int BFS = MFI->getObjectSize(BFI);
9225 if (FS != BFS || FS != (int)Bytes) return false;
9226 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
9229 SDValue Base1 = Loc, Base2 = BaseLoc;
9230 int64_t Offset1 = 0, Offset2 = 0;
9231 getBaseWithConstantOffset(Loc, Base1, Offset1, DAG);
9232 getBaseWithConstantOffset(BaseLoc, Base2, Offset2, DAG);
9233 if (Base1 == Base2 && Offset1 == (Offset2 + Dist * Bytes))
9236 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9237 const GlobalValue *GV1 = nullptr;
9238 const GlobalValue *GV2 = nullptr;
9241 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
9242 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
9243 if (isGA1 && isGA2 && GV1 == GV2)
9244 return Offset1 == (Offset2 + Dist*Bytes);
9248 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
9249 // not enforce equality of the chain operands.
9250 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
9251 unsigned Bytes, int Dist,
9252 SelectionDAG &DAG) {
9253 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
9254 EVT VT = LS->getMemoryVT();
9255 SDValue Loc = LS->getBasePtr();
9256 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
9259 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
9261 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9262 default: return false;
9263 case Intrinsic::ppc_qpx_qvlfd:
9264 case Intrinsic::ppc_qpx_qvlfda:
9267 case Intrinsic::ppc_qpx_qvlfs:
9268 case Intrinsic::ppc_qpx_qvlfsa:
9271 case Intrinsic::ppc_qpx_qvlfcd:
9272 case Intrinsic::ppc_qpx_qvlfcda:
9275 case Intrinsic::ppc_qpx_qvlfcs:
9276 case Intrinsic::ppc_qpx_qvlfcsa:
9279 case Intrinsic::ppc_qpx_qvlfiwa:
9280 case Intrinsic::ppc_qpx_qvlfiwz:
9281 case Intrinsic::ppc_altivec_lvx:
9282 case Intrinsic::ppc_altivec_lvxl:
9283 case Intrinsic::ppc_vsx_lxvw4x:
9286 case Intrinsic::ppc_vsx_lxvd2x:
9289 case Intrinsic::ppc_altivec_lvebx:
9292 case Intrinsic::ppc_altivec_lvehx:
9295 case Intrinsic::ppc_altivec_lvewx:
9300 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
9303 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
9305 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9306 default: return false;
9307 case Intrinsic::ppc_qpx_qvstfd:
9308 case Intrinsic::ppc_qpx_qvstfda:
9311 case Intrinsic::ppc_qpx_qvstfs:
9312 case Intrinsic::ppc_qpx_qvstfsa:
9315 case Intrinsic::ppc_qpx_qvstfcd:
9316 case Intrinsic::ppc_qpx_qvstfcda:
9319 case Intrinsic::ppc_qpx_qvstfcs:
9320 case Intrinsic::ppc_qpx_qvstfcsa:
9323 case Intrinsic::ppc_qpx_qvstfiw:
9324 case Intrinsic::ppc_qpx_qvstfiwa:
9325 case Intrinsic::ppc_altivec_stvx:
9326 case Intrinsic::ppc_altivec_stvxl:
9327 case Intrinsic::ppc_vsx_stxvw4x:
9330 case Intrinsic::ppc_vsx_stxvd2x:
9333 case Intrinsic::ppc_altivec_stvebx:
9336 case Intrinsic::ppc_altivec_stvehx:
9339 case Intrinsic::ppc_altivec_stvewx:
9344 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
9350 // Return true is there is a nearyby consecutive load to the one provided
9351 // (regardless of alignment). We search up and down the chain, looking though
9352 // token factors and other loads (but nothing else). As a result, a true result
9353 // indicates that it is safe to create a new consecutive load adjacent to the
9355 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
9356 SDValue Chain = LD->getChain();
9357 EVT VT = LD->getMemoryVT();
9359 SmallSet<SDNode *, 16> LoadRoots;
9360 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
9361 SmallSet<SDNode *, 16> Visited;
9363 // First, search up the chain, branching to follow all token-factor operands.
9364 // If we find a consecutive load, then we're done, otherwise, record all
9365 // nodes just above the top-level loads and token factors.
9366 while (!Queue.empty()) {
9367 SDNode *ChainNext = Queue.pop_back_val();
9368 if (!Visited.insert(ChainNext).second)
9371 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
9372 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9375 if (!Visited.count(ChainLD->getChain().getNode()))
9376 Queue.push_back(ChainLD->getChain().getNode());
9377 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
9378 for (const SDUse &O : ChainNext->ops())
9379 if (!Visited.count(O.getNode()))
9380 Queue.push_back(O.getNode());
9382 LoadRoots.insert(ChainNext);
9385 // Second, search down the chain, starting from the top-level nodes recorded
9386 // in the first phase. These top-level nodes are the nodes just above all
9387 // loads and token factors. Starting with their uses, recursively look though
9388 // all loads (just the chain uses) and token factors to find a consecutive
9393 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
9394 IE = LoadRoots.end(); I != IE; ++I) {
9395 Queue.push_back(*I);
9397 while (!Queue.empty()) {
9398 SDNode *LoadRoot = Queue.pop_back_val();
9399 if (!Visited.insert(LoadRoot).second)
9402 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
9403 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9406 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
9407 UE = LoadRoot->use_end(); UI != UE; ++UI)
9408 if (((isa<MemSDNode>(*UI) &&
9409 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
9410 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
9411 Queue.push_back(*UI);
9418 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
9419 DAGCombinerInfo &DCI) const {
9420 SelectionDAG &DAG = DCI.DAG;
9423 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits");
9424 // If we're tracking CR bits, we need to be careful that we don't have:
9425 // trunc(binary-ops(zext(x), zext(y)))
9427 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
9428 // such that we're unnecessarily moving things into GPRs when it would be
9429 // better to keep them in CR bits.
9431 // Note that trunc here can be an actual i1 trunc, or can be the effective
9432 // truncation that comes from a setcc or select_cc.
9433 if (N->getOpcode() == ISD::TRUNCATE &&
9434 N->getValueType(0) != MVT::i1)
9437 if (N->getOperand(0).getValueType() != MVT::i32 &&
9438 N->getOperand(0).getValueType() != MVT::i64)
9441 if (N->getOpcode() == ISD::SETCC ||
9442 N->getOpcode() == ISD::SELECT_CC) {
9443 // If we're looking at a comparison, then we need to make sure that the
9444 // high bits (all except for the first) don't matter the result.
9446 cast<CondCodeSDNode>(N->getOperand(
9447 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
9448 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
9450 if (ISD::isSignedIntSetCC(CC)) {
9451 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
9452 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
9454 } else if (ISD::isUnsignedIntSetCC(CC)) {
9455 if (!DAG.MaskedValueIsZero(N->getOperand(0),
9456 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
9457 !DAG.MaskedValueIsZero(N->getOperand(1),
9458 APInt::getHighBitsSet(OpBits, OpBits-1)))
9461 // This is neither a signed nor an unsigned comparison, just make sure
9462 // that the high bits are equal.
9463 APInt Op1Zero, Op1One;
9464 APInt Op2Zero, Op2One;
9465 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
9466 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
9468 // We don't really care about what is known about the first bit (if
9469 // anything), so clear it in all masks prior to comparing them.
9470 Op1Zero.clearBit(0); Op1One.clearBit(0);
9471 Op2Zero.clearBit(0); Op2One.clearBit(0);
9473 if (Op1Zero != Op2Zero || Op1One != Op2One)
9478 // We now know that the higher-order bits are irrelevant, we just need to
9479 // make sure that all of the intermediate operations are bit operations, and
9480 // all inputs are extensions.
9481 if (N->getOperand(0).getOpcode() != ISD::AND &&
9482 N->getOperand(0).getOpcode() != ISD::OR &&
9483 N->getOperand(0).getOpcode() != ISD::XOR &&
9484 N->getOperand(0).getOpcode() != ISD::SELECT &&
9485 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
9486 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
9487 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
9488 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
9489 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
9492 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
9493 N->getOperand(1).getOpcode() != ISD::AND &&
9494 N->getOperand(1).getOpcode() != ISD::OR &&
9495 N->getOperand(1).getOpcode() != ISD::XOR &&
9496 N->getOperand(1).getOpcode() != ISD::SELECT &&
9497 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
9498 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
9499 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
9500 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
9501 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
9504 SmallVector<SDValue, 4> Inputs;
9505 SmallVector<SDValue, 8> BinOps, PromOps;
9506 SmallPtrSet<SDNode *, 16> Visited;
9508 for (unsigned i = 0; i < 2; ++i) {
9509 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9510 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9511 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9512 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9513 isa<ConstantSDNode>(N->getOperand(i)))
9514 Inputs.push_back(N->getOperand(i));
9516 BinOps.push_back(N->getOperand(i));
9518 if (N->getOpcode() == ISD::TRUNCATE)
9522 // Visit all inputs, collect all binary operations (and, or, xor and
9523 // select) that are all fed by extensions.
9524 while (!BinOps.empty()) {
9525 SDValue BinOp = BinOps.back();
9528 if (!Visited.insert(BinOp.getNode()).second)
9531 PromOps.push_back(BinOp);
9533 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9534 // The condition of the select is not promoted.
9535 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9537 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9540 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9541 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9542 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9543 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9544 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9545 Inputs.push_back(BinOp.getOperand(i));
9546 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9547 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9548 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9549 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9550 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
9551 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9552 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9553 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9554 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
9555 BinOps.push_back(BinOp.getOperand(i));
9557 // We have an input that is not an extension or another binary
9558 // operation; we'll abort this transformation.
9564 // Make sure that this is a self-contained cluster of operations (which
9565 // is not quite the same thing as saying that everything has only one
9567 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9568 if (isa<ConstantSDNode>(Inputs[i]))
9571 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9572 UE = Inputs[i].getNode()->use_end();
9575 if (User != N && !Visited.count(User))
9578 // Make sure that we're not going to promote the non-output-value
9579 // operand(s) or SELECT or SELECT_CC.
9580 // FIXME: Although we could sometimes handle this, and it does occur in
9581 // practice that one of the condition inputs to the select is also one of
9582 // the outputs, we currently can't deal with this.
9583 if (User->getOpcode() == ISD::SELECT) {
9584 if (User->getOperand(0) == Inputs[i])
9586 } else if (User->getOpcode() == ISD::SELECT_CC) {
9587 if (User->getOperand(0) == Inputs[i] ||
9588 User->getOperand(1) == Inputs[i])
9594 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9595 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9596 UE = PromOps[i].getNode()->use_end();
9599 if (User != N && !Visited.count(User))
9602 // Make sure that we're not going to promote the non-output-value
9603 // operand(s) or SELECT or SELECT_CC.
9604 // FIXME: Although we could sometimes handle this, and it does occur in
9605 // practice that one of the condition inputs to the select is also one of
9606 // the outputs, we currently can't deal with this.
9607 if (User->getOpcode() == ISD::SELECT) {
9608 if (User->getOperand(0) == PromOps[i])
9610 } else if (User->getOpcode() == ISD::SELECT_CC) {
9611 if (User->getOperand(0) == PromOps[i] ||
9612 User->getOperand(1) == PromOps[i])
9618 // Replace all inputs with the extension operand.
9619 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9620 // Constants may have users outside the cluster of to-be-promoted nodes,
9621 // and so we need to replace those as we do the promotions.
9622 if (isa<ConstantSDNode>(Inputs[i]))
9625 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
9628 // Replace all operations (these are all the same, but have a different
9629 // (i1) return type). DAG.getNode will validate that the types of
9630 // a binary operator match, so go through the list in reverse so that
9631 // we've likely promoted both operands first. Any intermediate truncations or
9632 // extensions disappear.
9633 while (!PromOps.empty()) {
9634 SDValue PromOp = PromOps.back();
9637 if (PromOp.getOpcode() == ISD::TRUNCATE ||
9638 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
9639 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
9640 PromOp.getOpcode() == ISD::ANY_EXTEND) {
9641 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
9642 PromOp.getOperand(0).getValueType() != MVT::i1) {
9643 // The operand is not yet ready (see comment below).
9644 PromOps.insert(PromOps.begin(), PromOp);
9648 SDValue RepValue = PromOp.getOperand(0);
9649 if (isa<ConstantSDNode>(RepValue))
9650 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
9652 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
9657 switch (PromOp.getOpcode()) {
9658 default: C = 0; break;
9659 case ISD::SELECT: C = 1; break;
9660 case ISD::SELECT_CC: C = 2; break;
9663 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9664 PromOp.getOperand(C).getValueType() != MVT::i1) ||
9665 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9666 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
9667 // The to-be-promoted operands of this node have not yet been
9668 // promoted (this should be rare because we're going through the
9669 // list backward, but if one of the operands has several users in
9670 // this cluster of to-be-promoted nodes, it is possible).
9671 PromOps.insert(PromOps.begin(), PromOp);
9675 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9676 PromOp.getNode()->op_end());
9678 // If there are any constant inputs, make sure they're replaced now.
9679 for (unsigned i = 0; i < 2; ++i)
9680 if (isa<ConstantSDNode>(Ops[C+i]))
9681 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
9683 DAG.ReplaceAllUsesOfValueWith(PromOp,
9684 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
9687 // Now we're left with the initial truncation itself.
9688 if (N->getOpcode() == ISD::TRUNCATE)
9689 return N->getOperand(0);
9691 // Otherwise, this is a comparison. The operands to be compared have just
9692 // changed type (to i1), but everything else is the same.
9693 return SDValue(N, 0);
9696 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
9697 DAGCombinerInfo &DCI) const {
9698 SelectionDAG &DAG = DCI.DAG;
9701 // If we're tracking CR bits, we need to be careful that we don't have:
9702 // zext(binary-ops(trunc(x), trunc(y)))
9704 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
9705 // such that we're unnecessarily moving things into CR bits that can more
9706 // efficiently stay in GPRs. Note that if we're not certain that the high
9707 // bits are set as required by the final extension, we still may need to do
9708 // some masking to get the proper behavior.
9710 // This same functionality is important on PPC64 when dealing with
9711 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
9712 // the return values of functions. Because it is so similar, it is handled
9715 if (N->getValueType(0) != MVT::i32 &&
9716 N->getValueType(0) != MVT::i64)
9719 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
9720 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
9723 if (N->getOperand(0).getOpcode() != ISD::AND &&
9724 N->getOperand(0).getOpcode() != ISD::OR &&
9725 N->getOperand(0).getOpcode() != ISD::XOR &&
9726 N->getOperand(0).getOpcode() != ISD::SELECT &&
9727 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
9730 SmallVector<SDValue, 4> Inputs;
9731 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
9732 SmallPtrSet<SDNode *, 16> Visited;
9734 // Visit all inputs, collect all binary operations (and, or, xor and
9735 // select) that are all fed by truncations.
9736 while (!BinOps.empty()) {
9737 SDValue BinOp = BinOps.back();
9740 if (!Visited.insert(BinOp.getNode()).second)
9743 PromOps.push_back(BinOp);
9745 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9746 // The condition of the select is not promoted.
9747 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9749 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9752 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9753 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9754 Inputs.push_back(BinOp.getOperand(i));
9755 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9756 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9757 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9758 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9759 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
9760 BinOps.push_back(BinOp.getOperand(i));
9762 // We have an input that is not a truncation or another binary
9763 // operation; we'll abort this transformation.
9769 // The operands of a select that must be truncated when the select is
9770 // promoted because the operand is actually part of the to-be-promoted set.
9771 DenseMap<SDNode *, EVT> SelectTruncOp[2];
9773 // Make sure that this is a self-contained cluster of operations (which
9774 // is not quite the same thing as saying that everything has only one
9776 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9777 if (isa<ConstantSDNode>(Inputs[i]))
9780 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9781 UE = Inputs[i].getNode()->use_end();
9784 if (User != N && !Visited.count(User))
9787 // If we're going to promote the non-output-value operand(s) or SELECT or
9788 // SELECT_CC, record them for truncation.
9789 if (User->getOpcode() == ISD::SELECT) {
9790 if (User->getOperand(0) == Inputs[i])
9791 SelectTruncOp[0].insert(std::make_pair(User,
9792 User->getOperand(0).getValueType()));
9793 } else if (User->getOpcode() == ISD::SELECT_CC) {
9794 if (User->getOperand(0) == Inputs[i])
9795 SelectTruncOp[0].insert(std::make_pair(User,
9796 User->getOperand(0).getValueType()));
9797 if (User->getOperand(1) == Inputs[i])
9798 SelectTruncOp[1].insert(std::make_pair(User,
9799 User->getOperand(1).getValueType()));
9804 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9805 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9806 UE = PromOps[i].getNode()->use_end();
9809 if (User != N && !Visited.count(User))
9812 // If we're going to promote the non-output-value operand(s) or SELECT or
9813 // SELECT_CC, record them for truncation.
9814 if (User->getOpcode() == ISD::SELECT) {
9815 if (User->getOperand(0) == PromOps[i])
9816 SelectTruncOp[0].insert(std::make_pair(User,
9817 User->getOperand(0).getValueType()));
9818 } else if (User->getOpcode() == ISD::SELECT_CC) {
9819 if (User->getOperand(0) == PromOps[i])
9820 SelectTruncOp[0].insert(std::make_pair(User,
9821 User->getOperand(0).getValueType()));
9822 if (User->getOperand(1) == PromOps[i])
9823 SelectTruncOp[1].insert(std::make_pair(User,
9824 User->getOperand(1).getValueType()));
9829 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
9830 bool ReallyNeedsExt = false;
9831 if (N->getOpcode() != ISD::ANY_EXTEND) {
9832 // If all of the inputs are not already sign/zero extended, then
9833 // we'll still need to do that at the end.
9834 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9835 if (isa<ConstantSDNode>(Inputs[i]))
9839 Inputs[i].getOperand(0).getValueSizeInBits();
9840 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
9842 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
9843 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
9844 APInt::getHighBitsSet(OpBits,
9845 OpBits-PromBits))) ||
9846 (N->getOpcode() == ISD::SIGN_EXTEND &&
9847 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
9848 (OpBits-(PromBits-1)))) {
9849 ReallyNeedsExt = true;
9855 // Replace all inputs, either with the truncation operand, or a
9856 // truncation or extension to the final output type.
9857 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9858 // Constant inputs need to be replaced with the to-be-promoted nodes that
9859 // use them because they might have users outside of the cluster of
9861 if (isa<ConstantSDNode>(Inputs[i]))
9864 SDValue InSrc = Inputs[i].getOperand(0);
9865 if (Inputs[i].getValueType() == N->getValueType(0))
9866 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
9867 else if (N->getOpcode() == ISD::SIGN_EXTEND)
9868 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9869 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
9870 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9871 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9872 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
9874 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9875 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
9878 // Replace all operations (these are all the same, but have a different
9879 // (promoted) return type). DAG.getNode will validate that the types of
9880 // a binary operator match, so go through the list in reverse so that
9881 // we've likely promoted both operands first.
9882 while (!PromOps.empty()) {
9883 SDValue PromOp = PromOps.back();
9887 switch (PromOp.getOpcode()) {
9888 default: C = 0; break;
9889 case ISD::SELECT: C = 1; break;
9890 case ISD::SELECT_CC: C = 2; break;
9893 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9894 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
9895 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9896 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
9897 // The to-be-promoted operands of this node have not yet been
9898 // promoted (this should be rare because we're going through the
9899 // list backward, but if one of the operands has several users in
9900 // this cluster of to-be-promoted nodes, it is possible).
9901 PromOps.insert(PromOps.begin(), PromOp);
9905 // For SELECT and SELECT_CC nodes, we do a similar check for any
9906 // to-be-promoted comparison inputs.
9907 if (PromOp.getOpcode() == ISD::SELECT ||
9908 PromOp.getOpcode() == ISD::SELECT_CC) {
9909 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
9910 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
9911 (SelectTruncOp[1].count(PromOp.getNode()) &&
9912 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
9913 PromOps.insert(PromOps.begin(), PromOp);
9918 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9919 PromOp.getNode()->op_end());
9921 // If this node has constant inputs, then they'll need to be promoted here.
9922 for (unsigned i = 0; i < 2; ++i) {
9923 if (!isa<ConstantSDNode>(Ops[C+i]))
9925 if (Ops[C+i].getValueType() == N->getValueType(0))
9928 if (N->getOpcode() == ISD::SIGN_EXTEND)
9929 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9930 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9931 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9933 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9936 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
9937 // truncate them again to the original value type.
9938 if (PromOp.getOpcode() == ISD::SELECT ||
9939 PromOp.getOpcode() == ISD::SELECT_CC) {
9940 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
9941 if (SI0 != SelectTruncOp[0].end())
9942 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
9943 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
9944 if (SI1 != SelectTruncOp[1].end())
9945 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
9948 DAG.ReplaceAllUsesOfValueWith(PromOp,
9949 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
9952 // Now we're left with the initial extension itself.
9953 if (!ReallyNeedsExt)
9954 return N->getOperand(0);
9956 // To zero extend, just mask off everything except for the first bit (in the
9958 if (N->getOpcode() == ISD::ZERO_EXTEND)
9959 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
9960 DAG.getConstant(APInt::getLowBitsSet(
9961 N->getValueSizeInBits(0), PromBits),
9962 dl, N->getValueType(0)));
9964 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
9965 "Invalid extension type");
9966 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0), DAG.getDataLayout());
9968 DAG.getConstant(N->getValueSizeInBits(0) - PromBits, dl, ShiftAmountTy);
9970 ISD::SRA, dl, N->getValueType(0),
9971 DAG.getNode(ISD::SHL, dl, N->getValueType(0), N->getOperand(0), ShiftCst),
9975 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
9976 DAGCombinerInfo &DCI) const {
9977 assert((N->getOpcode() == ISD::SINT_TO_FP ||
9978 N->getOpcode() == ISD::UINT_TO_FP) &&
9979 "Need an int -> FP conversion node here");
9981 if (!Subtarget.has64BitSupport())
9984 SelectionDAG &DAG = DCI.DAG;
9988 // Don't handle ppc_fp128 here or i1 conversions.
9989 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
9991 if (Op.getOperand(0).getValueType() == MVT::i1)
9994 // For i32 intermediate values, unfortunately, the conversion functions
9995 // leave the upper 32 bits of the value are undefined. Within the set of
9996 // scalar instructions, we have no method for zero- or sign-extending the
9997 // value. Thus, we cannot handle i32 intermediate values here.
9998 if (Op.getOperand(0).getValueType() == MVT::i32)
10001 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
10002 "UINT_TO_FP is supported only with FPCVT");
10004 // If we have FCFIDS, then use it when converting to single-precision.
10005 // Otherwise, convert to double-precision and then round.
10006 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
10007 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
10009 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
10011 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
10015 // If we're converting from a float, to an int, and back to a float again,
10016 // then we don't need the store/load pair at all.
10017 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
10018 Subtarget.hasFPCVT()) ||
10019 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
10020 SDValue Src = Op.getOperand(0).getOperand(0);
10021 if (Src.getValueType() == MVT::f32) {
10022 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
10023 DCI.AddToWorklist(Src.getNode());
10024 } else if (Src.getValueType() != MVT::f64) {
10025 // Make sure that we don't pick up a ppc_fp128 source value.
10030 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
10033 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
10034 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
10036 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
10037 FP = DAG.getNode(ISD::FP_ROUND, dl,
10038 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
10039 DCI.AddToWorklist(FP.getNode());
10048 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
10049 // builtins) into loads with swaps.
10050 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
10051 DAGCombinerInfo &DCI) const {
10052 SelectionDAG &DAG = DCI.DAG;
10056 MachineMemOperand *MMO;
10058 switch (N->getOpcode()) {
10060 llvm_unreachable("Unexpected opcode for little endian VSX load");
10062 LoadSDNode *LD = cast<LoadSDNode>(N);
10063 Chain = LD->getChain();
10064 Base = LD->getBasePtr();
10065 MMO = LD->getMemOperand();
10066 // If the MMO suggests this isn't a load of a full vector, leave
10067 // things alone. For a built-in, we have to make the change for
10068 // correctness, so if there is a size problem that will be a bug.
10069 if (MMO->getSize() < 16)
10073 case ISD::INTRINSIC_W_CHAIN: {
10074 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
10075 Chain = Intrin->getChain();
10076 // Similarly to the store case below, Intrin->getBasePtr() doesn't get
10077 // us what we want. Get operand 2 instead.
10078 Base = Intrin->getOperand(2);
10079 MMO = Intrin->getMemOperand();
10084 MVT VecTy = N->getValueType(0).getSimpleVT();
10085 SDValue LoadOps[] = { Chain, Base };
10086 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
10087 DAG.getVTList(VecTy, MVT::Other),
10088 LoadOps, VecTy, MMO);
10089 DCI.AddToWorklist(Load.getNode());
10090 Chain = Load.getValue(1);
10091 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10092 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
10093 DCI.AddToWorklist(Swap.getNode());
10097 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
10098 // builtins) into stores with swaps.
10099 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
10100 DAGCombinerInfo &DCI) const {
10101 SelectionDAG &DAG = DCI.DAG;
10106 MachineMemOperand *MMO;
10108 switch (N->getOpcode()) {
10110 llvm_unreachable("Unexpected opcode for little endian VSX store");
10112 StoreSDNode *ST = cast<StoreSDNode>(N);
10113 Chain = ST->getChain();
10114 Base = ST->getBasePtr();
10115 MMO = ST->getMemOperand();
10117 // If the MMO suggests this isn't a store of a full vector, leave
10118 // things alone. For a built-in, we have to make the change for
10119 // correctness, so if there is a size problem that will be a bug.
10120 if (MMO->getSize() < 16)
10124 case ISD::INTRINSIC_VOID: {
10125 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
10126 Chain = Intrin->getChain();
10127 // Intrin->getBasePtr() oddly does not get what we want.
10128 Base = Intrin->getOperand(3);
10129 MMO = Intrin->getMemOperand();
10135 SDValue Src = N->getOperand(SrcOpnd);
10136 MVT VecTy = Src.getValueType().getSimpleVT();
10137 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10138 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
10139 DCI.AddToWorklist(Swap.getNode());
10140 Chain = Swap.getValue(1);
10141 SDValue StoreOps[] = { Chain, Swap, Base };
10142 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
10143 DAG.getVTList(MVT::Other),
10144 StoreOps, VecTy, MMO);
10145 DCI.AddToWorklist(Store.getNode());
10149 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
10150 DAGCombinerInfo &DCI) const {
10151 SelectionDAG &DAG = DCI.DAG;
10153 switch (N->getOpcode()) {
10156 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10157 if (C->isNullValue()) // 0 << V -> 0.
10158 return N->getOperand(0);
10162 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10163 if (C->isNullValue()) // 0 >>u V -> 0.
10164 return N->getOperand(0);
10168 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10169 if (C->isNullValue() || // 0 >>s V -> 0.
10170 C->isAllOnesValue()) // -1 >>s V -> -1.
10171 return N->getOperand(0);
10174 case ISD::SIGN_EXTEND:
10175 case ISD::ZERO_EXTEND:
10176 case ISD::ANY_EXTEND:
10177 return DAGCombineExtBoolTrunc(N, DCI);
10178 case ISD::TRUNCATE:
10180 case ISD::SELECT_CC:
10181 return DAGCombineTruncBoolExt(N, DCI);
10182 case ISD::SINT_TO_FP:
10183 case ISD::UINT_TO_FP:
10184 return combineFPToIntToFP(N, DCI);
10186 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
10187 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() &&
10188 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
10189 N->getOperand(1).getValueType() == MVT::i32 &&
10190 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
10191 SDValue Val = N->getOperand(1).getOperand(0);
10192 if (Val.getValueType() == MVT::f32) {
10193 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
10194 DCI.AddToWorklist(Val.getNode());
10196 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
10197 DCI.AddToWorklist(Val.getNode());
10200 N->getOperand(0), Val, N->getOperand(2),
10201 DAG.getValueType(N->getOperand(1).getValueType())
10204 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
10205 DAG.getVTList(MVT::Other), Ops,
10206 cast<StoreSDNode>(N)->getMemoryVT(),
10207 cast<StoreSDNode>(N)->getMemOperand());
10208 DCI.AddToWorklist(Val.getNode());
10212 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
10213 if (cast<StoreSDNode>(N)->isUnindexed() &&
10214 N->getOperand(1).getOpcode() == ISD::BSWAP &&
10215 N->getOperand(1).getNode()->hasOneUse() &&
10216 (N->getOperand(1).getValueType() == MVT::i32 ||
10217 N->getOperand(1).getValueType() == MVT::i16 ||
10218 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10219 N->getOperand(1).getValueType() == MVT::i64))) {
10220 SDValue BSwapOp = N->getOperand(1).getOperand(0);
10221 // Do an any-extend to 32-bits if this is a half-word input.
10222 if (BSwapOp.getValueType() == MVT::i16)
10223 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
10226 N->getOperand(0), BSwapOp, N->getOperand(2),
10227 DAG.getValueType(N->getOperand(1).getValueType())
10230 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
10231 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
10232 cast<StoreSDNode>(N)->getMemOperand());
10235 // For little endian, VSX stores require generating xxswapd/lxvd2x.
10236 EVT VT = N->getOperand(1).getValueType();
10237 if (VT.isSimple()) {
10238 MVT StoreVT = VT.getSimpleVT();
10239 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10240 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
10241 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
10242 return expandVSXStoreForLE(N, DCI);
10247 LoadSDNode *LD = cast<LoadSDNode>(N);
10248 EVT VT = LD->getValueType(0);
10250 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10251 if (VT.isSimple()) {
10252 MVT LoadVT = VT.getSimpleVT();
10253 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10254 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
10255 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
10256 return expandVSXLoadForLE(N, DCI);
10259 EVT MemVT = LD->getMemoryVT();
10260 Type *Ty = MemVT.getTypeForEVT(*DAG.getContext());
10261 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(Ty);
10262 Type *STy = MemVT.getScalarType().getTypeForEVT(*DAG.getContext());
10263 unsigned ScalarABIAlignment = DAG.getDataLayout().getABITypeAlignment(STy);
10264 if (LD->isUnindexed() && VT.isVector() &&
10265 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) &&
10266 // P8 and later hardware should just use LOAD.
10267 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 ||
10268 VT == MVT::v4i32 || VT == MVT::v4f32)) ||
10269 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) &&
10270 LD->getAlignment() >= ScalarABIAlignment)) &&
10271 LD->getAlignment() < ABIAlignment) {
10272 // This is a type-legal unaligned Altivec or QPX load.
10273 SDValue Chain = LD->getChain();
10274 SDValue Ptr = LD->getBasePtr();
10275 bool isLittleEndian = Subtarget.isLittleEndian();
10277 // This implements the loading of unaligned vectors as described in
10278 // the venerable Apple Velocity Engine overview. Specifically:
10279 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
10280 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
10282 // The general idea is to expand a sequence of one or more unaligned
10283 // loads into an alignment-based permutation-control instruction (lvsl
10284 // or lvsr), a series of regular vector loads (which always truncate
10285 // their input address to an aligned address), and a series of
10286 // permutations. The results of these permutations are the requested
10287 // loaded values. The trick is that the last "extra" load is not taken
10288 // from the address you might suspect (sizeof(vector) bytes after the
10289 // last requested load), but rather sizeof(vector) - 1 bytes after the
10290 // last requested vector. The point of this is to avoid a page fault if
10291 // the base address happened to be aligned. This works because if the
10292 // base address is aligned, then adding less than a full vector length
10293 // will cause the last vector in the sequence to be (re)loaded.
10294 // Otherwise, the next vector will be fetched as you might suspect was
10297 // We might be able to reuse the permutation generation from
10298 // a different base address offset from this one by an aligned amount.
10299 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
10300 // optimization later.
10301 Intrinsic::ID Intr, IntrLD, IntrPerm;
10302 MVT PermCntlTy, PermTy, LDTy;
10303 if (Subtarget.hasAltivec()) {
10304 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr :
10305 Intrinsic::ppc_altivec_lvsl;
10306 IntrLD = Intrinsic::ppc_altivec_lvx;
10307 IntrPerm = Intrinsic::ppc_altivec_vperm;
10308 PermCntlTy = MVT::v16i8;
10309 PermTy = MVT::v4i32;
10312 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld :
10313 Intrinsic::ppc_qpx_qvlpcls;
10314 IntrLD = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlfd :
10315 Intrinsic::ppc_qpx_qvlfs;
10316 IntrPerm = Intrinsic::ppc_qpx_qvfperm;
10317 PermCntlTy = MVT::v4f64;
10318 PermTy = MVT::v4f64;
10319 LDTy = MemVT.getSimpleVT();
10322 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, PermCntlTy);
10324 // Create the new MMO for the new base load. It is like the original MMO,
10325 // but represents an area in memory almost twice the vector size centered
10326 // on the original address. If the address is unaligned, we might start
10327 // reading up to (sizeof(vector)-1) bytes below the address of the
10328 // original unaligned load.
10329 MachineFunction &MF = DAG.getMachineFunction();
10330 MachineMemOperand *BaseMMO =
10331 MF.getMachineMemOperand(LD->getMemOperand(),
10332 -(long)MemVT.getStoreSize()+1,
10333 2*MemVT.getStoreSize()-1);
10335 // Create the new base load.
10337 DAG.getTargetConstant(IntrLD, dl, getPointerTy(MF.getDataLayout()));
10338 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
10340 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10341 DAG.getVTList(PermTy, MVT::Other),
10342 BaseLoadOps, LDTy, BaseMMO);
10344 // Note that the value of IncOffset (which is provided to the next
10345 // load's pointer info offset value, and thus used to calculate the
10346 // alignment), and the value of IncValue (which is actually used to
10347 // increment the pointer value) are different! This is because we
10348 // require the next load to appear to be aligned, even though it
10349 // is actually offset from the base pointer by a lesser amount.
10350 int IncOffset = VT.getSizeInBits() / 8;
10351 int IncValue = IncOffset;
10353 // Walk (both up and down) the chain looking for another load at the real
10354 // (aligned) offset (the alignment of the other load does not matter in
10355 // this case). If found, then do not use the offset reduction trick, as
10356 // that will prevent the loads from being later combined (as they would
10357 // otherwise be duplicates).
10358 if (!findConsecutiveLoad(LD, DAG))
10361 SDValue Increment =
10362 DAG.getConstant(IncValue, dl, getPointerTy(MF.getDataLayout()));
10363 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
10365 MachineMemOperand *ExtraMMO =
10366 MF.getMachineMemOperand(LD->getMemOperand(),
10367 1, 2*MemVT.getStoreSize()-1);
10368 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
10369 SDValue ExtraLoad =
10370 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10371 DAG.getVTList(PermTy, MVT::Other),
10372 ExtraLoadOps, LDTy, ExtraMMO);
10374 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
10375 BaseLoad.getValue(1), ExtraLoad.getValue(1));
10377 // Because vperm has a big-endian bias, we must reverse the order
10378 // of the input vectors and complement the permute control vector
10379 // when generating little endian code. We have already handled the
10380 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
10381 // and ExtraLoad here.
10383 if (isLittleEndian)
10384 Perm = BuildIntrinsicOp(IntrPerm,
10385 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
10387 Perm = BuildIntrinsicOp(IntrPerm,
10388 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
10391 Perm = Subtarget.hasAltivec() ?
10392 DAG.getNode(ISD::BITCAST, dl, VT, Perm) :
10393 DAG.getNode(ISD::FP_ROUND, dl, VT, Perm, // QPX
10394 DAG.getTargetConstant(1, dl, MVT::i64));
10395 // second argument is 1 because this rounding
10396 // is always exact.
10398 // The output of the permutation is our loaded result, the TokenFactor is
10400 DCI.CombineTo(N, Perm, TF);
10401 return SDValue(N, 0);
10405 case ISD::INTRINSIC_WO_CHAIN: {
10406 bool isLittleEndian = Subtarget.isLittleEndian();
10407 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
10408 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
10409 : Intrinsic::ppc_altivec_lvsl);
10410 if ((IID == Intr ||
10411 IID == Intrinsic::ppc_qpx_qvlpcld ||
10412 IID == Intrinsic::ppc_qpx_qvlpcls) &&
10413 N->getOperand(1)->getOpcode() == ISD::ADD) {
10414 SDValue Add = N->getOperand(1);
10416 int Bits = IID == Intrinsic::ppc_qpx_qvlpcld ?
10417 5 /* 32 byte alignment */ : 4 /* 16 byte alignment */;
10419 if (DAG.MaskedValueIsZero(
10420 Add->getOperand(1),
10421 APInt::getAllOnesValue(Bits /* alignment */)
10423 Add.getValueType().getScalarType().getSizeInBits()))) {
10424 SDNode *BasePtr = Add->getOperand(0).getNode();
10425 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10426 UE = BasePtr->use_end();
10428 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10429 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() == IID) {
10430 // We've found another LVSL/LVSR, and this address is an aligned
10431 // multiple of that one. The results will be the same, so use the
10432 // one we've just found instead.
10434 return SDValue(*UI, 0);
10439 if (isa<ConstantSDNode>(Add->getOperand(1))) {
10440 SDNode *BasePtr = Add->getOperand(0).getNode();
10441 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10442 UE = BasePtr->use_end(); UI != UE; ++UI) {
10443 if (UI->getOpcode() == ISD::ADD &&
10444 isa<ConstantSDNode>(UI->getOperand(1)) &&
10445 (cast<ConstantSDNode>(Add->getOperand(1))->getZExtValue() -
10446 cast<ConstantSDNode>(UI->getOperand(1))->getZExtValue()) %
10447 (1ULL << Bits) == 0) {
10448 SDNode *OtherAdd = *UI;
10449 for (SDNode::use_iterator VI = OtherAdd->use_begin(),
10450 VE = OtherAdd->use_end(); VI != VE; ++VI) {
10451 if (VI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10452 cast<ConstantSDNode>(VI->getOperand(0))->getZExtValue() == IID) {
10453 return SDValue(*VI, 0);
10463 case ISD::INTRINSIC_W_CHAIN: {
10464 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10465 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10466 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10469 case Intrinsic::ppc_vsx_lxvw4x:
10470 case Intrinsic::ppc_vsx_lxvd2x:
10471 return expandVSXLoadForLE(N, DCI);
10476 case ISD::INTRINSIC_VOID: {
10477 // For little endian, VSX stores require generating xxswapd/stxvd2x.
10478 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10479 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10482 case Intrinsic::ppc_vsx_stxvw4x:
10483 case Intrinsic::ppc_vsx_stxvd2x:
10484 return expandVSXStoreForLE(N, DCI);
10490 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
10491 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
10492 N->getOperand(0).hasOneUse() &&
10493 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
10494 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10495 N->getValueType(0) == MVT::i64))) {
10496 SDValue Load = N->getOperand(0);
10497 LoadSDNode *LD = cast<LoadSDNode>(Load);
10498 // Create the byte-swapping load.
10500 LD->getChain(), // Chain
10501 LD->getBasePtr(), // Ptr
10502 DAG.getValueType(N->getValueType(0)) // VT
10505 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
10506 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
10507 MVT::i64 : MVT::i32, MVT::Other),
10508 Ops, LD->getMemoryVT(), LD->getMemOperand());
10510 // If this is an i16 load, insert the truncate.
10511 SDValue ResVal = BSLoad;
10512 if (N->getValueType(0) == MVT::i16)
10513 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
10515 // First, combine the bswap away. This makes the value produced by the
10517 DCI.CombineTo(N, ResVal);
10519 // Next, combine the load away, we give it a bogus result value but a real
10520 // chain result. The result value is dead because the bswap is dead.
10521 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
10523 // Return N so it doesn't get rechecked!
10524 return SDValue(N, 0);
10528 case PPCISD::VCMP: {
10529 // If a VCMPo node already exists with exactly the same operands as this
10530 // node, use its result instead of this node (VCMPo computes both a CR6 and
10531 // a normal output).
10533 if (!N->getOperand(0).hasOneUse() &&
10534 !N->getOperand(1).hasOneUse() &&
10535 !N->getOperand(2).hasOneUse()) {
10537 // Scan all of the users of the LHS, looking for VCMPo's that match.
10538 SDNode *VCMPoNode = nullptr;
10540 SDNode *LHSN = N->getOperand(0).getNode();
10541 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
10543 if (UI->getOpcode() == PPCISD::VCMPo &&
10544 UI->getOperand(1) == N->getOperand(1) &&
10545 UI->getOperand(2) == N->getOperand(2) &&
10546 UI->getOperand(0) == N->getOperand(0)) {
10551 // If there is no VCMPo node, or if the flag value has a single use, don't
10553 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
10556 // Look at the (necessarily single) use of the flag value. If it has a
10557 // chain, this transformation is more complex. Note that multiple things
10558 // could use the value result, which we should ignore.
10559 SDNode *FlagUser = nullptr;
10560 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
10561 FlagUser == nullptr; ++UI) {
10562 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
10563 SDNode *User = *UI;
10564 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
10565 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
10572 // If the user is a MFOCRF instruction, we know this is safe.
10573 // Otherwise we give up for right now.
10574 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
10575 return SDValue(VCMPoNode, 0);
10579 case ISD::BRCOND: {
10580 SDValue Cond = N->getOperand(1);
10581 SDValue Target = N->getOperand(2);
10583 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10584 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
10585 Intrinsic::ppc_is_decremented_ctr_nonzero) {
10587 // We now need to make the intrinsic dead (it cannot be instruction
10589 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
10590 assert(Cond.getNode()->hasOneUse() &&
10591 "Counter decrement has more than one use");
10593 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
10594 N->getOperand(0), Target);
10599 // If this is a branch on an altivec predicate comparison, lower this so
10600 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
10601 // lowering is done pre-legalize, because the legalizer lowers the predicate
10602 // compare down to code that is difficult to reassemble.
10603 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
10604 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
10606 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
10607 // value. If so, pass-through the AND to get to the intrinsic.
10608 if (LHS.getOpcode() == ISD::AND &&
10609 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10610 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
10611 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10612 isa<ConstantSDNode>(LHS.getOperand(1)) &&
10613 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
10615 LHS = LHS.getOperand(0);
10617 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10618 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
10619 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10620 isa<ConstantSDNode>(RHS)) {
10621 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
10622 "Counter decrement comparison is not EQ or NE");
10624 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10625 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
10626 (CC == ISD::SETNE && !Val);
10628 // We now need to make the intrinsic dead (it cannot be instruction
10630 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
10631 assert(LHS.getNode()->hasOneUse() &&
10632 "Counter decrement has more than one use");
10634 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
10635 N->getOperand(0), N->getOperand(4));
10641 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10642 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
10643 getVectorCompareInfo(LHS, CompareOpc, isDot, Subtarget)) {
10644 assert(isDot && "Can't compare against a vector result!");
10646 // If this is a comparison against something other than 0/1, then we know
10647 // that the condition is never/always true.
10648 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10649 if (Val != 0 && Val != 1) {
10650 if (CC == ISD::SETEQ) // Cond never true, remove branch.
10651 return N->getOperand(0);
10652 // Always !=, turn it into an unconditional branch.
10653 return DAG.getNode(ISD::BR, dl, MVT::Other,
10654 N->getOperand(0), N->getOperand(4));
10657 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
10659 // Create the PPCISD altivec 'dot' comparison node.
10661 LHS.getOperand(2), // LHS of compare
10662 LHS.getOperand(3), // RHS of compare
10663 DAG.getConstant(CompareOpc, dl, MVT::i32)
10665 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
10666 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
10668 // Unpack the result based on how the target uses it.
10669 PPC::Predicate CompOpc;
10670 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
10671 default: // Can't happen, don't crash on invalid number though.
10672 case 0: // Branch on the value of the EQ bit of CR6.
10673 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
10675 case 1: // Branch on the inverted value of the EQ bit of CR6.
10676 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
10678 case 2: // Branch on the value of the LT bit of CR6.
10679 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
10681 case 3: // Branch on the inverted value of the LT bit of CR6.
10682 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
10686 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
10687 DAG.getConstant(CompOpc, dl, MVT::i32),
10688 DAG.getRegister(PPC::CR6, MVT::i32),
10689 N->getOperand(4), CompNode.getValue(1));
10699 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
10701 std::vector<SDNode *> *Created) const {
10702 // fold (sdiv X, pow2)
10703 EVT VT = N->getValueType(0);
10704 if (VT == MVT::i64 && !Subtarget.isPPC64())
10706 if ((VT != MVT::i32 && VT != MVT::i64) ||
10707 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
10711 SDValue N0 = N->getOperand(0);
10713 bool IsNegPow2 = (-Divisor).isPowerOf2();
10714 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
10715 SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT);
10717 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
10719 Created->push_back(Op.getNode());
10722 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Op);
10724 Created->push_back(Op.getNode());
10730 //===----------------------------------------------------------------------===//
10731 // Inline Assembly Support
10732 //===----------------------------------------------------------------------===//
10734 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10737 const SelectionDAG &DAG,
10738 unsigned Depth) const {
10739 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
10740 switch (Op.getOpcode()) {
10742 case PPCISD::LBRX: {
10743 // lhbrx is known to have the top bits cleared out.
10744 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
10745 KnownZero = 0xFFFF0000;
10748 case ISD::INTRINSIC_WO_CHAIN: {
10749 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
10751 case Intrinsic::ppc_altivec_vcmpbfp_p:
10752 case Intrinsic::ppc_altivec_vcmpeqfp_p:
10753 case Intrinsic::ppc_altivec_vcmpequb_p:
10754 case Intrinsic::ppc_altivec_vcmpequh_p:
10755 case Intrinsic::ppc_altivec_vcmpequw_p:
10756 case Intrinsic::ppc_altivec_vcmpequd_p:
10757 case Intrinsic::ppc_altivec_vcmpgefp_p:
10758 case Intrinsic::ppc_altivec_vcmpgtfp_p:
10759 case Intrinsic::ppc_altivec_vcmpgtsb_p:
10760 case Intrinsic::ppc_altivec_vcmpgtsh_p:
10761 case Intrinsic::ppc_altivec_vcmpgtsw_p:
10762 case Intrinsic::ppc_altivec_vcmpgtsd_p:
10763 case Intrinsic::ppc_altivec_vcmpgtub_p:
10764 case Intrinsic::ppc_altivec_vcmpgtuh_p:
10765 case Intrinsic::ppc_altivec_vcmpgtuw_p:
10766 case Intrinsic::ppc_altivec_vcmpgtud_p:
10767 KnownZero = ~1U; // All bits but the low one are known to be zero.
10774 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
10775 switch (Subtarget.getDarwinDirective()) {
10778 case PPC::DIR_PWR4:
10779 case PPC::DIR_PWR5:
10780 case PPC::DIR_PWR5X:
10781 case PPC::DIR_PWR6:
10782 case PPC::DIR_PWR6X:
10783 case PPC::DIR_PWR7:
10784 case PPC::DIR_PWR8: {
10788 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
10790 // For small loops (between 5 and 8 instructions), align to a 32-byte
10791 // boundary so that the entire loop fits in one instruction-cache line.
10792 uint64_t LoopSize = 0;
10793 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
10794 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
10795 LoopSize += TII->GetInstSizeInBytes(J);
10797 if (LoopSize > 16 && LoopSize <= 32)
10804 return TargetLowering::getPrefLoopAlignment(ML);
10807 /// getConstraintType - Given a constraint, return the type of
10808 /// constraint it is for this target.
10809 PPCTargetLowering::ConstraintType
10810 PPCTargetLowering::getConstraintType(StringRef Constraint) const {
10811 if (Constraint.size() == 1) {
10812 switch (Constraint[0]) {
10819 return C_RegisterClass;
10821 // FIXME: While Z does indicate a memory constraint, it specifically
10822 // indicates an r+r address (used in conjunction with the 'y' modifier
10823 // in the replacement string). Currently, we're forcing the base
10824 // register to be r0 in the asm printer (which is interpreted as zero)
10825 // and forming the complete address in the second register. This is
10829 } else if (Constraint == "wc") { // individual CR bits.
10830 return C_RegisterClass;
10831 } else if (Constraint == "wa" || Constraint == "wd" ||
10832 Constraint == "wf" || Constraint == "ws") {
10833 return C_RegisterClass; // VSX registers.
10835 return TargetLowering::getConstraintType(Constraint);
10838 /// Examine constraint type and operand type and determine a weight value.
10839 /// This object must already have been set up with the operand type
10840 /// and the current alternative constraint selected.
10841 TargetLowering::ConstraintWeight
10842 PPCTargetLowering::getSingleConstraintMatchWeight(
10843 AsmOperandInfo &info, const char *constraint) const {
10844 ConstraintWeight weight = CW_Invalid;
10845 Value *CallOperandVal = info.CallOperandVal;
10846 // If we don't have a value, we can't do a match,
10847 // but allow it at the lowest weight.
10848 if (!CallOperandVal)
10850 Type *type = CallOperandVal->getType();
10852 // Look at the constraint type.
10853 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
10854 return CW_Register; // an individual CR bit.
10855 else if ((StringRef(constraint) == "wa" ||
10856 StringRef(constraint) == "wd" ||
10857 StringRef(constraint) == "wf") &&
10858 type->isVectorTy())
10859 return CW_Register;
10860 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
10861 return CW_Register;
10863 switch (*constraint) {
10865 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10868 if (type->isIntegerTy())
10869 weight = CW_Register;
10872 if (type->isFloatTy())
10873 weight = CW_Register;
10876 if (type->isDoubleTy())
10877 weight = CW_Register;
10880 if (type->isVectorTy())
10881 weight = CW_Register;
10884 weight = CW_Register;
10887 weight = CW_Memory;
10893 std::pair<unsigned, const TargetRegisterClass *>
10894 PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
10895 StringRef Constraint,
10897 if (Constraint.size() == 1) {
10898 // GCC RS6000 Constraint Letters
10899 switch (Constraint[0]) {
10900 case 'b': // R1-R31
10901 if (VT == MVT::i64 && Subtarget.isPPC64())
10902 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
10903 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
10904 case 'r': // R0-R31
10905 if (VT == MVT::i64 && Subtarget.isPPC64())
10906 return std::make_pair(0U, &PPC::G8RCRegClass);
10907 return std::make_pair(0U, &PPC::GPRCRegClass);
10909 if (VT == MVT::f32 || VT == MVT::i32)
10910 return std::make_pair(0U, &PPC::F4RCRegClass);
10911 if (VT == MVT::f64 || VT == MVT::i64)
10912 return std::make_pair(0U, &PPC::F8RCRegClass);
10913 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10914 return std::make_pair(0U, &PPC::QFRCRegClass);
10915 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10916 return std::make_pair(0U, &PPC::QSRCRegClass);
10919 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10920 return std::make_pair(0U, &PPC::QFRCRegClass);
10921 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10922 return std::make_pair(0U, &PPC::QSRCRegClass);
10923 return std::make_pair(0U, &PPC::VRRCRegClass);
10925 return std::make_pair(0U, &PPC::CRRCRegClass);
10927 } else if (Constraint == "wc") { // an individual CR bit.
10928 return std::make_pair(0U, &PPC::CRBITRCRegClass);
10929 } else if (Constraint == "wa" || Constraint == "wd" ||
10930 Constraint == "wf") {
10931 return std::make_pair(0U, &PPC::VSRCRegClass);
10932 } else if (Constraint == "ws") {
10933 if (VT == MVT::f32)
10934 return std::make_pair(0U, &PPC::VSSRCRegClass);
10936 return std::make_pair(0U, &PPC::VSFRCRegClass);
10939 std::pair<unsigned, const TargetRegisterClass *> R =
10940 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
10942 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
10943 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
10944 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
10946 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
10947 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
10948 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
10949 PPC::GPRCRegClass.contains(R.first))
10950 return std::make_pair(TRI->getMatchingSuperReg(R.first,
10951 PPC::sub_32, &PPC::G8RCRegClass),
10952 &PPC::G8RCRegClass);
10954 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
10955 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
10956 R.first = PPC::CR0;
10957 R.second = &PPC::CRRCRegClass;
10963 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10964 /// vector. If it is invalid, don't add anything to Ops.
10965 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10966 std::string &Constraint,
10967 std::vector<SDValue>&Ops,
10968 SelectionDAG &DAG) const {
10971 // Only support length 1 constraints.
10972 if (Constraint.length() > 1) return;
10974 char Letter = Constraint[0];
10985 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
10986 if (!CST) return; // Must be an immediate to match.
10988 int64_t Value = CST->getSExtValue();
10989 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
10990 // numbers are printed as such.
10992 default: llvm_unreachable("Unknown constraint letter!");
10993 case 'I': // "I" is a signed 16-bit constant.
10994 if (isInt<16>(Value))
10995 Result = DAG.getTargetConstant(Value, dl, TCVT);
10997 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
10998 if (isShiftedUInt<16, 16>(Value))
10999 Result = DAG.getTargetConstant(Value, dl, TCVT);
11001 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
11002 if (isShiftedInt<16, 16>(Value))
11003 Result = DAG.getTargetConstant(Value, dl, TCVT);
11005 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
11006 if (isUInt<16>(Value))
11007 Result = DAG.getTargetConstant(Value, dl, TCVT);
11009 case 'M': // "M" is a constant that is greater than 31.
11011 Result = DAG.getTargetConstant(Value, dl, TCVT);
11013 case 'N': // "N" is a positive constant that is an exact power of two.
11014 if (Value > 0 && isPowerOf2_64(Value))
11015 Result = DAG.getTargetConstant(Value, dl, TCVT);
11017 case 'O': // "O" is the constant zero.
11019 Result = DAG.getTargetConstant(Value, dl, TCVT);
11021 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
11022 if (isInt<16>(-Value))
11023 Result = DAG.getTargetConstant(Value, dl, TCVT);
11030 if (Result.getNode()) {
11031 Ops.push_back(Result);
11035 // Handle standard constraint letters.
11036 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
11039 // isLegalAddressingMode - Return true if the addressing mode represented
11040 // by AM is legal for this target, for a load/store of the specified type.
11041 bool PPCTargetLowering::isLegalAddressingMode(const DataLayout &DL,
11042 const AddrMode &AM, Type *Ty,
11043 unsigned AS) const {
11044 // PPC does not allow r+i addressing modes for vectors!
11045 if (Ty->isVectorTy() && AM.BaseOffs != 0)
11048 // PPC allows a sign-extended 16-bit immediate field.
11049 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
11052 // No global is ever allowed as a base.
11056 // PPC only support r+r,
11057 switch (AM.Scale) {
11058 case 0: // "r+i" or just "i", depending on HasBaseReg.
11061 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
11063 // Otherwise we have r+r or r+i.
11066 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
11068 // Allow 2*r as r+r.
11071 // No other scales are supported.
11078 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
11079 SelectionDAG &DAG) const {
11080 MachineFunction &MF = DAG.getMachineFunction();
11081 MachineFrameInfo *MFI = MF.getFrameInfo();
11082 MFI->setReturnAddressIsTaken(true);
11084 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
11088 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11090 // Make sure the function does not optimize away the store of the RA to
11092 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
11093 FuncInfo->setLRStoreRequired();
11094 bool isPPC64 = Subtarget.isPPC64();
11095 auto PtrVT = getPointerTy(MF.getDataLayout());
11098 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11100 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl,
11101 isPPC64 ? MVT::i64 : MVT::i32);
11102 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11103 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
11104 MachinePointerInfo(), false, false, false, 0);
11107 // Just load the return address off the stack.
11108 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
11109 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
11110 MachinePointerInfo(), false, false, false, 0);
11113 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
11114 SelectionDAG &DAG) const {
11116 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11118 MachineFunction &MF = DAG.getMachineFunction();
11119 MachineFrameInfo *MFI = MF.getFrameInfo();
11120 MFI->setFrameAddressIsTaken(true);
11122 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
11123 bool isPPC64 = PtrVT == MVT::i64;
11125 // Naked functions never have a frame pointer, and so we use r1. For all
11126 // other functions, this decision must be delayed until during PEI.
11128 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
11129 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
11131 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
11133 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
11136 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
11137 FrameAddr, MachinePointerInfo(), false, false,
11142 // FIXME? Maybe this could be a TableGen attribute on some registers and
11143 // this table could be generated automatically from RegInfo.
11144 unsigned PPCTargetLowering::getRegisterByName(const char* RegName, EVT VT,
11145 SelectionDAG &DAG) const {
11146 bool isPPC64 = Subtarget.isPPC64();
11147 bool isDarwinABI = Subtarget.isDarwinABI();
11149 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
11150 (!isPPC64 && VT != MVT::i32))
11151 report_fatal_error("Invalid register global variable type");
11153 bool is64Bit = isPPC64 && VT == MVT::i64;
11154 unsigned Reg = StringSwitch<unsigned>(RegName)
11155 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
11156 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2)
11157 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
11158 (is64Bit ? PPC::X13 : PPC::R13))
11163 report_fatal_error("Invalid register name global variable");
11167 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
11168 // The PowerPC target isn't yet aware of offsets.
11172 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
11174 unsigned Intrinsic) const {
11176 switch (Intrinsic) {
11177 case Intrinsic::ppc_qpx_qvlfd:
11178 case Intrinsic::ppc_qpx_qvlfs:
11179 case Intrinsic::ppc_qpx_qvlfcd:
11180 case Intrinsic::ppc_qpx_qvlfcs:
11181 case Intrinsic::ppc_qpx_qvlfiwa:
11182 case Intrinsic::ppc_qpx_qvlfiwz:
11183 case Intrinsic::ppc_altivec_lvx:
11184 case Intrinsic::ppc_altivec_lvxl:
11185 case Intrinsic::ppc_altivec_lvebx:
11186 case Intrinsic::ppc_altivec_lvehx:
11187 case Intrinsic::ppc_altivec_lvewx:
11188 case Intrinsic::ppc_vsx_lxvd2x:
11189 case Intrinsic::ppc_vsx_lxvw4x: {
11191 switch (Intrinsic) {
11192 case Intrinsic::ppc_altivec_lvebx:
11195 case Intrinsic::ppc_altivec_lvehx:
11198 case Intrinsic::ppc_altivec_lvewx:
11201 case Intrinsic::ppc_vsx_lxvd2x:
11204 case Intrinsic::ppc_qpx_qvlfd:
11207 case Intrinsic::ppc_qpx_qvlfs:
11210 case Intrinsic::ppc_qpx_qvlfcd:
11213 case Intrinsic::ppc_qpx_qvlfcs:
11221 Info.opc = ISD::INTRINSIC_W_CHAIN;
11223 Info.ptrVal = I.getArgOperand(0);
11224 Info.offset = -VT.getStoreSize()+1;
11225 Info.size = 2*VT.getStoreSize()-1;
11228 Info.readMem = true;
11229 Info.writeMem = false;
11232 case Intrinsic::ppc_qpx_qvlfda:
11233 case Intrinsic::ppc_qpx_qvlfsa:
11234 case Intrinsic::ppc_qpx_qvlfcda:
11235 case Intrinsic::ppc_qpx_qvlfcsa:
11236 case Intrinsic::ppc_qpx_qvlfiwaa:
11237 case Intrinsic::ppc_qpx_qvlfiwza: {
11239 switch (Intrinsic) {
11240 case Intrinsic::ppc_qpx_qvlfda:
11243 case Intrinsic::ppc_qpx_qvlfsa:
11246 case Intrinsic::ppc_qpx_qvlfcda:
11249 case Intrinsic::ppc_qpx_qvlfcsa:
11257 Info.opc = ISD::INTRINSIC_W_CHAIN;
11259 Info.ptrVal = I.getArgOperand(0);
11261 Info.size = VT.getStoreSize();
11264 Info.readMem = true;
11265 Info.writeMem = false;
11268 case Intrinsic::ppc_qpx_qvstfd:
11269 case Intrinsic::ppc_qpx_qvstfs:
11270 case Intrinsic::ppc_qpx_qvstfcd:
11271 case Intrinsic::ppc_qpx_qvstfcs:
11272 case Intrinsic::ppc_qpx_qvstfiw:
11273 case Intrinsic::ppc_altivec_stvx:
11274 case Intrinsic::ppc_altivec_stvxl:
11275 case Intrinsic::ppc_altivec_stvebx:
11276 case Intrinsic::ppc_altivec_stvehx:
11277 case Intrinsic::ppc_altivec_stvewx:
11278 case Intrinsic::ppc_vsx_stxvd2x:
11279 case Intrinsic::ppc_vsx_stxvw4x: {
11281 switch (Intrinsic) {
11282 case Intrinsic::ppc_altivec_stvebx:
11285 case Intrinsic::ppc_altivec_stvehx:
11288 case Intrinsic::ppc_altivec_stvewx:
11291 case Intrinsic::ppc_vsx_stxvd2x:
11294 case Intrinsic::ppc_qpx_qvstfd:
11297 case Intrinsic::ppc_qpx_qvstfs:
11300 case Intrinsic::ppc_qpx_qvstfcd:
11303 case Intrinsic::ppc_qpx_qvstfcs:
11311 Info.opc = ISD::INTRINSIC_VOID;
11313 Info.ptrVal = I.getArgOperand(1);
11314 Info.offset = -VT.getStoreSize()+1;
11315 Info.size = 2*VT.getStoreSize()-1;
11318 Info.readMem = false;
11319 Info.writeMem = true;
11322 case Intrinsic::ppc_qpx_qvstfda:
11323 case Intrinsic::ppc_qpx_qvstfsa:
11324 case Intrinsic::ppc_qpx_qvstfcda:
11325 case Intrinsic::ppc_qpx_qvstfcsa:
11326 case Intrinsic::ppc_qpx_qvstfiwa: {
11328 switch (Intrinsic) {
11329 case Intrinsic::ppc_qpx_qvstfda:
11332 case Intrinsic::ppc_qpx_qvstfsa:
11335 case Intrinsic::ppc_qpx_qvstfcda:
11338 case Intrinsic::ppc_qpx_qvstfcsa:
11346 Info.opc = ISD::INTRINSIC_VOID;
11348 Info.ptrVal = I.getArgOperand(1);
11350 Info.size = VT.getStoreSize();
11353 Info.readMem = false;
11354 Info.writeMem = true;
11364 /// getOptimalMemOpType - Returns the target specific optimal type for load
11365 /// and store operations as a result of memset, memcpy, and memmove
11366 /// lowering. If DstAlign is zero that means it's safe to destination
11367 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
11368 /// means there isn't a need to check it against alignment requirement,
11369 /// probably because the source does not need to be loaded. If 'IsMemset' is
11370 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
11371 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
11372 /// source is constant so it does not need to be loaded.
11373 /// It returns EVT::Other if the type should be determined using generic
11374 /// target-independent logic.
11375 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
11376 unsigned DstAlign, unsigned SrcAlign,
11377 bool IsMemset, bool ZeroMemset,
11379 MachineFunction &MF) const {
11380 if (getTargetMachine().getOptLevel() != CodeGenOpt::None) {
11381 const Function *F = MF.getFunction();
11382 // When expanding a memset, require at least two QPX instructions to cover
11383 // the cost of loading the value to be stored from the constant pool.
11384 if (Subtarget.hasQPX() && Size >= 32 && (!IsMemset || Size >= 64) &&
11385 (!SrcAlign || SrcAlign >= 32) && (!DstAlign || DstAlign >= 32) &&
11386 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
11390 // We should use Altivec/VSX loads and stores when available. For unaligned
11391 // addresses, unaligned VSX loads are only fast starting with the P8.
11392 if (Subtarget.hasAltivec() && Size >= 16 &&
11393 (((!SrcAlign || SrcAlign >= 16) && (!DstAlign || DstAlign >= 16)) ||
11394 ((IsMemset && Subtarget.hasVSX()) || Subtarget.hasP8Vector())))
11398 if (Subtarget.isPPC64()) {
11405 /// \brief Returns true if it is beneficial to convert a load of a constant
11406 /// to just the constant itself.
11407 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11409 assert(Ty->isIntegerTy());
11411 unsigned BitSize = Ty->getPrimitiveSizeInBits();
11412 if (BitSize == 0 || BitSize > 64)
11417 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11418 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11420 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11421 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11422 return NumBits1 == 64 && NumBits2 == 32;
11425 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11426 if (!VT1.isInteger() || !VT2.isInteger())
11428 unsigned NumBits1 = VT1.getSizeInBits();
11429 unsigned NumBits2 = VT2.getSizeInBits();
11430 return NumBits1 == 64 && NumBits2 == 32;
11433 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
11434 // Generally speaking, zexts are not free, but they are free when they can be
11435 // folded with other operations.
11436 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
11437 EVT MemVT = LD->getMemoryVT();
11438 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
11439 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
11440 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
11441 LD->getExtensionType() == ISD::ZEXTLOAD))
11445 // FIXME: Add other cases...
11446 // - 32-bit shifts with a zext to i64
11447 // - zext after ctlz, bswap, etc.
11448 // - zext after and by a constant mask
11450 return TargetLowering::isZExtFree(Val, VT2);
11453 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
11454 assert(VT.isFloatingPoint());
11458 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
11459 return isInt<16>(Imm) || isUInt<16>(Imm);
11462 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
11463 return isInt<16>(Imm) || isUInt<16>(Imm);
11466 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
11469 bool *Fast) const {
11470 if (DisablePPCUnaligned)
11473 // PowerPC supports unaligned memory access for simple non-vector types.
11474 // Although accessing unaligned addresses is not as efficient as accessing
11475 // aligned addresses, it is generally more efficient than manual expansion,
11476 // and generally only traps for software emulation when crossing page
11479 if (!VT.isSimple())
11482 if (VT.getSimpleVT().isVector()) {
11483 if (Subtarget.hasVSX()) {
11484 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
11485 VT != MVT::v4f32 && VT != MVT::v4i32)
11492 if (VT == MVT::ppcf128)
11501 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
11502 VT = VT.getScalarType();
11504 if (!VT.isSimple())
11507 switch (VT.getSimpleVT().SimpleTy) {
11519 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
11520 // LR is a callee-save register, but we must treat it as clobbered by any call
11521 // site. Hence we include LR in the scratch registers, which are in turn added
11522 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
11523 // to CTR, which is used by any indirect call.
11524 static const MCPhysReg ScratchRegs[] = {
11525 PPC::X12, PPC::LR8, PPC::CTR8, 0
11528 return ScratchRegs;
11532 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
11533 EVT VT , unsigned DefinedValues) const {
11534 if (VT == MVT::v2i64)
11535 return Subtarget.hasDirectMove(); // Don't need stack ops with direct moves
11537 if (Subtarget.hasQPX()) {
11538 if (VT == MVT::v4f32 || VT == MVT::v4f64 || VT == MVT::v4i1)
11542 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
11545 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
11546 if (DisableILPPref || Subtarget.enableMachineScheduler())
11547 return TargetLowering::getSchedulingPreference(N);
11552 // Create a fast isel object.
11554 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
11555 const TargetLibraryInfo *LibInfo) const {
11556 return PPC::createFastISel(FuncInfo, LibInfo);