1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/Support/CommandLine.h"
36 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
37 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
40 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
41 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
45 // Use _setjmp/_longjmp instead of setjmp/longjmp.
46 setUseUnderscoreSetJmp(true);
47 setUseUnderscoreLongJmp(true);
49 // Set up the register classes.
50 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
51 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
52 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
54 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
55 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
56 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
58 // PowerPC does not have truncstore for i1.
59 setStoreXAction(MVT::i1, Promote);
61 // PowerPC has pre-inc load and store's.
62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
65 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
67 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
70 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
73 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
74 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
76 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg)
77 setConvertAction(MVT::ppcf128, MVT::f64, Expand);
78 setConvertAction(MVT::ppcf128, MVT::f32, Expand);
80 // PowerPC has no intrinsics for these particular operations
81 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
82 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
83 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
85 // PowerPC has no SREM/UREM instructions
86 setOperationAction(ISD::SREM, MVT::i32, Expand);
87 setOperationAction(ISD::UREM, MVT::i32, Expand);
88 setOperationAction(ISD::SREM, MVT::i64, Expand);
89 setOperationAction(ISD::UREM, MVT::i64, Expand);
91 // We don't support sin/cos/sqrt/fmod
92 setOperationAction(ISD::FSIN , MVT::f64, Expand);
93 setOperationAction(ISD::FCOS , MVT::f64, Expand);
94 setOperationAction(ISD::FREM , MVT::f64, Expand);
95 setOperationAction(ISD::FSIN , MVT::f32, Expand);
96 setOperationAction(ISD::FCOS , MVT::f32, Expand);
97 setOperationAction(ISD::FREM , MVT::f32, Expand);
99 // If we're enabling GP optimizations, use hardware square root
100 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
101 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
102 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
105 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
106 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
108 // PowerPC does not have BSWAP, CTPOP or CTTZ
109 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
110 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
111 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
112 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
113 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
114 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
116 // PowerPC does not have ROTR
117 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
119 // PowerPC does not have Select
120 setOperationAction(ISD::SELECT, MVT::i32, Expand);
121 setOperationAction(ISD::SELECT, MVT::i64, Expand);
122 setOperationAction(ISD::SELECT, MVT::f32, Expand);
123 setOperationAction(ISD::SELECT, MVT::f64, Expand);
125 // PowerPC wants to turn select_cc of FP into fsel when possible.
126 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
127 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
129 // PowerPC wants to optimize integer setcc a bit
130 setOperationAction(ISD::SETCC, MVT::i32, Custom);
132 // PowerPC does not have BRCOND which requires SetCC
133 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
135 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
137 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
138 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
140 // PowerPC does not have [U|S]INT_TO_FP
141 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
142 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
144 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
145 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
146 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
147 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
149 // We cannot sextinreg(i1). Expand to shifts.
150 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
152 // Support label based line numbers.
153 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
154 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
155 if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
156 setOperationAction(ISD::LABEL, MVT::Other, Expand);
158 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
159 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
160 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
161 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
164 // We want to legalize GlobalAddress and ConstantPool nodes into the
165 // appropriate instructions to materialize the address.
166 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
167 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
168 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
169 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
170 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
171 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
172 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
173 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
175 // RET must be custom lowered, to meet ABI requirements
176 setOperationAction(ISD::RET , MVT::Other, Custom);
178 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
179 setOperationAction(ISD::VASTART , MVT::Other, Custom);
181 // VAARG is custom lowered with ELF 32 ABI
182 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
183 setOperationAction(ISD::VAARG, MVT::Other, Custom);
185 setOperationAction(ISD::VAARG, MVT::Other, Expand);
187 // Use the default implementation.
188 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
189 setOperationAction(ISD::VAEND , MVT::Other, Expand);
190 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
191 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
192 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
193 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
195 // We want to custom lower some of our intrinsics.
196 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
198 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
199 // They also have instructions for converting between i64 and fp.
200 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
201 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
202 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
203 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
204 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
206 // FIXME: disable this lowered code. This generates 64-bit register values,
207 // and we don't model the fact that the top part is clobbered by calls. We
208 // need to flag these together so that the value isn't live across a call.
209 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
211 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
212 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
214 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
215 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
218 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
219 // 64 bit PowerPC implementations can support i64 types directly
220 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
221 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
222 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
224 // 32 bit PowerPC wants to expand i64 shifts itself.
225 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
226 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
227 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
230 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
231 // First set operation action for all vector types to expand. Then we
232 // will selectively turn on ones that can be effectively codegen'd.
233 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
234 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
235 // add/sub are legal for all supported vector VT's.
236 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
237 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
239 // We promote all shuffles to v16i8.
240 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
241 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
243 // We promote all non-typed operations to v4i32.
244 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
245 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
246 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
247 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
248 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
249 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
250 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
251 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
252 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
253 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
254 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
255 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
257 // No other operations are legal.
258 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
259 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
260 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
261 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
262 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
263 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
264 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
265 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
266 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
267 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
269 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
272 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
273 // with merges, splats, etc.
274 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
276 setOperationAction(ISD::AND , MVT::v4i32, Legal);
277 setOperationAction(ISD::OR , MVT::v4i32, Legal);
278 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
279 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
280 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
281 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
283 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
284 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
285 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
286 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
288 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
289 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
290 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
291 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
293 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
294 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
296 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
297 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
298 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
299 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
302 setSetCCResultType(MVT::i32);
303 setShiftAmountType(MVT::i32);
304 setSetCCResultContents(ZeroOrOneSetCCResult);
306 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
307 setStackPointerRegisterToSaveRestore(PPC::X1);
308 setExceptionPointerRegister(PPC::X3);
309 setExceptionSelectorRegister(PPC::X4);
311 setStackPointerRegisterToSaveRestore(PPC::R1);
312 setExceptionPointerRegister(PPC::R3);
313 setExceptionSelectorRegister(PPC::R4);
316 // We have target-specific dag combine patterns for the following nodes:
317 setTargetDAGCombine(ISD::SINT_TO_FP);
318 setTargetDAGCombine(ISD::STORE);
319 setTargetDAGCombine(ISD::BR_CC);
320 setTargetDAGCombine(ISD::BSWAP);
322 computeRegisterProperties();
325 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
328 case PPCISD::FSEL: return "PPCISD::FSEL";
329 case PPCISD::FCFID: return "PPCISD::FCFID";
330 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
331 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
332 case PPCISD::STFIWX: return "PPCISD::STFIWX";
333 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
334 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
335 case PPCISD::VPERM: return "PPCISD::VPERM";
336 case PPCISD::Hi: return "PPCISD::Hi";
337 case PPCISD::Lo: return "PPCISD::Lo";
338 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
339 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
340 case PPCISD::SRL: return "PPCISD::SRL";
341 case PPCISD::SRA: return "PPCISD::SRA";
342 case PPCISD::SHL: return "PPCISD::SHL";
343 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
344 case PPCISD::STD_32: return "PPCISD::STD_32";
345 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
346 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
347 case PPCISD::MTCTR: return "PPCISD::MTCTR";
348 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
349 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
350 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
351 case PPCISD::MFCR: return "PPCISD::MFCR";
352 case PPCISD::VCMP: return "PPCISD::VCMP";
353 case PPCISD::VCMPo: return "PPCISD::VCMPo";
354 case PPCISD::LBRX: return "PPCISD::LBRX";
355 case PPCISD::STBRX: return "PPCISD::STBRX";
356 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
360 //===----------------------------------------------------------------------===//
361 // Node matching predicates, for use by the tblgen matching code.
362 //===----------------------------------------------------------------------===//
364 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
365 static bool isFloatingPointZero(SDOperand Op) {
366 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
367 return CFP->getValueAPF().isZero();
368 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
369 // Maybe this has already been legalized into the constant pool?
370 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
371 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
372 return CFP->getValueAPF().isZero();
377 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
378 /// true if Op is undef or if it matches the specified value.
379 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
380 return Op.getOpcode() == ISD::UNDEF ||
381 cast<ConstantSDNode>(Op)->getValue() == Val;
384 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
385 /// VPKUHUM instruction.
386 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
388 for (unsigned i = 0; i != 16; ++i)
389 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
392 for (unsigned i = 0; i != 8; ++i)
393 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
394 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
400 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
401 /// VPKUWUM instruction.
402 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
404 for (unsigned i = 0; i != 16; i += 2)
405 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
406 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
409 for (unsigned i = 0; i != 8; i += 2)
410 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
411 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
412 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
413 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
419 /// isVMerge - Common function, used to match vmrg* shuffles.
421 static bool isVMerge(SDNode *N, unsigned UnitSize,
422 unsigned LHSStart, unsigned RHSStart) {
423 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
424 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
425 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
426 "Unsupported merge size!");
428 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
429 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
430 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
431 LHSStart+j+i*UnitSize) ||
432 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
433 RHSStart+j+i*UnitSize))
439 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
440 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
441 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
443 return isVMerge(N, UnitSize, 8, 24);
444 return isVMerge(N, UnitSize, 8, 8);
447 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
448 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
449 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
451 return isVMerge(N, UnitSize, 0, 16);
452 return isVMerge(N, UnitSize, 0, 0);
456 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
457 /// amount, otherwise return -1.
458 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
459 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
460 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
461 // Find the first non-undef value in the shuffle mask.
463 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
466 if (i == 16) return -1; // all undef.
468 // Otherwise, check to see if the rest of the elements are consequtively
469 // numbered from this value.
470 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
471 if (ShiftAmt < i) return -1;
475 // Check the rest of the elements to see if they are consequtive.
476 for (++i; i != 16; ++i)
477 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
480 // Check the rest of the elements to see if they are consequtive.
481 for (++i; i != 16; ++i)
482 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
489 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
490 /// specifies a splat of a single element that is suitable for input to
491 /// VSPLTB/VSPLTH/VSPLTW.
492 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
493 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
494 N->getNumOperands() == 16 &&
495 (EltSize == 1 || EltSize == 2 || EltSize == 4));
497 // This is a splat operation if each element of the permute is the same, and
498 // if the value doesn't reference the second vector.
499 unsigned ElementBase = 0;
500 SDOperand Elt = N->getOperand(0);
501 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
502 ElementBase = EltV->getValue();
504 return false; // FIXME: Handle UNDEF elements too!
506 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
509 // Check that they are consequtive.
510 for (unsigned i = 1; i != EltSize; ++i) {
511 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
512 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
516 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
517 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
518 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
519 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
520 "Invalid VECTOR_SHUFFLE mask!");
521 for (unsigned j = 0; j != EltSize; ++j)
522 if (N->getOperand(i+j) != N->getOperand(j))
529 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
531 bool PPC::isAllNegativeZeroVector(SDNode *N) {
532 assert(N->getOpcode() == ISD::BUILD_VECTOR);
533 if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
534 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
535 return CFP->getValueAPF().isNegZero();
539 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
540 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
541 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
542 assert(isSplatShuffleMask(N, EltSize));
543 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
546 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
547 /// by using a vspltis[bhw] instruction of the specified element size, return
548 /// the constant being splatted. The ByteSize field indicates the number of
549 /// bytes of each element [124] -> [bhw].
550 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
551 SDOperand OpVal(0, 0);
553 // If ByteSize of the splat is bigger than the element size of the
554 // build_vector, then we have a case where we are checking for a splat where
555 // multiple elements of the buildvector are folded together into a single
556 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
557 unsigned EltSize = 16/N->getNumOperands();
558 if (EltSize < ByteSize) {
559 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
560 SDOperand UniquedVals[4];
561 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
563 // See if all of the elements in the buildvector agree across.
564 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
565 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
566 // If the element isn't a constant, bail fully out.
567 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
570 if (UniquedVals[i&(Multiple-1)].Val == 0)
571 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
572 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
573 return SDOperand(); // no match.
576 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
577 // either constant or undef values that are identical for each chunk. See
578 // if these chunks can form into a larger vspltis*.
580 // Check to see if all of the leading entries are either 0 or -1. If
581 // neither, then this won't fit into the immediate field.
582 bool LeadingZero = true;
583 bool LeadingOnes = true;
584 for (unsigned i = 0; i != Multiple-1; ++i) {
585 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
587 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
588 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
590 // Finally, check the least significant entry.
592 if (UniquedVals[Multiple-1].Val == 0)
593 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
594 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
596 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
599 if (UniquedVals[Multiple-1].Val == 0)
600 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
601 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
602 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
603 return DAG.getTargetConstant(Val, MVT::i32);
609 // Check to see if this buildvec has a single non-undef value in its elements.
610 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
611 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
613 OpVal = N->getOperand(i);
614 else if (OpVal != N->getOperand(i))
618 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
620 unsigned ValSizeInBytes = 0;
622 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
623 Value = CN->getValue();
624 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
625 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
626 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
627 Value = FloatToBits(CN->getValueAPF().convertToFloat());
631 // If the splat value is larger than the element value, then we can never do
632 // this splat. The only case that we could fit the replicated bits into our
633 // immediate field for would be zero, and we prefer to use vxor for it.
634 if (ValSizeInBytes < ByteSize) return SDOperand();
636 // If the element value is larger than the splat value, cut it in half and
637 // check to see if the two halves are equal. Continue doing this until we
638 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
639 while (ValSizeInBytes > ByteSize) {
640 ValSizeInBytes >>= 1;
642 // If the top half equals the bottom half, we're still ok.
643 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
644 (Value & ((1 << (8*ValSizeInBytes))-1)))
648 // Properly sign extend the value.
649 int ShAmt = (4-ByteSize)*8;
650 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
652 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
653 if (MaskVal == 0) return SDOperand();
655 // Finally, if this value fits in a 5 bit sext field, return it
656 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
657 return DAG.getTargetConstant(MaskVal, MVT::i32);
661 //===----------------------------------------------------------------------===//
662 // Addressing Mode Selection
663 //===----------------------------------------------------------------------===//
665 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
666 /// or 64-bit immediate, and if the value can be accurately represented as a
667 /// sign extension from a 16-bit value. If so, this returns true and the
669 static bool isIntS16Immediate(SDNode *N, short &Imm) {
670 if (N->getOpcode() != ISD::Constant)
673 Imm = (short)cast<ConstantSDNode>(N)->getValue();
674 if (N->getValueType(0) == MVT::i32)
675 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
677 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
679 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
680 return isIntS16Immediate(Op.Val, Imm);
684 /// SelectAddressRegReg - Given the specified addressed, check to see if it
685 /// can be represented as an indexed [r+r] operation. Returns false if it
686 /// can be more efficiently represented with [r+imm].
687 bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
691 if (N.getOpcode() == ISD::ADD) {
692 if (isIntS16Immediate(N.getOperand(1), imm))
694 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
697 Base = N.getOperand(0);
698 Index = N.getOperand(1);
700 } else if (N.getOpcode() == ISD::OR) {
701 if (isIntS16Immediate(N.getOperand(1), imm))
702 return false; // r+i can fold it if we can.
704 // If this is an or of disjoint bitfields, we can codegen this as an add
705 // (for better address arithmetic) if the LHS and RHS of the OR are provably
707 uint64_t LHSKnownZero, LHSKnownOne;
708 uint64_t RHSKnownZero, RHSKnownOne;
709 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
712 DAG.ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne);
713 // If all of the bits are known zero on the LHS or RHS, the add won't
715 if ((LHSKnownZero | RHSKnownZero) == ~0U) {
716 Base = N.getOperand(0);
717 Index = N.getOperand(1);
726 /// Returns true if the address N can be represented by a base register plus
727 /// a signed 16-bit displacement [r+imm], and if it is not better
728 /// represented as reg+reg.
729 bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
730 SDOperand &Base, SelectionDAG &DAG){
731 // If this can be more profitably realized as r+r, fail.
732 if (SelectAddressRegReg(N, Disp, Base, DAG))
735 if (N.getOpcode() == ISD::ADD) {
737 if (isIntS16Immediate(N.getOperand(1), imm)) {
738 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
739 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
740 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
742 Base = N.getOperand(0);
744 return true; // [r+i]
745 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
746 // Match LOAD (ADD (X, Lo(G))).
747 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
748 && "Cannot handle constant offsets yet!");
749 Disp = N.getOperand(1).getOperand(0); // The global address.
750 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
751 Disp.getOpcode() == ISD::TargetConstantPool ||
752 Disp.getOpcode() == ISD::TargetJumpTable);
753 Base = N.getOperand(0);
754 return true; // [&g+r]
756 } else if (N.getOpcode() == ISD::OR) {
758 if (isIntS16Immediate(N.getOperand(1), imm)) {
759 // If this is an or of disjoint bitfields, we can codegen this as an add
760 // (for better address arithmetic) if the LHS and RHS of the OR are
761 // provably disjoint.
762 uint64_t LHSKnownZero, LHSKnownOne;
763 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
764 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
765 // If all of the bits are known zero on the LHS or RHS, the add won't
767 Base = N.getOperand(0);
768 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
772 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
773 // Loading from a constant address.
775 // If this address fits entirely in a 16-bit sext immediate field, codegen
778 if (isIntS16Immediate(CN, Imm)) {
779 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
780 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
784 // Handle 32-bit sext immediates with LIS + addr mode.
785 if (CN->getValueType(0) == MVT::i32 ||
786 (int64_t)CN->getValue() == (int)CN->getValue()) {
787 int Addr = (int)CN->getValue();
789 // Otherwise, break this down into an LIS + disp.
790 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
792 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
793 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
794 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
799 Disp = DAG.getTargetConstant(0, getPointerTy());
800 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
801 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
804 return true; // [r+0]
807 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
808 /// represented as an indexed [r+r] operation.
809 bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
812 // Check to see if we can easily represent this as an [r+r] address. This
813 // will fail if it thinks that the address is more profitably represented as
814 // reg+imm, e.g. where imm = 0.
815 if (SelectAddressRegReg(N, Base, Index, DAG))
818 // If the operand is an addition, always emit this as [r+r], since this is
819 // better (for code size, and execution, as the memop does the add for free)
820 // than emitting an explicit add.
821 if (N.getOpcode() == ISD::ADD) {
822 Base = N.getOperand(0);
823 Index = N.getOperand(1);
827 // Otherwise, do it the hard way, using R0 as the base register.
828 Base = DAG.getRegister(PPC::R0, N.getValueType());
833 /// SelectAddressRegImmShift - Returns true if the address N can be
834 /// represented by a base register plus a signed 14-bit displacement
835 /// [r+imm*4]. Suitable for use by STD and friends.
836 bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
839 // If this can be more profitably realized as r+r, fail.
840 if (SelectAddressRegReg(N, Disp, Base, DAG))
843 if (N.getOpcode() == ISD::ADD) {
845 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
846 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
847 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
848 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
850 Base = N.getOperand(0);
852 return true; // [r+i]
853 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
854 // Match LOAD (ADD (X, Lo(G))).
855 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
856 && "Cannot handle constant offsets yet!");
857 Disp = N.getOperand(1).getOperand(0); // The global address.
858 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
859 Disp.getOpcode() == ISD::TargetConstantPool ||
860 Disp.getOpcode() == ISD::TargetJumpTable);
861 Base = N.getOperand(0);
862 return true; // [&g+r]
864 } else if (N.getOpcode() == ISD::OR) {
866 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
867 // If this is an or of disjoint bitfields, we can codegen this as an add
868 // (for better address arithmetic) if the LHS and RHS of the OR are
869 // provably disjoint.
870 uint64_t LHSKnownZero, LHSKnownOne;
871 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
872 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
873 // If all of the bits are known zero on the LHS or RHS, the add won't
875 Base = N.getOperand(0);
876 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
880 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
881 // Loading from a constant address. Verify low two bits are clear.
882 if ((CN->getValue() & 3) == 0) {
883 // If this address fits entirely in a 14-bit sext immediate field, codegen
886 if (isIntS16Immediate(CN, Imm)) {
887 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
888 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
892 // Fold the low-part of 32-bit absolute addresses into addr mode.
893 if (CN->getValueType(0) == MVT::i32 ||
894 (int64_t)CN->getValue() == (int)CN->getValue()) {
895 int Addr = (int)CN->getValue();
897 // Otherwise, break this down into an LIS + disp.
898 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
900 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
901 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
902 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
908 Disp = DAG.getTargetConstant(0, getPointerTy());
909 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
910 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
913 return true; // [r+0]
917 /// getPreIndexedAddressParts - returns true by value, base pointer and
918 /// offset pointer and addressing mode by reference if the node's address
919 /// can be legally represented as pre-indexed load / store address.
920 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
922 ISD::MemIndexedMode &AM,
924 // Disabled by default for now.
925 if (!EnablePPCPreinc) return false;
929 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
930 Ptr = LD->getBasePtr();
931 VT = LD->getLoadedVT();
933 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
935 Ptr = ST->getBasePtr();
936 VT = ST->getStoredVT();
940 // PowerPC doesn't have preinc load/store instructions for vectors.
941 if (MVT::isVector(VT))
944 // TODO: Check reg+reg first.
946 // LDU/STU use reg+imm*4, others use reg+imm.
947 if (VT != MVT::i64) {
949 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
953 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
957 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
958 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
959 // sext i32 to i64 when addr mode is r+i.
960 if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 &&
961 LD->getExtensionType() == ISD::SEXTLOAD &&
962 isa<ConstantSDNode>(Offset))
970 //===----------------------------------------------------------------------===//
971 // LowerOperation implementation
972 //===----------------------------------------------------------------------===//
974 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
975 MVT::ValueType PtrVT = Op.getValueType();
976 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
977 Constant *C = CP->getConstVal();
978 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
979 SDOperand Zero = DAG.getConstant(0, PtrVT);
981 const TargetMachine &TM = DAG.getTarget();
983 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
984 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
986 // If this is a non-darwin platform, we don't support non-static relo models
988 if (TM.getRelocationModel() == Reloc::Static ||
989 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
990 // Generate non-pic code that has direct accesses to the constant pool.
991 // The address of the global is just (hi(&g)+lo(&g)).
992 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
995 if (TM.getRelocationModel() == Reloc::PIC_) {
996 // With PIC, the first instruction is actually "GR+hi(&G)".
997 Hi = DAG.getNode(ISD::ADD, PtrVT,
998 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1001 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1005 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
1006 MVT::ValueType PtrVT = Op.getValueType();
1007 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1008 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1009 SDOperand Zero = DAG.getConstant(0, PtrVT);
1011 const TargetMachine &TM = DAG.getTarget();
1013 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
1014 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
1016 // If this is a non-darwin platform, we don't support non-static relo models
1018 if (TM.getRelocationModel() == Reloc::Static ||
1019 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1020 // Generate non-pic code that has direct accesses to the constant pool.
1021 // The address of the global is just (hi(&g)+lo(&g)).
1022 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1025 if (TM.getRelocationModel() == Reloc::PIC_) {
1026 // With PIC, the first instruction is actually "GR+hi(&G)".
1027 Hi = DAG.getNode(ISD::ADD, PtrVT,
1028 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1031 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1035 static SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
1036 assert(0 && "TLS not implemented for PPC.");
1039 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
1040 MVT::ValueType PtrVT = Op.getValueType();
1041 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1042 GlobalValue *GV = GSDN->getGlobal();
1043 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1044 SDOperand Zero = DAG.getConstant(0, PtrVT);
1046 const TargetMachine &TM = DAG.getTarget();
1048 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
1049 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
1051 // If this is a non-darwin platform, we don't support non-static relo models
1053 if (TM.getRelocationModel() == Reloc::Static ||
1054 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1055 // Generate non-pic code that has direct accesses to globals.
1056 // The address of the global is just (hi(&g)+lo(&g)).
1057 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1060 if (TM.getRelocationModel() == Reloc::PIC_) {
1061 // With PIC, the first instruction is actually "GR+hi(&G)".
1062 Hi = DAG.getNode(ISD::ADD, PtrVT,
1063 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1066 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1068 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1071 // If the global is weak or external, we have to go through the lazy
1073 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
1076 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
1077 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1079 // If we're comparing for equality to zero, expose the fact that this is
1080 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1081 // fold the new nodes.
1082 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1083 if (C->isNullValue() && CC == ISD::SETEQ) {
1084 MVT::ValueType VT = Op.getOperand(0).getValueType();
1085 SDOperand Zext = Op.getOperand(0);
1086 if (VT < MVT::i32) {
1088 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1090 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
1091 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1092 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
1093 DAG.getConstant(Log2b, MVT::i32));
1094 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1096 // Leave comparisons against 0 and -1 alone for now, since they're usually
1097 // optimized. FIXME: revisit this when we can custom lower all setcc
1099 if (C->isAllOnesValue() || C->isNullValue())
1103 // If we have an integer seteq/setne, turn it into a compare against zero
1104 // by xor'ing the rhs with the lhs, which is faster than setting a
1105 // condition register, reading it back out, and masking the correct bit. The
1106 // normal approach here uses sub to do this instead of xor. Using xor exposes
1107 // the result to other bit-twiddling opportunities.
1108 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
1109 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1110 MVT::ValueType VT = Op.getValueType();
1111 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
1113 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1118 static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG,
1119 int VarArgsFrameIndex,
1120 int VarArgsStackOffset,
1121 unsigned VarArgsNumGPR,
1122 unsigned VarArgsNumFPR,
1123 const PPCSubtarget &Subtarget) {
1125 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1128 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
1129 int VarArgsFrameIndex,
1130 int VarArgsStackOffset,
1131 unsigned VarArgsNumGPR,
1132 unsigned VarArgsNumFPR,
1133 const PPCSubtarget &Subtarget) {
1135 if (Subtarget.isMachoABI()) {
1136 // vastart just stores the address of the VarArgsFrameIndex slot into the
1137 // memory location argument.
1138 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1139 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1140 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
1141 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
1145 // For ELF 32 ABI we follow the layout of the va_list struct.
1146 // We suppose the given va_list is already allocated.
1149 // char gpr; /* index into the array of 8 GPRs
1150 // * stored in the register save area
1151 // * gpr=0 corresponds to r3,
1152 // * gpr=1 to r4, etc.
1154 // char fpr; /* index into the array of 8 FPRs
1155 // * stored in the register save area
1156 // * fpr=0 corresponds to f1,
1157 // * fpr=1 to f2, etc.
1159 // char *overflow_arg_area;
1160 // /* location on stack that holds
1161 // * the next overflow argument
1163 // char *reg_save_area;
1164 // /* where r3:r10 and f1:f8 (if saved)
1170 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1171 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1174 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1176 SDOperand StackOffset = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1177 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1179 SDOperand ConstFrameOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8,
1181 SDOperand ConstStackOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8 - 1,
1183 SDOperand ConstFPROffset = DAG.getConstant(1, PtrVT);
1185 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
1187 // Store first byte : number of int regs
1188 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
1189 Op.getOperand(1), SV->getValue(),
1191 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
1194 // Store second byte : number of float regs
1195 SDOperand secondStore = DAG.getStore(firstStore, ArgFPR, nextPtr,
1196 SV->getValue(), SV->getOffset());
1197 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
1199 // Store second word : arguments given on stack
1200 SDOperand thirdStore = DAG.getStore(secondStore, StackOffset, nextPtr,
1201 SV->getValue(), SV->getOffset());
1202 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
1204 // Store third word : arguments given in registers
1205 return DAG.getStore(thirdStore, FR, nextPtr, SV->getValue(),
1210 #include "PPCGenCallingConv.inc"
1212 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1213 /// depending on which subtarget is selected.
1214 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1215 if (Subtarget.isMachoABI()) {
1216 static const unsigned FPR[] = {
1217 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1218 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1224 static const unsigned FPR[] = {
1225 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1231 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
1232 int &VarArgsFrameIndex,
1233 int &VarArgsStackOffset,
1234 unsigned &VarArgsNumGPR,
1235 unsigned &VarArgsNumFPR,
1236 const PPCSubtarget &Subtarget) {
1237 // TODO: add description of PPC stack frame format, or at least some docs.
1239 MachineFunction &MF = DAG.getMachineFunction();
1240 MachineFrameInfo *MFI = MF.getFrameInfo();
1241 SSARegMap *RegMap = MF.getSSARegMap();
1242 SmallVector<SDOperand, 8> ArgValues;
1243 SDOperand Root = Op.getOperand(0);
1245 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1246 bool isPPC64 = PtrVT == MVT::i64;
1247 bool isMachoABI = Subtarget.isMachoABI();
1248 bool isELF32_ABI = Subtarget.isELF32_ABI();
1249 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1251 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1253 static const unsigned GPR_32[] = { // 32-bit registers.
1254 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1255 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1257 static const unsigned GPR_64[] = { // 64-bit registers.
1258 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1259 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1262 static const unsigned *FPR = GetFPR(Subtarget);
1264 static const unsigned VR[] = {
1265 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1266 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1269 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1270 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
1271 const unsigned Num_VR_Regs = array_lengthof( VR);
1273 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1275 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1277 // Add DAG nodes to load the arguments or copy them out of registers. On
1278 // entry to a function on PPC, the arguments start after the linkage area,
1279 // although the first ones are often in registers.
1281 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
1282 // represented with two words (long long or double) must be copied to an
1283 // even GPR_idx value or to an even ArgOffset value.
1285 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
1287 bool needsLoad = false;
1288 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
1289 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
1290 unsigned ArgSize = ObjSize;
1291 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue();
1292 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1293 // See if next argument requires stack alignment in ELF
1294 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) &&
1295 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) &&
1296 (!(Flags & AlignFlag)));
1298 unsigned CurArgOffset = ArgOffset;
1300 default: assert(0 && "Unhandled argument type!");
1302 // Double word align in ELF
1303 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1304 if (GPR_idx != Num_GPR_Regs) {
1305 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1306 MF.addLiveIn(GPR[GPR_idx], VReg);
1307 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1311 ArgSize = PtrByteSize;
1313 // Stack align in ELF
1314 if (needsLoad && Expand && isELF32_ABI)
1315 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1316 // All int arguments reserve stack space in Macho ABI.
1317 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1320 case MVT::i64: // PPC64
1321 if (GPR_idx != Num_GPR_Regs) {
1322 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
1323 MF.addLiveIn(GPR[GPR_idx], VReg);
1324 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1329 // All int arguments reserve stack space in Macho ABI.
1330 if (isMachoABI || needsLoad) ArgOffset += 8;
1335 // Every 4 bytes of argument space consumes one of the GPRs available for
1336 // argument passing.
1337 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
1339 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1342 if (FPR_idx != Num_FPR_Regs) {
1344 if (ObjectVT == MVT::f32)
1345 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
1347 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
1348 MF.addLiveIn(FPR[FPR_idx], VReg);
1349 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1355 // Stack align in ELF
1356 if (needsLoad && Expand && isELF32_ABI)
1357 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1358 // All FP arguments reserve stack space in Macho ABI.
1359 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
1365 // Note that vector arguments in registers don't reserve stack space.
1366 if (VR_idx != Num_VR_Regs) {
1367 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass);
1368 MF.addLiveIn(VR[VR_idx], VReg);
1369 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1372 // This should be simple, but requires getting 16-byte aligned stack
1374 assert(0 && "Loading VR argument not implemented yet!");
1380 // We need to load the argument to a virtual register if we determined above
1381 // that we ran out of physical registers of the appropriate type
1383 // If the argument is actually used, emit a load from the right stack
1385 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
1386 int FI = MFI->CreateFixedObject(ObjSize,
1387 CurArgOffset + (ArgSize - ObjSize));
1388 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1389 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1391 // Don't emit a dead load.
1392 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
1396 ArgValues.push_back(ArgVal);
1399 // If the function takes variable number of arguments, make a frame index for
1400 // the start of the first vararg value... for expansion of llvm.va_start.
1401 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1406 VarArgsNumGPR = GPR_idx;
1407 VarArgsNumFPR = FPR_idx;
1409 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1411 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 +
1412 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 +
1413 MVT::getSizeInBits(PtrVT)/8);
1415 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1422 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1424 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1426 SmallVector<SDOperand, 8> MemOps;
1428 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1429 // stored to the VarArgsFrameIndex on the stack.
1431 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1432 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1433 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1434 MemOps.push_back(Store);
1435 // Increment the address by four for the next argument to store
1436 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1437 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1441 // If this function is vararg, store any remaining integer argument regs
1442 // to their spots on the stack so that they may be loaded by deferencing the
1443 // result of va_next.
1444 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1447 VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
1449 VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1451 MF.addLiveIn(GPR[GPR_idx], VReg);
1452 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1453 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1454 MemOps.push_back(Store);
1455 // Increment the address by four for the next argument to store
1456 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1457 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1460 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1463 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1464 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1465 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1466 MemOps.push_back(Store);
1467 // Increment the address by eight for the next argument to store
1468 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1470 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1473 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1475 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
1477 MF.addLiveIn(FPR[FPR_idx], VReg);
1478 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
1479 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1480 MemOps.push_back(Store);
1481 // Increment the address by eight for the next argument to store
1482 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1484 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1488 if (!MemOps.empty())
1489 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1492 ArgValues.push_back(Root);
1494 // Return the new list of results.
1495 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1496 Op.Val->value_end());
1497 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1500 /// isCallCompatibleAddress - Return the immediate to use if the specified
1501 /// 32-bit value is representable in the immediate field of a BxA instruction.
1502 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
1503 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1506 int Addr = C->getValue();
1507 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1508 (Addr << 6 >> 6) != Addr)
1509 return 0; // Top 6 bits have to be sext of immediate.
1511 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
1515 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
1516 const PPCSubtarget &Subtarget) {
1517 SDOperand Chain = Op.getOperand(0);
1518 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1519 SDOperand Callee = Op.getOperand(4);
1520 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1522 bool isMachoABI = Subtarget.isMachoABI();
1523 bool isELF32_ABI = Subtarget.isELF32_ABI();
1525 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1526 bool isPPC64 = PtrVT == MVT::i64;
1527 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1529 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1530 // SelectExpr to use to put the arguments in the appropriate registers.
1531 std::vector<SDOperand> args_to_use;
1533 // Count how many bytes are to be pushed on the stack, including the linkage
1534 // area, and parameter passing area. We start with 24/48 bytes, which is
1535 // prereserved space for [SP][CR][LR][3 x unused].
1536 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1538 // Add up all the space actually used.
1539 for (unsigned i = 0; i != NumOps; ++i) {
1540 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
1541 ArgSize = std::max(ArgSize, PtrByteSize);
1542 NumBytes += ArgSize;
1545 // The prolog code of the callee may store up to 8 GPR argument registers to
1546 // the stack, allowing va_start to index over them in memory if its varargs.
1547 // Because we cannot tell if this is needed on the caller side, we have to
1548 // conservatively assume that it is needed. As such, make sure we have at
1549 // least enough stack space for the caller to store the 8 GPRs.
1550 NumBytes = std::max(NumBytes,
1551 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1553 // Adjust the stack pointer for the new arguments...
1554 // These operations are automatically eliminated by the prolog/epilog pass
1555 Chain = DAG.getCALLSEQ_START(Chain,
1556 DAG.getConstant(NumBytes, PtrVT));
1558 // Set up a copy of the stack pointer for use loading and storing any
1559 // arguments that may not fit in the registers available for argument
1563 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
1565 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
1567 // Figure out which arguments are going to go in registers, and which in
1568 // memory. Also, if this is a vararg function, floating point operations
1569 // must be stored to our stack, and loaded into integer regs as well, if
1570 // any integer regs are available for argument passing.
1571 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1572 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1574 static const unsigned GPR_32[] = { // 32-bit registers.
1575 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1576 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1578 static const unsigned GPR_64[] = { // 64-bit registers.
1579 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1580 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1582 static const unsigned *FPR = GetFPR(Subtarget);
1584 static const unsigned VR[] = {
1585 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1586 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1588 const unsigned NumGPRs = array_lengthof(GPR_32);
1589 const unsigned NumFPRs = isMachoABI ? 13 : 8;
1590 const unsigned NumVRs = array_lengthof( VR);
1592 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1594 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1595 SmallVector<SDOperand, 8> MemOpChains;
1596 for (unsigned i = 0; i != NumOps; ++i) {
1598 SDOperand Arg = Op.getOperand(5+2*i);
1599 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
1600 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1601 // See if next argument requires stack alignment in ELF
1602 unsigned next = 5+2*(i+1)+1;
1603 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) &&
1604 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) &&
1605 (!(Flags & AlignFlag)));
1607 // PtrOff will be used to store the current argument to the stack if a
1608 // register cannot be found for it.
1611 // Stack align in ELF 32
1612 if (isELF32_ABI && Expand)
1613 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
1614 StackPtr.getValueType());
1616 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1618 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1620 // On PPC64, promote integers to 64-bit values.
1621 if (isPPC64 && Arg.getValueType() == MVT::i32) {
1622 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1624 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1627 switch (Arg.getValueType()) {
1628 default: assert(0 && "Unexpected ValueType for argument!");
1631 // Double word align in ELF
1632 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
1633 if (GPR_idx != NumGPRs) {
1634 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
1636 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1639 if (inMem || isMachoABI) {
1640 // Stack align in ELF
1641 if (isELF32_ABI && Expand)
1642 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1644 ArgOffset += PtrByteSize;
1650 // Float varargs need to be promoted to double.
1651 if (Arg.getValueType() == MVT::f32)
1652 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
1655 if (FPR_idx != NumFPRs) {
1656 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1659 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1660 MemOpChains.push_back(Store);
1662 // Float varargs are always shadowed in available integer registers
1663 if (GPR_idx != NumGPRs) {
1664 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1665 MemOpChains.push_back(Load.getValue(1));
1666 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1669 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
1670 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1671 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
1672 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1673 MemOpChains.push_back(Load.getValue(1));
1674 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1678 // If we have any FPRs remaining, we may also have GPRs remaining.
1679 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1682 if (GPR_idx != NumGPRs)
1684 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
1685 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
1690 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1693 if (inMem || isMachoABI) {
1694 // Stack align in ELF
1695 if (isELF32_ABI && Expand)
1696 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1700 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1707 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1708 assert(VR_idx != NumVRs &&
1709 "Don't support passing more than 12 vector args yet!");
1710 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1714 if (!MemOpChains.empty())
1715 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1716 &MemOpChains[0], MemOpChains.size());
1718 // Build a sequence of copy-to-reg nodes chained together with token chain
1719 // and flag operands which copy the outgoing args into the appropriate regs.
1721 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1722 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1724 InFlag = Chain.getValue(1);
1727 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
1728 if (isVarArg && isELF32_ABI) {
1729 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0);
1730 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag);
1731 InFlag = Chain.getValue(1);
1734 std::vector<MVT::ValueType> NodeTys;
1735 NodeTys.push_back(MVT::Other); // Returns a chain
1736 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1738 SmallVector<SDOperand, 8> Ops;
1739 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
1741 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1742 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1743 // node so that legalize doesn't hack it.
1744 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1745 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1746 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1747 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1748 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1749 // If this is an absolute destination address, use the munged value.
1750 Callee = SDOperand(Dest, 0);
1752 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1753 // to do the call, we can't use PPCISD::CALL.
1754 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
1755 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
1756 InFlag = Chain.getValue(1);
1758 // Copy the callee address into R12 on darwin.
1760 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1761 InFlag = Chain.getValue(1);
1765 NodeTys.push_back(MVT::Other);
1766 NodeTys.push_back(MVT::Flag);
1767 Ops.push_back(Chain);
1768 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
1772 // If this is a direct call, pass the chain and the callee.
1774 Ops.push_back(Chain);
1775 Ops.push_back(Callee);
1778 // Add argument registers to the end of the list so that they are known live
1780 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1781 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1782 RegsToPass[i].second.getValueType()));
1785 Ops.push_back(InFlag);
1786 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
1787 InFlag = Chain.getValue(1);
1789 SDOperand ResultVals[3];
1790 unsigned NumResults = 0;
1793 // If the call has results, copy the values out of the ret val registers.
1794 switch (Op.Val->getValueType(0)) {
1795 default: assert(0 && "Unexpected ret value!");
1796 case MVT::Other: break;
1798 if (Op.Val->getValueType(1) == MVT::i32) {
1799 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1800 ResultVals[0] = Chain.getValue(0);
1801 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32,
1802 Chain.getValue(2)).getValue(1);
1803 ResultVals[1] = Chain.getValue(0);
1805 NodeTys.push_back(MVT::i32);
1807 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1808 ResultVals[0] = Chain.getValue(0);
1811 NodeTys.push_back(MVT::i32);
1814 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
1815 ResultVals[0] = Chain.getValue(0);
1817 NodeTys.push_back(MVT::i64);
1820 if (Op.Val->getValueType(1) == MVT::f64) {
1821 Chain = DAG.getCopyFromReg(Chain, PPC::F1, MVT::f64, InFlag).getValue(1);
1822 ResultVals[0] = Chain.getValue(0);
1823 Chain = DAG.getCopyFromReg(Chain, PPC::F2, MVT::f64,
1824 Chain.getValue(2)).getValue(1);
1825 ResultVals[1] = Chain.getValue(0);
1827 NodeTys.push_back(MVT::f64);
1828 NodeTys.push_back(MVT::f64);
1831 // else fall through
1833 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1834 InFlag).getValue(1);
1835 ResultVals[0] = Chain.getValue(0);
1837 NodeTys.push_back(Op.Val->getValueType(0));
1843 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1844 InFlag).getValue(1);
1845 ResultVals[0] = Chain.getValue(0);
1847 NodeTys.push_back(Op.Val->getValueType(0));
1851 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1852 DAG.getConstant(NumBytes, PtrVT));
1853 NodeTys.push_back(MVT::Other);
1855 // If the function returns void, just return the chain.
1856 if (NumResults == 0)
1859 // Otherwise, merge everything together with a MERGE_VALUES node.
1860 ResultVals[NumResults++] = Chain;
1861 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1862 ResultVals, NumResults);
1863 return Res.getValue(Op.ResNo);
1866 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) {
1867 SmallVector<CCValAssign, 16> RVLocs;
1868 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1869 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1870 CCState CCInfo(CC, isVarArg, TM, RVLocs);
1871 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
1873 // If this is the first return lowered for this function, add the regs to the
1874 // liveout set for the function.
1875 if (DAG.getMachineFunction().liveout_empty()) {
1876 for (unsigned i = 0; i != RVLocs.size(); ++i)
1877 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
1880 SDOperand Chain = Op.getOperand(0);
1883 // Copy the result values into the output registers.
1884 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1885 CCValAssign &VA = RVLocs[i];
1886 assert(VA.isRegLoc() && "Can only return in registers!");
1887 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
1888 Flag = Chain.getValue(1);
1892 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
1894 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
1897 static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
1898 const PPCSubtarget &Subtarget) {
1899 // When we pop the dynamic allocation we need to restore the SP link.
1901 // Get the corect type for pointers.
1902 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1904 // Construct the stack pointer operand.
1905 bool IsPPC64 = Subtarget.isPPC64();
1906 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
1907 SDOperand StackPtr = DAG.getRegister(SP, PtrVT);
1909 // Get the operands for the STACKRESTORE.
1910 SDOperand Chain = Op.getOperand(0);
1911 SDOperand SaveSP = Op.getOperand(1);
1913 // Load the old link SP.
1914 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
1916 // Restore the stack pointer.
1917 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
1919 // Store the old link SP.
1920 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
1923 static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG,
1924 const PPCSubtarget &Subtarget) {
1925 MachineFunction &MF = DAG.getMachineFunction();
1926 bool IsPPC64 = Subtarget.isPPC64();
1927 bool isMachoABI = Subtarget.isMachoABI();
1929 // Get current frame pointer save index. The users of this index will be
1930 // primarily DYNALLOC instructions.
1931 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1932 int FPSI = FI->getFramePointerSaveIndex();
1934 // If the frame pointer save index hasn't been defined yet.
1936 // Find out what the fix offset of the frame pointer save area.
1937 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
1939 // Allocate the frame index for frame pointer save area.
1940 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
1942 FI->setFramePointerSaveIndex(FPSI);
1946 SDOperand Chain = Op.getOperand(0);
1947 SDOperand Size = Op.getOperand(1);
1949 // Get the corect type for pointers.
1950 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1952 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
1953 DAG.getConstant(0, PtrVT), Size);
1954 // Construct a node for the frame pointer save index.
1955 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT);
1956 // Build a DYNALLOC node.
1957 SDOperand Ops[3] = { Chain, NegSize, FPSIdx };
1958 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
1959 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
1963 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
1965 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
1966 // Not FP? Not a fsel.
1967 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
1968 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
1971 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1973 // Cannot handle SETEQ/SETNE.
1974 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
1976 MVT::ValueType ResVT = Op.getValueType();
1977 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
1978 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1979 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
1981 // If the RHS of the comparison is a 0.0, we don't need to do the
1982 // subtraction at all.
1983 if (isFloatingPointZero(RHS))
1985 default: break; // SETUO etc aren't handled by fsel.
1989 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1993 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1994 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1995 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
1999 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2003 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2004 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2005 return DAG.getNode(PPCISD::FSEL, ResVT,
2006 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
2011 default: break; // SETUO etc aren't handled by fsel.
2015 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2016 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2017 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2018 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2022 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2023 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2024 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2025 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2029 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2030 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2031 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2032 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2036 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2037 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2038 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2039 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2044 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
2045 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
2046 SDOperand Src = Op.getOperand(0);
2047 if (Src.getValueType() == MVT::f32)
2048 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
2051 switch (Op.getValueType()) {
2052 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
2054 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
2057 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
2061 // Convert the FP value to an int value through memory.
2062 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
2063 if (Op.getValueType() == MVT::i32)
2064 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
2068 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
2069 if (Op.getOperand(0).getValueType() == MVT::i64) {
2070 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
2071 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
2072 if (Op.getValueType() == MVT::f32)
2073 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
2077 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
2078 "Unhandled SINT_TO_FP type in custom expander!");
2079 // Since we only generate this in 64-bit mode, we can take advantage of
2080 // 64-bit registers. In particular, sign extend the input value into the
2081 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
2082 // then lfd it and fcfid it.
2083 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2084 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
2085 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2086 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2088 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
2091 // STD the extended value into the stack slot.
2092 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
2093 DAG.getEntryNode(), Ext64, FIdx,
2094 DAG.getSrcValue(NULL));
2095 // Load the value as a double.
2096 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
2098 // FCFID it and return it.
2099 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
2100 if (Op.getValueType() == MVT::f32)
2101 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
2105 static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2106 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2107 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
2109 // Expand into a bunch of logical ops. Note that these ops
2110 // depend on the PPC behavior for oversized shift amounts.
2111 SDOperand Lo = Op.getOperand(0);
2112 SDOperand Hi = Op.getOperand(1);
2113 SDOperand Amt = Op.getOperand(2);
2115 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2116 DAG.getConstant(32, MVT::i32), Amt);
2117 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
2118 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
2119 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2120 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2121 DAG.getConstant(-32U, MVT::i32));
2122 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
2123 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2124 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
2125 SDOperand OutOps[] = { OutLo, OutHi };
2126 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2130 static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2131 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2132 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!");
2134 // Otherwise, expand into a bunch of logical ops. Note that these ops
2135 // depend on the PPC behavior for oversized shift amounts.
2136 SDOperand Lo = Op.getOperand(0);
2137 SDOperand Hi = Op.getOperand(1);
2138 SDOperand Amt = Op.getOperand(2);
2140 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2141 DAG.getConstant(32, MVT::i32), Amt);
2142 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2143 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2144 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2145 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2146 DAG.getConstant(-32U, MVT::i32));
2147 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
2148 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2149 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
2150 SDOperand OutOps[] = { OutLo, OutHi };
2151 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2155 static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
2156 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2157 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
2159 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
2160 SDOperand Lo = Op.getOperand(0);
2161 SDOperand Hi = Op.getOperand(1);
2162 SDOperand Amt = Op.getOperand(2);
2164 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2165 DAG.getConstant(32, MVT::i32), Amt);
2166 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2167 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2168 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2169 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2170 DAG.getConstant(-32U, MVT::i32));
2171 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
2172 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
2173 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
2174 Tmp4, Tmp6, ISD::SETLE);
2175 SDOperand OutOps[] = { OutLo, OutHi };
2176 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2180 //===----------------------------------------------------------------------===//
2181 // Vector related lowering.
2184 // If this is a vector of constants or undefs, get the bits. A bit in
2185 // UndefBits is set if the corresponding element of the vector is an
2186 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2187 // zero. Return true if this is not an array of constants, false if it is.
2189 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
2190 uint64_t UndefBits[2]) {
2191 // Start with zero'd results.
2192 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
2194 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
2195 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2196 SDOperand OpVal = BV->getOperand(i);
2198 unsigned PartNo = i >= e/2; // In the upper 128 bits?
2199 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
2201 uint64_t EltBits = 0;
2202 if (OpVal.getOpcode() == ISD::UNDEF) {
2203 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
2204 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
2206 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2207 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
2208 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2209 assert(CN->getValueType(0) == MVT::f32 &&
2210 "Only one legal FP vector type!");
2211 EltBits = FloatToBits(CN->getValueAPF().convertToFloat());
2213 // Nonconstant element.
2217 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
2220 //printf("%llx %llx %llx %llx\n",
2221 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
2225 // If this is a splat (repetition) of a value across the whole vector, return
2226 // the smallest size that splats it. For example, "0x01010101010101..." is a
2227 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2228 // SplatSize = 1 byte.
2229 static bool isConstantSplat(const uint64_t Bits128[2],
2230 const uint64_t Undef128[2],
2231 unsigned &SplatBits, unsigned &SplatUndef,
2232 unsigned &SplatSize) {
2234 // Don't let undefs prevent splats from matching. See if the top 64-bits are
2235 // the same as the lower 64-bits, ignoring undefs.
2236 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
2237 return false; // Can't be a splat if two pieces don't match.
2239 uint64_t Bits64 = Bits128[0] | Bits128[1];
2240 uint64_t Undef64 = Undef128[0] & Undef128[1];
2242 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
2244 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
2245 return false; // Can't be a splat if two pieces don't match.
2247 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
2248 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
2250 // If the top 16-bits are different than the lower 16-bits, ignoring
2251 // undefs, we have an i32 splat.
2252 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
2254 SplatUndef = Undef32;
2259 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
2260 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
2262 // If the top 8-bits are different than the lower 8-bits, ignoring
2263 // undefs, we have an i16 splat.
2264 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
2266 SplatUndef = Undef16;
2271 // Otherwise, we have an 8-bit splat.
2272 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
2273 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
2278 /// BuildSplatI - Build a canonical splati of Val with an element size of
2279 /// SplatSize. Cast the result to VT.
2280 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
2281 SelectionDAG &DAG) {
2282 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
2284 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
2285 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
2288 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
2290 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
2294 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
2296 // Build a canonical splat for this value.
2297 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT));
2298 SmallVector<SDOperand, 8> Ops;
2299 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
2300 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
2301 &Ops[0], Ops.size());
2302 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
2305 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
2306 /// specified intrinsic ID.
2307 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
2309 MVT::ValueType DestVT = MVT::Other) {
2310 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
2311 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2312 DAG.getConstant(IID, MVT::i32), LHS, RHS);
2315 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
2316 /// specified intrinsic ID.
2317 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
2318 SDOperand Op2, SelectionDAG &DAG,
2319 MVT::ValueType DestVT = MVT::Other) {
2320 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
2321 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2322 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
2326 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
2327 /// amount. The result has the specified value type.
2328 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
2329 MVT::ValueType VT, SelectionDAG &DAG) {
2330 // Force LHS/RHS to be the right type.
2331 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
2332 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
2335 for (unsigned i = 0; i != 16; ++i)
2336 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
2337 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
2338 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
2339 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
2342 // If this is a case we can't handle, return null and let the default
2343 // expansion code take care of it. If we CAN select this case, and if it
2344 // selects to a single instruction, return Op. Otherwise, if we can codegen
2345 // this case more efficiently than a constant pool load, lower it to the
2346 // sequence of ops that should be used.
2347 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2348 // If this is a vector of constants or undefs, get the bits. A bit in
2349 // UndefBits is set if the corresponding element of the vector is an
2350 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2352 uint64_t VectorBits[2];
2353 uint64_t UndefBits[2];
2354 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
2355 return SDOperand(); // Not a constant vector.
2357 // If this is a splat (repetition) of a value across the whole vector, return
2358 // the smallest size that splats it. For example, "0x01010101010101..." is a
2359 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2360 // SplatSize = 1 byte.
2361 unsigned SplatBits, SplatUndef, SplatSize;
2362 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
2363 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
2365 // First, handle single instruction cases.
2368 if (SplatBits == 0) {
2369 // Canonicalize all zero vectors to be v4i32.
2370 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
2371 SDOperand Z = DAG.getConstant(0, MVT::i32);
2372 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
2373 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
2378 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
2379 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
2380 if (SextVal >= -16 && SextVal <= 15)
2381 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
2384 // Two instruction sequences.
2386 // If this value is in the range [-32,30] and is even, use:
2387 // tmp = VSPLTI[bhw], result = add tmp, tmp
2388 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
2389 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
2390 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
2393 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
2394 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
2396 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
2397 // Make -1 and vspltisw -1:
2398 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
2400 // Make the VSLW intrinsic, computing 0x8000_0000.
2401 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
2404 // xor by OnesV to invert it.
2405 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
2406 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2409 // Check to see if this is a wide variety of vsplti*, binop self cases.
2410 unsigned SplatBitSize = SplatSize*8;
2411 static const signed char SplatCsts[] = {
2412 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
2413 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
2416 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
2417 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
2418 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
2419 int i = SplatCsts[idx];
2421 // Figure out what shift amount will be used by altivec if shifted by i in
2423 unsigned TypeShiftAmt = i & (SplatBitSize-1);
2425 // vsplti + shl self.
2426 if (SextVal == (i << (int)TypeShiftAmt)) {
2427 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2428 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2429 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
2430 Intrinsic::ppc_altivec_vslw
2432 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2433 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2436 // vsplti + srl self.
2437 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2438 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2439 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2440 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
2441 Intrinsic::ppc_altivec_vsrw
2443 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2444 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2447 // vsplti + sra self.
2448 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2449 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2450 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2451 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
2452 Intrinsic::ppc_altivec_vsraw
2454 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2455 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2458 // vsplti + rol self.
2459 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
2460 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
2461 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2462 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2463 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
2464 Intrinsic::ppc_altivec_vrlw
2466 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2467 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2470 // t = vsplti c, result = vsldoi t, t, 1
2471 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
2472 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2473 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
2475 // t = vsplti c, result = vsldoi t, t, 2
2476 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
2477 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2478 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
2480 // t = vsplti c, result = vsldoi t, t, 3
2481 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
2482 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2483 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
2487 // Three instruction sequences.
2489 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
2490 if (SextVal >= 0 && SextVal <= 31) {
2491 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
2492 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2493 LHS = DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
2494 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2496 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
2497 if (SextVal >= -31 && SextVal <= 0) {
2498 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
2499 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2500 LHS = DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
2501 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2508 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2509 /// the specified operations to build the shuffle.
2510 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
2511 SDOperand RHS, SelectionDAG &DAG) {
2512 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2513 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2514 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2517 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2529 if (OpNum == OP_COPY) {
2530 if (LHSID == (1*9+2)*9+3) return LHS;
2531 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2535 SDOperand OpLHS, OpRHS;
2536 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
2537 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
2539 unsigned ShufIdxs[16];
2541 default: assert(0 && "Unknown i32 permute!");
2543 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
2544 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
2545 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
2546 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
2549 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
2550 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
2551 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
2552 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
2555 for (unsigned i = 0; i != 16; ++i)
2556 ShufIdxs[i] = (i&3)+0;
2559 for (unsigned i = 0; i != 16; ++i)
2560 ShufIdxs[i] = (i&3)+4;
2563 for (unsigned i = 0; i != 16; ++i)
2564 ShufIdxs[i] = (i&3)+8;
2567 for (unsigned i = 0; i != 16; ++i)
2568 ShufIdxs[i] = (i&3)+12;
2571 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
2573 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
2575 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
2578 for (unsigned i = 0; i != 16; ++i)
2579 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
2581 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
2582 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2585 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
2586 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
2587 /// return the code it can be lowered into. Worst case, it can always be
2588 /// lowered into a vperm.
2589 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2590 SDOperand V1 = Op.getOperand(0);
2591 SDOperand V2 = Op.getOperand(1);
2592 SDOperand PermMask = Op.getOperand(2);
2594 // Cases that are handled by instructions that take permute immediates
2595 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
2596 // selected by the instruction selector.
2597 if (V2.getOpcode() == ISD::UNDEF) {
2598 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
2599 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
2600 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
2601 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
2602 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
2603 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
2604 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
2605 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
2606 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
2607 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
2608 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
2609 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
2614 // Altivec has a variety of "shuffle immediates" that take two vector inputs
2615 // and produce a fixed permutation. If any of these match, do not lower to
2617 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
2618 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
2619 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
2620 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
2621 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
2622 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
2623 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
2624 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
2625 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
2628 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
2629 // perfect shuffle table to emit an optimal matching sequence.
2630 unsigned PFIndexes[4];
2631 bool isFourElementShuffle = true;
2632 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
2633 unsigned EltNo = 8; // Start out undef.
2634 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
2635 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
2636 continue; // Undef, ignore it.
2638 unsigned ByteSource =
2639 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
2640 if ((ByteSource & 3) != j) {
2641 isFourElementShuffle = false;
2646 EltNo = ByteSource/4;
2647 } else if (EltNo != ByteSource/4) {
2648 isFourElementShuffle = false;
2652 PFIndexes[i] = EltNo;
2655 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
2656 // perfect shuffle vector to determine if it is cost effective to do this as
2657 // discrete instructions, or whether we should use a vperm.
2658 if (isFourElementShuffle) {
2659 // Compute the index in the perfect shuffle table.
2660 unsigned PFTableIndex =
2661 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2663 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2664 unsigned Cost = (PFEntry >> 30);
2666 // Determining when to avoid vperm is tricky. Many things affect the cost
2667 // of vperm, particularly how many times the perm mask needs to be computed.
2668 // For example, if the perm mask can be hoisted out of a loop or is already
2669 // used (perhaps because there are multiple permutes with the same shuffle
2670 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
2671 // the loop requires an extra register.
2673 // As a compromise, we only emit discrete instructions if the shuffle can be
2674 // generated in 3 or fewer operations. When we have loop information
2675 // available, if this block is within a loop, we should avoid using vperm
2676 // for 3-operation perms and use a constant pool load instead.
2678 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
2681 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
2682 // vector that will get spilled to the constant pool.
2683 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
2685 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
2686 // that it is in input element units, not in bytes. Convert now.
2687 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType());
2688 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
2690 SmallVector<SDOperand, 16> ResultMask;
2691 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
2693 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
2696 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
2698 for (unsigned j = 0; j != BytesPerElement; ++j)
2699 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
2703 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
2704 &ResultMask[0], ResultMask.size());
2705 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
2708 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
2709 /// altivec comparison. If it is, return true and fill in Opc/isDot with
2710 /// information about the intrinsic.
2711 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
2713 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
2716 switch (IntrinsicID) {
2717 default: return false;
2718 // Comparison predicates.
2719 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
2720 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
2721 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
2722 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
2723 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
2724 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
2725 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
2726 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
2727 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
2728 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
2729 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
2730 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
2731 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
2733 // Normal Comparisons.
2734 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
2735 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
2736 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
2737 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
2738 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
2739 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
2740 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
2741 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
2742 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
2743 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
2744 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
2745 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
2746 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
2751 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
2752 /// lower, do it, otherwise return null.
2753 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
2754 // If this is a lowered altivec predicate compare, CompareOpc is set to the
2755 // opcode number of the comparison.
2758 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
2759 return SDOperand(); // Don't custom lower most intrinsics.
2761 // If this is a non-dot comparison, make the VCMP node and we are done.
2763 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
2764 Op.getOperand(1), Op.getOperand(2),
2765 DAG.getConstant(CompareOpc, MVT::i32));
2766 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
2769 // Create the PPCISD altivec 'dot' comparison node.
2771 Op.getOperand(2), // LHS
2772 Op.getOperand(3), // RHS
2773 DAG.getConstant(CompareOpc, MVT::i32)
2775 std::vector<MVT::ValueType> VTs;
2776 VTs.push_back(Op.getOperand(2).getValueType());
2777 VTs.push_back(MVT::Flag);
2778 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2780 // Now that we have the comparison, emit a copy from the CR to a GPR.
2781 // This is flagged to the above dot comparison.
2782 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
2783 DAG.getRegister(PPC::CR6, MVT::i32),
2784 CompNode.getValue(1));
2786 // Unpack the result based on how the target uses it.
2787 unsigned BitNo; // Bit # of CR6.
2788 bool InvertBit; // Invert result?
2789 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
2790 default: // Can't happen, don't crash on invalid number though.
2791 case 0: // Return the value of the EQ bit of CR6.
2792 BitNo = 0; InvertBit = false;
2794 case 1: // Return the inverted value of the EQ bit of CR6.
2795 BitNo = 0; InvertBit = true;
2797 case 2: // Return the value of the LT bit of CR6.
2798 BitNo = 2; InvertBit = false;
2800 case 3: // Return the inverted value of the LT bit of CR6.
2801 BitNo = 2; InvertBit = true;
2805 // Shift the bit into the low position.
2806 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
2807 DAG.getConstant(8-(3-BitNo), MVT::i32));
2809 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
2810 DAG.getConstant(1, MVT::i32));
2812 // If we are supposed to, toggle the bit.
2814 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
2815 DAG.getConstant(1, MVT::i32));
2819 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2820 // Create a stack slot that is 16-byte aligned.
2821 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2822 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
2823 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2824 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2826 // Store the input value into Value#0 of the stack slot.
2827 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
2828 Op.getOperand(0), FIdx, NULL, 0);
2830 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
2833 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
2834 if (Op.getValueType() == MVT::v4i32) {
2835 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2837 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
2838 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
2840 SDOperand RHSSwap = // = vrlw RHS, 16
2841 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
2843 // Shrinkify inputs to v8i16.
2844 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
2845 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
2846 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
2848 // Low parts multiplied together, generating 32-bit results (we ignore the
2850 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
2851 LHS, RHS, DAG, MVT::v4i32);
2853 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
2854 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
2855 // Shift the high parts up 16 bits.
2856 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
2857 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
2858 } else if (Op.getValueType() == MVT::v8i16) {
2859 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2861 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
2863 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
2864 LHS, RHS, Zero, DAG);
2865 } else if (Op.getValueType() == MVT::v16i8) {
2866 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2868 // Multiply the even 8-bit parts, producing 16-bit sums.
2869 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
2870 LHS, RHS, DAG, MVT::v8i16);
2871 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
2873 // Multiply the odd 8-bit parts, producing 16-bit sums.
2874 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
2875 LHS, RHS, DAG, MVT::v8i16);
2876 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
2878 // Merge the results together.
2880 for (unsigned i = 0; i != 8; ++i) {
2881 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
2882 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
2884 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
2885 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2887 assert(0 && "Unknown mul to lower!");
2892 /// LowerOperation - Provide custom lowering hooks for some operations.
2894 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2895 switch (Op.getOpcode()) {
2896 default: assert(0 && "Wasn't expecting to be able to lower this!");
2897 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2898 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2899 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2900 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2901 case ISD::SETCC: return LowerSETCC(Op, DAG);
2903 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
2904 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
2907 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
2908 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
2910 case ISD::FORMAL_ARGUMENTS:
2911 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
2912 VarArgsStackOffset, VarArgsNumGPR,
2913 VarArgsNumFPR, PPCSubTarget);
2915 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget);
2916 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
2917 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
2918 case ISD::DYNAMIC_STACKALLOC:
2919 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
2921 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2922 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
2923 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
2925 // Lower 64-bit shifts.
2926 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
2927 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
2928 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
2930 // Vector-related lowering.
2931 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2932 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2933 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2934 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2935 case ISD::MUL: return LowerMUL(Op, DAG);
2937 // Frame & Return address. Currently unimplemented
2938 case ISD::RETURNADDR: break;
2939 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2944 //===----------------------------------------------------------------------===//
2945 // Other Lowering Code
2946 //===----------------------------------------------------------------------===//
2949 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2950 MachineBasicBlock *BB) {
2951 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2952 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
2953 MI->getOpcode() == PPC::SELECT_CC_I8 ||
2954 MI->getOpcode() == PPC::SELECT_CC_F4 ||
2955 MI->getOpcode() == PPC::SELECT_CC_F8 ||
2956 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
2957 "Unexpected instr type to insert");
2959 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2960 // control-flow pattern. The incoming instruction knows the destination vreg
2961 // to set, the condition code register to branch on, the true/false values to
2962 // select between, and a branch opcode to use.
2963 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2964 ilist<MachineBasicBlock>::iterator It = BB;
2970 // cmpTY ccX, r1, r2
2972 // fallthrough --> copy0MBB
2973 MachineBasicBlock *thisMBB = BB;
2974 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2975 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2976 unsigned SelectPred = MI->getOperand(4).getImm();
2977 BuildMI(BB, TII->get(PPC::BCC))
2978 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
2979 MachineFunction *F = BB->getParent();
2980 F->getBasicBlockList().insert(It, copy0MBB);
2981 F->getBasicBlockList().insert(It, sinkMBB);
2982 // Update machine-CFG edges by first adding all successors of the current
2983 // block to the new block which will contain the Phi node for the select.
2984 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2985 e = BB->succ_end(); i != e; ++i)
2986 sinkMBB->addSuccessor(*i);
2987 // Next, remove all successors of the current block, and add the true
2988 // and fallthrough blocks as its successors.
2989 while(!BB->succ_empty())
2990 BB->removeSuccessor(BB->succ_begin());
2991 BB->addSuccessor(copy0MBB);
2992 BB->addSuccessor(sinkMBB);
2995 // %FalseValue = ...
2996 // # fallthrough to sinkMBB
2999 // Update machine-CFG edges
3000 BB->addSuccessor(sinkMBB);
3003 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3006 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
3007 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
3008 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3010 delete MI; // The pseudo instruction is gone now.
3014 //===----------------------------------------------------------------------===//
3015 // Target Optimization Hooks
3016 //===----------------------------------------------------------------------===//
3018 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
3019 DAGCombinerInfo &DCI) const {
3020 TargetMachine &TM = getTargetMachine();
3021 SelectionDAG &DAG = DCI.DAG;
3022 switch (N->getOpcode()) {
3025 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3026 if (C->getValue() == 0) // 0 << V -> 0.
3027 return N->getOperand(0);
3031 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3032 if (C->getValue() == 0) // 0 >>u V -> 0.
3033 return N->getOperand(0);
3037 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3038 if (C->getValue() == 0 || // 0 >>s V -> 0.
3039 C->isAllOnesValue()) // -1 >>s V -> -1.
3040 return N->getOperand(0);
3044 case ISD::SINT_TO_FP:
3045 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
3046 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
3047 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
3048 // We allow the src/dst to be either f32/f64, but the intermediate
3049 // type must be i64.
3050 if (N->getOperand(0).getValueType() == MVT::i64) {
3051 SDOperand Val = N->getOperand(0).getOperand(0);
3052 if (Val.getValueType() == MVT::f32) {
3053 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3054 DCI.AddToWorklist(Val.Val);
3057 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
3058 DCI.AddToWorklist(Val.Val);
3059 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
3060 DCI.AddToWorklist(Val.Val);
3061 if (N->getValueType(0) == MVT::f32) {
3062 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
3063 DCI.AddToWorklist(Val.Val);
3066 } else if (N->getOperand(0).getValueType() == MVT::i32) {
3067 // If the intermediate type is i32, we can avoid the load/store here
3074 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
3075 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
3076 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
3077 N->getOperand(1).getValueType() == MVT::i32) {
3078 SDOperand Val = N->getOperand(1).getOperand(0);
3079 if (Val.getValueType() == MVT::f32) {
3080 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3081 DCI.AddToWorklist(Val.Val);
3083 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
3084 DCI.AddToWorklist(Val.Val);
3086 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
3087 N->getOperand(2), N->getOperand(3));
3088 DCI.AddToWorklist(Val.Val);
3092 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
3093 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
3094 N->getOperand(1).Val->hasOneUse() &&
3095 (N->getOperand(1).getValueType() == MVT::i32 ||
3096 N->getOperand(1).getValueType() == MVT::i16)) {
3097 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
3098 // Do an any-extend to 32-bits if this is a half-word input.
3099 if (BSwapOp.getValueType() == MVT::i16)
3100 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
3102 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
3103 N->getOperand(2), N->getOperand(3),
3104 DAG.getValueType(N->getOperand(1).getValueType()));
3108 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
3109 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
3110 N->getOperand(0).hasOneUse() &&
3111 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
3112 SDOperand Load = N->getOperand(0);
3113 LoadSDNode *LD = cast<LoadSDNode>(Load);
3114 // Create the byte-swapping load.
3115 std::vector<MVT::ValueType> VTs;
3116 VTs.push_back(MVT::i32);
3117 VTs.push_back(MVT::Other);
3118 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset());
3120 LD->getChain(), // Chain
3121 LD->getBasePtr(), // Ptr
3123 DAG.getValueType(N->getValueType(0)) // VT
3125 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
3127 // If this is an i16 load, insert the truncate.
3128 SDOperand ResVal = BSLoad;
3129 if (N->getValueType(0) == MVT::i16)
3130 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
3132 // First, combine the bswap away. This makes the value produced by the
3134 DCI.CombineTo(N, ResVal);
3136 // Next, combine the load away, we give it a bogus result value but a real
3137 // chain result. The result value is dead because the bswap is dead.
3138 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
3140 // Return N so it doesn't get rechecked!
3141 return SDOperand(N, 0);
3145 case PPCISD::VCMP: {
3146 // If a VCMPo node already exists with exactly the same operands as this
3147 // node, use its result instead of this node (VCMPo computes both a CR6 and
3148 // a normal output).
3150 if (!N->getOperand(0).hasOneUse() &&
3151 !N->getOperand(1).hasOneUse() &&
3152 !N->getOperand(2).hasOneUse()) {
3154 // Scan all of the users of the LHS, looking for VCMPo's that match.
3155 SDNode *VCMPoNode = 0;
3157 SDNode *LHSN = N->getOperand(0).Val;
3158 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
3160 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
3161 (*UI)->getOperand(1) == N->getOperand(1) &&
3162 (*UI)->getOperand(2) == N->getOperand(2) &&
3163 (*UI)->getOperand(0) == N->getOperand(0)) {
3168 // If there is no VCMPo node, or if the flag value has a single use, don't
3170 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
3173 // Look at the (necessarily single) use of the flag value. If it has a
3174 // chain, this transformation is more complex. Note that multiple things
3175 // could use the value result, which we should ignore.
3176 SDNode *FlagUser = 0;
3177 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
3178 FlagUser == 0; ++UI) {
3179 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
3181 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
3182 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
3189 // If the user is a MFCR instruction, we know this is safe. Otherwise we
3190 // give up for right now.
3191 if (FlagUser->getOpcode() == PPCISD::MFCR)
3192 return SDOperand(VCMPoNode, 0);
3197 // If this is a branch on an altivec predicate comparison, lower this so
3198 // that we don't have to do a MFCR: instead, branch directly on CR6. This
3199 // lowering is done pre-legalize, because the legalizer lowers the predicate
3200 // compare down to code that is difficult to reassemble.
3201 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
3202 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
3206 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
3207 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
3208 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
3209 assert(isDot && "Can't compare against a vector result!");
3211 // If this is a comparison against something other than 0/1, then we know
3212 // that the condition is never/always true.
3213 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
3214 if (Val != 0 && Val != 1) {
3215 if (CC == ISD::SETEQ) // Cond never true, remove branch.
3216 return N->getOperand(0);
3217 // Always !=, turn it into an unconditional branch.
3218 return DAG.getNode(ISD::BR, MVT::Other,
3219 N->getOperand(0), N->getOperand(4));
3222 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
3224 // Create the PPCISD altivec 'dot' comparison node.
3225 std::vector<MVT::ValueType> VTs;
3227 LHS.getOperand(2), // LHS of compare
3228 LHS.getOperand(3), // RHS of compare
3229 DAG.getConstant(CompareOpc, MVT::i32)
3231 VTs.push_back(LHS.getOperand(2).getValueType());
3232 VTs.push_back(MVT::Flag);
3233 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
3235 // Unpack the result based on how the target uses it.
3236 PPC::Predicate CompOpc;
3237 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
3238 default: // Can't happen, don't crash on invalid number though.
3239 case 0: // Branch on the value of the EQ bit of CR6.
3240 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
3242 case 1: // Branch on the inverted value of the EQ bit of CR6.
3243 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
3245 case 2: // Branch on the value of the LT bit of CR6.
3246 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
3248 case 3: // Branch on the inverted value of the LT bit of CR6.
3249 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
3253 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
3254 DAG.getConstant(CompOpc, MVT::i32),
3255 DAG.getRegister(PPC::CR6, MVT::i32),
3256 N->getOperand(4), CompNode.getValue(1));
3265 //===----------------------------------------------------------------------===//
3266 // Inline Assembly Support
3267 //===----------------------------------------------------------------------===//
3269 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
3271 uint64_t &KnownZero,
3273 const SelectionDAG &DAG,
3274 unsigned Depth) const {
3277 switch (Op.getOpcode()) {
3279 case PPCISD::LBRX: {
3280 // lhbrx is known to have the top bits cleared out.
3281 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
3282 KnownZero = 0xFFFF0000;
3285 case ISD::INTRINSIC_WO_CHAIN: {
3286 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
3288 case Intrinsic::ppc_altivec_vcmpbfp_p:
3289 case Intrinsic::ppc_altivec_vcmpeqfp_p:
3290 case Intrinsic::ppc_altivec_vcmpequb_p:
3291 case Intrinsic::ppc_altivec_vcmpequh_p:
3292 case Intrinsic::ppc_altivec_vcmpequw_p:
3293 case Intrinsic::ppc_altivec_vcmpgefp_p:
3294 case Intrinsic::ppc_altivec_vcmpgtfp_p:
3295 case Intrinsic::ppc_altivec_vcmpgtsb_p:
3296 case Intrinsic::ppc_altivec_vcmpgtsh_p:
3297 case Intrinsic::ppc_altivec_vcmpgtsw_p:
3298 case Intrinsic::ppc_altivec_vcmpgtub_p:
3299 case Intrinsic::ppc_altivec_vcmpgtuh_p:
3300 case Intrinsic::ppc_altivec_vcmpgtuw_p:
3301 KnownZero = ~1U; // All bits but the low one are known to be zero.
3309 /// getConstraintType - Given a constraint, return the type of
3310 /// constraint it is for this target.
3311 PPCTargetLowering::ConstraintType
3312 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
3313 if (Constraint.size() == 1) {
3314 switch (Constraint[0]) {
3321 return C_RegisterClass;
3324 return TargetLowering::getConstraintType(Constraint);
3327 std::pair<unsigned, const TargetRegisterClass*>
3328 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3329 MVT::ValueType VT) const {
3330 if (Constraint.size() == 1) {
3331 // GCC RS6000 Constraint Letters
3332 switch (Constraint[0]) {
3335 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
3336 return std::make_pair(0U, PPC::G8RCRegisterClass);
3337 return std::make_pair(0U, PPC::GPRCRegisterClass);
3340 return std::make_pair(0U, PPC::F4RCRegisterClass);
3341 else if (VT == MVT::f64)
3342 return std::make_pair(0U, PPC::F8RCRegisterClass);
3345 return std::make_pair(0U, PPC::VRRCRegisterClass);
3347 return std::make_pair(0U, PPC::CRRCRegisterClass);
3351 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3355 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3356 /// vector. If it is invalid, don't add anything to Ops.
3357 void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter,
3358 std::vector<SDOperand>&Ops,
3359 SelectionDAG &DAG) {
3360 SDOperand Result(0,0);
3371 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
3372 if (!CST) return; // Must be an immediate to match.
3373 unsigned Value = CST->getValue();
3375 default: assert(0 && "Unknown constraint letter!");
3376 case 'I': // "I" is a signed 16-bit constant.
3377 if ((short)Value == (int)Value)
3378 Result = DAG.getTargetConstant(Value, Op.getValueType());
3380 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
3381 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
3382 if ((short)Value == 0)
3383 Result = DAG.getTargetConstant(Value, Op.getValueType());
3385 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
3386 if ((Value >> 16) == 0)
3387 Result = DAG.getTargetConstant(Value, Op.getValueType());
3389 case 'M': // "M" is a constant that is greater than 31.
3391 Result = DAG.getTargetConstant(Value, Op.getValueType());
3393 case 'N': // "N" is a positive constant that is an exact power of two.
3394 if ((int)Value > 0 && isPowerOf2_32(Value))
3395 Result = DAG.getTargetConstant(Value, Op.getValueType());
3397 case 'O': // "O" is the constant zero.
3399 Result = DAG.getTargetConstant(Value, Op.getValueType());
3401 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
3402 if ((short)-Value == (int)-Value)
3403 Result = DAG.getTargetConstant(Value, Op.getValueType());
3411 Ops.push_back(Result);
3415 // Handle standard constraint letters.
3416 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
3419 // isLegalAddressingMode - Return true if the addressing mode represented
3420 // by AM is legal for this target, for a load/store of the specified type.
3421 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3422 const Type *Ty) const {
3423 // FIXME: PPC does not allow r+i addressing modes for vectors!
3425 // PPC allows a sign-extended 16-bit immediate field.
3426 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3429 // No global is ever allowed as a base.
3433 // PPC only support r+r,
3435 case 0: // "r+i" or just "i", depending on HasBaseReg.
3438 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3440 // Otherwise we have r+r or r+i.
3443 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3445 // Allow 2*r as r+r.
3448 // No other scales are supported.
3455 /// isLegalAddressImmediate - Return true if the integer value can be used
3456 /// as the offset of the target addressing mode for load / store of the
3458 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
3459 // PPC allows a sign-extended 16-bit immediate field.
3460 return (V > -(1 << 16) && V < (1 << 16)-1);
3463 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
3467 SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG)
3469 // Depths > 0 not supported yet!
3470 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3473 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3474 bool isPPC64 = PtrVT == MVT::i64;
3476 MachineFunction &MF = DAG.getMachineFunction();
3477 MachineFrameInfo *MFI = MF.getFrameInfo();
3478 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
3479 && MFI->getStackSize();
3482 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
3485 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,