1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCTargetMachine.h"
16 #include "PPCPerfectShuffle.h"
17 #include "llvm/ADT/VectorExtras.h"
18 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Function.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Target/TargetOptions.h"
31 PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
32 : TargetLowering(TM) {
34 // Fold away setcc operations if possible.
35 setSetCCIsExpensive();
38 // Use _setjmp/_longjmp instead of setjmp/longjmp.
39 setUseUnderscoreSetJmpLongJmp(true);
41 // Set up the register classes.
42 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
43 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
44 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
46 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
47 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
49 // PowerPC has no intrinsics for these particular operations
50 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
51 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
52 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
54 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
55 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
56 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
58 // PowerPC has no SREM/UREM instructions
59 setOperationAction(ISD::SREM, MVT::i32, Expand);
60 setOperationAction(ISD::UREM, MVT::i32, Expand);
61 setOperationAction(ISD::SREM, MVT::i64, Expand);
62 setOperationAction(ISD::UREM, MVT::i64, Expand);
64 // We don't support sin/cos/sqrt/fmod
65 setOperationAction(ISD::FSIN , MVT::f64, Expand);
66 setOperationAction(ISD::FCOS , MVT::f64, Expand);
67 setOperationAction(ISD::FREM , MVT::f64, Expand);
68 setOperationAction(ISD::FSIN , MVT::f32, Expand);
69 setOperationAction(ISD::FCOS , MVT::f32, Expand);
70 setOperationAction(ISD::FREM , MVT::f32, Expand);
72 // If we're enabling GP optimizations, use hardware square root
73 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
74 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
75 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
78 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
79 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
81 // PowerPC does not have BSWAP, CTPOP or CTTZ
82 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
83 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
84 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
85 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
86 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
87 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
89 // PowerPC does not have ROTR
90 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
92 // PowerPC does not have Select
93 setOperationAction(ISD::SELECT, MVT::i32, Expand);
94 setOperationAction(ISD::SELECT, MVT::i64, Expand);
95 setOperationAction(ISD::SELECT, MVT::f32, Expand);
96 setOperationAction(ISD::SELECT, MVT::f64, Expand);
98 // PowerPC wants to turn select_cc of FP into fsel when possible.
99 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
100 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
102 // PowerPC wants to optimize integer setcc a bit
103 setOperationAction(ISD::SETCC, MVT::i32, Custom);
105 // PowerPC does not have BRCOND which requires SetCC
106 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
108 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
109 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
111 // PowerPC does not have [U|S]INT_TO_FP
112 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
113 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
115 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
116 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
117 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
118 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
120 // PowerPC does not have truncstore for i1.
121 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
123 // We cannot sextinreg(i1). Expand to shifts.
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
127 // Support label based line numbers.
128 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
129 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
130 // FIXME - use subtarget debug flags
131 if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
132 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
134 // We want to legalize GlobalAddress and ConstantPool nodes into the
135 // appropriate instructions to materialize the address.
136 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
137 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
138 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
139 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
140 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
141 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
143 // RET must be custom lowered, to meet ABI requirements
144 setOperationAction(ISD::RET , MVT::Other, Custom);
146 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
147 setOperationAction(ISD::VASTART , MVT::Other, Custom);
149 // Use the default implementation.
150 setOperationAction(ISD::VAARG , MVT::Other, Expand);
151 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
152 setOperationAction(ISD::VAEND , MVT::Other, Expand);
153 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
154 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
155 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
157 // We want to custom lower some of our intrinsics.
158 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
160 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
161 // They also have instructions for converting between i64 and fp.
162 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
163 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
165 // FIXME: disable this lowered code. This generates 64-bit register values,
166 // and we don't model the fact that the top part is clobbered by calls. We
167 // need to flag these together so that the value isn't live across a call.
168 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
170 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
171 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
173 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
174 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
177 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
178 // 64 bit PowerPC implementations can support i64 types directly
179 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
180 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
181 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
183 // 32 bit PowerPC wants to expand i64 shifts itself.
184 setOperationAction(ISD::SHL, MVT::i64, Custom);
185 setOperationAction(ISD::SRL, MVT::i64, Custom);
186 setOperationAction(ISD::SRA, MVT::i64, Custom);
189 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
190 // First set operation action for all vector types to expand. Then we
191 // will selectively turn on ones that can be effectively codegen'd.
192 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
193 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
194 // add/sub are legal for all supported vector VT's.
195 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
196 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
198 // We promote all shuffles to v16i8.
199 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
200 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
202 // We promote all non-typed operations to v4i32.
203 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
204 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
205 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
206 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
207 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
208 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
209 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
210 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
211 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
212 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
213 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
214 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
216 // No other operations are legal.
217 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
218 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
219 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
220 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
221 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
222 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
223 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
224 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
225 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
227 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
230 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
231 // with merges, splats, etc.
232 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
234 setOperationAction(ISD::AND , MVT::v4i32, Legal);
235 setOperationAction(ISD::OR , MVT::v4i32, Legal);
236 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
237 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
238 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
239 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
241 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
242 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
243 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
244 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
246 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
247 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
248 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
249 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
251 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
252 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
254 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
255 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
256 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
257 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
260 setSetCCResultType(MVT::i32);
261 setShiftAmountType(MVT::i32);
262 setSetCCResultContents(ZeroOrOneSetCCResult);
263 setStackPointerRegisterToSaveRestore(PPC::R1);
265 // We have target-specific dag combine patterns for the following nodes:
266 setTargetDAGCombine(ISD::SINT_TO_FP);
267 setTargetDAGCombine(ISD::STORE);
268 setTargetDAGCombine(ISD::BR_CC);
269 setTargetDAGCombine(ISD::BSWAP);
271 computeRegisterProperties();
274 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
277 case PPCISD::FSEL: return "PPCISD::FSEL";
278 case PPCISD::FCFID: return "PPCISD::FCFID";
279 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
280 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
281 case PPCISD::STFIWX: return "PPCISD::STFIWX";
282 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
283 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
284 case PPCISD::VPERM: return "PPCISD::VPERM";
285 case PPCISD::Hi: return "PPCISD::Hi";
286 case PPCISD::Lo: return "PPCISD::Lo";
287 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
288 case PPCISD::SRL: return "PPCISD::SRL";
289 case PPCISD::SRA: return "PPCISD::SRA";
290 case PPCISD::SHL: return "PPCISD::SHL";
291 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
292 case PPCISD::STD_32: return "PPCISD::STD_32";
293 case PPCISD::CALL: return "PPCISD::CALL";
294 case PPCISD::MTCTR: return "PPCISD::MTCTR";
295 case PPCISD::BCTRL: return "PPCISD::BCTRL";
296 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
297 case PPCISD::MFCR: return "PPCISD::MFCR";
298 case PPCISD::VCMP: return "PPCISD::VCMP";
299 case PPCISD::VCMPo: return "PPCISD::VCMPo";
300 case PPCISD::LBRX: return "PPCISD::LBRX";
301 case PPCISD::STBRX: return "PPCISD::STBRX";
302 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
306 //===----------------------------------------------------------------------===//
307 // Node matching predicates, for use by the tblgen matching code.
308 //===----------------------------------------------------------------------===//
310 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
311 static bool isFloatingPointZero(SDOperand Op) {
312 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
313 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
314 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
315 // Maybe this has already been legalized into the constant pool?
316 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
317 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
318 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
323 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
324 /// true if Op is undef or if it matches the specified value.
325 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
326 return Op.getOpcode() == ISD::UNDEF ||
327 cast<ConstantSDNode>(Op)->getValue() == Val;
330 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
331 /// VPKUHUM instruction.
332 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
334 for (unsigned i = 0; i != 16; ++i)
335 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
338 for (unsigned i = 0; i != 8; ++i)
339 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
340 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
346 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
347 /// VPKUWUM instruction.
348 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
350 for (unsigned i = 0; i != 16; i += 2)
351 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
352 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
355 for (unsigned i = 0; i != 8; i += 2)
356 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
357 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
358 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
359 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
365 /// isVMerge - Common function, used to match vmrg* shuffles.
367 static bool isVMerge(SDNode *N, unsigned UnitSize,
368 unsigned LHSStart, unsigned RHSStart) {
369 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
370 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
371 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
372 "Unsupported merge size!");
374 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
375 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
376 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
377 LHSStart+j+i*UnitSize) ||
378 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
379 RHSStart+j+i*UnitSize))
385 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
386 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
387 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
389 return isVMerge(N, UnitSize, 8, 24);
390 return isVMerge(N, UnitSize, 8, 8);
393 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
394 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
395 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
397 return isVMerge(N, UnitSize, 0, 16);
398 return isVMerge(N, UnitSize, 0, 0);
402 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
403 /// amount, otherwise return -1.
404 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
405 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
406 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
407 // Find the first non-undef value in the shuffle mask.
409 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
412 if (i == 16) return -1; // all undef.
414 // Otherwise, check to see if the rest of the elements are consequtively
415 // numbered from this value.
416 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
417 if (ShiftAmt < i) return -1;
421 // Check the rest of the elements to see if they are consequtive.
422 for (++i; i != 16; ++i)
423 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
426 // Check the rest of the elements to see if they are consequtive.
427 for (++i; i != 16; ++i)
428 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
435 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
436 /// specifies a splat of a single element that is suitable for input to
437 /// VSPLTB/VSPLTH/VSPLTW.
438 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
439 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
440 N->getNumOperands() == 16 &&
441 (EltSize == 1 || EltSize == 2 || EltSize == 4));
443 // This is a splat operation if each element of the permute is the same, and
444 // if the value doesn't reference the second vector.
445 unsigned ElementBase = 0;
446 SDOperand Elt = N->getOperand(0);
447 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
448 ElementBase = EltV->getValue();
450 return false; // FIXME: Handle UNDEF elements too!
452 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
455 // Check that they are consequtive.
456 for (unsigned i = 1; i != EltSize; ++i) {
457 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
458 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
462 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
463 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
464 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
465 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
466 "Invalid VECTOR_SHUFFLE mask!");
467 for (unsigned j = 0; j != EltSize; ++j)
468 if (N->getOperand(i+j) != N->getOperand(j))
475 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
476 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
477 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
478 assert(isSplatShuffleMask(N, EltSize));
479 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
482 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
483 /// by using a vspltis[bhw] instruction of the specified element size, return
484 /// the constant being splatted. The ByteSize field indicates the number of
485 /// bytes of each element [124] -> [bhw].
486 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
487 SDOperand OpVal(0, 0);
489 // If ByteSize of the splat is bigger than the element size of the
490 // build_vector, then we have a case where we are checking for a splat where
491 // multiple elements of the buildvector are folded together into a single
492 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
493 unsigned EltSize = 16/N->getNumOperands();
494 if (EltSize < ByteSize) {
495 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
496 SDOperand UniquedVals[4];
497 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
499 // See if all of the elements in the buildvector agree across.
500 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
501 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
502 // If the element isn't a constant, bail fully out.
503 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
506 if (UniquedVals[i&(Multiple-1)].Val == 0)
507 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
508 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
509 return SDOperand(); // no match.
512 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
513 // either constant or undef values that are identical for each chunk. See
514 // if these chunks can form into a larger vspltis*.
516 // Check to see if all of the leading entries are either 0 or -1. If
517 // neither, then this won't fit into the immediate field.
518 bool LeadingZero = true;
519 bool LeadingOnes = true;
520 for (unsigned i = 0; i != Multiple-1; ++i) {
521 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
523 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
524 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
526 // Finally, check the least significant entry.
528 if (UniquedVals[Multiple-1].Val == 0)
529 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
530 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
532 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
535 if (UniquedVals[Multiple-1].Val == 0)
536 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
537 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
538 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
539 return DAG.getTargetConstant(Val, MVT::i32);
545 // Check to see if this buildvec has a single non-undef value in its elements.
546 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
547 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
549 OpVal = N->getOperand(i);
550 else if (OpVal != N->getOperand(i))
554 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
556 unsigned ValSizeInBytes = 0;
558 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
559 Value = CN->getValue();
560 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
561 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
562 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
563 Value = FloatToBits(CN->getValue());
567 // If the splat value is larger than the element value, then we can never do
568 // this splat. The only case that we could fit the replicated bits into our
569 // immediate field for would be zero, and we prefer to use vxor for it.
570 if (ValSizeInBytes < ByteSize) return SDOperand();
572 // If the element value is larger than the splat value, cut it in half and
573 // check to see if the two halves are equal. Continue doing this until we
574 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
575 while (ValSizeInBytes > ByteSize) {
576 ValSizeInBytes >>= 1;
578 // If the top half equals the bottom half, we're still ok.
579 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
580 (Value & ((1 << (8*ValSizeInBytes))-1)))
584 // Properly sign extend the value.
585 int ShAmt = (4-ByteSize)*8;
586 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
588 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
589 if (MaskVal == 0) return SDOperand();
591 // Finally, if this value fits in a 5 bit sext field, return it
592 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
593 return DAG.getTargetConstant(MaskVal, MVT::i32);
597 //===----------------------------------------------------------------------===//
598 // LowerOperation implementation
599 //===----------------------------------------------------------------------===//
601 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
602 MVT::ValueType PtrVT = Op.getValueType();
603 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
604 Constant *C = CP->get();
605 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
606 SDOperand Zero = DAG.getConstant(0, PtrVT);
608 const TargetMachine &TM = DAG.getTarget();
610 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
611 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
613 // If this is a non-darwin platform, we don't support non-static relo models
615 if (TM.getRelocationModel() == Reloc::Static ||
616 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
617 // Generate non-pic code that has direct accesses to the constant pool.
618 // The address of the global is just (hi(&g)+lo(&g)).
619 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
622 if (TM.getRelocationModel() == Reloc::PIC_) {
623 // With PIC, the first instruction is actually "GR+hi(&G)".
624 Hi = DAG.getNode(ISD::ADD, PtrVT,
625 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
628 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
632 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
633 MVT::ValueType PtrVT = Op.getValueType();
634 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
635 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
636 SDOperand Zero = DAG.getConstant(0, PtrVT);
638 const TargetMachine &TM = DAG.getTarget();
640 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
641 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
643 // If this is a non-darwin platform, we don't support non-static relo models
645 if (TM.getRelocationModel() == Reloc::Static ||
646 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
647 // Generate non-pic code that has direct accesses to the constant pool.
648 // The address of the global is just (hi(&g)+lo(&g)).
649 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
652 if (TM.getRelocationModel() == Reloc::PIC_) {
653 // With PIC, the first instruction is actually "GR+hi(&G)".
654 Hi = DAG.getNode(ISD::ADD, PtrVT,
655 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
658 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
662 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
663 MVT::ValueType PtrVT = Op.getValueType();
664 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
665 GlobalValue *GV = GSDN->getGlobal();
666 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
667 SDOperand Zero = DAG.getConstant(0, PtrVT);
669 const TargetMachine &TM = DAG.getTarget();
671 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
672 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
674 // If this is a non-darwin platform, we don't support non-static relo models
676 if (TM.getRelocationModel() == Reloc::Static ||
677 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
678 // Generate non-pic code that has direct accesses to globals.
679 // The address of the global is just (hi(&g)+lo(&g)).
680 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
683 if (TM.getRelocationModel() == Reloc::PIC_) {
684 // With PIC, the first instruction is actually "GR+hi(&G)".
685 Hi = DAG.getNode(ISD::ADD, PtrVT,
686 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
689 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
691 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() &&
692 (!GV->isExternal() || GV->hasNotBeenReadFromBytecode()))
695 // If the global is weak or external, we have to go through the lazy
697 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
700 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
701 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
703 // If we're comparing for equality to zero, expose the fact that this is
704 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
705 // fold the new nodes.
706 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
707 if (C->isNullValue() && CC == ISD::SETEQ) {
708 MVT::ValueType VT = Op.getOperand(0).getValueType();
709 SDOperand Zext = Op.getOperand(0);
712 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
714 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
715 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
716 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
717 DAG.getConstant(Log2b, MVT::i32));
718 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
720 // Leave comparisons against 0 and -1 alone for now, since they're usually
721 // optimized. FIXME: revisit this when we can custom lower all setcc
723 if (C->isAllOnesValue() || C->isNullValue())
727 // If we have an integer seteq/setne, turn it into a compare against zero
728 // by subtracting the rhs from the lhs, which is faster than setting a
729 // condition register, reading it back out, and masking the correct bit.
730 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
731 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
732 MVT::ValueType VT = Op.getValueType();
733 SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0),
735 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
740 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
741 unsigned VarArgsFrameIndex) {
742 // vastart just stores the address of the VarArgsFrameIndex slot into the
743 // memory location argument.
744 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
745 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
746 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
747 Op.getOperand(1), Op.getOperand(2));
750 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
751 int &VarArgsFrameIndex) {
752 // TODO: add description of PPC stack frame format, or at least some docs.
754 MachineFunction &MF = DAG.getMachineFunction();
755 MachineFrameInfo *MFI = MF.getFrameInfo();
756 SSARegMap *RegMap = MF.getSSARegMap();
757 SmallVector<SDOperand, 8> ArgValues;
758 SDOperand Root = Op.getOperand(0);
760 unsigned ArgOffset = 24;
761 const unsigned Num_GPR_Regs = 8;
762 const unsigned Num_FPR_Regs = 13;
763 const unsigned Num_VR_Regs = 12;
764 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
766 static const unsigned GPR_32[] = { // 32-bit registers.
767 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
768 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
770 static const unsigned GPR_64[] = { // 64-bit registers.
771 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
772 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
774 static const unsigned FPR[] = {
775 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
776 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
778 static const unsigned VR[] = {
779 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
780 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
783 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
784 bool isPPC64 = PtrVT == MVT::i64;
785 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
787 // Add DAG nodes to load the arguments or copy them out of registers. On
788 // entry to a function on PPC, the arguments start at offset 24, although the
789 // first ones are often in registers.
790 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
792 bool needsLoad = false;
793 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
794 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
796 unsigned CurArgOffset = ArgOffset;
798 default: assert(0 && "Unhandled argument type!");
800 // All int arguments reserve stack space.
801 ArgOffset += isPPC64 ? 8 : 4;
803 if (GPR_idx != Num_GPR_Regs) {
804 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
805 MF.addLiveIn(GPR[GPR_idx], VReg);
806 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
812 case MVT::i64: // PPC64
813 // All int arguments reserve stack space.
816 if (GPR_idx != Num_GPR_Regs) {
817 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
818 MF.addLiveIn(GPR[GPR_idx], VReg);
819 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
827 // All FP arguments reserve stack space.
828 ArgOffset += ObjSize;
830 // Every 4 bytes of argument space consumes one of the GPRs available for
832 if (GPR_idx != Num_GPR_Regs) {
834 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs)
837 if (FPR_idx != Num_FPR_Regs) {
839 if (ObjectVT == MVT::f32)
840 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
842 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
843 MF.addLiveIn(FPR[FPR_idx], VReg);
844 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
854 // Note that vector arguments in registers don't reserve stack space.
855 if (VR_idx != Num_VR_Regs) {
856 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass);
857 MF.addLiveIn(VR[VR_idx], VReg);
858 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
861 // This should be simple, but requires getting 16-byte aligned stack
863 assert(0 && "Loading VR argument not implemented yet!");
869 // We need to load the argument to a virtual register if we determined above
870 // that we ran out of physical registers of the appropriate type
872 // If the argument is actually used, emit a load from the right stack
874 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
875 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
876 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
877 ArgVal = DAG.getLoad(ObjectVT, Root, FIN,
878 DAG.getSrcValue(NULL));
880 // Don't emit a dead load.
881 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
885 ArgValues.push_back(ArgVal);
888 // If the function takes variable number of arguments, make a frame index for
889 // the start of the first vararg value... for expansion of llvm.va_start.
890 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
892 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
894 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
895 // If this function is vararg, store any remaining integer argument regs
896 // to their spots on the stack so that they may be loaded by deferencing the
897 // result of va_next.
898 SmallVector<SDOperand, 8> MemOps;
899 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
900 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
901 MF.addLiveIn(GPR[GPR_idx], VReg);
902 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
903 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
904 Val, FIN, DAG.getSrcValue(NULL));
905 MemOps.push_back(Store);
906 // Increment the address by four for the next argument to store
907 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
908 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
911 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
914 ArgValues.push_back(Root);
916 // Return the new list of results.
917 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
918 Op.Val->value_end());
919 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
922 /// isCallCompatibleAddress - Return the immediate to use if the specified
923 /// 32-bit value is representable in the immediate field of a BxA instruction.
924 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
925 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
928 int Addr = C->getValue();
929 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
930 (Addr << 6 >> 6) != Addr)
931 return 0; // Top 6 bits have to be sext of immediate.
933 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
937 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
938 SDOperand Chain = Op.getOperand(0);
939 unsigned CallingConv= cast<ConstantSDNode>(Op.getOperand(1))->getValue();
940 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
941 bool isTailCall = cast<ConstantSDNode>(Op.getOperand(3))->getValue() != 0;
942 SDOperand Callee = Op.getOperand(4);
943 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
945 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
946 bool isPPC64 = PtrVT == MVT::i64;
947 unsigned PtrByteSize = isPPC64 ? 8 : 4;
950 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
951 // SelectExpr to use to put the arguments in the appropriate registers.
952 std::vector<SDOperand> args_to_use;
954 // Count how many bytes are to be pushed on the stack, including the linkage
955 // area, and parameter passing area. We start with 24/48 bytes, which is
956 // prereserved space for [SP][CR][LR][3 x unused].
957 unsigned NumBytes = 6*PtrByteSize;
959 // Add up all the space actually used.
960 for (unsigned i = 0; i != NumOps; ++i)
961 NumBytes += MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
963 // The prolog code of the callee may store up to 8 GPR argument registers to
964 // the stack, allowing va_start to index over them in memory if its varargs.
965 // Because we cannot tell if this is needed on the caller side, we have to
966 // conservatively assume that it is needed. As such, make sure we have at
967 // least enough stack space for the caller to store the 8 GPRs.
968 if (NumBytes < 6*PtrByteSize+8*PtrByteSize)
969 NumBytes = 6*PtrByteSize+8*PtrByteSize;
971 // Adjust the stack pointer for the new arguments...
972 // These operations are automatically eliminated by the prolog/epilog pass
973 Chain = DAG.getCALLSEQ_START(Chain,
974 DAG.getConstant(NumBytes, PtrVT));
976 // Set up a copy of the stack pointer for use loading and storing any
977 // arguments that may not fit in the registers available for argument
981 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
983 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
985 // Figure out which arguments are going to go in registers, and which in
986 // memory. Also, if this is a vararg function, floating point operations
987 // must be stored to our stack, and loaded into integer regs as well, if
988 // any integer regs are available for argument passing.
989 unsigned ArgOffset = 6*PtrByteSize;
990 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
991 static const unsigned GPR_32[] = { // 32-bit registers.
992 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
993 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
995 static const unsigned GPR_64[] = { // 64-bit registers.
996 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
997 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
999 static const unsigned FPR[] = {
1000 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1001 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1003 static const unsigned VR[] = {
1004 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1005 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1007 const unsigned NumGPRs = sizeof(GPR_32)/sizeof(GPR_32[0]);
1008 const unsigned NumFPRs = sizeof(FPR)/sizeof(FPR[0]);
1009 const unsigned NumVRs = sizeof( VR)/sizeof( VR[0]);
1011 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1013 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1014 SmallVector<SDOperand, 8> MemOpChains;
1015 for (unsigned i = 0; i != NumOps; ++i) {
1016 SDOperand Arg = Op.getOperand(5+2*i);
1018 // PtrOff will be used to store the current argument to the stack if a
1019 // register cannot be found for it.
1020 SDOperand PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1021 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1023 // On PPC64, promote integers to 64-bit values.
1024 if (isPPC64 && Arg.getValueType() == MVT::i32) {
1025 unsigned ExtOp = ISD::ZERO_EXTEND;
1026 if (cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue())
1027 ExtOp = ISD::SIGN_EXTEND;
1028 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1031 switch (Arg.getValueType()) {
1032 default: assert(0 && "Unexpected ValueType for argument!");
1035 if (GPR_idx != NumGPRs) {
1036 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
1038 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1039 Arg, PtrOff, DAG.getSrcValue(NULL)));
1041 ArgOffset += PtrByteSize;
1045 if (FPR_idx != NumFPRs) {
1046 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1049 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
1051 DAG.getSrcValue(NULL));
1052 MemOpChains.push_back(Store);
1054 // Float varargs are always shadowed in available integer registers
1055 if (GPR_idx != NumGPRs) {
1056 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff,
1057 DAG.getSrcValue(NULL));
1058 MemOpChains.push_back(Load.getValue(1));
1059 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1061 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64) {
1062 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1063 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
1064 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff,
1065 DAG.getSrcValue(NULL));
1066 MemOpChains.push_back(Load.getValue(1));
1067 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1070 // If we have any FPRs remaining, we may also have GPRs remaining.
1071 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1073 if (GPR_idx != NumGPRs)
1075 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64)
1079 MemOpChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1080 Arg, PtrOff, DAG.getSrcValue(NULL)));
1085 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1091 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1092 assert(VR_idx != NumVRs &&
1093 "Don't support passing more than 12 vector args yet!");
1094 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1098 if (!MemOpChains.empty())
1099 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1100 &MemOpChains[0], MemOpChains.size());
1102 // Build a sequence of copy-to-reg nodes chained together with token chain
1103 // and flag operands which copy the outgoing args into the appropriate regs.
1105 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1106 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1108 InFlag = Chain.getValue(1);
1111 std::vector<MVT::ValueType> NodeTys;
1112 NodeTys.push_back(MVT::Other); // Returns a chain
1113 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1115 SmallVector<SDOperand, 8> Ops;
1116 unsigned CallOpc = PPCISD::CALL;
1118 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1119 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1120 // node so that legalize doesn't hack it.
1121 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1122 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1123 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1124 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1125 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1126 // If this is an absolute destination address, use the munged value.
1127 Callee = SDOperand(Dest, 0);
1129 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1130 // to do the call, we can't use PPCISD::CALL.
1131 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
1132 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
1133 InFlag = Chain.getValue(1);
1135 // Copy the callee address into R12 on darwin.
1136 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1137 InFlag = Chain.getValue(1);
1140 NodeTys.push_back(MVT::Other);
1141 NodeTys.push_back(MVT::Flag);
1142 Ops.push_back(Chain);
1143 CallOpc = PPCISD::BCTRL;
1147 // If this is a direct call, pass the chain and the callee.
1149 Ops.push_back(Chain);
1150 Ops.push_back(Callee);
1153 // Add argument registers to the end of the list so that they are known live
1155 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1156 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1157 RegsToPass[i].second.getValueType()));
1160 Ops.push_back(InFlag);
1161 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
1162 InFlag = Chain.getValue(1);
1164 SDOperand ResultVals[3];
1165 unsigned NumResults = 0;
1168 // If the call has results, copy the values out of the ret val registers.
1169 switch (Op.Val->getValueType(0)) {
1170 default: assert(0 && "Unexpected ret value!");
1171 case MVT::Other: break;
1173 if (Op.Val->getValueType(1) == MVT::i32) {
1174 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32, InFlag).getValue(1);
1175 ResultVals[0] = Chain.getValue(0);
1176 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32,
1177 Chain.getValue(2)).getValue(1);
1178 ResultVals[1] = Chain.getValue(0);
1180 NodeTys.push_back(MVT::i32);
1182 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1183 ResultVals[0] = Chain.getValue(0);
1186 NodeTys.push_back(MVT::i32);
1189 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
1190 ResultVals[0] = Chain.getValue(0);
1192 NodeTys.push_back(MVT::i64);
1196 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1197 InFlag).getValue(1);
1198 ResultVals[0] = Chain.getValue(0);
1200 NodeTys.push_back(Op.Val->getValueType(0));
1206 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1207 InFlag).getValue(1);
1208 ResultVals[0] = Chain.getValue(0);
1210 NodeTys.push_back(Op.Val->getValueType(0));
1214 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1215 DAG.getConstant(NumBytes, PtrVT));
1216 NodeTys.push_back(MVT::Other);
1218 // If the function returns void, just return the chain.
1219 if (NumResults == 1)
1222 // Otherwise, merge everything together with a MERGE_VALUES node.
1223 ResultVals[NumResults++] = Chain;
1224 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1225 ResultVals, NumResults);
1226 return Res.getValue(Op.ResNo);
1229 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
1231 switch(Op.getNumOperands()) {
1233 assert(0 && "Do not know how to return this many arguments!");
1236 return SDOperand(); // ret void is legal
1238 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
1240 if (ArgVT == MVT::i32) {
1242 } else if (ArgVT == MVT::i64) {
1244 } else if (MVT::isVector(ArgVT)) {
1247 assert(MVT::isFloatingPoint(ArgVT));
1251 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
1254 // If we haven't noted the R3/F1 are live out, do so now.
1255 if (DAG.getMachineFunction().liveout_empty())
1256 DAG.getMachineFunction().addLiveOut(ArgReg);
1260 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(3),
1262 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
1263 // If we haven't noted the R3+R4 are live out, do so now.
1264 if (DAG.getMachineFunction().liveout_empty()) {
1265 DAG.getMachineFunction().addLiveOut(PPC::R3);
1266 DAG.getMachineFunction().addLiveOut(PPC::R4);
1270 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
1273 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
1275 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
1276 // Not FP? Not a fsel.
1277 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
1278 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
1281 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1283 // Cannot handle SETEQ/SETNE.
1284 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
1286 MVT::ValueType ResVT = Op.getValueType();
1287 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
1288 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1289 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
1291 // If the RHS of the comparison is a 0.0, we don't need to do the
1292 // subtraction at all.
1293 if (isFloatingPointZero(RHS))
1295 default: break; // SETUO etc aren't handled by fsel.
1299 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1303 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1304 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1305 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
1309 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1313 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1314 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1315 return DAG.getNode(PPCISD::FSEL, ResVT,
1316 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
1321 default: break; // SETUO etc aren't handled by fsel.
1325 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1326 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1327 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1328 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1332 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
1333 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1334 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1335 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1339 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1340 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1341 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1342 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
1346 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
1347 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
1348 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
1349 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
1354 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
1355 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
1356 SDOperand Src = Op.getOperand(0);
1357 if (Src.getValueType() == MVT::f32)
1358 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
1361 switch (Op.getValueType()) {
1362 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
1364 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
1367 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
1371 // Convert the FP value to an int value through memory.
1372 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
1373 if (Op.getValueType() == MVT::i32)
1374 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
1378 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
1379 if (Op.getOperand(0).getValueType() == MVT::i64) {
1380 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
1381 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
1382 if (Op.getValueType() == MVT::f32)
1383 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1387 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
1388 "Unhandled SINT_TO_FP type in custom expander!");
1389 // Since we only generate this in 64-bit mode, we can take advantage of
1390 // 64-bit registers. In particular, sign extend the input value into the
1391 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
1392 // then lfd it and fcfid it.
1393 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
1394 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
1395 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1396 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
1398 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
1401 // STD the extended value into the stack slot.
1402 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
1403 DAG.getEntryNode(), Ext64, FIdx,
1404 DAG.getSrcValue(NULL));
1405 // Load the value as a double.
1406 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL));
1408 // FCFID it and return it.
1409 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
1410 if (Op.getValueType() == MVT::f32)
1411 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
1415 static SDOperand LowerSHL(SDOperand Op, SelectionDAG &DAG,
1416 MVT::ValueType PtrVT) {
1417 assert(Op.getValueType() == MVT::i64 &&
1418 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
1419 // The generic code does a fine job expanding shift by a constant.
1420 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
1422 // Otherwise, expand into a bunch of logical ops. Note that these ops
1423 // depend on the PPC behavior for oversized shift amounts.
1424 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1425 DAG.getConstant(0, PtrVT));
1426 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1427 DAG.getConstant(1, PtrVT));
1428 SDOperand Amt = Op.getOperand(1);
1430 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1431 DAG.getConstant(32, MVT::i32), Amt);
1432 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
1433 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
1434 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1435 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1436 DAG.getConstant(-32U, MVT::i32));
1437 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
1438 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1439 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
1440 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
1443 static SDOperand LowerSRL(SDOperand Op, SelectionDAG &DAG,
1444 MVT::ValueType PtrVT) {
1445 assert(Op.getValueType() == MVT::i64 &&
1446 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
1447 // The generic code does a fine job expanding shift by a constant.
1448 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
1450 // Otherwise, expand into a bunch of logical ops. Note that these ops
1451 // depend on the PPC behavior for oversized shift amounts.
1452 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1453 DAG.getConstant(0, PtrVT));
1454 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1455 DAG.getConstant(1, PtrVT));
1456 SDOperand Amt = Op.getOperand(1);
1458 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1459 DAG.getConstant(32, MVT::i32), Amt);
1460 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1461 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1462 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1463 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1464 DAG.getConstant(-32U, MVT::i32));
1465 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
1466 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
1467 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
1468 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
1471 static SDOperand LowerSRA(SDOperand Op, SelectionDAG &DAG,
1472 MVT::ValueType PtrVT) {
1473 assert(Op.getValueType() == MVT::i64 &&
1474 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
1475 // The generic code does a fine job expanding shift by a constant.
1476 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
1478 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
1479 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1480 DAG.getConstant(0, PtrVT));
1481 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
1482 DAG.getConstant(1, PtrVT));
1483 SDOperand Amt = Op.getOperand(1);
1485 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
1486 DAG.getConstant(32, MVT::i32), Amt);
1487 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
1488 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
1489 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
1490 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
1491 DAG.getConstant(-32U, MVT::i32));
1492 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
1493 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
1494 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
1495 Tmp4, Tmp6, ISD::SETLE);
1496 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
1499 //===----------------------------------------------------------------------===//
1500 // Vector related lowering.
1503 // If this is a vector of constants or undefs, get the bits. A bit in
1504 // UndefBits is set if the corresponding element of the vector is an
1505 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1506 // zero. Return true if this is not an array of constants, false if it is.
1508 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
1509 uint64_t UndefBits[2]) {
1510 // Start with zero'd results.
1511 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
1513 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
1514 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
1515 SDOperand OpVal = BV->getOperand(i);
1517 unsigned PartNo = i >= e/2; // In the upper 128 bits?
1518 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
1520 uint64_t EltBits = 0;
1521 if (OpVal.getOpcode() == ISD::UNDEF) {
1522 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
1523 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
1525 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1526 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
1527 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1528 assert(CN->getValueType(0) == MVT::f32 &&
1529 "Only one legal FP vector type!");
1530 EltBits = FloatToBits(CN->getValue());
1532 // Nonconstant element.
1536 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
1539 //printf("%llx %llx %llx %llx\n",
1540 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
1544 // If this is a splat (repetition) of a value across the whole vector, return
1545 // the smallest size that splats it. For example, "0x01010101010101..." is a
1546 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1547 // SplatSize = 1 byte.
1548 static bool isConstantSplat(const uint64_t Bits128[2],
1549 const uint64_t Undef128[2],
1550 unsigned &SplatBits, unsigned &SplatUndef,
1551 unsigned &SplatSize) {
1553 // Don't let undefs prevent splats from matching. See if the top 64-bits are
1554 // the same as the lower 64-bits, ignoring undefs.
1555 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
1556 return false; // Can't be a splat if two pieces don't match.
1558 uint64_t Bits64 = Bits128[0] | Bits128[1];
1559 uint64_t Undef64 = Undef128[0] & Undef128[1];
1561 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
1563 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
1564 return false; // Can't be a splat if two pieces don't match.
1566 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
1567 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
1569 // If the top 16-bits are different than the lower 16-bits, ignoring
1570 // undefs, we have an i32 splat.
1571 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
1573 SplatUndef = Undef32;
1578 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
1579 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
1581 // If the top 8-bits are different than the lower 8-bits, ignoring
1582 // undefs, we have an i16 splat.
1583 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
1585 SplatUndef = Undef16;
1590 // Otherwise, we have an 8-bit splat.
1591 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
1592 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
1597 /// BuildSplatI - Build a canonical splati of Val with an element size of
1598 /// SplatSize. Cast the result to VT.
1599 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
1600 SelectionDAG &DAG) {
1601 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
1603 // Force vspltis[hw] -1 to vspltisb -1.
1604 if (Val == -1) SplatSize = 1;
1606 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
1607 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
1609 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
1611 // Build a canonical splat for this value.
1612 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT));
1613 SmallVector<SDOperand, 8> Ops;
1614 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
1615 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
1616 &Ops[0], Ops.size());
1617 return DAG.getNode(ISD::BIT_CONVERT, VT, Res);
1620 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
1621 /// specified intrinsic ID.
1622 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
1624 MVT::ValueType DestVT = MVT::Other) {
1625 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
1626 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1627 DAG.getConstant(IID, MVT::i32), LHS, RHS);
1630 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
1631 /// specified intrinsic ID.
1632 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
1633 SDOperand Op2, SelectionDAG &DAG,
1634 MVT::ValueType DestVT = MVT::Other) {
1635 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
1636 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
1637 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
1641 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
1642 /// amount. The result has the specified value type.
1643 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
1644 MVT::ValueType VT, SelectionDAG &DAG) {
1645 // Force LHS/RHS to be the right type.
1646 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
1647 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
1650 for (unsigned i = 0; i != 16; ++i)
1651 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
1652 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
1653 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
1654 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
1657 // If this is a case we can't handle, return null and let the default
1658 // expansion code take care of it. If we CAN select this case, and if it
1659 // selects to a single instruction, return Op. Otherwise, if we can codegen
1660 // this case more efficiently than a constant pool load, lower it to the
1661 // sequence of ops that should be used.
1662 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
1663 // If this is a vector of constants or undefs, get the bits. A bit in
1664 // UndefBits is set if the corresponding element of the vector is an
1665 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1667 uint64_t VectorBits[2];
1668 uint64_t UndefBits[2];
1669 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
1670 return SDOperand(); // Not a constant vector.
1672 // If this is a splat (repetition) of a value across the whole vector, return
1673 // the smallest size that splats it. For example, "0x01010101010101..." is a
1674 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1675 // SplatSize = 1 byte.
1676 unsigned SplatBits, SplatUndef, SplatSize;
1677 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
1678 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
1680 // First, handle single instruction cases.
1683 if (SplatBits == 0) {
1684 // Canonicalize all zero vectors to be v4i32.
1685 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
1686 SDOperand Z = DAG.getConstant(0, MVT::i32);
1687 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
1688 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
1693 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
1694 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
1695 if (SextVal >= -16 && SextVal <= 15)
1696 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
1699 // Two instruction sequences.
1701 // If this value is in the range [-32,30] and is even, use:
1702 // tmp = VSPLTI[bhw], result = add tmp, tmp
1703 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
1704 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
1705 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
1708 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
1709 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
1711 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
1712 // Make -1 and vspltisw -1:
1713 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
1715 // Make the VSLW intrinsic, computing 0x8000_0000.
1716 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
1719 // xor by OnesV to invert it.
1720 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
1721 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
1724 // Check to see if this is a wide variety of vsplti*, binop self cases.
1725 unsigned SplatBitSize = SplatSize*8;
1726 static const char SplatCsts[] = {
1727 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
1728 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
1730 for (unsigned idx = 0; idx < sizeof(SplatCsts)/sizeof(SplatCsts[0]); ++idx){
1731 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
1732 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
1733 int i = SplatCsts[idx];
1735 // Figure out what shift amount will be used by altivec if shifted by i in
1737 unsigned TypeShiftAmt = i & (SplatBitSize-1);
1739 // vsplti + shl self.
1740 if (SextVal == (i << (int)TypeShiftAmt)) {
1741 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1742 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1743 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
1744 Intrinsic::ppc_altivec_vslw
1746 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1749 // vsplti + srl self.
1750 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
1751 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1752 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1753 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
1754 Intrinsic::ppc_altivec_vsrw
1756 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1759 // vsplti + sra self.
1760 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
1761 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1762 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1763 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
1764 Intrinsic::ppc_altivec_vsraw
1766 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1769 // vsplti + rol self.
1770 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
1771 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
1772 Op = BuildSplatI(i, SplatSize, Op.getValueType(), DAG);
1773 static const unsigned IIDs[] = { // Intrinsic to use for each size.
1774 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
1775 Intrinsic::ppc_altivec_vrlw
1777 return BuildIntrinsicOp(IIDs[SplatSize-1], Op, Op, DAG);
1780 // t = vsplti c, result = vsldoi t, t, 1
1781 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
1782 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1783 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
1785 // t = vsplti c, result = vsldoi t, t, 2
1786 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
1787 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1788 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
1790 // t = vsplti c, result = vsldoi t, t, 3
1791 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
1792 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
1793 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
1797 // Three instruction sequences.
1799 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
1800 if (SextVal >= 0 && SextVal <= 31) {
1801 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, Op.getValueType(),DAG);
1802 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
1803 return DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
1805 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
1806 if (SextVal >= -31 && SextVal <= 0) {
1807 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, Op.getValueType(),DAG);
1808 SDOperand RHS = BuildSplatI(-16, SplatSize, Op.getValueType(), DAG);
1809 return DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
1816 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
1817 /// the specified operations to build the shuffle.
1818 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
1819 SDOperand RHS, SelectionDAG &DAG) {
1820 unsigned OpNum = (PFEntry >> 26) & 0x0F;
1821 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
1822 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
1825 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
1837 if (OpNum == OP_COPY) {
1838 if (LHSID == (1*9+2)*9+3) return LHS;
1839 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
1843 SDOperand OpLHS, OpRHS;
1844 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
1845 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
1847 unsigned ShufIdxs[16];
1849 default: assert(0 && "Unknown i32 permute!");
1851 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
1852 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
1853 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
1854 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
1857 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
1858 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
1859 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
1860 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
1863 for (unsigned i = 0; i != 16; ++i)
1864 ShufIdxs[i] = (i&3)+0;
1867 for (unsigned i = 0; i != 16; ++i)
1868 ShufIdxs[i] = (i&3)+4;
1871 for (unsigned i = 0; i != 16; ++i)
1872 ShufIdxs[i] = (i&3)+8;
1875 for (unsigned i = 0; i != 16; ++i)
1876 ShufIdxs[i] = (i&3)+12;
1879 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
1881 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
1883 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
1886 for (unsigned i = 0; i != 16; ++i)
1887 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
1889 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
1890 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
1893 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
1894 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
1895 /// return the code it can be lowered into. Worst case, it can always be
1896 /// lowered into a vperm.
1897 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
1898 SDOperand V1 = Op.getOperand(0);
1899 SDOperand V2 = Op.getOperand(1);
1900 SDOperand PermMask = Op.getOperand(2);
1902 // Cases that are handled by instructions that take permute immediates
1903 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
1904 // selected by the instruction selector.
1905 if (V2.getOpcode() == ISD::UNDEF) {
1906 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
1907 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
1908 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
1909 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
1910 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
1911 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
1912 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
1913 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
1914 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
1915 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
1916 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
1917 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
1922 // Altivec has a variety of "shuffle immediates" that take two vector inputs
1923 // and produce a fixed permutation. If any of these match, do not lower to
1925 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
1926 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
1927 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
1928 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
1929 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
1930 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
1931 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
1932 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
1933 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
1936 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
1937 // perfect shuffle table to emit an optimal matching sequence.
1938 unsigned PFIndexes[4];
1939 bool isFourElementShuffle = true;
1940 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
1941 unsigned EltNo = 8; // Start out undef.
1942 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
1943 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
1944 continue; // Undef, ignore it.
1946 unsigned ByteSource =
1947 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
1948 if ((ByteSource & 3) != j) {
1949 isFourElementShuffle = false;
1954 EltNo = ByteSource/4;
1955 } else if (EltNo != ByteSource/4) {
1956 isFourElementShuffle = false;
1960 PFIndexes[i] = EltNo;
1963 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
1964 // perfect shuffle vector to determine if it is cost effective to do this as
1965 // discrete instructions, or whether we should use a vperm.
1966 if (isFourElementShuffle) {
1967 // Compute the index in the perfect shuffle table.
1968 unsigned PFTableIndex =
1969 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
1971 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
1972 unsigned Cost = (PFEntry >> 30);
1974 // Determining when to avoid vperm is tricky. Many things affect the cost
1975 // of vperm, particularly how many times the perm mask needs to be computed.
1976 // For example, if the perm mask can be hoisted out of a loop or is already
1977 // used (perhaps because there are multiple permutes with the same shuffle
1978 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
1979 // the loop requires an extra register.
1981 // As a compromise, we only emit discrete instructions if the shuffle can be
1982 // generated in 3 or fewer operations. When we have loop information
1983 // available, if this block is within a loop, we should avoid using vperm
1984 // for 3-operation perms and use a constant pool load instead.
1986 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
1989 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
1990 // vector that will get spilled to the constant pool.
1991 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
1993 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
1994 // that it is in input element units, not in bytes. Convert now.
1995 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
1996 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
1998 SmallVector<SDOperand, 16> ResultMask;
1999 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
2001 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
2004 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
2006 for (unsigned j = 0; j != BytesPerElement; ++j)
2007 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
2011 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
2012 &ResultMask[0], ResultMask.size());
2013 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
2016 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
2017 /// altivec comparison. If it is, return true and fill in Opc/isDot with
2018 /// information about the intrinsic.
2019 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
2021 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
2024 switch (IntrinsicID) {
2025 default: return false;
2026 // Comparison predicates.
2027 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
2028 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
2029 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
2030 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
2031 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
2032 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
2033 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
2034 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
2035 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
2036 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
2037 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
2038 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
2039 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
2041 // Normal Comparisons.
2042 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
2043 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
2044 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
2045 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
2046 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
2047 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
2048 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
2049 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
2050 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
2051 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
2052 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
2053 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
2054 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
2059 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
2060 /// lower, do it, otherwise return null.
2061 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
2062 // If this is a lowered altivec predicate compare, CompareOpc is set to the
2063 // opcode number of the comparison.
2066 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
2067 return SDOperand(); // Don't custom lower most intrinsics.
2069 // If this is a non-dot comparison, make the VCMP node and we are done.
2071 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
2072 Op.getOperand(1), Op.getOperand(2),
2073 DAG.getConstant(CompareOpc, MVT::i32));
2074 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
2077 // Create the PPCISD altivec 'dot' comparison node.
2079 Op.getOperand(2), // LHS
2080 Op.getOperand(3), // RHS
2081 DAG.getConstant(CompareOpc, MVT::i32)
2083 std::vector<MVT::ValueType> VTs;
2084 VTs.push_back(Op.getOperand(2).getValueType());
2085 VTs.push_back(MVT::Flag);
2086 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2088 // Now that we have the comparison, emit a copy from the CR to a GPR.
2089 // This is flagged to the above dot comparison.
2090 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
2091 DAG.getRegister(PPC::CR6, MVT::i32),
2092 CompNode.getValue(1));
2094 // Unpack the result based on how the target uses it.
2095 unsigned BitNo; // Bit # of CR6.
2096 bool InvertBit; // Invert result?
2097 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
2098 default: // Can't happen, don't crash on invalid number though.
2099 case 0: // Return the value of the EQ bit of CR6.
2100 BitNo = 0; InvertBit = false;
2102 case 1: // Return the inverted value of the EQ bit of CR6.
2103 BitNo = 0; InvertBit = true;
2105 case 2: // Return the value of the LT bit of CR6.
2106 BitNo = 2; InvertBit = false;
2108 case 3: // Return the inverted value of the LT bit of CR6.
2109 BitNo = 2; InvertBit = true;
2113 // Shift the bit into the low position.
2114 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
2115 DAG.getConstant(8-(3-BitNo), MVT::i32));
2117 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
2118 DAG.getConstant(1, MVT::i32));
2120 // If we are supposed to, toggle the bit.
2122 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
2123 DAG.getConstant(1, MVT::i32));
2127 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2128 // Create a stack slot that is 16-byte aligned.
2129 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2130 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
2131 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2132 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2134 // Store the input value into Value#0 of the stack slot.
2135 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
2136 Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
2138 return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL));
2141 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
2142 if (Op.getValueType() == MVT::v4i32) {
2143 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2145 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
2146 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
2148 SDOperand RHSSwap = // = vrlw RHS, 16
2149 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
2151 // Shrinkify inputs to v8i16.
2152 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
2153 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
2154 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
2156 // Low parts multiplied together, generating 32-bit results (we ignore the
2158 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
2159 LHS, RHS, DAG, MVT::v4i32);
2161 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
2162 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
2163 // Shift the high parts up 16 bits.
2164 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
2165 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
2166 } else if (Op.getValueType() == MVT::v8i16) {
2167 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2169 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
2171 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
2172 LHS, RHS, Zero, DAG);
2173 } else if (Op.getValueType() == MVT::v16i8) {
2174 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2176 // Multiply the even 8-bit parts, producing 16-bit sums.
2177 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
2178 LHS, RHS, DAG, MVT::v8i16);
2179 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
2181 // Multiply the odd 8-bit parts, producing 16-bit sums.
2182 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
2183 LHS, RHS, DAG, MVT::v8i16);
2184 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
2186 // Merge the results together.
2188 for (unsigned i = 0; i != 8; ++i) {
2189 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
2190 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
2192 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
2193 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2195 assert(0 && "Unknown mul to lower!");
2200 /// LowerOperation - Provide custom lowering hooks for some operations.
2202 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2203 switch (Op.getOpcode()) {
2204 default: assert(0 && "Wasn't expecting to be able to lower this!");
2205 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2206 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2207 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2208 case ISD::SETCC: return LowerSETCC(Op, DAG);
2209 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
2210 case ISD::FORMAL_ARGUMENTS:
2211 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex);
2212 case ISD::CALL: return LowerCALL(Op, DAG);
2213 case ISD::RET: return LowerRET(Op, DAG);
2215 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2216 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
2217 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
2219 // Lower 64-bit shifts.
2220 case ISD::SHL: return LowerSHL(Op, DAG, getPointerTy());
2221 case ISD::SRL: return LowerSRL(Op, DAG, getPointerTy());
2222 case ISD::SRA: return LowerSRA(Op, DAG, getPointerTy());
2224 // Vector-related lowering.
2225 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2226 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2227 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2228 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2229 case ISD::MUL: return LowerMUL(Op, DAG);
2234 //===----------------------------------------------------------------------===//
2235 // Other Lowering Code
2236 //===----------------------------------------------------------------------===//
2239 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2240 MachineBasicBlock *BB) {
2241 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
2242 MI->getOpcode() == PPC::SELECT_CC_I8 ||
2243 MI->getOpcode() == PPC::SELECT_CC_F4 ||
2244 MI->getOpcode() == PPC::SELECT_CC_F8 ||
2245 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
2246 "Unexpected instr type to insert");
2248 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2249 // control-flow pattern. The incoming instruction knows the destination vreg
2250 // to set, the condition code register to branch on, the true/false values to
2251 // select between, and a branch opcode to use.
2252 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2253 ilist<MachineBasicBlock>::iterator It = BB;
2259 // cmpTY ccX, r1, r2
2261 // fallthrough --> copy0MBB
2262 MachineBasicBlock *thisMBB = BB;
2263 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2264 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2265 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
2266 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
2267 MachineFunction *F = BB->getParent();
2268 F->getBasicBlockList().insert(It, copy0MBB);
2269 F->getBasicBlockList().insert(It, sinkMBB);
2270 // Update machine-CFG edges by first adding all successors of the current
2271 // block to the new block which will contain the Phi node for the select.
2272 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2273 e = BB->succ_end(); i != e; ++i)
2274 sinkMBB->addSuccessor(*i);
2275 // Next, remove all successors of the current block, and add the true
2276 // and fallthrough blocks as its successors.
2277 while(!BB->succ_empty())
2278 BB->removeSuccessor(BB->succ_begin());
2279 BB->addSuccessor(copy0MBB);
2280 BB->addSuccessor(sinkMBB);
2283 // %FalseValue = ...
2284 // # fallthrough to sinkMBB
2287 // Update machine-CFG edges
2288 BB->addSuccessor(sinkMBB);
2291 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2294 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
2295 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
2296 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2298 delete MI; // The pseudo instruction is gone now.
2302 //===----------------------------------------------------------------------===//
2303 // Target Optimization Hooks
2304 //===----------------------------------------------------------------------===//
2306 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
2307 DAGCombinerInfo &DCI) const {
2308 TargetMachine &TM = getTargetMachine();
2309 SelectionDAG &DAG = DCI.DAG;
2310 switch (N->getOpcode()) {
2312 case ISD::SINT_TO_FP:
2313 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
2314 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
2315 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
2316 // We allow the src/dst to be either f32/f64, but the intermediate
2317 // type must be i64.
2318 if (N->getOperand(0).getValueType() == MVT::i64) {
2319 SDOperand Val = N->getOperand(0).getOperand(0);
2320 if (Val.getValueType() == MVT::f32) {
2321 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2322 DCI.AddToWorklist(Val.Val);
2325 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
2326 DCI.AddToWorklist(Val.Val);
2327 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
2328 DCI.AddToWorklist(Val.Val);
2329 if (N->getValueType(0) == MVT::f32) {
2330 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
2331 DCI.AddToWorklist(Val.Val);
2334 } else if (N->getOperand(0).getValueType() == MVT::i32) {
2335 // If the intermediate type is i32, we can avoid the load/store here
2342 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
2343 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
2344 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
2345 N->getOperand(1).getValueType() == MVT::i32) {
2346 SDOperand Val = N->getOperand(1).getOperand(0);
2347 if (Val.getValueType() == MVT::f32) {
2348 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
2349 DCI.AddToWorklist(Val.Val);
2351 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
2352 DCI.AddToWorklist(Val.Val);
2354 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
2355 N->getOperand(2), N->getOperand(3));
2356 DCI.AddToWorklist(Val.Val);
2360 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
2361 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
2362 N->getOperand(1).Val->hasOneUse() &&
2363 (N->getOperand(1).getValueType() == MVT::i32 ||
2364 N->getOperand(1).getValueType() == MVT::i16)) {
2365 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
2366 // Do an any-extend to 32-bits if this is a half-word input.
2367 if (BSwapOp.getValueType() == MVT::i16)
2368 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
2370 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
2371 N->getOperand(2), N->getOperand(3),
2372 DAG.getValueType(N->getOperand(1).getValueType()));
2376 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
2377 if (N->getOperand(0).getOpcode() == ISD::LOAD &&
2378 N->getOperand(0).hasOneUse() &&
2379 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
2380 SDOperand Load = N->getOperand(0);
2381 // Create the byte-swapping load.
2382 std::vector<MVT::ValueType> VTs;
2383 VTs.push_back(MVT::i32);
2384 VTs.push_back(MVT::Other);
2386 Load.getOperand(0), // Chain
2387 Load.getOperand(1), // Ptr
2388 Load.getOperand(2), // SrcValue
2389 DAG.getValueType(N->getValueType(0)) // VT
2391 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
2393 // If this is an i16 load, insert the truncate.
2394 SDOperand ResVal = BSLoad;
2395 if (N->getValueType(0) == MVT::i16)
2396 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
2398 // First, combine the bswap away. This makes the value produced by the
2400 DCI.CombineTo(N, ResVal);
2402 // Next, combine the load away, we give it a bogus result value but a real
2403 // chain result. The result value is dead because the bswap is dead.
2404 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
2406 // Return N so it doesn't get rechecked!
2407 return SDOperand(N, 0);
2411 case PPCISD::VCMP: {
2412 // If a VCMPo node already exists with exactly the same operands as this
2413 // node, use its result instead of this node (VCMPo computes both a CR6 and
2414 // a normal output).
2416 if (!N->getOperand(0).hasOneUse() &&
2417 !N->getOperand(1).hasOneUse() &&
2418 !N->getOperand(2).hasOneUse()) {
2420 // Scan all of the users of the LHS, looking for VCMPo's that match.
2421 SDNode *VCMPoNode = 0;
2423 SDNode *LHSN = N->getOperand(0).Val;
2424 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
2426 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
2427 (*UI)->getOperand(1) == N->getOperand(1) &&
2428 (*UI)->getOperand(2) == N->getOperand(2) &&
2429 (*UI)->getOperand(0) == N->getOperand(0)) {
2434 // If there is no VCMPo node, or if the flag value has a single use, don't
2436 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
2439 // Look at the (necessarily single) use of the flag value. If it has a
2440 // chain, this transformation is more complex. Note that multiple things
2441 // could use the value result, which we should ignore.
2442 SDNode *FlagUser = 0;
2443 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
2444 FlagUser == 0; ++UI) {
2445 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
2447 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
2448 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
2455 // If the user is a MFCR instruction, we know this is safe. Otherwise we
2456 // give up for right now.
2457 if (FlagUser->getOpcode() == PPCISD::MFCR)
2458 return SDOperand(VCMPoNode, 0);
2463 // If this is a branch on an altivec predicate comparison, lower this so
2464 // that we don't have to do a MFCR: instead, branch directly on CR6. This
2465 // lowering is done pre-legalize, because the legalizer lowers the predicate
2466 // compare down to code that is difficult to reassemble.
2467 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
2468 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
2472 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2473 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
2474 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
2475 assert(isDot && "Can't compare against a vector result!");
2477 // If this is a comparison against something other than 0/1, then we know
2478 // that the condition is never/always true.
2479 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
2480 if (Val != 0 && Val != 1) {
2481 if (CC == ISD::SETEQ) // Cond never true, remove branch.
2482 return N->getOperand(0);
2483 // Always !=, turn it into an unconditional branch.
2484 return DAG.getNode(ISD::BR, MVT::Other,
2485 N->getOperand(0), N->getOperand(4));
2488 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
2490 // Create the PPCISD altivec 'dot' comparison node.
2491 std::vector<MVT::ValueType> VTs;
2493 LHS.getOperand(2), // LHS of compare
2494 LHS.getOperand(3), // RHS of compare
2495 DAG.getConstant(CompareOpc, MVT::i32)
2497 VTs.push_back(LHS.getOperand(2).getValueType());
2498 VTs.push_back(MVT::Flag);
2499 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2501 // Unpack the result based on how the target uses it.
2503 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
2504 default: // Can't happen, don't crash on invalid number though.
2505 case 0: // Branch on the value of the EQ bit of CR6.
2506 CompOpc = BranchOnWhenPredTrue ? PPC::BEQ : PPC::BNE;
2508 case 1: // Branch on the inverted value of the EQ bit of CR6.
2509 CompOpc = BranchOnWhenPredTrue ? PPC::BNE : PPC::BEQ;
2511 case 2: // Branch on the value of the LT bit of CR6.
2512 CompOpc = BranchOnWhenPredTrue ? PPC::BLT : PPC::BGE;
2514 case 3: // Branch on the inverted value of the LT bit of CR6.
2515 CompOpc = BranchOnWhenPredTrue ? PPC::BGE : PPC::BLT;
2519 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
2520 DAG.getRegister(PPC::CR6, MVT::i32),
2521 DAG.getConstant(CompOpc, MVT::i32),
2522 N->getOperand(4), CompNode.getValue(1));
2531 //===----------------------------------------------------------------------===//
2532 // Inline Assembly Support
2533 //===----------------------------------------------------------------------===//
2535 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
2537 uint64_t &KnownZero,
2539 unsigned Depth) const {
2542 switch (Op.getOpcode()) {
2544 case PPCISD::LBRX: {
2545 // lhbrx is known to have the top bits cleared out.
2546 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
2547 KnownZero = 0xFFFF0000;
2550 case ISD::INTRINSIC_WO_CHAIN: {
2551 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
2553 case Intrinsic::ppc_altivec_vcmpbfp_p:
2554 case Intrinsic::ppc_altivec_vcmpeqfp_p:
2555 case Intrinsic::ppc_altivec_vcmpequb_p:
2556 case Intrinsic::ppc_altivec_vcmpequh_p:
2557 case Intrinsic::ppc_altivec_vcmpequw_p:
2558 case Intrinsic::ppc_altivec_vcmpgefp_p:
2559 case Intrinsic::ppc_altivec_vcmpgtfp_p:
2560 case Intrinsic::ppc_altivec_vcmpgtsb_p:
2561 case Intrinsic::ppc_altivec_vcmpgtsh_p:
2562 case Intrinsic::ppc_altivec_vcmpgtsw_p:
2563 case Intrinsic::ppc_altivec_vcmpgtub_p:
2564 case Intrinsic::ppc_altivec_vcmpgtuh_p:
2565 case Intrinsic::ppc_altivec_vcmpgtuw_p:
2566 KnownZero = ~1U; // All bits but the low one are known to be zero.
2574 /// getConstraintType - Given a constraint letter, return the type of
2575 /// constraint it is for this target.
2576 PPCTargetLowering::ConstraintType
2577 PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
2578 switch (ConstraintLetter) {
2585 return C_RegisterClass;
2587 return TargetLowering::getConstraintType(ConstraintLetter);
2591 std::vector<unsigned> PPCTargetLowering::
2592 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2593 MVT::ValueType VT) const {
2594 if (Constraint.size() == 1) {
2595 switch (Constraint[0]) { // GCC RS6000 Constraint Letters
2596 default: break; // Unknown constriant letter
2598 return make_vector<unsigned>(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 ,
2599 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
2600 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
2601 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
2602 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
2603 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
2604 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
2605 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
2608 return make_vector<unsigned>(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 ,
2609 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
2610 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
2611 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
2612 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
2613 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
2614 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
2615 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
2618 return make_vector<unsigned>(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 ,
2619 PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 ,
2620 PPC::F8 , PPC::F9 , PPC::F10, PPC::F11,
2621 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
2622 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
2623 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
2624 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
2625 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
2628 return make_vector<unsigned>(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 ,
2629 PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
2630 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11,
2631 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
2632 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
2633 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
2634 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
2635 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
2638 return make_vector<unsigned>(PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
2639 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7,
2644 return std::vector<unsigned>();
2647 // isOperandValidForConstraint
2648 bool PPCTargetLowering::
2649 isOperandValidForConstraint(SDOperand Op, char Letter) {
2660 if (!isa<ConstantSDNode>(Op)) return false; // Must be an immediate.
2661 unsigned Value = cast<ConstantSDNode>(Op)->getValue();
2663 default: assert(0 && "Unknown constraint letter!");
2664 case 'I': // "I" is a signed 16-bit constant.
2665 return (short)Value == (int)Value;
2666 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
2667 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
2668 return (short)Value == 0;
2669 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
2670 return (Value >> 16) == 0;
2671 case 'M': // "M" is a constant that is greater than 31.
2673 case 'N': // "N" is a positive constant that is an exact power of two.
2674 return (int)Value > 0 && isPowerOf2_32(Value);
2675 case 'O': // "O" is the constant zero.
2677 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
2678 return (short)-Value == (int)-Value;
2684 // Handle standard constraint letters.
2685 return TargetLowering::isOperandValidForConstraint(Op, Letter);
2688 /// isLegalAddressImmediate - Return true if the integer value can be used
2689 /// as the offset of the target addressing mode.
2690 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const {
2691 // PPC allows a sign-extended 16-bit immediate field.
2692 return (V > -(1 << 16) && V < (1 << 16)-1);