1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPerfectShuffle.h"
17 #include "PPCTargetMachine.h"
18 #include "MCTargetDesc/PPCPredicates.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetOptions.h"
39 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
40 CCValAssign::LocInfo &LocInfo,
41 ISD::ArgFlagsTy &ArgFlags,
43 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
45 CCValAssign::LocInfo &LocInfo,
46 ISD::ArgFlagsTy &ArgFlags,
48 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
50 CCValAssign::LocInfo &LocInfo,
51 ISD::ArgFlagsTy &ArgFlags,
54 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
55 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
58 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
59 if (TM.getSubtargetImpl()->isDarwin())
60 return new TargetLoweringObjectFileMachO();
62 return new TargetLoweringObjectFileELF();
65 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
66 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
70 // Use _setjmp/_longjmp instead of setjmp/longjmp.
71 setUseUnderscoreSetJmp(true);
72 setUseUnderscoreLongJmp(true);
74 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
75 // arguments are at least 4/8 bytes aligned.
76 setMinStackArgumentAlignment(TM.getSubtarget<PPCSubtarget>().isPPC64() ? 8:4);
78 // Set up the register classes.
79 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
80 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
81 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
83 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
85 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
87 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
89 // PowerPC has pre-inc load and store's.
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
94 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
101 // This is used in the ppcf128->int sequence. Note it has different semantics
102 // from FP_ROUND: that rounds to nearest, this rounds to zero.
103 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
105 // We do not currently implment this libm ops for PowerPC.
106 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
107 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
108 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
109 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
110 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
112 // PowerPC has no SREM/UREM instructions
113 setOperationAction(ISD::SREM, MVT::i32, Expand);
114 setOperationAction(ISD::UREM, MVT::i32, Expand);
115 setOperationAction(ISD::SREM, MVT::i64, Expand);
116 setOperationAction(ISD::UREM, MVT::i64, Expand);
118 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
119 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
120 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
121 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
122 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
123 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
124 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
125 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
126 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
128 // We don't support sin/cos/sqrt/fmod/pow
129 setOperationAction(ISD::FSIN , MVT::f64, Expand);
130 setOperationAction(ISD::FCOS , MVT::f64, Expand);
131 setOperationAction(ISD::FREM , MVT::f64, Expand);
132 setOperationAction(ISD::FPOW , MVT::f64, Expand);
133 setOperationAction(ISD::FMA , MVT::f64, Expand);
134 setOperationAction(ISD::FSIN , MVT::f32, Expand);
135 setOperationAction(ISD::FCOS , MVT::f32, Expand);
136 setOperationAction(ISD::FREM , MVT::f32, Expand);
137 setOperationAction(ISD::FPOW , MVT::f32, Expand);
138 setOperationAction(ISD::FMA , MVT::f32, Expand);
140 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
142 // If we're enabling GP optimizations, use hardware square root
143 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
144 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
145 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
148 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
149 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
151 // PowerPC does not have BSWAP, CTPOP or CTTZ
152 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
153 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
154 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
155 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
156 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
157 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
158 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
159 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
160 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
161 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
163 // PowerPC does not have ROTR
164 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
165 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
167 // PowerPC does not have Select
168 setOperationAction(ISD::SELECT, MVT::i32, Expand);
169 setOperationAction(ISD::SELECT, MVT::i64, Expand);
170 setOperationAction(ISD::SELECT, MVT::f32, Expand);
171 setOperationAction(ISD::SELECT, MVT::f64, Expand);
173 // PowerPC wants to turn select_cc of FP into fsel when possible.
174 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
175 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
177 // PowerPC wants to optimize integer setcc a bit
178 setOperationAction(ISD::SETCC, MVT::i32, Custom);
180 // PowerPC does not have BRCOND which requires SetCC
181 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
183 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
185 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
186 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
188 // PowerPC does not have [U|S]INT_TO_FP
189 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
190 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
192 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
193 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
194 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
195 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
197 // We cannot sextinreg(i1). Expand to shifts.
198 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
200 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
201 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
202 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
203 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
206 // We want to legalize GlobalAddress and ConstantPool nodes into the
207 // appropriate instructions to materialize the address.
208 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
209 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
210 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
211 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
212 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
213 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
214 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
215 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
216 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
217 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
220 setOperationAction(ISD::TRAP, MVT::Other, Legal);
222 // TRAMPOLINE is custom lowered.
223 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
224 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
226 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
227 setOperationAction(ISD::VASTART , MVT::Other, Custom);
229 if (TM.getSubtarget<PPCSubtarget>().isSVR4ABI()) {
230 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
231 // VAARG always uses double-word chunks, so promote anything smaller.
232 setOperationAction(ISD::VAARG, MVT::i1, Promote);
233 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
234 setOperationAction(ISD::VAARG, MVT::i8, Promote);
235 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
236 setOperationAction(ISD::VAARG, MVT::i16, Promote);
237 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
238 setOperationAction(ISD::VAARG, MVT::i32, Promote);
239 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
240 setOperationAction(ISD::VAARG, MVT::Other, Expand);
242 // VAARG is custom lowered with the 32-bit SVR4 ABI.
243 setOperationAction(ISD::VAARG, MVT::Other, Custom);
244 setOperationAction(ISD::VAARG, MVT::i64, Custom);
247 setOperationAction(ISD::VAARG, MVT::Other, Expand);
249 // Use the default implementation.
250 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
251 setOperationAction(ISD::VAEND , MVT::Other, Expand);
252 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
253 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
254 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
255 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
257 // We want to custom lower some of our intrinsics.
258 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
260 // Comparisons that require checking two conditions.
261 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
262 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
263 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
264 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
265 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
266 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
267 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
268 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
269 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
270 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
271 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
272 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
274 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
275 // They also have instructions for converting between i64 and fp.
276 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
277 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
278 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
279 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
280 // This is just the low 32 bits of a (signed) fp->i64 conversion.
281 // We cannot do this with Promote because i64 is not a legal type.
282 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
284 // FIXME: disable this lowered code. This generates 64-bit register values,
285 // and we don't model the fact that the top part is clobbered by calls. We
286 // need to flag these together so that the value isn't live across a call.
287 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
289 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
290 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
293 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
294 // 64-bit PowerPC implementations can support i64 types directly
295 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
296 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
297 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
298 // 64-bit PowerPC wants to expand i128 shifts itself.
299 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
300 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
301 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
303 // 32-bit PowerPC wants to expand i64 shifts itself.
304 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
305 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
306 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
309 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
310 // First set operation action for all vector types to expand. Then we
311 // will selectively turn on ones that can be effectively codegen'd.
312 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
313 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
314 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
316 // add/sub are legal for all supported vector VT's.
317 setOperationAction(ISD::ADD , VT, Legal);
318 setOperationAction(ISD::SUB , VT, Legal);
320 // We promote all shuffles to v16i8.
321 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
322 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
324 // We promote all non-typed operations to v4i32.
325 setOperationAction(ISD::AND , VT, Promote);
326 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
327 setOperationAction(ISD::OR , VT, Promote);
328 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
329 setOperationAction(ISD::XOR , VT, Promote);
330 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
331 setOperationAction(ISD::LOAD , VT, Promote);
332 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
333 setOperationAction(ISD::SELECT, VT, Promote);
334 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
335 setOperationAction(ISD::STORE, VT, Promote);
336 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
338 // No other operations are legal.
339 setOperationAction(ISD::MUL , VT, Expand);
340 setOperationAction(ISD::SDIV, VT, Expand);
341 setOperationAction(ISD::SREM, VT, Expand);
342 setOperationAction(ISD::UDIV, VT, Expand);
343 setOperationAction(ISD::UREM, VT, Expand);
344 setOperationAction(ISD::FDIV, VT, Expand);
345 setOperationAction(ISD::FNEG, VT, Expand);
346 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
347 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
348 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
349 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
350 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
351 setOperationAction(ISD::UDIVREM, VT, Expand);
352 setOperationAction(ISD::SDIVREM, VT, Expand);
353 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
354 setOperationAction(ISD::FPOW, VT, Expand);
355 setOperationAction(ISD::CTPOP, VT, Expand);
356 setOperationAction(ISD::CTLZ, VT, Expand);
357 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
358 setOperationAction(ISD::CTTZ, VT, Expand);
359 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
362 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
363 // with merges, splats, etc.
364 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
366 setOperationAction(ISD::AND , MVT::v4i32, Legal);
367 setOperationAction(ISD::OR , MVT::v4i32, Legal);
368 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
369 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
370 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
371 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
373 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
374 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
375 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
376 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
378 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
379 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
380 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
381 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
383 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
384 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
386 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
387 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
388 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
389 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
392 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
393 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
395 setBooleanContents(ZeroOrOneBooleanContent);
396 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
398 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
399 setStackPointerRegisterToSaveRestore(PPC::X1);
400 setExceptionPointerRegister(PPC::X3);
401 setExceptionSelectorRegister(PPC::X4);
403 setStackPointerRegisterToSaveRestore(PPC::R1);
404 setExceptionPointerRegister(PPC::R3);
405 setExceptionSelectorRegister(PPC::R4);
408 // We have target-specific dag combine patterns for the following nodes:
409 setTargetDAGCombine(ISD::SINT_TO_FP);
410 setTargetDAGCombine(ISD::STORE);
411 setTargetDAGCombine(ISD::BR_CC);
412 setTargetDAGCombine(ISD::BSWAP);
414 // Darwin long double math library functions have $LDBL128 appended.
415 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
416 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
417 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
418 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
419 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
420 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
421 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
422 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
423 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
424 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
425 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
428 setMinFunctionAlignment(2);
429 if (PPCSubTarget.isDarwin())
430 setPrefFunctionAlignment(4);
432 setInsertFencesForAtomic(true);
434 setSchedulingPreference(Sched::Hybrid);
436 computeRegisterProperties();
439 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
440 /// function arguments in the caller parameter area.
441 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
442 const TargetMachine &TM = getTargetMachine();
443 // Darwin passes everything on 4 byte boundary.
444 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
450 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
453 case PPCISD::FSEL: return "PPCISD::FSEL";
454 case PPCISD::FCFID: return "PPCISD::FCFID";
455 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
456 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
457 case PPCISD::STFIWX: return "PPCISD::STFIWX";
458 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
459 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
460 case PPCISD::VPERM: return "PPCISD::VPERM";
461 case PPCISD::Hi: return "PPCISD::Hi";
462 case PPCISD::Lo: return "PPCISD::Lo";
463 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
464 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
465 case PPCISD::LOAD: return "PPCISD::LOAD";
466 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
467 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
468 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
469 case PPCISD::SRL: return "PPCISD::SRL";
470 case PPCISD::SRA: return "PPCISD::SRA";
471 case PPCISD::SHL: return "PPCISD::SHL";
472 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
473 case PPCISD::STD_32: return "PPCISD::STD_32";
474 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4";
475 case PPCISD::CALL_NOP_SVR4: return "PPCISD::CALL_NOP_SVR4";
476 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin";
477 case PPCISD::NOP: return "PPCISD::NOP";
478 case PPCISD::MTCTR: return "PPCISD::MTCTR";
479 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin";
480 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4";
481 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
482 case PPCISD::MFCR: return "PPCISD::MFCR";
483 case PPCISD::VCMP: return "PPCISD::VCMP";
484 case PPCISD::VCMPo: return "PPCISD::VCMPo";
485 case PPCISD::LBRX: return "PPCISD::LBRX";
486 case PPCISD::STBRX: return "PPCISD::STBRX";
487 case PPCISD::LARX: return "PPCISD::LARX";
488 case PPCISD::STCX: return "PPCISD::STCX";
489 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
490 case PPCISD::MFFS: return "PPCISD::MFFS";
491 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
492 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
493 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
494 case PPCISD::MTFSF: return "PPCISD::MTFSF";
495 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
499 EVT PPCTargetLowering::getSetCCResultType(EVT VT) const {
503 //===----------------------------------------------------------------------===//
504 // Node matching predicates, for use by the tblgen matching code.
505 //===----------------------------------------------------------------------===//
507 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
508 static bool isFloatingPointZero(SDValue Op) {
509 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
510 return CFP->getValueAPF().isZero();
511 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
512 // Maybe this has already been legalized into the constant pool?
513 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
514 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
515 return CFP->getValueAPF().isZero();
520 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
521 /// true if Op is undef or if it matches the specified value.
522 static bool isConstantOrUndef(int Op, int Val) {
523 return Op < 0 || Op == Val;
526 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
527 /// VPKUHUM instruction.
528 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
530 for (unsigned i = 0; i != 16; ++i)
531 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
534 for (unsigned i = 0; i != 8; ++i)
535 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
536 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
542 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
543 /// VPKUWUM instruction.
544 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
546 for (unsigned i = 0; i != 16; i += 2)
547 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
548 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
551 for (unsigned i = 0; i != 8; i += 2)
552 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
553 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
554 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
555 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
561 /// isVMerge - Common function, used to match vmrg* shuffles.
563 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
564 unsigned LHSStart, unsigned RHSStart) {
565 assert(N->getValueType(0) == MVT::v16i8 &&
566 "PPC only supports shuffles by bytes!");
567 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
568 "Unsupported merge size!");
570 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
571 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
572 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
573 LHSStart+j+i*UnitSize) ||
574 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
575 RHSStart+j+i*UnitSize))
581 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
582 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
583 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
586 return isVMerge(N, UnitSize, 8, 24);
587 return isVMerge(N, UnitSize, 8, 8);
590 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
591 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
592 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
595 return isVMerge(N, UnitSize, 0, 16);
596 return isVMerge(N, UnitSize, 0, 0);
600 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
601 /// amount, otherwise return -1.
602 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
603 assert(N->getValueType(0) == MVT::v16i8 &&
604 "PPC only supports shuffles by bytes!");
606 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
608 // Find the first non-undef value in the shuffle mask.
610 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
613 if (i == 16) return -1; // all undef.
615 // Otherwise, check to see if the rest of the elements are consecutively
616 // numbered from this value.
617 unsigned ShiftAmt = SVOp->getMaskElt(i);
618 if (ShiftAmt < i) return -1;
622 // Check the rest of the elements to see if they are consecutive.
623 for (++i; i != 16; ++i)
624 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
627 // Check the rest of the elements to see if they are consecutive.
628 for (++i; i != 16; ++i)
629 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
635 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
636 /// specifies a splat of a single element that is suitable for input to
637 /// VSPLTB/VSPLTH/VSPLTW.
638 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
639 assert(N->getValueType(0) == MVT::v16i8 &&
640 (EltSize == 1 || EltSize == 2 || EltSize == 4));
642 // This is a splat operation if each element of the permute is the same, and
643 // if the value doesn't reference the second vector.
644 unsigned ElementBase = N->getMaskElt(0);
646 // FIXME: Handle UNDEF elements too!
647 if (ElementBase >= 16)
650 // Check that the indices are consecutive, in the case of a multi-byte element
651 // splatted with a v16i8 mask.
652 for (unsigned i = 1; i != EltSize; ++i)
653 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
656 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
657 if (N->getMaskElt(i) < 0) continue;
658 for (unsigned j = 0; j != EltSize; ++j)
659 if (N->getMaskElt(i+j) != N->getMaskElt(j))
665 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
667 bool PPC::isAllNegativeZeroVector(SDNode *N) {
668 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
670 APInt APVal, APUndef;
674 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
675 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
676 return CFP->getValueAPF().isNegZero();
681 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
682 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
683 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
684 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
685 assert(isSplatShuffleMask(SVOp, EltSize));
686 return SVOp->getMaskElt(0) / EltSize;
689 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
690 /// by using a vspltis[bhw] instruction of the specified element size, return
691 /// the constant being splatted. The ByteSize field indicates the number of
692 /// bytes of each element [124] -> [bhw].
693 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
696 // If ByteSize of the splat is bigger than the element size of the
697 // build_vector, then we have a case where we are checking for a splat where
698 // multiple elements of the buildvector are folded together into a single
699 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
700 unsigned EltSize = 16/N->getNumOperands();
701 if (EltSize < ByteSize) {
702 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
703 SDValue UniquedVals[4];
704 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
706 // See if all of the elements in the buildvector agree across.
707 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
708 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
709 // If the element isn't a constant, bail fully out.
710 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
713 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
714 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
715 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
716 return SDValue(); // no match.
719 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
720 // either constant or undef values that are identical for each chunk. See
721 // if these chunks can form into a larger vspltis*.
723 // Check to see if all of the leading entries are either 0 or -1. If
724 // neither, then this won't fit into the immediate field.
725 bool LeadingZero = true;
726 bool LeadingOnes = true;
727 for (unsigned i = 0; i != Multiple-1; ++i) {
728 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
730 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
731 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
733 // Finally, check the least significant entry.
735 if (UniquedVals[Multiple-1].getNode() == 0)
736 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
737 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
739 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
742 if (UniquedVals[Multiple-1].getNode() == 0)
743 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
744 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
745 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
746 return DAG.getTargetConstant(Val, MVT::i32);
752 // Check to see if this buildvec has a single non-undef value in its elements.
753 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
754 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
755 if (OpVal.getNode() == 0)
756 OpVal = N->getOperand(i);
757 else if (OpVal != N->getOperand(i))
761 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
763 unsigned ValSizeInBytes = EltSize;
765 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
766 Value = CN->getZExtValue();
767 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
768 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
769 Value = FloatToBits(CN->getValueAPF().convertToFloat());
772 // If the splat value is larger than the element value, then we can never do
773 // this splat. The only case that we could fit the replicated bits into our
774 // immediate field for would be zero, and we prefer to use vxor for it.
775 if (ValSizeInBytes < ByteSize) return SDValue();
777 // If the element value is larger than the splat value, cut it in half and
778 // check to see if the two halves are equal. Continue doing this until we
779 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
780 while (ValSizeInBytes > ByteSize) {
781 ValSizeInBytes >>= 1;
783 // If the top half equals the bottom half, we're still ok.
784 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
785 (Value & ((1 << (8*ValSizeInBytes))-1)))
789 // Properly sign extend the value.
790 int ShAmt = (4-ByteSize)*8;
791 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
793 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
794 if (MaskVal == 0) return SDValue();
796 // Finally, if this value fits in a 5 bit sext field, return it
797 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
798 return DAG.getTargetConstant(MaskVal, MVT::i32);
802 //===----------------------------------------------------------------------===//
803 // Addressing Mode Selection
804 //===----------------------------------------------------------------------===//
806 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
807 /// or 64-bit immediate, and if the value can be accurately represented as a
808 /// sign extension from a 16-bit value. If so, this returns true and the
810 static bool isIntS16Immediate(SDNode *N, short &Imm) {
811 if (N->getOpcode() != ISD::Constant)
814 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
815 if (N->getValueType(0) == MVT::i32)
816 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
818 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
820 static bool isIntS16Immediate(SDValue Op, short &Imm) {
821 return isIntS16Immediate(Op.getNode(), Imm);
825 /// SelectAddressRegReg - Given the specified addressed, check to see if it
826 /// can be represented as an indexed [r+r] operation. Returns false if it
827 /// can be more efficiently represented with [r+imm].
828 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
830 SelectionDAG &DAG) const {
832 if (N.getOpcode() == ISD::ADD) {
833 if (isIntS16Immediate(N.getOperand(1), imm))
835 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
838 Base = N.getOperand(0);
839 Index = N.getOperand(1);
841 } else if (N.getOpcode() == ISD::OR) {
842 if (isIntS16Immediate(N.getOperand(1), imm))
843 return false; // r+i can fold it if we can.
845 // If this is an or of disjoint bitfields, we can codegen this as an add
846 // (for better address arithmetic) if the LHS and RHS of the OR are provably
848 APInt LHSKnownZero, LHSKnownOne;
849 APInt RHSKnownZero, RHSKnownOne;
850 DAG.ComputeMaskedBits(N.getOperand(0),
851 APInt::getAllOnesValue(N.getOperand(0)
852 .getValueSizeInBits()),
853 LHSKnownZero, LHSKnownOne);
855 if (LHSKnownZero.getBoolValue()) {
856 DAG.ComputeMaskedBits(N.getOperand(1),
857 APInt::getAllOnesValue(N.getOperand(1)
858 .getValueSizeInBits()),
859 RHSKnownZero, RHSKnownOne);
860 // If all of the bits are known zero on the LHS or RHS, the add won't
862 if (~(LHSKnownZero | RHSKnownZero) == 0) {
863 Base = N.getOperand(0);
864 Index = N.getOperand(1);
873 /// Returns true if the address N can be represented by a base register plus
874 /// a signed 16-bit displacement [r+imm], and if it is not better
875 /// represented as reg+reg.
876 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
878 SelectionDAG &DAG) const {
879 // FIXME dl should come from parent load or store, not from address
880 DebugLoc dl = N.getDebugLoc();
881 // If this can be more profitably realized as r+r, fail.
882 if (SelectAddressRegReg(N, Disp, Base, DAG))
885 if (N.getOpcode() == ISD::ADD) {
887 if (isIntS16Immediate(N.getOperand(1), imm)) {
888 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
889 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
890 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
892 Base = N.getOperand(0);
894 return true; // [r+i]
895 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
896 // Match LOAD (ADD (X, Lo(G))).
897 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
898 && "Cannot handle constant offsets yet!");
899 Disp = N.getOperand(1).getOperand(0); // The global address.
900 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
901 Disp.getOpcode() == ISD::TargetConstantPool ||
902 Disp.getOpcode() == ISD::TargetJumpTable);
903 Base = N.getOperand(0);
904 return true; // [&g+r]
906 } else if (N.getOpcode() == ISD::OR) {
908 if (isIntS16Immediate(N.getOperand(1), imm)) {
909 // If this is an or of disjoint bitfields, we can codegen this as an add
910 // (for better address arithmetic) if the LHS and RHS of the OR are
911 // provably disjoint.
912 APInt LHSKnownZero, LHSKnownOne;
913 DAG.ComputeMaskedBits(N.getOperand(0),
914 APInt::getAllOnesValue(N.getOperand(0)
915 .getValueSizeInBits()),
916 LHSKnownZero, LHSKnownOne);
918 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
919 // If all of the bits are known zero on the LHS or RHS, the add won't
921 Base = N.getOperand(0);
922 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
926 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
927 // Loading from a constant address.
929 // If this address fits entirely in a 16-bit sext immediate field, codegen
932 if (isIntS16Immediate(CN, Imm)) {
933 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
934 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
935 CN->getValueType(0));
939 // Handle 32-bit sext immediates with LIS + addr mode.
940 if (CN->getValueType(0) == MVT::i32 ||
941 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
942 int Addr = (int)CN->getZExtValue();
944 // Otherwise, break this down into an LIS + disp.
945 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
947 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
948 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
949 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
954 Disp = DAG.getTargetConstant(0, getPointerTy());
955 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
956 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
959 return true; // [r+0]
962 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
963 /// represented as an indexed [r+r] operation.
964 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
966 SelectionDAG &DAG) const {
967 // Check to see if we can easily represent this as an [r+r] address. This
968 // will fail if it thinks that the address is more profitably represented as
969 // reg+imm, e.g. where imm = 0.
970 if (SelectAddressRegReg(N, Base, Index, DAG))
973 // If the operand is an addition, always emit this as [r+r], since this is
974 // better (for code size, and execution, as the memop does the add for free)
975 // than emitting an explicit add.
976 if (N.getOpcode() == ISD::ADD) {
977 Base = N.getOperand(0);
978 Index = N.getOperand(1);
982 // Otherwise, do it the hard way, using R0 as the base register.
983 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
989 /// SelectAddressRegImmShift - Returns true if the address N can be
990 /// represented by a base register plus a signed 14-bit displacement
991 /// [r+imm*4]. Suitable for use by STD and friends.
992 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
994 SelectionDAG &DAG) const {
995 // FIXME dl should come from the parent load or store, not the address
996 DebugLoc dl = N.getDebugLoc();
997 // If this can be more profitably realized as r+r, fail.
998 if (SelectAddressRegReg(N, Disp, Base, DAG))
1001 if (N.getOpcode() == ISD::ADD) {
1003 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1004 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1005 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1006 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1008 Base = N.getOperand(0);
1010 return true; // [r+i]
1011 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1012 // Match LOAD (ADD (X, Lo(G))).
1013 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1014 && "Cannot handle constant offsets yet!");
1015 Disp = N.getOperand(1).getOperand(0); // The global address.
1016 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1017 Disp.getOpcode() == ISD::TargetConstantPool ||
1018 Disp.getOpcode() == ISD::TargetJumpTable);
1019 Base = N.getOperand(0);
1020 return true; // [&g+r]
1022 } else if (N.getOpcode() == ISD::OR) {
1024 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1025 // If this is an or of disjoint bitfields, we can codegen this as an add
1026 // (for better address arithmetic) if the LHS and RHS of the OR are
1027 // provably disjoint.
1028 APInt LHSKnownZero, LHSKnownOne;
1029 DAG.ComputeMaskedBits(N.getOperand(0),
1030 APInt::getAllOnesValue(N.getOperand(0)
1031 .getValueSizeInBits()),
1032 LHSKnownZero, LHSKnownOne);
1033 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1034 // If all of the bits are known zero on the LHS or RHS, the add won't
1036 Base = N.getOperand(0);
1037 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1041 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1042 // Loading from a constant address. Verify low two bits are clear.
1043 if ((CN->getZExtValue() & 3) == 0) {
1044 // If this address fits entirely in a 14-bit sext immediate field, codegen
1047 if (isIntS16Immediate(CN, Imm)) {
1048 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1049 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
1050 CN->getValueType(0));
1054 // Fold the low-part of 32-bit absolute addresses into addr mode.
1055 if (CN->getValueType(0) == MVT::i32 ||
1056 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1057 int Addr = (int)CN->getZExtValue();
1059 // Otherwise, break this down into an LIS + disp.
1060 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1061 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1062 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1063 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1069 Disp = DAG.getTargetConstant(0, getPointerTy());
1070 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1071 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1074 return true; // [r+0]
1078 /// getPreIndexedAddressParts - returns true by value, base pointer and
1079 /// offset pointer and addressing mode by reference if the node's address
1080 /// can be legally represented as pre-indexed load / store address.
1081 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1083 ISD::MemIndexedMode &AM,
1084 SelectionDAG &DAG) const {
1085 // Disabled by default for now.
1086 if (!EnablePPCPreinc) return false;
1090 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1091 Ptr = LD->getBasePtr();
1092 VT = LD->getMemoryVT();
1094 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1095 Ptr = ST->getBasePtr();
1096 VT = ST->getMemoryVT();
1100 // PowerPC doesn't have preinc load/store instructions for vectors.
1104 // TODO: Check reg+reg first.
1106 // LDU/STU use reg+imm*4, others use reg+imm.
1107 if (VT != MVT::i64) {
1109 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1113 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1117 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1118 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1119 // sext i32 to i64 when addr mode is r+i.
1120 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1121 LD->getExtensionType() == ISD::SEXTLOAD &&
1122 isa<ConstantSDNode>(Offset))
1130 //===----------------------------------------------------------------------===//
1131 // LowerOperation implementation
1132 //===----------------------------------------------------------------------===//
1134 /// GetLabelAccessInfo - Return true if we should reference labels using a
1135 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1136 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1137 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1138 HiOpFlags = PPCII::MO_HA16;
1139 LoOpFlags = PPCII::MO_LO16;
1141 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1142 // non-darwin platform. We don't support PIC on other platforms yet.
1143 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1144 TM.getSubtarget<PPCSubtarget>().isDarwin();
1146 HiOpFlags |= PPCII::MO_PIC_FLAG;
1147 LoOpFlags |= PPCII::MO_PIC_FLAG;
1150 // If this is a reference to a global value that requires a non-lazy-ptr, make
1151 // sure that instruction lowering adds it.
1152 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1153 HiOpFlags |= PPCII::MO_NLP_FLAG;
1154 LoOpFlags |= PPCII::MO_NLP_FLAG;
1156 if (GV->hasHiddenVisibility()) {
1157 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1158 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1165 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1166 SelectionDAG &DAG) {
1167 EVT PtrVT = HiPart.getValueType();
1168 SDValue Zero = DAG.getConstant(0, PtrVT);
1169 DebugLoc DL = HiPart.getDebugLoc();
1171 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1172 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1174 // With PIC, the first instruction is actually "GR+hi(&G)".
1176 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1177 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1179 // Generate non-pic code that has direct accesses to the constant pool.
1180 // The address of the global is just (hi(&g)+lo(&g)).
1181 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1184 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1185 SelectionDAG &DAG) const {
1186 EVT PtrVT = Op.getValueType();
1187 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1188 const Constant *C = CP->getConstVal();
1190 unsigned MOHiFlag, MOLoFlag;
1191 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1193 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1195 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1196 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1199 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1200 EVT PtrVT = Op.getValueType();
1201 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1203 unsigned MOHiFlag, MOLoFlag;
1204 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1205 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1206 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1207 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1210 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1211 SelectionDAG &DAG) const {
1212 EVT PtrVT = Op.getValueType();
1214 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1216 unsigned MOHiFlag, MOLoFlag;
1217 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1218 SDValue TgtBAHi = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOHiFlag);
1219 SDValue TgtBALo = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOLoFlag);
1220 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1223 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1224 SelectionDAG &DAG) const {
1225 EVT PtrVT = Op.getValueType();
1226 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1227 DebugLoc DL = GSDN->getDebugLoc();
1228 const GlobalValue *GV = GSDN->getGlobal();
1230 // 64-bit SVR4 ABI code is always position-independent.
1231 // The actual address of the GlobalValue is stored in the TOC.
1232 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1233 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1234 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1235 DAG.getRegister(PPC::X2, MVT::i64));
1238 unsigned MOHiFlag, MOLoFlag;
1239 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1242 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1244 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1246 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1248 // If the global reference is actually to a non-lazy-pointer, we have to do an
1249 // extra load to get the address of the global.
1250 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1251 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1252 false, false, false, 0);
1256 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1257 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1258 DebugLoc dl = Op.getDebugLoc();
1260 // If we're comparing for equality to zero, expose the fact that this is
1261 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1262 // fold the new nodes.
1263 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1264 if (C->isNullValue() && CC == ISD::SETEQ) {
1265 EVT VT = Op.getOperand(0).getValueType();
1266 SDValue Zext = Op.getOperand(0);
1267 if (VT.bitsLT(MVT::i32)) {
1269 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1271 unsigned Log2b = Log2_32(VT.getSizeInBits());
1272 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1273 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1274 DAG.getConstant(Log2b, MVT::i32));
1275 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1277 // Leave comparisons against 0 and -1 alone for now, since they're usually
1278 // optimized. FIXME: revisit this when we can custom lower all setcc
1280 if (C->isAllOnesValue() || C->isNullValue())
1284 // If we have an integer seteq/setne, turn it into a compare against zero
1285 // by xor'ing the rhs with the lhs, which is faster than setting a
1286 // condition register, reading it back out, and masking the correct bit. The
1287 // normal approach here uses sub to do this instead of xor. Using xor exposes
1288 // the result to other bit-twiddling opportunities.
1289 EVT LHSVT = Op.getOperand(0).getValueType();
1290 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1291 EVT VT = Op.getValueType();
1292 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1294 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1299 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1300 const PPCSubtarget &Subtarget) const {
1301 SDNode *Node = Op.getNode();
1302 EVT VT = Node->getValueType(0);
1303 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1304 SDValue InChain = Node->getOperand(0);
1305 SDValue VAListPtr = Node->getOperand(1);
1306 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1307 DebugLoc dl = Node->getDebugLoc();
1309 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1312 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1313 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1315 InChain = GprIndex.getValue(1);
1317 if (VT == MVT::i64) {
1318 // Check if GprIndex is even
1319 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1320 DAG.getConstant(1, MVT::i32));
1321 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1322 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1323 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1324 DAG.getConstant(1, MVT::i32));
1325 // Align GprIndex to be even if it isn't
1326 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1330 // fpr index is 1 byte after gpr
1331 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1332 DAG.getConstant(1, MVT::i32));
1335 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1336 FprPtr, MachinePointerInfo(SV), MVT::i8,
1338 InChain = FprIndex.getValue(1);
1340 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1341 DAG.getConstant(8, MVT::i32));
1343 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1344 DAG.getConstant(4, MVT::i32));
1347 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1348 MachinePointerInfo(), false, false,
1350 InChain = OverflowArea.getValue(1);
1352 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1353 MachinePointerInfo(), false, false,
1355 InChain = RegSaveArea.getValue(1);
1357 // select overflow_area if index > 8
1358 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1359 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1361 // adjustment constant gpr_index * 4/8
1362 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1363 VT.isInteger() ? GprIndex : FprIndex,
1364 DAG.getConstant(VT.isInteger() ? 4 : 8,
1367 // OurReg = RegSaveArea + RegConstant
1368 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1371 // Floating types are 32 bytes into RegSaveArea
1372 if (VT.isFloatingPoint())
1373 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1374 DAG.getConstant(32, MVT::i32));
1376 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1377 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1378 VT.isInteger() ? GprIndex : FprIndex,
1379 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1382 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1383 VT.isInteger() ? VAListPtr : FprPtr,
1384 MachinePointerInfo(SV),
1385 MVT::i8, false, false, 0);
1387 // determine if we should load from reg_save_area or overflow_area
1388 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1390 // increase overflow_area by 4/8 if gpr/fpr > 8
1391 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1392 DAG.getConstant(VT.isInteger() ? 4 : 8,
1395 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1398 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1400 MachinePointerInfo(),
1401 MVT::i32, false, false, 0);
1403 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1404 false, false, false, 0);
1407 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1408 SelectionDAG &DAG) const {
1409 return Op.getOperand(0);
1412 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1413 SelectionDAG &DAG) const {
1414 SDValue Chain = Op.getOperand(0);
1415 SDValue Trmp = Op.getOperand(1); // trampoline
1416 SDValue FPtr = Op.getOperand(2); // nested function
1417 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1418 DebugLoc dl = Op.getDebugLoc();
1420 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1421 bool isPPC64 = (PtrVT == MVT::i64);
1423 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType(
1426 TargetLowering::ArgListTy Args;
1427 TargetLowering::ArgListEntry Entry;
1429 Entry.Ty = IntPtrTy;
1430 Entry.Node = Trmp; Args.push_back(Entry);
1432 // TrampSize == (isPPC64 ? 48 : 40);
1433 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1434 isPPC64 ? MVT::i64 : MVT::i32);
1435 Args.push_back(Entry);
1437 Entry.Node = FPtr; Args.push_back(Entry);
1438 Entry.Node = Nest; Args.push_back(Entry);
1440 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1441 std::pair<SDValue, SDValue> CallResult =
1442 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
1443 false, false, false, false, 0, CallingConv::C,
1444 /*isTailCall=*/false,
1445 /*doesNotRet=*/false, /*isReturnValueUsed=*/true,
1446 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1449 return CallResult.second;
1452 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1453 const PPCSubtarget &Subtarget) const {
1454 MachineFunction &MF = DAG.getMachineFunction();
1455 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1457 DebugLoc dl = Op.getDebugLoc();
1459 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1460 // vastart just stores the address of the VarArgsFrameIndex slot into the
1461 // memory location argument.
1462 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1463 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1464 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1465 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1466 MachinePointerInfo(SV),
1470 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1471 // We suppose the given va_list is already allocated.
1474 // char gpr; /* index into the array of 8 GPRs
1475 // * stored in the register save area
1476 // * gpr=0 corresponds to r3,
1477 // * gpr=1 to r4, etc.
1479 // char fpr; /* index into the array of 8 FPRs
1480 // * stored in the register save area
1481 // * fpr=0 corresponds to f1,
1482 // * fpr=1 to f2, etc.
1484 // char *overflow_arg_area;
1485 // /* location on stack that holds
1486 // * the next overflow argument
1488 // char *reg_save_area;
1489 // /* where r3:r10 and f1:f8 (if saved)
1495 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1496 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1499 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1501 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1503 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1506 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1507 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1509 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1510 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1512 uint64_t FPROffset = 1;
1513 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1515 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1517 // Store first byte : number of int regs
1518 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1520 MachinePointerInfo(SV),
1521 MVT::i8, false, false, 0);
1522 uint64_t nextOffset = FPROffset;
1523 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1526 // Store second byte : number of float regs
1527 SDValue secondStore =
1528 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1529 MachinePointerInfo(SV, nextOffset), MVT::i8,
1531 nextOffset += StackOffset;
1532 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1534 // Store second word : arguments given on stack
1535 SDValue thirdStore =
1536 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1537 MachinePointerInfo(SV, nextOffset),
1539 nextOffset += FrameOffset;
1540 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1542 // Store third word : arguments given in registers
1543 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1544 MachinePointerInfo(SV, nextOffset),
1549 #include "PPCGenCallingConv.inc"
1551 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1552 CCValAssign::LocInfo &LocInfo,
1553 ISD::ArgFlagsTy &ArgFlags,
1558 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1560 CCValAssign::LocInfo &LocInfo,
1561 ISD::ArgFlagsTy &ArgFlags,
1563 static const uint16_t ArgRegs[] = {
1564 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1565 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1567 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1569 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1571 // Skip one register if the first unallocated register has an even register
1572 // number and there are still argument registers available which have not been
1573 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1574 // need to skip a register if RegNum is odd.
1575 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1576 State.AllocateReg(ArgRegs[RegNum]);
1579 // Always return false here, as this function only makes sure that the first
1580 // unallocated register has an odd register number and does not actually
1581 // allocate a register for the current argument.
1585 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1587 CCValAssign::LocInfo &LocInfo,
1588 ISD::ArgFlagsTy &ArgFlags,
1590 static const uint16_t ArgRegs[] = {
1591 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1595 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1597 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1599 // If there is only one Floating-point register left we need to put both f64
1600 // values of a split ppc_fp128 value on the stack.
1601 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1602 State.AllocateReg(ArgRegs[RegNum]);
1605 // Always return false here, as this function only makes sure that the two f64
1606 // values a ppc_fp128 value is split into are both passed in registers or both
1607 // passed on the stack and does not actually allocate a register for the
1608 // current argument.
1612 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1614 static const uint16_t *GetFPR() {
1615 static const uint16_t FPR[] = {
1616 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1617 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1623 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1625 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1626 unsigned PtrByteSize) {
1627 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1628 if (Flags.isByVal())
1629 ArgSize = Flags.getByValSize();
1630 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1636 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1637 CallingConv::ID CallConv, bool isVarArg,
1638 const SmallVectorImpl<ISD::InputArg>
1640 DebugLoc dl, SelectionDAG &DAG,
1641 SmallVectorImpl<SDValue> &InVals)
1643 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
1644 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins,
1647 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1653 PPCTargetLowering::LowerFormalArguments_SVR4(
1655 CallingConv::ID CallConv, bool isVarArg,
1656 const SmallVectorImpl<ISD::InputArg>
1658 DebugLoc dl, SelectionDAG &DAG,
1659 SmallVectorImpl<SDValue> &InVals) const {
1661 // 32-bit SVR4 ABI Stack Frame Layout:
1662 // +-----------------------------------+
1663 // +--> | Back chain |
1664 // | +-----------------------------------+
1665 // | | Floating-point register save area |
1666 // | +-----------------------------------+
1667 // | | General register save area |
1668 // | +-----------------------------------+
1669 // | | CR save word |
1670 // | +-----------------------------------+
1671 // | | VRSAVE save word |
1672 // | +-----------------------------------+
1673 // | | Alignment padding |
1674 // | +-----------------------------------+
1675 // | | Vector register save area |
1676 // | +-----------------------------------+
1677 // | | Local variable space |
1678 // | +-----------------------------------+
1679 // | | Parameter list area |
1680 // | +-----------------------------------+
1681 // | | LR save word |
1682 // | +-----------------------------------+
1683 // SP--> +--- | Back chain |
1684 // +-----------------------------------+
1687 // System V Application Binary Interface PowerPC Processor Supplement
1688 // AltiVec Technology Programming Interface Manual
1690 MachineFunction &MF = DAG.getMachineFunction();
1691 MachineFrameInfo *MFI = MF.getFrameInfo();
1692 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1694 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1695 // Potential tail calls could cause overwriting of argument stack slots.
1696 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1697 (CallConv == CallingConv::Fast));
1698 unsigned PtrByteSize = 4;
1700 // Assign locations to all of the incoming arguments.
1701 SmallVector<CCValAssign, 16> ArgLocs;
1702 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1703 getTargetMachine(), ArgLocs, *DAG.getContext());
1705 // Reserve space for the linkage area on the stack.
1706 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
1708 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4);
1710 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1711 CCValAssign &VA = ArgLocs[i];
1713 // Arguments stored in registers.
1714 if (VA.isRegLoc()) {
1715 const TargetRegisterClass *RC;
1716 EVT ValVT = VA.getValVT();
1718 switch (ValVT.getSimpleVT().SimpleTy) {
1720 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1722 RC = PPC::GPRCRegisterClass;
1725 RC = PPC::F4RCRegisterClass;
1728 RC = PPC::F8RCRegisterClass;
1734 RC = PPC::VRRCRegisterClass;
1738 // Transform the arguments stored in physical registers into virtual ones.
1739 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1740 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1742 InVals.push_back(ArgValue);
1744 // Argument stored in memory.
1745 assert(VA.isMemLoc());
1747 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1748 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1751 // Create load nodes to retrieve arguments from the stack.
1752 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1753 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1754 MachinePointerInfo(),
1755 false, false, false, 0));
1759 // Assign locations to all of the incoming aggregate by value arguments.
1760 // Aggregates passed by value are stored in the local variable space of the
1761 // caller's stack frame, right above the parameter list area.
1762 SmallVector<CCValAssign, 16> ByValArgLocs;
1763 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1764 getTargetMachine(), ByValArgLocs, *DAG.getContext());
1766 // Reserve stack space for the allocations in CCInfo.
1767 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1769 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal);
1771 // Area that is at least reserved in the caller of this function.
1772 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1774 // Set the size that is at least reserved in caller of this function. Tail
1775 // call optimized function's reserved stack space needs to be aligned so that
1776 // taking the difference between two stack areas will result in an aligned
1778 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1781 std::max(MinReservedArea,
1782 PPCFrameLowering::getMinCallFrameSize(false, false));
1784 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
1785 getStackAlignment();
1786 unsigned AlignMask = TargetAlign-1;
1787 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1789 FI->setMinReservedArea(MinReservedArea);
1791 SmallVector<SDValue, 8> MemOps;
1793 // If the function takes variable number of arguments, make a frame index for
1794 // the start of the first vararg value... for expansion of llvm.va_start.
1796 static const uint16_t GPArgRegs[] = {
1797 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1798 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1800 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
1802 static const uint16_t FPArgRegs[] = {
1803 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1806 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
1808 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
1810 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
1813 // Make room for NumGPArgRegs and NumFPArgRegs.
1814 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
1815 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
1817 FuncInfo->setVarArgsStackOffset(
1818 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1819 CCInfo.getNextStackOffset(), true));
1821 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
1822 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1824 // The fixed integer arguments of a variadic function are stored to the
1825 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
1826 // the result of va_next.
1827 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
1828 // Get an existing live-in vreg, or add a new one.
1829 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
1831 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
1833 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1834 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1835 MachinePointerInfo(), false, false, 0);
1836 MemOps.push_back(Store);
1837 // Increment the address by four for the next argument to store
1838 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1839 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1842 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
1844 // The double arguments are stored to the VarArgsFrameIndex
1846 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
1847 // Get an existing live-in vreg, or add a new one.
1848 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
1850 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
1852 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
1853 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1854 MachinePointerInfo(), false, false, 0);
1855 MemOps.push_back(Store);
1856 // Increment the address by eight for the next argument to store
1857 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1859 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1863 if (!MemOps.empty())
1864 Chain = DAG.getNode(ISD::TokenFactor, dl,
1865 MVT::Other, &MemOps[0], MemOps.size());
1871 PPCTargetLowering::LowerFormalArguments_Darwin(
1873 CallingConv::ID CallConv, bool isVarArg,
1874 const SmallVectorImpl<ISD::InputArg>
1876 DebugLoc dl, SelectionDAG &DAG,
1877 SmallVectorImpl<SDValue> &InVals) const {
1878 // TODO: add description of PPC stack frame format, or at least some docs.
1880 MachineFunction &MF = DAG.getMachineFunction();
1881 MachineFrameInfo *MFI = MF.getFrameInfo();
1882 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1884 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1885 bool isPPC64 = PtrVT == MVT::i64;
1886 // Potential tail calls could cause overwriting of argument stack slots.
1887 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1888 (CallConv == CallingConv::Fast));
1889 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1891 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
1892 // Area that is at least reserved in caller of this function.
1893 unsigned MinReservedArea = ArgOffset;
1895 static const uint16_t GPR_32[] = { // 32-bit registers.
1896 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1897 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1899 static const uint16_t GPR_64[] = { // 64-bit registers.
1900 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1901 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1904 static const uint16_t *FPR = GetFPR();
1906 static const uint16_t VR[] = {
1907 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1908 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1911 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1912 const unsigned Num_FPR_Regs = 13;
1913 const unsigned Num_VR_Regs = array_lengthof( VR);
1915 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1917 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
1919 // In 32-bit non-varargs functions, the stack space for vectors is after the
1920 // stack space for non-vectors. We do not use this space unless we have
1921 // too many vectors to fit in registers, something that only occurs in
1922 // constructed examples:), but we have to walk the arglist to figure
1923 // that out...for the pathological case, compute VecArgOffset as the
1924 // start of the vector parameter area. Computing VecArgOffset is the
1925 // entire point of the following loop.
1926 unsigned VecArgOffset = ArgOffset;
1927 if (!isVarArg && !isPPC64) {
1928 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
1930 EVT ObjectVT = Ins[ArgNo].VT;
1931 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1933 if (Flags.isByVal()) {
1934 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1935 unsigned ObjSize = Flags.getByValSize();
1937 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1938 VecArgOffset += ArgSize;
1942 switch(ObjectVT.getSimpleVT().SimpleTy) {
1943 default: llvm_unreachable("Unhandled argument type!");
1946 VecArgOffset += isPPC64 ? 8 : 4;
1948 case MVT::i64: // PPC64
1956 // Nothing to do, we're only looking at Nonvector args here.
1961 // We've found where the vector parameter area in memory is. Skip the
1962 // first 12 parameters; these don't use that memory.
1963 VecArgOffset = ((VecArgOffset+15)/16)*16;
1964 VecArgOffset += 12*16;
1966 // Add DAG nodes to load the arguments or copy them out of registers. On
1967 // entry to a function on PPC, the arguments start after the linkage area,
1968 // although the first ones are often in registers.
1970 SmallVector<SDValue, 8> MemOps;
1971 unsigned nAltivecParamsAtEnd = 0;
1972 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
1974 bool needsLoad = false;
1975 EVT ObjectVT = Ins[ArgNo].VT;
1976 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1977 unsigned ArgSize = ObjSize;
1978 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1980 unsigned CurArgOffset = ArgOffset;
1982 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1983 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1984 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1985 if (isVarArg || isPPC64) {
1986 MinReservedArea = ((MinReservedArea+15)/16)*16;
1987 MinReservedArea += CalculateStackSlotSize(ObjectVT,
1990 } else nAltivecParamsAtEnd++;
1992 // Calculate min reserved area.
1993 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
1997 // FIXME the codegen can be much improved in some cases.
1998 // We do not have to keep everything in memory.
1999 if (Flags.isByVal()) {
2000 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2001 ObjSize = Flags.getByValSize();
2002 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2003 // Objects of size 1 and 2 are right justified, everything else is
2004 // left justified. This means the memory address is adjusted forwards.
2005 if (ObjSize==1 || ObjSize==2) {
2006 CurArgOffset = CurArgOffset + (4 - ObjSize);
2008 // The value of the object is its address.
2009 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2010 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2011 InVals.push_back(FIN);
2012 if (ObjSize==1 || ObjSize==2) {
2013 if (GPR_idx != Num_GPR_Regs) {
2016 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2018 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2019 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2020 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2021 MachinePointerInfo(),
2022 ObjSize==1 ? MVT::i8 : MVT::i16,
2024 MemOps.push_back(Store);
2028 ArgOffset += PtrByteSize;
2032 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2033 // Store whatever pieces of the object are in registers
2034 // to memory. ArgVal will be address of the beginning of
2036 if (GPR_idx != Num_GPR_Regs) {
2039 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2041 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2042 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2043 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2044 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2045 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2046 MachinePointerInfo(),
2048 MemOps.push_back(Store);
2050 ArgOffset += PtrByteSize;
2052 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2059 switch (ObjectVT.getSimpleVT().SimpleTy) {
2060 default: llvm_unreachable("Unhandled argument type!");
2063 if (GPR_idx != Num_GPR_Regs) {
2064 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2065 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2069 ArgSize = PtrByteSize;
2071 // All int arguments reserve stack space in the Darwin ABI.
2072 ArgOffset += PtrByteSize;
2076 case MVT::i64: // PPC64
2077 if (GPR_idx != Num_GPR_Regs) {
2078 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2079 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2081 if (ObjectVT == MVT::i32) {
2082 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2083 // value to MVT::i64 and then truncate to the correct register size.
2085 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2086 DAG.getValueType(ObjectVT));
2087 else if (Flags.isZExt())
2088 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2089 DAG.getValueType(ObjectVT));
2091 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2097 ArgSize = PtrByteSize;
2099 // All int arguments reserve stack space in the Darwin ABI.
2105 // Every 4 bytes of argument space consumes one of the GPRs available for
2106 // argument passing.
2107 if (GPR_idx != Num_GPR_Regs) {
2109 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2112 if (FPR_idx != Num_FPR_Regs) {
2115 if (ObjectVT == MVT::f32)
2116 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2118 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2120 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2126 // All FP arguments reserve stack space in the Darwin ABI.
2127 ArgOffset += isPPC64 ? 8 : ObjSize;
2133 // Note that vector arguments in registers don't reserve stack space,
2134 // except in varargs functions.
2135 if (VR_idx != Num_VR_Regs) {
2136 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2137 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2139 while ((ArgOffset % 16) != 0) {
2140 ArgOffset += PtrByteSize;
2141 if (GPR_idx != Num_GPR_Regs)
2145 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2149 if (!isVarArg && !isPPC64) {
2150 // Vectors go after all the nonvectors.
2151 CurArgOffset = VecArgOffset;
2154 // Vectors are aligned.
2155 ArgOffset = ((ArgOffset+15)/16)*16;
2156 CurArgOffset = ArgOffset;
2164 // We need to load the argument to a virtual register if we determined above
2165 // that we ran out of physical registers of the appropriate type.
2167 int FI = MFI->CreateFixedObject(ObjSize,
2168 CurArgOffset + (ArgSize - ObjSize),
2170 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2171 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2172 false, false, false, 0);
2175 InVals.push_back(ArgVal);
2178 // Set the size that is at least reserved in caller of this function. Tail
2179 // call optimized function's reserved stack space needs to be aligned so that
2180 // taking the difference between two stack areas will result in an aligned
2182 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2183 // Add the Altivec parameters at the end, if needed.
2184 if (nAltivecParamsAtEnd) {
2185 MinReservedArea = ((MinReservedArea+15)/16)*16;
2186 MinReservedArea += 16*nAltivecParamsAtEnd;
2189 std::max(MinReservedArea,
2190 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2191 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2192 getStackAlignment();
2193 unsigned AlignMask = TargetAlign-1;
2194 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2195 FI->setMinReservedArea(MinReservedArea);
2197 // If the function takes variable number of arguments, make a frame index for
2198 // the start of the first vararg value... for expansion of llvm.va_start.
2200 int Depth = ArgOffset;
2202 FuncInfo->setVarArgsFrameIndex(
2203 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2205 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2207 // If this function is vararg, store any remaining integer argument regs
2208 // to their spots on the stack so that they may be loaded by deferencing the
2209 // result of va_next.
2210 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2214 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2216 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2218 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2219 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2220 MachinePointerInfo(), false, false, 0);
2221 MemOps.push_back(Store);
2222 // Increment the address by four for the next argument to store
2223 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2224 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2228 if (!MemOps.empty())
2229 Chain = DAG.getNode(ISD::TokenFactor, dl,
2230 MVT::Other, &MemOps[0], MemOps.size());
2235 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
2236 /// linkage area for the Darwin ABI.
2238 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2242 const SmallVectorImpl<ISD::OutputArg>
2244 const SmallVectorImpl<SDValue> &OutVals,
2245 unsigned &nAltivecParamsAtEnd) {
2246 // Count how many bytes are to be pushed on the stack, including the linkage
2247 // area, and parameter passing area. We start with 24/48 bytes, which is
2248 // prereserved space for [SP][CR][LR][3 x unused].
2249 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2250 unsigned NumOps = Outs.size();
2251 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2253 // Add up all the space actually used.
2254 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2255 // they all go in registers, but we must reserve stack space for them for
2256 // possible use by the caller. In varargs or 64-bit calls, parameters are
2257 // assigned stack space in order, with padding so Altivec parameters are
2259 nAltivecParamsAtEnd = 0;
2260 for (unsigned i = 0; i != NumOps; ++i) {
2261 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2262 EVT ArgVT = Outs[i].VT;
2263 // Varargs Altivec parameters are padded to a 16 byte boundary.
2264 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2265 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2266 if (!isVarArg && !isPPC64) {
2267 // Non-varargs Altivec parameters go after all the non-Altivec
2268 // parameters; handle those later so we know how much padding we need.
2269 nAltivecParamsAtEnd++;
2272 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2273 NumBytes = ((NumBytes+15)/16)*16;
2275 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2278 // Allow for Altivec parameters at the end, if needed.
2279 if (nAltivecParamsAtEnd) {
2280 NumBytes = ((NumBytes+15)/16)*16;
2281 NumBytes += 16*nAltivecParamsAtEnd;
2284 // The prolog code of the callee may store up to 8 GPR argument registers to
2285 // the stack, allowing va_start to index over them in memory if its varargs.
2286 // Because we cannot tell if this is needed on the caller side, we have to
2287 // conservatively assume that it is needed. As such, make sure we have at
2288 // least enough stack space for the caller to store the 8 GPRs.
2289 NumBytes = std::max(NumBytes,
2290 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2292 // Tail call needs the stack to be aligned.
2293 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2294 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2295 getFrameLowering()->getStackAlignment();
2296 unsigned AlignMask = TargetAlign-1;
2297 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2303 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2304 /// adjusted to accommodate the arguments for the tailcall.
2305 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2306 unsigned ParamSize) {
2308 if (!isTailCall) return 0;
2310 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2311 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2312 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2313 // Remember only if the new adjustement is bigger.
2314 if (SPDiff < FI->getTailCallSPDelta())
2315 FI->setTailCallSPDelta(SPDiff);
2320 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2321 /// for tail call optimization. Targets which want to do tail call
2322 /// optimization should implement this function.
2324 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2325 CallingConv::ID CalleeCC,
2327 const SmallVectorImpl<ISD::InputArg> &Ins,
2328 SelectionDAG& DAG) const {
2329 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2332 // Variable argument functions are not supported.
2336 MachineFunction &MF = DAG.getMachineFunction();
2337 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2338 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2339 // Functions containing by val parameters are not supported.
2340 for (unsigned i = 0; i != Ins.size(); i++) {
2341 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2342 if (Flags.isByVal()) return false;
2345 // Non PIC/GOT tail calls are supported.
2346 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2349 // At the moment we can only do local tail calls (in same module, hidden
2350 // or protected) if we are generating PIC.
2351 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2352 return G->getGlobal()->hasHiddenVisibility()
2353 || G->getGlobal()->hasProtectedVisibility();
2359 /// isCallCompatibleAddress - Return the immediate to use if the specified
2360 /// 32-bit value is representable in the immediate field of a BxA instruction.
2361 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2362 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2365 int Addr = C->getZExtValue();
2366 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2367 (Addr << 6 >> 6) != Addr)
2368 return 0; // Top 6 bits have to be sext of immediate.
2370 return DAG.getConstant((int)C->getZExtValue() >> 2,
2371 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2376 struct TailCallArgumentInfo {
2381 TailCallArgumentInfo() : FrameIdx(0) {}
2386 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2388 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2390 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2391 SmallVector<SDValue, 8> &MemOpChains,
2393 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2394 SDValue Arg = TailCallArgs[i].Arg;
2395 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2396 int FI = TailCallArgs[i].FrameIdx;
2397 // Store relative to framepointer.
2398 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2399 MachinePointerInfo::getFixedStack(FI),
2404 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2405 /// the appropriate stack slot for the tail call optimized function call.
2406 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2407 MachineFunction &MF,
2416 // Calculate the new stack slot for the return address.
2417 int SlotSize = isPPC64 ? 8 : 4;
2418 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
2420 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2421 NewRetAddrLoc, true);
2422 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2423 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2424 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2425 MachinePointerInfo::getFixedStack(NewRetAddr),
2428 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2429 // slot as the FP is never overwritten.
2432 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2433 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
2435 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2436 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2437 MachinePointerInfo::getFixedStack(NewFPIdx),
2444 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2445 /// the position of the argument.
2447 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2448 SDValue Arg, int SPDiff, unsigned ArgOffset,
2449 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2450 int Offset = ArgOffset + SPDiff;
2451 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2452 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2453 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2454 SDValue FIN = DAG.getFrameIndex(FI, VT);
2455 TailCallArgumentInfo Info;
2457 Info.FrameIdxOp = FIN;
2459 TailCallArguments.push_back(Info);
2462 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2463 /// stack slot. Returns the chain as result and the loaded frame pointers in
2464 /// LROpOut/FPOpout. Used when tail calling.
2465 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2471 DebugLoc dl) const {
2473 // Load the LR and FP stack slot for later adjusting.
2474 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2475 LROpOut = getReturnAddrFrameIndex(DAG);
2476 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
2477 false, false, false, 0);
2478 Chain = SDValue(LROpOut.getNode(), 1);
2480 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
2481 // slot as the FP is never overwritten.
2483 FPOpOut = getFramePointerFrameIndex(DAG);
2484 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
2485 false, false, false, 0);
2486 Chain = SDValue(FPOpOut.getNode(), 1);
2492 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2493 /// by "Src" to address "Dst" of size "Size". Alignment information is
2494 /// specified by the specific parameter attribute. The copy will be passed as
2495 /// a byval function parameter.
2496 /// Sometimes what we are copying is the end of a larger object, the part that
2497 /// does not fit in registers.
2499 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2500 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2502 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2503 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2504 false, false, MachinePointerInfo(0),
2505 MachinePointerInfo(0));
2508 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2511 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2512 SDValue Arg, SDValue PtrOff, int SPDiff,
2513 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2514 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2515 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
2517 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2522 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2524 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2525 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2526 DAG.getConstant(ArgOffset, PtrVT));
2528 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2529 MachinePointerInfo(), false, false, 0));
2530 // Calculate and remember argument location.
2531 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2536 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
2537 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
2538 SDValue LROp, SDValue FPOp, bool isDarwinABI,
2539 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
2540 MachineFunction &MF = DAG.getMachineFunction();
2542 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2543 // might overwrite each other in case of tail call optimization.
2544 SmallVector<SDValue, 8> MemOpChains2;
2545 // Do not flag preceding copytoreg stuff together with the following stuff.
2547 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2549 if (!MemOpChains2.empty())
2550 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2551 &MemOpChains2[0], MemOpChains2.size());
2553 // Store the return address to the appropriate stack slot.
2554 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2555 isPPC64, isDarwinABI, dl);
2557 // Emit callseq_end just before tailcall node.
2558 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2559 DAG.getIntPtrConstant(0, true), InFlag);
2560 InFlag = Chain.getValue(1);
2564 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
2565 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
2566 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
2567 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
2568 const PPCSubtarget &PPCSubTarget) {
2570 bool isPPC64 = PPCSubTarget.isPPC64();
2571 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
2573 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2574 NodeTys.push_back(MVT::Other); // Returns a chain
2575 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
2577 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
2579 bool needIndirectCall = true;
2580 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
2581 // If this is an absolute destination address, use the munged value.
2582 Callee = SDValue(Dest, 0);
2583 needIndirectCall = false;
2586 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2587 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
2588 // Use indirect calls for ALL functions calls in JIT mode, since the
2589 // far-call stubs may be outside relocation limits for a BL instruction.
2590 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
2591 unsigned OpFlags = 0;
2592 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
2593 (PPCSubTarget.getTargetTriple().isMacOSX() &&
2594 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
2595 (G->getGlobal()->isDeclaration() ||
2596 G->getGlobal()->isWeakForLinker())) {
2597 // PC-relative references to external symbols should go through $stub,
2598 // unless we're building with the leopard linker or later, which
2599 // automatically synthesizes these stubs.
2600 OpFlags = PPCII::MO_DARWIN_STUB;
2603 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
2604 // every direct call is) turn it into a TargetGlobalAddress /
2605 // TargetExternalSymbol node so that legalize doesn't hack it.
2606 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2607 Callee.getValueType(),
2609 needIndirectCall = false;
2613 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2614 unsigned char OpFlags = 0;
2616 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
2617 (PPCSubTarget.getTargetTriple().isMacOSX() &&
2618 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
2619 // PC-relative references to external symbols should go through $stub,
2620 // unless we're building with the leopard linker or later, which
2621 // automatically synthesizes these stubs.
2622 OpFlags = PPCII::MO_DARWIN_STUB;
2625 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
2627 needIndirectCall = false;
2630 if (needIndirectCall) {
2631 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2632 // to do the call, we can't use PPCISD::CALL.
2633 SDValue MTCTROps[] = {Chain, Callee, InFlag};
2635 if (isSVR4ABI && isPPC64) {
2636 // Function pointers in the 64-bit SVR4 ABI do not point to the function
2637 // entry point, but to the function descriptor (the function entry point
2638 // address is part of the function descriptor though).
2639 // The function descriptor is a three doubleword structure with the
2640 // following fields: function entry point, TOC base address and
2641 // environment pointer.
2642 // Thus for a call through a function pointer, the following actions need
2644 // 1. Save the TOC of the caller in the TOC save area of its stack
2645 // frame (this is done in LowerCall_Darwin()).
2646 // 2. Load the address of the function entry point from the function
2648 // 3. Load the TOC of the callee from the function descriptor into r2.
2649 // 4. Load the environment pointer from the function descriptor into
2651 // 5. Branch to the function entry point address.
2652 // 6. On return of the callee, the TOC of the caller needs to be
2653 // restored (this is done in FinishCall()).
2655 // All those operations are flagged together to ensure that no other
2656 // operations can be scheduled in between. E.g. without flagging the
2657 // operations together, a TOC access in the caller could be scheduled
2658 // between the load of the callee TOC and the branch to the callee, which
2659 // results in the TOC access going through the TOC of the callee instead
2660 // of going through the TOC of the caller, which leads to incorrect code.
2662 // Load the address of the function entry point from the function
2664 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
2665 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
2666 InFlag.getNode() ? 3 : 2);
2667 Chain = LoadFuncPtr.getValue(1);
2668 InFlag = LoadFuncPtr.getValue(2);
2670 // Load environment pointer into r11.
2671 // Offset of the environment pointer within the function descriptor.
2672 SDValue PtrOff = DAG.getIntPtrConstant(16);
2674 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
2675 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
2677 Chain = LoadEnvPtr.getValue(1);
2678 InFlag = LoadEnvPtr.getValue(2);
2680 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
2682 Chain = EnvVal.getValue(0);
2683 InFlag = EnvVal.getValue(1);
2685 // Load TOC of the callee into r2. We are using a target-specific load
2686 // with r2 hard coded, because the result of a target-independent load
2687 // would never go directly into r2, since r2 is a reserved register (which
2688 // prevents the register allocator from allocating it), resulting in an
2689 // additional register being allocated and an unnecessary move instruction
2691 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2692 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
2694 Chain = LoadTOCPtr.getValue(0);
2695 InFlag = LoadTOCPtr.getValue(1);
2697 MTCTROps[0] = Chain;
2698 MTCTROps[1] = LoadFuncPtr;
2699 MTCTROps[2] = InFlag;
2702 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2703 2 + (InFlag.getNode() != 0));
2704 InFlag = Chain.getValue(1);
2707 NodeTys.push_back(MVT::Other);
2708 NodeTys.push_back(MVT::Glue);
2709 Ops.push_back(Chain);
2710 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
2712 // Add CTR register as callee so a bctr can be emitted later.
2714 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
2717 // If this is a direct call, pass the chain and the callee.
2718 if (Callee.getNode()) {
2719 Ops.push_back(Chain);
2720 Ops.push_back(Callee);
2722 // If this is a tail call add stack pointer delta.
2724 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2726 // Add argument registers to the end of the list so that they are known live
2728 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2729 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2730 RegsToPass[i].second.getValueType()));
2736 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2737 CallingConv::ID CallConv, bool isVarArg,
2738 const SmallVectorImpl<ISD::InputArg> &Ins,
2739 DebugLoc dl, SelectionDAG &DAG,
2740 SmallVectorImpl<SDValue> &InVals) const {
2742 SmallVector<CCValAssign, 16> RVLocs;
2743 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2744 getTargetMachine(), RVLocs, *DAG.getContext());
2745 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2747 // Copy all of the result registers out of their specified physreg.
2748 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2749 CCValAssign &VA = RVLocs[i];
2750 EVT VT = VA.getValVT();
2751 assert(VA.isRegLoc() && "Can only return in registers!");
2752 Chain = DAG.getCopyFromReg(Chain, dl,
2753 VA.getLocReg(), VT, InFlag).getValue(1);
2754 InVals.push_back(Chain.getValue(0));
2755 InFlag = Chain.getValue(2);
2762 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
2763 bool isTailCall, bool isVarArg,
2765 SmallVector<std::pair<unsigned, SDValue>, 8>
2767 SDValue InFlag, SDValue Chain,
2769 int SPDiff, unsigned NumBytes,
2770 const SmallVectorImpl<ISD::InputArg> &Ins,
2771 SmallVectorImpl<SDValue> &InVals) const {
2772 std::vector<EVT> NodeTys;
2773 SmallVector<SDValue, 8> Ops;
2774 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
2775 isTailCall, RegsToPass, Ops, NodeTys,
2778 // When performing tail call optimization the callee pops its arguments off
2779 // the stack. Account for this here so these bytes can be pushed back on in
2780 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2781 int BytesCalleePops =
2782 (CallConv == CallingConv::Fast &&
2783 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
2785 // Add a register mask operand representing the call-preserved registers.
2786 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2787 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2788 assert(Mask && "Missing call preserved mask for calling convention");
2789 Ops.push_back(DAG.getRegisterMask(Mask));
2791 if (InFlag.getNode())
2792 Ops.push_back(InFlag);
2796 // If this is the first return lowered for this function, add the regs
2797 // to the liveout set for the function.
2798 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2799 SmallVector<CCValAssign, 16> RVLocs;
2800 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2801 getTargetMachine(), RVLocs, *DAG.getContext());
2802 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2803 for (unsigned i = 0; i != RVLocs.size(); ++i)
2804 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2807 assert(((Callee.getOpcode() == ISD::Register &&
2808 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
2809 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2810 Callee.getOpcode() == ISD::TargetGlobalAddress ||
2811 isa<ConstantSDNode>(Callee)) &&
2812 "Expecting an global address, external symbol, absolute value or register");
2814 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
2817 // Add a NOP immediately after the branch instruction when using the 64-bit
2818 // SVR4 ABI. At link time, if caller and callee are in a different module and
2819 // thus have a different TOC, the call will be replaced with a call to a stub
2820 // function which saves the current TOC, loads the TOC of the callee and
2821 // branches to the callee. The NOP will be replaced with a load instruction
2822 // which restores the TOC of the caller from the TOC save slot of the current
2823 // stack frame. If caller and callee belong to the same module (and have the
2824 // same TOC), the NOP will remain unchanged.
2826 bool needsTOCRestore = false;
2827 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
2828 if (CallOpc == PPCISD::BCTRL_SVR4) {
2829 // This is a call through a function pointer.
2830 // Restore the caller TOC from the save area into R2.
2831 // See PrepareCall() for more information about calls through function
2832 // pointers in the 64-bit SVR4 ABI.
2833 // We are using a target-specific load with r2 hard coded, because the
2834 // result of a target-independent load would never go directly into r2,
2835 // since r2 is a reserved register (which prevents the register allocator
2836 // from allocating it), resulting in an additional register being
2837 // allocated and an unnecessary move instruction being generated.
2838 needsTOCRestore = true;
2839 } else if (CallOpc == PPCISD::CALL_SVR4) {
2840 // Otherwise insert NOP.
2841 CallOpc = PPCISD::CALL_NOP_SVR4;
2845 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
2846 InFlag = Chain.getValue(1);
2848 if (needsTOCRestore) {
2849 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2850 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
2851 InFlag = Chain.getValue(1);
2854 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2855 DAG.getIntPtrConstant(BytesCalleePops, true),
2858 InFlag = Chain.getValue(1);
2860 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2861 Ins, dl, DAG, InVals);
2865 PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2866 CallingConv::ID CallConv, bool isVarArg,
2867 bool doesNotRet, bool &isTailCall,
2868 const SmallVectorImpl<ISD::OutputArg> &Outs,
2869 const SmallVectorImpl<SDValue> &OutVals,
2870 const SmallVectorImpl<ISD::InputArg> &Ins,
2871 DebugLoc dl, SelectionDAG &DAG,
2872 SmallVectorImpl<SDValue> &InVals) const {
2874 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
2877 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
2878 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg,
2879 isTailCall, Outs, OutVals, Ins,
2882 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
2883 isTailCall, Outs, OutVals, Ins,
2888 PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
2889 CallingConv::ID CallConv, bool isVarArg,
2891 const SmallVectorImpl<ISD::OutputArg> &Outs,
2892 const SmallVectorImpl<SDValue> &OutVals,
2893 const SmallVectorImpl<ISD::InputArg> &Ins,
2894 DebugLoc dl, SelectionDAG &DAG,
2895 SmallVectorImpl<SDValue> &InVals) const {
2896 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description
2897 // of the 32-bit SVR4 ABI stack frame layout.
2899 assert((CallConv == CallingConv::C ||
2900 CallConv == CallingConv::Fast) && "Unknown calling convention!");
2902 unsigned PtrByteSize = 4;
2904 MachineFunction &MF = DAG.getMachineFunction();
2906 // Mark this function as potentially containing a function that contains a
2907 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2908 // and restoring the callers stack pointer in this functions epilog. This is
2909 // done because by tail calling the called function might overwrite the value
2910 // in this function's (MF) stack pointer stack slot 0(SP).
2911 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2912 CallConv == CallingConv::Fast)
2913 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2915 // Count how many bytes are to be pushed on the stack, including the linkage
2916 // area, parameter list area and the part of the local variable space which
2917 // contains copies of aggregates which are passed by value.
2919 // Assign locations to all of the outgoing arguments.
2920 SmallVector<CCValAssign, 16> ArgLocs;
2921 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2922 getTargetMachine(), ArgLocs, *DAG.getContext());
2924 // Reserve space for the linkage area on the stack.
2925 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2928 // Handle fixed and variable vector arguments differently.
2929 // Fixed vector arguments go into registers as long as registers are
2930 // available. Variable vector arguments always go into memory.
2931 unsigned NumArgs = Outs.size();
2933 for (unsigned i = 0; i != NumArgs; ++i) {
2934 MVT ArgVT = Outs[i].VT;
2935 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2938 if (Outs[i].IsFixed) {
2939 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
2942 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
2948 errs() << "Call operand #" << i << " has unhandled type "
2949 << EVT(ArgVT).getEVTString() << "\n";
2951 llvm_unreachable(0);
2955 // All arguments are treated the same.
2956 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4);
2959 // Assign locations to all of the outgoing aggregate by value arguments.
2960 SmallVector<CCValAssign, 16> ByValArgLocs;
2961 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2962 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2964 // Reserve stack space for the allocations in CCInfo.
2965 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2967 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal);
2969 // Size of the linkage area, parameter list area and the part of the local
2970 // space variable where copies of aggregates which are passed by value are
2972 unsigned NumBytes = CCByValInfo.getNextStackOffset();
2974 // Calculate by how many bytes the stack has to be adjusted in case of tail
2975 // call optimization.
2976 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2978 // Adjust the stack pointer for the new arguments...
2979 // These operations are automatically eliminated by the prolog/epilog pass
2980 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2981 SDValue CallSeqStart = Chain;
2983 // Load the return address and frame pointer so it can be moved somewhere else
2986 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
2989 // Set up a copy of the stack pointer for use loading and storing any
2990 // arguments that may not fit in the registers available for argument
2992 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2994 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2995 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2996 SmallVector<SDValue, 8> MemOpChains;
2998 bool seenFloatArg = false;
2999 // Walk the register/memloc assignments, inserting copies/loads.
3000 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3003 CCValAssign &VA = ArgLocs[i];
3004 SDValue Arg = OutVals[i];
3005 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3007 if (Flags.isByVal()) {
3008 // Argument is an aggregate which is passed by value, thus we need to
3009 // create a copy of it in the local variable space of the current stack
3010 // frame (which is the stack frame of the caller) and pass the address of
3011 // this copy to the callee.
3012 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3013 CCValAssign &ByValVA = ByValArgLocs[j++];
3014 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3016 // Memory reserved in the local variable space of the callers stack frame.
3017 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3019 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3020 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3022 // Create a copy of the argument in the local area of the current
3024 SDValue MemcpyCall =
3025 CreateCopyOfByValArgument(Arg, PtrOff,
3026 CallSeqStart.getNode()->getOperand(0),
3029 // This must go outside the CALLSEQ_START..END.
3030 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3031 CallSeqStart.getNode()->getOperand(1));
3032 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3033 NewCallSeqStart.getNode());
3034 Chain = CallSeqStart = NewCallSeqStart;
3036 // Pass the address of the aggregate copy on the stack either in a
3037 // physical register or in the parameter list area of the current stack
3038 // frame to the callee.
3042 if (VA.isRegLoc()) {
3043 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3044 // Put argument in a physical register.
3045 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3047 // Put argument in the parameter list area of the current stack frame.
3048 assert(VA.isMemLoc());
3049 unsigned LocMemOffset = VA.getLocMemOffset();
3052 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3053 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3055 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3056 MachinePointerInfo(),
3059 // Calculate and remember argument location.
3060 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3066 if (!MemOpChains.empty())
3067 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3068 &MemOpChains[0], MemOpChains.size());
3070 // Set CR6 to true if this is a vararg call with floating args passed in
3073 SDValue SetCR(DAG.getMachineNode(seenFloatArg ? PPC::CRSET : PPC::CRUNSET,
3075 RegsToPass.push_back(std::make_pair(unsigned(PPC::CR1EQ), SetCR));
3078 // Build a sequence of copy-to-reg nodes chained together with token chain
3079 // and flag operands which copy the outgoing args into the appropriate regs.
3081 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3082 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3083 RegsToPass[i].second, InFlag);
3084 InFlag = Chain.getValue(1);
3088 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3089 false, TailCallArguments);
3091 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3092 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3097 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
3098 CallingConv::ID CallConv, bool isVarArg,
3100 const SmallVectorImpl<ISD::OutputArg> &Outs,
3101 const SmallVectorImpl<SDValue> &OutVals,
3102 const SmallVectorImpl<ISD::InputArg> &Ins,
3103 DebugLoc dl, SelectionDAG &DAG,
3104 SmallVectorImpl<SDValue> &InVals) const {
3106 unsigned NumOps = Outs.size();
3108 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3109 bool isPPC64 = PtrVT == MVT::i64;
3110 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3112 MachineFunction &MF = DAG.getMachineFunction();
3114 // Mark this function as potentially containing a function that contains a
3115 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3116 // and restoring the callers stack pointer in this functions epilog. This is
3117 // done because by tail calling the called function might overwrite the value
3118 // in this function's (MF) stack pointer stack slot 0(SP).
3119 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3120 CallConv == CallingConv::Fast)
3121 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3123 unsigned nAltivecParamsAtEnd = 0;
3125 // Count how many bytes are to be pushed on the stack, including the linkage
3126 // area, and parameter passing area. We start with 24/48 bytes, which is
3127 // prereserved space for [SP][CR][LR][3 x unused].
3129 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
3131 nAltivecParamsAtEnd);
3133 // Calculate by how many bytes the stack has to be adjusted in case of tail
3134 // call optimization.
3135 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3137 // To protect arguments on the stack from being clobbered in a tail call,
3138 // force all the loads to happen before doing any other lowering.
3140 Chain = DAG.getStackArgumentTokenFactor(Chain);
3142 // Adjust the stack pointer for the new arguments...
3143 // These operations are automatically eliminated by the prolog/epilog pass
3144 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3145 SDValue CallSeqStart = Chain;
3147 // Load the return address and frame pointer so it can be move somewhere else
3150 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3153 // Set up a copy of the stack pointer for use loading and storing any
3154 // arguments that may not fit in the registers available for argument
3158 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3160 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3162 // Figure out which arguments are going to go in registers, and which in
3163 // memory. Also, if this is a vararg function, floating point operations
3164 // must be stored to our stack, and loaded into integer regs as well, if
3165 // any integer regs are available for argument passing.
3166 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
3167 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3169 static const uint16_t GPR_32[] = { // 32-bit registers.
3170 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3171 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3173 static const uint16_t GPR_64[] = { // 64-bit registers.
3174 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3175 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3177 static const uint16_t *FPR = GetFPR();
3179 static const uint16_t VR[] = {
3180 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3181 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3183 const unsigned NumGPRs = array_lengthof(GPR_32);
3184 const unsigned NumFPRs = 13;
3185 const unsigned NumVRs = array_lengthof(VR);
3187 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
3189 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3190 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3192 SmallVector<SDValue, 8> MemOpChains;
3193 for (unsigned i = 0; i != NumOps; ++i) {
3194 SDValue Arg = OutVals[i];
3195 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3197 // PtrOff will be used to store the current argument to the stack if a
3198 // register cannot be found for it.
3201 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3203 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3205 // On PPC64, promote integers to 64-bit values.
3206 if (isPPC64 && Arg.getValueType() == MVT::i32) {
3207 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3208 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3209 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3212 // FIXME memcpy is used way more than necessary. Correctness first.
3213 if (Flags.isByVal()) {
3214 unsigned Size = Flags.getByValSize();
3215 if (Size==1 || Size==2) {
3216 // Very small objects are passed right-justified.
3217 // Everything else is passed left-justified.
3218 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
3219 if (GPR_idx != NumGPRs) {
3220 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3221 MachinePointerInfo(), VT,
3223 MemOpChains.push_back(Load.getValue(1));
3224 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3226 ArgOffset += PtrByteSize;
3228 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
3229 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3230 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
3231 CallSeqStart.getNode()->getOperand(0),
3233 // This must go outside the CALLSEQ_START..END.
3234 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3235 CallSeqStart.getNode()->getOperand(1));
3236 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3237 NewCallSeqStart.getNode());
3238 Chain = CallSeqStart = NewCallSeqStart;
3239 ArgOffset += PtrByteSize;
3243 // Copy entire object into memory. There are cases where gcc-generated
3244 // code assumes it is there, even if it could be put entirely into
3245 // registers. (This is not what the doc says.)
3246 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3247 CallSeqStart.getNode()->getOperand(0),
3249 // This must go outside the CALLSEQ_START..END.
3250 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3251 CallSeqStart.getNode()->getOperand(1));
3252 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
3253 Chain = CallSeqStart = NewCallSeqStart;
3254 // And copy the pieces of it that fit into registers.
3255 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3256 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3257 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3258 if (GPR_idx != NumGPRs) {
3259 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3260 MachinePointerInfo(),
3261 false, false, false, 0);
3262 MemOpChains.push_back(Load.getValue(1));
3263 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3264 ArgOffset += PtrByteSize;
3266 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3273 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3274 default: llvm_unreachable("Unexpected ValueType for argument!");
3277 if (GPR_idx != NumGPRs) {
3278 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3280 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3281 isPPC64, isTailCall, false, MemOpChains,
3282 TailCallArguments, dl);
3284 ArgOffset += PtrByteSize;
3288 if (FPR_idx != NumFPRs) {
3289 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3292 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3293 MachinePointerInfo(), false, false, 0);
3294 MemOpChains.push_back(Store);
3296 // Float varargs are always shadowed in available integer registers
3297 if (GPR_idx != NumGPRs) {
3298 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3299 MachinePointerInfo(), false, false,
3301 MemOpChains.push_back(Load.getValue(1));
3302 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3304 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
3305 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3306 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3307 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3308 MachinePointerInfo(),
3309 false, false, false, 0);
3310 MemOpChains.push_back(Load.getValue(1));
3311 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3314 // If we have any FPRs remaining, we may also have GPRs remaining.
3315 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
3317 if (GPR_idx != NumGPRs)
3319 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
3320 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
3324 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3325 isPPC64, isTailCall, false, MemOpChains,
3326 TailCallArguments, dl);
3331 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
3338 // These go aligned on the stack, or in the corresponding R registers
3339 // when within range. The Darwin PPC ABI doc claims they also go in
3340 // V registers; in fact gcc does this only for arguments that are
3341 // prototyped, not for those that match the ... We do it for all
3342 // arguments, seems to work.
3343 while (ArgOffset % 16 !=0) {
3344 ArgOffset += PtrByteSize;
3345 if (GPR_idx != NumGPRs)
3348 // We could elide this store in the case where the object fits
3349 // entirely in R registers. Maybe later.
3350 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3351 DAG.getConstant(ArgOffset, PtrVT));
3352 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3353 MachinePointerInfo(), false, false, 0);
3354 MemOpChains.push_back(Store);
3355 if (VR_idx != NumVRs) {
3356 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
3357 MachinePointerInfo(),
3358 false, false, false, 0);
3359 MemOpChains.push_back(Load.getValue(1));
3360 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
3363 for (unsigned i=0; i<16; i+=PtrByteSize) {
3364 if (GPR_idx == NumGPRs)
3366 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
3367 DAG.getConstant(i, PtrVT));
3368 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
3369 false, false, false, 0);
3370 MemOpChains.push_back(Load.getValue(1));
3371 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3376 // Non-varargs Altivec params generally go in registers, but have
3377 // stack space allocated at the end.
3378 if (VR_idx != NumVRs) {
3379 // Doesn't have GPR space allocated.
3380 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
3381 } else if (nAltivecParamsAtEnd==0) {
3382 // We are emitting Altivec params in order.
3383 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3384 isPPC64, isTailCall, true, MemOpChains,
3385 TailCallArguments, dl);
3391 // If all Altivec parameters fit in registers, as they usually do,
3392 // they get stack space following the non-Altivec parameters. We
3393 // don't track this here because nobody below needs it.
3394 // If there are more Altivec parameters than fit in registers emit
3396 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
3398 // Offset is aligned; skip 1st 12 params which go in V registers.
3399 ArgOffset = ((ArgOffset+15)/16)*16;
3401 for (unsigned i = 0; i != NumOps; ++i) {
3402 SDValue Arg = OutVals[i];
3403 EVT ArgType = Outs[i].VT;
3404 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
3405 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
3408 // We are emitting Altivec params in order.
3409 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3410 isPPC64, isTailCall, true, MemOpChains,
3411 TailCallArguments, dl);
3418 if (!MemOpChains.empty())
3419 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3420 &MemOpChains[0], MemOpChains.size());
3422 // Check if this is an indirect call (MTCTR/BCTRL).
3423 // See PrepareCall() for more information about calls through function
3424 // pointers in the 64-bit SVR4 ABI.
3425 if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() &&
3426 !dyn_cast<GlobalAddressSDNode>(Callee) &&
3427 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3428 !isBLACompatibleAddress(Callee, DAG)) {
3429 // Load r2 into a virtual register and store it to the TOC save area.
3430 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
3431 // TOC save area offset.
3432 SDValue PtrOff = DAG.getIntPtrConstant(40);
3433 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3434 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
3438 // On Darwin, R12 must contain the address of an indirect callee. This does
3439 // not mean the MTCTR instruction must use R12; it's easier to model this as
3440 // an extra parameter, so do that.
3442 !dyn_cast<GlobalAddressSDNode>(Callee) &&
3443 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3444 !isBLACompatibleAddress(Callee, DAG))
3445 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
3446 PPC::R12), Callee));
3448 // Build a sequence of copy-to-reg nodes chained together with token chain
3449 // and flag operands which copy the outgoing args into the appropriate regs.
3451 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3452 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3453 RegsToPass[i].second, InFlag);
3454 InFlag = Chain.getValue(1);
3458 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
3459 FPOp, true, TailCallArguments);
3461 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3462 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3467 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3468 MachineFunction &MF, bool isVarArg,
3469 const SmallVectorImpl<ISD::OutputArg> &Outs,
3470 LLVMContext &Context) const {
3471 SmallVector<CCValAssign, 16> RVLocs;
3472 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
3474 return CCInfo.CheckReturn(Outs, RetCC_PPC);
3478 PPCTargetLowering::LowerReturn(SDValue Chain,
3479 CallingConv::ID CallConv, bool isVarArg,
3480 const SmallVectorImpl<ISD::OutputArg> &Outs,
3481 const SmallVectorImpl<SDValue> &OutVals,
3482 DebugLoc dl, SelectionDAG &DAG) const {
3484 SmallVector<CCValAssign, 16> RVLocs;
3485 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3486 getTargetMachine(), RVLocs, *DAG.getContext());
3487 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
3489 // If this is the first return lowered for this function, add the regs to the
3490 // liveout set for the function.
3491 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3492 for (unsigned i = 0; i != RVLocs.size(); ++i)
3493 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3498 // Copy the result values into the output registers.
3499 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3500 CCValAssign &VA = RVLocs[i];
3501 assert(VA.isRegLoc() && "Can only return in registers!");
3502 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3504 Flag = Chain.getValue(1);
3508 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
3510 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
3513 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
3514 const PPCSubtarget &Subtarget) const {
3515 // When we pop the dynamic allocation we need to restore the SP link.
3516 DebugLoc dl = Op.getDebugLoc();
3518 // Get the corect type for pointers.
3519 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3521 // Construct the stack pointer operand.
3522 bool isPPC64 = Subtarget.isPPC64();
3523 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
3524 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
3526 // Get the operands for the STACKRESTORE.
3527 SDValue Chain = Op.getOperand(0);
3528 SDValue SaveSP = Op.getOperand(1);
3530 // Load the old link SP.
3531 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
3532 MachinePointerInfo(),
3533 false, false, false, 0);
3535 // Restore the stack pointer.
3536 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
3538 // Store the old link SP.
3539 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
3546 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
3547 MachineFunction &MF = DAG.getMachineFunction();
3548 bool isPPC64 = PPCSubTarget.isPPC64();
3549 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3550 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3552 // Get current frame pointer save index. The users of this index will be
3553 // primarily DYNALLOC instructions.
3554 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3555 int RASI = FI->getReturnAddrSaveIndex();
3557 // If the frame pointer save index hasn't been defined yet.
3559 // Find out what the fix offset of the frame pointer save area.
3560 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
3561 // Allocate the frame index for frame pointer save area.
3562 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
3564 FI->setReturnAddrSaveIndex(RASI);
3566 return DAG.getFrameIndex(RASI, PtrVT);
3570 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
3571 MachineFunction &MF = DAG.getMachineFunction();
3572 bool isPPC64 = PPCSubTarget.isPPC64();
3573 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3574 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3576 // Get current frame pointer save index. The users of this index will be
3577 // primarily DYNALLOC instructions.
3578 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3579 int FPSI = FI->getFramePointerSaveIndex();
3581 // If the frame pointer save index hasn't been defined yet.
3583 // Find out what the fix offset of the frame pointer save area.
3584 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
3587 // Allocate the frame index for frame pointer save area.
3588 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
3590 FI->setFramePointerSaveIndex(FPSI);
3592 return DAG.getFrameIndex(FPSI, PtrVT);
3595 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3597 const PPCSubtarget &Subtarget) const {
3599 SDValue Chain = Op.getOperand(0);
3600 SDValue Size = Op.getOperand(1);
3601 DebugLoc dl = Op.getDebugLoc();
3603 // Get the corect type for pointers.
3604 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3606 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
3607 DAG.getConstant(0, PtrVT), Size);
3608 // Construct a node for the frame pointer save index.
3609 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
3610 // Build a DYNALLOC node.
3611 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
3612 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
3613 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
3616 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
3618 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3619 // Not FP? Not a fsel.
3620 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
3621 !Op.getOperand(2).getValueType().isFloatingPoint())
3624 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3626 // Cannot handle SETEQ/SETNE.
3627 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
3629 EVT ResVT = Op.getValueType();
3630 EVT CmpVT = Op.getOperand(0).getValueType();
3631 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3632 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
3633 DebugLoc dl = Op.getDebugLoc();
3635 // If the RHS of the comparison is a 0.0, we don't need to do the
3636 // subtraction at all.
3637 if (isFloatingPointZero(RHS))
3639 default: break; // SETUO etc aren't handled by fsel.
3642 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3645 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3646 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3647 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
3650 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3653 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3654 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3655 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
3656 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
3661 default: break; // SETUO etc aren't handled by fsel.
3664 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3665 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3666 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3667 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3670 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3671 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3672 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3673 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3676 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3677 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3678 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3679 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3682 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3683 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3684 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3685 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3690 // FIXME: Split this code up when LegalizeDAGTypes lands.
3691 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
3692 DebugLoc dl) const {
3693 assert(Op.getOperand(0).getValueType().isFloatingPoint());
3694 SDValue Src = Op.getOperand(0);
3695 if (Src.getValueType() == MVT::f32)
3696 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
3699 switch (Op.getValueType().getSimpleVT().SimpleTy) {
3700 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
3702 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
3707 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
3711 // Convert the FP value to an int value through memory.
3712 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
3714 // Emit a store to the stack slot.
3715 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
3716 MachinePointerInfo(), false, false, 0);
3718 // Result is a load from the stack slot. If loading 4 bytes, make sure to
3720 if (Op.getValueType() == MVT::i32)
3721 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
3722 DAG.getConstant(4, FIPtr.getValueType()));
3723 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(),
3724 false, false, false, 0);
3727 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op,
3728 SelectionDAG &DAG) const {
3729 DebugLoc dl = Op.getDebugLoc();
3730 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
3731 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
3734 if (Op.getOperand(0).getValueType() == MVT::i64) {
3735 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0));
3736 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
3737 if (Op.getValueType() == MVT::f32)
3738 FP = DAG.getNode(ISD::FP_ROUND, dl,
3739 MVT::f32, FP, DAG.getIntPtrConstant(0));
3743 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
3744 "Unhandled SINT_TO_FP type in custom expander!");
3745 // Since we only generate this in 64-bit mode, we can take advantage of
3746 // 64-bit registers. In particular, sign extend the input value into the
3747 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
3748 // then lfd it and fcfid it.
3749 MachineFunction &MF = DAG.getMachineFunction();
3750 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
3751 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
3752 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3753 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3755 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
3758 // STD the extended value into the stack slot.
3759 MachineMemOperand *MMO =
3760 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
3761 MachineMemOperand::MOStore, 8, 8);
3762 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
3764 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other),
3765 Ops, 4, MVT::i64, MMO);
3766 // Load the value as a double.
3767 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(),
3768 false, false, false, 0);
3770 // FCFID it and return it.
3771 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
3772 if (Op.getValueType() == MVT::f32)
3773 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
3777 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3778 SelectionDAG &DAG) const {
3779 DebugLoc dl = Op.getDebugLoc();
3781 The rounding mode is in bits 30:31 of FPSR, and has the following
3788 FLT_ROUNDS, on the other hand, expects the following:
3795 To perform the conversion, we do:
3796 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
3799 MachineFunction &MF = DAG.getMachineFunction();
3800 EVT VT = Op.getValueType();
3801 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3802 std::vector<EVT> NodeTys;
3803 SDValue MFFSreg, InFlag;
3805 // Save FP Control Word to register
3806 NodeTys.push_back(MVT::f64); // return register
3807 NodeTys.push_back(MVT::Glue); // unused in this context
3808 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
3810 // Save FP register to stack slot
3811 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
3812 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
3813 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
3814 StackSlot, MachinePointerInfo(), false, false,0);
3816 // Load FP Control Word from low 32 bits of stack slot.
3817 SDValue Four = DAG.getConstant(4, PtrVT);
3818 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
3819 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
3820 false, false, false, 0);
3822 // Transform as necessary
3824 DAG.getNode(ISD::AND, dl, MVT::i32,
3825 CWD, DAG.getConstant(3, MVT::i32));
3827 DAG.getNode(ISD::SRL, dl, MVT::i32,
3828 DAG.getNode(ISD::AND, dl, MVT::i32,
3829 DAG.getNode(ISD::XOR, dl, MVT::i32,
3830 CWD, DAG.getConstant(3, MVT::i32)),
3831 DAG.getConstant(3, MVT::i32)),
3832 DAG.getConstant(1, MVT::i32));
3835 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
3837 return DAG.getNode((VT.getSizeInBits() < 16 ?
3838 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3841 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3842 EVT VT = Op.getValueType();
3843 unsigned BitWidth = VT.getSizeInBits();
3844 DebugLoc dl = Op.getDebugLoc();
3845 assert(Op.getNumOperands() == 3 &&
3846 VT == Op.getOperand(1).getValueType() &&
3849 // Expand into a bunch of logical ops. Note that these ops
3850 // depend on the PPC behavior for oversized shift amounts.
3851 SDValue Lo = Op.getOperand(0);
3852 SDValue Hi = Op.getOperand(1);
3853 SDValue Amt = Op.getOperand(2);
3854 EVT AmtVT = Amt.getValueType();
3856 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3857 DAG.getConstant(BitWidth, AmtVT), Amt);
3858 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3859 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3860 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3861 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3862 DAG.getConstant(-BitWidth, AmtVT));
3863 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3864 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3865 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3866 SDValue OutOps[] = { OutLo, OutHi };
3867 return DAG.getMergeValues(OutOps, 2, dl);
3870 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3871 EVT VT = Op.getValueType();
3872 DebugLoc dl = Op.getDebugLoc();
3873 unsigned BitWidth = VT.getSizeInBits();
3874 assert(Op.getNumOperands() == 3 &&
3875 VT == Op.getOperand(1).getValueType() &&
3878 // Expand into a bunch of logical ops. Note that these ops
3879 // depend on the PPC behavior for oversized shift amounts.
3880 SDValue Lo = Op.getOperand(0);
3881 SDValue Hi = Op.getOperand(1);
3882 SDValue Amt = Op.getOperand(2);
3883 EVT AmtVT = Amt.getValueType();
3885 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3886 DAG.getConstant(BitWidth, AmtVT), Amt);
3887 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3888 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3889 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3890 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3891 DAG.getConstant(-BitWidth, AmtVT));
3892 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3893 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3894 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3895 SDValue OutOps[] = { OutLo, OutHi };
3896 return DAG.getMergeValues(OutOps, 2, dl);
3899 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
3900 DebugLoc dl = Op.getDebugLoc();
3901 EVT VT = Op.getValueType();
3902 unsigned BitWidth = VT.getSizeInBits();
3903 assert(Op.getNumOperands() == 3 &&
3904 VT == Op.getOperand(1).getValueType() &&
3907 // Expand into a bunch of logical ops, followed by a select_cc.
3908 SDValue Lo = Op.getOperand(0);
3909 SDValue Hi = Op.getOperand(1);
3910 SDValue Amt = Op.getOperand(2);
3911 EVT AmtVT = Amt.getValueType();
3913 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3914 DAG.getConstant(BitWidth, AmtVT), Amt);
3915 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3916 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3917 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3918 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3919 DAG.getConstant(-BitWidth, AmtVT));
3920 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3921 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3922 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
3923 Tmp4, Tmp6, ISD::SETLE);
3924 SDValue OutOps[] = { OutLo, OutHi };
3925 return DAG.getMergeValues(OutOps, 2, dl);
3928 //===----------------------------------------------------------------------===//
3929 // Vector related lowering.
3932 /// BuildSplatI - Build a canonical splati of Val with an element size of
3933 /// SplatSize. Cast the result to VT.
3934 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
3935 SelectionDAG &DAG, DebugLoc dl) {
3936 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3938 static const EVT VTys[] = { // canonical VT to use for each size.
3939 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3942 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3944 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3948 EVT CanonicalVT = VTys[SplatSize-1];
3950 // Build a canonical splat for this value.
3951 SDValue Elt = DAG.getConstant(Val, MVT::i32);
3952 SmallVector<SDValue, 8> Ops;
3953 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3954 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
3955 &Ops[0], Ops.size());
3956 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
3959 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3960 /// specified intrinsic ID.
3961 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3962 SelectionDAG &DAG, DebugLoc dl,
3963 EVT DestVT = MVT::Other) {
3964 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3965 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3966 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3969 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3970 /// specified intrinsic ID.
3971 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3972 SDValue Op2, SelectionDAG &DAG,
3973 DebugLoc dl, EVT DestVT = MVT::Other) {
3974 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3975 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3976 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3980 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3981 /// amount. The result has the specified value type.
3982 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3983 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3984 // Force LHS/RHS to be the right type.
3985 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
3986 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
3989 for (unsigned i = 0; i != 16; ++i)
3991 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
3992 return DAG.getNode(ISD::BITCAST, dl, VT, T);
3995 // If this is a case we can't handle, return null and let the default
3996 // expansion code take care of it. If we CAN select this case, and if it
3997 // selects to a single instruction, return Op. Otherwise, if we can codegen
3998 // this case more efficiently than a constant pool load, lower it to the
3999 // sequence of ops that should be used.
4000 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
4001 SelectionDAG &DAG) const {
4002 DebugLoc dl = Op.getDebugLoc();
4003 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
4004 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
4006 // Check if this is a splat of a constant value.
4007 APInt APSplatBits, APSplatUndef;
4008 unsigned SplatBitSize;
4010 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
4011 HasAnyUndefs, 0, true) || SplatBitSize > 32)
4014 unsigned SplatBits = APSplatBits.getZExtValue();
4015 unsigned SplatUndef = APSplatUndef.getZExtValue();
4016 unsigned SplatSize = SplatBitSize / 8;
4018 // First, handle single instruction cases.
4021 if (SplatBits == 0) {
4022 // Canonicalize all zero vectors to be v4i32.
4023 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
4024 SDValue Z = DAG.getConstant(0, MVT::i32);
4025 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
4026 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
4031 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
4032 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
4034 if (SextVal >= -16 && SextVal <= 15)
4035 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
4038 // Two instruction sequences.
4040 // If this value is in the range [-32,30] and is even, use:
4041 // tmp = VSPLTI[bhw], result = add tmp, tmp
4042 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
4043 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
4044 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
4045 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4048 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
4049 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
4051 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
4052 // Make -1 and vspltisw -1:
4053 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
4055 // Make the VSLW intrinsic, computing 0x8000_0000.
4056 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
4059 // xor by OnesV to invert it.
4060 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
4061 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4064 // Check to see if this is a wide variety of vsplti*, binop self cases.
4065 static const signed char SplatCsts[] = {
4066 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
4067 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
4070 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
4071 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
4072 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
4073 int i = SplatCsts[idx];
4075 // Figure out what shift amount will be used by altivec if shifted by i in
4077 unsigned TypeShiftAmt = i & (SplatBitSize-1);
4079 // vsplti + shl self.
4080 if (SextVal == (i << (int)TypeShiftAmt)) {
4081 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
4082 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4083 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
4084 Intrinsic::ppc_altivec_vslw
4086 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
4087 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4090 // vsplti + srl self.
4091 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
4092 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
4093 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4094 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
4095 Intrinsic::ppc_altivec_vsrw
4097 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
4098 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4101 // vsplti + sra self.
4102 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
4103 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
4104 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4105 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
4106 Intrinsic::ppc_altivec_vsraw
4108 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
4109 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4112 // vsplti + rol self.
4113 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
4114 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
4115 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
4116 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4117 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
4118 Intrinsic::ppc_altivec_vrlw
4120 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
4121 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4124 // t = vsplti c, result = vsldoi t, t, 1
4125 if (SextVal == ((i << 8) | (i < 0 ? 0xFF : 0))) {
4126 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
4127 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
4129 // t = vsplti c, result = vsldoi t, t, 2
4130 if (SextVal == ((i << 16) | (i < 0 ? 0xFFFF : 0))) {
4131 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
4132 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
4134 // t = vsplti c, result = vsldoi t, t, 3
4135 if (SextVal == ((i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
4136 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
4137 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
4141 // Three instruction sequences.
4143 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
4144 if (SextVal >= 0 && SextVal <= 31) {
4145 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
4146 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
4147 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
4148 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
4150 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
4151 if (SextVal >= -31 && SextVal <= 0) {
4152 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
4153 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
4154 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
4155 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
4161 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4162 /// the specified operations to build the shuffle.
4163 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4164 SDValue RHS, SelectionDAG &DAG,
4166 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4167 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4168 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4171 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4183 if (OpNum == OP_COPY) {
4184 if (LHSID == (1*9+2)*9+3) return LHS;
4185 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4189 SDValue OpLHS, OpRHS;
4190 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4191 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4195 default: llvm_unreachable("Unknown i32 permute!");
4197 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
4198 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
4199 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
4200 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
4203 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
4204 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
4205 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
4206 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
4209 for (unsigned i = 0; i != 16; ++i)
4210 ShufIdxs[i] = (i&3)+0;
4213 for (unsigned i = 0; i != 16; ++i)
4214 ShufIdxs[i] = (i&3)+4;
4217 for (unsigned i = 0; i != 16; ++i)
4218 ShufIdxs[i] = (i&3)+8;
4221 for (unsigned i = 0; i != 16; ++i)
4222 ShufIdxs[i] = (i&3)+12;
4225 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
4227 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
4229 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
4231 EVT VT = OpLHS.getValueType();
4232 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
4233 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
4234 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
4235 return DAG.getNode(ISD::BITCAST, dl, VT, T);
4238 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
4239 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
4240 /// return the code it can be lowered into. Worst case, it can always be
4241 /// lowered into a vperm.
4242 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4243 SelectionDAG &DAG) const {
4244 DebugLoc dl = Op.getDebugLoc();
4245 SDValue V1 = Op.getOperand(0);
4246 SDValue V2 = Op.getOperand(1);
4247 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4248 EVT VT = Op.getValueType();
4250 // Cases that are handled by instructions that take permute immediates
4251 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
4252 // selected by the instruction selector.
4253 if (V2.getOpcode() == ISD::UNDEF) {
4254 if (PPC::isSplatShuffleMask(SVOp, 1) ||
4255 PPC::isSplatShuffleMask(SVOp, 2) ||
4256 PPC::isSplatShuffleMask(SVOp, 4) ||
4257 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
4258 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
4259 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
4260 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
4261 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
4262 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
4263 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
4264 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
4265 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
4270 // Altivec has a variety of "shuffle immediates" that take two vector inputs
4271 // and produce a fixed permutation. If any of these match, do not lower to
4273 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
4274 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
4275 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
4276 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
4277 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
4278 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
4279 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
4280 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
4281 PPC::isVMRGHShuffleMask(SVOp, 4, false))
4284 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
4285 // perfect shuffle table to emit an optimal matching sequence.
4286 ArrayRef<int> PermMask = SVOp->getMask();
4288 unsigned PFIndexes[4];
4289 bool isFourElementShuffle = true;
4290 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
4291 unsigned EltNo = 8; // Start out undef.
4292 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
4293 if (PermMask[i*4+j] < 0)
4294 continue; // Undef, ignore it.
4296 unsigned ByteSource = PermMask[i*4+j];
4297 if ((ByteSource & 3) != j) {
4298 isFourElementShuffle = false;
4303 EltNo = ByteSource/4;
4304 } else if (EltNo != ByteSource/4) {
4305 isFourElementShuffle = false;
4309 PFIndexes[i] = EltNo;
4312 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
4313 // perfect shuffle vector to determine if it is cost effective to do this as
4314 // discrete instructions, or whether we should use a vperm.
4315 if (isFourElementShuffle) {
4316 // Compute the index in the perfect shuffle table.
4317 unsigned PFTableIndex =
4318 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4320 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4321 unsigned Cost = (PFEntry >> 30);
4323 // Determining when to avoid vperm is tricky. Many things affect the cost
4324 // of vperm, particularly how many times the perm mask needs to be computed.
4325 // For example, if the perm mask can be hoisted out of a loop or is already
4326 // used (perhaps because there are multiple permutes with the same shuffle
4327 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
4328 // the loop requires an extra register.
4330 // As a compromise, we only emit discrete instructions if the shuffle can be
4331 // generated in 3 or fewer operations. When we have loop information
4332 // available, if this block is within a loop, we should avoid using vperm
4333 // for 3-operation perms and use a constant pool load instead.
4335 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4338 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
4339 // vector that will get spilled to the constant pool.
4340 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
4342 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
4343 // that it is in input element units, not in bytes. Convert now.
4344 EVT EltVT = V1.getValueType().getVectorElementType();
4345 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
4347 SmallVector<SDValue, 16> ResultMask;
4348 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
4349 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
4351 for (unsigned j = 0; j != BytesPerElement; ++j)
4352 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
4356 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
4357 &ResultMask[0], ResultMask.size());
4358 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
4361 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
4362 /// altivec comparison. If it is, return true and fill in Opc/isDot with
4363 /// information about the intrinsic.
4364 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
4366 unsigned IntrinsicID =
4367 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
4370 switch (IntrinsicID) {
4371 default: return false;
4372 // Comparison predicates.
4373 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
4374 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
4375 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
4376 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
4377 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
4378 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
4379 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
4380 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
4381 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
4382 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
4383 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
4384 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
4385 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
4387 // Normal Comparisons.
4388 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
4389 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
4390 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
4391 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
4392 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
4393 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
4394 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
4395 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
4396 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
4397 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
4398 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
4399 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
4400 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
4405 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
4406 /// lower, do it, otherwise return null.
4407 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
4408 SelectionDAG &DAG) const {
4409 // If this is a lowered altivec predicate compare, CompareOpc is set to the
4410 // opcode number of the comparison.
4411 DebugLoc dl = Op.getDebugLoc();
4414 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
4415 return SDValue(); // Don't custom lower most intrinsics.
4417 // If this is a non-dot comparison, make the VCMP node and we are done.
4419 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
4420 Op.getOperand(1), Op.getOperand(2),
4421 DAG.getConstant(CompareOpc, MVT::i32));
4422 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
4425 // Create the PPCISD altivec 'dot' comparison node.
4427 Op.getOperand(2), // LHS
4428 Op.getOperand(3), // RHS
4429 DAG.getConstant(CompareOpc, MVT::i32)
4431 std::vector<EVT> VTs;
4432 VTs.push_back(Op.getOperand(2).getValueType());
4433 VTs.push_back(MVT::Glue);
4434 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
4436 // Now that we have the comparison, emit a copy from the CR to a GPR.
4437 // This is flagged to the above dot comparison.
4438 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
4439 DAG.getRegister(PPC::CR6, MVT::i32),
4440 CompNode.getValue(1));
4442 // Unpack the result based on how the target uses it.
4443 unsigned BitNo; // Bit # of CR6.
4444 bool InvertBit; // Invert result?
4445 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
4446 default: // Can't happen, don't crash on invalid number though.
4447 case 0: // Return the value of the EQ bit of CR6.
4448 BitNo = 0; InvertBit = false;
4450 case 1: // Return the inverted value of the EQ bit of CR6.
4451 BitNo = 0; InvertBit = true;
4453 case 2: // Return the value of the LT bit of CR6.
4454 BitNo = 2; InvertBit = false;
4456 case 3: // Return the inverted value of the LT bit of CR6.
4457 BitNo = 2; InvertBit = true;
4461 // Shift the bit into the low position.
4462 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
4463 DAG.getConstant(8-(3-BitNo), MVT::i32));
4465 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
4466 DAG.getConstant(1, MVT::i32));
4468 // If we are supposed to, toggle the bit.
4470 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
4471 DAG.getConstant(1, MVT::i32));
4475 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
4476 SelectionDAG &DAG) const {
4477 DebugLoc dl = Op.getDebugLoc();
4478 // Create a stack slot that is 16-byte aligned.
4479 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4480 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
4481 EVT PtrVT = getPointerTy();
4482 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4484 // Store the input value into Value#0 of the stack slot.
4485 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
4486 Op.getOperand(0), FIdx, MachinePointerInfo(),
4489 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
4490 false, false, false, 0);
4493 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
4494 DebugLoc dl = Op.getDebugLoc();
4495 if (Op.getValueType() == MVT::v4i32) {
4496 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4498 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
4499 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
4501 SDValue RHSSwap = // = vrlw RHS, 16
4502 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
4504 // Shrinkify inputs to v8i16.
4505 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
4506 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
4507 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
4509 // Low parts multiplied together, generating 32-bit results (we ignore the
4511 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
4512 LHS, RHS, DAG, dl, MVT::v4i32);
4514 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
4515 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
4516 // Shift the high parts up 16 bits.
4517 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
4519 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
4520 } else if (Op.getValueType() == MVT::v8i16) {
4521 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4523 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
4525 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
4526 LHS, RHS, Zero, DAG, dl);
4527 } else if (Op.getValueType() == MVT::v16i8) {
4528 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4530 // Multiply the even 8-bit parts, producing 16-bit sums.
4531 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
4532 LHS, RHS, DAG, dl, MVT::v8i16);
4533 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
4535 // Multiply the odd 8-bit parts, producing 16-bit sums.
4536 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
4537 LHS, RHS, DAG, dl, MVT::v8i16);
4538 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
4540 // Merge the results together.
4542 for (unsigned i = 0; i != 8; ++i) {
4544 Ops[i*2+1] = 2*i+1+16;
4546 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
4548 llvm_unreachable("Unknown mul to lower!");
4552 /// LowerOperation - Provide custom lowering hooks for some operations.
4554 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4555 switch (Op.getOpcode()) {
4556 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
4557 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4558 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4559 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4560 case ISD::GlobalTLSAddress: llvm_unreachable("TLS not implemented for PPC");
4561 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4562 case ISD::SETCC: return LowerSETCC(Op, DAG);
4563 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
4564 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
4566 return LowerVASTART(Op, DAG, PPCSubTarget);
4569 return LowerVAARG(Op, DAG, PPCSubTarget);
4571 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
4572 case ISD::DYNAMIC_STACKALLOC:
4573 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
4575 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4576 case ISD::FP_TO_UINT:
4577 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
4579 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4580 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4582 // Lower 64-bit shifts.
4583 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
4584 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
4585 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
4587 // Vector-related lowering.
4588 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4589 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4590 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4591 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4592 case ISD::MUL: return LowerMUL(Op, DAG);
4594 // Frame & Return address.
4595 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4596 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4600 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
4601 SmallVectorImpl<SDValue>&Results,
4602 SelectionDAG &DAG) const {
4603 const TargetMachine &TM = getTargetMachine();
4604 DebugLoc dl = N->getDebugLoc();
4605 switch (N->getOpcode()) {
4607 llvm_unreachable("Do not know how to custom type legalize this operation!");
4609 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
4610 || TM.getSubtarget<PPCSubtarget>().isPPC64())
4613 EVT VT = N->getValueType(0);
4615 if (VT == MVT::i64) {
4616 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
4618 Results.push_back(NewNode);
4619 Results.push_back(NewNode.getValue(1));
4623 case ISD::FP_ROUND_INREG: {
4624 assert(N->getValueType(0) == MVT::ppcf128);
4625 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
4626 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4627 MVT::f64, N->getOperand(0),
4628 DAG.getIntPtrConstant(0));
4629 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4630 MVT::f64, N->getOperand(0),
4631 DAG.getIntPtrConstant(1));
4633 // This sequence changes FPSCR to do round-to-zero, adds the two halves
4634 // of the long double, and puts FPSCR back the way it was. We do not
4635 // actually model FPSCR.
4636 std::vector<EVT> NodeTys;
4637 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
4639 NodeTys.push_back(MVT::f64); // Return register
4640 NodeTys.push_back(MVT::Glue); // Returns a flag for later insns
4641 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4642 MFFSreg = Result.getValue(0);
4643 InFlag = Result.getValue(1);
4646 NodeTys.push_back(MVT::Glue); // Returns a flag
4647 Ops[0] = DAG.getConstant(31, MVT::i32);
4649 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
4650 InFlag = Result.getValue(0);
4653 NodeTys.push_back(MVT::Glue); // Returns a flag
4654 Ops[0] = DAG.getConstant(30, MVT::i32);
4656 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
4657 InFlag = Result.getValue(0);
4660 NodeTys.push_back(MVT::f64); // result of add
4661 NodeTys.push_back(MVT::Glue); // Returns a flag
4665 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
4666 FPreg = Result.getValue(0);
4667 InFlag = Result.getValue(1);
4670 NodeTys.push_back(MVT::f64);
4671 Ops[0] = DAG.getConstant(1, MVT::i32);
4675 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
4676 FPreg = Result.getValue(0);
4678 // We know the low half is about to be thrown away, so just use something
4680 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
4684 case ISD::FP_TO_SINT:
4685 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
4691 //===----------------------------------------------------------------------===//
4692 // Other Lowering Code
4693 //===----------------------------------------------------------------------===//
4696 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4697 bool is64bit, unsigned BinOpcode) const {
4698 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4699 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4701 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4702 MachineFunction *F = BB->getParent();
4703 MachineFunction::iterator It = BB;
4706 unsigned dest = MI->getOperand(0).getReg();
4707 unsigned ptrA = MI->getOperand(1).getReg();
4708 unsigned ptrB = MI->getOperand(2).getReg();
4709 unsigned incr = MI->getOperand(3).getReg();
4710 DebugLoc dl = MI->getDebugLoc();
4712 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4713 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4714 F->insert(It, loopMBB);
4715 F->insert(It, exitMBB);
4716 exitMBB->splice(exitMBB->begin(), BB,
4717 llvm::next(MachineBasicBlock::iterator(MI)),
4719 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4721 MachineRegisterInfo &RegInfo = F->getRegInfo();
4722 unsigned TmpReg = (!BinOpcode) ? incr :
4723 RegInfo.createVirtualRegister(
4724 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4725 (const TargetRegisterClass *) &PPC::GPRCRegClass);
4729 // fallthrough --> loopMBB
4730 BB->addSuccessor(loopMBB);
4733 // l[wd]arx dest, ptr
4734 // add r0, dest, incr
4735 // st[wd]cx. r0, ptr
4737 // fallthrough --> exitMBB
4739 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4740 .addReg(ptrA).addReg(ptrB);
4742 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
4743 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4744 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
4745 BuildMI(BB, dl, TII->get(PPC::BCC))
4746 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4747 BB->addSuccessor(loopMBB);
4748 BB->addSuccessor(exitMBB);
4757 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
4758 MachineBasicBlock *BB,
4759 bool is8bit, // operation
4760 unsigned BinOpcode) const {
4761 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4762 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4763 // In 64 bit mode we have to use 64 bits for addresses, even though the
4764 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
4765 // registers without caring whether they're 32 or 64, but here we're
4766 // doing actual arithmetic on the addresses.
4767 bool is64bit = PPCSubTarget.isPPC64();
4768 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
4770 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4771 MachineFunction *F = BB->getParent();
4772 MachineFunction::iterator It = BB;
4775 unsigned dest = MI->getOperand(0).getReg();
4776 unsigned ptrA = MI->getOperand(1).getReg();
4777 unsigned ptrB = MI->getOperand(2).getReg();
4778 unsigned incr = MI->getOperand(3).getReg();
4779 DebugLoc dl = MI->getDebugLoc();
4781 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4782 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4783 F->insert(It, loopMBB);
4784 F->insert(It, exitMBB);
4785 exitMBB->splice(exitMBB->begin(), BB,
4786 llvm::next(MachineBasicBlock::iterator(MI)),
4788 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4790 MachineRegisterInfo &RegInfo = F->getRegInfo();
4791 const TargetRegisterClass *RC =
4792 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4793 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4794 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4795 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4796 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4797 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4798 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4799 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4800 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4801 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4802 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
4803 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4804 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4806 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
4810 // fallthrough --> loopMBB
4811 BB->addSuccessor(loopMBB);
4813 // The 4-byte load must be aligned, while a char or short may be
4814 // anywhere in the word. Hence all this nasty bookkeeping code.
4815 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4816 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4817 // xori shift, shift1, 24 [16]
4818 // rlwinm ptr, ptr1, 0, 0, 29
4819 // slw incr2, incr, shift
4820 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4821 // slw mask, mask2, shift
4823 // lwarx tmpDest, ptr
4824 // add tmp, tmpDest, incr2
4825 // andc tmp2, tmpDest, mask
4826 // and tmp3, tmp, mask
4827 // or tmp4, tmp3, tmp2
4830 // fallthrough --> exitMBB
4831 // srw dest, tmpDest, shift
4832 if (ptrA != ZeroReg) {
4833 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4834 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4835 .addReg(ptrA).addReg(ptrB);
4839 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4840 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4841 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4842 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4844 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4845 .addReg(Ptr1Reg).addImm(0).addImm(61);
4847 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4848 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4849 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
4850 .addReg(incr).addReg(ShiftReg);
4852 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4854 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4855 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
4857 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4858 .addReg(Mask2Reg).addReg(ShiftReg);
4861 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4862 .addReg(ZeroReg).addReg(PtrReg);
4864 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
4865 .addReg(Incr2Reg).addReg(TmpDestReg);
4866 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4867 .addReg(TmpDestReg).addReg(MaskReg);
4868 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4869 .addReg(TmpReg).addReg(MaskReg);
4870 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4871 .addReg(Tmp3Reg).addReg(Tmp2Reg);
4872 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4873 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
4874 BuildMI(BB, dl, TII->get(PPC::BCC))
4875 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4876 BB->addSuccessor(loopMBB);
4877 BB->addSuccessor(exitMBB);
4882 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
4888 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4889 MachineBasicBlock *BB) const {
4890 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4892 // To "insert" these instructions we actually have to insert their
4893 // control-flow patterns.
4894 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4895 MachineFunction::iterator It = BB;
4898 MachineFunction *F = BB->getParent();
4900 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4901 MI->getOpcode() == PPC::SELECT_CC_I8 ||
4902 MI->getOpcode() == PPC::SELECT_CC_F4 ||
4903 MI->getOpcode() == PPC::SELECT_CC_F8 ||
4904 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4906 // The incoming instruction knows the destination vreg to set, the
4907 // condition code register to branch on, the true/false values to
4908 // select between, and a branch opcode to use.
4913 // cmpTY ccX, r1, r2
4915 // fallthrough --> copy0MBB
4916 MachineBasicBlock *thisMBB = BB;
4917 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4918 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4919 unsigned SelectPred = MI->getOperand(4).getImm();
4920 DebugLoc dl = MI->getDebugLoc();
4921 F->insert(It, copy0MBB);
4922 F->insert(It, sinkMBB);
4924 // Transfer the remainder of BB and its successor edges to sinkMBB.
4925 sinkMBB->splice(sinkMBB->begin(), BB,
4926 llvm::next(MachineBasicBlock::iterator(MI)),
4928 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4930 // Next, add the true and fallthrough blocks as its successors.
4931 BB->addSuccessor(copy0MBB);
4932 BB->addSuccessor(sinkMBB);
4934 BuildMI(BB, dl, TII->get(PPC::BCC))
4935 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4938 // %FalseValue = ...
4939 // # fallthrough to sinkMBB
4942 // Update machine-CFG edges
4943 BB->addSuccessor(sinkMBB);
4946 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4949 BuildMI(*BB, BB->begin(), dl,
4950 TII->get(PPC::PHI), MI->getOperand(0).getReg())
4951 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4952 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4954 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4955 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4956 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4957 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4958 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4959 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4960 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4961 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4963 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4964 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4965 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4966 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4967 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4968 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4969 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4970 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4972 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4973 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4974 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4975 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4976 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4977 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4978 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4979 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4981 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4982 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4983 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4984 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4985 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4986 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4987 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4988 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4990 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4991 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
4992 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4993 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
4994 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4995 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
4996 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4997 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
4999 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
5000 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
5001 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
5002 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
5003 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
5004 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
5005 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
5006 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
5008 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
5009 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
5010 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
5011 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
5012 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
5013 BB = EmitAtomicBinary(MI, BB, false, 0);
5014 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
5015 BB = EmitAtomicBinary(MI, BB, true, 0);
5017 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
5018 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
5019 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
5021 unsigned dest = MI->getOperand(0).getReg();
5022 unsigned ptrA = MI->getOperand(1).getReg();
5023 unsigned ptrB = MI->getOperand(2).getReg();
5024 unsigned oldval = MI->getOperand(3).getReg();
5025 unsigned newval = MI->getOperand(4).getReg();
5026 DebugLoc dl = MI->getDebugLoc();
5028 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
5029 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
5030 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
5031 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5032 F->insert(It, loop1MBB);
5033 F->insert(It, loop2MBB);
5034 F->insert(It, midMBB);
5035 F->insert(It, exitMBB);
5036 exitMBB->splice(exitMBB->begin(), BB,
5037 llvm::next(MachineBasicBlock::iterator(MI)),
5039 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5043 // fallthrough --> loopMBB
5044 BB->addSuccessor(loop1MBB);
5047 // l[wd]arx dest, ptr
5048 // cmp[wd] dest, oldval
5051 // st[wd]cx. newval, ptr
5055 // st[wd]cx. dest, ptr
5058 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5059 .addReg(ptrA).addReg(ptrB);
5060 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
5061 .addReg(oldval).addReg(dest);
5062 BuildMI(BB, dl, TII->get(PPC::BCC))
5063 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
5064 BB->addSuccessor(loop2MBB);
5065 BB->addSuccessor(midMBB);
5068 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5069 .addReg(newval).addReg(ptrA).addReg(ptrB);
5070 BuildMI(BB, dl, TII->get(PPC::BCC))
5071 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
5072 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
5073 BB->addSuccessor(loop1MBB);
5074 BB->addSuccessor(exitMBB);
5077 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5078 .addReg(dest).addReg(ptrA).addReg(ptrB);
5079 BB->addSuccessor(exitMBB);
5084 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
5085 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
5086 // We must use 64-bit registers for addresses when targeting 64-bit,
5087 // since we're actually doing arithmetic on them. Other registers
5089 bool is64bit = PPCSubTarget.isPPC64();
5090 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
5092 unsigned dest = MI->getOperand(0).getReg();
5093 unsigned ptrA = MI->getOperand(1).getReg();
5094 unsigned ptrB = MI->getOperand(2).getReg();
5095 unsigned oldval = MI->getOperand(3).getReg();
5096 unsigned newval = MI->getOperand(4).getReg();
5097 DebugLoc dl = MI->getDebugLoc();
5099 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
5100 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
5101 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
5102 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5103 F->insert(It, loop1MBB);
5104 F->insert(It, loop2MBB);
5105 F->insert(It, midMBB);
5106 F->insert(It, exitMBB);
5107 exitMBB->splice(exitMBB->begin(), BB,
5108 llvm::next(MachineBasicBlock::iterator(MI)),
5110 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5112 MachineRegisterInfo &RegInfo = F->getRegInfo();
5113 const TargetRegisterClass *RC =
5114 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5115 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5116 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5117 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5118 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5119 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
5120 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
5121 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
5122 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
5123 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
5124 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
5125 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
5126 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
5127 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
5128 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
5130 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
5131 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
5134 // fallthrough --> loopMBB
5135 BB->addSuccessor(loop1MBB);
5137 // The 4-byte load must be aligned, while a char or short may be
5138 // anywhere in the word. Hence all this nasty bookkeeping code.
5139 // add ptr1, ptrA, ptrB [copy if ptrA==0]
5140 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
5141 // xori shift, shift1, 24 [16]
5142 // rlwinm ptr, ptr1, 0, 0, 29
5143 // slw newval2, newval, shift
5144 // slw oldval2, oldval,shift
5145 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
5146 // slw mask, mask2, shift
5147 // and newval3, newval2, mask
5148 // and oldval3, oldval2, mask
5150 // lwarx tmpDest, ptr
5151 // and tmp, tmpDest, mask
5152 // cmpw tmp, oldval3
5155 // andc tmp2, tmpDest, mask
5156 // or tmp4, tmp2, newval3
5161 // stwcx. tmpDest, ptr
5163 // srw dest, tmpDest, shift
5164 if (ptrA != ZeroReg) {
5165 Ptr1Reg = RegInfo.createVirtualRegister(RC);
5166 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
5167 .addReg(ptrA).addReg(ptrB);
5171 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5172 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
5173 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5174 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
5176 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
5177 .addReg(Ptr1Reg).addImm(0).addImm(61);
5179 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
5180 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
5181 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
5182 .addReg(newval).addReg(ShiftReg);
5183 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
5184 .addReg(oldval).addReg(ShiftReg);
5186 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
5188 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
5189 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
5190 .addReg(Mask3Reg).addImm(65535);
5192 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
5193 .addReg(Mask2Reg).addReg(ShiftReg);
5194 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
5195 .addReg(NewVal2Reg).addReg(MaskReg);
5196 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
5197 .addReg(OldVal2Reg).addReg(MaskReg);
5200 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
5201 .addReg(ZeroReg).addReg(PtrReg);
5202 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
5203 .addReg(TmpDestReg).addReg(MaskReg);
5204 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
5205 .addReg(TmpReg).addReg(OldVal3Reg);
5206 BuildMI(BB, dl, TII->get(PPC::BCC))
5207 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
5208 BB->addSuccessor(loop2MBB);
5209 BB->addSuccessor(midMBB);
5212 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
5213 .addReg(TmpDestReg).addReg(MaskReg);
5214 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
5215 .addReg(Tmp2Reg).addReg(NewVal3Reg);
5216 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
5217 .addReg(ZeroReg).addReg(PtrReg);
5218 BuildMI(BB, dl, TII->get(PPC::BCC))
5219 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
5220 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
5221 BB->addSuccessor(loop1MBB);
5222 BB->addSuccessor(exitMBB);
5225 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
5226 .addReg(ZeroReg).addReg(PtrReg);
5227 BB->addSuccessor(exitMBB);
5232 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
5235 llvm_unreachable("Unexpected instr type to insert");
5238 MI->eraseFromParent(); // The pseudo instruction is gone now.
5242 //===----------------------------------------------------------------------===//
5243 // Target Optimization Hooks
5244 //===----------------------------------------------------------------------===//
5246 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
5247 DAGCombinerInfo &DCI) const {
5248 const TargetMachine &TM = getTargetMachine();
5249 SelectionDAG &DAG = DCI.DAG;
5250 DebugLoc dl = N->getDebugLoc();
5251 switch (N->getOpcode()) {
5254 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5255 if (C->isNullValue()) // 0 << V -> 0.
5256 return N->getOperand(0);
5260 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5261 if (C->isNullValue()) // 0 >>u V -> 0.
5262 return N->getOperand(0);
5266 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5267 if (C->isNullValue() || // 0 >>s V -> 0.
5268 C->isAllOnesValue()) // -1 >>s V -> -1.
5269 return N->getOperand(0);
5273 case ISD::SINT_TO_FP:
5274 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
5275 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
5276 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
5277 // We allow the src/dst to be either f32/f64, but the intermediate
5278 // type must be i64.
5279 if (N->getOperand(0).getValueType() == MVT::i64 &&
5280 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
5281 SDValue Val = N->getOperand(0).getOperand(0);
5282 if (Val.getValueType() == MVT::f32) {
5283 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5284 DCI.AddToWorklist(Val.getNode());
5287 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
5288 DCI.AddToWorklist(Val.getNode());
5289 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
5290 DCI.AddToWorklist(Val.getNode());
5291 if (N->getValueType(0) == MVT::f32) {
5292 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
5293 DAG.getIntPtrConstant(0));
5294 DCI.AddToWorklist(Val.getNode());
5297 } else if (N->getOperand(0).getValueType() == MVT::i32) {
5298 // If the intermediate type is i32, we can avoid the load/store here
5305 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
5306 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
5307 !cast<StoreSDNode>(N)->isTruncatingStore() &&
5308 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
5309 N->getOperand(1).getValueType() == MVT::i32 &&
5310 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
5311 SDValue Val = N->getOperand(1).getOperand(0);
5312 if (Val.getValueType() == MVT::f32) {
5313 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5314 DCI.AddToWorklist(Val.getNode());
5316 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
5317 DCI.AddToWorklist(Val.getNode());
5319 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
5320 N->getOperand(2), N->getOperand(3));
5321 DCI.AddToWorklist(Val.getNode());
5325 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
5326 if (cast<StoreSDNode>(N)->isUnindexed() &&
5327 N->getOperand(1).getOpcode() == ISD::BSWAP &&
5328 N->getOperand(1).getNode()->hasOneUse() &&
5329 (N->getOperand(1).getValueType() == MVT::i32 ||
5330 N->getOperand(1).getValueType() == MVT::i16)) {
5331 SDValue BSwapOp = N->getOperand(1).getOperand(0);
5332 // Do an any-extend to 32-bits if this is a half-word input.
5333 if (BSwapOp.getValueType() == MVT::i16)
5334 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
5337 N->getOperand(0), BSwapOp, N->getOperand(2),
5338 DAG.getValueType(N->getOperand(1).getValueType())
5341 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
5342 Ops, array_lengthof(Ops),
5343 cast<StoreSDNode>(N)->getMemoryVT(),
5344 cast<StoreSDNode>(N)->getMemOperand());
5348 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
5349 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
5350 N->getOperand(0).hasOneUse() &&
5351 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
5352 SDValue Load = N->getOperand(0);
5353 LoadSDNode *LD = cast<LoadSDNode>(Load);
5354 // Create the byte-swapping load.
5356 LD->getChain(), // Chain
5357 LD->getBasePtr(), // Ptr
5358 DAG.getValueType(N->getValueType(0)) // VT
5361 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
5362 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3,
5363 LD->getMemoryVT(), LD->getMemOperand());
5365 // If this is an i16 load, insert the truncate.
5366 SDValue ResVal = BSLoad;
5367 if (N->getValueType(0) == MVT::i16)
5368 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
5370 // First, combine the bswap away. This makes the value produced by the
5372 DCI.CombineTo(N, ResVal);
5374 // Next, combine the load away, we give it a bogus result value but a real
5375 // chain result. The result value is dead because the bswap is dead.
5376 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
5378 // Return N so it doesn't get rechecked!
5379 return SDValue(N, 0);
5383 case PPCISD::VCMP: {
5384 // If a VCMPo node already exists with exactly the same operands as this
5385 // node, use its result instead of this node (VCMPo computes both a CR6 and
5386 // a normal output).
5388 if (!N->getOperand(0).hasOneUse() &&
5389 !N->getOperand(1).hasOneUse() &&
5390 !N->getOperand(2).hasOneUse()) {
5392 // Scan all of the users of the LHS, looking for VCMPo's that match.
5393 SDNode *VCMPoNode = 0;
5395 SDNode *LHSN = N->getOperand(0).getNode();
5396 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
5398 if (UI->getOpcode() == PPCISD::VCMPo &&
5399 UI->getOperand(1) == N->getOperand(1) &&
5400 UI->getOperand(2) == N->getOperand(2) &&
5401 UI->getOperand(0) == N->getOperand(0)) {
5406 // If there is no VCMPo node, or if the flag value has a single use, don't
5408 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
5411 // Look at the (necessarily single) use of the flag value. If it has a
5412 // chain, this transformation is more complex. Note that multiple things
5413 // could use the value result, which we should ignore.
5414 SDNode *FlagUser = 0;
5415 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
5416 FlagUser == 0; ++UI) {
5417 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
5419 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
5420 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
5427 // If the user is a MFCR instruction, we know this is safe. Otherwise we
5428 // give up for right now.
5429 if (FlagUser->getOpcode() == PPCISD::MFCR)
5430 return SDValue(VCMPoNode, 0);
5435 // If this is a branch on an altivec predicate comparison, lower this so
5436 // that we don't have to do a MFCR: instead, branch directly on CR6. This
5437 // lowering is done pre-legalize, because the legalizer lowers the predicate
5438 // compare down to code that is difficult to reassemble.
5439 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
5440 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
5444 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
5445 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
5446 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
5447 assert(isDot && "Can't compare against a vector result!");
5449 // If this is a comparison against something other than 0/1, then we know
5450 // that the condition is never/always true.
5451 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
5452 if (Val != 0 && Val != 1) {
5453 if (CC == ISD::SETEQ) // Cond never true, remove branch.
5454 return N->getOperand(0);
5455 // Always !=, turn it into an unconditional branch.
5456 return DAG.getNode(ISD::BR, dl, MVT::Other,
5457 N->getOperand(0), N->getOperand(4));
5460 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
5462 // Create the PPCISD altivec 'dot' comparison node.
5463 std::vector<EVT> VTs;
5465 LHS.getOperand(2), // LHS of compare
5466 LHS.getOperand(3), // RHS of compare
5467 DAG.getConstant(CompareOpc, MVT::i32)
5469 VTs.push_back(LHS.getOperand(2).getValueType());
5470 VTs.push_back(MVT::Glue);
5471 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5473 // Unpack the result based on how the target uses it.
5474 PPC::Predicate CompOpc;
5475 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
5476 default: // Can't happen, don't crash on invalid number though.
5477 case 0: // Branch on the value of the EQ bit of CR6.
5478 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
5480 case 1: // Branch on the inverted value of the EQ bit of CR6.
5481 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
5483 case 2: // Branch on the value of the LT bit of CR6.
5484 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
5486 case 3: // Branch on the inverted value of the LT bit of CR6.
5487 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
5491 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
5492 DAG.getConstant(CompOpc, MVT::i32),
5493 DAG.getRegister(PPC::CR6, MVT::i32),
5494 N->getOperand(4), CompNode.getValue(1));
5503 //===----------------------------------------------------------------------===//
5504 // Inline Assembly Support
5505 //===----------------------------------------------------------------------===//
5507 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5511 const SelectionDAG &DAG,
5512 unsigned Depth) const {
5513 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5514 switch (Op.getOpcode()) {
5516 case PPCISD::LBRX: {
5517 // lhbrx is known to have the top bits cleared out.
5518 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
5519 KnownZero = 0xFFFF0000;
5522 case ISD::INTRINSIC_WO_CHAIN: {
5523 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
5525 case Intrinsic::ppc_altivec_vcmpbfp_p:
5526 case Intrinsic::ppc_altivec_vcmpeqfp_p:
5527 case Intrinsic::ppc_altivec_vcmpequb_p:
5528 case Intrinsic::ppc_altivec_vcmpequh_p:
5529 case Intrinsic::ppc_altivec_vcmpequw_p:
5530 case Intrinsic::ppc_altivec_vcmpgefp_p:
5531 case Intrinsic::ppc_altivec_vcmpgtfp_p:
5532 case Intrinsic::ppc_altivec_vcmpgtsb_p:
5533 case Intrinsic::ppc_altivec_vcmpgtsh_p:
5534 case Intrinsic::ppc_altivec_vcmpgtsw_p:
5535 case Intrinsic::ppc_altivec_vcmpgtub_p:
5536 case Intrinsic::ppc_altivec_vcmpgtuh_p:
5537 case Intrinsic::ppc_altivec_vcmpgtuw_p:
5538 KnownZero = ~1U; // All bits but the low one are known to be zero.
5546 /// getConstraintType - Given a constraint, return the type of
5547 /// constraint it is for this target.
5548 PPCTargetLowering::ConstraintType
5549 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
5550 if (Constraint.size() == 1) {
5551 switch (Constraint[0]) {
5558 return C_RegisterClass;
5561 return TargetLowering::getConstraintType(Constraint);
5564 /// Examine constraint type and operand type and determine a weight value.
5565 /// This object must already have been set up with the operand type
5566 /// and the current alternative constraint selected.
5567 TargetLowering::ConstraintWeight
5568 PPCTargetLowering::getSingleConstraintMatchWeight(
5569 AsmOperandInfo &info, const char *constraint) const {
5570 ConstraintWeight weight = CW_Invalid;
5571 Value *CallOperandVal = info.CallOperandVal;
5572 // If we don't have a value, we can't do a match,
5573 // but allow it at the lowest weight.
5574 if (CallOperandVal == NULL)
5576 Type *type = CallOperandVal->getType();
5577 // Look at the constraint type.
5578 switch (*constraint) {
5580 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
5583 if (type->isIntegerTy())
5584 weight = CW_Register;
5587 if (type->isFloatTy())
5588 weight = CW_Register;
5591 if (type->isDoubleTy())
5592 weight = CW_Register;
5595 if (type->isVectorTy())
5596 weight = CW_Register;
5599 weight = CW_Register;
5605 std::pair<unsigned, const TargetRegisterClass*>
5606 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5608 if (Constraint.size() == 1) {
5609 // GCC RS6000 Constraint Letters
5610 switch (Constraint[0]) {
5613 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
5614 return std::make_pair(0U, PPC::G8RCRegisterClass);
5615 return std::make_pair(0U, PPC::GPRCRegisterClass);
5618 return std::make_pair(0U, PPC::F4RCRegisterClass);
5619 else if (VT == MVT::f64)
5620 return std::make_pair(0U, PPC::F8RCRegisterClass);
5623 return std::make_pair(0U, PPC::VRRCRegisterClass);
5625 return std::make_pair(0U, PPC::CRRCRegisterClass);
5629 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5633 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5634 /// vector. If it is invalid, don't add anything to Ops.
5635 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5636 std::string &Constraint,
5637 std::vector<SDValue>&Ops,
5638 SelectionDAG &DAG) const {
5639 SDValue Result(0,0);
5641 // Only support length 1 constraints.
5642 if (Constraint.length() > 1) return;
5644 char Letter = Constraint[0];
5655 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
5656 if (!CST) return; // Must be an immediate to match.
5657 unsigned Value = CST->getZExtValue();
5659 default: llvm_unreachable("Unknown constraint letter!");
5660 case 'I': // "I" is a signed 16-bit constant.
5661 if ((short)Value == (int)Value)
5662 Result = DAG.getTargetConstant(Value, Op.getValueType());
5664 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
5665 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
5666 if ((short)Value == 0)
5667 Result = DAG.getTargetConstant(Value, Op.getValueType());
5669 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
5670 if ((Value >> 16) == 0)
5671 Result = DAG.getTargetConstant(Value, Op.getValueType());
5673 case 'M': // "M" is a constant that is greater than 31.
5675 Result = DAG.getTargetConstant(Value, Op.getValueType());
5677 case 'N': // "N" is a positive constant that is an exact power of two.
5678 if ((int)Value > 0 && isPowerOf2_32(Value))
5679 Result = DAG.getTargetConstant(Value, Op.getValueType());
5681 case 'O': // "O" is the constant zero.
5683 Result = DAG.getTargetConstant(Value, Op.getValueType());
5685 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
5686 if ((short)-Value == (int)-Value)
5687 Result = DAG.getTargetConstant(Value, Op.getValueType());
5694 if (Result.getNode()) {
5695 Ops.push_back(Result);
5699 // Handle standard constraint letters.
5700 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5703 // isLegalAddressingMode - Return true if the addressing mode represented
5704 // by AM is legal for this target, for a load/store of the specified type.
5705 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5707 // FIXME: PPC does not allow r+i addressing modes for vectors!
5709 // PPC allows a sign-extended 16-bit immediate field.
5710 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
5713 // No global is ever allowed as a base.
5717 // PPC only support r+r,
5719 case 0: // "r+i" or just "i", depending on HasBaseReg.
5722 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
5724 // Otherwise we have r+r or r+i.
5727 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
5729 // Allow 2*r as r+r.
5732 // No other scales are supported.
5739 /// isLegalAddressImmediate - Return true if the integer value can be used
5740 /// as the offset of the target addressing mode for load / store of the
5742 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,Type *Ty) const{
5743 // PPC allows a sign-extended 16-bit immediate field.
5744 return (V > -(1 << 16) && V < (1 << 16)-1);
5747 bool PPCTargetLowering::isLegalAddressImmediate(GlobalValue* GV) const {
5751 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
5752 SelectionDAG &DAG) const {
5753 MachineFunction &MF = DAG.getMachineFunction();
5754 MachineFrameInfo *MFI = MF.getFrameInfo();
5755 MFI->setReturnAddressIsTaken(true);
5757 DebugLoc dl = Op.getDebugLoc();
5758 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5760 // Make sure the function does not optimize away the store of the RA to
5762 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
5763 FuncInfo->setLRStoreRequired();
5764 bool isPPC64 = PPCSubTarget.isPPC64();
5765 bool isDarwinABI = PPCSubTarget.isDarwinABI();
5768 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5771 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
5772 isPPC64? MVT::i64 : MVT::i32);
5773 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
5774 DAG.getNode(ISD::ADD, dl, getPointerTy(),
5776 MachinePointerInfo(), false, false, false, 0);
5779 // Just load the return address off the stack.
5780 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
5781 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
5782 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
5785 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
5786 SelectionDAG &DAG) const {
5787 DebugLoc dl = Op.getDebugLoc();
5788 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5790 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5791 bool isPPC64 = PtrVT == MVT::i64;
5793 MachineFunction &MF = DAG.getMachineFunction();
5794 MachineFrameInfo *MFI = MF.getFrameInfo();
5795 MFI->setFrameAddressIsTaken(true);
5796 bool is31 = (getTargetMachine().Options.DisableFramePointerElim(MF) ||
5797 MFI->hasVarSizedObjects()) &&
5798 MFI->getStackSize() &&
5799 !MF.getFunction()->hasFnAttr(Attribute::Naked);
5800 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) :
5801 (is31 ? PPC::R31 : PPC::R1);
5802 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
5805 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
5806 FrameAddr, MachinePointerInfo(), false, false,
5812 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5813 // The PowerPC target isn't yet aware of offsets.
5817 /// getOptimalMemOpType - Returns the target specific optimal type for load
5818 /// and store operations as a result of memset, memcpy, and memmove
5819 /// lowering. If DstAlign is zero that means it's safe to destination
5820 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
5821 /// means there isn't a need to check it against alignment requirement,
5822 /// probably because the source does not need to be loaded. If
5823 /// 'IsZeroVal' is true, that means it's safe to return a
5824 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
5825 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
5826 /// constant so it does not need to be loaded.
5827 /// It returns EVT::Other if the type should be determined using generic
5828 /// target-independent logic.
5829 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
5830 unsigned DstAlign, unsigned SrcAlign,
5833 MachineFunction &MF) const {
5834 if (this->PPCSubTarget.isPPC64()) {