1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
43 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
45 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
46 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
49 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
51 // FIXME: Remove this once the bug has been fixed!
52 extern cl::opt<bool> ANDIGlueBug;
54 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
55 // If it isn't a Mach-O file then it's going to be a linux ELF
58 return new TargetLoweringObjectFileMachO();
60 return new PPC64LinuxTargetObjectFile();
63 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
64 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))),
65 Subtarget(*TM.getSubtargetImpl()) {
68 // Use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(true);
72 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
73 // arguments are at least 4/8 bytes aligned.
74 bool isPPC64 = Subtarget.isPPC64();
75 setMinStackArgumentAlignment(isPPC64 ? 8:4);
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
82 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // PowerPC has pre-inc load and store's.
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
100 if (Subtarget.useCRBits()) {
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
103 if (isPPC64 || Subtarget.hasFPCVT()) {
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
108 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
109 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
115 // PowerPC does not support direct load / store of condition registers
116 setOperationAction(ISD::LOAD, MVT::i1, Custom);
117 setOperationAction(ISD::STORE, MVT::i1, Custom);
119 // FIXME: Remove this once the ANDI glue bug is fixed:
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
125 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
127 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
128 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath &&
180 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget.hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath &&
185 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget.hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget.hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget.hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget.useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget.isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget.isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget.has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget.use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget.hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
405 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
407 // add/sub are legal for all supported vector VT's.
408 setOperationAction(ISD::ADD , VT, Legal);
409 setOperationAction(ISD::SUB , VT, Legal);
411 // We promote all shuffles to v16i8.
412 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
413 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
415 // We promote all non-typed operations to v4i32.
416 setOperationAction(ISD::AND , VT, Promote);
417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
418 setOperationAction(ISD::OR , VT, Promote);
419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
420 setOperationAction(ISD::XOR , VT, Promote);
421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
422 setOperationAction(ISD::LOAD , VT, Promote);
423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
424 setOperationAction(ISD::SELECT, VT, Promote);
425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
426 setOperationAction(ISD::STORE, VT, Promote);
427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
429 // No other operations are legal.
430 setOperationAction(ISD::MUL , VT, Expand);
431 setOperationAction(ISD::SDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UDIV, VT, Expand);
434 setOperationAction(ISD::UREM, VT, Expand);
435 setOperationAction(ISD::FDIV, VT, Expand);
436 setOperationAction(ISD::FREM, VT, Expand);
437 setOperationAction(ISD::FNEG, VT, Expand);
438 setOperationAction(ISD::FSQRT, VT, Expand);
439 setOperationAction(ISD::FLOG, VT, Expand);
440 setOperationAction(ISD::FLOG10, VT, Expand);
441 setOperationAction(ISD::FLOG2, VT, Expand);
442 setOperationAction(ISD::FEXP, VT, Expand);
443 setOperationAction(ISD::FEXP2, VT, Expand);
444 setOperationAction(ISD::FSIN, VT, Expand);
445 setOperationAction(ISD::FCOS, VT, Expand);
446 setOperationAction(ISD::FABS, VT, Expand);
447 setOperationAction(ISD::FPOWI, VT, Expand);
448 setOperationAction(ISD::FFLOOR, VT, Expand);
449 setOperationAction(ISD::FCEIL, VT, Expand);
450 setOperationAction(ISD::FTRUNC, VT, Expand);
451 setOperationAction(ISD::FRINT, VT, Expand);
452 setOperationAction(ISD::FNEARBYINT, VT, Expand);
453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
455 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
456 setOperationAction(ISD::MULHU, VT, Expand);
457 setOperationAction(ISD::MULHS, VT, Expand);
458 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
459 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
460 setOperationAction(ISD::UDIVREM, VT, Expand);
461 setOperationAction(ISD::SDIVREM, VT, Expand);
462 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
463 setOperationAction(ISD::FPOW, VT, Expand);
464 setOperationAction(ISD::BSWAP, VT, Expand);
465 setOperationAction(ISD::CTPOP, VT, Expand);
466 setOperationAction(ISD::CTLZ, VT, Expand);
467 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
468 setOperationAction(ISD::CTTZ, VT, Expand);
469 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
470 setOperationAction(ISD::VSELECT, VT, Expand);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
473 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
474 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
475 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
476 setTruncStoreAction(VT, InnerVT, Expand);
478 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
479 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
480 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
483 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
484 // with merges, splats, etc.
485 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
487 setOperationAction(ISD::AND , MVT::v4i32, Legal);
488 setOperationAction(ISD::OR , MVT::v4i32, Legal);
489 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
490 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
491 setOperationAction(ISD::SELECT, MVT::v4i32,
492 Subtarget.useCRBits() ? Legal : Expand);
493 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
494 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
495 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
496 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
497 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
498 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
499 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
500 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
501 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
503 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
504 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
505 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
506 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
508 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
509 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
511 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
512 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
513 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
516 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
517 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
518 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
520 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
521 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
524 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
525 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
526 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
528 // Altivec does not contain unordered floating-point compare instructions
529 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
530 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
531 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
532 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
534 if (Subtarget.hasVSX()) {
535 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
536 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
538 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
540 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
541 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
542 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
544 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
546 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
547 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
549 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
550 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
552 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
553 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
554 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
558 // Share the Altivec comparison restrictions.
559 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
560 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
561 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
562 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
564 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
565 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
567 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
569 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
571 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
572 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
574 // VSX v2i64 only supports non-arithmetic operations.
575 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
576 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
578 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
579 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
580 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
582 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
584 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
585 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
586 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
587 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
589 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
591 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
592 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
593 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
594 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
596 // Vector operation legalization checks the result type of
597 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
598 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
599 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
600 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
601 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
603 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
607 if (Subtarget.has64BitSupport()) {
608 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
609 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
612 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
613 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
614 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
615 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
617 setBooleanContents(ZeroOrOneBooleanContent);
618 // Altivec instructions set fields to all zeros or all ones.
619 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
622 // These libcalls are not available in 32-bit.
623 setLibcallName(RTLIB::SHL_I128, nullptr);
624 setLibcallName(RTLIB::SRL_I128, nullptr);
625 setLibcallName(RTLIB::SRA_I128, nullptr);
629 setStackPointerRegisterToSaveRestore(PPC::X1);
630 setExceptionPointerRegister(PPC::X3);
631 setExceptionSelectorRegister(PPC::X4);
633 setStackPointerRegisterToSaveRestore(PPC::R1);
634 setExceptionPointerRegister(PPC::R3);
635 setExceptionSelectorRegister(PPC::R4);
638 // We have target-specific dag combine patterns for the following nodes:
639 setTargetDAGCombine(ISD::SINT_TO_FP);
640 setTargetDAGCombine(ISD::LOAD);
641 setTargetDAGCombine(ISD::STORE);
642 setTargetDAGCombine(ISD::BR_CC);
643 if (Subtarget.useCRBits())
644 setTargetDAGCombine(ISD::BRCOND);
645 setTargetDAGCombine(ISD::BSWAP);
646 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
648 setTargetDAGCombine(ISD::SIGN_EXTEND);
649 setTargetDAGCombine(ISD::ZERO_EXTEND);
650 setTargetDAGCombine(ISD::ANY_EXTEND);
652 if (Subtarget.useCRBits()) {
653 setTargetDAGCombine(ISD::TRUNCATE);
654 setTargetDAGCombine(ISD::SETCC);
655 setTargetDAGCombine(ISD::SELECT_CC);
658 // Use reciprocal estimates.
659 if (TM.Options.UnsafeFPMath) {
660 setTargetDAGCombine(ISD::FDIV);
661 setTargetDAGCombine(ISD::FSQRT);
664 // Darwin long double math library functions have $LDBL128 appended.
665 if (Subtarget.isDarwin()) {
666 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
667 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
668 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
669 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
670 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
671 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
672 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
673 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
674 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
675 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
678 // With 32 condition bits, we don't need to sink (and duplicate) compares
679 // aggressively in CodeGenPrep.
680 if (Subtarget.useCRBits())
681 setHasMultipleConditionRegisters();
683 setMinFunctionAlignment(2);
684 if (Subtarget.isDarwin())
685 setPrefFunctionAlignment(4);
687 setInsertFencesForAtomic(true);
689 if (Subtarget.enableMachineScheduler())
690 setSchedulingPreference(Sched::Source);
692 setSchedulingPreference(Sched::Hybrid);
694 computeRegisterProperties();
696 // The Freescale cores does better with aggressive inlining of memcpy and
697 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
698 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
699 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
700 MaxStoresPerMemset = 32;
701 MaxStoresPerMemsetOptSize = 16;
702 MaxStoresPerMemcpy = 32;
703 MaxStoresPerMemcpyOptSize = 8;
704 MaxStoresPerMemmove = 32;
705 MaxStoresPerMemmoveOptSize = 8;
707 setPrefFunctionAlignment(4);
711 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
712 /// the desired ByVal argument alignment.
713 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
714 unsigned MaxMaxAlign) {
715 if (MaxAlign == MaxMaxAlign)
717 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
718 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
720 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
722 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
723 unsigned EltAlign = 0;
724 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
725 if (EltAlign > MaxAlign)
727 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
728 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
729 unsigned EltAlign = 0;
730 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
731 if (EltAlign > MaxAlign)
733 if (MaxAlign == MaxMaxAlign)
739 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
740 /// function arguments in the caller parameter area.
741 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
742 // Darwin passes everything on 4 byte boundary.
743 if (Subtarget.isDarwin())
746 // 16byte and wider vectors are passed on 16byte boundary.
747 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
748 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
749 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
750 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
754 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
756 default: return nullptr;
757 case PPCISD::FSEL: return "PPCISD::FSEL";
758 case PPCISD::FCFID: return "PPCISD::FCFID";
759 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
760 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
761 case PPCISD::FRE: return "PPCISD::FRE";
762 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
763 case PPCISD::STFIWX: return "PPCISD::STFIWX";
764 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
765 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
766 case PPCISD::VPERM: return "PPCISD::VPERM";
767 case PPCISD::Hi: return "PPCISD::Hi";
768 case PPCISD::Lo: return "PPCISD::Lo";
769 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
770 case PPCISD::LOAD: return "PPCISD::LOAD";
771 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
772 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
773 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
774 case PPCISD::SRL: return "PPCISD::SRL";
775 case PPCISD::SRA: return "PPCISD::SRA";
776 case PPCISD::SHL: return "PPCISD::SHL";
777 case PPCISD::CALL: return "PPCISD::CALL";
778 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
779 case PPCISD::MTCTR: return "PPCISD::MTCTR";
780 case PPCISD::BCTRL: return "PPCISD::BCTRL";
781 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
782 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
783 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
784 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
785 case PPCISD::VCMP: return "PPCISD::VCMP";
786 case PPCISD::VCMPo: return "PPCISD::VCMPo";
787 case PPCISD::LBRX: return "PPCISD::LBRX";
788 case PPCISD::STBRX: return "PPCISD::STBRX";
789 case PPCISD::LARX: return "PPCISD::LARX";
790 case PPCISD::STCX: return "PPCISD::STCX";
791 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
792 case PPCISD::BDNZ: return "PPCISD::BDNZ";
793 case PPCISD::BDZ: return "PPCISD::BDZ";
794 case PPCISD::MFFS: return "PPCISD::MFFS";
795 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
796 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
797 case PPCISD::CR6SET: return "PPCISD::CR6SET";
798 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
799 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
800 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
801 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
802 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
803 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
804 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
805 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
806 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
807 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
808 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
809 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
810 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
811 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
812 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
813 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
814 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
815 case PPCISD::SC: return "PPCISD::SC";
819 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
821 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
822 return VT.changeVectorElementTypeToInteger();
825 //===----------------------------------------------------------------------===//
826 // Node matching predicates, for use by the tblgen matching code.
827 //===----------------------------------------------------------------------===//
829 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
830 static bool isFloatingPointZero(SDValue Op) {
831 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
832 return CFP->getValueAPF().isZero();
833 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
834 // Maybe this has already been legalized into the constant pool?
835 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
836 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
837 return CFP->getValueAPF().isZero();
842 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
843 /// true if Op is undef or if it matches the specified value.
844 static bool isConstantOrUndef(int Op, int Val) {
845 return Op < 0 || Op == Val;
848 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
849 /// VPKUHUM instruction.
850 /// The ShuffleKind distinguishes between big-endian operations with
851 /// two different inputs (0), either-endian operations with two identical
852 /// inputs (1), and little-endian operantion with two different inputs (2).
853 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
854 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
856 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
857 if (ShuffleKind == 0) {
860 for (unsigned i = 0; i != 16; ++i)
861 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
863 } else if (ShuffleKind == 2) {
866 for (unsigned i = 0; i != 16; ++i)
867 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
869 } else if (ShuffleKind == 1) {
870 unsigned j = IsLE ? 0 : 1;
871 for (unsigned i = 0; i != 8; ++i)
872 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
873 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
879 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
880 /// VPKUWUM instruction.
881 /// The ShuffleKind distinguishes between big-endian operations with
882 /// two different inputs (0), either-endian operations with two identical
883 /// inputs (1), and little-endian operantion with two different inputs (2).
884 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
885 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
887 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
888 if (ShuffleKind == 0) {
891 for (unsigned i = 0; i != 16; i += 2)
892 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
893 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
895 } else if (ShuffleKind == 2) {
898 for (unsigned i = 0; i != 16; i += 2)
899 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
900 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
902 } else if (ShuffleKind == 1) {
903 unsigned j = IsLE ? 0 : 2;
904 for (unsigned i = 0; i != 8; i += 2)
905 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
906 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
907 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
908 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
914 /// isVMerge - Common function, used to match vmrg* shuffles.
916 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
917 unsigned LHSStart, unsigned RHSStart) {
918 if (N->getValueType(0) != MVT::v16i8)
920 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
921 "Unsupported merge size!");
923 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
924 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
925 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
926 LHSStart+j+i*UnitSize) ||
927 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
928 RHSStart+j+i*UnitSize))
934 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
935 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
936 /// The ShuffleKind distinguishes between big-endian merges with two
937 /// different inputs (0), either-endian merges with two identical inputs (1),
938 /// and little-endian merges with two different inputs (2). For the latter,
939 /// the input operands are swapped (see PPCInstrAltivec.td).
940 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
941 unsigned ShuffleKind, SelectionDAG &DAG) {
942 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
943 if (ShuffleKind == 1) // unary
944 return isVMerge(N, UnitSize, 0, 0);
945 else if (ShuffleKind == 2) // swapped
946 return isVMerge(N, UnitSize, 0, 16);
950 if (ShuffleKind == 1) // unary
951 return isVMerge(N, UnitSize, 8, 8);
952 else if (ShuffleKind == 0) // normal
953 return isVMerge(N, UnitSize, 8, 24);
959 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
960 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
961 /// The ShuffleKind distinguishes between big-endian merges with two
962 /// different inputs (0), either-endian merges with two identical inputs (1),
963 /// and little-endian merges with two different inputs (2). For the latter,
964 /// the input operands are swapped (see PPCInstrAltivec.td).
965 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
966 unsigned ShuffleKind, SelectionDAG &DAG) {
967 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
968 if (ShuffleKind == 1) // unary
969 return isVMerge(N, UnitSize, 8, 8);
970 else if (ShuffleKind == 2) // swapped
971 return isVMerge(N, UnitSize, 8, 24);
975 if (ShuffleKind == 1) // unary
976 return isVMerge(N, UnitSize, 0, 0);
977 else if (ShuffleKind == 0) // normal
978 return isVMerge(N, UnitSize, 0, 16);
985 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
986 /// amount, otherwise return -1.
987 /// The ShuffleKind distinguishes between big-endian operations with two
988 /// different inputs (0), either-endian operations with two identical inputs
989 /// (1), and little-endian operations with two different inputs (2). For the
990 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
991 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
993 if (N->getValueType(0) != MVT::v16i8)
996 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
998 // Find the first non-undef value in the shuffle mask.
1000 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1003 if (i == 16) return -1; // all undef.
1005 // Otherwise, check to see if the rest of the elements are consecutively
1006 // numbered from this value.
1007 unsigned ShiftAmt = SVOp->getMaskElt(i);
1008 if (ShiftAmt < i) return -1;
1011 bool isLE = DAG.getTarget().getSubtargetImpl()->getDataLayout()->
1014 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1015 // Check the rest of the elements to see if they are consecutive.
1016 for (++i; i != 16; ++i)
1017 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1019 } else if (ShuffleKind == 1) {
1020 // Check the rest of the elements to see if they are consecutive.
1021 for (++i; i != 16; ++i)
1022 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1027 if (ShuffleKind == 2 && isLE)
1028 ShiftAmt = 16 - ShiftAmt;
1033 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1034 /// specifies a splat of a single element that is suitable for input to
1035 /// VSPLTB/VSPLTH/VSPLTW.
1036 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1037 assert(N->getValueType(0) == MVT::v16i8 &&
1038 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1040 // This is a splat operation if each element of the permute is the same, and
1041 // if the value doesn't reference the second vector.
1042 unsigned ElementBase = N->getMaskElt(0);
1044 // FIXME: Handle UNDEF elements too!
1045 if (ElementBase >= 16)
1048 // Check that the indices are consecutive, in the case of a multi-byte element
1049 // splatted with a v16i8 mask.
1050 for (unsigned i = 1; i != EltSize; ++i)
1051 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1054 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1055 if (N->getMaskElt(i) < 0) continue;
1056 for (unsigned j = 0; j != EltSize; ++j)
1057 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1063 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1065 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1066 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1068 APInt APVal, APUndef;
1072 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1073 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1074 return CFP->getValueAPF().isNegZero();
1079 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1080 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1081 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1082 SelectionDAG &DAG) {
1083 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1084 assert(isSplatShuffleMask(SVOp, EltSize));
1085 if (DAG.getSubtarget().getDataLayout()->isLittleEndian())
1086 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1088 return SVOp->getMaskElt(0) / EltSize;
1091 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1092 /// by using a vspltis[bhw] instruction of the specified element size, return
1093 /// the constant being splatted. The ByteSize field indicates the number of
1094 /// bytes of each element [124] -> [bhw].
1095 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1096 SDValue OpVal(nullptr, 0);
1098 // If ByteSize of the splat is bigger than the element size of the
1099 // build_vector, then we have a case where we are checking for a splat where
1100 // multiple elements of the buildvector are folded together into a single
1101 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1102 unsigned EltSize = 16/N->getNumOperands();
1103 if (EltSize < ByteSize) {
1104 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1105 SDValue UniquedVals[4];
1106 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1108 // See if all of the elements in the buildvector agree across.
1109 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1110 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1111 // If the element isn't a constant, bail fully out.
1112 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1115 if (!UniquedVals[i&(Multiple-1)].getNode())
1116 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1117 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1118 return SDValue(); // no match.
1121 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1122 // either constant or undef values that are identical for each chunk. See
1123 // if these chunks can form into a larger vspltis*.
1125 // Check to see if all of the leading entries are either 0 or -1. If
1126 // neither, then this won't fit into the immediate field.
1127 bool LeadingZero = true;
1128 bool LeadingOnes = true;
1129 for (unsigned i = 0; i != Multiple-1; ++i) {
1130 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1132 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1133 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1135 // Finally, check the least significant entry.
1137 if (!UniquedVals[Multiple-1].getNode())
1138 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1139 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1141 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1144 if (!UniquedVals[Multiple-1].getNode())
1145 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1146 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1147 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1148 return DAG.getTargetConstant(Val, MVT::i32);
1154 // Check to see if this buildvec has a single non-undef value in its elements.
1155 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1156 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1157 if (!OpVal.getNode())
1158 OpVal = N->getOperand(i);
1159 else if (OpVal != N->getOperand(i))
1163 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1165 unsigned ValSizeInBytes = EltSize;
1167 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1168 Value = CN->getZExtValue();
1169 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1170 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1171 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1174 // If the splat value is larger than the element value, then we can never do
1175 // this splat. The only case that we could fit the replicated bits into our
1176 // immediate field for would be zero, and we prefer to use vxor for it.
1177 if (ValSizeInBytes < ByteSize) return SDValue();
1179 // If the element value is larger than the splat value, cut it in half and
1180 // check to see if the two halves are equal. Continue doing this until we
1181 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1182 while (ValSizeInBytes > ByteSize) {
1183 ValSizeInBytes >>= 1;
1185 // If the top half equals the bottom half, we're still ok.
1186 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1187 (Value & ((1 << (8*ValSizeInBytes))-1)))
1191 // Properly sign extend the value.
1192 int MaskVal = SignExtend32(Value, ByteSize * 8);
1194 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1195 if (MaskVal == 0) return SDValue();
1197 // Finally, if this value fits in a 5 bit sext field, return it
1198 if (SignExtend32<5>(MaskVal) == MaskVal)
1199 return DAG.getTargetConstant(MaskVal, MVT::i32);
1203 //===----------------------------------------------------------------------===//
1204 // Addressing Mode Selection
1205 //===----------------------------------------------------------------------===//
1207 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1208 /// or 64-bit immediate, and if the value can be accurately represented as a
1209 /// sign extension from a 16-bit value. If so, this returns true and the
1211 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1212 if (!isa<ConstantSDNode>(N))
1215 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1216 if (N->getValueType(0) == MVT::i32)
1217 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1219 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1221 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1222 return isIntS16Immediate(Op.getNode(), Imm);
1226 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1227 /// can be represented as an indexed [r+r] operation. Returns false if it
1228 /// can be more efficiently represented with [r+imm].
1229 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1231 SelectionDAG &DAG) const {
1233 if (N.getOpcode() == ISD::ADD) {
1234 if (isIntS16Immediate(N.getOperand(1), imm))
1235 return false; // r+i
1236 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1237 return false; // r+i
1239 Base = N.getOperand(0);
1240 Index = N.getOperand(1);
1242 } else if (N.getOpcode() == ISD::OR) {
1243 if (isIntS16Immediate(N.getOperand(1), imm))
1244 return false; // r+i can fold it if we can.
1246 // If this is an or of disjoint bitfields, we can codegen this as an add
1247 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1249 APInt LHSKnownZero, LHSKnownOne;
1250 APInt RHSKnownZero, RHSKnownOne;
1251 DAG.computeKnownBits(N.getOperand(0),
1252 LHSKnownZero, LHSKnownOne);
1254 if (LHSKnownZero.getBoolValue()) {
1255 DAG.computeKnownBits(N.getOperand(1),
1256 RHSKnownZero, RHSKnownOne);
1257 // If all of the bits are known zero on the LHS or RHS, the add won't
1259 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1260 Base = N.getOperand(0);
1261 Index = N.getOperand(1);
1270 // If we happen to be doing an i64 load or store into a stack slot that has
1271 // less than a 4-byte alignment, then the frame-index elimination may need to
1272 // use an indexed load or store instruction (because the offset may not be a
1273 // multiple of 4). The extra register needed to hold the offset comes from the
1274 // register scavenger, and it is possible that the scavenger will need to use
1275 // an emergency spill slot. As a result, we need to make sure that a spill slot
1276 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1278 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1279 // FIXME: This does not handle the LWA case.
1283 // NOTE: We'll exclude negative FIs here, which come from argument
1284 // lowering, because there are no known test cases triggering this problem
1285 // using packed structures (or similar). We can remove this exclusion if
1286 // we find such a test case. The reason why this is so test-case driven is
1287 // because this entire 'fixup' is only to prevent crashes (from the
1288 // register scavenger) on not-really-valid inputs. For example, if we have:
1290 // %b = bitcast i1* %a to i64*
1291 // store i64* a, i64 b
1292 // then the store should really be marked as 'align 1', but is not. If it
1293 // were marked as 'align 1' then the indexed form would have been
1294 // instruction-selected initially, and the problem this 'fixup' is preventing
1295 // won't happen regardless.
1299 MachineFunction &MF = DAG.getMachineFunction();
1300 MachineFrameInfo *MFI = MF.getFrameInfo();
1302 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1306 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1307 FuncInfo->setHasNonRISpills();
1310 /// Returns true if the address N can be represented by a base register plus
1311 /// a signed 16-bit displacement [r+imm], and if it is not better
1312 /// represented as reg+reg. If Aligned is true, only accept displacements
1313 /// suitable for STD and friends, i.e. multiples of 4.
1314 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1317 bool Aligned) const {
1318 // FIXME dl should come from parent load or store, not from address
1320 // If this can be more profitably realized as r+r, fail.
1321 if (SelectAddressRegReg(N, Disp, Base, DAG))
1324 if (N.getOpcode() == ISD::ADD) {
1326 if (isIntS16Immediate(N.getOperand(1), imm) &&
1327 (!Aligned || (imm & 3) == 0)) {
1328 Disp = DAG.getTargetConstant(imm, N.getValueType());
1329 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1330 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1331 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1333 Base = N.getOperand(0);
1335 return true; // [r+i]
1336 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1337 // Match LOAD (ADD (X, Lo(G))).
1338 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1339 && "Cannot handle constant offsets yet!");
1340 Disp = N.getOperand(1).getOperand(0); // The global address.
1341 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1342 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1343 Disp.getOpcode() == ISD::TargetConstantPool ||
1344 Disp.getOpcode() == ISD::TargetJumpTable);
1345 Base = N.getOperand(0);
1346 return true; // [&g+r]
1348 } else if (N.getOpcode() == ISD::OR) {
1350 if (isIntS16Immediate(N.getOperand(1), imm) &&
1351 (!Aligned || (imm & 3) == 0)) {
1352 // If this is an or of disjoint bitfields, we can codegen this as an add
1353 // (for better address arithmetic) if the LHS and RHS of the OR are
1354 // provably disjoint.
1355 APInt LHSKnownZero, LHSKnownOne;
1356 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1358 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1359 // If all of the bits are known zero on the LHS or RHS, the add won't
1361 if (FrameIndexSDNode *FI =
1362 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1363 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1364 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1366 Base = N.getOperand(0);
1368 Disp = DAG.getTargetConstant(imm, N.getValueType());
1372 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1373 // Loading from a constant address.
1375 // If this address fits entirely in a 16-bit sext immediate field, codegen
1378 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1379 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1380 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1381 CN->getValueType(0));
1385 // Handle 32-bit sext immediates with LIS + addr mode.
1386 if ((CN->getValueType(0) == MVT::i32 ||
1387 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1388 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1389 int Addr = (int)CN->getZExtValue();
1391 // Otherwise, break this down into an LIS + disp.
1392 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1394 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1395 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1396 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1401 Disp = DAG.getTargetConstant(0, getPointerTy());
1402 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1403 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1404 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1407 return true; // [r+0]
1410 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1411 /// represented as an indexed [r+r] operation.
1412 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1414 SelectionDAG &DAG) const {
1415 // Check to see if we can easily represent this as an [r+r] address. This
1416 // will fail if it thinks that the address is more profitably represented as
1417 // reg+imm, e.g. where imm = 0.
1418 if (SelectAddressRegReg(N, Base, Index, DAG))
1421 // If the operand is an addition, always emit this as [r+r], since this is
1422 // better (for code size, and execution, as the memop does the add for free)
1423 // than emitting an explicit add.
1424 if (N.getOpcode() == ISD::ADD) {
1425 Base = N.getOperand(0);
1426 Index = N.getOperand(1);
1430 // Otherwise, do it the hard way, using R0 as the base register.
1431 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1437 /// getPreIndexedAddressParts - returns true by value, base pointer and
1438 /// offset pointer and addressing mode by reference if the node's address
1439 /// can be legally represented as pre-indexed load / store address.
1440 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1442 ISD::MemIndexedMode &AM,
1443 SelectionDAG &DAG) const {
1444 if (DisablePPCPreinc) return false;
1450 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1451 Ptr = LD->getBasePtr();
1452 VT = LD->getMemoryVT();
1453 Alignment = LD->getAlignment();
1454 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1455 Ptr = ST->getBasePtr();
1456 VT = ST->getMemoryVT();
1457 Alignment = ST->getAlignment();
1462 // PowerPC doesn't have preinc load/store instructions for vectors.
1466 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1468 // Common code will reject creating a pre-inc form if the base pointer
1469 // is a frame index, or if N is a store and the base pointer is either
1470 // the same as or a predecessor of the value being stored. Check for
1471 // those situations here, and try with swapped Base/Offset instead.
1474 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1477 SDValue Val = cast<StoreSDNode>(N)->getValue();
1478 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1483 std::swap(Base, Offset);
1489 // LDU/STU can only handle immediates that are a multiple of 4.
1490 if (VT != MVT::i64) {
1491 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1494 // LDU/STU need an address with at least 4-byte alignment.
1498 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1502 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1503 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1504 // sext i32 to i64 when addr mode is r+i.
1505 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1506 LD->getExtensionType() == ISD::SEXTLOAD &&
1507 isa<ConstantSDNode>(Offset))
1515 //===----------------------------------------------------------------------===//
1516 // LowerOperation implementation
1517 //===----------------------------------------------------------------------===//
1519 /// GetLabelAccessInfo - Return true if we should reference labels using a
1520 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1521 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1522 unsigned &LoOpFlags,
1523 const GlobalValue *GV = nullptr) {
1524 HiOpFlags = PPCII::MO_HA;
1525 LoOpFlags = PPCII::MO_LO;
1527 // Don't use the pic base if not in PIC relocation model.
1528 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1531 HiOpFlags |= PPCII::MO_PIC_FLAG;
1532 LoOpFlags |= PPCII::MO_PIC_FLAG;
1535 // If this is a reference to a global value that requires a non-lazy-ptr, make
1536 // sure that instruction lowering adds it.
1537 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1538 HiOpFlags |= PPCII::MO_NLP_FLAG;
1539 LoOpFlags |= PPCII::MO_NLP_FLAG;
1541 if (GV->hasHiddenVisibility()) {
1542 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1543 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1550 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1551 SelectionDAG &DAG) {
1552 EVT PtrVT = HiPart.getValueType();
1553 SDValue Zero = DAG.getConstant(0, PtrVT);
1556 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1557 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1559 // With PIC, the first instruction is actually "GR+hi(&G)".
1561 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1562 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1564 // Generate non-pic code that has direct accesses to the constant pool.
1565 // The address of the global is just (hi(&g)+lo(&g)).
1566 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1569 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1570 SelectionDAG &DAG) const {
1571 EVT PtrVT = Op.getValueType();
1572 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1573 const Constant *C = CP->getConstVal();
1575 // 64-bit SVR4 ABI code is always position-independent.
1576 // The actual address of the GlobalValue is stored in the TOC.
1577 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1578 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1579 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1580 DAG.getRegister(PPC::X2, MVT::i64));
1583 unsigned MOHiFlag, MOLoFlag;
1584 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1586 if (isPIC && Subtarget.isSVR4ABI()) {
1587 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1588 PPCII::MO_PIC_FLAG);
1590 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1591 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1595 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1597 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1598 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1601 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1602 EVT PtrVT = Op.getValueType();
1603 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1605 // 64-bit SVR4 ABI code is always position-independent.
1606 // The actual address of the GlobalValue is stored in the TOC.
1607 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1608 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1609 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1610 DAG.getRegister(PPC::X2, MVT::i64));
1613 unsigned MOHiFlag, MOLoFlag;
1614 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1616 if (isPIC && Subtarget.isSVR4ABI()) {
1617 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1618 PPCII::MO_PIC_FLAG);
1620 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1621 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1624 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1625 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1626 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1629 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1630 SelectionDAG &DAG) const {
1631 EVT PtrVT = Op.getValueType();
1633 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1635 unsigned MOHiFlag, MOLoFlag;
1636 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1637 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1638 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1639 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1642 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1643 SelectionDAG &DAG) const {
1645 // FIXME: TLS addresses currently use medium model code sequences,
1646 // which is the most useful form. Eventually support for small and
1647 // large models could be added if users need it, at the cost of
1648 // additional complexity.
1649 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1651 const GlobalValue *GV = GA->getGlobal();
1652 EVT PtrVT = getPointerTy();
1653 bool is64bit = Subtarget.isPPC64();
1655 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1657 if (Model == TLSModel::LocalExec) {
1658 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1659 PPCII::MO_TPREL_HA);
1660 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1661 PPCII::MO_TPREL_LO);
1662 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1663 is64bit ? MVT::i64 : MVT::i32);
1664 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1665 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1668 if (Model == TLSModel::InitialExec) {
1669 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1670 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1674 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1675 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1676 PtrVT, GOTReg, TGA);
1678 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1679 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1680 PtrVT, TGA, GOTPtr);
1681 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1684 if (Model == TLSModel::GeneralDynamic) {
1685 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1688 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1689 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1692 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1694 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1697 // We need a chain node, and don't have one handy. The underlying
1698 // call has no side effects, so using the function entry node
1700 SDValue Chain = DAG.getEntryNode();
1701 Chain = DAG.getCopyToReg(Chain, dl,
1702 is64bit ? PPC::X3 : PPC::R3, GOTEntry);
1703 SDValue ParmReg = DAG.getRegister(is64bit ? PPC::X3 : PPC::R3,
1704 is64bit ? MVT::i64 : MVT::i32);
1705 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1706 PtrVT, ParmReg, TGA);
1707 // The return value from GET_TLS_ADDR really is in X3 already, but
1708 // some hacks are needed here to tie everything together. The extra
1709 // copies dissolve during subsequent transforms.
1710 Chain = DAG.getCopyToReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, TLSAddr);
1711 return DAG.getCopyFromReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, PtrVT);
1714 if (Model == TLSModel::LocalDynamic) {
1715 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1718 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1719 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1722 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1724 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1727 // We need a chain node, and don't have one handy. The underlying
1728 // call has no side effects, so using the function entry node
1730 SDValue Chain = DAG.getEntryNode();
1731 Chain = DAG.getCopyToReg(Chain, dl,
1732 is64bit ? PPC::X3 : PPC::R3, GOTEntry);
1733 SDValue ParmReg = DAG.getRegister(is64bit ? PPC::X3 : PPC::R3,
1734 is64bit ? MVT::i64 : MVT::i32);
1735 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1736 PtrVT, ParmReg, TGA);
1737 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1738 // some hacks are needed here to tie everything together. The extra
1739 // copies dissolve during subsequent transforms.
1740 Chain = DAG.getCopyToReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, TLSAddr);
1741 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1742 Chain, ParmReg, TGA);
1743 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1746 llvm_unreachable("Unknown TLS model!");
1749 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1750 SelectionDAG &DAG) const {
1751 EVT PtrVT = Op.getValueType();
1752 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1754 const GlobalValue *GV = GSDN->getGlobal();
1756 // 64-bit SVR4 ABI code is always position-independent.
1757 // The actual address of the GlobalValue is stored in the TOC.
1758 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1759 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1760 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1761 DAG.getRegister(PPC::X2, MVT::i64));
1764 unsigned MOHiFlag, MOLoFlag;
1765 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1767 if (isPIC && Subtarget.isSVR4ABI()) {
1768 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1770 PPCII::MO_PIC_FLAG);
1771 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1772 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1776 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1778 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1780 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1782 // If the global reference is actually to a non-lazy-pointer, we have to do an
1783 // extra load to get the address of the global.
1784 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1785 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1786 false, false, false, 0);
1790 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1791 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1794 if (Op.getValueType() == MVT::v2i64) {
1795 // When the operands themselves are v2i64 values, we need to do something
1796 // special because VSX has no underlying comparison operations for these.
1797 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1798 // Equality can be handled by casting to the legal type for Altivec
1799 // comparisons, everything else needs to be expanded.
1800 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1801 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1802 DAG.getSetCC(dl, MVT::v4i32,
1803 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1804 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1811 // We handle most of these in the usual way.
1815 // If we're comparing for equality to zero, expose the fact that this is
1816 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1817 // fold the new nodes.
1818 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1819 if (C->isNullValue() && CC == ISD::SETEQ) {
1820 EVT VT = Op.getOperand(0).getValueType();
1821 SDValue Zext = Op.getOperand(0);
1822 if (VT.bitsLT(MVT::i32)) {
1824 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1826 unsigned Log2b = Log2_32(VT.getSizeInBits());
1827 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1828 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1829 DAG.getConstant(Log2b, MVT::i32));
1830 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1832 // Leave comparisons against 0 and -1 alone for now, since they're usually
1833 // optimized. FIXME: revisit this when we can custom lower all setcc
1835 if (C->isAllOnesValue() || C->isNullValue())
1839 // If we have an integer seteq/setne, turn it into a compare against zero
1840 // by xor'ing the rhs with the lhs, which is faster than setting a
1841 // condition register, reading it back out, and masking the correct bit. The
1842 // normal approach here uses sub to do this instead of xor. Using xor exposes
1843 // the result to other bit-twiddling opportunities.
1844 EVT LHSVT = Op.getOperand(0).getValueType();
1845 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1846 EVT VT = Op.getValueType();
1847 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1849 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1854 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1855 const PPCSubtarget &Subtarget) const {
1856 SDNode *Node = Op.getNode();
1857 EVT VT = Node->getValueType(0);
1858 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1859 SDValue InChain = Node->getOperand(0);
1860 SDValue VAListPtr = Node->getOperand(1);
1861 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1864 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1867 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1868 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1869 false, false, false, 0);
1870 InChain = GprIndex.getValue(1);
1872 if (VT == MVT::i64) {
1873 // Check if GprIndex is even
1874 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1875 DAG.getConstant(1, MVT::i32));
1876 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1877 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1878 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1879 DAG.getConstant(1, MVT::i32));
1880 // Align GprIndex to be even if it isn't
1881 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1885 // fpr index is 1 byte after gpr
1886 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1887 DAG.getConstant(1, MVT::i32));
1890 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1891 FprPtr, MachinePointerInfo(SV), MVT::i8,
1892 false, false, false, 0);
1893 InChain = FprIndex.getValue(1);
1895 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1896 DAG.getConstant(8, MVT::i32));
1898 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1899 DAG.getConstant(4, MVT::i32));
1902 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1903 MachinePointerInfo(), false, false,
1905 InChain = OverflowArea.getValue(1);
1907 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1908 MachinePointerInfo(), false, false,
1910 InChain = RegSaveArea.getValue(1);
1912 // select overflow_area if index > 8
1913 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1914 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1916 // adjustment constant gpr_index * 4/8
1917 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1918 VT.isInteger() ? GprIndex : FprIndex,
1919 DAG.getConstant(VT.isInteger() ? 4 : 8,
1922 // OurReg = RegSaveArea + RegConstant
1923 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1926 // Floating types are 32 bytes into RegSaveArea
1927 if (VT.isFloatingPoint())
1928 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1929 DAG.getConstant(32, MVT::i32));
1931 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1932 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1933 VT.isInteger() ? GprIndex : FprIndex,
1934 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1937 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1938 VT.isInteger() ? VAListPtr : FprPtr,
1939 MachinePointerInfo(SV),
1940 MVT::i8, false, false, 0);
1942 // determine if we should load from reg_save_area or overflow_area
1943 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1945 // increase overflow_area by 4/8 if gpr/fpr > 8
1946 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1947 DAG.getConstant(VT.isInteger() ? 4 : 8,
1950 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1953 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1955 MachinePointerInfo(),
1956 MVT::i32, false, false, 0);
1958 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1959 false, false, false, 0);
1962 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1963 const PPCSubtarget &Subtarget) const {
1964 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1966 // We have to copy the entire va_list struct:
1967 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1968 return DAG.getMemcpy(Op.getOperand(0), Op,
1969 Op.getOperand(1), Op.getOperand(2),
1970 DAG.getConstant(12, MVT::i32), 8, false, true,
1971 MachinePointerInfo(), MachinePointerInfo());
1974 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1975 SelectionDAG &DAG) const {
1976 return Op.getOperand(0);
1979 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1980 SelectionDAG &DAG) const {
1981 SDValue Chain = Op.getOperand(0);
1982 SDValue Trmp = Op.getOperand(1); // trampoline
1983 SDValue FPtr = Op.getOperand(2); // nested function
1984 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1987 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1988 bool isPPC64 = (PtrVT == MVT::i64);
1990 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1993 TargetLowering::ArgListTy Args;
1994 TargetLowering::ArgListEntry Entry;
1996 Entry.Ty = IntPtrTy;
1997 Entry.Node = Trmp; Args.push_back(Entry);
1999 // TrampSize == (isPPC64 ? 48 : 40);
2000 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2001 isPPC64 ? MVT::i64 : MVT::i32);
2002 Args.push_back(Entry);
2004 Entry.Node = FPtr; Args.push_back(Entry);
2005 Entry.Node = Nest; Args.push_back(Entry);
2007 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2008 TargetLowering::CallLoweringInfo CLI(DAG);
2009 CLI.setDebugLoc(dl).setChain(Chain)
2010 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2011 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2012 std::move(Args), 0);
2014 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2015 return CallResult.second;
2018 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2019 const PPCSubtarget &Subtarget) const {
2020 MachineFunction &MF = DAG.getMachineFunction();
2021 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2025 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2026 // vastart just stores the address of the VarArgsFrameIndex slot into the
2027 // memory location argument.
2028 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2029 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2030 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2031 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2032 MachinePointerInfo(SV),
2036 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2037 // We suppose the given va_list is already allocated.
2040 // char gpr; /* index into the array of 8 GPRs
2041 // * stored in the register save area
2042 // * gpr=0 corresponds to r3,
2043 // * gpr=1 to r4, etc.
2045 // char fpr; /* index into the array of 8 FPRs
2046 // * stored in the register save area
2047 // * fpr=0 corresponds to f1,
2048 // * fpr=1 to f2, etc.
2050 // char *overflow_arg_area;
2051 // /* location on stack that holds
2052 // * the next overflow argument
2054 // char *reg_save_area;
2055 // /* where r3:r10 and f1:f8 (if saved)
2061 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2062 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2065 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2067 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2069 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2072 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2073 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2075 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2076 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2078 uint64_t FPROffset = 1;
2079 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2081 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2083 // Store first byte : number of int regs
2084 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2086 MachinePointerInfo(SV),
2087 MVT::i8, false, false, 0);
2088 uint64_t nextOffset = FPROffset;
2089 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2092 // Store second byte : number of float regs
2093 SDValue secondStore =
2094 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2095 MachinePointerInfo(SV, nextOffset), MVT::i8,
2097 nextOffset += StackOffset;
2098 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2100 // Store second word : arguments given on stack
2101 SDValue thirdStore =
2102 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2103 MachinePointerInfo(SV, nextOffset),
2105 nextOffset += FrameOffset;
2106 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2108 // Store third word : arguments given in registers
2109 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2110 MachinePointerInfo(SV, nextOffset),
2115 #include "PPCGenCallingConv.inc"
2117 // Function whose sole purpose is to kill compiler warnings
2118 // stemming from unused functions included from PPCGenCallingConv.inc.
2119 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2120 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2123 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2124 CCValAssign::LocInfo &LocInfo,
2125 ISD::ArgFlagsTy &ArgFlags,
2130 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2132 CCValAssign::LocInfo &LocInfo,
2133 ISD::ArgFlagsTy &ArgFlags,
2135 static const MCPhysReg ArgRegs[] = {
2136 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2137 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2139 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2141 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2143 // Skip one register if the first unallocated register has an even register
2144 // number and there are still argument registers available which have not been
2145 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2146 // need to skip a register if RegNum is odd.
2147 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2148 State.AllocateReg(ArgRegs[RegNum]);
2151 // Always return false here, as this function only makes sure that the first
2152 // unallocated register has an odd register number and does not actually
2153 // allocate a register for the current argument.
2157 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2159 CCValAssign::LocInfo &LocInfo,
2160 ISD::ArgFlagsTy &ArgFlags,
2162 static const MCPhysReg ArgRegs[] = {
2163 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2167 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2169 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2171 // If there is only one Floating-point register left we need to put both f64
2172 // values of a split ppc_fp128 value on the stack.
2173 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2174 State.AllocateReg(ArgRegs[RegNum]);
2177 // Always return false here, as this function only makes sure that the two f64
2178 // values a ppc_fp128 value is split into are both passed in registers or both
2179 // passed on the stack and does not actually allocate a register for the
2180 // current argument.
2184 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2186 static const MCPhysReg *GetFPR() {
2187 static const MCPhysReg FPR[] = {
2188 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2189 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2195 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2197 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2198 unsigned PtrByteSize) {
2199 unsigned ArgSize = ArgVT.getStoreSize();
2200 if (Flags.isByVal())
2201 ArgSize = Flags.getByValSize();
2203 // Round up to multiples of the pointer size, except for array members,
2204 // which are always packed.
2205 if (!Flags.isInConsecutiveRegs())
2206 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2211 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2213 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2214 ISD::ArgFlagsTy Flags,
2215 unsigned PtrByteSize) {
2216 unsigned Align = PtrByteSize;
2218 // Altivec parameters are padded to a 16 byte boundary.
2219 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2220 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2221 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2224 // ByVal parameters are aligned as requested.
2225 if (Flags.isByVal()) {
2226 unsigned BVAlign = Flags.getByValAlign();
2227 if (BVAlign > PtrByteSize) {
2228 if (BVAlign % PtrByteSize != 0)
2230 "ByVal alignment is not a multiple of the pointer size");
2236 // Array members are always packed to their original alignment.
2237 if (Flags.isInConsecutiveRegs()) {
2238 // If the array member was split into multiple registers, the first
2239 // needs to be aligned to the size of the full type. (Except for
2240 // ppcf128, which is only aligned as its f64 components.)
2241 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2242 Align = OrigVT.getStoreSize();
2244 Align = ArgVT.getStoreSize();
2250 /// CalculateStackSlotUsed - Return whether this argument will use its
2251 /// stack slot (instead of being passed in registers). ArgOffset,
2252 /// AvailableFPRs, and AvailableVRs must hold the current argument
2253 /// position, and will be updated to account for this argument.
2254 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2255 ISD::ArgFlagsTy Flags,
2256 unsigned PtrByteSize,
2257 unsigned LinkageSize,
2258 unsigned ParamAreaSize,
2259 unsigned &ArgOffset,
2260 unsigned &AvailableFPRs,
2261 unsigned &AvailableVRs) {
2262 bool UseMemory = false;
2264 // Respect alignment of argument on the stack.
2266 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2267 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2268 // If there's no space left in the argument save area, we must
2269 // use memory (this check also catches zero-sized arguments).
2270 if (ArgOffset >= LinkageSize + ParamAreaSize)
2273 // Allocate argument on the stack.
2274 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2275 if (Flags.isInConsecutiveRegsLast())
2276 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2277 // If we overran the argument save area, we must use memory
2278 // (this check catches arguments passed partially in memory)
2279 if (ArgOffset > LinkageSize + ParamAreaSize)
2282 // However, if the argument is actually passed in an FPR or a VR,
2283 // we don't use memory after all.
2284 if (!Flags.isByVal()) {
2285 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2286 if (AvailableFPRs > 0) {
2290 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2291 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2292 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2293 if (AvailableVRs > 0) {
2302 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2303 /// ensure minimum alignment required for target.
2304 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2305 unsigned NumBytes) {
2306 unsigned TargetAlign =
2307 Target.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
2308 unsigned AlignMask = TargetAlign - 1;
2309 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2314 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2315 CallingConv::ID CallConv, bool isVarArg,
2316 const SmallVectorImpl<ISD::InputArg>
2318 SDLoc dl, SelectionDAG &DAG,
2319 SmallVectorImpl<SDValue> &InVals)
2321 if (Subtarget.isSVR4ABI()) {
2322 if (Subtarget.isPPC64())
2323 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2326 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2329 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2335 PPCTargetLowering::LowerFormalArguments_32SVR4(
2337 CallingConv::ID CallConv, bool isVarArg,
2338 const SmallVectorImpl<ISD::InputArg>
2340 SDLoc dl, SelectionDAG &DAG,
2341 SmallVectorImpl<SDValue> &InVals) const {
2343 // 32-bit SVR4 ABI Stack Frame Layout:
2344 // +-----------------------------------+
2345 // +--> | Back chain |
2346 // | +-----------------------------------+
2347 // | | Floating-point register save area |
2348 // | +-----------------------------------+
2349 // | | General register save area |
2350 // | +-----------------------------------+
2351 // | | CR save word |
2352 // | +-----------------------------------+
2353 // | | VRSAVE save word |
2354 // | +-----------------------------------+
2355 // | | Alignment padding |
2356 // | +-----------------------------------+
2357 // | | Vector register save area |
2358 // | +-----------------------------------+
2359 // | | Local variable space |
2360 // | +-----------------------------------+
2361 // | | Parameter list area |
2362 // | +-----------------------------------+
2363 // | | LR save word |
2364 // | +-----------------------------------+
2365 // SP--> +--- | Back chain |
2366 // +-----------------------------------+
2369 // System V Application Binary Interface PowerPC Processor Supplement
2370 // AltiVec Technology Programming Interface Manual
2372 MachineFunction &MF = DAG.getMachineFunction();
2373 MachineFrameInfo *MFI = MF.getFrameInfo();
2374 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2376 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2377 // Potential tail calls could cause overwriting of argument stack slots.
2378 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2379 (CallConv == CallingConv::Fast));
2380 unsigned PtrByteSize = 4;
2382 // Assign locations to all of the incoming arguments.
2383 SmallVector<CCValAssign, 16> ArgLocs;
2384 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2387 // Reserve space for the linkage area on the stack.
2388 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2389 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2391 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2393 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2394 CCValAssign &VA = ArgLocs[i];
2396 // Arguments stored in registers.
2397 if (VA.isRegLoc()) {
2398 const TargetRegisterClass *RC;
2399 EVT ValVT = VA.getValVT();
2401 switch (ValVT.getSimpleVT().SimpleTy) {
2403 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2406 RC = &PPC::GPRCRegClass;
2409 RC = &PPC::F4RCRegClass;
2412 if (Subtarget.hasVSX())
2413 RC = &PPC::VSFRCRegClass;
2415 RC = &PPC::F8RCRegClass;
2421 RC = &PPC::VRRCRegClass;
2425 RC = &PPC::VSHRCRegClass;
2429 // Transform the arguments stored in physical registers into virtual ones.
2430 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2431 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2432 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2434 if (ValVT == MVT::i1)
2435 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2437 InVals.push_back(ArgValue);
2439 // Argument stored in memory.
2440 assert(VA.isMemLoc());
2442 unsigned ArgSize = VA.getLocVT().getStoreSize();
2443 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2446 // Create load nodes to retrieve arguments from the stack.
2447 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2448 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2449 MachinePointerInfo(),
2450 false, false, false, 0));
2454 // Assign locations to all of the incoming aggregate by value arguments.
2455 // Aggregates passed by value are stored in the local variable space of the
2456 // caller's stack frame, right above the parameter list area.
2457 SmallVector<CCValAssign, 16> ByValArgLocs;
2458 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2459 ByValArgLocs, *DAG.getContext());
2461 // Reserve stack space for the allocations in CCInfo.
2462 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2464 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2466 // Area that is at least reserved in the caller of this function.
2467 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2468 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2470 // Set the size that is at least reserved in caller of this function. Tail
2471 // call optimized function's reserved stack space needs to be aligned so that
2472 // taking the difference between two stack areas will result in an aligned
2474 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2475 FuncInfo->setMinReservedArea(MinReservedArea);
2477 SmallVector<SDValue, 8> MemOps;
2479 // If the function takes variable number of arguments, make a frame index for
2480 // the start of the first vararg value... for expansion of llvm.va_start.
2482 static const MCPhysReg GPArgRegs[] = {
2483 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2484 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2486 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2488 static const MCPhysReg FPArgRegs[] = {
2489 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2492 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2494 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2496 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2499 // Make room for NumGPArgRegs and NumFPArgRegs.
2500 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2501 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2503 FuncInfo->setVarArgsStackOffset(
2504 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2505 CCInfo.getNextStackOffset(), true));
2507 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2508 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2510 // The fixed integer arguments of a variadic function are stored to the
2511 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2512 // the result of va_next.
2513 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2514 // Get an existing live-in vreg, or add a new one.
2515 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2517 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2519 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2520 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2521 MachinePointerInfo(), false, false, 0);
2522 MemOps.push_back(Store);
2523 // Increment the address by four for the next argument to store
2524 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2525 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2528 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2530 // The double arguments are stored to the VarArgsFrameIndex
2532 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2533 // Get an existing live-in vreg, or add a new one.
2534 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2536 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2538 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2539 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2540 MachinePointerInfo(), false, false, 0);
2541 MemOps.push_back(Store);
2542 // Increment the address by eight for the next argument to store
2543 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2545 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2549 if (!MemOps.empty())
2550 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2555 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2556 // value to MVT::i64 and then truncate to the correct register size.
2558 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2559 SelectionDAG &DAG, SDValue ArgVal,
2562 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2563 DAG.getValueType(ObjectVT));
2564 else if (Flags.isZExt())
2565 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2566 DAG.getValueType(ObjectVT));
2568 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2572 PPCTargetLowering::LowerFormalArguments_64SVR4(
2574 CallingConv::ID CallConv, bool isVarArg,
2575 const SmallVectorImpl<ISD::InputArg>
2577 SDLoc dl, SelectionDAG &DAG,
2578 SmallVectorImpl<SDValue> &InVals) const {
2579 // TODO: add description of PPC stack frame format, or at least some docs.
2581 bool isELFv2ABI = Subtarget.isELFv2ABI();
2582 bool isLittleEndian = Subtarget.isLittleEndian();
2583 MachineFunction &MF = DAG.getMachineFunction();
2584 MachineFrameInfo *MFI = MF.getFrameInfo();
2585 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2587 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2588 // Potential tail calls could cause overwriting of argument stack slots.
2589 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2590 (CallConv == CallingConv::Fast));
2591 unsigned PtrByteSize = 8;
2593 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2596 static const MCPhysReg GPR[] = {
2597 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2598 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2601 static const MCPhysReg *FPR = GetFPR();
2603 static const MCPhysReg VR[] = {
2604 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2605 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2607 static const MCPhysReg VSRH[] = {
2608 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2609 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2612 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2613 const unsigned Num_FPR_Regs = 13;
2614 const unsigned Num_VR_Regs = array_lengthof(VR);
2616 // Do a first pass over the arguments to determine whether the ABI
2617 // guarantees that our caller has allocated the parameter save area
2618 // on its stack frame. In the ELFv1 ABI, this is always the case;
2619 // in the ELFv2 ABI, it is true if this is a vararg function or if
2620 // any parameter is located in a stack slot.
2622 bool HasParameterArea = !isELFv2ABI || isVarArg;
2623 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2624 unsigned NumBytes = LinkageSize;
2625 unsigned AvailableFPRs = Num_FPR_Regs;
2626 unsigned AvailableVRs = Num_VR_Regs;
2627 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2628 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2629 PtrByteSize, LinkageSize, ParamAreaSize,
2630 NumBytes, AvailableFPRs, AvailableVRs))
2631 HasParameterArea = true;
2633 // Add DAG nodes to load the arguments or copy them out of registers. On
2634 // entry to a function on PPC, the arguments start after the linkage area,
2635 // although the first ones are often in registers.
2637 unsigned ArgOffset = LinkageSize;
2638 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
2639 SmallVector<SDValue, 8> MemOps;
2640 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2641 unsigned CurArgIdx = 0;
2642 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2644 bool needsLoad = false;
2645 EVT ObjectVT = Ins[ArgNo].VT;
2646 EVT OrigVT = Ins[ArgNo].ArgVT;
2647 unsigned ObjSize = ObjectVT.getStoreSize();
2648 unsigned ArgSize = ObjSize;
2649 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2650 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2651 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2653 /* Respect alignment of argument on the stack. */
2655 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2656 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2657 unsigned CurArgOffset = ArgOffset;
2659 /* Compute GPR index associated with argument offset. */
2660 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2661 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2663 // FIXME the codegen can be much improved in some cases.
2664 // We do not have to keep everything in memory.
2665 if (Flags.isByVal()) {
2666 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2667 ObjSize = Flags.getByValSize();
2668 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2669 // Empty aggregate parameters do not take up registers. Examples:
2673 // etc. However, we have to provide a place-holder in InVals, so
2674 // pretend we have an 8-byte item at the current address for that
2677 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2678 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2679 InVals.push_back(FIN);
2683 // Create a stack object covering all stack doublewords occupied
2684 // by the argument. If the argument is (fully or partially) on
2685 // the stack, or if the argument is fully in registers but the
2686 // caller has allocated the parameter save anyway, we can refer
2687 // directly to the caller's stack frame. Otherwise, create a
2688 // local copy in our own frame.
2690 if (HasParameterArea ||
2691 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2692 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false);
2694 FI = MFI->CreateStackObject(ArgSize, Align, false);
2695 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2697 // Handle aggregates smaller than 8 bytes.
2698 if (ObjSize < PtrByteSize) {
2699 // The value of the object is its address, which differs from the
2700 // address of the enclosing doubleword on big-endian systems.
2702 if (!isLittleEndian) {
2703 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2704 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2706 InVals.push_back(Arg);
2708 if (GPR_idx != Num_GPR_Regs) {
2709 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2710 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2713 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2714 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2715 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2716 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2717 MachinePointerInfo(FuncArg),
2718 ObjType, false, false, 0);
2720 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2721 // store the whole register as-is to the parameter save area
2723 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2724 MachinePointerInfo(FuncArg),
2728 MemOps.push_back(Store);
2730 // Whether we copied from a register or not, advance the offset
2731 // into the parameter save area by a full doubleword.
2732 ArgOffset += PtrByteSize;
2736 // The value of the object is its address, which is the address of
2737 // its first stack doubleword.
2738 InVals.push_back(FIN);
2740 // Store whatever pieces of the object are in registers to memory.
2741 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2742 if (GPR_idx == Num_GPR_Regs)
2745 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2746 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2749 SDValue Off = DAG.getConstant(j, PtrVT);
2750 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2752 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2753 MachinePointerInfo(FuncArg, j),
2755 MemOps.push_back(Store);
2758 ArgOffset += ArgSize;
2762 switch (ObjectVT.getSimpleVT().SimpleTy) {
2763 default: llvm_unreachable("Unhandled argument type!");
2767 // These can be scalar arguments or elements of an integer array type
2768 // passed directly. Clang may use those instead of "byval" aggregate
2769 // types to avoid forcing arguments to memory unnecessarily.
2770 if (GPR_idx != Num_GPR_Regs) {
2771 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2772 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2774 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2775 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2776 // value to MVT::i64 and then truncate to the correct register size.
2777 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2780 ArgSize = PtrByteSize;
2787 // These can be scalar arguments or elements of a float array type
2788 // passed directly. The latter are used to implement ELFv2 homogenous
2789 // float aggregates.
2790 if (FPR_idx != Num_FPR_Regs) {
2793 if (ObjectVT == MVT::f32)
2794 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2796 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2797 &PPC::VSFRCRegClass :
2798 &PPC::F8RCRegClass);
2800 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2802 } else if (GPR_idx != Num_GPR_Regs) {
2803 // This can only ever happen in the presence of f32 array types,
2804 // since otherwise we never run out of FPRs before running out
2806 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2807 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2809 if (ObjectVT == MVT::f32) {
2810 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2811 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2812 DAG.getConstant(32, MVT::i32));
2813 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2816 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2821 // When passing an array of floats, the array occupies consecutive
2822 // space in the argument area; only round up to the next doubleword
2823 // at the end of the array. Otherwise, each float takes 8 bytes.
2824 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2825 ArgOffset += ArgSize;
2826 if (Flags.isInConsecutiveRegsLast())
2827 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2835 // These can be scalar arguments or elements of a vector array type
2836 // passed directly. The latter are used to implement ELFv2 homogenous
2837 // vector aggregates.
2838 if (VR_idx != Num_VR_Regs) {
2839 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2840 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2841 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2842 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2851 // We need to load the argument to a virtual register if we determined
2852 // above that we ran out of physical registers of the appropriate type.
2854 if (ObjSize < ArgSize && !isLittleEndian)
2855 CurArgOffset += ArgSize - ObjSize;
2856 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2857 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2858 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2859 false, false, false, 0);
2862 InVals.push_back(ArgVal);
2865 // Area that is at least reserved in the caller of this function.
2866 unsigned MinReservedArea;
2867 if (HasParameterArea)
2868 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2870 MinReservedArea = LinkageSize;
2872 // Set the size that is at least reserved in caller of this function. Tail
2873 // call optimized functions' reserved stack space needs to be aligned so that
2874 // taking the difference between two stack areas will result in an aligned
2876 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2877 FuncInfo->setMinReservedArea(MinReservedArea);
2879 // If the function takes variable number of arguments, make a frame index for
2880 // the start of the first vararg value... for expansion of llvm.va_start.
2882 int Depth = ArgOffset;
2884 FuncInfo->setVarArgsFrameIndex(
2885 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2886 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2888 // If this function is vararg, store any remaining integer argument regs
2889 // to their spots on the stack so that they may be loaded by deferencing the
2890 // result of va_next.
2891 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2892 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2893 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2894 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2895 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2896 MachinePointerInfo(), false, false, 0);
2897 MemOps.push_back(Store);
2898 // Increment the address by four for the next argument to store
2899 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2900 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2904 if (!MemOps.empty())
2905 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2911 PPCTargetLowering::LowerFormalArguments_Darwin(
2913 CallingConv::ID CallConv, bool isVarArg,
2914 const SmallVectorImpl<ISD::InputArg>
2916 SDLoc dl, SelectionDAG &DAG,
2917 SmallVectorImpl<SDValue> &InVals) const {
2918 // TODO: add description of PPC stack frame format, or at least some docs.
2920 MachineFunction &MF = DAG.getMachineFunction();
2921 MachineFrameInfo *MFI = MF.getFrameInfo();
2922 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2924 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2925 bool isPPC64 = PtrVT == MVT::i64;
2926 // Potential tail calls could cause overwriting of argument stack slots.
2927 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2928 (CallConv == CallingConv::Fast));
2929 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2931 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
2933 unsigned ArgOffset = LinkageSize;
2934 // Area that is at least reserved in caller of this function.
2935 unsigned MinReservedArea = ArgOffset;
2937 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2938 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2939 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2941 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2942 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2943 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2946 static const MCPhysReg *FPR = GetFPR();
2948 static const MCPhysReg VR[] = {
2949 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2950 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2953 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2954 const unsigned Num_FPR_Regs = 13;
2955 const unsigned Num_VR_Regs = array_lengthof( VR);
2957 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2959 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2961 // In 32-bit non-varargs functions, the stack space for vectors is after the
2962 // stack space for non-vectors. We do not use this space unless we have
2963 // too many vectors to fit in registers, something that only occurs in
2964 // constructed examples:), but we have to walk the arglist to figure
2965 // that out...for the pathological case, compute VecArgOffset as the
2966 // start of the vector parameter area. Computing VecArgOffset is the
2967 // entire point of the following loop.
2968 unsigned VecArgOffset = ArgOffset;
2969 if (!isVarArg && !isPPC64) {
2970 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2972 EVT ObjectVT = Ins[ArgNo].VT;
2973 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2975 if (Flags.isByVal()) {
2976 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2977 unsigned ObjSize = Flags.getByValSize();
2979 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2980 VecArgOffset += ArgSize;
2984 switch(ObjectVT.getSimpleVT().SimpleTy) {
2985 default: llvm_unreachable("Unhandled argument type!");
2991 case MVT::i64: // PPC64
2993 // FIXME: We are guaranteed to be !isPPC64 at this point.
2994 // Does MVT::i64 apply?
3001 // Nothing to do, we're only looking at Nonvector args here.
3006 // We've found where the vector parameter area in memory is. Skip the
3007 // first 12 parameters; these don't use that memory.
3008 VecArgOffset = ((VecArgOffset+15)/16)*16;
3009 VecArgOffset += 12*16;
3011 // Add DAG nodes to load the arguments or copy them out of registers. On
3012 // entry to a function on PPC, the arguments start after the linkage area,
3013 // although the first ones are often in registers.
3015 SmallVector<SDValue, 8> MemOps;
3016 unsigned nAltivecParamsAtEnd = 0;
3017 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3018 unsigned CurArgIdx = 0;
3019 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3021 bool needsLoad = false;
3022 EVT ObjectVT = Ins[ArgNo].VT;
3023 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3024 unsigned ArgSize = ObjSize;
3025 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3026 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3027 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3029 unsigned CurArgOffset = ArgOffset;
3031 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3032 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3033 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3034 if (isVarArg || isPPC64) {
3035 MinReservedArea = ((MinReservedArea+15)/16)*16;
3036 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3039 } else nAltivecParamsAtEnd++;
3041 // Calculate min reserved area.
3042 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3046 // FIXME the codegen can be much improved in some cases.
3047 // We do not have to keep everything in memory.
3048 if (Flags.isByVal()) {
3049 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3050 ObjSize = Flags.getByValSize();
3051 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3052 // Objects of size 1 and 2 are right justified, everything else is
3053 // left justified. This means the memory address is adjusted forwards.
3054 if (ObjSize==1 || ObjSize==2) {
3055 CurArgOffset = CurArgOffset + (4 - ObjSize);
3057 // The value of the object is its address.
3058 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
3059 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3060 InVals.push_back(FIN);
3061 if (ObjSize==1 || ObjSize==2) {
3062 if (GPR_idx != Num_GPR_Regs) {
3065 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3067 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3068 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3069 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3070 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3071 MachinePointerInfo(FuncArg),
3072 ObjType, false, false, 0);
3073 MemOps.push_back(Store);
3077 ArgOffset += PtrByteSize;
3081 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3082 // Store whatever pieces of the object are in registers
3083 // to memory. ArgOffset will be the address of the beginning
3085 if (GPR_idx != Num_GPR_Regs) {
3088 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3090 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3091 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3092 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3093 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3094 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3095 MachinePointerInfo(FuncArg, j),
3097 MemOps.push_back(Store);
3099 ArgOffset += PtrByteSize;
3101 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3108 switch (ObjectVT.getSimpleVT().SimpleTy) {
3109 default: llvm_unreachable("Unhandled argument type!");
3113 if (GPR_idx != Num_GPR_Regs) {
3114 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3115 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3117 if (ObjectVT == MVT::i1)
3118 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3123 ArgSize = PtrByteSize;
3125 // All int arguments reserve stack space in the Darwin ABI.
3126 ArgOffset += PtrByteSize;
3130 case MVT::i64: // PPC64
3131 if (GPR_idx != Num_GPR_Regs) {
3132 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3133 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3135 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3136 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3137 // value to MVT::i64 and then truncate to the correct register size.
3138 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3143 ArgSize = PtrByteSize;
3145 // All int arguments reserve stack space in the Darwin ABI.
3151 // Every 4 bytes of argument space consumes one of the GPRs available for
3152 // argument passing.
3153 if (GPR_idx != Num_GPR_Regs) {
3155 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3158 if (FPR_idx != Num_FPR_Regs) {
3161 if (ObjectVT == MVT::f32)
3162 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3164 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3166 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3172 // All FP arguments reserve stack space in the Darwin ABI.
3173 ArgOffset += isPPC64 ? 8 : ObjSize;
3179 // Note that vector arguments in registers don't reserve stack space,
3180 // except in varargs functions.
3181 if (VR_idx != Num_VR_Regs) {
3182 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3183 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3185 while ((ArgOffset % 16) != 0) {
3186 ArgOffset += PtrByteSize;
3187 if (GPR_idx != Num_GPR_Regs)
3191 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3195 if (!isVarArg && !isPPC64) {
3196 // Vectors go after all the nonvectors.
3197 CurArgOffset = VecArgOffset;
3200 // Vectors are aligned.
3201 ArgOffset = ((ArgOffset+15)/16)*16;
3202 CurArgOffset = ArgOffset;
3210 // We need to load the argument to a virtual register if we determined above
3211 // that we ran out of physical registers of the appropriate type.
3213 int FI = MFI->CreateFixedObject(ObjSize,
3214 CurArgOffset + (ArgSize - ObjSize),
3216 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3217 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3218 false, false, false, 0);
3221 InVals.push_back(ArgVal);
3224 // Allow for Altivec parameters at the end, if needed.
3225 if (nAltivecParamsAtEnd) {
3226 MinReservedArea = ((MinReservedArea+15)/16)*16;
3227 MinReservedArea += 16*nAltivecParamsAtEnd;
3230 // Area that is at least reserved in the caller of this function.
3231 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3233 // Set the size that is at least reserved in caller of this function. Tail
3234 // call optimized functions' reserved stack space needs to be aligned so that
3235 // taking the difference between two stack areas will result in an aligned
3237 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3238 FuncInfo->setMinReservedArea(MinReservedArea);
3240 // If the function takes variable number of arguments, make a frame index for
3241 // the start of the first vararg value... for expansion of llvm.va_start.
3243 int Depth = ArgOffset;
3245 FuncInfo->setVarArgsFrameIndex(
3246 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3248 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3250 // If this function is vararg, store any remaining integer argument regs
3251 // to their spots on the stack so that they may be loaded by deferencing the
3252 // result of va_next.
3253 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3257 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3259 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3261 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3262 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3263 MachinePointerInfo(), false, false, 0);
3264 MemOps.push_back(Store);
3265 // Increment the address by four for the next argument to store
3266 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3267 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3271 if (!MemOps.empty())
3272 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3277 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3278 /// adjusted to accommodate the arguments for the tailcall.
3279 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3280 unsigned ParamSize) {
3282 if (!isTailCall) return 0;
3284 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3285 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3286 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3287 // Remember only if the new adjustement is bigger.
3288 if (SPDiff < FI->getTailCallSPDelta())
3289 FI->setTailCallSPDelta(SPDiff);
3294 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3295 /// for tail call optimization. Targets which want to do tail call
3296 /// optimization should implement this function.
3298 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3299 CallingConv::ID CalleeCC,
3301 const SmallVectorImpl<ISD::InputArg> &Ins,
3302 SelectionDAG& DAG) const {
3303 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3306 // Variable argument functions are not supported.
3310 MachineFunction &MF = DAG.getMachineFunction();
3311 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3312 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3313 // Functions containing by val parameters are not supported.
3314 for (unsigned i = 0; i != Ins.size(); i++) {
3315 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3316 if (Flags.isByVal()) return false;
3319 // Non-PIC/GOT tail calls are supported.
3320 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3323 // At the moment we can only do local tail calls (in same module, hidden
3324 // or protected) if we are generating PIC.
3325 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3326 return G->getGlobal()->hasHiddenVisibility()
3327 || G->getGlobal()->hasProtectedVisibility();
3333 /// isCallCompatibleAddress - Return the immediate to use if the specified
3334 /// 32-bit value is representable in the immediate field of a BxA instruction.
3335 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3336 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3337 if (!C) return nullptr;
3339 int Addr = C->getZExtValue();
3340 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3341 SignExtend32<26>(Addr) != Addr)
3342 return nullptr; // Top 6 bits have to be sext of immediate.
3344 return DAG.getConstant((int)C->getZExtValue() >> 2,
3345 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3350 struct TailCallArgumentInfo {
3355 TailCallArgumentInfo() : FrameIdx(0) {}
3360 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3362 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3364 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3365 SmallVectorImpl<SDValue> &MemOpChains,
3367 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3368 SDValue Arg = TailCallArgs[i].Arg;
3369 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3370 int FI = TailCallArgs[i].FrameIdx;
3371 // Store relative to framepointer.
3372 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3373 MachinePointerInfo::getFixedStack(FI),
3378 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3379 /// the appropriate stack slot for the tail call optimized function call.
3380 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3381 MachineFunction &MF,
3390 // Calculate the new stack slot for the return address.
3391 int SlotSize = isPPC64 ? 8 : 4;
3392 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3394 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3395 NewRetAddrLoc, true);
3396 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3397 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3398 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3399 MachinePointerInfo::getFixedStack(NewRetAddr),
3402 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3403 // slot as the FP is never overwritten.
3406 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3407 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3409 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3410 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3411 MachinePointerInfo::getFixedStack(NewFPIdx),
3418 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3419 /// the position of the argument.
3421 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3422 SDValue Arg, int SPDiff, unsigned ArgOffset,
3423 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3424 int Offset = ArgOffset + SPDiff;
3425 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3426 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3427 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3428 SDValue FIN = DAG.getFrameIndex(FI, VT);
3429 TailCallArgumentInfo Info;
3431 Info.FrameIdxOp = FIN;
3433 TailCallArguments.push_back(Info);
3436 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3437 /// stack slot. Returns the chain as result and the loaded frame pointers in
3438 /// LROpOut/FPOpout. Used when tail calling.
3439 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3447 // Load the LR and FP stack slot for later adjusting.
3448 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3449 LROpOut = getReturnAddrFrameIndex(DAG);
3450 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3451 false, false, false, 0);
3452 Chain = SDValue(LROpOut.getNode(), 1);
3454 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3455 // slot as the FP is never overwritten.
3457 FPOpOut = getFramePointerFrameIndex(DAG);
3458 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3459 false, false, false, 0);
3460 Chain = SDValue(FPOpOut.getNode(), 1);
3466 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3467 /// by "Src" to address "Dst" of size "Size". Alignment information is
3468 /// specified by the specific parameter attribute. The copy will be passed as
3469 /// a byval function parameter.
3470 /// Sometimes what we are copying is the end of a larger object, the part that
3471 /// does not fit in registers.
3473 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3474 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3476 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3477 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3478 false, false, MachinePointerInfo(),
3479 MachinePointerInfo());
3482 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3485 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3486 SDValue Arg, SDValue PtrOff, int SPDiff,
3487 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3488 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3489 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3491 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3496 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3498 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3499 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3500 DAG.getConstant(ArgOffset, PtrVT));
3502 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3503 MachinePointerInfo(), false, false, 0));
3504 // Calculate and remember argument location.
3505 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3510 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3511 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3512 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3513 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3514 MachineFunction &MF = DAG.getMachineFunction();
3516 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3517 // might overwrite each other in case of tail call optimization.
3518 SmallVector<SDValue, 8> MemOpChains2;
3519 // Do not flag preceding copytoreg stuff together with the following stuff.
3521 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3523 if (!MemOpChains2.empty())
3524 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3526 // Store the return address to the appropriate stack slot.
3527 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3528 isPPC64, isDarwinABI, dl);
3530 // Emit callseq_end just before tailcall node.
3531 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3532 DAG.getIntPtrConstant(0, true), InFlag, dl);
3533 InFlag = Chain.getValue(1);
3537 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3538 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3539 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3540 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3541 const PPCSubtarget &Subtarget) {
3543 bool isPPC64 = Subtarget.isPPC64();
3544 bool isSVR4ABI = Subtarget.isSVR4ABI();
3545 bool isELFv2ABI = Subtarget.isELFv2ABI();
3547 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3548 NodeTys.push_back(MVT::Other); // Returns a chain
3549 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3551 unsigned CallOpc = PPCISD::CALL;
3553 bool needIndirectCall = true;
3554 if (!isSVR4ABI || !isPPC64)
3555 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3556 // If this is an absolute destination address, use the munged value.
3557 Callee = SDValue(Dest, 0);
3558 needIndirectCall = false;
3561 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3562 unsigned OpFlags = 0;
3563 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3564 (Subtarget.getTargetTriple().isMacOSX() &&
3565 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3566 (G->getGlobal()->isDeclaration() ||
3567 G->getGlobal()->isWeakForLinker())) ||
3568 (Subtarget.isTargetELF() && !isPPC64 &&
3569 !G->getGlobal()->hasLocalLinkage() &&
3570 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3571 // PC-relative references to external symbols should go through $stub,
3572 // unless we're building with the leopard linker or later, which
3573 // automatically synthesizes these stubs.
3574 OpFlags = PPCII::MO_PLT_OR_STUB;
3577 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3578 // every direct call is) turn it into a TargetGlobalAddress /
3579 // TargetExternalSymbol node so that legalize doesn't hack it.
3580 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3581 Callee.getValueType(), 0, OpFlags);
3582 needIndirectCall = false;
3585 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3586 unsigned char OpFlags = 0;
3588 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3589 (Subtarget.getTargetTriple().isMacOSX() &&
3590 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3591 (Subtarget.isTargetELF() && !isPPC64 &&
3592 DAG.getTarget().getRelocationModel() == Reloc::PIC_) ) {
3593 // PC-relative references to external symbols should go through $stub,
3594 // unless we're building with the leopard linker or later, which
3595 // automatically synthesizes these stubs.
3596 OpFlags = PPCII::MO_PLT_OR_STUB;
3599 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3601 needIndirectCall = false;
3604 if (needIndirectCall) {
3605 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3606 // to do the call, we can't use PPCISD::CALL.
3607 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3609 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3610 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3611 // entry point, but to the function descriptor (the function entry point
3612 // address is part of the function descriptor though).
3613 // The function descriptor is a three doubleword structure with the
3614 // following fields: function entry point, TOC base address and
3615 // environment pointer.
3616 // Thus for a call through a function pointer, the following actions need
3618 // 1. Save the TOC of the caller in the TOC save area of its stack
3619 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3620 // 2. Load the address of the function entry point from the function
3622 // 3. Load the TOC of the callee from the function descriptor into r2.
3623 // 4. Load the environment pointer from the function descriptor into
3625 // 5. Branch to the function entry point address.
3626 // 6. On return of the callee, the TOC of the caller needs to be
3627 // restored (this is done in FinishCall()).
3629 // All those operations are flagged together to ensure that no other
3630 // operations can be scheduled in between. E.g. without flagging the
3631 // operations together, a TOC access in the caller could be scheduled
3632 // between the load of the callee TOC and the branch to the callee, which
3633 // results in the TOC access going through the TOC of the callee instead
3634 // of going through the TOC of the caller, which leads to incorrect code.
3636 // Load the address of the function entry point from the function
3638 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3639 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3640 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3641 Chain = LoadFuncPtr.getValue(1);
3642 InFlag = LoadFuncPtr.getValue(2);
3644 // Load environment pointer into r11.
3645 // Offset of the environment pointer within the function descriptor.
3646 SDValue PtrOff = DAG.getIntPtrConstant(16);
3648 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3649 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3651 Chain = LoadEnvPtr.getValue(1);
3652 InFlag = LoadEnvPtr.getValue(2);
3654 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3656 Chain = EnvVal.getValue(0);
3657 InFlag = EnvVal.getValue(1);
3659 // Load TOC of the callee into r2. We are using a target-specific load
3660 // with r2 hard coded, because the result of a target-independent load
3661 // would never go directly into r2, since r2 is a reserved register (which
3662 // prevents the register allocator from allocating it), resulting in an
3663 // additional register being allocated and an unnecessary move instruction
3665 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3666 SDValue TOCOff = DAG.getIntPtrConstant(8);
3667 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3668 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3670 Chain = LoadTOCPtr.getValue(0);
3671 InFlag = LoadTOCPtr.getValue(1);
3673 MTCTROps[0] = Chain;
3674 MTCTROps[1] = LoadFuncPtr;
3675 MTCTROps[2] = InFlag;
3678 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3679 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3680 InFlag = Chain.getValue(1);
3683 NodeTys.push_back(MVT::Other);
3684 NodeTys.push_back(MVT::Glue);
3685 Ops.push_back(Chain);
3686 CallOpc = PPCISD::BCTRL;
3687 Callee.setNode(nullptr);
3688 // Add use of X11 (holding environment pointer)
3689 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3690 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3691 // Add CTR register as callee so a bctr can be emitted later.
3693 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3696 // If this is a direct call, pass the chain and the callee.
3697 if (Callee.getNode()) {
3698 Ops.push_back(Chain);
3699 Ops.push_back(Callee);
3701 // If this is a tail call add stack pointer delta.
3703 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3705 // Add argument registers to the end of the list so that they are known live
3707 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3708 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3709 RegsToPass[i].second.getValueType()));
3711 // Direct calls in the ELFv2 ABI need the TOC register live into the call.
3712 if (Callee.getNode() && isELFv2ABI)
3713 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3719 bool isLocalCall(const SDValue &Callee)
3721 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3722 return !G->getGlobal()->isDeclaration() &&
3723 !G->getGlobal()->isWeakForLinker();
3728 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3729 CallingConv::ID CallConv, bool isVarArg,
3730 const SmallVectorImpl<ISD::InputArg> &Ins,
3731 SDLoc dl, SelectionDAG &DAG,
3732 SmallVectorImpl<SDValue> &InVals) const {
3734 SmallVector<CCValAssign, 16> RVLocs;
3735 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3737 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3739 // Copy all of the result registers out of their specified physreg.
3740 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3741 CCValAssign &VA = RVLocs[i];
3742 assert(VA.isRegLoc() && "Can only return in registers!");
3744 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3745 VA.getLocReg(), VA.getLocVT(), InFlag);
3746 Chain = Val.getValue(1);
3747 InFlag = Val.getValue(2);
3749 switch (VA.getLocInfo()) {
3750 default: llvm_unreachable("Unknown loc info!");
3751 case CCValAssign::Full: break;
3752 case CCValAssign::AExt:
3753 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3755 case CCValAssign::ZExt:
3756 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3757 DAG.getValueType(VA.getValVT()));
3758 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3760 case CCValAssign::SExt:
3761 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3762 DAG.getValueType(VA.getValVT()));
3763 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3767 InVals.push_back(Val);
3774 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3775 bool isTailCall, bool isVarArg,
3777 SmallVector<std::pair<unsigned, SDValue>, 8>
3779 SDValue InFlag, SDValue Chain,
3781 int SPDiff, unsigned NumBytes,
3782 const SmallVectorImpl<ISD::InputArg> &Ins,
3783 SmallVectorImpl<SDValue> &InVals) const {
3785 bool isELFv2ABI = Subtarget.isELFv2ABI();
3786 std::vector<EVT> NodeTys;
3787 SmallVector<SDValue, 8> Ops;
3788 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3789 isTailCall, RegsToPass, Ops, NodeTys,
3792 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3793 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3794 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3796 // When performing tail call optimization the callee pops its arguments off
3797 // the stack. Account for this here so these bytes can be pushed back on in
3798 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3799 int BytesCalleePops =
3800 (CallConv == CallingConv::Fast &&
3801 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3803 // Add a register mask operand representing the call-preserved registers.
3804 const TargetRegisterInfo *TRI =
3805 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3806 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3807 assert(Mask && "Missing call preserved mask for calling convention");
3808 Ops.push_back(DAG.getRegisterMask(Mask));
3810 if (InFlag.getNode())
3811 Ops.push_back(InFlag);
3815 assert(((Callee.getOpcode() == ISD::Register &&
3816 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3817 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3818 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3819 isa<ConstantSDNode>(Callee)) &&
3820 "Expecting an global address, external symbol, absolute value or register");
3822 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3825 // Add a NOP immediately after the branch instruction when using the 64-bit
3826 // SVR4 ABI. At link time, if caller and callee are in a different module and
3827 // thus have a different TOC, the call will be replaced with a call to a stub
3828 // function which saves the current TOC, loads the TOC of the callee and
3829 // branches to the callee. The NOP will be replaced with a load instruction
3830 // which restores the TOC of the caller from the TOC save slot of the current
3831 // stack frame. If caller and callee belong to the same module (and have the
3832 // same TOC), the NOP will remain unchanged.
3834 bool needsTOCRestore = false;
3835 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3836 if (CallOpc == PPCISD::BCTRL) {
3837 // This is a call through a function pointer.
3838 // Restore the caller TOC from the save area into R2.
3839 // See PrepareCall() for more information about calls through function
3840 // pointers in the 64-bit SVR4 ABI.
3841 // We are using a target-specific load with r2 hard coded, because the
3842 // result of a target-independent load would never go directly into r2,
3843 // since r2 is a reserved register (which prevents the register allocator
3844 // from allocating it), resulting in an additional register being
3845 // allocated and an unnecessary move instruction being generated.
3846 needsTOCRestore = true;
3847 } else if ((CallOpc == PPCISD::CALL) &&
3848 (!isLocalCall(Callee) ||
3849 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3850 // Otherwise insert NOP for non-local calls.
3851 CallOpc = PPCISD::CALL_NOP;
3855 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3856 InFlag = Chain.getValue(1);
3858 if (needsTOCRestore) {
3859 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3860 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3861 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3862 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3863 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3864 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3865 Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag);
3866 InFlag = Chain.getValue(1);
3869 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3870 DAG.getIntPtrConstant(BytesCalleePops, true),
3873 InFlag = Chain.getValue(1);
3875 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3876 Ins, dl, DAG, InVals);
3880 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3881 SmallVectorImpl<SDValue> &InVals) const {
3882 SelectionDAG &DAG = CLI.DAG;
3884 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3885 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3886 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3887 SDValue Chain = CLI.Chain;
3888 SDValue Callee = CLI.Callee;
3889 bool &isTailCall = CLI.IsTailCall;
3890 CallingConv::ID CallConv = CLI.CallConv;
3891 bool isVarArg = CLI.IsVarArg;
3894 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3897 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3898 report_fatal_error("failed to perform tail call elimination on a call "
3899 "site marked musttail");
3901 if (Subtarget.isSVR4ABI()) {
3902 if (Subtarget.isPPC64())
3903 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3904 isTailCall, Outs, OutVals, Ins,
3907 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3908 isTailCall, Outs, OutVals, Ins,
3912 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3913 isTailCall, Outs, OutVals, Ins,
3918 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3919 CallingConv::ID CallConv, bool isVarArg,
3921 const SmallVectorImpl<ISD::OutputArg> &Outs,
3922 const SmallVectorImpl<SDValue> &OutVals,
3923 const SmallVectorImpl<ISD::InputArg> &Ins,
3924 SDLoc dl, SelectionDAG &DAG,
3925 SmallVectorImpl<SDValue> &InVals) const {
3926 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3927 // of the 32-bit SVR4 ABI stack frame layout.
3929 assert((CallConv == CallingConv::C ||
3930 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3932 unsigned PtrByteSize = 4;
3934 MachineFunction &MF = DAG.getMachineFunction();
3936 // Mark this function as potentially containing a function that contains a
3937 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3938 // and restoring the callers stack pointer in this functions epilog. This is
3939 // done because by tail calling the called function might overwrite the value
3940 // in this function's (MF) stack pointer stack slot 0(SP).
3941 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3942 CallConv == CallingConv::Fast)
3943 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3945 // Count how many bytes are to be pushed on the stack, including the linkage
3946 // area, parameter list area and the part of the local variable space which
3947 // contains copies of aggregates which are passed by value.
3949 // Assign locations to all of the outgoing arguments.
3950 SmallVector<CCValAssign, 16> ArgLocs;
3951 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3954 // Reserve space for the linkage area on the stack.
3955 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
3959 // Handle fixed and variable vector arguments differently.
3960 // Fixed vector arguments go into registers as long as registers are
3961 // available. Variable vector arguments always go into memory.
3962 unsigned NumArgs = Outs.size();
3964 for (unsigned i = 0; i != NumArgs; ++i) {
3965 MVT ArgVT = Outs[i].VT;
3966 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3969 if (Outs[i].IsFixed) {
3970 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3973 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3979 errs() << "Call operand #" << i << " has unhandled type "
3980 << EVT(ArgVT).getEVTString() << "\n";
3982 llvm_unreachable(nullptr);
3986 // All arguments are treated the same.
3987 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3990 // Assign locations to all of the outgoing aggregate by value arguments.
3991 SmallVector<CCValAssign, 16> ByValArgLocs;
3992 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3993 ByValArgLocs, *DAG.getContext());
3995 // Reserve stack space for the allocations in CCInfo.
3996 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3998 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4000 // Size of the linkage area, parameter list area and the part of the local
4001 // space variable where copies of aggregates which are passed by value are
4003 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4005 // Calculate by how many bytes the stack has to be adjusted in case of tail
4006 // call optimization.
4007 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4009 // Adjust the stack pointer for the new arguments...
4010 // These operations are automatically eliminated by the prolog/epilog pass
4011 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4013 SDValue CallSeqStart = Chain;
4015 // Load the return address and frame pointer so it can be moved somewhere else
4018 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4021 // Set up a copy of the stack pointer for use loading and storing any
4022 // arguments that may not fit in the registers available for argument
4024 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4026 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4027 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4028 SmallVector<SDValue, 8> MemOpChains;
4030 bool seenFloatArg = false;
4031 // Walk the register/memloc assignments, inserting copies/loads.
4032 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4035 CCValAssign &VA = ArgLocs[i];
4036 SDValue Arg = OutVals[i];
4037 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4039 if (Flags.isByVal()) {
4040 // Argument is an aggregate which is passed by value, thus we need to
4041 // create a copy of it in the local variable space of the current stack
4042 // frame (which is the stack frame of the caller) and pass the address of
4043 // this copy to the callee.
4044 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4045 CCValAssign &ByValVA = ByValArgLocs[j++];
4046 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4048 // Memory reserved in the local variable space of the callers stack frame.
4049 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4051 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4052 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4054 // Create a copy of the argument in the local area of the current
4056 SDValue MemcpyCall =
4057 CreateCopyOfByValArgument(Arg, PtrOff,
4058 CallSeqStart.getNode()->getOperand(0),
4061 // This must go outside the CALLSEQ_START..END.
4062 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4063 CallSeqStart.getNode()->getOperand(1),
4065 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4066 NewCallSeqStart.getNode());
4067 Chain = CallSeqStart = NewCallSeqStart;
4069 // Pass the address of the aggregate copy on the stack either in a
4070 // physical register or in the parameter list area of the current stack
4071 // frame to the callee.
4075 if (VA.isRegLoc()) {
4076 if (Arg.getValueType() == MVT::i1)
4077 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4079 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4080 // Put argument in a physical register.
4081 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4083 // Put argument in the parameter list area of the current stack frame.
4084 assert(VA.isMemLoc());
4085 unsigned LocMemOffset = VA.getLocMemOffset();
4088 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4089 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4091 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4092 MachinePointerInfo(),
4095 // Calculate and remember argument location.
4096 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4102 if (!MemOpChains.empty())
4103 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4105 // Build a sequence of copy-to-reg nodes chained together with token chain
4106 // and flag operands which copy the outgoing args into the appropriate regs.
4108 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4109 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4110 RegsToPass[i].second, InFlag);
4111 InFlag = Chain.getValue(1);
4114 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4117 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4118 SDValue Ops[] = { Chain, InFlag };
4120 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4121 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4123 InFlag = Chain.getValue(1);
4127 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4128 false, TailCallArguments);
4130 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4131 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4135 // Copy an argument into memory, being careful to do this outside the
4136 // call sequence for the call to which the argument belongs.
4138 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4139 SDValue CallSeqStart,
4140 ISD::ArgFlagsTy Flags,
4143 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4144 CallSeqStart.getNode()->getOperand(0),
4146 // The MEMCPY must go outside the CALLSEQ_START..END.
4147 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4148 CallSeqStart.getNode()->getOperand(1),
4150 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4151 NewCallSeqStart.getNode());
4152 return NewCallSeqStart;
4156 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4157 CallingConv::ID CallConv, bool isVarArg,
4159 const SmallVectorImpl<ISD::OutputArg> &Outs,
4160 const SmallVectorImpl<SDValue> &OutVals,
4161 const SmallVectorImpl<ISD::InputArg> &Ins,
4162 SDLoc dl, SelectionDAG &DAG,
4163 SmallVectorImpl<SDValue> &InVals) const {
4165 bool isELFv2ABI = Subtarget.isELFv2ABI();
4166 bool isLittleEndian = Subtarget.isLittleEndian();
4167 unsigned NumOps = Outs.size();
4169 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4170 unsigned PtrByteSize = 8;
4172 MachineFunction &MF = DAG.getMachineFunction();
4174 // Mark this function as potentially containing a function that contains a
4175 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4176 // and restoring the callers stack pointer in this functions epilog. This is
4177 // done because by tail calling the called function might overwrite the value
4178 // in this function's (MF) stack pointer stack slot 0(SP).
4179 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4180 CallConv == CallingConv::Fast)
4181 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4183 // Count how many bytes are to be pushed on the stack, including the linkage
4184 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4185 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4186 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4187 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4189 unsigned NumBytes = LinkageSize;
4191 // Add up all the space actually used.
4192 for (unsigned i = 0; i != NumOps; ++i) {
4193 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4194 EVT ArgVT = Outs[i].VT;
4195 EVT OrigVT = Outs[i].ArgVT;
4197 /* Respect alignment of argument on the stack. */
4199 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4200 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4202 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4203 if (Flags.isInConsecutiveRegsLast())
4204 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4207 unsigned NumBytesActuallyUsed = NumBytes;
4209 // The prolog code of the callee may store up to 8 GPR argument registers to
4210 // the stack, allowing va_start to index over them in memory if its varargs.
4211 // Because we cannot tell if this is needed on the caller side, we have to
4212 // conservatively assume that it is needed. As such, make sure we have at
4213 // least enough stack space for the caller to store the 8 GPRs.
4214 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4215 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4217 // Tail call needs the stack to be aligned.
4218 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4219 CallConv == CallingConv::Fast)
4220 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4222 // Calculate by how many bytes the stack has to be adjusted in case of tail
4223 // call optimization.
4224 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4226 // To protect arguments on the stack from being clobbered in a tail call,
4227 // force all the loads to happen before doing any other lowering.
4229 Chain = DAG.getStackArgumentTokenFactor(Chain);
4231 // Adjust the stack pointer for the new arguments...
4232 // These operations are automatically eliminated by the prolog/epilog pass
4233 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4235 SDValue CallSeqStart = Chain;
4237 // Load the return address and frame pointer so it can be move somewhere else
4240 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4243 // Set up a copy of the stack pointer for use loading and storing any
4244 // arguments that may not fit in the registers available for argument
4246 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4248 // Figure out which arguments are going to go in registers, and which in
4249 // memory. Also, if this is a vararg function, floating point operations
4250 // must be stored to our stack, and loaded into integer regs as well, if
4251 // any integer regs are available for argument passing.
4252 unsigned ArgOffset = LinkageSize;
4253 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
4255 static const MCPhysReg GPR[] = {
4256 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4257 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4259 static const MCPhysReg *FPR = GetFPR();
4261 static const MCPhysReg VR[] = {
4262 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4263 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4265 static const MCPhysReg VSRH[] = {
4266 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4267 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4270 const unsigned NumGPRs = array_lengthof(GPR);
4271 const unsigned NumFPRs = 13;
4272 const unsigned NumVRs = array_lengthof(VR);
4274 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4275 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4277 SmallVector<SDValue, 8> MemOpChains;
4278 for (unsigned i = 0; i != NumOps; ++i) {
4279 SDValue Arg = OutVals[i];
4280 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4281 EVT ArgVT = Outs[i].VT;
4282 EVT OrigVT = Outs[i].ArgVT;
4284 /* Respect alignment of argument on the stack. */
4286 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4287 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4289 /* Compute GPR index associated with argument offset. */
4290 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4291 GPR_idx = std::min(GPR_idx, NumGPRs);
4293 // PtrOff will be used to store the current argument to the stack if a
4294 // register cannot be found for it.
4297 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4299 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4301 // Promote integers to 64-bit values.
4302 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4303 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4304 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4305 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4308 // FIXME memcpy is used way more than necessary. Correctness first.
4309 // Note: "by value" is code for passing a structure by value, not
4311 if (Flags.isByVal()) {
4312 // Note: Size includes alignment padding, so
4313 // struct x { short a; char b; }
4314 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4315 // These are the proper values we need for right-justifying the
4316 // aggregate in a parameter register.
4317 unsigned Size = Flags.getByValSize();
4319 // An empty aggregate parameter takes up no storage and no
4324 // All aggregates smaller than 8 bytes must be passed right-justified.
4325 if (Size==1 || Size==2 || Size==4) {
4326 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4327 if (GPR_idx != NumGPRs) {
4328 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4329 MachinePointerInfo(), VT,
4330 false, false, false, 0);
4331 MemOpChains.push_back(Load.getValue(1));
4332 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4334 ArgOffset += PtrByteSize;
4339 if (GPR_idx == NumGPRs && Size < 8) {
4340 SDValue AddPtr = PtrOff;
4341 if (!isLittleEndian) {
4342 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4343 PtrOff.getValueType());
4344 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4346 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4349 ArgOffset += PtrByteSize;
4352 // Copy entire object into memory. There are cases where gcc-generated
4353 // code assumes it is there, even if it could be put entirely into
4354 // registers. (This is not what the doc says.)
4356 // FIXME: The above statement is likely due to a misunderstanding of the
4357 // documents. All arguments must be copied into the parameter area BY
4358 // THE CALLEE in the event that the callee takes the address of any
4359 // formal argument. That has not yet been implemented. However, it is
4360 // reasonable to use the stack area as a staging area for the register
4363 // Skip this for small aggregates, as we will use the same slot for a
4364 // right-justified copy, below.
4366 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4370 // When a register is available, pass a small aggregate right-justified.
4371 if (Size < 8 && GPR_idx != NumGPRs) {
4372 // The easiest way to get this right-justified in a register
4373 // is to copy the structure into the rightmost portion of a
4374 // local variable slot, then load the whole slot into the
4376 // FIXME: The memcpy seems to produce pretty awful code for
4377 // small aggregates, particularly for packed ones.
4378 // FIXME: It would be preferable to use the slot in the
4379 // parameter save area instead of a new local variable.
4380 SDValue AddPtr = PtrOff;
4381 if (!isLittleEndian) {
4382 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4383 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4385 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4389 // Load the slot into the register.
4390 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4391 MachinePointerInfo(),
4392 false, false, false, 0);
4393 MemOpChains.push_back(Load.getValue(1));
4394 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4396 // Done with this argument.
4397 ArgOffset += PtrByteSize;
4401 // For aggregates larger than PtrByteSize, copy the pieces of the
4402 // object that fit into registers from the parameter save area.
4403 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4404 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4405 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4406 if (GPR_idx != NumGPRs) {
4407 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4408 MachinePointerInfo(),
4409 false, false, false, 0);
4410 MemOpChains.push_back(Load.getValue(1));
4411 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4412 ArgOffset += PtrByteSize;
4414 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4421 switch (Arg.getSimpleValueType().SimpleTy) {
4422 default: llvm_unreachable("Unexpected ValueType for argument!");
4426 // These can be scalar arguments or elements of an integer array type
4427 // passed directly. Clang may use those instead of "byval" aggregate
4428 // types to avoid forcing arguments to memory unnecessarily.
4429 if (GPR_idx != NumGPRs) {
4430 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Arg));
4432 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4433 true, isTailCall, false, MemOpChains,
4434 TailCallArguments, dl);
4436 ArgOffset += PtrByteSize;
4440 // These can be scalar arguments or elements of a float array type
4441 // passed directly. The latter are used to implement ELFv2 homogenous
4442 // float aggregates.
4444 // Named arguments go into FPRs first, and once they overflow, the
4445 // remaining arguments go into GPRs and then the parameter save area.
4446 // Unnamed arguments for vararg functions always go to GPRs and
4447 // then the parameter save area. For now, put all arguments to vararg
4448 // routines always in both locations (FPR *and* GPR or stack slot).
4449 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4451 // First load the argument into the next available FPR.
4452 if (FPR_idx != NumFPRs)
4453 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4455 // Next, load the argument into GPR or stack slot if needed.
4456 if (!NeedGPROrStack)
4458 else if (GPR_idx != NumGPRs) {
4459 // In the non-vararg case, this can only ever happen in the
4460 // presence of f32 array types, since otherwise we never run
4461 // out of FPRs before running out of GPRs.
4464 // Double values are always passed in a single GPR.
4465 if (Arg.getValueType() != MVT::f32) {
4466 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4468 // Non-array float values are extended and passed in a GPR.
4469 } else if (!Flags.isInConsecutiveRegs()) {
4470 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4471 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4473 // If we have an array of floats, we collect every odd element
4474 // together with its predecessor into one GPR.
4475 } else if (ArgOffset % PtrByteSize != 0) {
4477 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4478 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4479 if (!isLittleEndian)
4481 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4483 // The final element, if even, goes into the first half of a GPR.
4484 } else if (Flags.isInConsecutiveRegsLast()) {
4485 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4486 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4487 if (!isLittleEndian)
4488 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4489 DAG.getConstant(32, MVT::i32));
4491 // Non-final even elements are skipped; they will be handled
4492 // together the with subsequent argument on the next go-around.
4496 if (ArgVal.getNode())
4497 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], ArgVal));
4499 // Single-precision floating-point values are mapped to the
4500 // second (rightmost) word of the stack doubleword.
4501 if (Arg.getValueType() == MVT::f32 &&
4502 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4503 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4504 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4507 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4508 true, isTailCall, false, MemOpChains,
4509 TailCallArguments, dl);
4511 // When passing an array of floats, the array occupies consecutive
4512 // space in the argument area; only round up to the next doubleword
4513 // at the end of the array. Otherwise, each float takes 8 bytes.
4514 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4515 Flags.isInConsecutiveRegs()) ? 4 : 8;
4516 if (Flags.isInConsecutiveRegsLast())
4517 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4526 // These can be scalar arguments or elements of a vector array type
4527 // passed directly. The latter are used to implement ELFv2 homogenous
4528 // vector aggregates.
4530 // For a varargs call, named arguments go into VRs or on the stack as
4531 // usual; unnamed arguments always go to the stack or the corresponding
4532 // GPRs when within range. For now, we always put the value in both
4533 // locations (or even all three).
4535 // We could elide this store in the case where the object fits
4536 // entirely in R registers. Maybe later.
4537 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4538 MachinePointerInfo(), false, false, 0);
4539 MemOpChains.push_back(Store);
4540 if (VR_idx != NumVRs) {
4541 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4542 MachinePointerInfo(),
4543 false, false, false, 0);
4544 MemOpChains.push_back(Load.getValue(1));
4546 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4547 Arg.getSimpleValueType() == MVT::v2i64) ?
4548 VSRH[VR_idx] : VR[VR_idx];
4551 RegsToPass.push_back(std::make_pair(VReg, Load));
4554 for (unsigned i=0; i<16; i+=PtrByteSize) {
4555 if (GPR_idx == NumGPRs)
4557 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4558 DAG.getConstant(i, PtrVT));
4559 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4560 false, false, false, 0);
4561 MemOpChains.push_back(Load.getValue(1));
4562 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4567 // Non-varargs Altivec params go into VRs or on the stack.
4568 if (VR_idx != NumVRs) {
4569 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4570 Arg.getSimpleValueType() == MVT::v2i64) ?
4571 VSRH[VR_idx] : VR[VR_idx];
4574 RegsToPass.push_back(std::make_pair(VReg, Arg));
4576 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4577 true, isTailCall, true, MemOpChains,
4578 TailCallArguments, dl);
4585 assert(NumBytesActuallyUsed == ArgOffset);
4586 (void)NumBytesActuallyUsed;
4588 if (!MemOpChains.empty())
4589 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4591 // Check if this is an indirect call (MTCTR/BCTRL).
4592 // See PrepareCall() for more information about calls through function
4593 // pointers in the 64-bit SVR4 ABI.
4595 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4596 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4597 // Load r2 into a virtual register and store it to the TOC save area.
4598 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4599 // TOC save area offset.
4600 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4601 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4602 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4603 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4605 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4606 // This does not mean the MTCTR instruction must use R12; it's easier
4607 // to model this as an extra parameter, so do that.
4609 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4612 // Build a sequence of copy-to-reg nodes chained together with token chain
4613 // and flag operands which copy the outgoing args into the appropriate regs.
4615 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4616 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4617 RegsToPass[i].second, InFlag);
4618 InFlag = Chain.getValue(1);
4622 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4623 FPOp, true, TailCallArguments);
4625 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4626 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4631 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4632 CallingConv::ID CallConv, bool isVarArg,
4634 const SmallVectorImpl<ISD::OutputArg> &Outs,
4635 const SmallVectorImpl<SDValue> &OutVals,
4636 const SmallVectorImpl<ISD::InputArg> &Ins,
4637 SDLoc dl, SelectionDAG &DAG,
4638 SmallVectorImpl<SDValue> &InVals) const {
4640 unsigned NumOps = Outs.size();
4642 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4643 bool isPPC64 = PtrVT == MVT::i64;
4644 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4646 MachineFunction &MF = DAG.getMachineFunction();
4648 // Mark this function as potentially containing a function that contains a
4649 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4650 // and restoring the callers stack pointer in this functions epilog. This is
4651 // done because by tail calling the called function might overwrite the value
4652 // in this function's (MF) stack pointer stack slot 0(SP).
4653 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4654 CallConv == CallingConv::Fast)
4655 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4657 // Count how many bytes are to be pushed on the stack, including the linkage
4658 // area, and parameter passing area. We start with 24/48 bytes, which is
4659 // prereserved space for [SP][CR][LR][3 x unused].
4660 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4662 unsigned NumBytes = LinkageSize;
4664 // Add up all the space actually used.
4665 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4666 // they all go in registers, but we must reserve stack space for them for
4667 // possible use by the caller. In varargs or 64-bit calls, parameters are
4668 // assigned stack space in order, with padding so Altivec parameters are
4670 unsigned nAltivecParamsAtEnd = 0;
4671 for (unsigned i = 0; i != NumOps; ++i) {
4672 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4673 EVT ArgVT = Outs[i].VT;
4674 // Varargs Altivec parameters are padded to a 16 byte boundary.
4675 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4676 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4677 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4678 if (!isVarArg && !isPPC64) {
4679 // Non-varargs Altivec parameters go after all the non-Altivec
4680 // parameters; handle those later so we know how much padding we need.
4681 nAltivecParamsAtEnd++;
4684 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4685 NumBytes = ((NumBytes+15)/16)*16;
4687 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4690 // Allow for Altivec parameters at the end, if needed.
4691 if (nAltivecParamsAtEnd) {
4692 NumBytes = ((NumBytes+15)/16)*16;
4693 NumBytes += 16*nAltivecParamsAtEnd;
4696 // The prolog code of the callee may store up to 8 GPR argument registers to
4697 // the stack, allowing va_start to index over them in memory if its varargs.
4698 // Because we cannot tell if this is needed on the caller side, we have to
4699 // conservatively assume that it is needed. As such, make sure we have at
4700 // least enough stack space for the caller to store the 8 GPRs.
4701 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4703 // Tail call needs the stack to be aligned.
4704 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4705 CallConv == CallingConv::Fast)
4706 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4708 // Calculate by how many bytes the stack has to be adjusted in case of tail
4709 // call optimization.
4710 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4712 // To protect arguments on the stack from being clobbered in a tail call,
4713 // force all the loads to happen before doing any other lowering.
4715 Chain = DAG.getStackArgumentTokenFactor(Chain);
4717 // Adjust the stack pointer for the new arguments...
4718 // These operations are automatically eliminated by the prolog/epilog pass
4719 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4721 SDValue CallSeqStart = Chain;
4723 // Load the return address and frame pointer so it can be move somewhere else
4726 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4729 // Set up a copy of the stack pointer for use loading and storing any
4730 // arguments that may not fit in the registers available for argument
4734 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4736 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4738 // Figure out which arguments are going to go in registers, and which in
4739 // memory. Also, if this is a vararg function, floating point operations
4740 // must be stored to our stack, and loaded into integer regs as well, if
4741 // any integer regs are available for argument passing.
4742 unsigned ArgOffset = LinkageSize;
4743 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4745 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4746 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4747 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4749 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4750 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4751 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4753 static const MCPhysReg *FPR = GetFPR();
4755 static const MCPhysReg VR[] = {
4756 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4757 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4759 const unsigned NumGPRs = array_lengthof(GPR_32);
4760 const unsigned NumFPRs = 13;
4761 const unsigned NumVRs = array_lengthof(VR);
4763 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4765 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4766 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4768 SmallVector<SDValue, 8> MemOpChains;
4769 for (unsigned i = 0; i != NumOps; ++i) {
4770 SDValue Arg = OutVals[i];
4771 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4773 // PtrOff will be used to store the current argument to the stack if a
4774 // register cannot be found for it.
4777 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4779 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4781 // On PPC64, promote integers to 64-bit values.
4782 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4783 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4784 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4785 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4788 // FIXME memcpy is used way more than necessary. Correctness first.
4789 // Note: "by value" is code for passing a structure by value, not
4791 if (Flags.isByVal()) {
4792 unsigned Size = Flags.getByValSize();
4793 // Very small objects are passed right-justified. Everything else is
4794 // passed left-justified.
4795 if (Size==1 || Size==2) {
4796 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4797 if (GPR_idx != NumGPRs) {
4798 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4799 MachinePointerInfo(), VT,
4800 false, false, false, 0);
4801 MemOpChains.push_back(Load.getValue(1));
4802 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4804 ArgOffset += PtrByteSize;
4806 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4807 PtrOff.getValueType());
4808 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4809 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4812 ArgOffset += PtrByteSize;
4816 // Copy entire object into memory. There are cases where gcc-generated
4817 // code assumes it is there, even if it could be put entirely into
4818 // registers. (This is not what the doc says.)
4819 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4823 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4824 // copy the pieces of the object that fit into registers from the
4825 // parameter save area.
4826 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4827 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4828 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4829 if (GPR_idx != NumGPRs) {
4830 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4831 MachinePointerInfo(),
4832 false, false, false, 0);
4833 MemOpChains.push_back(Load.getValue(1));
4834 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4835 ArgOffset += PtrByteSize;
4837 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4844 switch (Arg.getSimpleValueType().SimpleTy) {
4845 default: llvm_unreachable("Unexpected ValueType for argument!");
4849 if (GPR_idx != NumGPRs) {
4850 if (Arg.getValueType() == MVT::i1)
4851 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4853 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4855 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4856 isPPC64, isTailCall, false, MemOpChains,
4857 TailCallArguments, dl);
4859 ArgOffset += PtrByteSize;
4863 if (FPR_idx != NumFPRs) {
4864 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4867 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4868 MachinePointerInfo(), false, false, 0);
4869 MemOpChains.push_back(Store);
4871 // Float varargs are always shadowed in available integer registers
4872 if (GPR_idx != NumGPRs) {
4873 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4874 MachinePointerInfo(), false, false,
4876 MemOpChains.push_back(Load.getValue(1));
4877 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4879 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4880 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4881 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4882 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4883 MachinePointerInfo(),
4884 false, false, false, 0);
4885 MemOpChains.push_back(Load.getValue(1));
4886 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4889 // If we have any FPRs remaining, we may also have GPRs remaining.
4890 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4892 if (GPR_idx != NumGPRs)
4894 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4895 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4899 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4900 isPPC64, isTailCall, false, MemOpChains,
4901 TailCallArguments, dl);
4905 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4912 // These go aligned on the stack, or in the corresponding R registers
4913 // when within range. The Darwin PPC ABI doc claims they also go in
4914 // V registers; in fact gcc does this only for arguments that are
4915 // prototyped, not for those that match the ... We do it for all
4916 // arguments, seems to work.
4917 while (ArgOffset % 16 !=0) {
4918 ArgOffset += PtrByteSize;
4919 if (GPR_idx != NumGPRs)
4922 // We could elide this store in the case where the object fits
4923 // entirely in R registers. Maybe later.
4924 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4925 DAG.getConstant(ArgOffset, PtrVT));
4926 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4927 MachinePointerInfo(), false, false, 0);
4928 MemOpChains.push_back(Store);
4929 if (VR_idx != NumVRs) {
4930 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4931 MachinePointerInfo(),
4932 false, false, false, 0);
4933 MemOpChains.push_back(Load.getValue(1));
4934 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4937 for (unsigned i=0; i<16; i+=PtrByteSize) {
4938 if (GPR_idx == NumGPRs)
4940 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4941 DAG.getConstant(i, PtrVT));
4942 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4943 false, false, false, 0);
4944 MemOpChains.push_back(Load.getValue(1));
4945 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4950 // Non-varargs Altivec params generally go in registers, but have
4951 // stack space allocated at the end.
4952 if (VR_idx != NumVRs) {
4953 // Doesn't have GPR space allocated.
4954 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4955 } else if (nAltivecParamsAtEnd==0) {
4956 // We are emitting Altivec params in order.
4957 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4958 isPPC64, isTailCall, true, MemOpChains,
4959 TailCallArguments, dl);
4965 // If all Altivec parameters fit in registers, as they usually do,
4966 // they get stack space following the non-Altivec parameters. We
4967 // don't track this here because nobody below needs it.
4968 // If there are more Altivec parameters than fit in registers emit
4970 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4972 // Offset is aligned; skip 1st 12 params which go in V registers.
4973 ArgOffset = ((ArgOffset+15)/16)*16;
4975 for (unsigned i = 0; i != NumOps; ++i) {
4976 SDValue Arg = OutVals[i];
4977 EVT ArgType = Outs[i].VT;
4978 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4979 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4982 // We are emitting Altivec params in order.
4983 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4984 isPPC64, isTailCall, true, MemOpChains,
4985 TailCallArguments, dl);
4992 if (!MemOpChains.empty())
4993 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4995 // On Darwin, R12 must contain the address of an indirect callee. This does
4996 // not mean the MTCTR instruction must use R12; it's easier to model this as
4997 // an extra parameter, so do that.
4999 !dyn_cast<GlobalAddressSDNode>(Callee) &&
5000 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
5001 !isBLACompatibleAddress(Callee, DAG))
5002 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5003 PPC::R12), Callee));
5005 // Build a sequence of copy-to-reg nodes chained together with token chain
5006 // and flag operands which copy the outgoing args into the appropriate regs.
5008 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5009 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5010 RegsToPass[i].second, InFlag);
5011 InFlag = Chain.getValue(1);
5015 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5016 FPOp, true, TailCallArguments);
5018 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
5019 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
5024 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5025 MachineFunction &MF, bool isVarArg,
5026 const SmallVectorImpl<ISD::OutputArg> &Outs,
5027 LLVMContext &Context) const {
5028 SmallVector<CCValAssign, 16> RVLocs;
5029 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5030 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5034 PPCTargetLowering::LowerReturn(SDValue Chain,
5035 CallingConv::ID CallConv, bool isVarArg,
5036 const SmallVectorImpl<ISD::OutputArg> &Outs,
5037 const SmallVectorImpl<SDValue> &OutVals,
5038 SDLoc dl, SelectionDAG &DAG) const {
5040 SmallVector<CCValAssign, 16> RVLocs;
5041 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5043 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5046 SmallVector<SDValue, 4> RetOps(1, Chain);
5048 // Copy the result values into the output registers.
5049 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5050 CCValAssign &VA = RVLocs[i];
5051 assert(VA.isRegLoc() && "Can only return in registers!");
5053 SDValue Arg = OutVals[i];
5055 switch (VA.getLocInfo()) {
5056 default: llvm_unreachable("Unknown loc info!");
5057 case CCValAssign::Full: break;
5058 case CCValAssign::AExt:
5059 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5061 case CCValAssign::ZExt:
5062 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5064 case CCValAssign::SExt:
5065 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5069 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5070 Flag = Chain.getValue(1);
5071 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5074 RetOps[0] = Chain; // Update chain.
5076 // Add the flag if we have it.
5078 RetOps.push_back(Flag);
5080 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5083 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5084 const PPCSubtarget &Subtarget) const {
5085 // When we pop the dynamic allocation we need to restore the SP link.
5088 // Get the corect type for pointers.
5089 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5091 // Construct the stack pointer operand.
5092 bool isPPC64 = Subtarget.isPPC64();
5093 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5094 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5096 // Get the operands for the STACKRESTORE.
5097 SDValue Chain = Op.getOperand(0);
5098 SDValue SaveSP = Op.getOperand(1);
5100 // Load the old link SP.
5101 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5102 MachinePointerInfo(),
5103 false, false, false, 0);
5105 // Restore the stack pointer.
5106 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5108 // Store the old link SP.
5109 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5116 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5117 MachineFunction &MF = DAG.getMachineFunction();
5118 bool isPPC64 = Subtarget.isPPC64();
5119 bool isDarwinABI = Subtarget.isDarwinABI();
5120 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5122 // Get current frame pointer save index. The users of this index will be
5123 // primarily DYNALLOC instructions.
5124 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5125 int RASI = FI->getReturnAddrSaveIndex();
5127 // If the frame pointer save index hasn't been defined yet.
5129 // Find out what the fix offset of the frame pointer save area.
5130 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5131 // Allocate the frame index for frame pointer save area.
5132 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
5134 FI->setReturnAddrSaveIndex(RASI);
5136 return DAG.getFrameIndex(RASI, PtrVT);
5140 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5141 MachineFunction &MF = DAG.getMachineFunction();
5142 bool isPPC64 = Subtarget.isPPC64();
5143 bool isDarwinABI = Subtarget.isDarwinABI();
5144 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5146 // Get current frame pointer save index. The users of this index will be
5147 // primarily DYNALLOC instructions.
5148 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5149 int FPSI = FI->getFramePointerSaveIndex();
5151 // If the frame pointer save index hasn't been defined yet.
5153 // Find out what the fix offset of the frame pointer save area.
5154 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5157 // Allocate the frame index for frame pointer save area.
5158 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5160 FI->setFramePointerSaveIndex(FPSI);
5162 return DAG.getFrameIndex(FPSI, PtrVT);
5165 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5167 const PPCSubtarget &Subtarget) const {
5169 SDValue Chain = Op.getOperand(0);
5170 SDValue Size = Op.getOperand(1);
5173 // Get the corect type for pointers.
5174 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5176 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5177 DAG.getConstant(0, PtrVT), Size);
5178 // Construct a node for the frame pointer save index.
5179 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5180 // Build a DYNALLOC node.
5181 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5182 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5183 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5186 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5187 SelectionDAG &DAG) const {
5189 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5190 DAG.getVTList(MVT::i32, MVT::Other),
5191 Op.getOperand(0), Op.getOperand(1));
5194 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5195 SelectionDAG &DAG) const {
5197 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5198 Op.getOperand(0), Op.getOperand(1));
5201 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5202 assert(Op.getValueType() == MVT::i1 &&
5203 "Custom lowering only for i1 loads");
5205 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5208 LoadSDNode *LD = cast<LoadSDNode>(Op);
5210 SDValue Chain = LD->getChain();
5211 SDValue BasePtr = LD->getBasePtr();
5212 MachineMemOperand *MMO = LD->getMemOperand();
5214 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5215 BasePtr, MVT::i8, MMO);
5216 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5218 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5219 return DAG.getMergeValues(Ops, dl);
5222 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5223 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5224 "Custom lowering only for i1 stores");
5226 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5229 StoreSDNode *ST = cast<StoreSDNode>(Op);
5231 SDValue Chain = ST->getChain();
5232 SDValue BasePtr = ST->getBasePtr();
5233 SDValue Value = ST->getValue();
5234 MachineMemOperand *MMO = ST->getMemOperand();
5236 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5237 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5240 // FIXME: Remove this once the ANDI glue bug is fixed:
5241 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5242 assert(Op.getValueType() == MVT::i1 &&
5243 "Custom lowering only for i1 results");
5246 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5250 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5252 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5253 // Not FP? Not a fsel.
5254 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5255 !Op.getOperand(2).getValueType().isFloatingPoint())
5258 // We might be able to do better than this under some circumstances, but in
5259 // general, fsel-based lowering of select is a finite-math-only optimization.
5260 // For more information, see section F.3 of the 2.06 ISA specification.
5261 if (!DAG.getTarget().Options.NoInfsFPMath ||
5262 !DAG.getTarget().Options.NoNaNsFPMath)
5265 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5267 EVT ResVT = Op.getValueType();
5268 EVT CmpVT = Op.getOperand(0).getValueType();
5269 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5270 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5273 // If the RHS of the comparison is a 0.0, we don't need to do the
5274 // subtraction at all.
5276 if (isFloatingPointZero(RHS))
5278 default: break; // SETUO etc aren't handled by fsel.
5282 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5283 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5284 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5285 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5286 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5287 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5288 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5291 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5294 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5295 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5296 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5299 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5302 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5303 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5304 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5305 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5310 default: break; // SETUO etc aren't handled by fsel.
5314 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5315 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5316 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5317 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5318 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5319 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5320 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5321 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5324 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5325 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5326 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5327 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5330 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5331 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5332 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5333 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5336 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5337 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5338 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5339 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5342 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5343 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5344 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5345 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5350 // FIXME: Split this code up when LegalizeDAGTypes lands.
5351 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5353 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5354 SDValue Src = Op.getOperand(0);
5355 if (Src.getValueType() == MVT::f32)
5356 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5359 switch (Op.getSimpleValueType().SimpleTy) {
5360 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5362 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5363 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5368 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5369 "i64 FP_TO_UINT is supported only with FPCVT");
5370 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5376 // Convert the FP value to an int value through memory.
5377 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5378 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5379 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5380 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5381 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5383 // Emit a store to the stack slot.
5386 MachineFunction &MF = DAG.getMachineFunction();
5387 MachineMemOperand *MMO =
5388 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5389 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5390 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5391 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5393 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5394 MPI, false, false, 0);
5396 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5398 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5399 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5400 DAG.getConstant(4, FIPtr.getValueType()));
5401 MPI = MachinePointerInfo();
5404 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5405 false, false, false, 0);
5408 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5409 SelectionDAG &DAG) const {
5411 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5412 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5415 if (Op.getOperand(0).getValueType() == MVT::i1)
5416 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5417 DAG.getConstantFP(1.0, Op.getValueType()),
5418 DAG.getConstantFP(0.0, Op.getValueType()));
5420 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5421 "UINT_TO_FP is supported only with FPCVT");
5423 // If we have FCFIDS, then use it when converting to single-precision.
5424 // Otherwise, convert to double-precision and then round.
5425 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5426 (Op.getOpcode() == ISD::UINT_TO_FP ?
5427 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5428 (Op.getOpcode() == ISD::UINT_TO_FP ?
5429 PPCISD::FCFIDU : PPCISD::FCFID);
5430 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5431 MVT::f32 : MVT::f64;
5433 if (Op.getOperand(0).getValueType() == MVT::i64) {
5434 SDValue SINT = Op.getOperand(0);
5435 // When converting to single-precision, we actually need to convert
5436 // to double-precision first and then round to single-precision.
5437 // To avoid double-rounding effects during that operation, we have
5438 // to prepare the input operand. Bits that might be truncated when
5439 // converting to double-precision are replaced by a bit that won't
5440 // be lost at this stage, but is below the single-precision rounding
5443 // However, if -enable-unsafe-fp-math is in effect, accept double
5444 // rounding to avoid the extra overhead.
5445 if (Op.getValueType() == MVT::f32 &&
5446 !Subtarget.hasFPCVT() &&
5447 !DAG.getTarget().Options.UnsafeFPMath) {
5449 // Twiddle input to make sure the low 11 bits are zero. (If this
5450 // is the case, we are guaranteed the value will fit into the 53 bit
5451 // mantissa of an IEEE double-precision value without rounding.)
5452 // If any of those low 11 bits were not zero originally, make sure
5453 // bit 12 (value 2048) is set instead, so that the final rounding
5454 // to single-precision gets the correct result.
5455 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5456 SINT, DAG.getConstant(2047, MVT::i64));
5457 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5458 Round, DAG.getConstant(2047, MVT::i64));
5459 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5460 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5461 Round, DAG.getConstant(-2048, MVT::i64));
5463 // However, we cannot use that value unconditionally: if the magnitude
5464 // of the input value is small, the bit-twiddling we did above might
5465 // end up visibly changing the output. Fortunately, in that case, we
5466 // don't need to twiddle bits since the original input will convert
5467 // exactly to double-precision floating-point already. Therefore,
5468 // construct a conditional to use the original value if the top 11
5469 // bits are all sign-bit copies, and use the rounded value computed
5471 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5472 SINT, DAG.getConstant(53, MVT::i32));
5473 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5474 Cond, DAG.getConstant(1, MVT::i64));
5475 Cond = DAG.getSetCC(dl, MVT::i32,
5476 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5478 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5481 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5482 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5484 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5485 FP = DAG.getNode(ISD::FP_ROUND, dl,
5486 MVT::f32, FP, DAG.getIntPtrConstant(0));
5490 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5491 "Unhandled INT_TO_FP type in custom expander!");
5492 // Since we only generate this in 64-bit mode, we can take advantage of
5493 // 64-bit registers. In particular, sign extend the input value into the
5494 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5495 // then lfd it and fcfid it.
5496 MachineFunction &MF = DAG.getMachineFunction();
5497 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5498 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5501 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5502 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5503 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5505 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5506 MachinePointerInfo::getFixedStack(FrameIdx),
5509 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5510 "Expected an i32 store");
5511 MachineMemOperand *MMO =
5512 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5513 MachineMemOperand::MOLoad, 4, 4);
5514 SDValue Ops[] = { Store, FIdx };
5515 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5516 PPCISD::LFIWZX : PPCISD::LFIWAX,
5517 dl, DAG.getVTList(MVT::f64, MVT::Other),
5518 Ops, MVT::i32, MMO);
5520 assert(Subtarget.isPPC64() &&
5521 "i32->FP without LFIWAX supported only on PPC64");
5523 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5524 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5526 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5529 // STD the extended value into the stack slot.
5530 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5531 MachinePointerInfo::getFixedStack(FrameIdx),
5534 // Load the value as a double.
5535 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5536 MachinePointerInfo::getFixedStack(FrameIdx),
5537 false, false, false, 0);
5540 // FCFID it and return it.
5541 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5542 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5543 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5547 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5548 SelectionDAG &DAG) const {
5551 The rounding mode is in bits 30:31 of FPSR, and has the following
5558 FLT_ROUNDS, on the other hand, expects the following:
5565 To perform the conversion, we do:
5566 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5569 MachineFunction &MF = DAG.getMachineFunction();
5570 EVT VT = Op.getValueType();
5571 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5573 // Save FP Control Word to register
5575 MVT::f64, // return register
5576 MVT::Glue // unused in this context
5578 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5580 // Save FP register to stack slot
5581 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5582 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5583 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5584 StackSlot, MachinePointerInfo(), false, false,0);
5586 // Load FP Control Word from low 32 bits of stack slot.
5587 SDValue Four = DAG.getConstant(4, PtrVT);
5588 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5589 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5590 false, false, false, 0);
5592 // Transform as necessary
5594 DAG.getNode(ISD::AND, dl, MVT::i32,
5595 CWD, DAG.getConstant(3, MVT::i32));
5597 DAG.getNode(ISD::SRL, dl, MVT::i32,
5598 DAG.getNode(ISD::AND, dl, MVT::i32,
5599 DAG.getNode(ISD::XOR, dl, MVT::i32,
5600 CWD, DAG.getConstant(3, MVT::i32)),
5601 DAG.getConstant(3, MVT::i32)),
5602 DAG.getConstant(1, MVT::i32));
5605 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5607 return DAG.getNode((VT.getSizeInBits() < 16 ?
5608 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5611 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5612 EVT VT = Op.getValueType();
5613 unsigned BitWidth = VT.getSizeInBits();
5615 assert(Op.getNumOperands() == 3 &&
5616 VT == Op.getOperand(1).getValueType() &&
5619 // Expand into a bunch of logical ops. Note that these ops
5620 // depend on the PPC behavior for oversized shift amounts.
5621 SDValue Lo = Op.getOperand(0);
5622 SDValue Hi = Op.getOperand(1);
5623 SDValue Amt = Op.getOperand(2);
5624 EVT AmtVT = Amt.getValueType();
5626 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5627 DAG.getConstant(BitWidth, AmtVT), Amt);
5628 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5629 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5630 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5631 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5632 DAG.getConstant(-BitWidth, AmtVT));
5633 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5634 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5635 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5636 SDValue OutOps[] = { OutLo, OutHi };
5637 return DAG.getMergeValues(OutOps, dl);
5640 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5641 EVT VT = Op.getValueType();
5643 unsigned BitWidth = VT.getSizeInBits();
5644 assert(Op.getNumOperands() == 3 &&
5645 VT == Op.getOperand(1).getValueType() &&
5648 // Expand into a bunch of logical ops. Note that these ops
5649 // depend on the PPC behavior for oversized shift amounts.
5650 SDValue Lo = Op.getOperand(0);
5651 SDValue Hi = Op.getOperand(1);
5652 SDValue Amt = Op.getOperand(2);
5653 EVT AmtVT = Amt.getValueType();
5655 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5656 DAG.getConstant(BitWidth, AmtVT), Amt);
5657 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5658 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5659 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5660 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5661 DAG.getConstant(-BitWidth, AmtVT));
5662 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5663 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5664 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5665 SDValue OutOps[] = { OutLo, OutHi };
5666 return DAG.getMergeValues(OutOps, dl);
5669 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5671 EVT VT = Op.getValueType();
5672 unsigned BitWidth = VT.getSizeInBits();
5673 assert(Op.getNumOperands() == 3 &&
5674 VT == Op.getOperand(1).getValueType() &&
5677 // Expand into a bunch of logical ops, followed by a select_cc.
5678 SDValue Lo = Op.getOperand(0);
5679 SDValue Hi = Op.getOperand(1);
5680 SDValue Amt = Op.getOperand(2);
5681 EVT AmtVT = Amt.getValueType();
5683 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5684 DAG.getConstant(BitWidth, AmtVT), Amt);
5685 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5686 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5687 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5688 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5689 DAG.getConstant(-BitWidth, AmtVT));
5690 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5691 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5692 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5693 Tmp4, Tmp6, ISD::SETLE);
5694 SDValue OutOps[] = { OutLo, OutHi };
5695 return DAG.getMergeValues(OutOps, dl);
5698 //===----------------------------------------------------------------------===//
5699 // Vector related lowering.
5702 /// BuildSplatI - Build a canonical splati of Val with an element size of
5703 /// SplatSize. Cast the result to VT.
5704 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5705 SelectionDAG &DAG, SDLoc dl) {
5706 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5708 static const EVT VTys[] = { // canonical VT to use for each size.
5709 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5712 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5714 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5718 EVT CanonicalVT = VTys[SplatSize-1];
5720 // Build a canonical splat for this value.
5721 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5722 SmallVector<SDValue, 8> Ops;
5723 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5724 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5725 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5728 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5729 /// specified intrinsic ID.
5730 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5731 SelectionDAG &DAG, SDLoc dl,
5732 EVT DestVT = MVT::Other) {
5733 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5734 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5735 DAG.getConstant(IID, MVT::i32), Op);
5738 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5739 /// specified intrinsic ID.
5740 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5741 SelectionDAG &DAG, SDLoc dl,
5742 EVT DestVT = MVT::Other) {
5743 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5744 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5745 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5748 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5749 /// specified intrinsic ID.
5750 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5751 SDValue Op2, SelectionDAG &DAG,
5752 SDLoc dl, EVT DestVT = MVT::Other) {
5753 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5754 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5755 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5759 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5760 /// amount. The result has the specified value type.
5761 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5762 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5763 // Force LHS/RHS to be the right type.
5764 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5765 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5768 for (unsigned i = 0; i != 16; ++i)
5770 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5771 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5774 // If this is a case we can't handle, return null and let the default
5775 // expansion code take care of it. If we CAN select this case, and if it
5776 // selects to a single instruction, return Op. Otherwise, if we can codegen
5777 // this case more efficiently than a constant pool load, lower it to the
5778 // sequence of ops that should be used.
5779 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5780 SelectionDAG &DAG) const {
5782 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5783 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5785 // Check if this is a splat of a constant value.
5786 APInt APSplatBits, APSplatUndef;
5787 unsigned SplatBitSize;
5789 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5790 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5793 unsigned SplatBits = APSplatBits.getZExtValue();
5794 unsigned SplatUndef = APSplatUndef.getZExtValue();
5795 unsigned SplatSize = SplatBitSize / 8;
5797 // First, handle single instruction cases.
5800 if (SplatBits == 0) {
5801 // Canonicalize all zero vectors to be v4i32.
5802 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5803 SDValue Z = DAG.getConstant(0, MVT::i32);
5804 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5805 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5810 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5811 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5813 if (SextVal >= -16 && SextVal <= 15)
5814 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5817 // Two instruction sequences.
5819 // If this value is in the range [-32,30] and is even, use:
5820 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5821 // If this value is in the range [17,31] and is odd, use:
5822 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5823 // If this value is in the range [-31,-17] and is odd, use:
5824 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5825 // Note the last two are three-instruction sequences.
5826 if (SextVal >= -32 && SextVal <= 31) {
5827 // To avoid having these optimizations undone by constant folding,
5828 // we convert to a pseudo that will be expanded later into one of
5830 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5831 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5832 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5833 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5834 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5835 if (VT == Op.getValueType())
5838 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5841 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5842 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5844 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5845 // Make -1 and vspltisw -1:
5846 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5848 // Make the VSLW intrinsic, computing 0x8000_0000.
5849 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5852 // xor by OnesV to invert it.
5853 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5854 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5857 // The remaining cases assume either big endian element order or
5858 // a splat-size that equates to the element size of the vector
5859 // to be built. An example that doesn't work for little endian is
5860 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5861 // and a vector element size of 16 bits. The code below will
5862 // produce the vector in big endian element order, which for little
5863 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5865 // For now, just avoid these optimizations in that case.
5866 // FIXME: Develop correct optimizations for LE with mismatched
5867 // splat and element sizes.
5869 if (Subtarget.isLittleEndian() &&
5870 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5873 // Check to see if this is a wide variety of vsplti*, binop self cases.
5874 static const signed char SplatCsts[] = {
5875 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5876 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5879 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5880 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5881 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5882 int i = SplatCsts[idx];
5884 // Figure out what shift amount will be used by altivec if shifted by i in
5886 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5888 // vsplti + shl self.
5889 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5890 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5891 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5892 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5893 Intrinsic::ppc_altivec_vslw
5895 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5896 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5899 // vsplti + srl self.
5900 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5901 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5902 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5903 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5904 Intrinsic::ppc_altivec_vsrw
5906 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5907 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5910 // vsplti + sra self.
5911 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5912 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5913 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5914 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5915 Intrinsic::ppc_altivec_vsraw
5917 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5918 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5921 // vsplti + rol self.
5922 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5923 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5924 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5925 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5926 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5927 Intrinsic::ppc_altivec_vrlw
5929 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5930 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5933 // t = vsplti c, result = vsldoi t, t, 1
5934 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5935 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5936 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5938 // t = vsplti c, result = vsldoi t, t, 2
5939 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5940 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5941 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5943 // t = vsplti c, result = vsldoi t, t, 3
5944 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5945 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5946 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5953 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5954 /// the specified operations to build the shuffle.
5955 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5956 SDValue RHS, SelectionDAG &DAG,
5958 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5959 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5960 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5963 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5975 if (OpNum == OP_COPY) {
5976 if (LHSID == (1*9+2)*9+3) return LHS;
5977 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5981 SDValue OpLHS, OpRHS;
5982 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5983 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5987 default: llvm_unreachable("Unknown i32 permute!");
5989 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5990 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5991 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5992 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5995 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5996 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5997 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5998 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6001 for (unsigned i = 0; i != 16; ++i)
6002 ShufIdxs[i] = (i&3)+0;
6005 for (unsigned i = 0; i != 16; ++i)
6006 ShufIdxs[i] = (i&3)+4;
6009 for (unsigned i = 0; i != 16; ++i)
6010 ShufIdxs[i] = (i&3)+8;
6013 for (unsigned i = 0; i != 16; ++i)
6014 ShufIdxs[i] = (i&3)+12;
6017 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6019 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6021 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6023 EVT VT = OpLHS.getValueType();
6024 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6025 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6026 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6027 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6030 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6031 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6032 /// return the code it can be lowered into. Worst case, it can always be
6033 /// lowered into a vperm.
6034 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6035 SelectionDAG &DAG) const {
6037 SDValue V1 = Op.getOperand(0);
6038 SDValue V2 = Op.getOperand(1);
6039 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6040 EVT VT = Op.getValueType();
6041 bool isLittleEndian = Subtarget.isLittleEndian();
6043 // Cases that are handled by instructions that take permute immediates
6044 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6045 // selected by the instruction selector.
6046 if (V2.getOpcode() == ISD::UNDEF) {
6047 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6048 PPC::isSplatShuffleMask(SVOp, 2) ||
6049 PPC::isSplatShuffleMask(SVOp, 4) ||
6050 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6051 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6052 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
6053 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6054 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6055 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6056 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6057 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6058 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6063 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6064 // and produce a fixed permutation. If any of these match, do not lower to
6066 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6067 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6068 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6069 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
6070 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6071 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6072 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6073 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6074 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6075 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6078 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6079 // perfect shuffle table to emit an optimal matching sequence.
6080 ArrayRef<int> PermMask = SVOp->getMask();
6082 unsigned PFIndexes[4];
6083 bool isFourElementShuffle = true;
6084 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6085 unsigned EltNo = 8; // Start out undef.
6086 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6087 if (PermMask[i*4+j] < 0)
6088 continue; // Undef, ignore it.
6090 unsigned ByteSource = PermMask[i*4+j];
6091 if ((ByteSource & 3) != j) {
6092 isFourElementShuffle = false;
6097 EltNo = ByteSource/4;
6098 } else if (EltNo != ByteSource/4) {
6099 isFourElementShuffle = false;
6103 PFIndexes[i] = EltNo;
6106 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6107 // perfect shuffle vector to determine if it is cost effective to do this as
6108 // discrete instructions, or whether we should use a vperm.
6109 // For now, we skip this for little endian until such time as we have a
6110 // little-endian perfect shuffle table.
6111 if (isFourElementShuffle && !isLittleEndian) {
6112 // Compute the index in the perfect shuffle table.
6113 unsigned PFTableIndex =
6114 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6116 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6117 unsigned Cost = (PFEntry >> 30);
6119 // Determining when to avoid vperm is tricky. Many things affect the cost
6120 // of vperm, particularly how many times the perm mask needs to be computed.
6121 // For example, if the perm mask can be hoisted out of a loop or is already
6122 // used (perhaps because there are multiple permutes with the same shuffle
6123 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6124 // the loop requires an extra register.
6126 // As a compromise, we only emit discrete instructions if the shuffle can be
6127 // generated in 3 or fewer operations. When we have loop information
6128 // available, if this block is within a loop, we should avoid using vperm
6129 // for 3-operation perms and use a constant pool load instead.
6131 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6134 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6135 // vector that will get spilled to the constant pool.
6136 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6138 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6139 // that it is in input element units, not in bytes. Convert now.
6141 // For little endian, the order of the input vectors is reversed, and
6142 // the permutation mask is complemented with respect to 31. This is
6143 // necessary to produce proper semantics with the big-endian-biased vperm
6145 EVT EltVT = V1.getValueType().getVectorElementType();
6146 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6148 SmallVector<SDValue, 16> ResultMask;
6149 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6150 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6152 for (unsigned j = 0; j != BytesPerElement; ++j)
6154 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6157 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6161 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6164 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6167 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6171 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6172 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6173 /// information about the intrinsic.
6174 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6176 unsigned IntrinsicID =
6177 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6180 switch (IntrinsicID) {
6181 default: return false;
6182 // Comparison predicates.
6183 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6184 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6185 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6186 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6187 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6188 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6189 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6190 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6191 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6192 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6193 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6194 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6195 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6197 // Normal Comparisons.
6198 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6199 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6200 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6201 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6202 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6203 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6204 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6205 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6206 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6207 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6208 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6209 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6210 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6215 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6216 /// lower, do it, otherwise return null.
6217 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6218 SelectionDAG &DAG) const {
6219 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6220 // opcode number of the comparison.
6224 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6225 return SDValue(); // Don't custom lower most intrinsics.
6227 // If this is a non-dot comparison, make the VCMP node and we are done.
6229 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6230 Op.getOperand(1), Op.getOperand(2),
6231 DAG.getConstant(CompareOpc, MVT::i32));
6232 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6235 // Create the PPCISD altivec 'dot' comparison node.
6237 Op.getOperand(2), // LHS
6238 Op.getOperand(3), // RHS
6239 DAG.getConstant(CompareOpc, MVT::i32)
6241 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6242 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6244 // Now that we have the comparison, emit a copy from the CR to a GPR.
6245 // This is flagged to the above dot comparison.
6246 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6247 DAG.getRegister(PPC::CR6, MVT::i32),
6248 CompNode.getValue(1));
6250 // Unpack the result based on how the target uses it.
6251 unsigned BitNo; // Bit # of CR6.
6252 bool InvertBit; // Invert result?
6253 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6254 default: // Can't happen, don't crash on invalid number though.
6255 case 0: // Return the value of the EQ bit of CR6.
6256 BitNo = 0; InvertBit = false;
6258 case 1: // Return the inverted value of the EQ bit of CR6.
6259 BitNo = 0; InvertBit = true;
6261 case 2: // Return the value of the LT bit of CR6.
6262 BitNo = 2; InvertBit = false;
6264 case 3: // Return the inverted value of the LT bit of CR6.
6265 BitNo = 2; InvertBit = true;
6269 // Shift the bit into the low position.
6270 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6271 DAG.getConstant(8-(3-BitNo), MVT::i32));
6273 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6274 DAG.getConstant(1, MVT::i32));
6276 // If we are supposed to, toggle the bit.
6278 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6279 DAG.getConstant(1, MVT::i32));
6283 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6284 SelectionDAG &DAG) const {
6286 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6287 // instructions), but for smaller types, we need to first extend up to v2i32
6288 // before doing going farther.
6289 if (Op.getValueType() == MVT::v2i64) {
6290 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6291 if (ExtVT != MVT::v2i32) {
6292 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6293 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6294 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6295 ExtVT.getVectorElementType(), 4)));
6296 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6297 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6298 DAG.getValueType(MVT::v2i32));
6307 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6308 SelectionDAG &DAG) const {
6310 // Create a stack slot that is 16-byte aligned.
6311 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6312 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6313 EVT PtrVT = getPointerTy();
6314 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6316 // Store the input value into Value#0 of the stack slot.
6317 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6318 Op.getOperand(0), FIdx, MachinePointerInfo(),
6321 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6322 false, false, false, 0);
6325 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6327 if (Op.getValueType() == MVT::v4i32) {
6328 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6330 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6331 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6333 SDValue RHSSwap = // = vrlw RHS, 16
6334 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6336 // Shrinkify inputs to v8i16.
6337 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6338 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6339 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6341 // Low parts multiplied together, generating 32-bit results (we ignore the
6343 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6344 LHS, RHS, DAG, dl, MVT::v4i32);
6346 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6347 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6348 // Shift the high parts up 16 bits.
6349 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6351 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6352 } else if (Op.getValueType() == MVT::v8i16) {
6353 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6355 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6357 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6358 LHS, RHS, Zero, DAG, dl);
6359 } else if (Op.getValueType() == MVT::v16i8) {
6360 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6361 bool isLittleEndian = Subtarget.isLittleEndian();
6363 // Multiply the even 8-bit parts, producing 16-bit sums.
6364 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6365 LHS, RHS, DAG, dl, MVT::v8i16);
6366 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6368 // Multiply the odd 8-bit parts, producing 16-bit sums.
6369 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6370 LHS, RHS, DAG, dl, MVT::v8i16);
6371 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6373 // Merge the results together. Because vmuleub and vmuloub are
6374 // instructions with a big-endian bias, we must reverse the
6375 // element numbering and reverse the meaning of "odd" and "even"
6376 // when generating little endian code.
6378 for (unsigned i = 0; i != 8; ++i) {
6379 if (isLittleEndian) {
6381 Ops[i*2+1] = 2*i+16;
6384 Ops[i*2+1] = 2*i+1+16;
6388 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6390 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6392 llvm_unreachable("Unknown mul to lower!");
6396 /// LowerOperation - Provide custom lowering hooks for some operations.
6398 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6399 switch (Op.getOpcode()) {
6400 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6401 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6402 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6403 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6404 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6405 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6406 case ISD::SETCC: return LowerSETCC(Op, DAG);
6407 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6408 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6410 return LowerVASTART(Op, DAG, Subtarget);
6413 return LowerVAARG(Op, DAG, Subtarget);
6416 return LowerVACOPY(Op, DAG, Subtarget);
6418 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6419 case ISD::DYNAMIC_STACKALLOC:
6420 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6422 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6423 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6425 case ISD::LOAD: return LowerLOAD(Op, DAG);
6426 case ISD::STORE: return LowerSTORE(Op, DAG);
6427 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6428 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6429 case ISD::FP_TO_UINT:
6430 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6432 case ISD::UINT_TO_FP:
6433 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6434 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6436 // Lower 64-bit shifts.
6437 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6438 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6439 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6441 // Vector-related lowering.
6442 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6443 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6444 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6445 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6446 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6447 case ISD::MUL: return LowerMUL(Op, DAG);
6449 // For counter-based loop handling.
6450 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6452 // Frame & Return address.
6453 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6454 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6458 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6459 SmallVectorImpl<SDValue>&Results,
6460 SelectionDAG &DAG) const {
6461 const TargetMachine &TM = getTargetMachine();
6463 switch (N->getOpcode()) {
6465 llvm_unreachable("Do not know how to custom type legalize this operation!");
6466 case ISD::INTRINSIC_W_CHAIN: {
6467 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6468 Intrinsic::ppc_is_decremented_ctr_nonzero)
6471 assert(N->getValueType(0) == MVT::i1 &&
6472 "Unexpected result type for CTR decrement intrinsic");
6473 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6474 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6475 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6478 Results.push_back(NewInt);
6479 Results.push_back(NewInt.getValue(1));
6483 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6484 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6487 EVT VT = N->getValueType(0);
6489 if (VT == MVT::i64) {
6490 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6492 Results.push_back(NewNode);
6493 Results.push_back(NewNode.getValue(1));
6497 case ISD::FP_ROUND_INREG: {
6498 assert(N->getValueType(0) == MVT::ppcf128);
6499 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6500 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6501 MVT::f64, N->getOperand(0),
6502 DAG.getIntPtrConstant(0));
6503 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6504 MVT::f64, N->getOperand(0),
6505 DAG.getIntPtrConstant(1));
6507 // Add the two halves of the long double in round-to-zero mode.
6508 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6510 // We know the low half is about to be thrown away, so just use something
6512 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6516 case ISD::FP_TO_SINT:
6517 // LowerFP_TO_INT() can only handle f32 and f64.
6518 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6520 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6526 //===----------------------------------------------------------------------===//
6527 // Other Lowering Code
6528 //===----------------------------------------------------------------------===//
6531 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6532 bool is64bit, unsigned BinOpcode) const {
6533 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6534 const TargetInstrInfo *TII =
6535 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6537 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6538 MachineFunction *F = BB->getParent();
6539 MachineFunction::iterator It = BB;
6542 unsigned dest = MI->getOperand(0).getReg();
6543 unsigned ptrA = MI->getOperand(1).getReg();
6544 unsigned ptrB = MI->getOperand(2).getReg();
6545 unsigned incr = MI->getOperand(3).getReg();
6546 DebugLoc dl = MI->getDebugLoc();
6548 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6549 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6550 F->insert(It, loopMBB);
6551 F->insert(It, exitMBB);
6552 exitMBB->splice(exitMBB->begin(), BB,
6553 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6554 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6556 MachineRegisterInfo &RegInfo = F->getRegInfo();
6557 unsigned TmpReg = (!BinOpcode) ? incr :
6558 RegInfo.createVirtualRegister(
6559 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6560 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6564 // fallthrough --> loopMBB
6565 BB->addSuccessor(loopMBB);
6568 // l[wd]arx dest, ptr
6569 // add r0, dest, incr
6570 // st[wd]cx. r0, ptr
6572 // fallthrough --> exitMBB
6574 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6575 .addReg(ptrA).addReg(ptrB);
6577 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6578 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6579 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6580 BuildMI(BB, dl, TII->get(PPC::BCC))
6581 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6582 BB->addSuccessor(loopMBB);
6583 BB->addSuccessor(exitMBB);
6592 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6593 MachineBasicBlock *BB,
6594 bool is8bit, // operation
6595 unsigned BinOpcode) const {
6596 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6597 const TargetInstrInfo *TII =
6598 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6599 // In 64 bit mode we have to use 64 bits for addresses, even though the
6600 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6601 // registers without caring whether they're 32 or 64, but here we're
6602 // doing actual arithmetic on the addresses.
6603 bool is64bit = Subtarget.isPPC64();
6604 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6606 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6607 MachineFunction *F = BB->getParent();
6608 MachineFunction::iterator It = BB;
6611 unsigned dest = MI->getOperand(0).getReg();
6612 unsigned ptrA = MI->getOperand(1).getReg();
6613 unsigned ptrB = MI->getOperand(2).getReg();
6614 unsigned incr = MI->getOperand(3).getReg();
6615 DebugLoc dl = MI->getDebugLoc();
6617 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6618 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6619 F->insert(It, loopMBB);
6620 F->insert(It, exitMBB);
6621 exitMBB->splice(exitMBB->begin(), BB,
6622 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6623 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6625 MachineRegisterInfo &RegInfo = F->getRegInfo();
6626 const TargetRegisterClass *RC =
6627 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6628 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6629 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6630 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6631 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6632 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6633 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6634 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6635 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6636 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6637 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6638 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6639 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6641 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6645 // fallthrough --> loopMBB
6646 BB->addSuccessor(loopMBB);
6648 // The 4-byte load must be aligned, while a char or short may be
6649 // anywhere in the word. Hence all this nasty bookkeeping code.
6650 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6651 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6652 // xori shift, shift1, 24 [16]
6653 // rlwinm ptr, ptr1, 0, 0, 29
6654 // slw incr2, incr, shift
6655 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6656 // slw mask, mask2, shift
6658 // lwarx tmpDest, ptr
6659 // add tmp, tmpDest, incr2
6660 // andc tmp2, tmpDest, mask
6661 // and tmp3, tmp, mask
6662 // or tmp4, tmp3, tmp2
6665 // fallthrough --> exitMBB
6666 // srw dest, tmpDest, shift
6667 if (ptrA != ZeroReg) {
6668 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6669 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6670 .addReg(ptrA).addReg(ptrB);
6674 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6675 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6676 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6677 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6679 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6680 .addReg(Ptr1Reg).addImm(0).addImm(61);
6682 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6683 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6684 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6685 .addReg(incr).addReg(ShiftReg);
6687 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6689 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6690 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6692 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6693 .addReg(Mask2Reg).addReg(ShiftReg);
6696 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6697 .addReg(ZeroReg).addReg(PtrReg);
6699 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6700 .addReg(Incr2Reg).addReg(TmpDestReg);
6701 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6702 .addReg(TmpDestReg).addReg(MaskReg);
6703 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6704 .addReg(TmpReg).addReg(MaskReg);
6705 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6706 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6707 BuildMI(BB, dl, TII->get(PPC::STWCX))
6708 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6709 BuildMI(BB, dl, TII->get(PPC::BCC))
6710 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6711 BB->addSuccessor(loopMBB);
6712 BB->addSuccessor(exitMBB);
6717 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6722 llvm::MachineBasicBlock*
6723 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6724 MachineBasicBlock *MBB) const {
6725 DebugLoc DL = MI->getDebugLoc();
6726 const TargetInstrInfo *TII =
6727 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6729 MachineFunction *MF = MBB->getParent();
6730 MachineRegisterInfo &MRI = MF->getRegInfo();
6732 const BasicBlock *BB = MBB->getBasicBlock();
6733 MachineFunction::iterator I = MBB;
6737 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6738 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6740 unsigned DstReg = MI->getOperand(0).getReg();
6741 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6742 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6743 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6744 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6746 MVT PVT = getPointerTy();
6747 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6748 "Invalid Pointer Size!");
6749 // For v = setjmp(buf), we generate
6752 // SjLjSetup mainMBB
6758 // buf[LabelOffset] = LR
6762 // v = phi(main, restore)
6765 MachineBasicBlock *thisMBB = MBB;
6766 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6767 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6768 MF->insert(I, mainMBB);
6769 MF->insert(I, sinkMBB);
6771 MachineInstrBuilder MIB;
6773 // Transfer the remainder of BB and its successor edges to sinkMBB.
6774 sinkMBB->splice(sinkMBB->begin(), MBB,
6775 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6776 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6778 // Note that the structure of the jmp_buf used here is not compatible
6779 // with that used by libc, and is not designed to be. Specifically, it
6780 // stores only those 'reserved' registers that LLVM does not otherwise
6781 // understand how to spill. Also, by convention, by the time this
6782 // intrinsic is called, Clang has already stored the frame address in the
6783 // first slot of the buffer and stack address in the third. Following the
6784 // X86 target code, we'll store the jump address in the second slot. We also
6785 // need to save the TOC pointer (R2) to handle jumps between shared
6786 // libraries, and that will be stored in the fourth slot. The thread
6787 // identifier (R13) is not affected.
6790 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6791 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6792 const int64_t BPOffset = 4 * PVT.getStoreSize();
6794 // Prepare IP either in reg.
6795 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6796 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6797 unsigned BufReg = MI->getOperand(1).getReg();
6799 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6800 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6804 MIB.setMemRefs(MMOBegin, MMOEnd);
6807 // Naked functions never have a base pointer, and so we use r1. For all
6808 // other functions, this decision must be delayed until during PEI.
6810 if (MF->getFunction()->getAttributes().hasAttribute(
6811 AttributeSet::FunctionIndex, Attribute::Naked))
6812 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6814 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6816 MIB = BuildMI(*thisMBB, MI, DL,
6817 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6821 MIB.setMemRefs(MMOBegin, MMOEnd);
6824 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6825 const PPCRegisterInfo *TRI =
6826 getTargetMachine().getSubtarget<PPCSubtarget>().getRegisterInfo();
6827 MIB.addRegMask(TRI->getNoPreservedMask());
6829 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6831 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6833 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6835 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6836 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6840 MIB = BuildMI(mainMBB, DL,
6841 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6844 if (Subtarget.isPPC64()) {
6845 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6847 .addImm(LabelOffset)
6850 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6852 .addImm(LabelOffset)
6856 MIB.setMemRefs(MMOBegin, MMOEnd);
6858 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6859 mainMBB->addSuccessor(sinkMBB);
6862 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6863 TII->get(PPC::PHI), DstReg)
6864 .addReg(mainDstReg).addMBB(mainMBB)
6865 .addReg(restoreDstReg).addMBB(thisMBB);
6867 MI->eraseFromParent();
6872 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6873 MachineBasicBlock *MBB) const {
6874 DebugLoc DL = MI->getDebugLoc();
6875 const TargetInstrInfo *TII =
6876 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6878 MachineFunction *MF = MBB->getParent();
6879 MachineRegisterInfo &MRI = MF->getRegInfo();
6882 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6883 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6885 MVT PVT = getPointerTy();
6886 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6887 "Invalid Pointer Size!");
6889 const TargetRegisterClass *RC =
6890 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6891 unsigned Tmp = MRI.createVirtualRegister(RC);
6892 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6893 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6894 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6895 unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
6896 (Subtarget.isSVR4ABI() &&
6897 MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
6898 PPC::R29 : PPC::R30);
6900 MachineInstrBuilder MIB;
6902 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6903 const int64_t SPOffset = 2 * PVT.getStoreSize();
6904 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6905 const int64_t BPOffset = 4 * PVT.getStoreSize();
6907 unsigned BufReg = MI->getOperand(0).getReg();
6909 // Reload FP (the jumped-to function may not have had a
6910 // frame pointer, and if so, then its r31 will be restored
6912 if (PVT == MVT::i64) {
6913 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6917 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6921 MIB.setMemRefs(MMOBegin, MMOEnd);
6924 if (PVT == MVT::i64) {
6925 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6926 .addImm(LabelOffset)
6929 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6930 .addImm(LabelOffset)
6933 MIB.setMemRefs(MMOBegin, MMOEnd);
6936 if (PVT == MVT::i64) {
6937 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6941 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6945 MIB.setMemRefs(MMOBegin, MMOEnd);
6948 if (PVT == MVT::i64) {
6949 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6953 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6957 MIB.setMemRefs(MMOBegin, MMOEnd);
6960 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
6961 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6965 MIB.setMemRefs(MMOBegin, MMOEnd);
6969 BuildMI(*MBB, MI, DL,
6970 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6971 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6973 MI->eraseFromParent();
6978 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6979 MachineBasicBlock *BB) const {
6980 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6981 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6982 return emitEHSjLjSetJmp(MI, BB);
6983 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6984 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6985 return emitEHSjLjLongJmp(MI, BB);
6988 const TargetInstrInfo *TII =
6989 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6991 // To "insert" these instructions we actually have to insert their
6992 // control-flow patterns.
6993 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6994 MachineFunction::iterator It = BB;
6997 MachineFunction *F = BB->getParent();
6999 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7000 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7001 MI->getOpcode() == PPC::SELECT_I4 ||
7002 MI->getOpcode() == PPC::SELECT_I8)) {
7003 SmallVector<MachineOperand, 2> Cond;
7004 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7005 MI->getOpcode() == PPC::SELECT_CC_I8)
7006 Cond.push_back(MI->getOperand(4));
7008 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
7009 Cond.push_back(MI->getOperand(1));
7011 DebugLoc dl = MI->getDebugLoc();
7012 const TargetInstrInfo *TII =
7013 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7014 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7015 Cond, MI->getOperand(2).getReg(),
7016 MI->getOperand(3).getReg());
7017 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7018 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7019 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7020 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7021 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7022 MI->getOpcode() == PPC::SELECT_I4 ||
7023 MI->getOpcode() == PPC::SELECT_I8 ||
7024 MI->getOpcode() == PPC::SELECT_F4 ||
7025 MI->getOpcode() == PPC::SELECT_F8 ||
7026 MI->getOpcode() == PPC::SELECT_VRRC) {
7027 // The incoming instruction knows the destination vreg to set, the
7028 // condition code register to branch on, the true/false values to
7029 // select between, and a branch opcode to use.
7034 // cmpTY ccX, r1, r2
7036 // fallthrough --> copy0MBB
7037 MachineBasicBlock *thisMBB = BB;
7038 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7039 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7040 DebugLoc dl = MI->getDebugLoc();
7041 F->insert(It, copy0MBB);
7042 F->insert(It, sinkMBB);
7044 // Transfer the remainder of BB and its successor edges to sinkMBB.
7045 sinkMBB->splice(sinkMBB->begin(), BB,
7046 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7047 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7049 // Next, add the true and fallthrough blocks as its successors.
7050 BB->addSuccessor(copy0MBB);
7051 BB->addSuccessor(sinkMBB);
7053 if (MI->getOpcode() == PPC::SELECT_I4 ||
7054 MI->getOpcode() == PPC::SELECT_I8 ||
7055 MI->getOpcode() == PPC::SELECT_F4 ||
7056 MI->getOpcode() == PPC::SELECT_F8 ||
7057 MI->getOpcode() == PPC::SELECT_VRRC) {
7058 BuildMI(BB, dl, TII->get(PPC::BC))
7059 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7061 unsigned SelectPred = MI->getOperand(4).getImm();
7062 BuildMI(BB, dl, TII->get(PPC::BCC))
7063 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7067 // %FalseValue = ...
7068 // # fallthrough to sinkMBB
7071 // Update machine-CFG edges
7072 BB->addSuccessor(sinkMBB);
7075 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7078 BuildMI(*BB, BB->begin(), dl,
7079 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7080 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7081 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7083 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7084 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7085 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7086 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7087 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7088 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7089 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7090 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7092 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7093 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7094 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7095 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7096 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7097 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7098 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7099 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7101 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7102 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7103 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7104 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7105 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7106 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7107 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7108 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7110 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7111 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7112 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7113 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7114 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7115 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7116 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7117 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7119 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7120 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7121 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7122 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7123 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7124 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7125 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7126 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7128 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7129 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7130 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7131 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7132 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7133 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7134 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7135 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7137 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7138 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7139 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7140 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7141 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7142 BB = EmitAtomicBinary(MI, BB, false, 0);
7143 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7144 BB = EmitAtomicBinary(MI, BB, true, 0);
7146 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7147 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7148 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7150 unsigned dest = MI->getOperand(0).getReg();
7151 unsigned ptrA = MI->getOperand(1).getReg();
7152 unsigned ptrB = MI->getOperand(2).getReg();
7153 unsigned oldval = MI->getOperand(3).getReg();
7154 unsigned newval = MI->getOperand(4).getReg();
7155 DebugLoc dl = MI->getDebugLoc();
7157 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7158 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7159 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7160 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7161 F->insert(It, loop1MBB);
7162 F->insert(It, loop2MBB);
7163 F->insert(It, midMBB);
7164 F->insert(It, exitMBB);
7165 exitMBB->splice(exitMBB->begin(), BB,
7166 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7167 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7171 // fallthrough --> loopMBB
7172 BB->addSuccessor(loop1MBB);
7175 // l[wd]arx dest, ptr
7176 // cmp[wd] dest, oldval
7179 // st[wd]cx. newval, ptr
7183 // st[wd]cx. dest, ptr
7186 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7187 .addReg(ptrA).addReg(ptrB);
7188 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7189 .addReg(oldval).addReg(dest);
7190 BuildMI(BB, dl, TII->get(PPC::BCC))
7191 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7192 BB->addSuccessor(loop2MBB);
7193 BB->addSuccessor(midMBB);
7196 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7197 .addReg(newval).addReg(ptrA).addReg(ptrB);
7198 BuildMI(BB, dl, TII->get(PPC::BCC))
7199 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7200 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7201 BB->addSuccessor(loop1MBB);
7202 BB->addSuccessor(exitMBB);
7205 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7206 .addReg(dest).addReg(ptrA).addReg(ptrB);
7207 BB->addSuccessor(exitMBB);
7212 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7213 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7214 // We must use 64-bit registers for addresses when targeting 64-bit,
7215 // since we're actually doing arithmetic on them. Other registers
7217 bool is64bit = Subtarget.isPPC64();
7218 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7220 unsigned dest = MI->getOperand(0).getReg();
7221 unsigned ptrA = MI->getOperand(1).getReg();
7222 unsigned ptrB = MI->getOperand(2).getReg();
7223 unsigned oldval = MI->getOperand(3).getReg();
7224 unsigned newval = MI->getOperand(4).getReg();
7225 DebugLoc dl = MI->getDebugLoc();
7227 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7228 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7229 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7230 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7231 F->insert(It, loop1MBB);
7232 F->insert(It, loop2MBB);
7233 F->insert(It, midMBB);
7234 F->insert(It, exitMBB);
7235 exitMBB->splice(exitMBB->begin(), BB,
7236 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7237 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7239 MachineRegisterInfo &RegInfo = F->getRegInfo();
7240 const TargetRegisterClass *RC =
7241 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
7242 (const TargetRegisterClass *) &PPC::GPRCRegClass;
7243 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7244 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7245 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7246 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7247 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7248 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7249 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7250 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7251 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7252 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7253 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7254 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7255 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7257 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7258 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7261 // fallthrough --> loopMBB
7262 BB->addSuccessor(loop1MBB);
7264 // The 4-byte load must be aligned, while a char or short may be
7265 // anywhere in the word. Hence all this nasty bookkeeping code.
7266 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7267 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7268 // xori shift, shift1, 24 [16]
7269 // rlwinm ptr, ptr1, 0, 0, 29
7270 // slw newval2, newval, shift
7271 // slw oldval2, oldval,shift
7272 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7273 // slw mask, mask2, shift
7274 // and newval3, newval2, mask
7275 // and oldval3, oldval2, mask
7277 // lwarx tmpDest, ptr
7278 // and tmp, tmpDest, mask
7279 // cmpw tmp, oldval3
7282 // andc tmp2, tmpDest, mask
7283 // or tmp4, tmp2, newval3
7288 // stwcx. tmpDest, ptr
7290 // srw dest, tmpDest, shift
7291 if (ptrA != ZeroReg) {
7292 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7293 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7294 .addReg(ptrA).addReg(ptrB);
7298 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7299 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7300 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7301 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7303 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7304 .addReg(Ptr1Reg).addImm(0).addImm(61);
7306 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7307 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7308 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7309 .addReg(newval).addReg(ShiftReg);
7310 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7311 .addReg(oldval).addReg(ShiftReg);
7313 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7315 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7316 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7317 .addReg(Mask3Reg).addImm(65535);
7319 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7320 .addReg(Mask2Reg).addReg(ShiftReg);
7321 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7322 .addReg(NewVal2Reg).addReg(MaskReg);
7323 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7324 .addReg(OldVal2Reg).addReg(MaskReg);
7327 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7328 .addReg(ZeroReg).addReg(PtrReg);
7329 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7330 .addReg(TmpDestReg).addReg(MaskReg);
7331 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7332 .addReg(TmpReg).addReg(OldVal3Reg);
7333 BuildMI(BB, dl, TII->get(PPC::BCC))
7334 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7335 BB->addSuccessor(loop2MBB);
7336 BB->addSuccessor(midMBB);
7339 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7340 .addReg(TmpDestReg).addReg(MaskReg);
7341 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7342 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7343 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7344 .addReg(ZeroReg).addReg(PtrReg);
7345 BuildMI(BB, dl, TII->get(PPC::BCC))
7346 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7347 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7348 BB->addSuccessor(loop1MBB);
7349 BB->addSuccessor(exitMBB);
7352 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7353 .addReg(ZeroReg).addReg(PtrReg);
7354 BB->addSuccessor(exitMBB);
7359 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7361 } else if (MI->getOpcode() == PPC::FADDrtz) {
7362 // This pseudo performs an FADD with rounding mode temporarily forced
7363 // to round-to-zero. We emit this via custom inserter since the FPSCR
7364 // is not modeled at the SelectionDAG level.
7365 unsigned Dest = MI->getOperand(0).getReg();
7366 unsigned Src1 = MI->getOperand(1).getReg();
7367 unsigned Src2 = MI->getOperand(2).getReg();
7368 DebugLoc dl = MI->getDebugLoc();
7370 MachineRegisterInfo &RegInfo = F->getRegInfo();
7371 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7373 // Save FPSCR value.
7374 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7376 // Set rounding mode to round-to-zero.
7377 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7378 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7380 // Perform addition.
7381 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7383 // Restore FPSCR value.
7384 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7385 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7386 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7387 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7388 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7389 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7390 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7391 PPC::ANDIo8 : PPC::ANDIo;
7392 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7393 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7395 MachineRegisterInfo &RegInfo = F->getRegInfo();
7396 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7397 &PPC::GPRCRegClass :
7398 &PPC::G8RCRegClass);
7400 DebugLoc dl = MI->getDebugLoc();
7401 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7402 .addReg(MI->getOperand(1).getReg()).addImm(1);
7403 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7404 MI->getOperand(0).getReg())
7405 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7407 llvm_unreachable("Unexpected instr type to insert");
7410 MI->eraseFromParent(); // The pseudo instruction is gone now.
7414 //===----------------------------------------------------------------------===//
7415 // Target Optimization Hooks
7416 //===----------------------------------------------------------------------===//
7418 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
7419 DAGCombinerInfo &DCI) const {
7420 if (DCI.isAfterLegalizeVectorOps())
7423 EVT VT = Op.getValueType();
7425 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7426 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7427 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7428 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7430 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7431 // For the reciprocal, we need to find the zero of the function:
7432 // F(X) = A X - 1 [which has a zero at X = 1/A]
7434 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7435 // does not require additional intermediate precision]
7437 // Convergence is quadratic, so we essentially double the number of digits
7438 // correct after every iteration. The minimum architected relative
7439 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7440 // 23 digits and double has 52 digits.
7441 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7442 if (VT.getScalarType() == MVT::f64)
7445 SelectionDAG &DAG = DCI.DAG;
7449 DAG.getConstantFP(1.0, VT.getScalarType());
7450 if (VT.isVector()) {
7451 assert(VT.getVectorNumElements() == 4 &&
7452 "Unknown vector type");
7453 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7454 FPOne, FPOne, FPOne, FPOne);
7457 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
7458 DCI.AddToWorklist(Est.getNode());
7460 // Newton iterations: Est = Est + Est (1 - Arg * Est)
7461 for (int i = 0; i < Iterations; ++i) {
7462 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
7463 DCI.AddToWorklist(NewEst.getNode());
7465 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
7466 DCI.AddToWorklist(NewEst.getNode());
7468 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7469 DCI.AddToWorklist(NewEst.getNode());
7471 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
7472 DCI.AddToWorklist(Est.getNode());
7481 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
7482 DAGCombinerInfo &DCI) const {
7483 if (DCI.isAfterLegalizeVectorOps())
7486 EVT VT = Op.getValueType();
7488 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7489 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7490 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7491 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7493 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7494 // For the reciprocal sqrt, we need to find the zero of the function:
7495 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7497 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7498 // As a result, we precompute A/2 prior to the iteration loop.
7500 // Convergence is quadratic, so we essentially double the number of digits
7501 // correct after every iteration. The minimum architected relative
7502 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7503 // 23 digits and double has 52 digits.
7504 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7505 if (VT.getScalarType() == MVT::f64)
7508 SelectionDAG &DAG = DCI.DAG;
7511 SDValue FPThreeHalves =
7512 DAG.getConstantFP(1.5, VT.getScalarType());
7513 if (VT.isVector()) {
7514 assert(VT.getVectorNumElements() == 4 &&
7515 "Unknown vector type");
7516 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7517 FPThreeHalves, FPThreeHalves,
7518 FPThreeHalves, FPThreeHalves);
7521 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7522 DCI.AddToWorklist(Est.getNode());
7524 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7525 // this entire sequence requires only one FP constant.
7526 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7527 DCI.AddToWorklist(HalfArg.getNode());
7529 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7530 DCI.AddToWorklist(HalfArg.getNode());
7532 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7533 for (int i = 0; i < Iterations; ++i) {
7534 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7535 DCI.AddToWorklist(NewEst.getNode());
7537 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7538 DCI.AddToWorklist(NewEst.getNode());
7540 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7541 DCI.AddToWorklist(NewEst.getNode());
7543 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7544 DCI.AddToWorklist(Est.getNode());
7553 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
7554 unsigned Bytes, int Dist,
7555 SelectionDAG &DAG) {
7556 if (VT.getSizeInBits() / 8 != Bytes)
7559 SDValue BaseLoc = Base->getBasePtr();
7560 if (Loc.getOpcode() == ISD::FrameIndex) {
7561 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7563 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7564 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7565 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7566 int FS = MFI->getObjectSize(FI);
7567 int BFS = MFI->getObjectSize(BFI);
7568 if (FS != BFS || FS != (int)Bytes) return false;
7569 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7573 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7574 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7577 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7578 const GlobalValue *GV1 = nullptr;
7579 const GlobalValue *GV2 = nullptr;
7580 int64_t Offset1 = 0;
7581 int64_t Offset2 = 0;
7582 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7583 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7584 if (isGA1 && isGA2 && GV1 == GV2)
7585 return Offset1 == (Offset2 + Dist*Bytes);
7589 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7590 // not enforce equality of the chain operands.
7591 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
7592 unsigned Bytes, int Dist,
7593 SelectionDAG &DAG) {
7594 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
7595 EVT VT = LS->getMemoryVT();
7596 SDValue Loc = LS->getBasePtr();
7597 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
7600 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
7602 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7603 default: return false;
7604 case Intrinsic::ppc_altivec_lvx:
7605 case Intrinsic::ppc_altivec_lvxl:
7608 case Intrinsic::ppc_altivec_lvebx:
7611 case Intrinsic::ppc_altivec_lvehx:
7614 case Intrinsic::ppc_altivec_lvewx:
7619 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
7622 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
7624 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7625 default: return false;
7626 case Intrinsic::ppc_altivec_stvx:
7627 case Intrinsic::ppc_altivec_stvxl:
7630 case Intrinsic::ppc_altivec_stvebx:
7633 case Intrinsic::ppc_altivec_stvehx:
7636 case Intrinsic::ppc_altivec_stvewx:
7641 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
7647 // Return true is there is a nearyby consecutive load to the one provided
7648 // (regardless of alignment). We search up and down the chain, looking though
7649 // token factors and other loads (but nothing else). As a result, a true result
7650 // indicates that it is safe to create a new consecutive load adjacent to the
7652 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7653 SDValue Chain = LD->getChain();
7654 EVT VT = LD->getMemoryVT();
7656 SmallSet<SDNode *, 16> LoadRoots;
7657 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7658 SmallSet<SDNode *, 16> Visited;
7660 // First, search up the chain, branching to follow all token-factor operands.
7661 // If we find a consecutive load, then we're done, otherwise, record all
7662 // nodes just above the top-level loads and token factors.
7663 while (!Queue.empty()) {
7664 SDNode *ChainNext = Queue.pop_back_val();
7665 if (!Visited.insert(ChainNext))
7668 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
7669 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7672 if (!Visited.count(ChainLD->getChain().getNode()))
7673 Queue.push_back(ChainLD->getChain().getNode());
7674 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7675 for (const SDUse &O : ChainNext->ops())
7676 if (!Visited.count(O.getNode()))
7677 Queue.push_back(O.getNode());
7679 LoadRoots.insert(ChainNext);
7682 // Second, search down the chain, starting from the top-level nodes recorded
7683 // in the first phase. These top-level nodes are the nodes just above all
7684 // loads and token factors. Starting with their uses, recursively look though
7685 // all loads (just the chain uses) and token factors to find a consecutive
7690 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7691 IE = LoadRoots.end(); I != IE; ++I) {
7692 Queue.push_back(*I);
7694 while (!Queue.empty()) {
7695 SDNode *LoadRoot = Queue.pop_back_val();
7696 if (!Visited.insert(LoadRoot))
7699 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
7700 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7703 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7704 UE = LoadRoot->use_end(); UI != UE; ++UI)
7705 if (((isa<MemSDNode>(*UI) &&
7706 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7707 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7708 Queue.push_back(*UI);
7715 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7716 DAGCombinerInfo &DCI) const {
7717 SelectionDAG &DAG = DCI.DAG;
7720 assert(Subtarget.useCRBits() &&
7721 "Expecting to be tracking CR bits");
7722 // If we're tracking CR bits, we need to be careful that we don't have:
7723 // trunc(binary-ops(zext(x), zext(y)))
7725 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7726 // such that we're unnecessarily moving things into GPRs when it would be
7727 // better to keep them in CR bits.
7729 // Note that trunc here can be an actual i1 trunc, or can be the effective
7730 // truncation that comes from a setcc or select_cc.
7731 if (N->getOpcode() == ISD::TRUNCATE &&
7732 N->getValueType(0) != MVT::i1)
7735 if (N->getOperand(0).getValueType() != MVT::i32 &&
7736 N->getOperand(0).getValueType() != MVT::i64)
7739 if (N->getOpcode() == ISD::SETCC ||
7740 N->getOpcode() == ISD::SELECT_CC) {
7741 // If we're looking at a comparison, then we need to make sure that the
7742 // high bits (all except for the first) don't matter the result.
7744 cast<CondCodeSDNode>(N->getOperand(
7745 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7746 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7748 if (ISD::isSignedIntSetCC(CC)) {
7749 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7750 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7752 } else if (ISD::isUnsignedIntSetCC(CC)) {
7753 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7754 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7755 !DAG.MaskedValueIsZero(N->getOperand(1),
7756 APInt::getHighBitsSet(OpBits, OpBits-1)))
7759 // This is neither a signed nor an unsigned comparison, just make sure
7760 // that the high bits are equal.
7761 APInt Op1Zero, Op1One;
7762 APInt Op2Zero, Op2One;
7763 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7764 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7766 // We don't really care about what is known about the first bit (if
7767 // anything), so clear it in all masks prior to comparing them.
7768 Op1Zero.clearBit(0); Op1One.clearBit(0);
7769 Op2Zero.clearBit(0); Op2One.clearBit(0);
7771 if (Op1Zero != Op2Zero || Op1One != Op2One)
7776 // We now know that the higher-order bits are irrelevant, we just need to
7777 // make sure that all of the intermediate operations are bit operations, and
7778 // all inputs are extensions.
7779 if (N->getOperand(0).getOpcode() != ISD::AND &&
7780 N->getOperand(0).getOpcode() != ISD::OR &&
7781 N->getOperand(0).getOpcode() != ISD::XOR &&
7782 N->getOperand(0).getOpcode() != ISD::SELECT &&
7783 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7784 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7785 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7786 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7787 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7790 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7791 N->getOperand(1).getOpcode() != ISD::AND &&
7792 N->getOperand(1).getOpcode() != ISD::OR &&
7793 N->getOperand(1).getOpcode() != ISD::XOR &&
7794 N->getOperand(1).getOpcode() != ISD::SELECT &&
7795 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7796 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7797 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7798 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7799 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7802 SmallVector<SDValue, 4> Inputs;
7803 SmallVector<SDValue, 8> BinOps, PromOps;
7804 SmallPtrSet<SDNode *, 16> Visited;
7806 for (unsigned i = 0; i < 2; ++i) {
7807 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7808 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7809 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7810 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7811 isa<ConstantSDNode>(N->getOperand(i)))
7812 Inputs.push_back(N->getOperand(i));
7814 BinOps.push_back(N->getOperand(i));
7816 if (N->getOpcode() == ISD::TRUNCATE)
7820 // Visit all inputs, collect all binary operations (and, or, xor and
7821 // select) that are all fed by extensions.
7822 while (!BinOps.empty()) {
7823 SDValue BinOp = BinOps.back();
7826 if (!Visited.insert(BinOp.getNode()))
7829 PromOps.push_back(BinOp);
7831 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7832 // The condition of the select is not promoted.
7833 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7835 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7838 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7839 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7840 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7841 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7842 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7843 Inputs.push_back(BinOp.getOperand(i));
7844 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7845 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7846 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7847 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7848 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7849 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7850 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7851 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7852 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7853 BinOps.push_back(BinOp.getOperand(i));
7855 // We have an input that is not an extension or another binary
7856 // operation; we'll abort this transformation.
7862 // Make sure that this is a self-contained cluster of operations (which
7863 // is not quite the same thing as saying that everything has only one
7865 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7866 if (isa<ConstantSDNode>(Inputs[i]))
7869 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7870 UE = Inputs[i].getNode()->use_end();
7873 if (User != N && !Visited.count(User))
7876 // Make sure that we're not going to promote the non-output-value
7877 // operand(s) or SELECT or SELECT_CC.
7878 // FIXME: Although we could sometimes handle this, and it does occur in
7879 // practice that one of the condition inputs to the select is also one of
7880 // the outputs, we currently can't deal with this.
7881 if (User->getOpcode() == ISD::SELECT) {
7882 if (User->getOperand(0) == Inputs[i])
7884 } else if (User->getOpcode() == ISD::SELECT_CC) {
7885 if (User->getOperand(0) == Inputs[i] ||
7886 User->getOperand(1) == Inputs[i])
7892 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7893 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7894 UE = PromOps[i].getNode()->use_end();
7897 if (User != N && !Visited.count(User))
7900 // Make sure that we're not going to promote the non-output-value
7901 // operand(s) or SELECT or SELECT_CC.
7902 // FIXME: Although we could sometimes handle this, and it does occur in
7903 // practice that one of the condition inputs to the select is also one of
7904 // the outputs, we currently can't deal with this.
7905 if (User->getOpcode() == ISD::SELECT) {
7906 if (User->getOperand(0) == PromOps[i])
7908 } else if (User->getOpcode() == ISD::SELECT_CC) {
7909 if (User->getOperand(0) == PromOps[i] ||
7910 User->getOperand(1) == PromOps[i])
7916 // Replace all inputs with the extension operand.
7917 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7918 // Constants may have users outside the cluster of to-be-promoted nodes,
7919 // and so we need to replace those as we do the promotions.
7920 if (isa<ConstantSDNode>(Inputs[i]))
7923 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7926 // Replace all operations (these are all the same, but have a different
7927 // (i1) return type). DAG.getNode will validate that the types of
7928 // a binary operator match, so go through the list in reverse so that
7929 // we've likely promoted both operands first. Any intermediate truncations or
7930 // extensions disappear.
7931 while (!PromOps.empty()) {
7932 SDValue PromOp = PromOps.back();
7935 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7936 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7937 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7938 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7939 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7940 PromOp.getOperand(0).getValueType() != MVT::i1) {
7941 // The operand is not yet ready (see comment below).
7942 PromOps.insert(PromOps.begin(), PromOp);
7946 SDValue RepValue = PromOp.getOperand(0);
7947 if (isa<ConstantSDNode>(RepValue))
7948 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7950 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7955 switch (PromOp.getOpcode()) {
7956 default: C = 0; break;
7957 case ISD::SELECT: C = 1; break;
7958 case ISD::SELECT_CC: C = 2; break;
7961 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7962 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7963 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7964 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7965 // The to-be-promoted operands of this node have not yet been
7966 // promoted (this should be rare because we're going through the
7967 // list backward, but if one of the operands has several users in
7968 // this cluster of to-be-promoted nodes, it is possible).
7969 PromOps.insert(PromOps.begin(), PromOp);
7973 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7974 PromOp.getNode()->op_end());
7976 // If there are any constant inputs, make sure they're replaced now.
7977 for (unsigned i = 0; i < 2; ++i)
7978 if (isa<ConstantSDNode>(Ops[C+i]))
7979 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7981 DAG.ReplaceAllUsesOfValueWith(PromOp,
7982 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
7985 // Now we're left with the initial truncation itself.
7986 if (N->getOpcode() == ISD::TRUNCATE)
7987 return N->getOperand(0);
7989 // Otherwise, this is a comparison. The operands to be compared have just
7990 // changed type (to i1), but everything else is the same.
7991 return SDValue(N, 0);
7994 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7995 DAGCombinerInfo &DCI) const {
7996 SelectionDAG &DAG = DCI.DAG;
7999 // If we're tracking CR bits, we need to be careful that we don't have:
8000 // zext(binary-ops(trunc(x), trunc(y)))
8002 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
8003 // such that we're unnecessarily moving things into CR bits that can more
8004 // efficiently stay in GPRs. Note that if we're not certain that the high
8005 // bits are set as required by the final extension, we still may need to do
8006 // some masking to get the proper behavior.
8008 // This same functionality is important on PPC64 when dealing with
8009 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
8010 // the return values of functions. Because it is so similar, it is handled
8013 if (N->getValueType(0) != MVT::i32 &&
8014 N->getValueType(0) != MVT::i64)
8017 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
8018 Subtarget.useCRBits()) ||
8019 (N->getOperand(0).getValueType() == MVT::i32 &&
8020 Subtarget.isPPC64())))
8023 if (N->getOperand(0).getOpcode() != ISD::AND &&
8024 N->getOperand(0).getOpcode() != ISD::OR &&
8025 N->getOperand(0).getOpcode() != ISD::XOR &&
8026 N->getOperand(0).getOpcode() != ISD::SELECT &&
8027 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
8030 SmallVector<SDValue, 4> Inputs;
8031 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
8032 SmallPtrSet<SDNode *, 16> Visited;
8034 // Visit all inputs, collect all binary operations (and, or, xor and
8035 // select) that are all fed by truncations.
8036 while (!BinOps.empty()) {
8037 SDValue BinOp = BinOps.back();
8040 if (!Visited.insert(BinOp.getNode()))
8043 PromOps.push_back(BinOp);
8045 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8046 // The condition of the select is not promoted.
8047 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8049 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8052 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8053 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8054 Inputs.push_back(BinOp.getOperand(i));
8055 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8056 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8057 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8058 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8059 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
8060 BinOps.push_back(BinOp.getOperand(i));
8062 // We have an input that is not a truncation or another binary
8063 // operation; we'll abort this transformation.
8069 // Make sure that this is a self-contained cluster of operations (which
8070 // is not quite the same thing as saying that everything has only one
8072 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8073 if (isa<ConstantSDNode>(Inputs[i]))
8076 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8077 UE = Inputs[i].getNode()->use_end();
8080 if (User != N && !Visited.count(User))
8083 // Make sure that we're not going to promote the non-output-value
8084 // operand(s) or SELECT or SELECT_CC.
8085 // FIXME: Although we could sometimes handle this, and it does occur in
8086 // practice that one of the condition inputs to the select is also one of
8087 // the outputs, we currently can't deal with this.
8088 if (User->getOpcode() == ISD::SELECT) {
8089 if (User->getOperand(0) == Inputs[i])
8091 } else if (User->getOpcode() == ISD::SELECT_CC) {
8092 if (User->getOperand(0) == Inputs[i] ||
8093 User->getOperand(1) == Inputs[i])
8099 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8100 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8101 UE = PromOps[i].getNode()->use_end();
8104 if (User != N && !Visited.count(User))
8107 // Make sure that we're not going to promote the non-output-value
8108 // operand(s) or SELECT or SELECT_CC.
8109 // FIXME: Although we could sometimes handle this, and it does occur in
8110 // practice that one of the condition inputs to the select is also one of
8111 // the outputs, we currently can't deal with this.
8112 if (User->getOpcode() == ISD::SELECT) {
8113 if (User->getOperand(0) == PromOps[i])
8115 } else if (User->getOpcode() == ISD::SELECT_CC) {
8116 if (User->getOperand(0) == PromOps[i] ||
8117 User->getOperand(1) == PromOps[i])
8123 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8124 bool ReallyNeedsExt = false;
8125 if (N->getOpcode() != ISD::ANY_EXTEND) {
8126 // If all of the inputs are not already sign/zero extended, then
8127 // we'll still need to do that at the end.
8128 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8129 if (isa<ConstantSDNode>(Inputs[i]))
8133 Inputs[i].getOperand(0).getValueSizeInBits();
8134 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8136 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8137 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8138 APInt::getHighBitsSet(OpBits,
8139 OpBits-PromBits))) ||
8140 (N->getOpcode() == ISD::SIGN_EXTEND &&
8141 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8142 (OpBits-(PromBits-1)))) {
8143 ReallyNeedsExt = true;
8149 // Replace all inputs, either with the truncation operand, or a
8150 // truncation or extension to the final output type.
8151 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8152 // Constant inputs need to be replaced with the to-be-promoted nodes that
8153 // use them because they might have users outside of the cluster of
8155 if (isa<ConstantSDNode>(Inputs[i]))
8158 SDValue InSrc = Inputs[i].getOperand(0);
8159 if (Inputs[i].getValueType() == N->getValueType(0))
8160 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8161 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8162 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8163 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8164 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8165 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8166 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8168 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8169 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8172 // Replace all operations (these are all the same, but have a different
8173 // (promoted) return type). DAG.getNode will validate that the types of
8174 // a binary operator match, so go through the list in reverse so that
8175 // we've likely promoted both operands first.
8176 while (!PromOps.empty()) {
8177 SDValue PromOp = PromOps.back();
8181 switch (PromOp.getOpcode()) {
8182 default: C = 0; break;
8183 case ISD::SELECT: C = 1; break;
8184 case ISD::SELECT_CC: C = 2; break;
8187 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8188 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8189 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8190 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8191 // The to-be-promoted operands of this node have not yet been
8192 // promoted (this should be rare because we're going through the
8193 // list backward, but if one of the operands has several users in
8194 // this cluster of to-be-promoted nodes, it is possible).
8195 PromOps.insert(PromOps.begin(), PromOp);
8199 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8200 PromOp.getNode()->op_end());
8202 // If this node has constant inputs, then they'll need to be promoted here.
8203 for (unsigned i = 0; i < 2; ++i) {
8204 if (!isa<ConstantSDNode>(Ops[C+i]))
8206 if (Ops[C+i].getValueType() == N->getValueType(0))
8209 if (N->getOpcode() == ISD::SIGN_EXTEND)
8210 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8211 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8212 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8214 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8217 DAG.ReplaceAllUsesOfValueWith(PromOp,
8218 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8221 // Now we're left with the initial extension itself.
8222 if (!ReallyNeedsExt)
8223 return N->getOperand(0);
8225 // To zero extend, just mask off everything except for the first bit (in the
8227 if (N->getOpcode() == ISD::ZERO_EXTEND)
8228 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8229 DAG.getConstant(APInt::getLowBitsSet(
8230 N->getValueSizeInBits(0), PromBits),
8231 N->getValueType(0)));
8233 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8234 "Invalid extension type");
8235 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8237 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8238 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8239 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8240 N->getOperand(0), ShiftCst), ShiftCst);
8243 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8244 DAGCombinerInfo &DCI) const {
8245 const TargetMachine &TM = getTargetMachine();
8246 SelectionDAG &DAG = DCI.DAG;
8248 switch (N->getOpcode()) {
8251 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8252 if (C->isNullValue()) // 0 << V -> 0.
8253 return N->getOperand(0);
8257 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8258 if (C->isNullValue()) // 0 >>u V -> 0.
8259 return N->getOperand(0);
8263 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8264 if (C->isNullValue() || // 0 >>s V -> 0.
8265 C->isAllOnesValue()) // -1 >>s V -> -1.
8266 return N->getOperand(0);
8269 case ISD::SIGN_EXTEND:
8270 case ISD::ZERO_EXTEND:
8271 case ISD::ANY_EXTEND:
8272 return DAGCombineExtBoolTrunc(N, DCI);
8275 case ISD::SELECT_CC:
8276 return DAGCombineTruncBoolExt(N, DCI);
8278 assert(TM.Options.UnsafeFPMath &&
8279 "Reciprocal estimates require UnsafeFPMath");
8281 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
8283 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
8285 DCI.AddToWorklist(RV.getNode());
8286 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8287 N->getOperand(0), RV);
8289 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
8290 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
8292 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
8295 DCI.AddToWorklist(RV.getNode());
8296 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
8297 N->getValueType(0), RV);
8298 DCI.AddToWorklist(RV.getNode());
8299 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8300 N->getOperand(0), RV);
8302 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
8303 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
8305 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
8308 DCI.AddToWorklist(RV.getNode());
8309 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
8310 N->getValueType(0), RV,
8311 N->getOperand(1).getOperand(1));
8312 DCI.AddToWorklist(RV.getNode());
8313 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8314 N->getOperand(0), RV);
8318 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
8320 DCI.AddToWorklist(RV.getNode());
8321 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8322 N->getOperand(0), RV);
8328 assert(TM.Options.UnsafeFPMath &&
8329 "Reciprocal estimates require UnsafeFPMath");
8331 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
8333 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
8335 DCI.AddToWorklist(RV.getNode());
8336 RV = DAGCombineFastRecip(RV, DCI);
8338 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
8339 // this case and force the answer to 0.
8341 EVT VT = RV.getValueType();
8343 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
8344 if (VT.isVector()) {
8345 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
8346 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
8350 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
8351 N->getOperand(0), Zero, ISD::SETEQ);
8352 DCI.AddToWorklist(ZeroCmp.getNode());
8353 DCI.AddToWorklist(RV.getNode());
8355 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
8363 case ISD::SINT_TO_FP:
8364 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
8365 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8366 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8367 // We allow the src/dst to be either f32/f64, but the intermediate
8368 // type must be i64.
8369 if (N->getOperand(0).getValueType() == MVT::i64 &&
8370 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
8371 SDValue Val = N->getOperand(0).getOperand(0);
8372 if (Val.getValueType() == MVT::f32) {
8373 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8374 DCI.AddToWorklist(Val.getNode());
8377 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8378 DCI.AddToWorklist(Val.getNode());
8379 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8380 DCI.AddToWorklist(Val.getNode());
8381 if (N->getValueType(0) == MVT::f32) {
8382 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8383 DAG.getIntPtrConstant(0));
8384 DCI.AddToWorklist(Val.getNode());
8387 } else if (N->getOperand(0).getValueType() == MVT::i32) {
8388 // If the intermediate type is i32, we can avoid the load/store here
8395 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8396 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8397 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8398 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8399 N->getOperand(1).getValueType() == MVT::i32 &&
8400 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8401 SDValue Val = N->getOperand(1).getOperand(0);
8402 if (Val.getValueType() == MVT::f32) {
8403 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8404 DCI.AddToWorklist(Val.getNode());
8406 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8407 DCI.AddToWorklist(Val.getNode());
8410 N->getOperand(0), Val, N->getOperand(2),
8411 DAG.getValueType(N->getOperand(1).getValueType())
8414 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8415 DAG.getVTList(MVT::Other), Ops,
8416 cast<StoreSDNode>(N)->getMemoryVT(),
8417 cast<StoreSDNode>(N)->getMemOperand());
8418 DCI.AddToWorklist(Val.getNode());
8422 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8423 if (cast<StoreSDNode>(N)->isUnindexed() &&
8424 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8425 N->getOperand(1).getNode()->hasOneUse() &&
8426 (N->getOperand(1).getValueType() == MVT::i32 ||
8427 N->getOperand(1).getValueType() == MVT::i16 ||
8428 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8429 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8430 N->getOperand(1).getValueType() == MVT::i64))) {
8431 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8432 // Do an any-extend to 32-bits if this is a half-word input.
8433 if (BSwapOp.getValueType() == MVT::i16)
8434 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8437 N->getOperand(0), BSwapOp, N->getOperand(2),
8438 DAG.getValueType(N->getOperand(1).getValueType())
8441 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8442 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8443 cast<StoreSDNode>(N)->getMemOperand());
8447 LoadSDNode *LD = cast<LoadSDNode>(N);
8448 EVT VT = LD->getValueType(0);
8449 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8450 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8451 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8452 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8453 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8454 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8455 LD->getAlignment() < ABIAlignment) {
8456 // This is a type-legal unaligned Altivec load.
8457 SDValue Chain = LD->getChain();
8458 SDValue Ptr = LD->getBasePtr();
8459 bool isLittleEndian = Subtarget.isLittleEndian();
8461 // This implements the loading of unaligned vectors as described in
8462 // the venerable Apple Velocity Engine overview. Specifically:
8463 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8464 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8466 // The general idea is to expand a sequence of one or more unaligned
8467 // loads into an alignment-based permutation-control instruction (lvsl
8468 // or lvsr), a series of regular vector loads (which always truncate
8469 // their input address to an aligned address), and a series of
8470 // permutations. The results of these permutations are the requested
8471 // loaded values. The trick is that the last "extra" load is not taken
8472 // from the address you might suspect (sizeof(vector) bytes after the
8473 // last requested load), but rather sizeof(vector) - 1 bytes after the
8474 // last requested vector. The point of this is to avoid a page fault if
8475 // the base address happened to be aligned. This works because if the
8476 // base address is aligned, then adding less than a full vector length
8477 // will cause the last vector in the sequence to be (re)loaded.
8478 // Otherwise, the next vector will be fetched as you might suspect was
8481 // We might be able to reuse the permutation generation from
8482 // a different base address offset from this one by an aligned amount.
8483 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8484 // optimization later.
8485 Intrinsic::ID Intr = (isLittleEndian ?
8486 Intrinsic::ppc_altivec_lvsr :
8487 Intrinsic::ppc_altivec_lvsl);
8488 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8490 // Create the new MMO for the new base load. It is like the original MMO,
8491 // but represents an area in memory almost twice the vector size centered
8492 // on the original address. If the address is unaligned, we might start
8493 // reading up to (sizeof(vector)-1) bytes below the address of the
8494 // original unaligned load.
8495 MachineFunction &MF = DAG.getMachineFunction();
8496 MachineMemOperand *BaseMMO =
8497 MF.getMachineMemOperand(LD->getMemOperand(),
8498 -LD->getMemoryVT().getStoreSize()+1,
8499 2*LD->getMemoryVT().getStoreSize()-1);
8501 // Create the new base load.
8502 SDValue LDXIntID = DAG.getTargetConstant(Intrinsic::ppc_altivec_lvx,
8504 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
8506 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8507 DAG.getVTList(MVT::v4i32, MVT::Other),
8508 BaseLoadOps, MVT::v4i32, BaseMMO);
8510 // Note that the value of IncOffset (which is provided to the next
8511 // load's pointer info offset value, and thus used to calculate the
8512 // alignment), and the value of IncValue (which is actually used to
8513 // increment the pointer value) are different! This is because we
8514 // require the next load to appear to be aligned, even though it
8515 // is actually offset from the base pointer by a lesser amount.
8516 int IncOffset = VT.getSizeInBits() / 8;
8517 int IncValue = IncOffset;
8519 // Walk (both up and down) the chain looking for another load at the real
8520 // (aligned) offset (the alignment of the other load does not matter in
8521 // this case). If found, then do not use the offset reduction trick, as
8522 // that will prevent the loads from being later combined (as they would
8523 // otherwise be duplicates).
8524 if (!findConsecutiveLoad(LD, DAG))
8527 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8528 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8530 MachineMemOperand *ExtraMMO =
8531 MF.getMachineMemOperand(LD->getMemOperand(),
8532 1, 2*LD->getMemoryVT().getStoreSize()-1);
8533 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
8535 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8536 DAG.getVTList(MVT::v4i32, MVT::Other),
8537 ExtraLoadOps, MVT::v4i32, ExtraMMO);
8539 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8540 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8542 // Because vperm has a big-endian bias, we must reverse the order
8543 // of the input vectors and complement the permute control vector
8544 // when generating little endian code. We have already handled the
8545 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8546 // and ExtraLoad here.
8549 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8550 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8552 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8553 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8555 if (VT != MVT::v4i32)
8556 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8558 // The output of the permutation is our loaded result, the TokenFactor is
8560 DCI.CombineTo(N, Perm, TF);
8561 return SDValue(N, 0);
8565 case ISD::INTRINSIC_WO_CHAIN: {
8566 bool isLittleEndian = Subtarget.isLittleEndian();
8567 Intrinsic::ID Intr = (isLittleEndian ?
8568 Intrinsic::ppc_altivec_lvsr :
8569 Intrinsic::ppc_altivec_lvsl);
8570 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8571 N->getOperand(1)->getOpcode() == ISD::ADD) {
8572 SDValue Add = N->getOperand(1);
8574 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8575 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8576 Add.getValueType().getScalarType().getSizeInBits()))) {
8577 SDNode *BasePtr = Add->getOperand(0).getNode();
8578 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8579 UE = BasePtr->use_end(); UI != UE; ++UI) {
8580 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8581 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8583 // We've found another LVSL/LVSR, and this address is an aligned
8584 // multiple of that one. The results will be the same, so use the
8585 // one we've just found instead.
8587 return SDValue(*UI, 0);
8596 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8597 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8598 N->getOperand(0).hasOneUse() &&
8599 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8600 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8601 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8602 N->getValueType(0) == MVT::i64))) {
8603 SDValue Load = N->getOperand(0);
8604 LoadSDNode *LD = cast<LoadSDNode>(Load);
8605 // Create the byte-swapping load.
8607 LD->getChain(), // Chain
8608 LD->getBasePtr(), // Ptr
8609 DAG.getValueType(N->getValueType(0)) // VT
8612 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8613 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8614 MVT::i64 : MVT::i32, MVT::Other),
8615 Ops, LD->getMemoryVT(), LD->getMemOperand());
8617 // If this is an i16 load, insert the truncate.
8618 SDValue ResVal = BSLoad;
8619 if (N->getValueType(0) == MVT::i16)
8620 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8622 // First, combine the bswap away. This makes the value produced by the
8624 DCI.CombineTo(N, ResVal);
8626 // Next, combine the load away, we give it a bogus result value but a real
8627 // chain result. The result value is dead because the bswap is dead.
8628 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8630 // Return N so it doesn't get rechecked!
8631 return SDValue(N, 0);
8635 case PPCISD::VCMP: {
8636 // If a VCMPo node already exists with exactly the same operands as this
8637 // node, use its result instead of this node (VCMPo computes both a CR6 and
8638 // a normal output).
8640 if (!N->getOperand(0).hasOneUse() &&
8641 !N->getOperand(1).hasOneUse() &&
8642 !N->getOperand(2).hasOneUse()) {
8644 // Scan all of the users of the LHS, looking for VCMPo's that match.
8645 SDNode *VCMPoNode = nullptr;
8647 SDNode *LHSN = N->getOperand(0).getNode();
8648 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8650 if (UI->getOpcode() == PPCISD::VCMPo &&
8651 UI->getOperand(1) == N->getOperand(1) &&
8652 UI->getOperand(2) == N->getOperand(2) &&
8653 UI->getOperand(0) == N->getOperand(0)) {
8658 // If there is no VCMPo node, or if the flag value has a single use, don't
8660 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8663 // Look at the (necessarily single) use of the flag value. If it has a
8664 // chain, this transformation is more complex. Note that multiple things
8665 // could use the value result, which we should ignore.
8666 SDNode *FlagUser = nullptr;
8667 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8668 FlagUser == nullptr; ++UI) {
8669 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8671 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8672 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8679 // If the user is a MFOCRF instruction, we know this is safe.
8680 // Otherwise we give up for right now.
8681 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8682 return SDValue(VCMPoNode, 0);
8687 SDValue Cond = N->getOperand(1);
8688 SDValue Target = N->getOperand(2);
8690 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8691 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8692 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8694 // We now need to make the intrinsic dead (it cannot be instruction
8696 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8697 assert(Cond.getNode()->hasOneUse() &&
8698 "Counter decrement has more than one use");
8700 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8701 N->getOperand(0), Target);
8706 // If this is a branch on an altivec predicate comparison, lower this so
8707 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8708 // lowering is done pre-legalize, because the legalizer lowers the predicate
8709 // compare down to code that is difficult to reassemble.
8710 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8711 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8713 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8714 // value. If so, pass-through the AND to get to the intrinsic.
8715 if (LHS.getOpcode() == ISD::AND &&
8716 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8717 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8718 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8719 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8720 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8722 LHS = LHS.getOperand(0);
8724 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8725 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8726 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8727 isa<ConstantSDNode>(RHS)) {
8728 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8729 "Counter decrement comparison is not EQ or NE");
8731 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8732 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8733 (CC == ISD::SETNE && !Val);
8735 // We now need to make the intrinsic dead (it cannot be instruction
8737 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8738 assert(LHS.getNode()->hasOneUse() &&
8739 "Counter decrement has more than one use");
8741 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8742 N->getOperand(0), N->getOperand(4));
8748 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8749 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8750 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8751 assert(isDot && "Can't compare against a vector result!");
8753 // If this is a comparison against something other than 0/1, then we know
8754 // that the condition is never/always true.
8755 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8756 if (Val != 0 && Val != 1) {
8757 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8758 return N->getOperand(0);
8759 // Always !=, turn it into an unconditional branch.
8760 return DAG.getNode(ISD::BR, dl, MVT::Other,
8761 N->getOperand(0), N->getOperand(4));
8764 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8766 // Create the PPCISD altivec 'dot' comparison node.
8768 LHS.getOperand(2), // LHS of compare
8769 LHS.getOperand(3), // RHS of compare
8770 DAG.getConstant(CompareOpc, MVT::i32)
8772 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8773 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8775 // Unpack the result based on how the target uses it.
8776 PPC::Predicate CompOpc;
8777 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8778 default: // Can't happen, don't crash on invalid number though.
8779 case 0: // Branch on the value of the EQ bit of CR6.
8780 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8782 case 1: // Branch on the inverted value of the EQ bit of CR6.
8783 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8785 case 2: // Branch on the value of the LT bit of CR6.
8786 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8788 case 3: // Branch on the inverted value of the LT bit of CR6.
8789 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8793 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8794 DAG.getConstant(CompOpc, MVT::i32),
8795 DAG.getRegister(PPC::CR6, MVT::i32),
8796 N->getOperand(4), CompNode.getValue(1));
8805 //===----------------------------------------------------------------------===//
8806 // Inline Assembly Support
8807 //===----------------------------------------------------------------------===//
8809 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8812 const SelectionDAG &DAG,
8813 unsigned Depth) const {
8814 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8815 switch (Op.getOpcode()) {
8817 case PPCISD::LBRX: {
8818 // lhbrx is known to have the top bits cleared out.
8819 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8820 KnownZero = 0xFFFF0000;
8823 case ISD::INTRINSIC_WO_CHAIN: {
8824 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8826 case Intrinsic::ppc_altivec_vcmpbfp_p:
8827 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8828 case Intrinsic::ppc_altivec_vcmpequb_p:
8829 case Intrinsic::ppc_altivec_vcmpequh_p:
8830 case Intrinsic::ppc_altivec_vcmpequw_p:
8831 case Intrinsic::ppc_altivec_vcmpgefp_p:
8832 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8833 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8834 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8835 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8836 case Intrinsic::ppc_altivec_vcmpgtub_p:
8837 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8838 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8839 KnownZero = ~1U; // All bits but the low one are known to be zero.
8847 /// getConstraintType - Given a constraint, return the type of
8848 /// constraint it is for this target.
8849 PPCTargetLowering::ConstraintType
8850 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8851 if (Constraint.size() == 1) {
8852 switch (Constraint[0]) {
8859 return C_RegisterClass;
8861 // FIXME: While Z does indicate a memory constraint, it specifically
8862 // indicates an r+r address (used in conjunction with the 'y' modifier
8863 // in the replacement string). Currently, we're forcing the base
8864 // register to be r0 in the asm printer (which is interpreted as zero)
8865 // and forming the complete address in the second register. This is
8869 } else if (Constraint == "wc") { // individual CR bits.
8870 return C_RegisterClass;
8871 } else if (Constraint == "wa" || Constraint == "wd" ||
8872 Constraint == "wf" || Constraint == "ws") {
8873 return C_RegisterClass; // VSX registers.
8875 return TargetLowering::getConstraintType(Constraint);
8878 /// Examine constraint type and operand type and determine a weight value.
8879 /// This object must already have been set up with the operand type
8880 /// and the current alternative constraint selected.
8881 TargetLowering::ConstraintWeight
8882 PPCTargetLowering::getSingleConstraintMatchWeight(
8883 AsmOperandInfo &info, const char *constraint) const {
8884 ConstraintWeight weight = CW_Invalid;
8885 Value *CallOperandVal = info.CallOperandVal;
8886 // If we don't have a value, we can't do a match,
8887 // but allow it at the lowest weight.
8888 if (!CallOperandVal)
8890 Type *type = CallOperandVal->getType();
8892 // Look at the constraint type.
8893 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8894 return CW_Register; // an individual CR bit.
8895 else if ((StringRef(constraint) == "wa" ||
8896 StringRef(constraint) == "wd" ||
8897 StringRef(constraint) == "wf") &&
8900 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8903 switch (*constraint) {
8905 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8908 if (type->isIntegerTy())
8909 weight = CW_Register;
8912 if (type->isFloatTy())
8913 weight = CW_Register;
8916 if (type->isDoubleTy())
8917 weight = CW_Register;
8920 if (type->isVectorTy())
8921 weight = CW_Register;
8924 weight = CW_Register;
8933 std::pair<unsigned, const TargetRegisterClass*>
8934 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8936 if (Constraint.size() == 1) {
8937 // GCC RS6000 Constraint Letters
8938 switch (Constraint[0]) {
8940 if (VT == MVT::i64 && Subtarget.isPPC64())
8941 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8942 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8944 if (VT == MVT::i64 && Subtarget.isPPC64())
8945 return std::make_pair(0U, &PPC::G8RCRegClass);
8946 return std::make_pair(0U, &PPC::GPRCRegClass);
8948 if (VT == MVT::f32 || VT == MVT::i32)
8949 return std::make_pair(0U, &PPC::F4RCRegClass);
8950 if (VT == MVT::f64 || VT == MVT::i64)
8951 return std::make_pair(0U, &PPC::F8RCRegClass);
8954 return std::make_pair(0U, &PPC::VRRCRegClass);
8956 return std::make_pair(0U, &PPC::CRRCRegClass);
8958 } else if (Constraint == "wc") { // an individual CR bit.
8959 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8960 } else if (Constraint == "wa" || Constraint == "wd" ||
8961 Constraint == "wf") {
8962 return std::make_pair(0U, &PPC::VSRCRegClass);
8963 } else if (Constraint == "ws") {
8964 return std::make_pair(0U, &PPC::VSFRCRegClass);
8967 std::pair<unsigned, const TargetRegisterClass*> R =
8968 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8970 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8971 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8972 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8974 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8975 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8976 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
8977 PPC::GPRCRegClass.contains(R.first)) {
8978 const TargetRegisterInfo *TRI =
8979 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
8980 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8981 PPC::sub_32, &PPC::G8RCRegClass),
8982 &PPC::G8RCRegClass);
8989 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8990 /// vector. If it is invalid, don't add anything to Ops.
8991 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8992 std::string &Constraint,
8993 std::vector<SDValue>&Ops,
8994 SelectionDAG &DAG) const {
8997 // Only support length 1 constraints.
8998 if (Constraint.length() > 1) return;
9000 char Letter = Constraint[0];
9011 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
9012 if (!CST) return; // Must be an immediate to match.
9013 unsigned Value = CST->getZExtValue();
9015 default: llvm_unreachable("Unknown constraint letter!");
9016 case 'I': // "I" is a signed 16-bit constant.
9017 if ((short)Value == (int)Value)
9018 Result = DAG.getTargetConstant(Value, Op.getValueType());
9020 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
9021 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
9022 if ((short)Value == 0)
9023 Result = DAG.getTargetConstant(Value, Op.getValueType());
9025 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
9026 if ((Value >> 16) == 0)
9027 Result = DAG.getTargetConstant(Value, Op.getValueType());
9029 case 'M': // "M" is a constant that is greater than 31.
9031 Result = DAG.getTargetConstant(Value, Op.getValueType());
9033 case 'N': // "N" is a positive constant that is an exact power of two.
9034 if ((int)Value > 0 && isPowerOf2_32(Value))
9035 Result = DAG.getTargetConstant(Value, Op.getValueType());
9037 case 'O': // "O" is the constant zero.
9039 Result = DAG.getTargetConstant(Value, Op.getValueType());
9041 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
9042 if ((short)-Value == (int)-Value)
9043 Result = DAG.getTargetConstant(Value, Op.getValueType());
9050 if (Result.getNode()) {
9051 Ops.push_back(Result);
9055 // Handle standard constraint letters.
9056 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9059 // isLegalAddressingMode - Return true if the addressing mode represented
9060 // by AM is legal for this target, for a load/store of the specified type.
9061 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9063 // FIXME: PPC does not allow r+i addressing modes for vectors!
9065 // PPC allows a sign-extended 16-bit immediate field.
9066 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
9069 // No global is ever allowed as a base.
9073 // PPC only support r+r,
9075 case 0: // "r+i" or just "i", depending on HasBaseReg.
9078 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9080 // Otherwise we have r+r or r+i.
9083 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9085 // Allow 2*r as r+r.
9088 // No other scales are supported.
9095 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
9096 SelectionDAG &DAG) const {
9097 MachineFunction &MF = DAG.getMachineFunction();
9098 MachineFrameInfo *MFI = MF.getFrameInfo();
9099 MFI->setReturnAddressIsTaken(true);
9101 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9105 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9107 // Make sure the function does not optimize away the store of the RA to
9109 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9110 FuncInfo->setLRStoreRequired();
9111 bool isPPC64 = Subtarget.isPPC64();
9112 bool isDarwinABI = Subtarget.isDarwinABI();
9115 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9118 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
9119 isPPC64? MVT::i64 : MVT::i32);
9120 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9121 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9123 MachinePointerInfo(), false, false, false, 0);
9126 // Just load the return address off the stack.
9127 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9128 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9129 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9132 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9133 SelectionDAG &DAG) const {
9135 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9137 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9138 bool isPPC64 = PtrVT == MVT::i64;
9140 MachineFunction &MF = DAG.getMachineFunction();
9141 MachineFrameInfo *MFI = MF.getFrameInfo();
9142 MFI->setFrameAddressIsTaken(true);
9144 // Naked functions never have a frame pointer, and so we use r1. For all
9145 // other functions, this decision must be delayed until during PEI.
9147 if (MF.getFunction()->getAttributes().hasAttribute(
9148 AttributeSet::FunctionIndex, Attribute::Naked))
9149 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9151 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9153 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9156 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9157 FrameAddr, MachinePointerInfo(), false, false,
9162 // FIXME? Maybe this could be a TableGen attribute on some registers and
9163 // this table could be generated automatically from RegInfo.
9164 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9166 bool isPPC64 = Subtarget.isPPC64();
9167 bool isDarwinABI = Subtarget.isDarwinABI();
9169 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9170 (!isPPC64 && VT != MVT::i32))
9171 report_fatal_error("Invalid register global variable type");
9173 bool is64Bit = isPPC64 && VT == MVT::i64;
9174 unsigned Reg = StringSwitch<unsigned>(RegName)
9175 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9176 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
9177 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9178 (is64Bit ? PPC::X13 : PPC::R13))
9183 report_fatal_error("Invalid register name global variable");
9187 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9188 // The PowerPC target isn't yet aware of offsets.
9192 /// getOptimalMemOpType - Returns the target specific optimal type for load
9193 /// and store operations as a result of memset, memcpy, and memmove
9194 /// lowering. If DstAlign is zero that means it's safe to destination
9195 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9196 /// means there isn't a need to check it against alignment requirement,
9197 /// probably because the source does not need to be loaded. If 'IsMemset' is
9198 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9199 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9200 /// source is constant so it does not need to be loaded.
9201 /// It returns EVT::Other if the type should be determined using generic
9202 /// target-independent logic.
9203 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9204 unsigned DstAlign, unsigned SrcAlign,
9205 bool IsMemset, bool ZeroMemset,
9207 MachineFunction &MF) const {
9208 if (Subtarget.isPPC64()) {
9215 /// \brief Returns true if it is beneficial to convert a load of a constant
9216 /// to just the constant itself.
9217 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9219 assert(Ty->isIntegerTy());
9221 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9222 if (BitSize == 0 || BitSize > 64)
9227 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9228 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9230 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9231 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9232 return NumBits1 == 64 && NumBits2 == 32;
9235 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9236 if (!VT1.isInteger() || !VT2.isInteger())
9238 unsigned NumBits1 = VT1.getSizeInBits();
9239 unsigned NumBits2 = VT2.getSizeInBits();
9240 return NumBits1 == 64 && NumBits2 == 32;
9243 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9244 return isInt<16>(Imm) || isUInt<16>(Imm);
9247 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9248 return isInt<16>(Imm) || isUInt<16>(Imm);
9251 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9255 if (DisablePPCUnaligned)
9258 // PowerPC supports unaligned memory access for simple non-vector types.
9259 // Although accessing unaligned addresses is not as efficient as accessing
9260 // aligned addresses, it is generally more efficient than manual expansion,
9261 // and generally only traps for software emulation when crossing page
9267 if (VT.getSimpleVT().isVector()) {
9268 if (Subtarget.hasVSX()) {
9269 if (VT != MVT::v2f64 && VT != MVT::v2i64)
9276 if (VT == MVT::ppcf128)
9285 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9286 VT = VT.getScalarType();
9291 switch (VT.getSimpleVT().SimpleTy) {
9303 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
9304 EVT VT , unsigned DefinedValues) const {
9305 if (VT == MVT::v2i64)
9308 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9311 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9312 if (DisableILPPref || Subtarget.enableMachineScheduler())
9313 return TargetLowering::getSchedulingPreference(N);
9318 // Create a fast isel object.
9320 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9321 const TargetLibraryInfo *LibInfo) const {
9322 return PPC::createFastISel(FuncInfo, LibInfo);