1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
45 // FIXME: Remove this once soft-float is supported.
46 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
47 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
49 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
50 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
52 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
53 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
55 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
56 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
58 // FIXME: Remove this once the bug has been fixed!
59 extern cl::opt<bool> ANDIGlueBug;
61 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
62 const PPCSubtarget &STI)
63 : TargetLowering(TM), Subtarget(STI) {
64 // Use _setjmp/_longjmp instead of setjmp/longjmp.
65 setUseUnderscoreSetJmp(true);
66 setUseUnderscoreLongJmp(true);
68 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
69 // arguments are at least 4/8 bytes aligned.
70 bool isPPC64 = Subtarget.isPPC64();
71 setMinStackArgumentAlignment(isPPC64 ? 8:4);
73 // Set up the register classes.
74 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
75 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
76 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
78 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
79 for (MVT VT : MVT::integer_valuetypes()) {
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
84 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
86 // PowerPC has pre-inc load and store's.
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
102 if (Subtarget.useCRBits()) {
103 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
105 if (isPPC64 || Subtarget.hasFPCVT()) {
106 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
107 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
108 isPPC64 ? MVT::i64 : MVT::i32);
109 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
110 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
111 isPPC64 ? MVT::i64 : MVT::i32);
113 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
114 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
117 // PowerPC does not support direct load / store of condition registers
118 setOperationAction(ISD::LOAD, MVT::i1, Custom);
119 setOperationAction(ISD::STORE, MVT::i1, Custom);
121 // FIXME: Remove this once the ANDI glue bug is fixed:
123 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
125 for (MVT VT : MVT::integer_valuetypes()) {
126 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
127 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
128 setTruncStoreAction(VT, MVT::i1, Expand);
131 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
134 // This is used in the ppcf128->int sequence. Note it has different semantics
135 // from FP_ROUND: that rounds to nearest, this rounds to zero.
136 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
138 // We do not currently implement these libm ops for PowerPC.
139 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
144 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
146 // PowerPC has no SREM/UREM instructions
147 setOperationAction(ISD::SREM, MVT::i32, Expand);
148 setOperationAction(ISD::UREM, MVT::i32, Expand);
149 setOperationAction(ISD::SREM, MVT::i64, Expand);
150 setOperationAction(ISD::UREM, MVT::i64, Expand);
152 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
153 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
155 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
157 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
159 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
160 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
162 // We don't support sin/cos/sqrt/fmod/pow
163 setOperationAction(ISD::FSIN , MVT::f64, Expand);
164 setOperationAction(ISD::FCOS , MVT::f64, Expand);
165 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
166 setOperationAction(ISD::FREM , MVT::f64, Expand);
167 setOperationAction(ISD::FPOW , MVT::f64, Expand);
168 setOperationAction(ISD::FMA , MVT::f64, Legal);
169 setOperationAction(ISD::FSIN , MVT::f32, Expand);
170 setOperationAction(ISD::FCOS , MVT::f32, Expand);
171 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
172 setOperationAction(ISD::FREM , MVT::f32, Expand);
173 setOperationAction(ISD::FPOW , MVT::f32, Expand);
174 setOperationAction(ISD::FMA , MVT::f32, Legal);
176 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
178 // If we're enabling GP optimizations, use hardware square root
179 if (!Subtarget.hasFSQRT() &&
180 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
182 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
184 if (!Subtarget.hasFSQRT() &&
185 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
186 Subtarget.hasFRES()))
187 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
189 if (Subtarget.hasFCPSGN()) {
190 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
191 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
194 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
197 if (Subtarget.hasFPRND()) {
198 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
199 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
200 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
201 setOperationAction(ISD::FROUND, MVT::f64, Legal);
203 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
204 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
205 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
206 setOperationAction(ISD::FROUND, MVT::f32, Legal);
209 // PowerPC does not have BSWAP, CTPOP or CTTZ
210 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
212 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
214 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
216 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
217 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
219 if (Subtarget.hasPOPCNTD()) {
220 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
221 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
223 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
224 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
227 // PowerPC does not have ROTR
228 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
229 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
231 if (!Subtarget.useCRBits()) {
232 // PowerPC does not have Select
233 setOperationAction(ISD::SELECT, MVT::i32, Expand);
234 setOperationAction(ISD::SELECT, MVT::i64, Expand);
235 setOperationAction(ISD::SELECT, MVT::f32, Expand);
236 setOperationAction(ISD::SELECT, MVT::f64, Expand);
239 // PowerPC wants to turn select_cc of FP into fsel when possible.
240 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
241 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
243 // PowerPC wants to optimize integer setcc a bit
244 if (!Subtarget.useCRBits())
245 setOperationAction(ISD::SETCC, MVT::i32, Custom);
247 // PowerPC does not have BRCOND which requires SetCC
248 if (!Subtarget.useCRBits())
249 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
251 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
253 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
254 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
256 // PowerPC does not have [U|S]INT_TO_FP
257 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
258 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
262 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
263 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
265 // We cannot sextinreg(i1). Expand to shifts.
266 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
268 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
269 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
270 // support continuation, user-level threading, and etc.. As a result, no
271 // other SjLj exception interfaces are implemented and please don't build
272 // your own exception handling based on them.
273 // LLVM/Clang supports zero-cost DWARF exception handling.
274 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
275 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
277 // We want to legalize GlobalAddress and ConstantPool nodes into the
278 // appropriate instructions to materialize the address.
279 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
280 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
281 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
282 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
283 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
284 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
285 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
286 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
287 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
288 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
291 setOperationAction(ISD::TRAP, MVT::Other, Legal);
293 // TRAMPOLINE is custom lowered.
294 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
295 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
297 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
298 setOperationAction(ISD::VASTART , MVT::Other, Custom);
300 if (Subtarget.isSVR4ABI()) {
302 // VAARG always uses double-word chunks, so promote anything smaller.
303 setOperationAction(ISD::VAARG, MVT::i1, Promote);
304 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
305 setOperationAction(ISD::VAARG, MVT::i8, Promote);
306 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
307 setOperationAction(ISD::VAARG, MVT::i16, Promote);
308 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
309 setOperationAction(ISD::VAARG, MVT::i32, Promote);
310 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
311 setOperationAction(ISD::VAARG, MVT::Other, Expand);
313 // VAARG is custom lowered with the 32-bit SVR4 ABI.
314 setOperationAction(ISD::VAARG, MVT::Other, Custom);
315 setOperationAction(ISD::VAARG, MVT::i64, Custom);
318 setOperationAction(ISD::VAARG, MVT::Other, Expand);
320 if (Subtarget.isSVR4ABI() && !isPPC64)
321 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
322 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
324 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
326 // Use the default implementation.
327 setOperationAction(ISD::VAEND , MVT::Other, Expand);
328 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
329 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
331 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
333 // We want to custom lower some of our intrinsics.
334 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
336 // To handle counter-based loop conditions.
337 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
339 // Comparisons that require checking two conditions.
340 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
341 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
343 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
345 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
347 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
349 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
351 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
353 if (Subtarget.has64BitSupport()) {
354 // They also have instructions for converting between i64 and fp.
355 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
356 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
357 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
358 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
359 // This is just the low 32 bits of a (signed) fp->i64 conversion.
360 // We cannot do this with Promote because i64 is not a legal type.
361 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
363 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
364 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
366 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
367 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
370 // With the instructions enabled under FPCVT, we can do everything.
371 if (Subtarget.hasFPCVT()) {
372 if (Subtarget.has64BitSupport()) {
373 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
374 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
375 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
376 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
379 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
380 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
381 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
382 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
385 if (Subtarget.use64BitRegs()) {
386 // 64-bit PowerPC implementations can support i64 types directly
387 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
388 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
389 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
390 // 64-bit PowerPC wants to expand i128 shifts itself.
391 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
393 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
395 // 32-bit PowerPC wants to expand i64 shifts itself.
396 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
398 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
401 if (Subtarget.hasAltivec()) {
402 // First set operation action for all vector types to expand. Then we
403 // will selectively turn on ones that can be effectively codegen'd.
404 for (MVT VT : MVT::vector_valuetypes()) {
405 // add/sub are legal for all supported vector VT's.
406 setOperationAction(ISD::ADD, VT, Legal);
407 setOperationAction(ISD::SUB, VT, Legal);
409 // Vector instructions introduced in P8
410 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
411 setOperationAction(ISD::CTPOP, VT, Legal);
412 setOperationAction(ISD::CTLZ, VT, Legal);
415 setOperationAction(ISD::CTPOP, VT, Expand);
416 setOperationAction(ISD::CTLZ, VT, Expand);
419 // We promote all shuffles to v16i8.
420 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
421 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
423 // We promote all non-typed operations to v4i32.
424 setOperationAction(ISD::AND , VT, Promote);
425 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
426 setOperationAction(ISD::OR , VT, Promote);
427 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
428 setOperationAction(ISD::XOR , VT, Promote);
429 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
430 setOperationAction(ISD::LOAD , VT, Promote);
431 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
432 setOperationAction(ISD::SELECT, VT, Promote);
433 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
434 setOperationAction(ISD::SELECT_CC, VT, Promote);
435 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
436 setOperationAction(ISD::STORE, VT, Promote);
437 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
439 // No other operations are legal.
440 setOperationAction(ISD::MUL , VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::SREM, VT, Expand);
443 setOperationAction(ISD::UDIV, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
445 setOperationAction(ISD::FDIV, VT, Expand);
446 setOperationAction(ISD::FREM, VT, Expand);
447 setOperationAction(ISD::FNEG, VT, Expand);
448 setOperationAction(ISD::FSQRT, VT, Expand);
449 setOperationAction(ISD::FLOG, VT, Expand);
450 setOperationAction(ISD::FLOG10, VT, Expand);
451 setOperationAction(ISD::FLOG2, VT, Expand);
452 setOperationAction(ISD::FEXP, VT, Expand);
453 setOperationAction(ISD::FEXP2, VT, Expand);
454 setOperationAction(ISD::FSIN, VT, Expand);
455 setOperationAction(ISD::FCOS, VT, Expand);
456 setOperationAction(ISD::FABS, VT, Expand);
457 setOperationAction(ISD::FPOWI, VT, Expand);
458 setOperationAction(ISD::FFLOOR, VT, Expand);
459 setOperationAction(ISD::FCEIL, VT, Expand);
460 setOperationAction(ISD::FTRUNC, VT, Expand);
461 setOperationAction(ISD::FRINT, VT, Expand);
462 setOperationAction(ISD::FNEARBYINT, VT, Expand);
463 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
464 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
465 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
466 setOperationAction(ISD::MULHU, VT, Expand);
467 setOperationAction(ISD::MULHS, VT, Expand);
468 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
469 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
470 setOperationAction(ISD::UDIVREM, VT, Expand);
471 setOperationAction(ISD::SDIVREM, VT, Expand);
472 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
473 setOperationAction(ISD::FPOW, VT, Expand);
474 setOperationAction(ISD::BSWAP, VT, Expand);
475 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
476 setOperationAction(ISD::CTTZ, VT, Expand);
477 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
478 setOperationAction(ISD::VSELECT, VT, Expand);
479 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
481 for (MVT InnerVT : MVT::vector_valuetypes()) {
482 setTruncStoreAction(VT, InnerVT, Expand);
483 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
484 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
485 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
489 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
490 // with merges, splats, etc.
491 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
493 setOperationAction(ISD::AND , MVT::v4i32, Legal);
494 setOperationAction(ISD::OR , MVT::v4i32, Legal);
495 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
496 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
497 setOperationAction(ISD::SELECT, MVT::v4i32,
498 Subtarget.useCRBits() ? Legal : Expand);
499 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
500 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
501 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
502 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
503 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
504 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
505 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
506 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
507 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
509 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
510 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
511 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
512 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
514 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
515 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
517 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
518 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
519 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
522 if (Subtarget.hasP8Altivec())
523 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
525 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
527 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
528 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
530 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
531 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
533 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
534 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
535 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
536 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
538 // Altivec does not contain unordered floating-point compare instructions
539 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
540 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
541 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
542 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
544 if (Subtarget.hasVSX()) {
545 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
546 if (Subtarget.hasP8Vector())
547 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
548 if (Subtarget.hasDirectMove()) {
549 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
550 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
551 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
552 // FIXME: this is causing bootstrap failures, disable temporarily
553 //setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
555 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
557 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
558 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
559 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
560 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
561 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
563 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
565 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
566 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
568 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
569 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
571 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
572 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
573 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
574 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
575 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
577 // Share the Altivec comparison restrictions.
578 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
579 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
580 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
581 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
583 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
584 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
586 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
588 if (Subtarget.hasP8Vector())
589 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
591 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
593 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
594 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
595 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
597 if (Subtarget.hasP8Altivec()) {
598 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
599 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
600 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
602 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
605 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
606 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
607 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
609 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
611 // VSX v2i64 only supports non-arithmetic operations.
612 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
613 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
616 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
617 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
618 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
619 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
621 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
623 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
624 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
625 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
626 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
628 // Vector operation legalization checks the result type of
629 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
630 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
631 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
632 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
633 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
635 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
638 if (Subtarget.hasP8Altivec()) {
639 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
640 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
644 if (Subtarget.hasQPX()) {
645 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
646 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
647 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
648 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
650 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
651 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand);
653 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
654 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
656 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
657 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
659 if (!Subtarget.useCRBits())
660 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
661 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
663 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);
664 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
665 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
666 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
667 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
668 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
669 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
671 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
672 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
674 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
675 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
676 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
678 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
679 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
680 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
681 setOperationAction(ISD::FCOS , MVT::v4f64, Expand);
682 setOperationAction(ISD::FPOWI , MVT::v4f64, Expand);
683 setOperationAction(ISD::FPOW , MVT::v4f64, Expand);
684 setOperationAction(ISD::FLOG , MVT::v4f64, Expand);
685 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
686 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand);
687 setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
688 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
690 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
691 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
693 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
694 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
696 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
698 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
699 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
700 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
701 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
703 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
704 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
706 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
707 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
709 if (!Subtarget.useCRBits())
710 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
711 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
713 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
714 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
715 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
716 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
717 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
718 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
719 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
721 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
722 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
724 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
725 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
726 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
727 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
728 setOperationAction(ISD::FPOWI , MVT::v4f32, Expand);
729 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
730 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
731 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
732 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
733 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
734 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
736 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
737 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
739 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
740 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
742 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
744 setOperationAction(ISD::AND , MVT::v4i1, Legal);
745 setOperationAction(ISD::OR , MVT::v4i1, Legal);
746 setOperationAction(ISD::XOR , MVT::v4i1, Legal);
748 if (!Subtarget.useCRBits())
749 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
750 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
752 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
753 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
755 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);
756 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
757 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
758 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand);
759 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
760 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
761 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
763 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
764 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
766 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
768 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
769 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
770 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
771 setOperationAction(ISD::FROUND, MVT::v4f64, Legal);
773 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
774 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
775 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
776 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
778 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
779 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
781 // These need to set FE_INEXACT, and so cannot be vectorized here.
782 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
783 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
785 if (TM.Options.UnsafeFPMath) {
786 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
787 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
789 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
790 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
792 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
793 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
795 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
796 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
800 if (Subtarget.has64BitSupport())
801 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
803 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
806 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
807 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
810 setBooleanContents(ZeroOrOneBooleanContent);
812 if (Subtarget.hasAltivec()) {
813 // Altivec instructions set fields to all zeros or all ones.
814 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
818 // These libcalls are not available in 32-bit.
819 setLibcallName(RTLIB::SHL_I128, nullptr);
820 setLibcallName(RTLIB::SRL_I128, nullptr);
821 setLibcallName(RTLIB::SRA_I128, nullptr);
825 setStackPointerRegisterToSaveRestore(PPC::X1);
826 setExceptionPointerRegister(PPC::X3);
827 setExceptionSelectorRegister(PPC::X4);
829 setStackPointerRegisterToSaveRestore(PPC::R1);
830 setExceptionPointerRegister(PPC::R3);
831 setExceptionSelectorRegister(PPC::R4);
834 // We have target-specific dag combine patterns for the following nodes:
835 setTargetDAGCombine(ISD::SINT_TO_FP);
836 if (Subtarget.hasFPCVT())
837 setTargetDAGCombine(ISD::UINT_TO_FP);
838 setTargetDAGCombine(ISD::LOAD);
839 setTargetDAGCombine(ISD::STORE);
840 setTargetDAGCombine(ISD::BR_CC);
841 if (Subtarget.useCRBits())
842 setTargetDAGCombine(ISD::BRCOND);
843 setTargetDAGCombine(ISD::BSWAP);
844 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
845 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
846 setTargetDAGCombine(ISD::INTRINSIC_VOID);
848 setTargetDAGCombine(ISD::SIGN_EXTEND);
849 setTargetDAGCombine(ISD::ZERO_EXTEND);
850 setTargetDAGCombine(ISD::ANY_EXTEND);
852 if (Subtarget.useCRBits()) {
853 setTargetDAGCombine(ISD::TRUNCATE);
854 setTargetDAGCombine(ISD::SETCC);
855 setTargetDAGCombine(ISD::SELECT_CC);
858 // Use reciprocal estimates.
859 if (TM.Options.UnsafeFPMath) {
860 setTargetDAGCombine(ISD::FDIV);
861 setTargetDAGCombine(ISD::FSQRT);
864 // Darwin long double math library functions have $LDBL128 appended.
865 if (Subtarget.isDarwin()) {
866 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
867 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
868 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
869 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
870 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
871 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
872 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
873 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
874 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
875 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
878 // With 32 condition bits, we don't need to sink (and duplicate) compares
879 // aggressively in CodeGenPrep.
880 if (Subtarget.useCRBits()) {
881 setHasMultipleConditionRegisters();
882 setJumpIsExpensive();
885 setMinFunctionAlignment(2);
886 if (Subtarget.isDarwin())
887 setPrefFunctionAlignment(4);
889 switch (Subtarget.getDarwinDirective()) {
893 case PPC::DIR_E500mc:
902 setPrefFunctionAlignment(4);
903 setPrefLoopAlignment(4);
907 setInsertFencesForAtomic(true);
909 if (Subtarget.enableMachineScheduler())
910 setSchedulingPreference(Sched::Source);
912 setSchedulingPreference(Sched::Hybrid);
914 computeRegisterProperties(STI.getRegisterInfo());
916 // The Freescale cores do better with aggressive inlining of memcpy and
917 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
918 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
919 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
920 MaxStoresPerMemset = 32;
921 MaxStoresPerMemsetOptSize = 16;
922 MaxStoresPerMemcpy = 32;
923 MaxStoresPerMemcpyOptSize = 8;
924 MaxStoresPerMemmove = 32;
925 MaxStoresPerMemmoveOptSize = 8;
926 } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) {
927 // The A2 also benefits from (very) aggressive inlining of memcpy and
928 // friends. The overhead of a the function call, even when warm, can be
929 // over one hundred cycles.
930 MaxStoresPerMemset = 128;
931 MaxStoresPerMemcpy = 128;
932 MaxStoresPerMemmove = 128;
936 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
937 /// the desired ByVal argument alignment.
938 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
939 unsigned MaxMaxAlign) {
940 if (MaxAlign == MaxMaxAlign)
942 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
943 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
945 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
947 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
948 unsigned EltAlign = 0;
949 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
950 if (EltAlign > MaxAlign)
952 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
953 for (auto *EltTy : STy->elements()) {
954 unsigned EltAlign = 0;
955 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
956 if (EltAlign > MaxAlign)
958 if (MaxAlign == MaxMaxAlign)
964 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
965 /// function arguments in the caller parameter area.
966 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
967 const DataLayout &DL) const {
968 // Darwin passes everything on 4 byte boundary.
969 if (Subtarget.isDarwin())
972 // 16byte and wider vectors are passed on 16byte boundary.
973 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
974 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
975 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
976 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
980 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
981 switch ((PPCISD::NodeType)Opcode) {
982 case PPCISD::FIRST_NUMBER: break;
983 case PPCISD::FSEL: return "PPCISD::FSEL";
984 case PPCISD::FCFID: return "PPCISD::FCFID";
985 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
986 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
987 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
988 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
989 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
990 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
991 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
992 case PPCISD::FRE: return "PPCISD::FRE";
993 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
994 case PPCISD::STFIWX: return "PPCISD::STFIWX";
995 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
996 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
997 case PPCISD::VPERM: return "PPCISD::VPERM";
998 case PPCISD::CMPB: return "PPCISD::CMPB";
999 case PPCISD::Hi: return "PPCISD::Hi";
1000 case PPCISD::Lo: return "PPCISD::Lo";
1001 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1002 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1003 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1004 case PPCISD::SRL: return "PPCISD::SRL";
1005 case PPCISD::SRA: return "PPCISD::SRA";
1006 case PPCISD::SHL: return "PPCISD::SHL";
1007 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1008 case PPCISD::CALL: return "PPCISD::CALL";
1009 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1010 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1011 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1012 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1013 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1014 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1015 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1016 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1017 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1018 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1019 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1020 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1021 case PPCISD::ANDIo_1_EQ_BIT: return "PPCISD::ANDIo_1_EQ_BIT";
1022 case PPCISD::ANDIo_1_GT_BIT: return "PPCISD::ANDIo_1_GT_BIT";
1023 case PPCISD::VCMP: return "PPCISD::VCMP";
1024 case PPCISD::VCMPo: return "PPCISD::VCMPo";
1025 case PPCISD::LBRX: return "PPCISD::LBRX";
1026 case PPCISD::STBRX: return "PPCISD::STBRX";
1027 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1028 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1029 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1030 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1031 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1032 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1033 case PPCISD::BDZ: return "PPCISD::BDZ";
1034 case PPCISD::MFFS: return "PPCISD::MFFS";
1035 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1036 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1037 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1038 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1039 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1040 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1041 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1042 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1043 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1044 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1045 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1046 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1047 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1048 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1049 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1050 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1051 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1052 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1053 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1054 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1055 case PPCISD::SC: return "PPCISD::SC";
1056 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1057 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1058 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1059 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1060 case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1061 case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1062 case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1063 case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1064 case PPCISD::QBFLT: return "PPCISD::QBFLT";
1065 case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1070 EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1073 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1075 if (Subtarget.hasQPX())
1076 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
1078 return VT.changeVectorElementTypeToInteger();
1081 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1082 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1086 //===----------------------------------------------------------------------===//
1087 // Node matching predicates, for use by the tblgen matching code.
1088 //===----------------------------------------------------------------------===//
1090 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1091 static bool isFloatingPointZero(SDValue Op) {
1092 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1093 return CFP->getValueAPF().isZero();
1094 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1095 // Maybe this has already been legalized into the constant pool?
1096 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1097 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1098 return CFP->getValueAPF().isZero();
1103 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1104 /// true if Op is undef or if it matches the specified value.
1105 static bool isConstantOrUndef(int Op, int Val) {
1106 return Op < 0 || Op == Val;
1109 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1110 /// VPKUHUM instruction.
1111 /// The ShuffleKind distinguishes between big-endian operations with
1112 /// two different inputs (0), either-endian operations with two identical
1113 /// inputs (1), and little-endian operations with two different inputs (2).
1114 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1115 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1116 SelectionDAG &DAG) {
1117 bool IsLE = DAG.getDataLayout().isLittleEndian();
1118 if (ShuffleKind == 0) {
1121 for (unsigned i = 0; i != 16; ++i)
1122 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1124 } else if (ShuffleKind == 2) {
1127 for (unsigned i = 0; i != 16; ++i)
1128 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1130 } else if (ShuffleKind == 1) {
1131 unsigned j = IsLE ? 0 : 1;
1132 for (unsigned i = 0; i != 8; ++i)
1133 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1134 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1140 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1141 /// VPKUWUM instruction.
1142 /// The ShuffleKind distinguishes between big-endian operations with
1143 /// two different inputs (0), either-endian operations with two identical
1144 /// inputs (1), and little-endian operations with two different inputs (2).
1145 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1146 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1147 SelectionDAG &DAG) {
1148 bool IsLE = DAG.getDataLayout().isLittleEndian();
1149 if (ShuffleKind == 0) {
1152 for (unsigned i = 0; i != 16; i += 2)
1153 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1154 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1156 } else if (ShuffleKind == 2) {
1159 for (unsigned i = 0; i != 16; i += 2)
1160 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1161 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1163 } else if (ShuffleKind == 1) {
1164 unsigned j = IsLE ? 0 : 2;
1165 for (unsigned i = 0; i != 8; i += 2)
1166 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1167 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1168 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1169 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1175 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1176 /// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1177 /// current subtarget.
1179 /// The ShuffleKind distinguishes between big-endian operations with
1180 /// two different inputs (0), either-endian operations with two identical
1181 /// inputs (1), and little-endian operations with two different inputs (2).
1182 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1183 bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1184 SelectionDAG &DAG) {
1185 const PPCSubtarget& Subtarget =
1186 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1187 if (!Subtarget.hasP8Vector())
1190 bool IsLE = DAG.getDataLayout().isLittleEndian();
1191 if (ShuffleKind == 0) {
1194 for (unsigned i = 0; i != 16; i += 4)
1195 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1196 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1197 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1198 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1200 } else if (ShuffleKind == 2) {
1203 for (unsigned i = 0; i != 16; i += 4)
1204 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1205 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1206 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1207 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1209 } else if (ShuffleKind == 1) {
1210 unsigned j = IsLE ? 0 : 4;
1211 for (unsigned i = 0; i != 8; i += 4)
1212 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1213 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1214 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1215 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1216 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1217 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1218 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1219 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1225 /// isVMerge - Common function, used to match vmrg* shuffles.
1227 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1228 unsigned LHSStart, unsigned RHSStart) {
1229 if (N->getValueType(0) != MVT::v16i8)
1231 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1232 "Unsupported merge size!");
1234 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1235 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1236 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1237 LHSStart+j+i*UnitSize) ||
1238 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1239 RHSStart+j+i*UnitSize))
1245 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1246 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1247 /// The ShuffleKind distinguishes between big-endian merges with two
1248 /// different inputs (0), either-endian merges with two identical inputs (1),
1249 /// and little-endian merges with two different inputs (2). For the latter,
1250 /// the input operands are swapped (see PPCInstrAltivec.td).
1251 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1252 unsigned ShuffleKind, SelectionDAG &DAG) {
1253 if (DAG.getDataLayout().isLittleEndian()) {
1254 if (ShuffleKind == 1) // unary
1255 return isVMerge(N, UnitSize, 0, 0);
1256 else if (ShuffleKind == 2) // swapped
1257 return isVMerge(N, UnitSize, 0, 16);
1261 if (ShuffleKind == 1) // unary
1262 return isVMerge(N, UnitSize, 8, 8);
1263 else if (ShuffleKind == 0) // normal
1264 return isVMerge(N, UnitSize, 8, 24);
1270 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1271 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1272 /// The ShuffleKind distinguishes between big-endian merges with two
1273 /// different inputs (0), either-endian merges with two identical inputs (1),
1274 /// and little-endian merges with two different inputs (2). For the latter,
1275 /// the input operands are swapped (see PPCInstrAltivec.td).
1276 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1277 unsigned ShuffleKind, SelectionDAG &DAG) {
1278 if (DAG.getDataLayout().isLittleEndian()) {
1279 if (ShuffleKind == 1) // unary
1280 return isVMerge(N, UnitSize, 8, 8);
1281 else if (ShuffleKind == 2) // swapped
1282 return isVMerge(N, UnitSize, 8, 24);
1286 if (ShuffleKind == 1) // unary
1287 return isVMerge(N, UnitSize, 0, 0);
1288 else if (ShuffleKind == 0) // normal
1289 return isVMerge(N, UnitSize, 0, 16);
1296 * \brief Common function used to match vmrgew and vmrgow shuffles
1298 * The indexOffset determines whether to look for even or odd words in
1299 * the shuffle mask. This is based on the of the endianness of the target
1302 * - Use offset of 0 to check for odd elements
1303 * - Use offset of 4 to check for even elements
1305 * - Use offset of 0 to check for even elements
1306 * - Use offset of 4 to check for odd elements
1307 * A detailed description of the vector element ordering for little endian and
1308 * big endian can be found at
1309 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1310 * Targeting your applications - what little endian and big endian IBM XL C/C++
1311 * compiler differences mean to you
1313 * The mask to the shuffle vector instruction specifies the indices of the
1314 * elements from the two input vectors to place in the result. The elements are
1315 * numbered in array-access order, starting with the first vector. These vectors
1316 * are always of type v16i8, thus each vector will contain 16 elements of size
1317 * 8. More info on the shuffle vector can be found in the
1318 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1319 * Language Reference.
1321 * The RHSStartValue indicates whether the same input vectors are used (unary)
1322 * or two different input vectors are used, based on the following:
1323 * - If the instruction uses the same vector for both inputs, the range of the
1324 * indices will be 0 to 15. In this case, the RHSStart value passed should
1326 * - If the instruction has two different vectors then the range of the
1327 * indices will be 0 to 31. In this case, the RHSStart value passed should
1328 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1329 * to 31 specify elements in the second vector).
1331 * \param[in] N The shuffle vector SD Node to analyze
1332 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1333 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1334 * vector to the shuffle_vector instruction
1335 * \return true iff this shuffle vector represents an even or odd word merge
1337 static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1338 unsigned RHSStartValue) {
1339 if (N->getValueType(0) != MVT::v16i8)
1342 for (unsigned i = 0; i < 2; ++i)
1343 for (unsigned j = 0; j < 4; ++j)
1344 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1345 i*RHSStartValue+j+IndexOffset) ||
1346 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1347 i*RHSStartValue+j+IndexOffset+8))
1353 * \brief Determine if the specified shuffle mask is suitable for the vmrgew or
1354 * vmrgow instructions.
1356 * \param[in] N The shuffle vector SD Node to analyze
1357 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1358 * \param[in] ShuffleKind Identify the type of merge:
1359 * - 0 = big-endian merge with two different inputs;
1360 * - 1 = either-endian merge with two identical inputs;
1361 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1362 * little-endian merges).
1363 * \param[in] DAG The current SelectionDAG
1364 * \return true iff this shuffle mask
1366 bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1367 unsigned ShuffleKind, SelectionDAG &DAG) {
1368 if (DAG.getDataLayout().isLittleEndian()) {
1369 unsigned indexOffset = CheckEven ? 4 : 0;
1370 if (ShuffleKind == 1) // Unary
1371 return isVMerge(N, indexOffset, 0);
1372 else if (ShuffleKind == 2) // swapped
1373 return isVMerge(N, indexOffset, 16);
1378 unsigned indexOffset = CheckEven ? 0 : 4;
1379 if (ShuffleKind == 1) // Unary
1380 return isVMerge(N, indexOffset, 0);
1381 else if (ShuffleKind == 0) // Normal
1382 return isVMerge(N, indexOffset, 16);
1389 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1390 /// amount, otherwise return -1.
1391 /// The ShuffleKind distinguishes between big-endian operations with two
1392 /// different inputs (0), either-endian operations with two identical inputs
1393 /// (1), and little-endian operations with two different inputs (2). For the
1394 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1395 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1396 SelectionDAG &DAG) {
1397 if (N->getValueType(0) != MVT::v16i8)
1400 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1402 // Find the first non-undef value in the shuffle mask.
1404 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1407 if (i == 16) return -1; // all undef.
1409 // Otherwise, check to see if the rest of the elements are consecutively
1410 // numbered from this value.
1411 unsigned ShiftAmt = SVOp->getMaskElt(i);
1412 if (ShiftAmt < i) return -1;
1415 bool isLE = DAG.getDataLayout().isLittleEndian();
1417 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1418 // Check the rest of the elements to see if they are consecutive.
1419 for (++i; i != 16; ++i)
1420 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1422 } else if (ShuffleKind == 1) {
1423 // Check the rest of the elements to see if they are consecutive.
1424 for (++i; i != 16; ++i)
1425 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1431 ShiftAmt = 16 - ShiftAmt;
1436 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1437 /// specifies a splat of a single element that is suitable for input to
1438 /// VSPLTB/VSPLTH/VSPLTW.
1439 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1440 assert(N->getValueType(0) == MVT::v16i8 &&
1441 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1443 // The consecutive indices need to specify an element, not part of two
1444 // different elements. So abandon ship early if this isn't the case.
1445 if (N->getMaskElt(0) % EltSize != 0)
1448 // This is a splat operation if each element of the permute is the same, and
1449 // if the value doesn't reference the second vector.
1450 unsigned ElementBase = N->getMaskElt(0);
1452 // FIXME: Handle UNDEF elements too!
1453 if (ElementBase >= 16)
1456 // Check that the indices are consecutive, in the case of a multi-byte element
1457 // splatted with a v16i8 mask.
1458 for (unsigned i = 1; i != EltSize; ++i)
1459 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1462 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1463 if (N->getMaskElt(i) < 0) continue;
1464 for (unsigned j = 0; j != EltSize; ++j)
1465 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1471 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1472 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1473 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1474 SelectionDAG &DAG) {
1475 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1476 assert(isSplatShuffleMask(SVOp, EltSize));
1477 if (DAG.getDataLayout().isLittleEndian())
1478 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1480 return SVOp->getMaskElt(0) / EltSize;
1483 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1484 /// by using a vspltis[bhw] instruction of the specified element size, return
1485 /// the constant being splatted. The ByteSize field indicates the number of
1486 /// bytes of each element [124] -> [bhw].
1487 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1488 SDValue OpVal(nullptr, 0);
1490 // If ByteSize of the splat is bigger than the element size of the
1491 // build_vector, then we have a case where we are checking for a splat where
1492 // multiple elements of the buildvector are folded together into a single
1493 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1494 unsigned EltSize = 16/N->getNumOperands();
1495 if (EltSize < ByteSize) {
1496 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1497 SDValue UniquedVals[4];
1498 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1500 // See if all of the elements in the buildvector agree across.
1501 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1502 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1503 // If the element isn't a constant, bail fully out.
1504 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1507 if (!UniquedVals[i&(Multiple-1)].getNode())
1508 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1509 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1510 return SDValue(); // no match.
1513 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1514 // either constant or undef values that are identical for each chunk. See
1515 // if these chunks can form into a larger vspltis*.
1517 // Check to see if all of the leading entries are either 0 or -1. If
1518 // neither, then this won't fit into the immediate field.
1519 bool LeadingZero = true;
1520 bool LeadingOnes = true;
1521 for (unsigned i = 0; i != Multiple-1; ++i) {
1522 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1524 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1525 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1527 // Finally, check the least significant entry.
1529 if (!UniquedVals[Multiple-1].getNode())
1530 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
1531 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1532 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
1533 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1536 if (!UniquedVals[Multiple-1].getNode())
1537 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
1538 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1539 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1540 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1546 // Check to see if this buildvec has a single non-undef value in its elements.
1547 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1548 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1549 if (!OpVal.getNode())
1550 OpVal = N->getOperand(i);
1551 else if (OpVal != N->getOperand(i))
1555 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1557 unsigned ValSizeInBytes = EltSize;
1559 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1560 Value = CN->getZExtValue();
1561 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1562 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1563 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1566 // If the splat value is larger than the element value, then we can never do
1567 // this splat. The only case that we could fit the replicated bits into our
1568 // immediate field for would be zero, and we prefer to use vxor for it.
1569 if (ValSizeInBytes < ByteSize) return SDValue();
1571 // If the element value is larger than the splat value, check if it consists
1572 // of a repeated bit pattern of size ByteSize.
1573 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
1576 // Properly sign extend the value.
1577 int MaskVal = SignExtend32(Value, ByteSize * 8);
1579 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1580 if (MaskVal == 0) return SDValue();
1582 // Finally, if this value fits in a 5 bit sext field, return it
1583 if (SignExtend32<5>(MaskVal) == MaskVal)
1584 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
1588 /// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
1589 /// amount, otherwise return -1.
1590 int PPC::isQVALIGNIShuffleMask(SDNode *N) {
1591 EVT VT = N->getValueType(0);
1592 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
1595 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1597 // Find the first non-undef value in the shuffle mask.
1599 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
1602 if (i == 4) return -1; // all undef.
1604 // Otherwise, check to see if the rest of the elements are consecutively
1605 // numbered from this value.
1606 unsigned ShiftAmt = SVOp->getMaskElt(i);
1607 if (ShiftAmt < i) return -1;
1610 // Check the rest of the elements to see if they are consecutive.
1611 for (++i; i != 4; ++i)
1612 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1618 //===----------------------------------------------------------------------===//
1619 // Addressing Mode Selection
1620 //===----------------------------------------------------------------------===//
1622 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1623 /// or 64-bit immediate, and if the value can be accurately represented as a
1624 /// sign extension from a 16-bit value. If so, this returns true and the
1626 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1627 if (!isa<ConstantSDNode>(N))
1630 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1631 if (N->getValueType(0) == MVT::i32)
1632 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1634 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1636 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1637 return isIntS16Immediate(Op.getNode(), Imm);
1641 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1642 /// can be represented as an indexed [r+r] operation. Returns false if it
1643 /// can be more efficiently represented with [r+imm].
1644 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1646 SelectionDAG &DAG) const {
1648 if (N.getOpcode() == ISD::ADD) {
1649 if (isIntS16Immediate(N.getOperand(1), imm))
1650 return false; // r+i
1651 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1652 return false; // r+i
1654 Base = N.getOperand(0);
1655 Index = N.getOperand(1);
1657 } else if (N.getOpcode() == ISD::OR) {
1658 if (isIntS16Immediate(N.getOperand(1), imm))
1659 return false; // r+i can fold it if we can.
1661 // If this is an or of disjoint bitfields, we can codegen this as an add
1662 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1664 APInt LHSKnownZero, LHSKnownOne;
1665 APInt RHSKnownZero, RHSKnownOne;
1666 DAG.computeKnownBits(N.getOperand(0),
1667 LHSKnownZero, LHSKnownOne);
1669 if (LHSKnownZero.getBoolValue()) {
1670 DAG.computeKnownBits(N.getOperand(1),
1671 RHSKnownZero, RHSKnownOne);
1672 // If all of the bits are known zero on the LHS or RHS, the add won't
1674 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1675 Base = N.getOperand(0);
1676 Index = N.getOperand(1);
1685 // If we happen to be doing an i64 load or store into a stack slot that has
1686 // less than a 4-byte alignment, then the frame-index elimination may need to
1687 // use an indexed load or store instruction (because the offset may not be a
1688 // multiple of 4). The extra register needed to hold the offset comes from the
1689 // register scavenger, and it is possible that the scavenger will need to use
1690 // an emergency spill slot. As a result, we need to make sure that a spill slot
1691 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1693 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1694 // FIXME: This does not handle the LWA case.
1698 // NOTE: We'll exclude negative FIs here, which come from argument
1699 // lowering, because there are no known test cases triggering this problem
1700 // using packed structures (or similar). We can remove this exclusion if
1701 // we find such a test case. The reason why this is so test-case driven is
1702 // because this entire 'fixup' is only to prevent crashes (from the
1703 // register scavenger) on not-really-valid inputs. For example, if we have:
1705 // %b = bitcast i1* %a to i64*
1706 // store i64* a, i64 b
1707 // then the store should really be marked as 'align 1', but is not. If it
1708 // were marked as 'align 1' then the indexed form would have been
1709 // instruction-selected initially, and the problem this 'fixup' is preventing
1710 // won't happen regardless.
1714 MachineFunction &MF = DAG.getMachineFunction();
1715 MachineFrameInfo *MFI = MF.getFrameInfo();
1717 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1721 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1722 FuncInfo->setHasNonRISpills();
1725 /// Returns true if the address N can be represented by a base register plus
1726 /// a signed 16-bit displacement [r+imm], and if it is not better
1727 /// represented as reg+reg. If Aligned is true, only accept displacements
1728 /// suitable for STD and friends, i.e. multiples of 4.
1729 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1732 bool Aligned) const {
1733 // FIXME dl should come from parent load or store, not from address
1735 // If this can be more profitably realized as r+r, fail.
1736 if (SelectAddressRegReg(N, Disp, Base, DAG))
1739 if (N.getOpcode() == ISD::ADD) {
1741 if (isIntS16Immediate(N.getOperand(1), imm) &&
1742 (!Aligned || (imm & 3) == 0)) {
1743 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1744 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1745 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1746 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1748 Base = N.getOperand(0);
1750 return true; // [r+i]
1751 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1752 // Match LOAD (ADD (X, Lo(G))).
1753 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1754 && "Cannot handle constant offsets yet!");
1755 Disp = N.getOperand(1).getOperand(0); // The global address.
1756 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1757 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1758 Disp.getOpcode() == ISD::TargetConstantPool ||
1759 Disp.getOpcode() == ISD::TargetJumpTable);
1760 Base = N.getOperand(0);
1761 return true; // [&g+r]
1763 } else if (N.getOpcode() == ISD::OR) {
1765 if (isIntS16Immediate(N.getOperand(1), imm) &&
1766 (!Aligned || (imm & 3) == 0)) {
1767 // If this is an or of disjoint bitfields, we can codegen this as an add
1768 // (for better address arithmetic) if the LHS and RHS of the OR are
1769 // provably disjoint.
1770 APInt LHSKnownZero, LHSKnownOne;
1771 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1773 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1774 // If all of the bits are known zero on the LHS or RHS, the add won't
1776 if (FrameIndexSDNode *FI =
1777 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1778 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1779 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1781 Base = N.getOperand(0);
1783 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1787 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1788 // Loading from a constant address.
1790 // If this address fits entirely in a 16-bit sext immediate field, codegen
1793 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1794 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
1795 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1796 CN->getValueType(0));
1800 // Handle 32-bit sext immediates with LIS + addr mode.
1801 if ((CN->getValueType(0) == MVT::i32 ||
1802 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1803 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1804 int Addr = (int)CN->getZExtValue();
1806 // Otherwise, break this down into an LIS + disp.
1807 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
1809 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
1811 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1812 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1817 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
1818 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1819 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1820 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1823 return true; // [r+0]
1826 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1827 /// represented as an indexed [r+r] operation.
1828 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1830 SelectionDAG &DAG) const {
1831 // Check to see if we can easily represent this as an [r+r] address. This
1832 // will fail if it thinks that the address is more profitably represented as
1833 // reg+imm, e.g. where imm = 0.
1834 if (SelectAddressRegReg(N, Base, Index, DAG))
1837 // If the operand is an addition, always emit this as [r+r], since this is
1838 // better (for code size, and execution, as the memop does the add for free)
1839 // than emitting an explicit add.
1840 if (N.getOpcode() == ISD::ADD) {
1841 Base = N.getOperand(0);
1842 Index = N.getOperand(1);
1846 // Otherwise, do it the hard way, using R0 as the base register.
1847 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1853 /// getPreIndexedAddressParts - returns true by value, base pointer and
1854 /// offset pointer and addressing mode by reference if the node's address
1855 /// can be legally represented as pre-indexed load / store address.
1856 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1858 ISD::MemIndexedMode &AM,
1859 SelectionDAG &DAG) const {
1860 if (DisablePPCPreinc) return false;
1866 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1867 Ptr = LD->getBasePtr();
1868 VT = LD->getMemoryVT();
1869 Alignment = LD->getAlignment();
1870 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1871 Ptr = ST->getBasePtr();
1872 VT = ST->getMemoryVT();
1873 Alignment = ST->getAlignment();
1878 // PowerPC doesn't have preinc load/store instructions for vectors (except
1879 // for QPX, which does have preinc r+r forms).
1880 if (VT.isVector()) {
1881 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
1883 } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
1889 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1891 // Common code will reject creating a pre-inc form if the base pointer
1892 // is a frame index, or if N is a store and the base pointer is either
1893 // the same as or a predecessor of the value being stored. Check for
1894 // those situations here, and try with swapped Base/Offset instead.
1897 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1900 SDValue Val = cast<StoreSDNode>(N)->getValue();
1901 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1906 std::swap(Base, Offset);
1912 // LDU/STU can only handle immediates that are a multiple of 4.
1913 if (VT != MVT::i64) {
1914 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1917 // LDU/STU need an address with at least 4-byte alignment.
1921 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1925 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1926 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1927 // sext i32 to i64 when addr mode is r+i.
1928 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1929 LD->getExtensionType() == ISD::SEXTLOAD &&
1930 isa<ConstantSDNode>(Offset))
1938 //===----------------------------------------------------------------------===//
1939 // LowerOperation implementation
1940 //===----------------------------------------------------------------------===//
1942 /// GetLabelAccessInfo - Return true if we should reference labels using a
1943 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1944 static bool GetLabelAccessInfo(const TargetMachine &TM,
1945 const PPCSubtarget &Subtarget,
1946 unsigned &HiOpFlags, unsigned &LoOpFlags,
1947 const GlobalValue *GV = nullptr) {
1948 HiOpFlags = PPCII::MO_HA;
1949 LoOpFlags = PPCII::MO_LO;
1951 // Don't use the pic base if not in PIC relocation model.
1952 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1955 HiOpFlags |= PPCII::MO_PIC_FLAG;
1956 LoOpFlags |= PPCII::MO_PIC_FLAG;
1959 // If this is a reference to a global value that requires a non-lazy-ptr, make
1960 // sure that instruction lowering adds it.
1961 if (GV && Subtarget.hasLazyResolverStub(GV)) {
1962 HiOpFlags |= PPCII::MO_NLP_FLAG;
1963 LoOpFlags |= PPCII::MO_NLP_FLAG;
1965 if (GV->hasHiddenVisibility()) {
1966 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1967 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1974 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1975 SelectionDAG &DAG) {
1977 EVT PtrVT = HiPart.getValueType();
1978 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
1980 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1981 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1983 // With PIC, the first instruction is actually "GR+hi(&G)".
1985 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1986 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1988 // Generate non-pic code that has direct accesses to the constant pool.
1989 // The address of the global is just (hi(&g)+lo(&g)).
1990 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1993 static void setUsesTOCBasePtr(MachineFunction &MF) {
1994 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1995 FuncInfo->setUsesTOCBasePtr();
1998 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
1999 setUsesTOCBasePtr(DAG.getMachineFunction());
2002 static SDValue getTOCEntry(SelectionDAG &DAG, SDLoc dl, bool Is64Bit,
2004 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2005 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
2006 DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
2008 SDValue Ops[] = { GA, Reg };
2009 return DAG.getMemIntrinsicNode(
2010 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
2011 MachinePointerInfo::getGOT(DAG.getMachineFunction()), 0, false, true,
2015 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2016 SelectionDAG &DAG) const {
2017 EVT PtrVT = Op.getValueType();
2018 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2019 const Constant *C = CP->getConstVal();
2021 // 64-bit SVR4 ABI code is always position-independent.
2022 // The actual address of the GlobalValue is stored in the TOC.
2023 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2024 setUsesTOCBasePtr(DAG);
2025 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
2026 return getTOCEntry(DAG, SDLoc(CP), true, GA);
2029 unsigned MOHiFlag, MOLoFlag;
2031 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2033 if (isPIC && Subtarget.isSVR4ABI()) {
2034 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
2035 PPCII::MO_PIC_FLAG);
2036 return getTOCEntry(DAG, SDLoc(CP), false, GA);
2040 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
2042 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
2043 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
2046 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2047 EVT PtrVT = Op.getValueType();
2048 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2050 // 64-bit SVR4 ABI code is always position-independent.
2051 // The actual address of the GlobalValue is stored in the TOC.
2052 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2053 setUsesTOCBasePtr(DAG);
2054 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2055 return getTOCEntry(DAG, SDLoc(JT), true, GA);
2058 unsigned MOHiFlag, MOLoFlag;
2060 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2062 if (isPIC && Subtarget.isSVR4ABI()) {
2063 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2064 PPCII::MO_PIC_FLAG);
2065 return getTOCEntry(DAG, SDLoc(GA), false, GA);
2068 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
2069 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
2070 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
2073 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2074 SelectionDAG &DAG) const {
2075 EVT PtrVT = Op.getValueType();
2076 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2077 const BlockAddress *BA = BASDN->getBlockAddress();
2079 // 64-bit SVR4 ABI code is always position-independent.
2080 // The actual BlockAddress is stored in the TOC.
2081 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2082 setUsesTOCBasePtr(DAG);
2083 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
2084 return getTOCEntry(DAG, SDLoc(BASDN), true, GA);
2087 unsigned MOHiFlag, MOLoFlag;
2089 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2090 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
2091 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
2092 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
2095 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2096 SelectionDAG &DAG) const {
2098 // FIXME: TLS addresses currently use medium model code sequences,
2099 // which is the most useful form. Eventually support for small and
2100 // large models could be added if users need it, at the cost of
2101 // additional complexity.
2102 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2103 if (DAG.getTarget().Options.EmulatedTLS)
2104 return LowerToTLSEmulatedModel(GA, DAG);
2107 const GlobalValue *GV = GA->getGlobal();
2108 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2109 bool is64bit = Subtarget.isPPC64();
2110 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
2111 PICLevel::Level picLevel = M->getPICLevel();
2113 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
2115 if (Model == TLSModel::LocalExec) {
2116 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2117 PPCII::MO_TPREL_HA);
2118 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2119 PPCII::MO_TPREL_LO);
2120 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
2121 is64bit ? MVT::i64 : MVT::i32);
2122 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
2123 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
2126 if (Model == TLSModel::InitialExec) {
2127 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2128 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2132 setUsesTOCBasePtr(DAG);
2133 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2134 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
2135 PtrVT, GOTReg, TGA);
2137 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
2138 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
2139 PtrVT, TGA, GOTPtr);
2140 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
2143 if (Model == TLSModel::GeneralDynamic) {
2144 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2147 setUsesTOCBasePtr(DAG);
2148 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2149 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
2152 if (picLevel == PICLevel::Small)
2153 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2155 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2157 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
2161 if (Model == TLSModel::LocalDynamic) {
2162 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2165 setUsesTOCBasePtr(DAG);
2166 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2167 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2170 if (picLevel == PICLevel::Small)
2171 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2173 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2175 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2176 PtrVT, GOTPtr, TGA, TGA);
2177 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2178 PtrVT, TLSAddr, TGA);
2179 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2182 llvm_unreachable("Unknown TLS model!");
2185 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2186 SelectionDAG &DAG) const {
2187 EVT PtrVT = Op.getValueType();
2188 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2190 const GlobalValue *GV = GSDN->getGlobal();
2192 // 64-bit SVR4 ABI code is always position-independent.
2193 // The actual address of the GlobalValue is stored in the TOC.
2194 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2195 setUsesTOCBasePtr(DAG);
2196 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2197 return getTOCEntry(DAG, DL, true, GA);
2200 unsigned MOHiFlag, MOLoFlag;
2202 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag, GV);
2204 if (isPIC && Subtarget.isSVR4ABI()) {
2205 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2207 PPCII::MO_PIC_FLAG);
2208 return getTOCEntry(DAG, DL, false, GA);
2212 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2214 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2216 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
2218 // If the global reference is actually to a non-lazy-pointer, we have to do an
2219 // extra load to get the address of the global.
2220 if (MOHiFlag & PPCII::MO_NLP_FLAG)
2221 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
2222 false, false, false, 0);
2226 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2227 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2230 if (Op.getValueType() == MVT::v2i64) {
2231 // When the operands themselves are v2i64 values, we need to do something
2232 // special because VSX has no underlying comparison operations for these.
2233 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2234 // Equality can be handled by casting to the legal type for Altivec
2235 // comparisons, everything else needs to be expanded.
2236 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2237 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2238 DAG.getSetCC(dl, MVT::v4i32,
2239 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2240 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2247 // We handle most of these in the usual way.
2251 // If we're comparing for equality to zero, expose the fact that this is
2252 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
2253 // fold the new nodes.
2254 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2255 if (C->isNullValue() && CC == ISD::SETEQ) {
2256 EVT VT = Op.getOperand(0).getValueType();
2257 SDValue Zext = Op.getOperand(0);
2258 if (VT.bitsLT(MVT::i32)) {
2260 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
2262 unsigned Log2b = Log2_32(VT.getSizeInBits());
2263 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
2264 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
2265 DAG.getConstant(Log2b, dl, MVT::i32));
2266 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
2268 // Leave comparisons against 0 and -1 alone for now, since they're usually
2269 // optimized. FIXME: revisit this when we can custom lower all setcc
2271 if (C->isAllOnesValue() || C->isNullValue())
2275 // If we have an integer seteq/setne, turn it into a compare against zero
2276 // by xor'ing the rhs with the lhs, which is faster than setting a
2277 // condition register, reading it back out, and masking the correct bit. The
2278 // normal approach here uses sub to do this instead of xor. Using xor exposes
2279 // the result to other bit-twiddling opportunities.
2280 EVT LHSVT = Op.getOperand(0).getValueType();
2281 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2282 EVT VT = Op.getValueType();
2283 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2285 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
2290 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
2291 const PPCSubtarget &Subtarget) const {
2292 SDNode *Node = Op.getNode();
2293 EVT VT = Node->getValueType(0);
2294 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2295 SDValue InChain = Node->getOperand(0);
2296 SDValue VAListPtr = Node->getOperand(1);
2297 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2300 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
2303 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2304 VAListPtr, MachinePointerInfo(SV), MVT::i8,
2305 false, false, false, 0);
2306 InChain = GprIndex.getValue(1);
2308 if (VT == MVT::i64) {
2309 // Check if GprIndex is even
2310 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2311 DAG.getConstant(1, dl, MVT::i32));
2312 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2313 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
2314 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2315 DAG.getConstant(1, dl, MVT::i32));
2316 // Align GprIndex to be even if it isn't
2317 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2321 // fpr index is 1 byte after gpr
2322 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2323 DAG.getConstant(1, dl, MVT::i32));
2326 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2327 FprPtr, MachinePointerInfo(SV), MVT::i8,
2328 false, false, false, 0);
2329 InChain = FprIndex.getValue(1);
2331 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2332 DAG.getConstant(8, dl, MVT::i32));
2334 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2335 DAG.getConstant(4, dl, MVT::i32));
2338 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
2339 MachinePointerInfo(), false, false,
2341 InChain = OverflowArea.getValue(1);
2343 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
2344 MachinePointerInfo(), false, false,
2346 InChain = RegSaveArea.getValue(1);
2348 // select overflow_area if index > 8
2349 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
2350 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
2352 // adjustment constant gpr_index * 4/8
2353 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
2354 VT.isInteger() ? GprIndex : FprIndex,
2355 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
2358 // OurReg = RegSaveArea + RegConstant
2359 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2362 // Floating types are 32 bytes into RegSaveArea
2363 if (VT.isFloatingPoint())
2364 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2365 DAG.getConstant(32, dl, MVT::i32));
2367 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
2368 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2369 VT.isInteger() ? GprIndex : FprIndex,
2370 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
2373 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
2374 VT.isInteger() ? VAListPtr : FprPtr,
2375 MachinePointerInfo(SV),
2376 MVT::i8, false, false, 0);
2378 // determine if we should load from reg_save_area or overflow_area
2379 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
2381 // increase overflow_area by 4/8 if gpr/fpr > 8
2382 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2383 DAG.getConstant(VT.isInteger() ? 4 : 8,
2386 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2389 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
2391 MachinePointerInfo(),
2392 MVT::i32, false, false, 0);
2394 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
2395 false, false, false, 0);
2398 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2399 const PPCSubtarget &Subtarget) const {
2400 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2402 // We have to copy the entire va_list struct:
2403 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2404 return DAG.getMemcpy(Op.getOperand(0), Op,
2405 Op.getOperand(1), Op.getOperand(2),
2406 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
2407 false, MachinePointerInfo(), MachinePointerInfo());
2410 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2411 SelectionDAG &DAG) const {
2412 return Op.getOperand(0);
2415 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2416 SelectionDAG &DAG) const {
2417 SDValue Chain = Op.getOperand(0);
2418 SDValue Trmp = Op.getOperand(1); // trampoline
2419 SDValue FPtr = Op.getOperand(2); // nested function
2420 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2423 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2424 bool isPPC64 = (PtrVT == MVT::i64);
2425 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
2427 TargetLowering::ArgListTy Args;
2428 TargetLowering::ArgListEntry Entry;
2430 Entry.Ty = IntPtrTy;
2431 Entry.Node = Trmp; Args.push_back(Entry);
2433 // TrampSize == (isPPC64 ? 48 : 40);
2434 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
2435 isPPC64 ? MVT::i64 : MVT::i32);
2436 Args.push_back(Entry);
2438 Entry.Node = FPtr; Args.push_back(Entry);
2439 Entry.Node = Nest; Args.push_back(Entry);
2441 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2442 TargetLowering::CallLoweringInfo CLI(DAG);
2443 CLI.setDebugLoc(dl).setChain(Chain)
2444 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2445 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2446 std::move(Args), 0);
2448 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2449 return CallResult.second;
2452 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2453 const PPCSubtarget &Subtarget) const {
2454 MachineFunction &MF = DAG.getMachineFunction();
2455 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2459 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2460 // vastart just stores the address of the VarArgsFrameIndex slot into the
2461 // memory location argument.
2462 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2463 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2464 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2465 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2466 MachinePointerInfo(SV),
2470 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2471 // We suppose the given va_list is already allocated.
2474 // char gpr; /* index into the array of 8 GPRs
2475 // * stored in the register save area
2476 // * gpr=0 corresponds to r3,
2477 // * gpr=1 to r4, etc.
2479 // char fpr; /* index into the array of 8 FPRs
2480 // * stored in the register save area
2481 // * fpr=0 corresponds to f1,
2482 // * fpr=1 to f2, etc.
2484 // char *overflow_arg_area;
2485 // /* location on stack that holds
2486 // * the next overflow argument
2488 // char *reg_save_area;
2489 // /* where r3:r10 and f1:f8 (if saved)
2495 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
2496 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
2498 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2500 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2502 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2505 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2506 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
2508 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2509 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
2511 uint64_t FPROffset = 1;
2512 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
2514 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2516 // Store first byte : number of int regs
2517 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2519 MachinePointerInfo(SV),
2520 MVT::i8, false, false, 0);
2521 uint64_t nextOffset = FPROffset;
2522 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2525 // Store second byte : number of float regs
2526 SDValue secondStore =
2527 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2528 MachinePointerInfo(SV, nextOffset), MVT::i8,
2530 nextOffset += StackOffset;
2531 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2533 // Store second word : arguments given on stack
2534 SDValue thirdStore =
2535 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2536 MachinePointerInfo(SV, nextOffset),
2538 nextOffset += FrameOffset;
2539 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2541 // Store third word : arguments given in registers
2542 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2543 MachinePointerInfo(SV, nextOffset),
2548 #include "PPCGenCallingConv.inc"
2550 // Function whose sole purpose is to kill compiler warnings
2551 // stemming from unused functions included from PPCGenCallingConv.inc.
2552 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2553 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2556 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2557 CCValAssign::LocInfo &LocInfo,
2558 ISD::ArgFlagsTy &ArgFlags,
2563 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2565 CCValAssign::LocInfo &LocInfo,
2566 ISD::ArgFlagsTy &ArgFlags,
2568 static const MCPhysReg ArgRegs[] = {
2569 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2570 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2572 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2574 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2576 // Skip one register if the first unallocated register has an even register
2577 // number and there are still argument registers available which have not been
2578 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2579 // need to skip a register if RegNum is odd.
2580 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2581 State.AllocateReg(ArgRegs[RegNum]);
2584 // Always return false here, as this function only makes sure that the first
2585 // unallocated register has an odd register number and does not actually
2586 // allocate a register for the current argument.
2590 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2592 CCValAssign::LocInfo &LocInfo,
2593 ISD::ArgFlagsTy &ArgFlags,
2595 static const MCPhysReg ArgRegs[] = {
2596 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2600 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2602 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2604 // If there is only one Floating-point register left we need to put both f64
2605 // values of a split ppc_fp128 value on the stack.
2606 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2607 State.AllocateReg(ArgRegs[RegNum]);
2610 // Always return false here, as this function only makes sure that the two f64
2611 // values a ppc_fp128 value is split into are both passed in registers or both
2612 // passed on the stack and does not actually allocate a register for the
2613 // current argument.
2617 /// FPR - The set of FP registers that should be allocated for arguments,
2619 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
2620 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
2621 PPC::F11, PPC::F12, PPC::F13};
2623 /// QFPR - The set of QPX registers that should be allocated for arguments.
2624 static const MCPhysReg QFPR[] = {
2625 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
2626 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
2628 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2630 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2631 unsigned PtrByteSize) {
2632 unsigned ArgSize = ArgVT.getStoreSize();
2633 if (Flags.isByVal())
2634 ArgSize = Flags.getByValSize();
2636 // Round up to multiples of the pointer size, except for array members,
2637 // which are always packed.
2638 if (!Flags.isInConsecutiveRegs())
2639 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2644 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2646 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2647 ISD::ArgFlagsTy Flags,
2648 unsigned PtrByteSize) {
2649 unsigned Align = PtrByteSize;
2651 // Altivec parameters are padded to a 16 byte boundary.
2652 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2653 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2654 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2655 ArgVT == MVT::v1i128)
2657 // QPX vector types stored in double-precision are padded to a 32 byte
2659 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
2662 // ByVal parameters are aligned as requested.
2663 if (Flags.isByVal()) {
2664 unsigned BVAlign = Flags.getByValAlign();
2665 if (BVAlign > PtrByteSize) {
2666 if (BVAlign % PtrByteSize != 0)
2668 "ByVal alignment is not a multiple of the pointer size");
2674 // Array members are always packed to their original alignment.
2675 if (Flags.isInConsecutiveRegs()) {
2676 // If the array member was split into multiple registers, the first
2677 // needs to be aligned to the size of the full type. (Except for
2678 // ppcf128, which is only aligned as its f64 components.)
2679 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2680 Align = OrigVT.getStoreSize();
2682 Align = ArgVT.getStoreSize();
2688 /// CalculateStackSlotUsed - Return whether this argument will use its
2689 /// stack slot (instead of being passed in registers). ArgOffset,
2690 /// AvailableFPRs, and AvailableVRs must hold the current argument
2691 /// position, and will be updated to account for this argument.
2692 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2693 ISD::ArgFlagsTy Flags,
2694 unsigned PtrByteSize,
2695 unsigned LinkageSize,
2696 unsigned ParamAreaSize,
2697 unsigned &ArgOffset,
2698 unsigned &AvailableFPRs,
2699 unsigned &AvailableVRs, bool HasQPX) {
2700 bool UseMemory = false;
2702 // Respect alignment of argument on the stack.
2704 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2705 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2706 // If there's no space left in the argument save area, we must
2707 // use memory (this check also catches zero-sized arguments).
2708 if (ArgOffset >= LinkageSize + ParamAreaSize)
2711 // Allocate argument on the stack.
2712 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2713 if (Flags.isInConsecutiveRegsLast())
2714 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2715 // If we overran the argument save area, we must use memory
2716 // (this check catches arguments passed partially in memory)
2717 if (ArgOffset > LinkageSize + ParamAreaSize)
2720 // However, if the argument is actually passed in an FPR or a VR,
2721 // we don't use memory after all.
2722 if (!Flags.isByVal()) {
2723 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
2724 // QPX registers overlap with the scalar FP registers.
2725 (HasQPX && (ArgVT == MVT::v4f32 ||
2726 ArgVT == MVT::v4f64 ||
2727 ArgVT == MVT::v4i1)))
2728 if (AvailableFPRs > 0) {
2732 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2733 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2734 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2735 ArgVT == MVT::v1i128)
2736 if (AvailableVRs > 0) {
2745 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2746 /// ensure minimum alignment required for target.
2747 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2748 unsigned NumBytes) {
2749 unsigned TargetAlign = Lowering->getStackAlignment();
2750 unsigned AlignMask = TargetAlign - 1;
2751 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2756 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2757 CallingConv::ID CallConv, bool isVarArg,
2758 const SmallVectorImpl<ISD::InputArg>
2760 SDLoc dl, SelectionDAG &DAG,
2761 SmallVectorImpl<SDValue> &InVals)
2763 if (Subtarget.isSVR4ABI()) {
2764 if (Subtarget.isPPC64())
2765 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2768 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2771 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2777 PPCTargetLowering::LowerFormalArguments_32SVR4(
2779 CallingConv::ID CallConv, bool isVarArg,
2780 const SmallVectorImpl<ISD::InputArg>
2782 SDLoc dl, SelectionDAG &DAG,
2783 SmallVectorImpl<SDValue> &InVals) const {
2785 // 32-bit SVR4 ABI Stack Frame Layout:
2786 // +-----------------------------------+
2787 // +--> | Back chain |
2788 // | +-----------------------------------+
2789 // | | Floating-point register save area |
2790 // | +-----------------------------------+
2791 // | | General register save area |
2792 // | +-----------------------------------+
2793 // | | CR save word |
2794 // | +-----------------------------------+
2795 // | | VRSAVE save word |
2796 // | +-----------------------------------+
2797 // | | Alignment padding |
2798 // | +-----------------------------------+
2799 // | | Vector register save area |
2800 // | +-----------------------------------+
2801 // | | Local variable space |
2802 // | +-----------------------------------+
2803 // | | Parameter list area |
2804 // | +-----------------------------------+
2805 // | | LR save word |
2806 // | +-----------------------------------+
2807 // SP--> +--- | Back chain |
2808 // +-----------------------------------+
2811 // System V Application Binary Interface PowerPC Processor Supplement
2812 // AltiVec Technology Programming Interface Manual
2814 MachineFunction &MF = DAG.getMachineFunction();
2815 MachineFrameInfo *MFI = MF.getFrameInfo();
2816 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2818 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2819 // Potential tail calls could cause overwriting of argument stack slots.
2820 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2821 (CallConv == CallingConv::Fast));
2822 unsigned PtrByteSize = 4;
2824 // Assign locations to all of the incoming arguments.
2825 SmallVector<CCValAssign, 16> ArgLocs;
2826 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2829 // Reserve space for the linkage area on the stack.
2830 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
2831 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2833 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2835 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2836 CCValAssign &VA = ArgLocs[i];
2838 // Arguments stored in registers.
2839 if (VA.isRegLoc()) {
2840 const TargetRegisterClass *RC;
2841 EVT ValVT = VA.getValVT();
2843 switch (ValVT.getSimpleVT().SimpleTy) {
2845 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2848 RC = &PPC::GPRCRegClass;
2851 if (Subtarget.hasP8Vector())
2852 RC = &PPC::VSSRCRegClass;
2854 RC = &PPC::F4RCRegClass;
2857 if (Subtarget.hasVSX())
2858 RC = &PPC::VSFRCRegClass;
2860 RC = &PPC::F8RCRegClass;
2865 RC = &PPC::VRRCRegClass;
2868 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
2872 RC = &PPC::VSHRCRegClass;
2875 RC = &PPC::QFRCRegClass;
2878 RC = &PPC::QBRCRegClass;
2882 // Transform the arguments stored in physical registers into virtual ones.
2883 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2884 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2885 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2887 if (ValVT == MVT::i1)
2888 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2890 InVals.push_back(ArgValue);
2892 // Argument stored in memory.
2893 assert(VA.isMemLoc());
2895 unsigned ArgSize = VA.getLocVT().getStoreSize();
2896 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2899 // Create load nodes to retrieve arguments from the stack.
2900 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2901 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2902 MachinePointerInfo(),
2903 false, false, false, 0));
2907 // Assign locations to all of the incoming aggregate by value arguments.
2908 // Aggregates passed by value are stored in the local variable space of the
2909 // caller's stack frame, right above the parameter list area.
2910 SmallVector<CCValAssign, 16> ByValArgLocs;
2911 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2912 ByValArgLocs, *DAG.getContext());
2914 // Reserve stack space for the allocations in CCInfo.
2915 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2917 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2919 // Area that is at least reserved in the caller of this function.
2920 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2921 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2923 // Set the size that is at least reserved in caller of this function. Tail
2924 // call optimized function's reserved stack space needs to be aligned so that
2925 // taking the difference between two stack areas will result in an aligned
2928 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2929 FuncInfo->setMinReservedArea(MinReservedArea);
2931 SmallVector<SDValue, 8> MemOps;
2933 // If the function takes variable number of arguments, make a frame index for
2934 // the start of the first vararg value... for expansion of llvm.va_start.
2936 static const MCPhysReg GPArgRegs[] = {
2937 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2938 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2940 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2942 static const MCPhysReg FPArgRegs[] = {
2943 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2946 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2947 if (DisablePPCFloatInVariadic)
2950 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
2951 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
2953 // Make room for NumGPArgRegs and NumFPArgRegs.
2954 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2955 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2957 FuncInfo->setVarArgsStackOffset(
2958 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2959 CCInfo.getNextStackOffset(), true));
2961 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2962 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2964 // The fixed integer arguments of a variadic function are stored to the
2965 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2966 // the result of va_next.
2967 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2968 // Get an existing live-in vreg, or add a new one.
2969 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2971 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2973 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2974 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2975 MachinePointerInfo(), false, false, 0);
2976 MemOps.push_back(Store);
2977 // Increment the address by four for the next argument to store
2978 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
2979 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2982 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2984 // The double arguments are stored to the VarArgsFrameIndex
2986 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2987 // Get an existing live-in vreg, or add a new one.
2988 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2990 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2992 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2993 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2994 MachinePointerInfo(), false, false, 0);
2995 MemOps.push_back(Store);
2996 // Increment the address by eight for the next argument to store
2997 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
2999 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3003 if (!MemOps.empty())
3004 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3009 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3010 // value to MVT::i64 and then truncate to the correct register size.
3012 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
3013 SelectionDAG &DAG, SDValue ArgVal,
3016 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
3017 DAG.getValueType(ObjectVT));
3018 else if (Flags.isZExt())
3019 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3020 DAG.getValueType(ObjectVT));
3022 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3026 PPCTargetLowering::LowerFormalArguments_64SVR4(
3028 CallingConv::ID CallConv, bool isVarArg,
3029 const SmallVectorImpl<ISD::InputArg>
3031 SDLoc dl, SelectionDAG &DAG,
3032 SmallVectorImpl<SDValue> &InVals) const {
3033 // TODO: add description of PPC stack frame format, or at least some docs.
3035 bool isELFv2ABI = Subtarget.isELFv2ABI();
3036 bool isLittleEndian = Subtarget.isLittleEndian();
3037 MachineFunction &MF = DAG.getMachineFunction();
3038 MachineFrameInfo *MFI = MF.getFrameInfo();
3039 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3041 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
3042 "fastcc not supported on varargs functions");
3044 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
3045 // Potential tail calls could cause overwriting of argument stack slots.
3046 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3047 (CallConv == CallingConv::Fast));
3048 unsigned PtrByteSize = 8;
3049 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3051 static const MCPhysReg GPR[] = {
3052 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3053 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3055 static const MCPhysReg VR[] = {
3056 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3057 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3059 static const MCPhysReg VSRH[] = {
3060 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
3061 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
3064 const unsigned Num_GPR_Regs = array_lengthof(GPR);
3065 const unsigned Num_FPR_Regs = 13;
3066 const unsigned Num_VR_Regs = array_lengthof(VR);
3067 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3069 // Do a first pass over the arguments to determine whether the ABI
3070 // guarantees that our caller has allocated the parameter save area
3071 // on its stack frame. In the ELFv1 ABI, this is always the case;
3072 // in the ELFv2 ABI, it is true if this is a vararg function or if
3073 // any parameter is located in a stack slot.
3075 bool HasParameterArea = !isELFv2ABI || isVarArg;
3076 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3077 unsigned NumBytes = LinkageSize;
3078 unsigned AvailableFPRs = Num_FPR_Regs;
3079 unsigned AvailableVRs = Num_VR_Regs;
3080 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3081 if (Ins[i].Flags.isNest())
3084 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3085 PtrByteSize, LinkageSize, ParamAreaSize,
3086 NumBytes, AvailableFPRs, AvailableVRs,
3087 Subtarget.hasQPX()))
3088 HasParameterArea = true;
3091 // Add DAG nodes to load the arguments or copy them out of registers. On
3092 // entry to a function on PPC, the arguments start after the linkage area,
3093 // although the first ones are often in registers.
3095 unsigned ArgOffset = LinkageSize;
3096 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3097 unsigned &QFPR_idx = FPR_idx;
3098 SmallVector<SDValue, 8> MemOps;
3099 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3100 unsigned CurArgIdx = 0;
3101 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3103 bool needsLoad = false;
3104 EVT ObjectVT = Ins[ArgNo].VT;
3105 EVT OrigVT = Ins[ArgNo].ArgVT;
3106 unsigned ObjSize = ObjectVT.getStoreSize();
3107 unsigned ArgSize = ObjSize;
3108 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3109 if (Ins[ArgNo].isOrigArg()) {
3110 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3111 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3113 // We re-align the argument offset for each argument, except when using the
3114 // fast calling convention, when we need to make sure we do that only when
3115 // we'll actually use a stack slot.
3116 unsigned CurArgOffset, Align;
3117 auto ComputeArgOffset = [&]() {
3118 /* Respect alignment of argument on the stack. */
3119 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
3120 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3121 CurArgOffset = ArgOffset;
3124 if (CallConv != CallingConv::Fast) {
3127 /* Compute GPR index associated with argument offset. */
3128 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3129 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
3132 // FIXME the codegen can be much improved in some cases.
3133 // We do not have to keep everything in memory.
3134 if (Flags.isByVal()) {
3135 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3137 if (CallConv == CallingConv::Fast)
3140 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3141 ObjSize = Flags.getByValSize();
3142 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3143 // Empty aggregate parameters do not take up registers. Examples:
3147 // etc. However, we have to provide a place-holder in InVals, so
3148 // pretend we have an 8-byte item at the current address for that
3151 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3152 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3153 InVals.push_back(FIN);
3157 // Create a stack object covering all stack doublewords occupied
3158 // by the argument. If the argument is (fully or partially) on
3159 // the stack, or if the argument is fully in registers but the
3160 // caller has allocated the parameter save anyway, we can refer
3161 // directly to the caller's stack frame. Otherwise, create a
3162 // local copy in our own frame.
3164 if (HasParameterArea ||
3165 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
3166 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
3168 FI = MFI->CreateStackObject(ArgSize, Align, false);
3169 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3171 // Handle aggregates smaller than 8 bytes.
3172 if (ObjSize < PtrByteSize) {
3173 // The value of the object is its address, which differs from the
3174 // address of the enclosing doubleword on big-endian systems.
3176 if (!isLittleEndian) {
3177 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
3178 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3180 InVals.push_back(Arg);
3182 if (GPR_idx != Num_GPR_Regs) {
3183 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3184 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3187 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3188 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3189 (ObjSize == 2 ? MVT::i16 : MVT::i32));
3190 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3191 MachinePointerInfo(FuncArg),
3192 ObjType, false, false, 0);
3194 // For sizes that don't fit a truncating store (3, 5, 6, 7),
3195 // store the whole register as-is to the parameter save area
3197 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3198 MachinePointerInfo(FuncArg),
3202 MemOps.push_back(Store);
3204 // Whether we copied from a register or not, advance the offset
3205 // into the parameter save area by a full doubleword.
3206 ArgOffset += PtrByteSize;
3210 // The value of the object is its address, which is the address of
3211 // its first stack doubleword.
3212 InVals.push_back(FIN);
3214 // Store whatever pieces of the object are in registers to memory.
3215 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3216 if (GPR_idx == Num_GPR_Regs)
3219 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3220 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3223 SDValue Off = DAG.getConstant(j, dl, PtrVT);
3224 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3226 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
3227 MachinePointerInfo(FuncArg, j),
3229 MemOps.push_back(Store);
3232 ArgOffset += ArgSize;
3236 switch (ObjectVT.getSimpleVT().SimpleTy) {
3237 default: llvm_unreachable("Unhandled argument type!");
3241 if (Flags.isNest()) {
3242 // The 'nest' parameter, if any, is passed in R11.
3243 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
3244 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3246 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3247 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3252 // These can be scalar arguments or elements of an integer array type
3253 // passed directly. Clang may use those instead of "byval" aggregate
3254 // types to avoid forcing arguments to memory unnecessarily.
3255 if (GPR_idx != Num_GPR_Regs) {
3256 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3257 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3259 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3260 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3261 // value to MVT::i64 and then truncate to the correct register size.
3262 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3264 if (CallConv == CallingConv::Fast)
3268 ArgSize = PtrByteSize;
3270 if (CallConv != CallingConv::Fast || needsLoad)
3276 // These can be scalar arguments or elements of a float array type
3277 // passed directly. The latter are used to implement ELFv2 homogenous
3278 // float aggregates.
3279 if (FPR_idx != Num_FPR_Regs) {
3282 if (ObjectVT == MVT::f32)
3283 VReg = MF.addLiveIn(FPR[FPR_idx],
3284 Subtarget.hasP8Vector()
3285 ? &PPC::VSSRCRegClass
3286 : &PPC::F4RCRegClass);
3288 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3289 ? &PPC::VSFRCRegClass
3290 : &PPC::F8RCRegClass);
3292 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3294 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3295 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3296 // once we support fp <-> gpr moves.
3298 // This can only ever happen in the presence of f32 array types,
3299 // since otherwise we never run out of FPRs before running out
3301 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3302 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3304 if (ObjectVT == MVT::f32) {
3305 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3306 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3307 DAG.getConstant(32, dl, MVT::i32));
3308 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3311 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3313 if (CallConv == CallingConv::Fast)
3319 // When passing an array of floats, the array occupies consecutive
3320 // space in the argument area; only round up to the next doubleword
3321 // at the end of the array. Otherwise, each float takes 8 bytes.
3322 if (CallConv != CallingConv::Fast || needsLoad) {
3323 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3324 ArgOffset += ArgSize;
3325 if (Flags.isInConsecutiveRegsLast())
3326 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3336 if (!Subtarget.hasQPX()) {
3337 // These can be scalar arguments or elements of a vector array type
3338 // passed directly. The latter are used to implement ELFv2 homogenous
3339 // vector aggregates.
3340 if (VR_idx != Num_VR_Regs) {
3341 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
3342 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
3343 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3344 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3347 if (CallConv == CallingConv::Fast)
3352 if (CallConv != CallingConv::Fast || needsLoad)
3357 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
3358 "Invalid QPX parameter type");
3363 // QPX vectors are treated like their scalar floating-point subregisters
3364 // (except that they're larger).
3365 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3366 if (QFPR_idx != Num_QFPR_Regs) {
3367 const TargetRegisterClass *RC;
3368 switch (ObjectVT.getSimpleVT().SimpleTy) {
3369 case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3370 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3371 default: RC = &PPC::QBRCRegClass; break;
3374 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3375 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3378 if (CallConv == CallingConv::Fast)
3382 if (CallConv != CallingConv::Fast || needsLoad)
3387 // We need to load the argument to a virtual register if we determined
3388 // above that we ran out of physical registers of the appropriate type.
3390 if (ObjSize < ArgSize && !isLittleEndian)
3391 CurArgOffset += ArgSize - ObjSize;
3392 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
3393 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3394 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3395 false, false, false, 0);
3398 InVals.push_back(ArgVal);
3401 // Area that is at least reserved in the caller of this function.
3402 unsigned MinReservedArea;
3403 if (HasParameterArea)
3404 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
3406 MinReservedArea = LinkageSize;
3408 // Set the size that is at least reserved in caller of this function. Tail
3409 // call optimized functions' reserved stack space needs to be aligned so that
3410 // taking the difference between two stack areas will result in an aligned
3413 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3414 FuncInfo->setMinReservedArea(MinReservedArea);
3416 // If the function takes variable number of arguments, make a frame index for
3417 // the start of the first vararg value... for expansion of llvm.va_start.
3419 int Depth = ArgOffset;
3421 FuncInfo->setVarArgsFrameIndex(
3422 MFI->CreateFixedObject(PtrByteSize, Depth, true));
3423 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3425 // If this function is vararg, store any remaining integer argument regs
3426 // to their spots on the stack so that they may be loaded by deferencing the
3427 // result of va_next.
3428 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3429 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
3430 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3431 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3432 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3433 MachinePointerInfo(), false, false, 0);
3434 MemOps.push_back(Store);
3435 // Increment the address by four for the next argument to store
3436 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
3437 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3441 if (!MemOps.empty())
3442 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3448 PPCTargetLowering::LowerFormalArguments_Darwin(
3450 CallingConv::ID CallConv, bool isVarArg,
3451 const SmallVectorImpl<ISD::InputArg>
3453 SDLoc dl, SelectionDAG &DAG,
3454 SmallVectorImpl<SDValue> &InVals) const {
3455 // TODO: add description of PPC stack frame format, or at least some docs.
3457 MachineFunction &MF = DAG.getMachineFunction();
3458 MachineFrameInfo *MFI = MF.getFrameInfo();
3459 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3461 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
3462 bool isPPC64 = PtrVT == MVT::i64;
3463 // Potential tail calls could cause overwriting of argument stack slots.
3464 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3465 (CallConv == CallingConv::Fast));
3466 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3467 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3468 unsigned ArgOffset = LinkageSize;
3469 // Area that is at least reserved in caller of this function.
3470 unsigned MinReservedArea = ArgOffset;
3472 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3473 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3474 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3476 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3477 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3478 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3480 static const MCPhysReg VR[] = {
3481 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3482 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3485 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3486 const unsigned Num_FPR_Regs = 13;
3487 const unsigned Num_VR_Regs = array_lengthof( VR);
3489 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3491 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3493 // In 32-bit non-varargs functions, the stack space for vectors is after the
3494 // stack space for non-vectors. We do not use this space unless we have
3495 // too many vectors to fit in registers, something that only occurs in
3496 // constructed examples:), but we have to walk the arglist to figure
3497 // that out...for the pathological case, compute VecArgOffset as the
3498 // start of the vector parameter area. Computing VecArgOffset is the
3499 // entire point of the following loop.
3500 unsigned VecArgOffset = ArgOffset;
3501 if (!isVarArg && !isPPC64) {
3502 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3504 EVT ObjectVT = Ins[ArgNo].VT;
3505 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3507 if (Flags.isByVal()) {
3508 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3509 unsigned ObjSize = Flags.getByValSize();
3511 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3512 VecArgOffset += ArgSize;
3516 switch(ObjectVT.getSimpleVT().SimpleTy) {
3517 default: llvm_unreachable("Unhandled argument type!");
3523 case MVT::i64: // PPC64
3525 // FIXME: We are guaranteed to be !isPPC64 at this point.
3526 // Does MVT::i64 apply?
3533 // Nothing to do, we're only looking at Nonvector args here.
3538 // We've found where the vector parameter area in memory is. Skip the
3539 // first 12 parameters; these don't use that memory.
3540 VecArgOffset = ((VecArgOffset+15)/16)*16;
3541 VecArgOffset += 12*16;
3543 // Add DAG nodes to load the arguments or copy them out of registers. On
3544 // entry to a function on PPC, the arguments start after the linkage area,
3545 // although the first ones are often in registers.
3547 SmallVector<SDValue, 8> MemOps;
3548 unsigned nAltivecParamsAtEnd = 0;
3549 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3550 unsigned CurArgIdx = 0;
3551 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3553 bool needsLoad = false;
3554 EVT ObjectVT = Ins[ArgNo].VT;
3555 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3556 unsigned ArgSize = ObjSize;
3557 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3558 if (Ins[ArgNo].isOrigArg()) {
3559 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3560 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3562 unsigned CurArgOffset = ArgOffset;
3564 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3565 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3566 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3567 if (isVarArg || isPPC64) {
3568 MinReservedArea = ((MinReservedArea+15)/16)*16;
3569 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3572 } else nAltivecParamsAtEnd++;
3574 // Calculate min reserved area.
3575 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3579 // FIXME the codegen can be much improved in some cases.
3580 // We do not have to keep everything in memory.
3581 if (Flags.isByVal()) {
3582 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3584 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3585 ObjSize = Flags.getByValSize();
3586 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3587 // Objects of size 1 and 2 are right justified, everything else is
3588 // left justified. This means the memory address is adjusted forwards.
3589 if (ObjSize==1 || ObjSize==2) {
3590 CurArgOffset = CurArgOffset + (4 - ObjSize);
3592 // The value of the object is its address.
3593 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3594 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3595 InVals.push_back(FIN);
3596 if (ObjSize==1 || ObjSize==2) {
3597 if (GPR_idx != Num_GPR_Regs) {
3600 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3602 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3603 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3604 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3605 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3606 MachinePointerInfo(FuncArg),
3607 ObjType, false, false, 0);
3608 MemOps.push_back(Store);
3612 ArgOffset += PtrByteSize;
3616 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3617 // Store whatever pieces of the object are in registers
3618 // to memory. ArgOffset will be the address of the beginning
3620 if (GPR_idx != Num_GPR_Regs) {
3623 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3625 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3626 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3627 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3628 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3629 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3630 MachinePointerInfo(FuncArg, j),
3632 MemOps.push_back(Store);
3634 ArgOffset += PtrByteSize;
3636 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3643 switch (ObjectVT.getSimpleVT().SimpleTy) {
3644 default: llvm_unreachable("Unhandled argument type!");
3648 if (GPR_idx != Num_GPR_Regs) {
3649 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3650 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3652 if (ObjectVT == MVT::i1)
3653 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3658 ArgSize = PtrByteSize;
3660 // All int arguments reserve stack space in the Darwin ABI.
3661 ArgOffset += PtrByteSize;
3665 case MVT::i64: // PPC64
3666 if (GPR_idx != Num_GPR_Regs) {
3667 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3668 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3670 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3671 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3672 // value to MVT::i64 and then truncate to the correct register size.
3673 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3678 ArgSize = PtrByteSize;
3680 // All int arguments reserve stack space in the Darwin ABI.
3686 // Every 4 bytes of argument space consumes one of the GPRs available for
3687 // argument passing.
3688 if (GPR_idx != Num_GPR_Regs) {
3690 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3693 if (FPR_idx != Num_FPR_Regs) {
3696 if (ObjectVT == MVT::f32)
3697 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3699 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3701 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3707 // All FP arguments reserve stack space in the Darwin ABI.
3708 ArgOffset += isPPC64 ? 8 : ObjSize;
3714 // Note that vector arguments in registers don't reserve stack space,
3715 // except in varargs functions.
3716 if (VR_idx != Num_VR_Regs) {
3717 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3718 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3720 while ((ArgOffset % 16) != 0) {
3721 ArgOffset += PtrByteSize;
3722 if (GPR_idx != Num_GPR_Regs)
3726 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3730 if (!isVarArg && !isPPC64) {
3731 // Vectors go after all the nonvectors.
3732 CurArgOffset = VecArgOffset;
3735 // Vectors are aligned.
3736 ArgOffset = ((ArgOffset+15)/16)*16;
3737 CurArgOffset = ArgOffset;
3745 // We need to load the argument to a virtual register if we determined above
3746 // that we ran out of physical registers of the appropriate type.
3748 int FI = MFI->CreateFixedObject(ObjSize,
3749 CurArgOffset + (ArgSize - ObjSize),
3751 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3752 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3753 false, false, false, 0);
3756 InVals.push_back(ArgVal);
3759 // Allow for Altivec parameters at the end, if needed.
3760 if (nAltivecParamsAtEnd) {
3761 MinReservedArea = ((MinReservedArea+15)/16)*16;
3762 MinReservedArea += 16*nAltivecParamsAtEnd;
3765 // Area that is at least reserved in the caller of this function.
3766 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3768 // Set the size that is at least reserved in caller of this function. Tail
3769 // call optimized functions' reserved stack space needs to be aligned so that
3770 // taking the difference between two stack areas will result in an aligned
3773 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3774 FuncInfo->setMinReservedArea(MinReservedArea);
3776 // If the function takes variable number of arguments, make a frame index for
3777 // the start of the first vararg value... for expansion of llvm.va_start.
3779 int Depth = ArgOffset;
3781 FuncInfo->setVarArgsFrameIndex(
3782 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3784 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3786 // If this function is vararg, store any remaining integer argument regs
3787 // to their spots on the stack so that they may be loaded by deferencing the
3788 // result of va_next.
3789 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3793 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3795 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3797 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3798 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3799 MachinePointerInfo(), false, false, 0);
3800 MemOps.push_back(Store);
3801 // Increment the address by four for the next argument to store
3802 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3803 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3807 if (!MemOps.empty())
3808 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3813 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3814 /// adjusted to accommodate the arguments for the tailcall.
3815 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3816 unsigned ParamSize) {
3818 if (!isTailCall) return 0;
3820 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3821 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3822 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3823 // Remember only if the new adjustement is bigger.
3824 if (SPDiff < FI->getTailCallSPDelta())
3825 FI->setTailCallSPDelta(SPDiff);
3830 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3831 /// for tail call optimization. Targets which want to do tail call
3832 /// optimization should implement this function.
3834 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3835 CallingConv::ID CalleeCC,
3837 const SmallVectorImpl<ISD::InputArg> &Ins,
3838 SelectionDAG& DAG) const {
3839 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3842 // Variable argument functions are not supported.
3846 MachineFunction &MF = DAG.getMachineFunction();
3847 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3848 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3849 // Functions containing by val parameters are not supported.
3850 for (unsigned i = 0; i != Ins.size(); i++) {
3851 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3852 if (Flags.isByVal()) return false;
3855 // Non-PIC/GOT tail calls are supported.
3856 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3859 // At the moment we can only do local tail calls (in same module, hidden
3860 // or protected) if we are generating PIC.
3861 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3862 return G->getGlobal()->hasHiddenVisibility()
3863 || G->getGlobal()->hasProtectedVisibility();
3869 /// isCallCompatibleAddress - Return the immediate to use if the specified
3870 /// 32-bit value is representable in the immediate field of a BxA instruction.
3871 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3872 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3873 if (!C) return nullptr;
3875 int Addr = C->getZExtValue();
3876 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3877 SignExtend32<26>(Addr) != Addr)
3878 return nullptr; // Top 6 bits have to be sext of immediate.
3880 return DAG.getConstant((int)C->getZExtValue() >> 2, SDLoc(Op),
3881 DAG.getTargetLoweringInfo().getPointerTy(
3882 DAG.getDataLayout())).getNode();
3887 struct TailCallArgumentInfo {
3892 TailCallArgumentInfo() : FrameIdx(0) {}
3897 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3899 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3901 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3902 SmallVectorImpl<SDValue> &MemOpChains,
3904 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3905 SDValue Arg = TailCallArgs[i].Arg;
3906 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3907 int FI = TailCallArgs[i].FrameIdx;
3908 // Store relative to framepointer.
3909 MemOpChains.push_back(DAG.getStore(
3910 Chain, dl, Arg, FIN,
3911 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
3916 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3917 /// the appropriate stack slot for the tail call optimized function call.
3918 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3919 MachineFunction &MF,
3928 // Calculate the new stack slot for the return address.
3929 int SlotSize = isPPC64 ? 8 : 4;
3930 const PPCFrameLowering *FL =
3931 MF.getSubtarget<PPCSubtarget>().getFrameLowering();
3932 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
3933 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3934 NewRetAddrLoc, true);
3935 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3936 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3937 Chain = DAG.getStore(
3938 Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3939 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), NewRetAddr),
3942 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3943 // slot as the FP is never overwritten.
3945 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
3946 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3948 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3949 Chain = DAG.getStore(
3950 Chain, dl, OldFP, NewFramePtrIdx,
3951 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), NewFPIdx),
3958 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3959 /// the position of the argument.
3961 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3962 SDValue Arg, int SPDiff, unsigned ArgOffset,
3963 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3964 int Offset = ArgOffset + SPDiff;
3965 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3966 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3967 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3968 SDValue FIN = DAG.getFrameIndex(FI, VT);
3969 TailCallArgumentInfo Info;
3971 Info.FrameIdxOp = FIN;
3973 TailCallArguments.push_back(Info);
3976 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3977 /// stack slot. Returns the chain as result and the loaded frame pointers in
3978 /// LROpOut/FPOpout. Used when tail calling.
3979 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3987 // Load the LR and FP stack slot for later adjusting.
3988 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3989 LROpOut = getReturnAddrFrameIndex(DAG);
3990 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3991 false, false, false, 0);
3992 Chain = SDValue(LROpOut.getNode(), 1);
3994 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3995 // slot as the FP is never overwritten.
3997 FPOpOut = getFramePointerFrameIndex(DAG);
3998 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3999 false, false, false, 0);
4000 Chain = SDValue(FPOpOut.getNode(), 1);
4006 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
4007 /// by "Src" to address "Dst" of size "Size". Alignment information is
4008 /// specified by the specific parameter attribute. The copy will be passed as
4009 /// a byval function parameter.
4010 /// Sometimes what we are copying is the end of a larger object, the part that
4011 /// does not fit in registers.
4013 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
4014 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
4016 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
4017 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
4018 false, false, false, MachinePointerInfo(),
4019 MachinePointerInfo());
4022 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
4025 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
4026 SDValue Arg, SDValue PtrOff, int SPDiff,
4027 unsigned ArgOffset, bool isPPC64, bool isTailCall,
4028 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
4029 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
4031 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4036 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4038 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4039 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4040 DAG.getConstant(ArgOffset, dl, PtrVT));
4042 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4043 MachinePointerInfo(), false, false, 0));
4044 // Calculate and remember argument location.
4045 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
4050 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
4051 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
4052 SDValue LROp, SDValue FPOp, bool isDarwinABI,
4053 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
4054 MachineFunction &MF = DAG.getMachineFunction();
4056 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
4057 // might overwrite each other in case of tail call optimization.
4058 SmallVector<SDValue, 8> MemOpChains2;
4059 // Do not flag preceding copytoreg stuff together with the following stuff.
4061 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
4063 if (!MemOpChains2.empty())
4064 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4066 // Store the return address to the appropriate stack slot.
4067 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
4068 isPPC64, isDarwinABI, dl);
4070 // Emit callseq_end just before tailcall node.
4071 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4072 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4073 InFlag = Chain.getValue(1);
4076 // Is this global address that of a function that can be called by name? (as
4077 // opposed to something that must hold a descriptor for an indirect call).
4078 static bool isFunctionGlobalAddress(SDValue Callee) {
4079 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
4080 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
4081 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
4084 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
4091 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
4092 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
4093 bool isTailCall, bool IsPatchPoint, bool hasNest,
4094 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
4095 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
4096 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
4098 bool isPPC64 = Subtarget.isPPC64();
4099 bool isSVR4ABI = Subtarget.isSVR4ABI();
4100 bool isELFv2ABI = Subtarget.isELFv2ABI();
4102 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4103 NodeTys.push_back(MVT::Other); // Returns a chain
4104 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
4106 unsigned CallOpc = PPCISD::CALL;
4108 bool needIndirectCall = true;
4109 if (!isSVR4ABI || !isPPC64)
4110 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
4111 // If this is an absolute destination address, use the munged value.
4112 Callee = SDValue(Dest, 0);
4113 needIndirectCall = false;
4116 if (isFunctionGlobalAddress(Callee)) {
4117 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
4118 // A call to a TLS address is actually an indirect call to a
4119 // thread-specific pointer.
4120 unsigned OpFlags = 0;
4121 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4122 (Subtarget.getTargetTriple().isMacOSX() &&
4123 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
4124 !G->getGlobal()->isStrongDefinitionForLinker()) ||
4125 (Subtarget.isTargetELF() && !isPPC64 &&
4126 !G->getGlobal()->hasLocalLinkage() &&
4127 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4128 // PC-relative references to external symbols should go through $stub,
4129 // unless we're building with the leopard linker or later, which
4130 // automatically synthesizes these stubs.
4131 OpFlags = PPCII::MO_PLT_OR_STUB;
4134 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
4135 // every direct call is) turn it into a TargetGlobalAddress /
4136 // TargetExternalSymbol node so that legalize doesn't hack it.
4137 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
4138 Callee.getValueType(), 0, OpFlags);
4139 needIndirectCall = false;
4142 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
4143 unsigned char OpFlags = 0;
4145 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4146 (Subtarget.getTargetTriple().isMacOSX() &&
4147 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
4148 (Subtarget.isTargetELF() && !isPPC64 &&
4149 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4150 // PC-relative references to external symbols should go through $stub,
4151 // unless we're building with the leopard linker or later, which
4152 // automatically synthesizes these stubs.
4153 OpFlags = PPCII::MO_PLT_OR_STUB;
4156 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
4158 needIndirectCall = false;
4162 // We'll form an invalid direct call when lowering a patchpoint; the full
4163 // sequence for an indirect call is complicated, and many of the
4164 // instructions introduced might have side effects (and, thus, can't be
4165 // removed later). The call itself will be removed as soon as the
4166 // argument/return lowering is complete, so the fact that it has the wrong
4167 // kind of operands should not really matter.
4168 needIndirectCall = false;
4171 if (needIndirectCall) {
4172 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
4173 // to do the call, we can't use PPCISD::CALL.
4174 SDValue MTCTROps[] = {Chain, Callee, InFlag};
4176 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
4177 // Function pointers in the 64-bit SVR4 ABI do not point to the function
4178 // entry point, but to the function descriptor (the function entry point
4179 // address is part of the function descriptor though).
4180 // The function descriptor is a three doubleword structure with the
4181 // following fields: function entry point, TOC base address and
4182 // environment pointer.
4183 // Thus for a call through a function pointer, the following actions need
4185 // 1. Save the TOC of the caller in the TOC save area of its stack
4186 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
4187 // 2. Load the address of the function entry point from the function
4189 // 3. Load the TOC of the callee from the function descriptor into r2.
4190 // 4. Load the environment pointer from the function descriptor into
4192 // 5. Branch to the function entry point address.
4193 // 6. On return of the callee, the TOC of the caller needs to be
4194 // restored (this is done in FinishCall()).
4196 // The loads are scheduled at the beginning of the call sequence, and the
4197 // register copies are flagged together to ensure that no other
4198 // operations can be scheduled in between. E.g. without flagging the
4199 // copies together, a TOC access in the caller could be scheduled between
4200 // the assignment of the callee TOC and the branch to the callee, which
4201 // results in the TOC access going through the TOC of the callee instead
4202 // of going through the TOC of the caller, which leads to incorrect code.
4204 // Load the address of the function entry point from the function
4206 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
4207 if (LDChain.getValueType() == MVT::Glue)
4208 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
4210 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
4212 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
4213 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
4214 false, false, LoadsInv, 8);
4216 // Load environment pointer into r11.
4217 SDValue PtrOff = DAG.getIntPtrConstant(16, dl);
4218 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
4219 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
4220 MPI.getWithOffset(16), false, false,
4223 SDValue TOCOff = DAG.getIntPtrConstant(8, dl);
4224 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
4225 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
4226 MPI.getWithOffset(8), false, false,
4229 setUsesTOCBasePtr(DAG);
4230 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
4232 Chain = TOCVal.getValue(0);
4233 InFlag = TOCVal.getValue(1);
4235 // If the function call has an explicit 'nest' parameter, it takes the
4236 // place of the environment pointer.
4238 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
4241 Chain = EnvVal.getValue(0);
4242 InFlag = EnvVal.getValue(1);
4245 MTCTROps[0] = Chain;
4246 MTCTROps[1] = LoadFuncPtr;
4247 MTCTROps[2] = InFlag;
4250 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
4251 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
4252 InFlag = Chain.getValue(1);
4255 NodeTys.push_back(MVT::Other);
4256 NodeTys.push_back(MVT::Glue);
4257 Ops.push_back(Chain);
4258 CallOpc = PPCISD::BCTRL;
4259 Callee.setNode(nullptr);
4260 // Add use of X11 (holding environment pointer)
4261 if (isSVR4ABI && isPPC64 && !isELFv2ABI && !hasNest)
4262 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
4263 // Add CTR register as callee so a bctr can be emitted later.
4265 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
4268 // If this is a direct call, pass the chain and the callee.
4269 if (Callee.getNode()) {
4270 Ops.push_back(Chain);
4271 Ops.push_back(Callee);
4273 // If this is a tail call add stack pointer delta.
4275 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
4277 // Add argument registers to the end of the list so that they are known live
4279 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4280 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4281 RegsToPass[i].second.getValueType()));
4283 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
4285 if (isSVR4ABI && isPPC64 && !IsPatchPoint) {
4286 setUsesTOCBasePtr(DAG);
4287 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
4294 bool isLocalCall(const SDValue &Callee)
4296 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4297 return G->getGlobal()->isStrongDefinitionForLinker();
4302 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
4303 CallingConv::ID CallConv, bool isVarArg,
4304 const SmallVectorImpl<ISD::InputArg> &Ins,
4305 SDLoc dl, SelectionDAG &DAG,
4306 SmallVectorImpl<SDValue> &InVals) const {
4308 SmallVector<CCValAssign, 16> RVLocs;
4309 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
4311 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
4313 // Copy all of the result registers out of their specified physreg.
4314 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4315 CCValAssign &VA = RVLocs[i];
4316 assert(VA.isRegLoc() && "Can only return in registers!");
4318 SDValue Val = DAG.getCopyFromReg(Chain, dl,
4319 VA.getLocReg(), VA.getLocVT(), InFlag);
4320 Chain = Val.getValue(1);
4321 InFlag = Val.getValue(2);
4323 switch (VA.getLocInfo()) {
4324 default: llvm_unreachable("Unknown loc info!");
4325 case CCValAssign::Full: break;
4326 case CCValAssign::AExt:
4327 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4329 case CCValAssign::ZExt:
4330 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
4331 DAG.getValueType(VA.getValVT()));
4332 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4334 case CCValAssign::SExt:
4335 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
4336 DAG.getValueType(VA.getValVT()));
4337 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4341 InVals.push_back(Val);
4348 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
4349 bool isTailCall, bool isVarArg, bool IsPatchPoint,
4350 bool hasNest, SelectionDAG &DAG,
4351 SmallVector<std::pair<unsigned, SDValue>, 8>
4353 SDValue InFlag, SDValue Chain,
4354 SDValue CallSeqStart, SDValue &Callee,
4355 int SPDiff, unsigned NumBytes,
4356 const SmallVectorImpl<ISD::InputArg> &Ins,
4357 SmallVectorImpl<SDValue> &InVals,
4358 ImmutableCallSite *CS) const {
4360 std::vector<EVT> NodeTys;
4361 SmallVector<SDValue, 8> Ops;
4362 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
4363 SPDiff, isTailCall, IsPatchPoint, hasNest,
4364 RegsToPass, Ops, NodeTys, CS, Subtarget);
4366 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
4367 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
4368 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
4370 // When performing tail call optimization the callee pops its arguments off
4371 // the stack. Account for this here so these bytes can be pushed back on in
4372 // PPCFrameLowering::eliminateCallFramePseudoInstr.
4373 int BytesCalleePops =
4374 (CallConv == CallingConv::Fast &&
4375 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
4377 // Add a register mask operand representing the call-preserved registers.
4378 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4379 const uint32_t *Mask =
4380 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
4381 assert(Mask && "Missing call preserved mask for calling convention");
4382 Ops.push_back(DAG.getRegisterMask(Mask));
4384 if (InFlag.getNode())
4385 Ops.push_back(InFlag);
4389 assert(((Callee.getOpcode() == ISD::Register &&
4390 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
4391 Callee.getOpcode() == ISD::TargetExternalSymbol ||
4392 Callee.getOpcode() == ISD::TargetGlobalAddress ||
4393 isa<ConstantSDNode>(Callee)) &&
4394 "Expecting an global address, external symbol, absolute value or register");
4396 DAG.getMachineFunction().getFrameInfo()->setHasTailCall();
4397 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
4400 // Add a NOP immediately after the branch instruction when using the 64-bit
4401 // SVR4 ABI. At link time, if caller and callee are in a different module and
4402 // thus have a different TOC, the call will be replaced with a call to a stub
4403 // function which saves the current TOC, loads the TOC of the callee and
4404 // branches to the callee. The NOP will be replaced with a load instruction
4405 // which restores the TOC of the caller from the TOC save slot of the current
4406 // stack frame. If caller and callee belong to the same module (and have the
4407 // same TOC), the NOP will remain unchanged.
4409 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
4411 if (CallOpc == PPCISD::BCTRL) {
4412 // This is a call through a function pointer.
4413 // Restore the caller TOC from the save area into R2.
4414 // See PrepareCall() for more information about calls through function
4415 // pointers in the 64-bit SVR4 ABI.
4416 // We are using a target-specific load with r2 hard coded, because the
4417 // result of a target-independent load would never go directly into r2,
4418 // since r2 is a reserved register (which prevents the register allocator
4419 // from allocating it), resulting in an additional register being
4420 // allocated and an unnecessary move instruction being generated.
4421 CallOpc = PPCISD::BCTRL_LOAD_TOC;
4423 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4424 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
4425 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
4426 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
4427 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
4429 // The address needs to go after the chain input but before the flag (or
4430 // any other variadic arguments).
4431 Ops.insert(std::next(Ops.begin()), AddTOC);
4432 } else if ((CallOpc == PPCISD::CALL) &&
4433 (!isLocalCall(Callee) ||
4434 DAG.getTarget().getRelocationModel() == Reloc::PIC_))
4435 // Otherwise insert NOP for non-local calls.
4436 CallOpc = PPCISD::CALL_NOP;
4439 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
4440 InFlag = Chain.getValue(1);
4442 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4443 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
4446 InFlag = Chain.getValue(1);
4448 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
4449 Ins, dl, DAG, InVals);
4453 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
4454 SmallVectorImpl<SDValue> &InVals) const {
4455 SelectionDAG &DAG = CLI.DAG;
4457 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
4458 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4459 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4460 SDValue Chain = CLI.Chain;
4461 SDValue Callee = CLI.Callee;
4462 bool &isTailCall = CLI.IsTailCall;
4463 CallingConv::ID CallConv = CLI.CallConv;
4464 bool isVarArg = CLI.IsVarArg;
4465 bool IsPatchPoint = CLI.IsPatchPoint;
4466 ImmutableCallSite *CS = CLI.CS;
4469 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
4472 if (!isTailCall && CS && CS->isMustTailCall())
4473 report_fatal_error("failed to perform tail call elimination on a call "
4474 "site marked musttail");
4476 if (Subtarget.isSVR4ABI()) {
4477 if (Subtarget.isPPC64())
4478 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4479 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4480 dl, DAG, InVals, CS);
4482 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4483 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4484 dl, DAG, InVals, CS);
4487 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4488 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4489 dl, DAG, InVals, CS);
4493 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4494 CallingConv::ID CallConv, bool isVarArg,
4495 bool isTailCall, bool IsPatchPoint,
4496 const SmallVectorImpl<ISD::OutputArg> &Outs,
4497 const SmallVectorImpl<SDValue> &OutVals,
4498 const SmallVectorImpl<ISD::InputArg> &Ins,
4499 SDLoc dl, SelectionDAG &DAG,
4500 SmallVectorImpl<SDValue> &InVals,
4501 ImmutableCallSite *CS) const {
4502 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4503 // of the 32-bit SVR4 ABI stack frame layout.
4505 assert((CallConv == CallingConv::C ||
4506 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4508 unsigned PtrByteSize = 4;
4510 MachineFunction &MF = DAG.getMachineFunction();
4512 // Mark this function as potentially containing a function that contains a
4513 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4514 // and restoring the callers stack pointer in this functions epilog. This is
4515 // done because by tail calling the called function might overwrite the value
4516 // in this function's (MF) stack pointer stack slot 0(SP).
4517 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4518 CallConv == CallingConv::Fast)
4519 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4521 // Count how many bytes are to be pushed on the stack, including the linkage
4522 // area, parameter list area and the part of the local variable space which
4523 // contains copies of aggregates which are passed by value.
4525 // Assign locations to all of the outgoing arguments.
4526 SmallVector<CCValAssign, 16> ArgLocs;
4527 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4530 // Reserve space for the linkage area on the stack.
4531 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
4535 // Handle fixed and variable vector arguments differently.
4536 // Fixed vector arguments go into registers as long as registers are
4537 // available. Variable vector arguments always go into memory.
4538 unsigned NumArgs = Outs.size();
4540 for (unsigned i = 0; i != NumArgs; ++i) {
4541 MVT ArgVT = Outs[i].VT;
4542 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4545 if (Outs[i].IsFixed) {
4546 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4549 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4555 errs() << "Call operand #" << i << " has unhandled type "
4556 << EVT(ArgVT).getEVTString() << "\n";
4558 llvm_unreachable(nullptr);
4562 // All arguments are treated the same.
4563 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4566 // Assign locations to all of the outgoing aggregate by value arguments.
4567 SmallVector<CCValAssign, 16> ByValArgLocs;
4568 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4569 ByValArgLocs, *DAG.getContext());
4571 // Reserve stack space for the allocations in CCInfo.
4572 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4574 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4576 // Size of the linkage area, parameter list area and the part of the local
4577 // space variable where copies of aggregates which are passed by value are
4579 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4581 // Calculate by how many bytes the stack has to be adjusted in case of tail
4582 // call optimization.
4583 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4585 // Adjust the stack pointer for the new arguments...
4586 // These operations are automatically eliminated by the prolog/epilog pass
4587 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4589 SDValue CallSeqStart = Chain;
4591 // Load the return address and frame pointer so it can be moved somewhere else
4594 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4597 // Set up a copy of the stack pointer for use loading and storing any
4598 // arguments that may not fit in the registers available for argument
4600 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4602 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4603 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4604 SmallVector<SDValue, 8> MemOpChains;
4606 bool seenFloatArg = false;
4607 // Walk the register/memloc assignments, inserting copies/loads.
4608 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4611 CCValAssign &VA = ArgLocs[i];
4612 SDValue Arg = OutVals[i];
4613 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4615 if (Flags.isByVal()) {
4616 // Argument is an aggregate which is passed by value, thus we need to
4617 // create a copy of it in the local variable space of the current stack
4618 // frame (which is the stack frame of the caller) and pass the address of
4619 // this copy to the callee.
4620 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4621 CCValAssign &ByValVA = ByValArgLocs[j++];
4622 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4624 // Memory reserved in the local variable space of the callers stack frame.
4625 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4627 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4628 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4631 // Create a copy of the argument in the local area of the current
4633 SDValue MemcpyCall =
4634 CreateCopyOfByValArgument(Arg, PtrOff,
4635 CallSeqStart.getNode()->getOperand(0),
4638 // This must go outside the CALLSEQ_START..END.
4639 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4640 CallSeqStart.getNode()->getOperand(1),
4642 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4643 NewCallSeqStart.getNode());
4644 Chain = CallSeqStart = NewCallSeqStart;
4646 // Pass the address of the aggregate copy on the stack either in a
4647 // physical register or in the parameter list area of the current stack
4648 // frame to the callee.
4652 if (VA.isRegLoc()) {
4653 if (Arg.getValueType() == MVT::i1)
4654 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4656 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4657 // Put argument in a physical register.
4658 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4660 // Put argument in the parameter list area of the current stack frame.
4661 assert(VA.isMemLoc());
4662 unsigned LocMemOffset = VA.getLocMemOffset();
4665 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4666 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4669 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4670 MachinePointerInfo(),
4673 // Calculate and remember argument location.
4674 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4680 if (!MemOpChains.empty())
4681 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4683 // Build a sequence of copy-to-reg nodes chained together with token chain
4684 // and flag operands which copy the outgoing args into the appropriate regs.
4686 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4687 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4688 RegsToPass[i].second, InFlag);
4689 InFlag = Chain.getValue(1);
4692 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4695 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4696 SDValue Ops[] = { Chain, InFlag };
4698 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4699 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4701 InFlag = Chain.getValue(1);
4705 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4706 false, TailCallArguments);
4708 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
4709 /* unused except on PPC64 ELFv1 */ false, DAG,
4710 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4711 NumBytes, Ins, InVals, CS);
4714 // Copy an argument into memory, being careful to do this outside the
4715 // call sequence for the call to which the argument belongs.
4717 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4718 SDValue CallSeqStart,
4719 ISD::ArgFlagsTy Flags,
4722 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4723 CallSeqStart.getNode()->getOperand(0),
4725 // The MEMCPY must go outside the CALLSEQ_START..END.
4726 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4727 CallSeqStart.getNode()->getOperand(1),
4729 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4730 NewCallSeqStart.getNode());
4731 return NewCallSeqStart;
4735 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4736 CallingConv::ID CallConv, bool isVarArg,
4737 bool isTailCall, bool IsPatchPoint,
4738 const SmallVectorImpl<ISD::OutputArg> &Outs,
4739 const SmallVectorImpl<SDValue> &OutVals,
4740 const SmallVectorImpl<ISD::InputArg> &Ins,
4741 SDLoc dl, SelectionDAG &DAG,
4742 SmallVectorImpl<SDValue> &InVals,
4743 ImmutableCallSite *CS) const {
4745 bool isELFv2ABI = Subtarget.isELFv2ABI();
4746 bool isLittleEndian = Subtarget.isLittleEndian();
4747 unsigned NumOps = Outs.size();
4748 bool hasNest = false;
4750 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4751 unsigned PtrByteSize = 8;
4753 MachineFunction &MF = DAG.getMachineFunction();
4755 // Mark this function as potentially containing a function that contains a
4756 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4757 // and restoring the callers stack pointer in this functions epilog. This is
4758 // done because by tail calling the called function might overwrite the value
4759 // in this function's (MF) stack pointer stack slot 0(SP).
4760 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4761 CallConv == CallingConv::Fast)
4762 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4764 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
4765 "fastcc not supported on varargs functions");
4767 // Count how many bytes are to be pushed on the stack, including the linkage
4768 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4769 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4770 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4771 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4772 unsigned NumBytes = LinkageSize;
4773 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4774 unsigned &QFPR_idx = FPR_idx;
4776 static const MCPhysReg GPR[] = {
4777 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4778 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4780 static const MCPhysReg VR[] = {
4781 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4782 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4784 static const MCPhysReg VSRH[] = {
4785 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4786 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4789 const unsigned NumGPRs = array_lengthof(GPR);
4790 const unsigned NumFPRs = 13;
4791 const unsigned NumVRs = array_lengthof(VR);
4792 const unsigned NumQFPRs = NumFPRs;
4794 // When using the fast calling convention, we don't provide backing for
4795 // arguments that will be in registers.
4796 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
4798 // Add up all the space actually used.
4799 for (unsigned i = 0; i != NumOps; ++i) {
4800 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4801 EVT ArgVT = Outs[i].VT;
4802 EVT OrigVT = Outs[i].ArgVT;
4807 if (CallConv == CallingConv::Fast) {
4808 if (Flags.isByVal())
4809 NumGPRsUsed += (Flags.getByValSize()+7)/8;
4811 switch (ArgVT.getSimpleVT().SimpleTy) {
4812 default: llvm_unreachable("Unexpected ValueType for argument!");
4816 if (++NumGPRsUsed <= NumGPRs)
4825 if (++NumVRsUsed <= NumVRs)
4829 // When using QPX, this is handled like a FP register, otherwise, it
4830 // is an Altivec register.
4831 if (Subtarget.hasQPX()) {
4832 if (++NumFPRsUsed <= NumFPRs)
4835 if (++NumVRsUsed <= NumVRs)
4841 case MVT::v4f64: // QPX
4842 case MVT::v4i1: // QPX
4843 if (++NumFPRsUsed <= NumFPRs)
4849 /* Respect alignment of argument on the stack. */
4851 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4852 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4854 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4855 if (Flags.isInConsecutiveRegsLast())
4856 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4859 unsigned NumBytesActuallyUsed = NumBytes;
4861 // The prolog code of the callee may store up to 8 GPR argument registers to
4862 // the stack, allowing va_start to index over them in memory if its varargs.
4863 // Because we cannot tell if this is needed on the caller side, we have to
4864 // conservatively assume that it is needed. As such, make sure we have at
4865 // least enough stack space for the caller to store the 8 GPRs.
4866 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4867 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4869 // Tail call needs the stack to be aligned.
4870 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4871 CallConv == CallingConv::Fast)
4872 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4874 // Calculate by how many bytes the stack has to be adjusted in case of tail
4875 // call optimization.
4876 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4878 // To protect arguments on the stack from being clobbered in a tail call,
4879 // force all the loads to happen before doing any other lowering.
4881 Chain = DAG.getStackArgumentTokenFactor(Chain);
4883 // Adjust the stack pointer for the new arguments...
4884 // These operations are automatically eliminated by the prolog/epilog pass
4885 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4887 SDValue CallSeqStart = Chain;
4889 // Load the return address and frame pointer so it can be move somewhere else
4892 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4895 // Set up a copy of the stack pointer for use loading and storing any
4896 // arguments that may not fit in the registers available for argument
4898 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4900 // Figure out which arguments are going to go in registers, and which in
4901 // memory. Also, if this is a vararg function, floating point operations
4902 // must be stored to our stack, and loaded into integer regs as well, if
4903 // any integer regs are available for argument passing.
4904 unsigned ArgOffset = LinkageSize;
4906 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4907 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4909 SmallVector<SDValue, 8> MemOpChains;
4910 for (unsigned i = 0; i != NumOps; ++i) {
4911 SDValue Arg = OutVals[i];
4912 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4913 EVT ArgVT = Outs[i].VT;
4914 EVT OrigVT = Outs[i].ArgVT;
4916 // PtrOff will be used to store the current argument to the stack if a
4917 // register cannot be found for it.
4920 // We re-align the argument offset for each argument, except when using the
4921 // fast calling convention, when we need to make sure we do that only when
4922 // we'll actually use a stack slot.
4923 auto ComputePtrOff = [&]() {
4924 /* Respect alignment of argument on the stack. */
4926 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4927 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4929 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
4931 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4934 if (CallConv != CallingConv::Fast) {
4937 /* Compute GPR index associated with argument offset. */
4938 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4939 GPR_idx = std::min(GPR_idx, NumGPRs);
4942 // Promote integers to 64-bit values.
4943 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4944 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4945 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4946 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4949 // FIXME memcpy is used way more than necessary. Correctness first.
4950 // Note: "by value" is code for passing a structure by value, not
4952 if (Flags.isByVal()) {
4953 // Note: Size includes alignment padding, so
4954 // struct x { short a; char b; }
4955 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4956 // These are the proper values we need for right-justifying the
4957 // aggregate in a parameter register.
4958 unsigned Size = Flags.getByValSize();
4960 // An empty aggregate parameter takes up no storage and no
4965 if (CallConv == CallingConv::Fast)
4968 // All aggregates smaller than 8 bytes must be passed right-justified.
4969 if (Size==1 || Size==2 || Size==4) {
4970 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4971 if (GPR_idx != NumGPRs) {
4972 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4973 MachinePointerInfo(), VT,
4974 false, false, false, 0);
4975 MemOpChains.push_back(Load.getValue(1));
4976 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4978 ArgOffset += PtrByteSize;
4983 if (GPR_idx == NumGPRs && Size < 8) {
4984 SDValue AddPtr = PtrOff;
4985 if (!isLittleEndian) {
4986 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
4987 PtrOff.getValueType());
4988 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4990 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4993 ArgOffset += PtrByteSize;
4996 // Copy entire object into memory. There are cases where gcc-generated
4997 // code assumes it is there, even if it could be put entirely into
4998 // registers. (This is not what the doc says.)
5000 // FIXME: The above statement is likely due to a misunderstanding of the
5001 // documents. All arguments must be copied into the parameter area BY
5002 // THE CALLEE in the event that the callee takes the address of any
5003 // formal argument. That has not yet been implemented. However, it is
5004 // reasonable to use the stack area as a staging area for the register
5007 // Skip this for small aggregates, as we will use the same slot for a
5008 // right-justified copy, below.
5010 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5014 // When a register is available, pass a small aggregate right-justified.
5015 if (Size < 8 && GPR_idx != NumGPRs) {
5016 // The easiest way to get this right-justified in a register
5017 // is to copy the structure into the rightmost portion of a
5018 // local variable slot, then load the whole slot into the
5020 // FIXME: The memcpy seems to produce pretty awful code for
5021 // small aggregates, particularly for packed ones.
5022 // FIXME: It would be preferable to use the slot in the
5023 // parameter save area instead of a new local variable.
5024 SDValue AddPtr = PtrOff;
5025 if (!isLittleEndian) {
5026 SDValue Const = DAG.getConstant(8 - Size, dl, PtrOff.getValueType());
5027 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5029 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5033 // Load the slot into the register.
5034 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
5035 MachinePointerInfo(),
5036 false, false, false, 0);
5037 MemOpChains.push_back(Load.getValue(1));
5038 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5040 // Done with this argument.
5041 ArgOffset += PtrByteSize;
5045 // For aggregates larger than PtrByteSize, copy the pieces of the
5046 // object that fit into registers from the parameter save area.
5047 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5048 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5049 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5050 if (GPR_idx != NumGPRs) {
5051 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5052 MachinePointerInfo(),
5053 false, false, false, 0);
5054 MemOpChains.push_back(Load.getValue(1));
5055 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5056 ArgOffset += PtrByteSize;
5058 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5065 switch (Arg.getSimpleValueType().SimpleTy) {
5066 default: llvm_unreachable("Unexpected ValueType for argument!");
5070 if (Flags.isNest()) {
5071 // The 'nest' parameter, if any, is passed in R11.
5072 RegsToPass.push_back(std::make_pair(PPC::X11, Arg));
5077 // These can be scalar arguments or elements of an integer array type
5078 // passed directly. Clang may use those instead of "byval" aggregate
5079 // types to avoid forcing arguments to memory unnecessarily.
5080 if (GPR_idx != NumGPRs) {
5081 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5083 if (CallConv == CallingConv::Fast)
5086 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5087 true, isTailCall, false, MemOpChains,
5088 TailCallArguments, dl);
5089 if (CallConv == CallingConv::Fast)
5090 ArgOffset += PtrByteSize;
5092 if (CallConv != CallingConv::Fast)
5093 ArgOffset += PtrByteSize;
5097 // These can be scalar arguments or elements of a float array type
5098 // passed directly. The latter are used to implement ELFv2 homogenous
5099 // float aggregates.
5101 // Named arguments go into FPRs first, and once they overflow, the
5102 // remaining arguments go into GPRs and then the parameter save area.
5103 // Unnamed arguments for vararg functions always go to GPRs and
5104 // then the parameter save area. For now, put all arguments to vararg
5105 // routines always in both locations (FPR *and* GPR or stack slot).
5106 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
5107 bool NeededLoad = false;
5109 // First load the argument into the next available FPR.
5110 if (FPR_idx != NumFPRs)
5111 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5113 // Next, load the argument into GPR or stack slot if needed.
5114 if (!NeedGPROrStack)
5116 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
5117 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
5118 // once we support fp <-> gpr moves.
5120 // In the non-vararg case, this can only ever happen in the
5121 // presence of f32 array types, since otherwise we never run
5122 // out of FPRs before running out of GPRs.
5125 // Double values are always passed in a single GPR.
5126 if (Arg.getValueType() != MVT::f32) {
5127 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
5129 // Non-array float values are extended and passed in a GPR.
5130 } else if (!Flags.isInConsecutiveRegs()) {
5131 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5132 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5134 // If we have an array of floats, we collect every odd element
5135 // together with its predecessor into one GPR.
5136 } else if (ArgOffset % PtrByteSize != 0) {
5138 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
5139 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5140 if (!isLittleEndian)
5142 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5144 // The final element, if even, goes into the first half of a GPR.
5145 } else if (Flags.isInConsecutiveRegsLast()) {
5146 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5147 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5148 if (!isLittleEndian)
5149 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
5150 DAG.getConstant(32, dl, MVT::i32));
5152 // Non-final even elements are skipped; they will be handled
5153 // together the with subsequent argument on the next go-around.
5157 if (ArgVal.getNode())
5158 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
5160 if (CallConv == CallingConv::Fast)
5163 // Single-precision floating-point values are mapped to the
5164 // second (rightmost) word of the stack doubleword.
5165 if (Arg.getValueType() == MVT::f32 &&
5166 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
5167 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5168 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5171 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5172 true, isTailCall, false, MemOpChains,
5173 TailCallArguments, dl);
5177 // When passing an array of floats, the array occupies consecutive
5178 // space in the argument area; only round up to the next doubleword
5179 // at the end of the array. Otherwise, each float takes 8 bytes.
5180 if (CallConv != CallingConv::Fast || NeededLoad) {
5181 ArgOffset += (Arg.getValueType() == MVT::f32 &&
5182 Flags.isInConsecutiveRegs()) ? 4 : 8;
5183 if (Flags.isInConsecutiveRegsLast())
5184 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
5195 if (!Subtarget.hasQPX()) {
5196 // These can be scalar arguments or elements of a vector array type
5197 // passed directly. The latter are used to implement ELFv2 homogenous
5198 // vector aggregates.
5200 // For a varargs call, named arguments go into VRs or on the stack as
5201 // usual; unnamed arguments always go to the stack or the corresponding
5202 // GPRs when within range. For now, we always put the value in both
5203 // locations (or even all three).
5205 // We could elide this store in the case where the object fits
5206 // entirely in R registers. Maybe later.
5207 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5208 MachinePointerInfo(), false, false, 0);
5209 MemOpChains.push_back(Store);
5210 if (VR_idx != NumVRs) {
5211 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5212 MachinePointerInfo(),
5213 false, false, false, 0);
5214 MemOpChains.push_back(Load.getValue(1));
5216 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5217 Arg.getSimpleValueType() == MVT::v2i64) ?
5218 VSRH[VR_idx] : VR[VR_idx];
5221 RegsToPass.push_back(std::make_pair(VReg, Load));
5224 for (unsigned i=0; i<16; i+=PtrByteSize) {
5225 if (GPR_idx == NumGPRs)
5227 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5228 DAG.getConstant(i, dl, PtrVT));
5229 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5230 false, false, false, 0);
5231 MemOpChains.push_back(Load.getValue(1));
5232 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5237 // Non-varargs Altivec params go into VRs or on the stack.
5238 if (VR_idx != NumVRs) {
5239 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5240 Arg.getSimpleValueType() == MVT::v2i64) ?
5241 VSRH[VR_idx] : VR[VR_idx];
5244 RegsToPass.push_back(std::make_pair(VReg, Arg));
5246 if (CallConv == CallingConv::Fast)
5249 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5250 true, isTailCall, true, MemOpChains,
5251 TailCallArguments, dl);
5252 if (CallConv == CallingConv::Fast)
5256 if (CallConv != CallingConv::Fast)
5261 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
5262 "Invalid QPX parameter type");
5267 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;
5269 // We could elide this store in the case where the object fits
5270 // entirely in R registers. Maybe later.
5271 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5272 MachinePointerInfo(), false, false, 0);
5273 MemOpChains.push_back(Store);
5274 if (QFPR_idx != NumQFPRs) {
5275 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl,
5276 Store, PtrOff, MachinePointerInfo(),
5277 false, false, false, 0);
5278 MemOpChains.push_back(Load.getValue(1));
5279 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Load));
5281 ArgOffset += (IsF32 ? 16 : 32);
5282 for (unsigned i = 0; i < (IsF32 ? 16U : 32U); i += PtrByteSize) {
5283 if (GPR_idx == NumGPRs)
5285 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5286 DAG.getConstant(i, dl, PtrVT));
5287 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5288 false, false, false, 0);
5289 MemOpChains.push_back(Load.getValue(1));
5290 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5295 // Non-varargs QPX params go into registers or on the stack.
5296 if (QFPR_idx != NumQFPRs) {
5297 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Arg));
5299 if (CallConv == CallingConv::Fast)
5302 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5303 true, isTailCall, true, MemOpChains,
5304 TailCallArguments, dl);
5305 if (CallConv == CallingConv::Fast)
5306 ArgOffset += (IsF32 ? 16 : 32);
5309 if (CallConv != CallingConv::Fast)
5310 ArgOffset += (IsF32 ? 16 : 32);
5316 assert(NumBytesActuallyUsed == ArgOffset);
5317 (void)NumBytesActuallyUsed;
5319 if (!MemOpChains.empty())
5320 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5322 // Check if this is an indirect call (MTCTR/BCTRL).
5323 // See PrepareCall() for more information about calls through function
5324 // pointers in the 64-bit SVR4 ABI.
5325 if (!isTailCall && !IsPatchPoint &&
5326 !isFunctionGlobalAddress(Callee) &&
5327 !isa<ExternalSymbolSDNode>(Callee)) {
5328 // Load r2 into a virtual register and store it to the TOC save area.
5329 setUsesTOCBasePtr(DAG);
5330 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
5331 // TOC save area offset.
5332 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5333 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5334 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5335 Chain = DAG.getStore(
5336 Val.getValue(1), dl, Val, AddPtr,
5337 MachinePointerInfo::getStack(DAG.getMachineFunction(), TOCSaveOffset),
5339 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
5340 // This does not mean the MTCTR instruction must use R12; it's easier
5341 // to model this as an extra parameter, so do that.
5342 if (isELFv2ABI && !IsPatchPoint)
5343 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
5346 // Build a sequence of copy-to-reg nodes chained together with token chain
5347 // and flag operands which copy the outgoing args into the appropriate regs.
5349 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5350 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5351 RegsToPass[i].second, InFlag);
5352 InFlag = Chain.getValue(1);
5356 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
5357 FPOp, true, TailCallArguments);
5359 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
5360 hasNest, DAG, RegsToPass, InFlag, Chain, CallSeqStart,
5361 Callee, SPDiff, NumBytes, Ins, InVals, CS);
5365 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
5366 CallingConv::ID CallConv, bool isVarArg,
5367 bool isTailCall, bool IsPatchPoint,
5368 const SmallVectorImpl<ISD::OutputArg> &Outs,
5369 const SmallVectorImpl<SDValue> &OutVals,
5370 const SmallVectorImpl<ISD::InputArg> &Ins,
5371 SDLoc dl, SelectionDAG &DAG,
5372 SmallVectorImpl<SDValue> &InVals,
5373 ImmutableCallSite *CS) const {
5375 unsigned NumOps = Outs.size();
5377 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5378 bool isPPC64 = PtrVT == MVT::i64;
5379 unsigned PtrByteSize = isPPC64 ? 8 : 4;
5381 MachineFunction &MF = DAG.getMachineFunction();
5383 // Mark this function as potentially containing a function that contains a
5384 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5385 // and restoring the callers stack pointer in this functions epilog. This is
5386 // done because by tail calling the called function might overwrite the value
5387 // in this function's (MF) stack pointer stack slot 0(SP).
5388 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5389 CallConv == CallingConv::Fast)
5390 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5392 // Count how many bytes are to be pushed on the stack, including the linkage
5393 // area, and parameter passing area. We start with 24/48 bytes, which is
5394 // prereserved space for [SP][CR][LR][3 x unused].
5395 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5396 unsigned NumBytes = LinkageSize;
5398 // Add up all the space actually used.
5399 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
5400 // they all go in registers, but we must reserve stack space for them for
5401 // possible use by the caller. In varargs or 64-bit calls, parameters are
5402 // assigned stack space in order, with padding so Altivec parameters are
5404 unsigned nAltivecParamsAtEnd = 0;
5405 for (unsigned i = 0; i != NumOps; ++i) {
5406 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5407 EVT ArgVT = Outs[i].VT;
5408 // Varargs Altivec parameters are padded to a 16 byte boundary.
5409 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
5410 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
5411 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
5412 if (!isVarArg && !isPPC64) {
5413 // Non-varargs Altivec parameters go after all the non-Altivec
5414 // parameters; handle those later so we know how much padding we need.
5415 nAltivecParamsAtEnd++;
5418 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
5419 NumBytes = ((NumBytes+15)/16)*16;
5421 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
5424 // Allow for Altivec parameters at the end, if needed.
5425 if (nAltivecParamsAtEnd) {
5426 NumBytes = ((NumBytes+15)/16)*16;
5427 NumBytes += 16*nAltivecParamsAtEnd;
5430 // The prolog code of the callee may store up to 8 GPR argument registers to
5431 // the stack, allowing va_start to index over them in memory if its varargs.
5432 // Because we cannot tell if this is needed on the caller side, we have to
5433 // conservatively assume that it is needed. As such, make sure we have at
5434 // least enough stack space for the caller to store the 8 GPRs.
5435 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
5437 // Tail call needs the stack to be aligned.
5438 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5439 CallConv == CallingConv::Fast)
5440 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
5442 // Calculate by how many bytes the stack has to be adjusted in case of tail
5443 // call optimization.
5444 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5446 // To protect arguments on the stack from being clobbered in a tail call,
5447 // force all the loads to happen before doing any other lowering.
5449 Chain = DAG.getStackArgumentTokenFactor(Chain);
5451 // Adjust the stack pointer for the new arguments...
5452 // These operations are automatically eliminated by the prolog/epilog pass
5453 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5455 SDValue CallSeqStart = Chain;
5457 // Load the return address and frame pointer so it can be move somewhere else
5460 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
5463 // Set up a copy of the stack pointer for use loading and storing any
5464 // arguments that may not fit in the registers available for argument
5468 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5470 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5472 // Figure out which arguments are going to go in registers, and which in
5473 // memory. Also, if this is a vararg function, floating point operations
5474 // must be stored to our stack, and loaded into integer regs as well, if
5475 // any integer regs are available for argument passing.
5476 unsigned ArgOffset = LinkageSize;
5477 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5479 static const MCPhysReg GPR_32[] = { // 32-bit registers.
5480 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
5481 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
5483 static const MCPhysReg GPR_64[] = { // 64-bit registers.
5484 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5485 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5487 static const MCPhysReg VR[] = {
5488 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5489 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5491 const unsigned NumGPRs = array_lengthof(GPR_32);
5492 const unsigned NumFPRs = 13;
5493 const unsigned NumVRs = array_lengthof(VR);
5495 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
5497 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5498 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5500 SmallVector<SDValue, 8> MemOpChains;
5501 for (unsigned i = 0; i != NumOps; ++i) {
5502 SDValue Arg = OutVals[i];
5503 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5505 // PtrOff will be used to store the current argument to the stack if a
5506 // register cannot be found for it.
5509 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
5511 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5513 // On PPC64, promote integers to 64-bit values.
5514 if (isPPC64 && Arg.getValueType() == MVT::i32) {
5515 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
5516 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5517 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
5520 // FIXME memcpy is used way more than necessary. Correctness first.
5521 // Note: "by value" is code for passing a structure by value, not
5523 if (Flags.isByVal()) {
5524 unsigned Size = Flags.getByValSize();
5525 // Very small objects are passed right-justified. Everything else is
5526 // passed left-justified.
5527 if (Size==1 || Size==2) {
5528 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
5529 if (GPR_idx != NumGPRs) {
5530 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5531 MachinePointerInfo(), VT,
5532 false, false, false, 0);
5533 MemOpChains.push_back(Load.getValue(1));
5534 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5536 ArgOffset += PtrByteSize;
5538 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
5539 PtrOff.getValueType());
5540 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5541 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5544 ArgOffset += PtrByteSize;
5548 // Copy entire object into memory. There are cases where gcc-generated
5549 // code assumes it is there, even if it could be put entirely into
5550 // registers. (This is not what the doc says.)
5551 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5555 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5556 // copy the pieces of the object that fit into registers from the
5557 // parameter save area.
5558 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5559 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5560 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5561 if (GPR_idx != NumGPRs) {
5562 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5563 MachinePointerInfo(),
5564 false, false, false, 0);
5565 MemOpChains.push_back(Load.getValue(1));
5566 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5567 ArgOffset += PtrByteSize;
5569 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5576 switch (Arg.getSimpleValueType().SimpleTy) {
5577 default: llvm_unreachable("Unexpected ValueType for argument!");
5581 if (GPR_idx != NumGPRs) {
5582 if (Arg.getValueType() == MVT::i1)
5583 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5585 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5587 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5588 isPPC64, isTailCall, false, MemOpChains,
5589 TailCallArguments, dl);
5591 ArgOffset += PtrByteSize;
5595 if (FPR_idx != NumFPRs) {
5596 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5599 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5600 MachinePointerInfo(), false, false, 0);
5601 MemOpChains.push_back(Store);
5603 // Float varargs are always shadowed in available integer registers
5604 if (GPR_idx != NumGPRs) {
5605 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5606 MachinePointerInfo(), false, false,
5608 MemOpChains.push_back(Load.getValue(1));
5609 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5611 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5612 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5613 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5614 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5615 MachinePointerInfo(),
5616 false, false, false, 0);
5617 MemOpChains.push_back(Load.getValue(1));
5618 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5621 // If we have any FPRs remaining, we may also have GPRs remaining.
5622 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5624 if (GPR_idx != NumGPRs)
5626 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5627 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5631 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5632 isPPC64, isTailCall, false, MemOpChains,
5633 TailCallArguments, dl);
5637 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5644 // These go aligned on the stack, or in the corresponding R registers
5645 // when within range. The Darwin PPC ABI doc claims they also go in
5646 // V registers; in fact gcc does this only for arguments that are
5647 // prototyped, not for those that match the ... We do it for all
5648 // arguments, seems to work.
5649 while (ArgOffset % 16 !=0) {
5650 ArgOffset += PtrByteSize;
5651 if (GPR_idx != NumGPRs)
5654 // We could elide this store in the case where the object fits
5655 // entirely in R registers. Maybe later.
5656 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5657 DAG.getConstant(ArgOffset, dl, PtrVT));
5658 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5659 MachinePointerInfo(), false, false, 0);
5660 MemOpChains.push_back(Store);
5661 if (VR_idx != NumVRs) {
5662 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5663 MachinePointerInfo(),
5664 false, false, false, 0);
5665 MemOpChains.push_back(Load.getValue(1));
5666 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5669 for (unsigned i=0; i<16; i+=PtrByteSize) {
5670 if (GPR_idx == NumGPRs)
5672 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5673 DAG.getConstant(i, dl, PtrVT));
5674 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5675 false, false, false, 0);
5676 MemOpChains.push_back(Load.getValue(1));
5677 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5682 // Non-varargs Altivec params generally go in registers, but have
5683 // stack space allocated at the end.
5684 if (VR_idx != NumVRs) {
5685 // Doesn't have GPR space allocated.
5686 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5687 } else if (nAltivecParamsAtEnd==0) {
5688 // We are emitting Altivec params in order.
5689 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5690 isPPC64, isTailCall, true, MemOpChains,
5691 TailCallArguments, dl);
5697 // If all Altivec parameters fit in registers, as they usually do,
5698 // they get stack space following the non-Altivec parameters. We
5699 // don't track this here because nobody below needs it.
5700 // If there are more Altivec parameters than fit in registers emit
5702 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5704 // Offset is aligned; skip 1st 12 params which go in V registers.
5705 ArgOffset = ((ArgOffset+15)/16)*16;
5707 for (unsigned i = 0; i != NumOps; ++i) {
5708 SDValue Arg = OutVals[i];
5709 EVT ArgType = Outs[i].VT;
5710 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5711 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5714 // We are emitting Altivec params in order.
5715 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5716 isPPC64, isTailCall, true, MemOpChains,
5717 TailCallArguments, dl);
5724 if (!MemOpChains.empty())
5725 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5727 // On Darwin, R12 must contain the address of an indirect callee. This does
5728 // not mean the MTCTR instruction must use R12; it's easier to model this as
5729 // an extra parameter, so do that.
5731 !isFunctionGlobalAddress(Callee) &&
5732 !isa<ExternalSymbolSDNode>(Callee) &&
5733 !isBLACompatibleAddress(Callee, DAG))
5734 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5735 PPC::R12), Callee));
5737 // Build a sequence of copy-to-reg nodes chained together with token chain
5738 // and flag operands which copy the outgoing args into the appropriate regs.
5740 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5741 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5742 RegsToPass[i].second, InFlag);
5743 InFlag = Chain.getValue(1);
5747 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5748 FPOp, true, TailCallArguments);
5750 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
5751 /* unused except on PPC64 ELFv1 */ false, DAG,
5752 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5753 NumBytes, Ins, InVals, CS);
5757 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5758 MachineFunction &MF, bool isVarArg,
5759 const SmallVectorImpl<ISD::OutputArg> &Outs,
5760 LLVMContext &Context) const {
5761 SmallVector<CCValAssign, 16> RVLocs;
5762 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5763 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5767 PPCTargetLowering::LowerReturn(SDValue Chain,
5768 CallingConv::ID CallConv, bool isVarArg,
5769 const SmallVectorImpl<ISD::OutputArg> &Outs,
5770 const SmallVectorImpl<SDValue> &OutVals,
5771 SDLoc dl, SelectionDAG &DAG) const {
5773 SmallVector<CCValAssign, 16> RVLocs;
5774 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5776 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5779 SmallVector<SDValue, 4> RetOps(1, Chain);
5781 // Copy the result values into the output registers.
5782 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5783 CCValAssign &VA = RVLocs[i];
5784 assert(VA.isRegLoc() && "Can only return in registers!");
5786 SDValue Arg = OutVals[i];
5788 switch (VA.getLocInfo()) {
5789 default: llvm_unreachable("Unknown loc info!");
5790 case CCValAssign::Full: break;
5791 case CCValAssign::AExt:
5792 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5794 case CCValAssign::ZExt:
5795 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5797 case CCValAssign::SExt:
5798 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5802 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5803 Flag = Chain.getValue(1);
5804 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5807 RetOps[0] = Chain; // Update chain.
5809 // Add the flag if we have it.
5811 RetOps.push_back(Flag);
5813 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5816 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5817 const PPCSubtarget &Subtarget) const {
5818 // When we pop the dynamic allocation we need to restore the SP link.
5821 // Get the corect type for pointers.
5822 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5824 // Construct the stack pointer operand.
5825 bool isPPC64 = Subtarget.isPPC64();
5826 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5827 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5829 // Get the operands for the STACKRESTORE.
5830 SDValue Chain = Op.getOperand(0);
5831 SDValue SaveSP = Op.getOperand(1);
5833 // Load the old link SP.
5834 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5835 MachinePointerInfo(),
5836 false, false, false, 0);
5838 // Restore the stack pointer.
5839 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5841 // Store the old link SP.
5842 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5846 SDValue PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG &DAG) const {
5847 MachineFunction &MF = DAG.getMachineFunction();
5848 bool isPPC64 = Subtarget.isPPC64();
5849 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
5851 // Get current frame pointer save index. The users of this index will be
5852 // primarily DYNALLOC instructions.
5853 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5854 int RASI = FI->getReturnAddrSaveIndex();
5856 // If the frame pointer save index hasn't been defined yet.
5858 // Find out what the fix offset of the frame pointer save area.
5859 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset();
5860 // Allocate the frame index for frame pointer save area.
5861 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5863 FI->setReturnAddrSaveIndex(RASI);
5865 return DAG.getFrameIndex(RASI, PtrVT);
5869 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5870 MachineFunction &MF = DAG.getMachineFunction();
5871 bool isPPC64 = Subtarget.isPPC64();
5872 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
5874 // Get current frame pointer save index. The users of this index will be
5875 // primarily DYNALLOC instructions.
5876 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5877 int FPSI = FI->getFramePointerSaveIndex();
5879 // If the frame pointer save index hasn't been defined yet.
5881 // Find out what the fix offset of the frame pointer save area.
5882 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset();
5883 // Allocate the frame index for frame pointer save area.
5884 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5886 FI->setFramePointerSaveIndex(FPSI);
5888 return DAG.getFrameIndex(FPSI, PtrVT);
5891 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5893 const PPCSubtarget &Subtarget) const {
5895 SDValue Chain = Op.getOperand(0);
5896 SDValue Size = Op.getOperand(1);
5899 // Get the corect type for pointers.
5900 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5902 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5903 DAG.getConstant(0, dl, PtrVT), Size);
5904 // Construct a node for the frame pointer save index.
5905 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5906 // Build a DYNALLOC node.
5907 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5908 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5909 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5912 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5913 SelectionDAG &DAG) const {
5915 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5916 DAG.getVTList(MVT::i32, MVT::Other),
5917 Op.getOperand(0), Op.getOperand(1));
5920 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5921 SelectionDAG &DAG) const {
5923 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5924 Op.getOperand(0), Op.getOperand(1));
5927 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5928 if (Op.getValueType().isVector())
5929 return LowerVectorLoad(Op, DAG);
5931 assert(Op.getValueType() == MVT::i1 &&
5932 "Custom lowering only for i1 loads");
5934 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5937 LoadSDNode *LD = cast<LoadSDNode>(Op);
5939 SDValue Chain = LD->getChain();
5940 SDValue BasePtr = LD->getBasePtr();
5941 MachineMemOperand *MMO = LD->getMemOperand();
5944 DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(DAG.getDataLayout()), Chain,
5945 BasePtr, MVT::i8, MMO);
5946 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5948 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5949 return DAG.getMergeValues(Ops, dl);
5952 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5953 if (Op.getOperand(1).getValueType().isVector())
5954 return LowerVectorStore(Op, DAG);
5956 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5957 "Custom lowering only for i1 stores");
5959 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5962 StoreSDNode *ST = cast<StoreSDNode>(Op);
5964 SDValue Chain = ST->getChain();
5965 SDValue BasePtr = ST->getBasePtr();
5966 SDValue Value = ST->getValue();
5967 MachineMemOperand *MMO = ST->getMemOperand();
5969 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(DAG.getDataLayout()),
5971 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5974 // FIXME: Remove this once the ANDI glue bug is fixed:
5975 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5976 assert(Op.getValueType() == MVT::i1 &&
5977 "Custom lowering only for i1 results");
5980 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5984 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5986 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5987 // Not FP? Not a fsel.
5988 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5989 !Op.getOperand(2).getValueType().isFloatingPoint())
5992 // We might be able to do better than this under some circumstances, but in
5993 // general, fsel-based lowering of select is a finite-math-only optimization.
5994 // For more information, see section F.3 of the 2.06 ISA specification.
5995 if (!DAG.getTarget().Options.NoInfsFPMath ||
5996 !DAG.getTarget().Options.NoNaNsFPMath)
5998 // TODO: Propagate flags from the select rather than global settings.
6000 Flags.setNoInfs(true);
6001 Flags.setNoNaNs(true);
6003 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
6005 EVT ResVT = Op.getValueType();
6006 EVT CmpVT = Op.getOperand(0).getValueType();
6007 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6008 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
6011 // If the RHS of the comparison is a 0.0, we don't need to do the
6012 // subtraction at all.
6014 if (isFloatingPointZero(RHS))
6016 default: break; // SETUO etc aren't handled by fsel.
6020 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6021 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6022 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6023 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6024 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6025 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6026 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
6029 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6032 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6033 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6034 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6037 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6040 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6041 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6042 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6043 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
6048 default: break; // SETUO etc aren't handled by fsel.
6052 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6053 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6054 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6055 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6056 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6057 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6058 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6059 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
6062 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6063 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6064 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6065 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6068 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6069 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6070 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6071 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6074 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, &Flags);
6075 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6076 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6077 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6080 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, &Flags);
6081 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6082 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6083 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6088 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
6091 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6092 SDValue Src = Op.getOperand(0);
6093 if (Src.getValueType() == MVT::f32)
6094 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6097 switch (Op.getSimpleValueType().SimpleTy) {
6098 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6101 Op.getOpcode() == ISD::FP_TO_SINT
6103 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6107 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6108 "i64 FP_TO_UINT is supported only with FPCVT");
6109 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6115 // Convert the FP value to an int value through memory.
6116 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
6117 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
6118 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
6119 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
6120 MachinePointerInfo MPI =
6121 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
6123 // Emit a store to the stack slot.
6126 MachineFunction &MF = DAG.getMachineFunction();
6127 MachineMemOperand *MMO =
6128 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
6129 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
6130 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
6131 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
6133 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
6134 MPI, false, false, 0);
6136 // Result is a load from the stack slot. If loading 4 bytes, make sure to
6138 if (Op.getValueType() == MVT::i32 && !i32Stack) {
6139 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
6140 DAG.getConstant(4, dl, FIPtr.getValueType()));
6141 MPI = MPI.getWithOffset(4);
6149 /// \brief Custom lowers floating point to integer conversions to use
6150 /// the direct move instructions available in ISA 2.07 to avoid the
6151 /// need for load/store combinations.
6152 SDValue PPCTargetLowering::LowerFP_TO_INTDirectMove(SDValue Op,
6155 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6156 SDValue Src = Op.getOperand(0);
6158 if (Src.getValueType() == MVT::f32)
6159 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6162 switch (Op.getSimpleValueType().SimpleTy) {
6163 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6166 Op.getOpcode() == ISD::FP_TO_SINT
6168 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6170 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp);
6173 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6174 "i64 FP_TO_UINT is supported only with FPCVT");
6175 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6178 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp);
6184 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
6186 if (Subtarget.hasDirectMove() && Subtarget.isPPC64())
6187 return LowerFP_TO_INTDirectMove(Op, DAG, dl);
6190 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6192 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6193 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6197 // We're trying to insert a regular store, S, and then a load, L. If the
6198 // incoming value, O, is a load, we might just be able to have our load use the
6199 // address used by O. However, we don't know if anything else will store to
6200 // that address before we can load from it. To prevent this situation, we need
6201 // to insert our load, L, into the chain as a peer of O. To do this, we give L
6202 // the same chain operand as O, we create a token factor from the chain results
6203 // of O and L, and we replace all uses of O's chain result with that token
6204 // factor (see spliceIntoChain below for this last part).
6205 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
6208 ISD::LoadExtType ET) const {
6210 if (ET == ISD::NON_EXTLOAD &&
6211 (Op.getOpcode() == ISD::FP_TO_UINT ||
6212 Op.getOpcode() == ISD::FP_TO_SINT) &&
6213 isOperationLegalOrCustom(Op.getOpcode(),
6214 Op.getOperand(0).getValueType())) {
6216 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6220 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
6221 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
6222 LD->isNonTemporal())
6224 if (LD->getMemoryVT() != MemVT)
6227 RLI.Ptr = LD->getBasePtr();
6228 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
6229 assert(LD->getAddressingMode() == ISD::PRE_INC &&
6230 "Non-pre-inc AM on PPC?");
6231 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
6235 RLI.Chain = LD->getChain();
6236 RLI.MPI = LD->getPointerInfo();
6237 RLI.IsInvariant = LD->isInvariant();
6238 RLI.Alignment = LD->getAlignment();
6239 RLI.AAInfo = LD->getAAInfo();
6240 RLI.Ranges = LD->getRanges();
6242 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
6246 // Given the head of the old chain, ResChain, insert a token factor containing
6247 // it and NewResChain, and make users of ResChain now be users of that token
6249 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
6250 SDValue NewResChain,
6251 SelectionDAG &DAG) const {
6255 SDLoc dl(NewResChain);
6257 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6258 NewResChain, DAG.getUNDEF(MVT::Other));
6259 assert(TF.getNode() != NewResChain.getNode() &&
6260 "A new TF really is required here");
6262 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
6263 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
6266 /// \brief Custom lowers integer to floating point conversions to use
6267 /// the direct move instructions available in ISA 2.07 to avoid the
6268 /// need for load/store combinations.
6269 SDValue PPCTargetLowering::LowerINT_TO_FPDirectMove(SDValue Op,
6272 assert((Op.getValueType() == MVT::f32 ||
6273 Op.getValueType() == MVT::f64) &&
6274 "Invalid floating point type as target of conversion");
6275 assert(Subtarget.hasFPCVT() &&
6276 "Int to FP conversions with direct moves require FPCVT");
6278 SDValue Src = Op.getOperand(0);
6279 bool SinglePrec = Op.getValueType() == MVT::f32;
6280 bool WordInt = Src.getSimpleValueType().SimpleTy == MVT::i32;
6281 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP;
6282 unsigned ConvOp = Signed ? (SinglePrec ? PPCISD::FCFIDS : PPCISD::FCFID) :
6283 (SinglePrec ? PPCISD::FCFIDUS : PPCISD::FCFIDU);
6286 FP = DAG.getNode(Signed ? PPCISD::MTVSRA : PPCISD::MTVSRZ,
6288 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6291 FP = DAG.getNode(PPCISD::MTVSRA, dl, MVT::f64, Src);
6292 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6298 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
6299 SelectionDAG &DAG) const {
6302 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) {
6303 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64)
6306 SDValue Value = Op.getOperand(0);
6307 // The values are now known to be -1 (false) or 1 (true). To convert this
6308 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
6309 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
6310 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
6312 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
6313 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64, FPHalfs, FPHalfs,
6316 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
6318 if (Op.getValueType() != MVT::v4f64)
6319 Value = DAG.getNode(ISD::FP_ROUND, dl,
6320 Op.getValueType(), Value,
6321 DAG.getIntPtrConstant(1, dl));
6325 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
6326 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
6329 if (Op.getOperand(0).getValueType() == MVT::i1)
6330 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
6331 DAG.getConstantFP(1.0, dl, Op.getValueType()),
6332 DAG.getConstantFP(0.0, dl, Op.getValueType()));
6334 // If we have direct moves, we can do all the conversion, skip the store/load
6335 // however, without FPCVT we can't do most conversions.
6336 if (Subtarget.hasDirectMove() && Subtarget.isPPC64() && Subtarget.hasFPCVT())
6337 return LowerINT_TO_FPDirectMove(Op, DAG, dl);
6339 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
6340 "UINT_TO_FP is supported only with FPCVT");
6342 // If we have FCFIDS, then use it when converting to single-precision.
6343 // Otherwise, convert to double-precision and then round.
6344 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6345 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
6347 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
6349 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6353 if (Op.getOperand(0).getValueType() == MVT::i64) {
6354 SDValue SINT = Op.getOperand(0);
6355 // When converting to single-precision, we actually need to convert
6356 // to double-precision first and then round to single-precision.
6357 // To avoid double-rounding effects during that operation, we have
6358 // to prepare the input operand. Bits that might be truncated when
6359 // converting to double-precision are replaced by a bit that won't
6360 // be lost at this stage, but is below the single-precision rounding
6363 // However, if -enable-unsafe-fp-math is in effect, accept double
6364 // rounding to avoid the extra overhead.
6365 if (Op.getValueType() == MVT::f32 &&
6366 !Subtarget.hasFPCVT() &&
6367 !DAG.getTarget().Options.UnsafeFPMath) {
6369 // Twiddle input to make sure the low 11 bits are zero. (If this
6370 // is the case, we are guaranteed the value will fit into the 53 bit
6371 // mantissa of an IEEE double-precision value without rounding.)
6372 // If any of those low 11 bits were not zero originally, make sure
6373 // bit 12 (value 2048) is set instead, so that the final rounding
6374 // to single-precision gets the correct result.
6375 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6376 SINT, DAG.getConstant(2047, dl, MVT::i64));
6377 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
6378 Round, DAG.getConstant(2047, dl, MVT::i64));
6379 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
6380 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6381 Round, DAG.getConstant(-2048, dl, MVT::i64));
6383 // However, we cannot use that value unconditionally: if the magnitude
6384 // of the input value is small, the bit-twiddling we did above might
6385 // end up visibly changing the output. Fortunately, in that case, we
6386 // don't need to twiddle bits since the original input will convert
6387 // exactly to double-precision floating-point already. Therefore,
6388 // construct a conditional to use the original value if the top 11
6389 // bits are all sign-bit copies, and use the rounded value computed
6391 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
6392 SINT, DAG.getConstant(53, dl, MVT::i32));
6393 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
6394 Cond, DAG.getConstant(1, dl, MVT::i64));
6395 Cond = DAG.getSetCC(dl, MVT::i32,
6396 Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT);
6398 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
6404 MachineFunction &MF = DAG.getMachineFunction();
6405 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
6406 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6407 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6409 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6410 } else if (Subtarget.hasLFIWAX() &&
6411 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
6412 MachineMemOperand *MMO =
6413 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6414 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6415 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6416 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
6417 DAG.getVTList(MVT::f64, MVT::Other),
6418 Ops, MVT::i32, MMO);
6419 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6420 } else if (Subtarget.hasFPCVT() &&
6421 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
6422 MachineMemOperand *MMO =
6423 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6424 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6425 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6426 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
6427 DAG.getVTList(MVT::f64, MVT::Other),
6428 Ops, MVT::i32, MMO);
6429 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6430 } else if (((Subtarget.hasLFIWAX() &&
6431 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
6432 (Subtarget.hasFPCVT() &&
6433 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
6434 SINT.getOperand(0).getValueType() == MVT::i32) {
6435 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6436 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
6438 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6439 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6441 SDValue Store = DAG.getStore(
6442 DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
6443 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6446 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6447 "Expected an i32 store");
6452 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6455 MachineMemOperand *MMO =
6456 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6457 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6458 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6459 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
6460 PPCISD::LFIWZX : PPCISD::LFIWAX,
6461 dl, DAG.getVTList(MVT::f64, MVT::Other),
6462 Ops, MVT::i32, MMO);
6464 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
6466 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
6468 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6469 FP = DAG.getNode(ISD::FP_ROUND, dl,
6470 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
6474 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
6475 "Unhandled INT_TO_FP type in custom expander!");
6476 // Since we only generate this in 64-bit mode, we can take advantage of
6477 // 64-bit registers. In particular, sign extend the input value into the
6478 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
6479 // then lfd it and fcfid it.
6480 MachineFunction &MF = DAG.getMachineFunction();
6481 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6482 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
6485 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
6488 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
6490 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6491 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6493 SDValue Store = DAG.getStore(
6494 DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
6495 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6498 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6499 "Expected an i32 store");
6504 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6508 MachineMemOperand *MMO =
6509 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6510 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6511 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6512 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
6513 PPCISD::LFIWZX : PPCISD::LFIWAX,
6514 dl, DAG.getVTList(MVT::f64, MVT::Other),
6515 Ops, MVT::i32, MMO);
6517 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
6519 assert(Subtarget.isPPC64() &&
6520 "i32->FP without LFIWAX supported only on PPC64");
6522 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
6523 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6525 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
6528 // STD the extended value into the stack slot.
6529 SDValue Store = DAG.getStore(
6530 DAG.getEntryNode(), dl, Ext64, FIdx,
6531 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6534 // Load the value as a double.
6536 MVT::f64, dl, Store, FIdx,
6537 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6538 false, false, false, 0);
6541 // FCFID it and return it.
6542 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
6543 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6544 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
6545 DAG.getIntPtrConstant(0, dl));
6549 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
6550 SelectionDAG &DAG) const {
6553 The rounding mode is in bits 30:31 of FPSR, and has the following
6560 FLT_ROUNDS, on the other hand, expects the following:
6567 To perform the conversion, we do:
6568 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
6571 MachineFunction &MF = DAG.getMachineFunction();
6572 EVT VT = Op.getValueType();
6573 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
6575 // Save FP Control Word to register
6577 MVT::f64, // return register
6578 MVT::Glue // unused in this context
6580 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
6582 // Save FP register to stack slot
6583 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
6584 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
6585 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
6586 StackSlot, MachinePointerInfo(), false, false,0);
6588 // Load FP Control Word from low 32 bits of stack slot.
6589 SDValue Four = DAG.getConstant(4, dl, PtrVT);
6590 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
6591 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
6592 false, false, false, 0);
6594 // Transform as necessary
6596 DAG.getNode(ISD::AND, dl, MVT::i32,
6597 CWD, DAG.getConstant(3, dl, MVT::i32));
6599 DAG.getNode(ISD::SRL, dl, MVT::i32,
6600 DAG.getNode(ISD::AND, dl, MVT::i32,
6601 DAG.getNode(ISD::XOR, dl, MVT::i32,
6602 CWD, DAG.getConstant(3, dl, MVT::i32)),
6603 DAG.getConstant(3, dl, MVT::i32)),
6604 DAG.getConstant(1, dl, MVT::i32));
6607 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
6609 return DAG.getNode((VT.getSizeInBits() < 16 ?
6610 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6613 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6614 EVT VT = Op.getValueType();
6615 unsigned BitWidth = VT.getSizeInBits();
6617 assert(Op.getNumOperands() == 3 &&
6618 VT == Op.getOperand(1).getValueType() &&
6621 // Expand into a bunch of logical ops. Note that these ops
6622 // depend on the PPC behavior for oversized shift amounts.
6623 SDValue Lo = Op.getOperand(0);
6624 SDValue Hi = Op.getOperand(1);
6625 SDValue Amt = Op.getOperand(2);
6626 EVT AmtVT = Amt.getValueType();
6628 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6629 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6630 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
6631 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
6632 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
6633 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6634 DAG.getConstant(-BitWidth, dl, AmtVT));
6635 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
6636 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6637 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
6638 SDValue OutOps[] = { OutLo, OutHi };
6639 return DAG.getMergeValues(OutOps, dl);
6642 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6643 EVT VT = Op.getValueType();
6645 unsigned BitWidth = VT.getSizeInBits();
6646 assert(Op.getNumOperands() == 3 &&
6647 VT == Op.getOperand(1).getValueType() &&
6650 // Expand into a bunch of logical ops. Note that these ops
6651 // depend on the PPC behavior for oversized shift amounts.
6652 SDValue Lo = Op.getOperand(0);
6653 SDValue Hi = Op.getOperand(1);
6654 SDValue Amt = Op.getOperand(2);
6655 EVT AmtVT = Amt.getValueType();
6657 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6658 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6659 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6660 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6661 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6662 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6663 DAG.getConstant(-BitWidth, dl, AmtVT));
6664 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
6665 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6666 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
6667 SDValue OutOps[] = { OutLo, OutHi };
6668 return DAG.getMergeValues(OutOps, dl);
6671 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6673 EVT VT = Op.getValueType();
6674 unsigned BitWidth = VT.getSizeInBits();
6675 assert(Op.getNumOperands() == 3 &&
6676 VT == Op.getOperand(1).getValueType() &&
6679 // Expand into a bunch of logical ops, followed by a select_cc.
6680 SDValue Lo = Op.getOperand(0);
6681 SDValue Hi = Op.getOperand(1);
6682 SDValue Amt = Op.getOperand(2);
6683 EVT AmtVT = Amt.getValueType();
6685 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6686 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6687 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6688 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6689 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6690 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6691 DAG.getConstant(-BitWidth, dl, AmtVT));
6692 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
6693 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
6694 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, dl, AmtVT),
6695 Tmp4, Tmp6, ISD::SETLE);
6696 SDValue OutOps[] = { OutLo, OutHi };
6697 return DAG.getMergeValues(OutOps, dl);
6700 //===----------------------------------------------------------------------===//
6701 // Vector related lowering.
6704 /// BuildSplatI - Build a canonical splati of Val with an element size of
6705 /// SplatSize. Cast the result to VT.
6706 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6707 SelectionDAG &DAG, SDLoc dl) {
6708 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
6710 static const MVT VTys[] = { // canonical VT to use for each size.
6711 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6714 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
6716 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
6720 EVT CanonicalVT = VTys[SplatSize-1];
6722 // Build a canonical splat for this value.
6723 SDValue Elt = DAG.getConstant(Val, dl, MVT::i32);
6724 SmallVector<SDValue, 8> Ops;
6725 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
6726 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
6727 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
6730 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
6731 /// specified intrinsic ID.
6732 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6733 SelectionDAG &DAG, SDLoc dl,
6734 EVT DestVT = MVT::Other) {
6735 if (DestVT == MVT::Other) DestVT = Op.getValueType();
6736 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6737 DAG.getConstant(IID, dl, MVT::i32), Op);
6740 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
6741 /// specified intrinsic ID.
6742 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6743 SelectionDAG &DAG, SDLoc dl,
6744 EVT DestVT = MVT::Other) {
6745 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
6746 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6747 DAG.getConstant(IID, dl, MVT::i32), LHS, RHS);
6750 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
6751 /// specified intrinsic ID.
6752 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6753 SDValue Op2, SelectionDAG &DAG,
6754 SDLoc dl, EVT DestVT = MVT::Other) {
6755 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6756 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6757 DAG.getConstant(IID, dl, MVT::i32), Op0, Op1, Op2);
6761 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6762 /// amount. The result has the specified value type.
6763 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6764 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6765 // Force LHS/RHS to be the right type.
6766 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6767 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6770 for (unsigned i = 0; i != 16; ++i)
6772 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6773 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6776 // If this is a case we can't handle, return null and let the default
6777 // expansion code take care of it. If we CAN select this case, and if it
6778 // selects to a single instruction, return Op. Otherwise, if we can codegen
6779 // this case more efficiently than a constant pool load, lower it to the
6780 // sequence of ops that should be used.
6781 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6782 SelectionDAG &DAG) const {
6784 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6785 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6787 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) {
6788 // We first build an i32 vector, load it into a QPX register,
6789 // then convert it to a floating-point vector and compare it
6790 // to a zero vector to get the boolean result.
6791 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6792 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6793 MachinePointerInfo PtrInfo =
6794 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6795 EVT PtrVT = getPointerTy(DAG.getDataLayout());
6796 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6798 assert(BVN->getNumOperands() == 4 &&
6799 "BUILD_VECTOR for v4i1 does not have 4 operands");
6801 bool IsConst = true;
6802 for (unsigned i = 0; i < 4; ++i) {
6803 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6804 if (!isa<ConstantSDNode>(BVN->getOperand(i))) {
6812 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), 1.0);
6814 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), -1.0);
6816 SmallVector<Constant*, 4> CV(4, NegOne);
6817 for (unsigned i = 0; i < 4; ++i) {
6818 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF)
6819 CV[i] = UndefValue::get(Type::getFloatTy(*DAG.getContext()));
6820 else if (cast<ConstantSDNode>(BVN->getOperand(i))->
6821 getConstantIntValue()->isZero())
6827 Constant *CP = ConstantVector::get(CV);
6828 SDValue CPIdx = DAG.getConstantPool(CP, getPointerTy(DAG.getDataLayout()),
6829 16 /* alignment */);
6831 SmallVector<SDValue, 2> Ops;
6832 Ops.push_back(DAG.getEntryNode());
6833 Ops.push_back(CPIdx);
6835 SmallVector<EVT, 2> ValueVTs;
6836 ValueVTs.push_back(MVT::v4i1);
6837 ValueVTs.push_back(MVT::Other); // chain
6838 SDVTList VTs = DAG.getVTList(ValueVTs);
6840 return DAG.getMemIntrinsicNode(
6841 PPCISD::QVLFSb, dl, VTs, Ops, MVT::v4f32,
6842 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
6845 SmallVector<SDValue, 4> Stores;
6846 for (unsigned i = 0; i < 4; ++i) {
6847 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6849 unsigned Offset = 4*i;
6850 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
6851 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
6853 unsigned StoreSize = BVN->getOperand(i).getValueType().getStoreSize();
6854 if (StoreSize > 4) {
6855 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
6856 BVN->getOperand(i), Idx,
6857 PtrInfo.getWithOffset(Offset),
6858 MVT::i32, false, false, 0));
6860 SDValue StoreValue = BVN->getOperand(i);
6862 StoreValue = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, StoreValue);
6864 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
6866 PtrInfo.getWithOffset(Offset),
6872 if (!Stores.empty())
6873 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
6875 StoreChain = DAG.getEntryNode();
6877 // Now load from v4i32 into the QPX register; this will extend it to
6878 // v4i64 but not yet convert it to a floating point. Nevertheless, this
6879 // is typed as v4f64 because the QPX register integer states are not
6880 // explicitly represented.
6882 SmallVector<SDValue, 2> Ops;
6883 Ops.push_back(StoreChain);
6884 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvlfiwz, dl, MVT::i32));
6885 Ops.push_back(FIdx);
6887 SmallVector<EVT, 2> ValueVTs;
6888 ValueVTs.push_back(MVT::v4f64);
6889 ValueVTs.push_back(MVT::Other); // chain
6890 SDVTList VTs = DAG.getVTList(ValueVTs);
6892 SDValue LoadedVect = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN,
6893 dl, VTs, Ops, MVT::v4i32, PtrInfo);
6894 LoadedVect = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
6895 DAG.getConstant(Intrinsic::ppc_qpx_qvfcfidu, dl, MVT::i32),
6898 SDValue FPZeros = DAG.getConstantFP(0.0, dl, MVT::f64);
6899 FPZeros = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6900 FPZeros, FPZeros, FPZeros, FPZeros);
6902 return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ);
6905 // All other QPX vectors are handled by generic code.
6906 if (Subtarget.hasQPX())
6909 // Check if this is a splat of a constant value.
6910 APInt APSplatBits, APSplatUndef;
6911 unsigned SplatBitSize;
6913 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6914 HasAnyUndefs, 0, !Subtarget.isLittleEndian()) ||
6918 unsigned SplatBits = APSplatBits.getZExtValue();
6919 unsigned SplatUndef = APSplatUndef.getZExtValue();
6920 unsigned SplatSize = SplatBitSize / 8;
6922 // First, handle single instruction cases.
6925 if (SplatBits == 0) {
6926 // Canonicalize all zero vectors to be v4i32.
6927 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6928 SDValue Z = DAG.getConstant(0, dl, MVT::i32);
6929 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6930 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6935 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6936 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6938 if (SextVal >= -16 && SextVal <= 15)
6939 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6942 // Two instruction sequences.
6944 // If this value is in the range [-32,30] and is even, use:
6945 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6946 // If this value is in the range [17,31] and is odd, use:
6947 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6948 // If this value is in the range [-31,-17] and is odd, use:
6949 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6950 // Note the last two are three-instruction sequences.
6951 if (SextVal >= -32 && SextVal <= 31) {
6952 // To avoid having these optimizations undone by constant folding,
6953 // we convert to a pseudo that will be expanded later into one of
6955 SDValue Elt = DAG.getConstant(SextVal, dl, MVT::i32);
6956 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6957 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6958 SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32);
6959 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6960 if (VT == Op.getValueType())
6963 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6966 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6967 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6969 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6970 // Make -1 and vspltisw -1:
6971 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6973 // Make the VSLW intrinsic, computing 0x8000_0000.
6974 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6977 // xor by OnesV to invert it.
6978 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6979 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6982 // Check to see if this is a wide variety of vsplti*, binop self cases.
6983 static const signed char SplatCsts[] = {
6984 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6985 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6988 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6989 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6990 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6991 int i = SplatCsts[idx];
6993 // Figure out what shift amount will be used by altivec if shifted by i in
6995 unsigned TypeShiftAmt = i & (SplatBitSize-1);
6997 // vsplti + shl self.
6998 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
6999 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7000 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7001 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
7002 Intrinsic::ppc_altivec_vslw
7004 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7005 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7008 // vsplti + srl self.
7009 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
7010 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7011 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7012 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
7013 Intrinsic::ppc_altivec_vsrw
7015 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7016 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7019 // vsplti + sra self.
7020 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
7021 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7022 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7023 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
7024 Intrinsic::ppc_altivec_vsraw
7026 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7027 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7030 // vsplti + rol self.
7031 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
7032 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
7033 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7034 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7035 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
7036 Intrinsic::ppc_altivec_vrlw
7038 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7039 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7042 // t = vsplti c, result = vsldoi t, t, 1
7043 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
7044 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7045 unsigned Amt = Subtarget.isLittleEndian() ? 15 : 1;
7046 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7048 // t = vsplti c, result = vsldoi t, t, 2
7049 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
7050 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7051 unsigned Amt = Subtarget.isLittleEndian() ? 14 : 2;
7052 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7054 // t = vsplti c, result = vsldoi t, t, 3
7055 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
7056 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7057 unsigned Amt = Subtarget.isLittleEndian() ? 13 : 3;
7058 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7065 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
7066 /// the specified operations to build the shuffle.
7067 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
7068 SDValue RHS, SelectionDAG &DAG,
7070 unsigned OpNum = (PFEntry >> 26) & 0x0F;
7071 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
7072 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
7075 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
7087 if (OpNum == OP_COPY) {
7088 if (LHSID == (1*9+2)*9+3) return LHS;
7089 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
7093 SDValue OpLHS, OpRHS;
7094 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
7095 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
7099 default: llvm_unreachable("Unknown i32 permute!");
7101 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
7102 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
7103 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
7104 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
7107 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
7108 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
7109 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
7110 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
7113 for (unsigned i = 0; i != 16; ++i)
7114 ShufIdxs[i] = (i&3)+0;
7117 for (unsigned i = 0; i != 16; ++i)
7118 ShufIdxs[i] = (i&3)+4;
7121 for (unsigned i = 0; i != 16; ++i)
7122 ShufIdxs[i] = (i&3)+8;
7125 for (unsigned i = 0; i != 16; ++i)
7126 ShufIdxs[i] = (i&3)+12;
7129 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
7131 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
7133 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
7135 EVT VT = OpLHS.getValueType();
7136 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
7137 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
7138 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
7139 return DAG.getNode(ISD::BITCAST, dl, VT, T);
7142 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
7143 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
7144 /// return the code it can be lowered into. Worst case, it can always be
7145 /// lowered into a vperm.
7146 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
7147 SelectionDAG &DAG) const {
7149 SDValue V1 = Op.getOperand(0);
7150 SDValue V2 = Op.getOperand(1);
7151 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7152 EVT VT = Op.getValueType();
7153 bool isLittleEndian = Subtarget.isLittleEndian();
7155 if (Subtarget.hasQPX()) {
7156 if (VT.getVectorNumElements() != 4)
7159 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7161 int AlignIdx = PPC::isQVALIGNIShuffleMask(SVOp);
7162 if (AlignIdx != -1) {
7163 return DAG.getNode(PPCISD::QVALIGNI, dl, VT, V1, V2,
7164 DAG.getConstant(AlignIdx, dl, MVT::i32));
7165 } else if (SVOp->isSplat()) {
7166 int SplatIdx = SVOp->getSplatIndex();
7167 if (SplatIdx >= 4) {
7172 // FIXME: If SplatIdx == 0 and the input came from a load, then there is
7175 return DAG.getNode(PPCISD::QVESPLATI, dl, VT, V1,
7176 DAG.getConstant(SplatIdx, dl, MVT::i32));
7179 // Lower this into a qvgpci/qvfperm pair.
7181 // Compute the qvgpci literal
7183 for (unsigned i = 0; i < 4; ++i) {
7184 int m = SVOp->getMaskElt(i);
7185 unsigned mm = m >= 0 ? (unsigned) m : i;
7186 idx |= mm << (3-i)*3;
7189 SDValue V3 = DAG.getNode(PPCISD::QVGPCI, dl, MVT::v4f64,
7190 DAG.getConstant(idx, dl, MVT::i32));
7191 return DAG.getNode(PPCISD::QVFPERM, dl, VT, V1, V2, V3);
7194 // Cases that are handled by instructions that take permute immediates
7195 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
7196 // selected by the instruction selector.
7197 if (V2.getOpcode() == ISD::UNDEF) {
7198 if (PPC::isSplatShuffleMask(SVOp, 1) ||
7199 PPC::isSplatShuffleMask(SVOp, 2) ||
7200 PPC::isSplatShuffleMask(SVOp, 4) ||
7201 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
7202 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
7203 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
7204 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
7205 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
7206 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
7207 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
7208 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
7209 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG) ||
7210 (Subtarget.hasP8Altivec() && (
7211 PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
7212 PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
7213 PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)))) {
7218 // Altivec has a variety of "shuffle immediates" that take two vector inputs
7219 // and produce a fixed permutation. If any of these match, do not lower to
7221 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
7222 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7223 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7224 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
7225 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7226 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7227 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7228 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7229 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7230 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7231 (Subtarget.hasP8Altivec() && (
7232 PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7233 PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
7234 PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))))
7237 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
7238 // perfect shuffle table to emit an optimal matching sequence.
7239 ArrayRef<int> PermMask = SVOp->getMask();
7241 unsigned PFIndexes[4];
7242 bool isFourElementShuffle = true;
7243 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
7244 unsigned EltNo = 8; // Start out undef.
7245 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
7246 if (PermMask[i*4+j] < 0)
7247 continue; // Undef, ignore it.
7249 unsigned ByteSource = PermMask[i*4+j];
7250 if ((ByteSource & 3) != j) {
7251 isFourElementShuffle = false;
7256 EltNo = ByteSource/4;
7257 } else if (EltNo != ByteSource/4) {
7258 isFourElementShuffle = false;
7262 PFIndexes[i] = EltNo;
7265 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
7266 // perfect shuffle vector to determine if it is cost effective to do this as
7267 // discrete instructions, or whether we should use a vperm.
7268 // For now, we skip this for little endian until such time as we have a
7269 // little-endian perfect shuffle table.
7270 if (isFourElementShuffle && !isLittleEndian) {
7271 // Compute the index in the perfect shuffle table.
7272 unsigned PFTableIndex =
7273 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
7275 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
7276 unsigned Cost = (PFEntry >> 30);
7278 // Determining when to avoid vperm is tricky. Many things affect the cost
7279 // of vperm, particularly how many times the perm mask needs to be computed.
7280 // For example, if the perm mask can be hoisted out of a loop or is already
7281 // used (perhaps because there are multiple permutes with the same shuffle
7282 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
7283 // the loop requires an extra register.
7285 // As a compromise, we only emit discrete instructions if the shuffle can be
7286 // generated in 3 or fewer operations. When we have loop information
7287 // available, if this block is within a loop, we should avoid using vperm
7288 // for 3-operation perms and use a constant pool load instead.
7290 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
7293 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
7294 // vector that will get spilled to the constant pool.
7295 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7297 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
7298 // that it is in input element units, not in bytes. Convert now.
7300 // For little endian, the order of the input vectors is reversed, and
7301 // the permutation mask is complemented with respect to 31. This is
7302 // necessary to produce proper semantics with the big-endian-biased vperm
7304 EVT EltVT = V1.getValueType().getVectorElementType();
7305 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
7307 SmallVector<SDValue, 16> ResultMask;
7308 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
7309 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
7311 for (unsigned j = 0; j != BytesPerElement; ++j)
7313 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement + j),
7316 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement + j, dl,
7320 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
7323 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7326 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7330 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
7331 /// altivec comparison. If it is, return true and fill in Opc/isDot with
7332 /// information about the intrinsic.
7333 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
7334 bool &isDot, const PPCSubtarget &Subtarget) {
7335 unsigned IntrinsicID =
7336 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
7339 switch (IntrinsicID) {
7340 default: return false;
7341 // Comparison predicates.
7342 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
7343 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
7344 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
7345 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
7346 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
7347 case Intrinsic::ppc_altivec_vcmpequd_p:
7348 if (Subtarget.hasP8Altivec()) {
7355 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
7356 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
7357 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
7358 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
7359 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
7360 case Intrinsic::ppc_altivec_vcmpgtsd_p:
7361 if (Subtarget.hasP8Altivec()) {
7368 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
7369 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
7370 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
7371 case Intrinsic::ppc_altivec_vcmpgtud_p:
7372 if (Subtarget.hasP8Altivec()) {
7380 // Normal Comparisons.
7381 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
7382 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
7383 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
7384 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
7385 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
7386 case Intrinsic::ppc_altivec_vcmpequd:
7387 if (Subtarget.hasP8Altivec()) {
7394 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
7395 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
7396 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
7397 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
7398 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
7399 case Intrinsic::ppc_altivec_vcmpgtsd:
7400 if (Subtarget.hasP8Altivec()) {
7407 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
7408 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
7409 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
7410 case Intrinsic::ppc_altivec_vcmpgtud:
7411 if (Subtarget.hasP8Altivec()) {
7422 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
7423 /// lower, do it, otherwise return null.
7424 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
7425 SelectionDAG &DAG) const {
7426 // If this is a lowered altivec predicate compare, CompareOpc is set to the
7427 // opcode number of the comparison.
7431 if (!getAltivecCompareInfo(Op, CompareOpc, isDot, Subtarget))
7432 return SDValue(); // Don't custom lower most intrinsics.
7434 // If this is a non-dot comparison, make the VCMP node and we are done.
7436 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
7437 Op.getOperand(1), Op.getOperand(2),
7438 DAG.getConstant(CompareOpc, dl, MVT::i32));
7439 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
7442 // Create the PPCISD altivec 'dot' comparison node.
7444 Op.getOperand(2), // LHS
7445 Op.getOperand(3), // RHS
7446 DAG.getConstant(CompareOpc, dl, MVT::i32)
7448 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
7449 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
7451 // Now that we have the comparison, emit a copy from the CR to a GPR.
7452 // This is flagged to the above dot comparison.
7453 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
7454 DAG.getRegister(PPC::CR6, MVT::i32),
7455 CompNode.getValue(1));
7457 // Unpack the result based on how the target uses it.
7458 unsigned BitNo; // Bit # of CR6.
7459 bool InvertBit; // Invert result?
7460 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
7461 default: // Can't happen, don't crash on invalid number though.
7462 case 0: // Return the value of the EQ bit of CR6.
7463 BitNo = 0; InvertBit = false;
7465 case 1: // Return the inverted value of the EQ bit of CR6.
7466 BitNo = 0; InvertBit = true;
7468 case 2: // Return the value of the LT bit of CR6.
7469 BitNo = 2; InvertBit = false;
7471 case 3: // Return the inverted value of the LT bit of CR6.
7472 BitNo = 2; InvertBit = true;
7476 // Shift the bit into the low position.
7477 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
7478 DAG.getConstant(8 - (3 - BitNo), dl, MVT::i32));
7480 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
7481 DAG.getConstant(1, dl, MVT::i32));
7483 // If we are supposed to, toggle the bit.
7485 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
7486 DAG.getConstant(1, dl, MVT::i32));
7490 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
7491 SelectionDAG &DAG) const {
7493 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
7494 // instructions), but for smaller types, we need to first extend up to v2i32
7495 // before doing going farther.
7496 if (Op.getValueType() == MVT::v2i64) {
7497 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
7498 if (ExtVT != MVT::v2i32) {
7499 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
7500 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
7501 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
7502 ExtVT.getVectorElementType(), 4)));
7503 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
7504 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
7505 DAG.getValueType(MVT::v2i32));
7514 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
7515 SelectionDAG &DAG) const {
7517 // Create a stack slot that is 16-byte aligned.
7518 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7519 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7520 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7521 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7523 // Store the input value into Value#0 of the stack slot.
7524 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
7525 Op.getOperand(0), FIdx, MachinePointerInfo(),
7528 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
7529 false, false, false, 0);
7532 SDValue PPCTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7533 SelectionDAG &DAG) const {
7535 SDNode *N = Op.getNode();
7537 assert(N->getOperand(0).getValueType() == MVT::v4i1 &&
7538 "Unknown extract_vector_elt type");
7540 SDValue Value = N->getOperand(0);
7542 // The first part of this is like the store lowering except that we don't
7543 // need to track the chain.
7545 // The values are now known to be -1 (false) or 1 (true). To convert this
7546 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7547 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7548 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7550 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7551 // understand how to form the extending load.
7552 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7553 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7554 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7556 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7558 // Now convert to an integer and store.
7559 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7560 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7563 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7564 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7565 MachinePointerInfo PtrInfo =
7566 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
7567 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7568 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7570 SDValue StoreChain = DAG.getEntryNode();
7571 SmallVector<SDValue, 2> Ops;
7572 Ops.push_back(StoreChain);
7573 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7574 Ops.push_back(Value);
7575 Ops.push_back(FIdx);
7577 SmallVector<EVT, 2> ValueVTs;
7578 ValueVTs.push_back(MVT::Other); // chain
7579 SDVTList VTs = DAG.getVTList(ValueVTs);
7581 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7582 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7584 // Extract the value requested.
7585 unsigned Offset = 4*cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7586 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7587 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7589 SDValue IntVal = DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7590 PtrInfo.getWithOffset(Offset),
7591 false, false, false, 0);
7593 if (!Subtarget.useCRBits())
7596 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, IntVal);
7599 /// Lowering for QPX v4i1 loads
7600 SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
7601 SelectionDAG &DAG) const {
7603 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
7604 SDValue LoadChain = LN->getChain();
7605 SDValue BasePtr = LN->getBasePtr();
7607 if (Op.getValueType() == MVT::v4f64 ||
7608 Op.getValueType() == MVT::v4f32) {
7609 EVT MemVT = LN->getMemoryVT();
7610 unsigned Alignment = LN->getAlignment();
7612 // If this load is properly aligned, then it is legal.
7613 if (Alignment >= MemVT.getStoreSize())
7616 EVT ScalarVT = Op.getValueType().getScalarType(),
7617 ScalarMemVT = MemVT.getScalarType();
7618 unsigned Stride = ScalarMemVT.getStoreSize();
7620 SmallVector<SDValue, 8> Vals, LoadChains;
7621 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7623 if (ScalarVT != ScalarMemVT)
7625 DAG.getExtLoad(LN->getExtensionType(), dl, ScalarVT, LoadChain,
7627 LN->getPointerInfo().getWithOffset(Idx*Stride),
7628 ScalarMemVT, LN->isVolatile(), LN->isNonTemporal(),
7629 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7633 DAG.getLoad(ScalarVT, dl, LoadChain, BasePtr,
7634 LN->getPointerInfo().getWithOffset(Idx*Stride),
7635 LN->isVolatile(), LN->isNonTemporal(),
7636 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7639 if (Idx == 0 && LN->isIndexed()) {
7640 assert(LN->getAddressingMode() == ISD::PRE_INC &&
7641 "Unknown addressing mode on vector load");
7642 Load = DAG.getIndexedLoad(Load, dl, BasePtr, LN->getOffset(),
7643 LN->getAddressingMode());
7646 Vals.push_back(Load);
7647 LoadChains.push_back(Load.getValue(1));
7649 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7650 DAG.getConstant(Stride, dl,
7651 BasePtr.getValueType()));
7654 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7655 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
7656 Op.getValueType(), Vals);
7658 if (LN->isIndexed()) {
7659 SDValue RetOps[] = { Value, Vals[0].getValue(1), TF };
7660 return DAG.getMergeValues(RetOps, dl);
7663 SDValue RetOps[] = { Value, TF };
7664 return DAG.getMergeValues(RetOps, dl);
7667 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower");
7668 assert(LN->isUnindexed() && "Indexed v4i1 loads are not supported");
7670 // To lower v4i1 from a byte array, we load the byte elements of the
7671 // vector and then reuse the BUILD_VECTOR logic.
7673 SmallVector<SDValue, 4> VectElmts, VectElmtChains;
7674 for (unsigned i = 0; i < 4; ++i) {
7675 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7676 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7678 VectElmts.push_back(DAG.getExtLoad(ISD::EXTLOAD,
7679 dl, MVT::i32, LoadChain, Idx,
7680 LN->getPointerInfo().getWithOffset(i),
7681 MVT::i8 /* memory type */,
7682 LN->isVolatile(), LN->isNonTemporal(),
7684 1 /* alignment */, LN->getAAInfo()));
7685 VectElmtChains.push_back(VectElmts[i].getValue(1));
7688 LoadChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, VectElmtChains);
7689 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i1, VectElmts);
7691 SDValue RVals[] = { Value, LoadChain };
7692 return DAG.getMergeValues(RVals, dl);
7695 /// Lowering for QPX v4i1 stores
7696 SDValue PPCTargetLowering::LowerVectorStore(SDValue Op,
7697 SelectionDAG &DAG) const {
7699 StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
7700 SDValue StoreChain = SN->getChain();
7701 SDValue BasePtr = SN->getBasePtr();
7702 SDValue Value = SN->getValue();
7704 if (Value.getValueType() == MVT::v4f64 ||
7705 Value.getValueType() == MVT::v4f32) {
7706 EVT MemVT = SN->getMemoryVT();
7707 unsigned Alignment = SN->getAlignment();
7709 // If this store is properly aligned, then it is legal.
7710 if (Alignment >= MemVT.getStoreSize())
7713 EVT ScalarVT = Value.getValueType().getScalarType(),
7714 ScalarMemVT = MemVT.getScalarType();
7715 unsigned Stride = ScalarMemVT.getStoreSize();
7717 SmallVector<SDValue, 8> Stores;
7718 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7719 SDValue Ex = DAG.getNode(
7720 ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, Value,
7721 DAG.getConstant(Idx, dl, getVectorIdxTy(DAG.getDataLayout())));
7723 if (ScalarVT != ScalarMemVT)
7725 DAG.getTruncStore(StoreChain, dl, Ex, BasePtr,
7726 SN->getPointerInfo().getWithOffset(Idx*Stride),
7727 ScalarMemVT, SN->isVolatile(), SN->isNonTemporal(),
7728 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7731 DAG.getStore(StoreChain, dl, Ex, BasePtr,
7732 SN->getPointerInfo().getWithOffset(Idx*Stride),
7733 SN->isVolatile(), SN->isNonTemporal(),
7734 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7736 if (Idx == 0 && SN->isIndexed()) {
7737 assert(SN->getAddressingMode() == ISD::PRE_INC &&
7738 "Unknown addressing mode on vector store");
7739 Store = DAG.getIndexedStore(Store, dl, BasePtr, SN->getOffset(),
7740 SN->getAddressingMode());
7743 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7744 DAG.getConstant(Stride, dl,
7745 BasePtr.getValueType()));
7746 Stores.push_back(Store);
7749 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7751 if (SN->isIndexed()) {
7752 SDValue RetOps[] = { TF, Stores[0].getValue(1) };
7753 return DAG.getMergeValues(RetOps, dl);
7759 assert(SN->isUnindexed() && "Indexed v4i1 stores are not supported");
7760 assert(Value.getValueType() == MVT::v4i1 && "Unknown store to lower");
7762 // The values are now known to be -1 (false) or 1 (true). To convert this
7763 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7764 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7765 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7767 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7768 // understand how to form the extending load.
7769 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7770 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7771 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7773 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7775 // Now convert to an integer and store.
7776 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7777 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7780 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7781 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7782 MachinePointerInfo PtrInfo =
7783 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
7784 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7785 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7787 SmallVector<SDValue, 2> Ops;
7788 Ops.push_back(StoreChain);
7789 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7790 Ops.push_back(Value);
7791 Ops.push_back(FIdx);
7793 SmallVector<EVT, 2> ValueVTs;
7794 ValueVTs.push_back(MVT::Other); // chain
7795 SDVTList VTs = DAG.getVTList(ValueVTs);
7797 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7798 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7800 // Move data into the byte array.
7801 SmallVector<SDValue, 4> Loads, LoadChains;
7802 for (unsigned i = 0; i < 4; ++i) {
7803 unsigned Offset = 4*i;
7804 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7805 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7807 Loads.push_back(DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7808 PtrInfo.getWithOffset(Offset),
7809 false, false, false, 0));
7810 LoadChains.push_back(Loads[i].getValue(1));
7813 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7815 SmallVector<SDValue, 4> Stores;
7816 for (unsigned i = 0; i < 4; ++i) {
7817 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7818 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7820 Stores.push_back(DAG.getTruncStore(
7821 StoreChain, dl, Loads[i], Idx, SN->getPointerInfo().getWithOffset(i),
7822 MVT::i8 /* memory type */, SN->isNonTemporal(), SN->isVolatile(),
7823 1 /* alignment */, SN->getAAInfo()));
7826 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7831 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
7833 if (Op.getValueType() == MVT::v4i32) {
7834 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7836 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
7837 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
7839 SDValue RHSSwap = // = vrlw RHS, 16
7840 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
7842 // Shrinkify inputs to v8i16.
7843 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
7844 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
7845 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
7847 // Low parts multiplied together, generating 32-bit results (we ignore the
7849 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
7850 LHS, RHS, DAG, dl, MVT::v4i32);
7852 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
7853 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
7854 // Shift the high parts up 16 bits.
7855 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
7857 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
7858 } else if (Op.getValueType() == MVT::v8i16) {
7859 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7861 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
7863 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
7864 LHS, RHS, Zero, DAG, dl);
7865 } else if (Op.getValueType() == MVT::v16i8) {
7866 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7867 bool isLittleEndian = Subtarget.isLittleEndian();
7869 // Multiply the even 8-bit parts, producing 16-bit sums.
7870 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
7871 LHS, RHS, DAG, dl, MVT::v8i16);
7872 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
7874 // Multiply the odd 8-bit parts, producing 16-bit sums.
7875 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
7876 LHS, RHS, DAG, dl, MVT::v8i16);
7877 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
7879 // Merge the results together. Because vmuleub and vmuloub are
7880 // instructions with a big-endian bias, we must reverse the
7881 // element numbering and reverse the meaning of "odd" and "even"
7882 // when generating little endian code.
7884 for (unsigned i = 0; i != 8; ++i) {
7885 if (isLittleEndian) {
7887 Ops[i*2+1] = 2*i+16;
7890 Ops[i*2+1] = 2*i+1+16;
7894 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
7896 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
7898 llvm_unreachable("Unknown mul to lower!");
7902 /// LowerOperation - Provide custom lowering hooks for some operations.
7904 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7905 switch (Op.getOpcode()) {
7906 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
7907 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7908 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7909 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7910 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7911 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7912 case ISD::SETCC: return LowerSETCC(Op, DAG);
7913 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
7914 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
7916 return LowerVASTART(Op, DAG, Subtarget);
7919 return LowerVAARG(Op, DAG, Subtarget);
7922 return LowerVACOPY(Op, DAG, Subtarget);
7924 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
7925 case ISD::DYNAMIC_STACKALLOC:
7926 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
7928 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
7929 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
7931 case ISD::LOAD: return LowerLOAD(Op, DAG);
7932 case ISD::STORE: return LowerSTORE(Op, DAG);
7933 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
7934 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
7935 case ISD::FP_TO_UINT:
7936 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
7938 case ISD::UINT_TO_FP:
7939 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
7940 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7942 // Lower 64-bit shifts.
7943 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
7944 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
7945 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
7947 // Vector-related lowering.
7948 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7949 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7950 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7951 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7952 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
7953 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7954 case ISD::MUL: return LowerMUL(Op, DAG);
7956 // For counter-based loop handling.
7957 case ISD::INTRINSIC_W_CHAIN: return SDValue();
7959 // Frame & Return address.
7960 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7961 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7965 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
7966 SmallVectorImpl<SDValue>&Results,
7967 SelectionDAG &DAG) const {
7969 switch (N->getOpcode()) {
7971 llvm_unreachable("Do not know how to custom type legalize this operation!");
7972 case ISD::READCYCLECOUNTER: {
7973 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7974 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
7976 Results.push_back(RTB);
7977 Results.push_back(RTB.getValue(1));
7978 Results.push_back(RTB.getValue(2));
7981 case ISD::INTRINSIC_W_CHAIN: {
7982 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
7983 Intrinsic::ppc_is_decremented_ctr_nonzero)
7986 assert(N->getValueType(0) == MVT::i1 &&
7987 "Unexpected result type for CTR decrement intrinsic");
7988 EVT SVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
7989 N->getValueType(0));
7990 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
7991 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
7994 Results.push_back(NewInt);
7995 Results.push_back(NewInt.getValue(1));
7999 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
8002 EVT VT = N->getValueType(0);
8004 if (VT == MVT::i64) {
8005 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
8007 Results.push_back(NewNode);
8008 Results.push_back(NewNode.getValue(1));
8012 case ISD::FP_ROUND_INREG: {
8013 assert(N->getValueType(0) == MVT::ppcf128);
8014 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
8015 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
8016 MVT::f64, N->getOperand(0),
8017 DAG.getIntPtrConstant(0, dl));
8018 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
8019 MVT::f64, N->getOperand(0),
8020 DAG.getIntPtrConstant(1, dl));
8022 // Add the two halves of the long double in round-to-zero mode.
8023 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
8025 // We know the low half is about to be thrown away, so just use something
8027 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
8031 case ISD::FP_TO_SINT:
8032 case ISD::FP_TO_UINT:
8033 // LowerFP_TO_INT() can only handle f32 and f64.
8034 if (N->getOperand(0).getValueType() == MVT::ppcf128)
8036 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
8042 //===----------------------------------------------------------------------===//
8043 // Other Lowering Code
8044 //===----------------------------------------------------------------------===//
8046 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
8047 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8048 Function *Func = Intrinsic::getDeclaration(M, Id);
8049 return Builder.CreateCall(Func, {});
8052 // The mappings for emitLeading/TrailingFence is taken from
8053 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
8054 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
8055 AtomicOrdering Ord, bool IsStore,
8056 bool IsLoad) const {
8057 if (Ord == SequentiallyConsistent)
8058 return callIntrinsic(Builder, Intrinsic::ppc_sync);
8059 if (isAtLeastRelease(Ord))
8060 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8064 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
8065 AtomicOrdering Ord, bool IsStore,
8066 bool IsLoad) const {
8067 if (IsLoad && isAtLeastAcquire(Ord))
8068 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8069 // FIXME: this is too conservative, a dependent branch + isync is enough.
8070 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
8071 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
8072 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
8077 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
8078 unsigned AtomicSize,
8079 unsigned BinOpcode) const {
8080 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8081 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8083 auto LoadMnemonic = PPC::LDARX;
8084 auto StoreMnemonic = PPC::STDCX;
8085 switch (AtomicSize) {
8087 llvm_unreachable("Unexpected size of atomic entity");
8089 LoadMnemonic = PPC::LBARX;
8090 StoreMnemonic = PPC::STBCX;
8091 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8094 LoadMnemonic = PPC::LHARX;
8095 StoreMnemonic = PPC::STHCX;
8096 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8099 LoadMnemonic = PPC::LWARX;
8100 StoreMnemonic = PPC::STWCX;
8103 LoadMnemonic = PPC::LDARX;
8104 StoreMnemonic = PPC::STDCX;
8108 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8109 MachineFunction *F = BB->getParent();
8110 MachineFunction::iterator It = BB;
8113 unsigned dest = MI->getOperand(0).getReg();
8114 unsigned ptrA = MI->getOperand(1).getReg();
8115 unsigned ptrB = MI->getOperand(2).getReg();
8116 unsigned incr = MI->getOperand(3).getReg();
8117 DebugLoc dl = MI->getDebugLoc();
8119 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8120 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8121 F->insert(It, loopMBB);
8122 F->insert(It, exitMBB);
8123 exitMBB->splice(exitMBB->begin(), BB,
8124 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8125 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8127 MachineRegisterInfo &RegInfo = F->getRegInfo();
8128 unsigned TmpReg = (!BinOpcode) ? incr :
8129 RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass
8130 : &PPC::GPRCRegClass);
8134 // fallthrough --> loopMBB
8135 BB->addSuccessor(loopMBB);
8138 // l[wd]arx dest, ptr
8139 // add r0, dest, incr
8140 // st[wd]cx. r0, ptr
8142 // fallthrough --> exitMBB
8144 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8145 .addReg(ptrA).addReg(ptrB);
8147 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
8148 BuildMI(BB, dl, TII->get(StoreMnemonic))
8149 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
8150 BuildMI(BB, dl, TII->get(PPC::BCC))
8151 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8152 BB->addSuccessor(loopMBB);
8153 BB->addSuccessor(exitMBB);
8162 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
8163 MachineBasicBlock *BB,
8164 bool is8bit, // operation
8165 unsigned BinOpcode) const {
8166 // If we support part-word atomic mnemonics, just use them
8167 if (Subtarget.hasPartwordAtomics())
8168 return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode);
8170 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8171 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8172 // In 64 bit mode we have to use 64 bits for addresses, even though the
8173 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
8174 // registers without caring whether they're 32 or 64, but here we're
8175 // doing actual arithmetic on the addresses.
8176 bool is64bit = Subtarget.isPPC64();
8177 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8179 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8180 MachineFunction *F = BB->getParent();
8181 MachineFunction::iterator It = BB;
8184 unsigned dest = MI->getOperand(0).getReg();
8185 unsigned ptrA = MI->getOperand(1).getReg();
8186 unsigned ptrB = MI->getOperand(2).getReg();
8187 unsigned incr = MI->getOperand(3).getReg();
8188 DebugLoc dl = MI->getDebugLoc();
8190 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8191 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8192 F->insert(It, loopMBB);
8193 F->insert(It, exitMBB);
8194 exitMBB->splice(exitMBB->begin(), BB,
8195 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8196 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8198 MachineRegisterInfo &RegInfo = F->getRegInfo();
8199 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8200 : &PPC::GPRCRegClass;
8201 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8202 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8203 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8204 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
8205 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8206 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8207 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8208 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8209 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
8210 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8211 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8213 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
8217 // fallthrough --> loopMBB
8218 BB->addSuccessor(loopMBB);
8220 // The 4-byte load must be aligned, while a char or short may be
8221 // anywhere in the word. Hence all this nasty bookkeeping code.
8222 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8223 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8224 // xori shift, shift1, 24 [16]
8225 // rlwinm ptr, ptr1, 0, 0, 29
8226 // slw incr2, incr, shift
8227 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8228 // slw mask, mask2, shift
8230 // lwarx tmpDest, ptr
8231 // add tmp, tmpDest, incr2
8232 // andc tmp2, tmpDest, mask
8233 // and tmp3, tmp, mask
8234 // or tmp4, tmp3, tmp2
8237 // fallthrough --> exitMBB
8238 // srw dest, tmpDest, shift
8239 if (ptrA != ZeroReg) {
8240 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8241 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8242 .addReg(ptrA).addReg(ptrB);
8246 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8247 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8248 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8249 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8251 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8252 .addReg(Ptr1Reg).addImm(0).addImm(61);
8254 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8255 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8256 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
8257 .addReg(incr).addReg(ShiftReg);
8259 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
8261 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
8262 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
8264 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
8265 .addReg(Mask2Reg).addReg(ShiftReg);
8268 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
8269 .addReg(ZeroReg).addReg(PtrReg);
8271 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
8272 .addReg(Incr2Reg).addReg(TmpDestReg);
8273 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
8274 .addReg(TmpDestReg).addReg(MaskReg);
8275 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
8276 .addReg(TmpReg).addReg(MaskReg);
8277 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
8278 .addReg(Tmp3Reg).addReg(Tmp2Reg);
8279 BuildMI(BB, dl, TII->get(PPC::STWCX))
8280 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
8281 BuildMI(BB, dl, TII->get(PPC::BCC))
8282 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8283 BB->addSuccessor(loopMBB);
8284 BB->addSuccessor(exitMBB);
8289 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
8294 llvm::MachineBasicBlock*
8295 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
8296 MachineBasicBlock *MBB) const {
8297 DebugLoc DL = MI->getDebugLoc();
8298 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8300 MachineFunction *MF = MBB->getParent();
8301 MachineRegisterInfo &MRI = MF->getRegInfo();
8303 const BasicBlock *BB = MBB->getBasicBlock();
8304 MachineFunction::iterator I = MBB;
8308 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8309 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8311 unsigned DstReg = MI->getOperand(0).getReg();
8312 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
8313 assert(RC->hasType(MVT::i32) && "Invalid destination!");
8314 unsigned mainDstReg = MRI.createVirtualRegister(RC);
8315 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
8317 MVT PVT = getPointerTy(MF->getDataLayout());
8318 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8319 "Invalid Pointer Size!");
8320 // For v = setjmp(buf), we generate
8323 // SjLjSetup mainMBB
8329 // buf[LabelOffset] = LR
8333 // v = phi(main, restore)
8336 MachineBasicBlock *thisMBB = MBB;
8337 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
8338 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
8339 MF->insert(I, mainMBB);
8340 MF->insert(I, sinkMBB);
8342 MachineInstrBuilder MIB;
8344 // Transfer the remainder of BB and its successor edges to sinkMBB.
8345 sinkMBB->splice(sinkMBB->begin(), MBB,
8346 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
8347 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
8349 // Note that the structure of the jmp_buf used here is not compatible
8350 // with that used by libc, and is not designed to be. Specifically, it
8351 // stores only those 'reserved' registers that LLVM does not otherwise
8352 // understand how to spill. Also, by convention, by the time this
8353 // intrinsic is called, Clang has already stored the frame address in the
8354 // first slot of the buffer and stack address in the third. Following the
8355 // X86 target code, we'll store the jump address in the second slot. We also
8356 // need to save the TOC pointer (R2) to handle jumps between shared
8357 // libraries, and that will be stored in the fourth slot. The thread
8358 // identifier (R13) is not affected.
8361 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8362 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8363 const int64_t BPOffset = 4 * PVT.getStoreSize();
8365 // Prepare IP either in reg.
8366 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
8367 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
8368 unsigned BufReg = MI->getOperand(1).getReg();
8370 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
8371 setUsesTOCBasePtr(*MBB->getParent());
8372 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
8376 MIB.setMemRefs(MMOBegin, MMOEnd);
8379 // Naked functions never have a base pointer, and so we use r1. For all
8380 // other functions, this decision must be delayed until during PEI.
8382 if (MF->getFunction()->hasFnAttribute(Attribute::Naked))
8383 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
8385 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
8387 MIB = BuildMI(*thisMBB, MI, DL,
8388 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
8392 MIB.setMemRefs(MMOBegin, MMOEnd);
8395 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
8396 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
8397 MIB.addRegMask(TRI->getNoPreservedMask());
8399 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
8401 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
8403 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
8405 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
8406 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
8411 BuildMI(mainMBB, DL,
8412 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
8415 if (Subtarget.isPPC64()) {
8416 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
8418 .addImm(LabelOffset)
8421 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
8423 .addImm(LabelOffset)
8427 MIB.setMemRefs(MMOBegin, MMOEnd);
8429 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
8430 mainMBB->addSuccessor(sinkMBB);
8433 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
8434 TII->get(PPC::PHI), DstReg)
8435 .addReg(mainDstReg).addMBB(mainMBB)
8436 .addReg(restoreDstReg).addMBB(thisMBB);
8438 MI->eraseFromParent();
8443 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
8444 MachineBasicBlock *MBB) const {
8445 DebugLoc DL = MI->getDebugLoc();
8446 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8448 MachineFunction *MF = MBB->getParent();
8449 MachineRegisterInfo &MRI = MF->getRegInfo();
8452 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8453 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8455 MVT PVT = getPointerTy(MF->getDataLayout());
8456 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8457 "Invalid Pointer Size!");
8459 const TargetRegisterClass *RC =
8460 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
8461 unsigned Tmp = MRI.createVirtualRegister(RC);
8462 // Since FP is only updated here but NOT referenced, it's treated as GPR.
8463 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
8464 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
8468 : (Subtarget.isSVR4ABI() &&
8469 MF->getTarget().getRelocationModel() == Reloc::PIC_
8473 MachineInstrBuilder MIB;
8475 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8476 const int64_t SPOffset = 2 * PVT.getStoreSize();
8477 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8478 const int64_t BPOffset = 4 * PVT.getStoreSize();
8480 unsigned BufReg = MI->getOperand(0).getReg();
8482 // Reload FP (the jumped-to function may not have had a
8483 // frame pointer, and if so, then its r31 will be restored
8485 if (PVT == MVT::i64) {
8486 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
8490 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
8494 MIB.setMemRefs(MMOBegin, MMOEnd);
8497 if (PVT == MVT::i64) {
8498 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
8499 .addImm(LabelOffset)
8502 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
8503 .addImm(LabelOffset)
8506 MIB.setMemRefs(MMOBegin, MMOEnd);
8509 if (PVT == MVT::i64) {
8510 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
8514 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
8518 MIB.setMemRefs(MMOBegin, MMOEnd);
8521 if (PVT == MVT::i64) {
8522 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
8526 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
8530 MIB.setMemRefs(MMOBegin, MMOEnd);
8533 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
8534 setUsesTOCBasePtr(*MBB->getParent());
8535 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
8539 MIB.setMemRefs(MMOBegin, MMOEnd);
8543 BuildMI(*MBB, MI, DL,
8544 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
8545 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
8547 MI->eraseFromParent();
8552 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8553 MachineBasicBlock *BB) const {
8554 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
8555 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8556 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
8557 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8558 // Call lowering should have added an r2 operand to indicate a dependence
8559 // on the TOC base pointer value. It can't however, because there is no
8560 // way to mark the dependence as implicit there, and so the stackmap code
8561 // will confuse it with a regular operand. Instead, add the dependence
8563 setUsesTOCBasePtr(*BB->getParent());
8564 MI->addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
8567 return emitPatchPoint(MI, BB);
8570 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
8571 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
8572 return emitEHSjLjSetJmp(MI, BB);
8573 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
8574 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
8575 return emitEHSjLjLongJmp(MI, BB);
8578 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8580 // To "insert" these instructions we actually have to insert their
8581 // control-flow patterns.
8582 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8583 MachineFunction::iterator It = BB;
8586 MachineFunction *F = BB->getParent();
8588 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8589 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8590 MI->getOpcode() == PPC::SELECT_I4 ||
8591 MI->getOpcode() == PPC::SELECT_I8)) {
8592 SmallVector<MachineOperand, 2> Cond;
8593 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8594 MI->getOpcode() == PPC::SELECT_CC_I8)
8595 Cond.push_back(MI->getOperand(4));
8597 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
8598 Cond.push_back(MI->getOperand(1));
8600 DebugLoc dl = MI->getDebugLoc();
8601 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
8602 Cond, MI->getOperand(2).getReg(),
8603 MI->getOperand(3).getReg());
8604 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8605 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8606 MI->getOpcode() == PPC::SELECT_CC_F4 ||
8607 MI->getOpcode() == PPC::SELECT_CC_F8 ||
8608 MI->getOpcode() == PPC::SELECT_CC_QFRC ||
8609 MI->getOpcode() == PPC::SELECT_CC_QSRC ||
8610 MI->getOpcode() == PPC::SELECT_CC_QBRC ||
8611 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
8612 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
8613 MI->getOpcode() == PPC::SELECT_CC_VSSRC ||
8614 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
8615 MI->getOpcode() == PPC::SELECT_I4 ||
8616 MI->getOpcode() == PPC::SELECT_I8 ||
8617 MI->getOpcode() == PPC::SELECT_F4 ||
8618 MI->getOpcode() == PPC::SELECT_F8 ||
8619 MI->getOpcode() == PPC::SELECT_QFRC ||
8620 MI->getOpcode() == PPC::SELECT_QSRC ||
8621 MI->getOpcode() == PPC::SELECT_QBRC ||
8622 MI->getOpcode() == PPC::SELECT_VRRC ||
8623 MI->getOpcode() == PPC::SELECT_VSFRC ||
8624 MI->getOpcode() == PPC::SELECT_VSSRC ||
8625 MI->getOpcode() == PPC::SELECT_VSRC) {
8626 // The incoming instruction knows the destination vreg to set, the
8627 // condition code register to branch on, the true/false values to
8628 // select between, and a branch opcode to use.
8633 // cmpTY ccX, r1, r2
8635 // fallthrough --> copy0MBB
8636 MachineBasicBlock *thisMBB = BB;
8637 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8638 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8639 DebugLoc dl = MI->getDebugLoc();
8640 F->insert(It, copy0MBB);
8641 F->insert(It, sinkMBB);
8643 // Transfer the remainder of BB and its successor edges to sinkMBB.
8644 sinkMBB->splice(sinkMBB->begin(), BB,
8645 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8646 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8648 // Next, add the true and fallthrough blocks as its successors.
8649 BB->addSuccessor(copy0MBB);
8650 BB->addSuccessor(sinkMBB);
8652 if (MI->getOpcode() == PPC::SELECT_I4 ||
8653 MI->getOpcode() == PPC::SELECT_I8 ||
8654 MI->getOpcode() == PPC::SELECT_F4 ||
8655 MI->getOpcode() == PPC::SELECT_F8 ||
8656 MI->getOpcode() == PPC::SELECT_QFRC ||
8657 MI->getOpcode() == PPC::SELECT_QSRC ||
8658 MI->getOpcode() == PPC::SELECT_QBRC ||
8659 MI->getOpcode() == PPC::SELECT_VRRC ||
8660 MI->getOpcode() == PPC::SELECT_VSFRC ||
8661 MI->getOpcode() == PPC::SELECT_VSSRC ||
8662 MI->getOpcode() == PPC::SELECT_VSRC) {
8663 BuildMI(BB, dl, TII->get(PPC::BC))
8664 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8666 unsigned SelectPred = MI->getOperand(4).getImm();
8667 BuildMI(BB, dl, TII->get(PPC::BCC))
8668 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8672 // %FalseValue = ...
8673 // # fallthrough to sinkMBB
8676 // Update machine-CFG edges
8677 BB->addSuccessor(sinkMBB);
8680 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8683 BuildMI(*BB, BB->begin(), dl,
8684 TII->get(PPC::PHI), MI->getOperand(0).getReg())
8685 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
8686 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8687 } else if (MI->getOpcode() == PPC::ReadTB) {
8688 // To read the 64-bit time-base register on a 32-bit target, we read the
8689 // two halves. Should the counter have wrapped while it was being read, we
8690 // need to try again.
8693 // mfspr Rx,TBU # load from TBU
8694 // mfspr Ry,TB # load from TB
8695 // mfspr Rz,TBU # load from TBU
8696 // cmpw crX,Rx,Rz # check if 'old'='new'
8697 // bne readLoop # branch if they're not equal
8700 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
8701 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8702 DebugLoc dl = MI->getDebugLoc();
8703 F->insert(It, readMBB);
8704 F->insert(It, sinkMBB);
8706 // Transfer the remainder of BB and its successor edges to sinkMBB.
8707 sinkMBB->splice(sinkMBB->begin(), BB,
8708 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8709 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8711 BB->addSuccessor(readMBB);
8714 MachineRegisterInfo &RegInfo = F->getRegInfo();
8715 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
8716 unsigned LoReg = MI->getOperand(0).getReg();
8717 unsigned HiReg = MI->getOperand(1).getReg();
8719 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
8720 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
8721 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
8723 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
8725 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
8726 .addReg(HiReg).addReg(ReadAgainReg);
8727 BuildMI(BB, dl, TII->get(PPC::BCC))
8728 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
8730 BB->addSuccessor(readMBB);
8731 BB->addSuccessor(sinkMBB);
8733 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
8734 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
8735 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
8736 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
8737 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
8738 BB = EmitAtomicBinary(MI, BB, 4, PPC::ADD4);
8739 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
8740 BB = EmitAtomicBinary(MI, BB, 8, PPC::ADD8);
8742 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
8743 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
8744 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
8745 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
8746 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
8747 BB = EmitAtomicBinary(MI, BB, 4, PPC::AND);
8748 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
8749 BB = EmitAtomicBinary(MI, BB, 8, PPC::AND8);
8751 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
8752 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
8753 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
8754 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
8755 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
8756 BB = EmitAtomicBinary(MI, BB, 4, PPC::OR);
8757 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
8758 BB = EmitAtomicBinary(MI, BB, 8, PPC::OR8);
8760 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
8761 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
8762 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
8763 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
8764 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
8765 BB = EmitAtomicBinary(MI, BB, 4, PPC::XOR);
8766 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
8767 BB = EmitAtomicBinary(MI, BB, 8, PPC::XOR8);
8769 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
8770 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
8771 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
8772 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
8773 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
8774 BB = EmitAtomicBinary(MI, BB, 4, PPC::NAND);
8775 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
8776 BB = EmitAtomicBinary(MI, BB, 8, PPC::NAND8);
8778 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
8779 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
8780 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
8781 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
8782 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
8783 BB = EmitAtomicBinary(MI, BB, 4, PPC::SUBF);
8784 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
8785 BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8);
8787 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
8788 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
8789 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
8790 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
8791 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
8792 BB = EmitAtomicBinary(MI, BB, 4, 0);
8793 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
8794 BB = EmitAtomicBinary(MI, BB, 8, 0);
8796 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
8797 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 ||
8798 (Subtarget.hasPartwordAtomics() &&
8799 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) ||
8800 (Subtarget.hasPartwordAtomics() &&
8801 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) {
8802 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
8804 auto LoadMnemonic = PPC::LDARX;
8805 auto StoreMnemonic = PPC::STDCX;
8806 switch(MI->getOpcode()) {
8808 llvm_unreachable("Compare and swap of unknown size");
8809 case PPC::ATOMIC_CMP_SWAP_I8:
8810 LoadMnemonic = PPC::LBARX;
8811 StoreMnemonic = PPC::STBCX;
8812 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8814 case PPC::ATOMIC_CMP_SWAP_I16:
8815 LoadMnemonic = PPC::LHARX;
8816 StoreMnemonic = PPC::STHCX;
8817 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8819 case PPC::ATOMIC_CMP_SWAP_I32:
8820 LoadMnemonic = PPC::LWARX;
8821 StoreMnemonic = PPC::STWCX;
8823 case PPC::ATOMIC_CMP_SWAP_I64:
8824 LoadMnemonic = PPC::LDARX;
8825 StoreMnemonic = PPC::STDCX;
8828 unsigned dest = MI->getOperand(0).getReg();
8829 unsigned ptrA = MI->getOperand(1).getReg();
8830 unsigned ptrB = MI->getOperand(2).getReg();
8831 unsigned oldval = MI->getOperand(3).getReg();
8832 unsigned newval = MI->getOperand(4).getReg();
8833 DebugLoc dl = MI->getDebugLoc();
8835 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8836 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8837 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8838 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8839 F->insert(It, loop1MBB);
8840 F->insert(It, loop2MBB);
8841 F->insert(It, midMBB);
8842 F->insert(It, exitMBB);
8843 exitMBB->splice(exitMBB->begin(), BB,
8844 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8845 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8849 // fallthrough --> loopMBB
8850 BB->addSuccessor(loop1MBB);
8853 // l[bhwd]arx dest, ptr
8854 // cmp[wd] dest, oldval
8857 // st[bhwd]cx. newval, ptr
8861 // st[bhwd]cx. dest, ptr
8864 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8865 .addReg(ptrA).addReg(ptrB);
8866 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
8867 .addReg(oldval).addReg(dest);
8868 BuildMI(BB, dl, TII->get(PPC::BCC))
8869 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
8870 BB->addSuccessor(loop2MBB);
8871 BB->addSuccessor(midMBB);
8874 BuildMI(BB, dl, TII->get(StoreMnemonic))
8875 .addReg(newval).addReg(ptrA).addReg(ptrB);
8876 BuildMI(BB, dl, TII->get(PPC::BCC))
8877 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
8878 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
8879 BB->addSuccessor(loop1MBB);
8880 BB->addSuccessor(exitMBB);
8883 BuildMI(BB, dl, TII->get(StoreMnemonic))
8884 .addReg(dest).addReg(ptrA).addReg(ptrB);
8885 BB->addSuccessor(exitMBB);
8890 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
8891 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
8892 // We must use 64-bit registers for addresses when targeting 64-bit,
8893 // since we're actually doing arithmetic on them. Other registers
8895 bool is64bit = Subtarget.isPPC64();
8896 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
8898 unsigned dest = MI->getOperand(0).getReg();
8899 unsigned ptrA = MI->getOperand(1).getReg();
8900 unsigned ptrB = MI->getOperand(2).getReg();
8901 unsigned oldval = MI->getOperand(3).getReg();
8902 unsigned newval = MI->getOperand(4).getReg();
8903 DebugLoc dl = MI->getDebugLoc();
8905 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8906 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8907 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8908 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8909 F->insert(It, loop1MBB);
8910 F->insert(It, loop2MBB);
8911 F->insert(It, midMBB);
8912 F->insert(It, exitMBB);
8913 exitMBB->splice(exitMBB->begin(), BB,
8914 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8915 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8917 MachineRegisterInfo &RegInfo = F->getRegInfo();
8918 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8919 : &PPC::GPRCRegClass;
8920 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8921 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8922 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8923 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
8924 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
8925 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
8926 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
8927 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8928 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8929 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8930 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8931 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8932 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8934 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
8935 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8938 // fallthrough --> loopMBB
8939 BB->addSuccessor(loop1MBB);
8941 // The 4-byte load must be aligned, while a char or short may be
8942 // anywhere in the word. Hence all this nasty bookkeeping code.
8943 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8944 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8945 // xori shift, shift1, 24 [16]
8946 // rlwinm ptr, ptr1, 0, 0, 29
8947 // slw newval2, newval, shift
8948 // slw oldval2, oldval,shift
8949 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8950 // slw mask, mask2, shift
8951 // and newval3, newval2, mask
8952 // and oldval3, oldval2, mask
8954 // lwarx tmpDest, ptr
8955 // and tmp, tmpDest, mask
8956 // cmpw tmp, oldval3
8959 // andc tmp2, tmpDest, mask
8960 // or tmp4, tmp2, newval3
8965 // stwcx. tmpDest, ptr
8967 // srw dest, tmpDest, shift
8968 if (ptrA != ZeroReg) {
8969 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8970 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8971 .addReg(ptrA).addReg(ptrB);
8975 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8976 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8977 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8978 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8980 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8981 .addReg(Ptr1Reg).addImm(0).addImm(61);
8983 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8984 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8985 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
8986 .addReg(newval).addReg(ShiftReg);
8987 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
8988 .addReg(oldval).addReg(ShiftReg);
8990 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
8992 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
8993 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
8994 .addReg(Mask3Reg).addImm(65535);
8996 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
8997 .addReg(Mask2Reg).addReg(ShiftReg);
8998 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
8999 .addReg(NewVal2Reg).addReg(MaskReg);
9000 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
9001 .addReg(OldVal2Reg).addReg(MaskReg);
9004 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
9005 .addReg(ZeroReg).addReg(PtrReg);
9006 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
9007 .addReg(TmpDestReg).addReg(MaskReg);
9008 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
9009 .addReg(TmpReg).addReg(OldVal3Reg);
9010 BuildMI(BB, dl, TII->get(PPC::BCC))
9011 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
9012 BB->addSuccessor(loop2MBB);
9013 BB->addSuccessor(midMBB);
9016 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
9017 .addReg(TmpDestReg).addReg(MaskReg);
9018 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
9019 .addReg(Tmp2Reg).addReg(NewVal3Reg);
9020 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
9021 .addReg(ZeroReg).addReg(PtrReg);
9022 BuildMI(BB, dl, TII->get(PPC::BCC))
9023 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
9024 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
9025 BB->addSuccessor(loop1MBB);
9026 BB->addSuccessor(exitMBB);
9029 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
9030 .addReg(ZeroReg).addReg(PtrReg);
9031 BB->addSuccessor(exitMBB);
9036 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
9038 } else if (MI->getOpcode() == PPC::FADDrtz) {
9039 // This pseudo performs an FADD with rounding mode temporarily forced
9040 // to round-to-zero. We emit this via custom inserter since the FPSCR
9041 // is not modeled at the SelectionDAG level.
9042 unsigned Dest = MI->getOperand(0).getReg();
9043 unsigned Src1 = MI->getOperand(1).getReg();
9044 unsigned Src2 = MI->getOperand(2).getReg();
9045 DebugLoc dl = MI->getDebugLoc();
9047 MachineRegisterInfo &RegInfo = F->getRegInfo();
9048 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
9050 // Save FPSCR value.
9051 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
9053 // Set rounding mode to round-to-zero.
9054 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
9055 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
9057 // Perform addition.
9058 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
9060 // Restore FPSCR value.
9061 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
9062 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9063 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
9064 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9065 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
9066 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9067 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
9068 PPC::ANDIo8 : PPC::ANDIo;
9069 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9070 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
9072 MachineRegisterInfo &RegInfo = F->getRegInfo();
9073 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
9074 &PPC::GPRCRegClass :
9075 &PPC::G8RCRegClass);
9077 DebugLoc dl = MI->getDebugLoc();
9078 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
9079 .addReg(MI->getOperand(1).getReg()).addImm(1);
9080 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
9081 MI->getOperand(0).getReg())
9082 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
9083 } else if (MI->getOpcode() == PPC::TCHECK_RET) {
9084 DebugLoc Dl = MI->getDebugLoc();
9085 MachineRegisterInfo &RegInfo = F->getRegInfo();
9086 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
9087 BuildMI(*BB, MI, Dl, TII->get(PPC::TCHECK), CRReg);
9090 llvm_unreachable("Unexpected instr type to insert");
9093 MI->eraseFromParent(); // The pseudo instruction is gone now.
9097 //===----------------------------------------------------------------------===//
9098 // Target Optimization Hooks
9099 //===----------------------------------------------------------------------===//
9101 static std::string getRecipOp(const char *Base, EVT VT) {
9102 std::string RecipOp(Base);
9103 if (VT.getScalarType() == MVT::f64)
9109 RecipOp = "vec-" + RecipOp;
9114 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
9115 DAGCombinerInfo &DCI,
9116 unsigned &RefinementSteps,
9117 bool &UseOneConstNR) const {
9118 EVT VT = Operand.getValueType();
9119 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
9120 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
9121 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9122 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9123 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9124 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9125 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
9126 std::string RecipOp = getRecipOp("sqrt", VT);
9127 if (!Recips.isEnabled(RecipOp))
9130 RefinementSteps = Recips.getRefinementSteps(RecipOp);
9131 UseOneConstNR = true;
9132 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
9137 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
9138 DAGCombinerInfo &DCI,
9139 unsigned &RefinementSteps) const {
9140 EVT VT = Operand.getValueType();
9141 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
9142 (VT == MVT::f64 && Subtarget.hasFRE()) ||
9143 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9144 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9145 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9146 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9147 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
9148 std::string RecipOp = getRecipOp("div", VT);
9149 if (!Recips.isEnabled(RecipOp))
9152 RefinementSteps = Recips.getRefinementSteps(RecipOp);
9153 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
9158 unsigned PPCTargetLowering::combineRepeatedFPDivisors() const {
9159 // Note: This functionality is used only when unsafe-fp-math is enabled, and
9160 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
9161 // enabled for division), this functionality is redundant with the default
9162 // combiner logic (once the division -> reciprocal/multiply transformation
9163 // has taken place). As a result, this matters more for older cores than for
9166 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9167 // reciprocal if there are two or more FDIVs (for embedded cores with only
9168 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
9169 switch (Subtarget.getDarwinDirective()) {
9174 case PPC::DIR_E500mc:
9175 case PPC::DIR_E5500:
9180 // isConsecutiveLSLoc needs to work even if all adds have not yet been
9181 // collapsed, and so we need to look through chains of them.
9182 static void getBaseWithConstantOffset(SDValue Loc, SDValue &Base,
9183 int64_t& Offset, SelectionDAG &DAG) {
9184 if (DAG.isBaseWithConstantOffset(Loc)) {
9185 Base = Loc.getOperand(0);
9186 Offset += cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue();
9188 // The base might itself be a base plus an offset, and if so, accumulate
9190 getBaseWithConstantOffset(Loc.getOperand(0), Base, Offset, DAG);
9194 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
9195 unsigned Bytes, int Dist,
9196 SelectionDAG &DAG) {
9197 if (VT.getSizeInBits() / 8 != Bytes)
9200 SDValue BaseLoc = Base->getBasePtr();
9201 if (Loc.getOpcode() == ISD::FrameIndex) {
9202 if (BaseLoc.getOpcode() != ISD::FrameIndex)
9204 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9205 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
9206 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
9207 int FS = MFI->getObjectSize(FI);
9208 int BFS = MFI->getObjectSize(BFI);
9209 if (FS != BFS || FS != (int)Bytes) return false;
9210 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
9213 SDValue Base1 = Loc, Base2 = BaseLoc;
9214 int64_t Offset1 = 0, Offset2 = 0;
9215 getBaseWithConstantOffset(Loc, Base1, Offset1, DAG);
9216 getBaseWithConstantOffset(BaseLoc, Base2, Offset2, DAG);
9217 if (Base1 == Base2 && Offset1 == (Offset2 + Dist * Bytes))
9220 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9221 const GlobalValue *GV1 = nullptr;
9222 const GlobalValue *GV2 = nullptr;
9225 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
9226 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
9227 if (isGA1 && isGA2 && GV1 == GV2)
9228 return Offset1 == (Offset2 + Dist*Bytes);
9232 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
9233 // not enforce equality of the chain operands.
9234 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
9235 unsigned Bytes, int Dist,
9236 SelectionDAG &DAG) {
9237 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
9238 EVT VT = LS->getMemoryVT();
9239 SDValue Loc = LS->getBasePtr();
9240 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
9243 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
9245 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9246 default: return false;
9247 case Intrinsic::ppc_qpx_qvlfd:
9248 case Intrinsic::ppc_qpx_qvlfda:
9251 case Intrinsic::ppc_qpx_qvlfs:
9252 case Intrinsic::ppc_qpx_qvlfsa:
9255 case Intrinsic::ppc_qpx_qvlfcd:
9256 case Intrinsic::ppc_qpx_qvlfcda:
9259 case Intrinsic::ppc_qpx_qvlfcs:
9260 case Intrinsic::ppc_qpx_qvlfcsa:
9263 case Intrinsic::ppc_qpx_qvlfiwa:
9264 case Intrinsic::ppc_qpx_qvlfiwz:
9265 case Intrinsic::ppc_altivec_lvx:
9266 case Intrinsic::ppc_altivec_lvxl:
9267 case Intrinsic::ppc_vsx_lxvw4x:
9270 case Intrinsic::ppc_vsx_lxvd2x:
9273 case Intrinsic::ppc_altivec_lvebx:
9276 case Intrinsic::ppc_altivec_lvehx:
9279 case Intrinsic::ppc_altivec_lvewx:
9284 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
9287 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
9289 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9290 default: return false;
9291 case Intrinsic::ppc_qpx_qvstfd:
9292 case Intrinsic::ppc_qpx_qvstfda:
9295 case Intrinsic::ppc_qpx_qvstfs:
9296 case Intrinsic::ppc_qpx_qvstfsa:
9299 case Intrinsic::ppc_qpx_qvstfcd:
9300 case Intrinsic::ppc_qpx_qvstfcda:
9303 case Intrinsic::ppc_qpx_qvstfcs:
9304 case Intrinsic::ppc_qpx_qvstfcsa:
9307 case Intrinsic::ppc_qpx_qvstfiw:
9308 case Intrinsic::ppc_qpx_qvstfiwa:
9309 case Intrinsic::ppc_altivec_stvx:
9310 case Intrinsic::ppc_altivec_stvxl:
9311 case Intrinsic::ppc_vsx_stxvw4x:
9314 case Intrinsic::ppc_vsx_stxvd2x:
9317 case Intrinsic::ppc_altivec_stvebx:
9320 case Intrinsic::ppc_altivec_stvehx:
9323 case Intrinsic::ppc_altivec_stvewx:
9328 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
9334 // Return true is there is a nearyby consecutive load to the one provided
9335 // (regardless of alignment). We search up and down the chain, looking though
9336 // token factors and other loads (but nothing else). As a result, a true result
9337 // indicates that it is safe to create a new consecutive load adjacent to the
9339 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
9340 SDValue Chain = LD->getChain();
9341 EVT VT = LD->getMemoryVT();
9343 SmallSet<SDNode *, 16> LoadRoots;
9344 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
9345 SmallSet<SDNode *, 16> Visited;
9347 // First, search up the chain, branching to follow all token-factor operands.
9348 // If we find a consecutive load, then we're done, otherwise, record all
9349 // nodes just above the top-level loads and token factors.
9350 while (!Queue.empty()) {
9351 SDNode *ChainNext = Queue.pop_back_val();
9352 if (!Visited.insert(ChainNext).second)
9355 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
9356 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9359 if (!Visited.count(ChainLD->getChain().getNode()))
9360 Queue.push_back(ChainLD->getChain().getNode());
9361 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
9362 for (const SDUse &O : ChainNext->ops())
9363 if (!Visited.count(O.getNode()))
9364 Queue.push_back(O.getNode());
9366 LoadRoots.insert(ChainNext);
9369 // Second, search down the chain, starting from the top-level nodes recorded
9370 // in the first phase. These top-level nodes are the nodes just above all
9371 // loads and token factors. Starting with their uses, recursively look though
9372 // all loads (just the chain uses) and token factors to find a consecutive
9377 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
9378 IE = LoadRoots.end(); I != IE; ++I) {
9379 Queue.push_back(*I);
9381 while (!Queue.empty()) {
9382 SDNode *LoadRoot = Queue.pop_back_val();
9383 if (!Visited.insert(LoadRoot).second)
9386 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
9387 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9390 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
9391 UE = LoadRoot->use_end(); UI != UE; ++UI)
9392 if (((isa<MemSDNode>(*UI) &&
9393 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
9394 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
9395 Queue.push_back(*UI);
9402 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
9403 DAGCombinerInfo &DCI) const {
9404 SelectionDAG &DAG = DCI.DAG;
9407 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits");
9408 // If we're tracking CR bits, we need to be careful that we don't have:
9409 // trunc(binary-ops(zext(x), zext(y)))
9411 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
9412 // such that we're unnecessarily moving things into GPRs when it would be
9413 // better to keep them in CR bits.
9415 // Note that trunc here can be an actual i1 trunc, or can be the effective
9416 // truncation that comes from a setcc or select_cc.
9417 if (N->getOpcode() == ISD::TRUNCATE &&
9418 N->getValueType(0) != MVT::i1)
9421 if (N->getOperand(0).getValueType() != MVT::i32 &&
9422 N->getOperand(0).getValueType() != MVT::i64)
9425 if (N->getOpcode() == ISD::SETCC ||
9426 N->getOpcode() == ISD::SELECT_CC) {
9427 // If we're looking at a comparison, then we need to make sure that the
9428 // high bits (all except for the first) don't matter the result.
9430 cast<CondCodeSDNode>(N->getOperand(
9431 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
9432 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
9434 if (ISD::isSignedIntSetCC(CC)) {
9435 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
9436 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
9438 } else if (ISD::isUnsignedIntSetCC(CC)) {
9439 if (!DAG.MaskedValueIsZero(N->getOperand(0),
9440 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
9441 !DAG.MaskedValueIsZero(N->getOperand(1),
9442 APInt::getHighBitsSet(OpBits, OpBits-1)))
9445 // This is neither a signed nor an unsigned comparison, just make sure
9446 // that the high bits are equal.
9447 APInt Op1Zero, Op1One;
9448 APInt Op2Zero, Op2One;
9449 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
9450 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
9452 // We don't really care about what is known about the first bit (if
9453 // anything), so clear it in all masks prior to comparing them.
9454 Op1Zero.clearBit(0); Op1One.clearBit(0);
9455 Op2Zero.clearBit(0); Op2One.clearBit(0);
9457 if (Op1Zero != Op2Zero || Op1One != Op2One)
9462 // We now know that the higher-order bits are irrelevant, we just need to
9463 // make sure that all of the intermediate operations are bit operations, and
9464 // all inputs are extensions.
9465 if (N->getOperand(0).getOpcode() != ISD::AND &&
9466 N->getOperand(0).getOpcode() != ISD::OR &&
9467 N->getOperand(0).getOpcode() != ISD::XOR &&
9468 N->getOperand(0).getOpcode() != ISD::SELECT &&
9469 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
9470 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
9471 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
9472 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
9473 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
9476 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
9477 N->getOperand(1).getOpcode() != ISD::AND &&
9478 N->getOperand(1).getOpcode() != ISD::OR &&
9479 N->getOperand(1).getOpcode() != ISD::XOR &&
9480 N->getOperand(1).getOpcode() != ISD::SELECT &&
9481 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
9482 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
9483 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
9484 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
9485 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
9488 SmallVector<SDValue, 4> Inputs;
9489 SmallVector<SDValue, 8> BinOps, PromOps;
9490 SmallPtrSet<SDNode *, 16> Visited;
9492 for (unsigned i = 0; i < 2; ++i) {
9493 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9494 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9495 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9496 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9497 isa<ConstantSDNode>(N->getOperand(i)))
9498 Inputs.push_back(N->getOperand(i));
9500 BinOps.push_back(N->getOperand(i));
9502 if (N->getOpcode() == ISD::TRUNCATE)
9506 // Visit all inputs, collect all binary operations (and, or, xor and
9507 // select) that are all fed by extensions.
9508 while (!BinOps.empty()) {
9509 SDValue BinOp = BinOps.back();
9512 if (!Visited.insert(BinOp.getNode()).second)
9515 PromOps.push_back(BinOp);
9517 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9518 // The condition of the select is not promoted.
9519 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9521 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9524 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9525 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9526 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9527 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9528 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9529 Inputs.push_back(BinOp.getOperand(i));
9530 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9531 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9532 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9533 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9534 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
9535 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9536 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9537 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9538 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
9539 BinOps.push_back(BinOp.getOperand(i));
9541 // We have an input that is not an extension or another binary
9542 // operation; we'll abort this transformation.
9548 // Make sure that this is a self-contained cluster of operations (which
9549 // is not quite the same thing as saying that everything has only one
9551 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9552 if (isa<ConstantSDNode>(Inputs[i]))
9555 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9556 UE = Inputs[i].getNode()->use_end();
9559 if (User != N && !Visited.count(User))
9562 // Make sure that we're not going to promote the non-output-value
9563 // operand(s) or SELECT or SELECT_CC.
9564 // FIXME: Although we could sometimes handle this, and it does occur in
9565 // practice that one of the condition inputs to the select is also one of
9566 // the outputs, we currently can't deal with this.
9567 if (User->getOpcode() == ISD::SELECT) {
9568 if (User->getOperand(0) == Inputs[i])
9570 } else if (User->getOpcode() == ISD::SELECT_CC) {
9571 if (User->getOperand(0) == Inputs[i] ||
9572 User->getOperand(1) == Inputs[i])
9578 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9579 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9580 UE = PromOps[i].getNode()->use_end();
9583 if (User != N && !Visited.count(User))
9586 // Make sure that we're not going to promote the non-output-value
9587 // operand(s) or SELECT or SELECT_CC.
9588 // FIXME: Although we could sometimes handle this, and it does occur in
9589 // practice that one of the condition inputs to the select is also one of
9590 // the outputs, we currently can't deal with this.
9591 if (User->getOpcode() == ISD::SELECT) {
9592 if (User->getOperand(0) == PromOps[i])
9594 } else if (User->getOpcode() == ISD::SELECT_CC) {
9595 if (User->getOperand(0) == PromOps[i] ||
9596 User->getOperand(1) == PromOps[i])
9602 // Replace all inputs with the extension operand.
9603 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9604 // Constants may have users outside the cluster of to-be-promoted nodes,
9605 // and so we need to replace those as we do the promotions.
9606 if (isa<ConstantSDNode>(Inputs[i]))
9609 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
9612 // Replace all operations (these are all the same, but have a different
9613 // (i1) return type). DAG.getNode will validate that the types of
9614 // a binary operator match, so go through the list in reverse so that
9615 // we've likely promoted both operands first. Any intermediate truncations or
9616 // extensions disappear.
9617 while (!PromOps.empty()) {
9618 SDValue PromOp = PromOps.back();
9621 if (PromOp.getOpcode() == ISD::TRUNCATE ||
9622 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
9623 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
9624 PromOp.getOpcode() == ISD::ANY_EXTEND) {
9625 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
9626 PromOp.getOperand(0).getValueType() != MVT::i1) {
9627 // The operand is not yet ready (see comment below).
9628 PromOps.insert(PromOps.begin(), PromOp);
9632 SDValue RepValue = PromOp.getOperand(0);
9633 if (isa<ConstantSDNode>(RepValue))
9634 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
9636 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
9641 switch (PromOp.getOpcode()) {
9642 default: C = 0; break;
9643 case ISD::SELECT: C = 1; break;
9644 case ISD::SELECT_CC: C = 2; break;
9647 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9648 PromOp.getOperand(C).getValueType() != MVT::i1) ||
9649 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9650 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
9651 // The to-be-promoted operands of this node have not yet been
9652 // promoted (this should be rare because we're going through the
9653 // list backward, but if one of the operands has several users in
9654 // this cluster of to-be-promoted nodes, it is possible).
9655 PromOps.insert(PromOps.begin(), PromOp);
9659 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9660 PromOp.getNode()->op_end());
9662 // If there are any constant inputs, make sure they're replaced now.
9663 for (unsigned i = 0; i < 2; ++i)
9664 if (isa<ConstantSDNode>(Ops[C+i]))
9665 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
9667 DAG.ReplaceAllUsesOfValueWith(PromOp,
9668 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
9671 // Now we're left with the initial truncation itself.
9672 if (N->getOpcode() == ISD::TRUNCATE)
9673 return N->getOperand(0);
9675 // Otherwise, this is a comparison. The operands to be compared have just
9676 // changed type (to i1), but everything else is the same.
9677 return SDValue(N, 0);
9680 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
9681 DAGCombinerInfo &DCI) const {
9682 SelectionDAG &DAG = DCI.DAG;
9685 // If we're tracking CR bits, we need to be careful that we don't have:
9686 // zext(binary-ops(trunc(x), trunc(y)))
9688 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
9689 // such that we're unnecessarily moving things into CR bits that can more
9690 // efficiently stay in GPRs. Note that if we're not certain that the high
9691 // bits are set as required by the final extension, we still may need to do
9692 // some masking to get the proper behavior.
9694 // This same functionality is important on PPC64 when dealing with
9695 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
9696 // the return values of functions. Because it is so similar, it is handled
9699 if (N->getValueType(0) != MVT::i32 &&
9700 N->getValueType(0) != MVT::i64)
9703 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
9704 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
9707 if (N->getOperand(0).getOpcode() != ISD::AND &&
9708 N->getOperand(0).getOpcode() != ISD::OR &&
9709 N->getOperand(0).getOpcode() != ISD::XOR &&
9710 N->getOperand(0).getOpcode() != ISD::SELECT &&
9711 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
9714 SmallVector<SDValue, 4> Inputs;
9715 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
9716 SmallPtrSet<SDNode *, 16> Visited;
9718 // Visit all inputs, collect all binary operations (and, or, xor and
9719 // select) that are all fed by truncations.
9720 while (!BinOps.empty()) {
9721 SDValue BinOp = BinOps.back();
9724 if (!Visited.insert(BinOp.getNode()).second)
9727 PromOps.push_back(BinOp);
9729 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9730 // The condition of the select is not promoted.
9731 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9733 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9736 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9737 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9738 Inputs.push_back(BinOp.getOperand(i));
9739 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9740 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9741 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9742 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9743 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
9744 BinOps.push_back(BinOp.getOperand(i));
9746 // We have an input that is not a truncation or another binary
9747 // operation; we'll abort this transformation.
9753 // The operands of a select that must be truncated when the select is
9754 // promoted because the operand is actually part of the to-be-promoted set.
9755 DenseMap<SDNode *, EVT> SelectTruncOp[2];
9757 // Make sure that this is a self-contained cluster of operations (which
9758 // is not quite the same thing as saying that everything has only one
9760 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9761 if (isa<ConstantSDNode>(Inputs[i]))
9764 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9765 UE = Inputs[i].getNode()->use_end();
9768 if (User != N && !Visited.count(User))
9771 // If we're going to promote the non-output-value operand(s) or SELECT or
9772 // SELECT_CC, record them for truncation.
9773 if (User->getOpcode() == ISD::SELECT) {
9774 if (User->getOperand(0) == Inputs[i])
9775 SelectTruncOp[0].insert(std::make_pair(User,
9776 User->getOperand(0).getValueType()));
9777 } else if (User->getOpcode() == ISD::SELECT_CC) {
9778 if (User->getOperand(0) == Inputs[i])
9779 SelectTruncOp[0].insert(std::make_pair(User,
9780 User->getOperand(0).getValueType()));
9781 if (User->getOperand(1) == Inputs[i])
9782 SelectTruncOp[1].insert(std::make_pair(User,
9783 User->getOperand(1).getValueType()));
9788 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9789 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9790 UE = PromOps[i].getNode()->use_end();
9793 if (User != N && !Visited.count(User))
9796 // If we're going to promote the non-output-value operand(s) or SELECT or
9797 // SELECT_CC, record them for truncation.
9798 if (User->getOpcode() == ISD::SELECT) {
9799 if (User->getOperand(0) == PromOps[i])
9800 SelectTruncOp[0].insert(std::make_pair(User,
9801 User->getOperand(0).getValueType()));
9802 } else if (User->getOpcode() == ISD::SELECT_CC) {
9803 if (User->getOperand(0) == PromOps[i])
9804 SelectTruncOp[0].insert(std::make_pair(User,
9805 User->getOperand(0).getValueType()));
9806 if (User->getOperand(1) == PromOps[i])
9807 SelectTruncOp[1].insert(std::make_pair(User,
9808 User->getOperand(1).getValueType()));
9813 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
9814 bool ReallyNeedsExt = false;
9815 if (N->getOpcode() != ISD::ANY_EXTEND) {
9816 // If all of the inputs are not already sign/zero extended, then
9817 // we'll still need to do that at the end.
9818 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9819 if (isa<ConstantSDNode>(Inputs[i]))
9823 Inputs[i].getOperand(0).getValueSizeInBits();
9824 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
9826 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
9827 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
9828 APInt::getHighBitsSet(OpBits,
9829 OpBits-PromBits))) ||
9830 (N->getOpcode() == ISD::SIGN_EXTEND &&
9831 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
9832 (OpBits-(PromBits-1)))) {
9833 ReallyNeedsExt = true;
9839 // Replace all inputs, either with the truncation operand, or a
9840 // truncation or extension to the final output type.
9841 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9842 // Constant inputs need to be replaced with the to-be-promoted nodes that
9843 // use them because they might have users outside of the cluster of
9845 if (isa<ConstantSDNode>(Inputs[i]))
9848 SDValue InSrc = Inputs[i].getOperand(0);
9849 if (Inputs[i].getValueType() == N->getValueType(0))
9850 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
9851 else if (N->getOpcode() == ISD::SIGN_EXTEND)
9852 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9853 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
9854 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9855 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9856 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
9858 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9859 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
9862 // Replace all operations (these are all the same, but have a different
9863 // (promoted) return type). DAG.getNode will validate that the types of
9864 // a binary operator match, so go through the list in reverse so that
9865 // we've likely promoted both operands first.
9866 while (!PromOps.empty()) {
9867 SDValue PromOp = PromOps.back();
9871 switch (PromOp.getOpcode()) {
9872 default: C = 0; break;
9873 case ISD::SELECT: C = 1; break;
9874 case ISD::SELECT_CC: C = 2; break;
9877 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9878 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
9879 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9880 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
9881 // The to-be-promoted operands of this node have not yet been
9882 // promoted (this should be rare because we're going through the
9883 // list backward, but if one of the operands has several users in
9884 // this cluster of to-be-promoted nodes, it is possible).
9885 PromOps.insert(PromOps.begin(), PromOp);
9889 // For SELECT and SELECT_CC nodes, we do a similar check for any
9890 // to-be-promoted comparison inputs.
9891 if (PromOp.getOpcode() == ISD::SELECT ||
9892 PromOp.getOpcode() == ISD::SELECT_CC) {
9893 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
9894 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
9895 (SelectTruncOp[1].count(PromOp.getNode()) &&
9896 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
9897 PromOps.insert(PromOps.begin(), PromOp);
9902 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9903 PromOp.getNode()->op_end());
9905 // If this node has constant inputs, then they'll need to be promoted here.
9906 for (unsigned i = 0; i < 2; ++i) {
9907 if (!isa<ConstantSDNode>(Ops[C+i]))
9909 if (Ops[C+i].getValueType() == N->getValueType(0))
9912 if (N->getOpcode() == ISD::SIGN_EXTEND)
9913 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9914 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9915 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9917 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9920 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
9921 // truncate them again to the original value type.
9922 if (PromOp.getOpcode() == ISD::SELECT ||
9923 PromOp.getOpcode() == ISD::SELECT_CC) {
9924 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
9925 if (SI0 != SelectTruncOp[0].end())
9926 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
9927 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
9928 if (SI1 != SelectTruncOp[1].end())
9929 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
9932 DAG.ReplaceAllUsesOfValueWith(PromOp,
9933 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
9936 // Now we're left with the initial extension itself.
9937 if (!ReallyNeedsExt)
9938 return N->getOperand(0);
9940 // To zero extend, just mask off everything except for the first bit (in the
9942 if (N->getOpcode() == ISD::ZERO_EXTEND)
9943 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
9944 DAG.getConstant(APInt::getLowBitsSet(
9945 N->getValueSizeInBits(0), PromBits),
9946 dl, N->getValueType(0)));
9948 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
9949 "Invalid extension type");
9950 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0), DAG.getDataLayout());
9952 DAG.getConstant(N->getValueSizeInBits(0) - PromBits, dl, ShiftAmountTy);
9954 ISD::SRA, dl, N->getValueType(0),
9955 DAG.getNode(ISD::SHL, dl, N->getValueType(0), N->getOperand(0), ShiftCst),
9959 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
9960 DAGCombinerInfo &DCI) const {
9961 assert((N->getOpcode() == ISD::SINT_TO_FP ||
9962 N->getOpcode() == ISD::UINT_TO_FP) &&
9963 "Need an int -> FP conversion node here");
9965 if (!Subtarget.has64BitSupport())
9968 SelectionDAG &DAG = DCI.DAG;
9972 // Don't handle ppc_fp128 here or i1 conversions.
9973 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
9975 if (Op.getOperand(0).getValueType() == MVT::i1)
9978 // For i32 intermediate values, unfortunately, the conversion functions
9979 // leave the upper 32 bits of the value are undefined. Within the set of
9980 // scalar instructions, we have no method for zero- or sign-extending the
9981 // value. Thus, we cannot handle i32 intermediate values here.
9982 if (Op.getOperand(0).getValueType() == MVT::i32)
9985 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
9986 "UINT_TO_FP is supported only with FPCVT");
9988 // If we have FCFIDS, then use it when converting to single-precision.
9989 // Otherwise, convert to double-precision and then round.
9990 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
9991 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
9993 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
9995 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
9999 // If we're converting from a float, to an int, and back to a float again,
10000 // then we don't need the store/load pair at all.
10001 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
10002 Subtarget.hasFPCVT()) ||
10003 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
10004 SDValue Src = Op.getOperand(0).getOperand(0);
10005 if (Src.getValueType() == MVT::f32) {
10006 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
10007 DCI.AddToWorklist(Src.getNode());
10008 } else if (Src.getValueType() != MVT::f64) {
10009 // Make sure that we don't pick up a ppc_fp128 source value.
10014 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
10017 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
10018 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
10020 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
10021 FP = DAG.getNode(ISD::FP_ROUND, dl,
10022 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
10023 DCI.AddToWorklist(FP.getNode());
10032 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
10033 // builtins) into loads with swaps.
10034 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
10035 DAGCombinerInfo &DCI) const {
10036 SelectionDAG &DAG = DCI.DAG;
10040 MachineMemOperand *MMO;
10042 switch (N->getOpcode()) {
10044 llvm_unreachable("Unexpected opcode for little endian VSX load");
10046 LoadSDNode *LD = cast<LoadSDNode>(N);
10047 Chain = LD->getChain();
10048 Base = LD->getBasePtr();
10049 MMO = LD->getMemOperand();
10050 // If the MMO suggests this isn't a load of a full vector, leave
10051 // things alone. For a built-in, we have to make the change for
10052 // correctness, so if there is a size problem that will be a bug.
10053 if (MMO->getSize() < 16)
10057 case ISD::INTRINSIC_W_CHAIN: {
10058 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
10059 Chain = Intrin->getChain();
10060 // Similarly to the store case below, Intrin->getBasePtr() doesn't get
10061 // us what we want. Get operand 2 instead.
10062 Base = Intrin->getOperand(2);
10063 MMO = Intrin->getMemOperand();
10068 MVT VecTy = N->getValueType(0).getSimpleVT();
10069 SDValue LoadOps[] = { Chain, Base };
10070 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
10071 DAG.getVTList(VecTy, MVT::Other),
10072 LoadOps, VecTy, MMO);
10073 DCI.AddToWorklist(Load.getNode());
10074 Chain = Load.getValue(1);
10075 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10076 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
10077 DCI.AddToWorklist(Swap.getNode());
10081 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
10082 // builtins) into stores with swaps.
10083 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
10084 DAGCombinerInfo &DCI) const {
10085 SelectionDAG &DAG = DCI.DAG;
10090 MachineMemOperand *MMO;
10092 switch (N->getOpcode()) {
10094 llvm_unreachable("Unexpected opcode for little endian VSX store");
10096 StoreSDNode *ST = cast<StoreSDNode>(N);
10097 Chain = ST->getChain();
10098 Base = ST->getBasePtr();
10099 MMO = ST->getMemOperand();
10101 // If the MMO suggests this isn't a store of a full vector, leave
10102 // things alone. For a built-in, we have to make the change for
10103 // correctness, so if there is a size problem that will be a bug.
10104 if (MMO->getSize() < 16)
10108 case ISD::INTRINSIC_VOID: {
10109 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
10110 Chain = Intrin->getChain();
10111 // Intrin->getBasePtr() oddly does not get what we want.
10112 Base = Intrin->getOperand(3);
10113 MMO = Intrin->getMemOperand();
10119 SDValue Src = N->getOperand(SrcOpnd);
10120 MVT VecTy = Src.getValueType().getSimpleVT();
10121 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10122 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
10123 DCI.AddToWorklist(Swap.getNode());
10124 Chain = Swap.getValue(1);
10125 SDValue StoreOps[] = { Chain, Swap, Base };
10126 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
10127 DAG.getVTList(MVT::Other),
10128 StoreOps, VecTy, MMO);
10129 DCI.AddToWorklist(Store.getNode());
10133 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
10134 DAGCombinerInfo &DCI) const {
10135 SelectionDAG &DAG = DCI.DAG;
10137 switch (N->getOpcode()) {
10140 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10141 if (C->isNullValue()) // 0 << V -> 0.
10142 return N->getOperand(0);
10146 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10147 if (C->isNullValue()) // 0 >>u V -> 0.
10148 return N->getOperand(0);
10152 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10153 if (C->isNullValue() || // 0 >>s V -> 0.
10154 C->isAllOnesValue()) // -1 >>s V -> -1.
10155 return N->getOperand(0);
10158 case ISD::SIGN_EXTEND:
10159 case ISD::ZERO_EXTEND:
10160 case ISD::ANY_EXTEND:
10161 return DAGCombineExtBoolTrunc(N, DCI);
10162 case ISD::TRUNCATE:
10164 case ISD::SELECT_CC:
10165 return DAGCombineTruncBoolExt(N, DCI);
10166 case ISD::SINT_TO_FP:
10167 case ISD::UINT_TO_FP:
10168 return combineFPToIntToFP(N, DCI);
10170 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
10171 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() &&
10172 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
10173 N->getOperand(1).getValueType() == MVT::i32 &&
10174 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
10175 SDValue Val = N->getOperand(1).getOperand(0);
10176 if (Val.getValueType() == MVT::f32) {
10177 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
10178 DCI.AddToWorklist(Val.getNode());
10180 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
10181 DCI.AddToWorklist(Val.getNode());
10184 N->getOperand(0), Val, N->getOperand(2),
10185 DAG.getValueType(N->getOperand(1).getValueType())
10188 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
10189 DAG.getVTList(MVT::Other), Ops,
10190 cast<StoreSDNode>(N)->getMemoryVT(),
10191 cast<StoreSDNode>(N)->getMemOperand());
10192 DCI.AddToWorklist(Val.getNode());
10196 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
10197 if (cast<StoreSDNode>(N)->isUnindexed() &&
10198 N->getOperand(1).getOpcode() == ISD::BSWAP &&
10199 N->getOperand(1).getNode()->hasOneUse() &&
10200 (N->getOperand(1).getValueType() == MVT::i32 ||
10201 N->getOperand(1).getValueType() == MVT::i16 ||
10202 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10203 N->getOperand(1).getValueType() == MVT::i64))) {
10204 SDValue BSwapOp = N->getOperand(1).getOperand(0);
10205 // Do an any-extend to 32-bits if this is a half-word input.
10206 if (BSwapOp.getValueType() == MVT::i16)
10207 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
10210 N->getOperand(0), BSwapOp, N->getOperand(2),
10211 DAG.getValueType(N->getOperand(1).getValueType())
10214 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
10215 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
10216 cast<StoreSDNode>(N)->getMemOperand());
10219 // For little endian, VSX stores require generating xxswapd/lxvd2x.
10220 EVT VT = N->getOperand(1).getValueType();
10221 if (VT.isSimple()) {
10222 MVT StoreVT = VT.getSimpleVT();
10223 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10224 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
10225 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
10226 return expandVSXStoreForLE(N, DCI);
10231 LoadSDNode *LD = cast<LoadSDNode>(N);
10232 EVT VT = LD->getValueType(0);
10234 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10235 if (VT.isSimple()) {
10236 MVT LoadVT = VT.getSimpleVT();
10237 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10238 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
10239 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
10240 return expandVSXLoadForLE(N, DCI);
10243 EVT MemVT = LD->getMemoryVT();
10244 Type *Ty = MemVT.getTypeForEVT(*DAG.getContext());
10245 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(Ty);
10246 Type *STy = MemVT.getScalarType().getTypeForEVT(*DAG.getContext());
10247 unsigned ScalarABIAlignment = DAG.getDataLayout().getABITypeAlignment(STy);
10248 if (LD->isUnindexed() && VT.isVector() &&
10249 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) &&
10250 // P8 and later hardware should just use LOAD.
10251 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 ||
10252 VT == MVT::v4i32 || VT == MVT::v4f32)) ||
10253 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) &&
10254 LD->getAlignment() >= ScalarABIAlignment)) &&
10255 LD->getAlignment() < ABIAlignment) {
10256 // This is a type-legal unaligned Altivec or QPX load.
10257 SDValue Chain = LD->getChain();
10258 SDValue Ptr = LD->getBasePtr();
10259 bool isLittleEndian = Subtarget.isLittleEndian();
10261 // This implements the loading of unaligned vectors as described in
10262 // the venerable Apple Velocity Engine overview. Specifically:
10263 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
10264 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
10266 // The general idea is to expand a sequence of one or more unaligned
10267 // loads into an alignment-based permutation-control instruction (lvsl
10268 // or lvsr), a series of regular vector loads (which always truncate
10269 // their input address to an aligned address), and a series of
10270 // permutations. The results of these permutations are the requested
10271 // loaded values. The trick is that the last "extra" load is not taken
10272 // from the address you might suspect (sizeof(vector) bytes after the
10273 // last requested load), but rather sizeof(vector) - 1 bytes after the
10274 // last requested vector. The point of this is to avoid a page fault if
10275 // the base address happened to be aligned. This works because if the
10276 // base address is aligned, then adding less than a full vector length
10277 // will cause the last vector in the sequence to be (re)loaded.
10278 // Otherwise, the next vector will be fetched as you might suspect was
10281 // We might be able to reuse the permutation generation from
10282 // a different base address offset from this one by an aligned amount.
10283 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
10284 // optimization later.
10285 Intrinsic::ID Intr, IntrLD, IntrPerm;
10286 MVT PermCntlTy, PermTy, LDTy;
10287 if (Subtarget.hasAltivec()) {
10288 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr :
10289 Intrinsic::ppc_altivec_lvsl;
10290 IntrLD = Intrinsic::ppc_altivec_lvx;
10291 IntrPerm = Intrinsic::ppc_altivec_vperm;
10292 PermCntlTy = MVT::v16i8;
10293 PermTy = MVT::v4i32;
10296 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld :
10297 Intrinsic::ppc_qpx_qvlpcls;
10298 IntrLD = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlfd :
10299 Intrinsic::ppc_qpx_qvlfs;
10300 IntrPerm = Intrinsic::ppc_qpx_qvfperm;
10301 PermCntlTy = MVT::v4f64;
10302 PermTy = MVT::v4f64;
10303 LDTy = MemVT.getSimpleVT();
10306 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, PermCntlTy);
10308 // Create the new MMO for the new base load. It is like the original MMO,
10309 // but represents an area in memory almost twice the vector size centered
10310 // on the original address. If the address is unaligned, we might start
10311 // reading up to (sizeof(vector)-1) bytes below the address of the
10312 // original unaligned load.
10313 MachineFunction &MF = DAG.getMachineFunction();
10314 MachineMemOperand *BaseMMO =
10315 MF.getMachineMemOperand(LD->getMemOperand(),
10316 -(long)MemVT.getStoreSize()+1,
10317 2*MemVT.getStoreSize()-1);
10319 // Create the new base load.
10321 DAG.getTargetConstant(IntrLD, dl, getPointerTy(MF.getDataLayout()));
10322 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
10324 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10325 DAG.getVTList(PermTy, MVT::Other),
10326 BaseLoadOps, LDTy, BaseMMO);
10328 // Note that the value of IncOffset (which is provided to the next
10329 // load's pointer info offset value, and thus used to calculate the
10330 // alignment), and the value of IncValue (which is actually used to
10331 // increment the pointer value) are different! This is because we
10332 // require the next load to appear to be aligned, even though it
10333 // is actually offset from the base pointer by a lesser amount.
10334 int IncOffset = VT.getSizeInBits() / 8;
10335 int IncValue = IncOffset;
10337 // Walk (both up and down) the chain looking for another load at the real
10338 // (aligned) offset (the alignment of the other load does not matter in
10339 // this case). If found, then do not use the offset reduction trick, as
10340 // that will prevent the loads from being later combined (as they would
10341 // otherwise be duplicates).
10342 if (!findConsecutiveLoad(LD, DAG))
10345 SDValue Increment =
10346 DAG.getConstant(IncValue, dl, getPointerTy(MF.getDataLayout()));
10347 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
10349 MachineMemOperand *ExtraMMO =
10350 MF.getMachineMemOperand(LD->getMemOperand(),
10351 1, 2*MemVT.getStoreSize()-1);
10352 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
10353 SDValue ExtraLoad =
10354 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10355 DAG.getVTList(PermTy, MVT::Other),
10356 ExtraLoadOps, LDTy, ExtraMMO);
10358 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
10359 BaseLoad.getValue(1), ExtraLoad.getValue(1));
10361 // Because vperm has a big-endian bias, we must reverse the order
10362 // of the input vectors and complement the permute control vector
10363 // when generating little endian code. We have already handled the
10364 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
10365 // and ExtraLoad here.
10367 if (isLittleEndian)
10368 Perm = BuildIntrinsicOp(IntrPerm,
10369 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
10371 Perm = BuildIntrinsicOp(IntrPerm,
10372 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
10375 Perm = Subtarget.hasAltivec() ?
10376 DAG.getNode(ISD::BITCAST, dl, VT, Perm) :
10377 DAG.getNode(ISD::FP_ROUND, dl, VT, Perm, // QPX
10378 DAG.getTargetConstant(1, dl, MVT::i64));
10379 // second argument is 1 because this rounding
10380 // is always exact.
10382 // The output of the permutation is our loaded result, the TokenFactor is
10384 DCI.CombineTo(N, Perm, TF);
10385 return SDValue(N, 0);
10389 case ISD::INTRINSIC_WO_CHAIN: {
10390 bool isLittleEndian = Subtarget.isLittleEndian();
10391 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
10392 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
10393 : Intrinsic::ppc_altivec_lvsl);
10394 if ((IID == Intr ||
10395 IID == Intrinsic::ppc_qpx_qvlpcld ||
10396 IID == Intrinsic::ppc_qpx_qvlpcls) &&
10397 N->getOperand(1)->getOpcode() == ISD::ADD) {
10398 SDValue Add = N->getOperand(1);
10400 int Bits = IID == Intrinsic::ppc_qpx_qvlpcld ?
10401 5 /* 32 byte alignment */ : 4 /* 16 byte alignment */;
10403 if (DAG.MaskedValueIsZero(
10404 Add->getOperand(1),
10405 APInt::getAllOnesValue(Bits /* alignment */)
10407 Add.getValueType().getScalarType().getSizeInBits()))) {
10408 SDNode *BasePtr = Add->getOperand(0).getNode();
10409 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10410 UE = BasePtr->use_end();
10412 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10413 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() == IID) {
10414 // We've found another LVSL/LVSR, and this address is an aligned
10415 // multiple of that one. The results will be the same, so use the
10416 // one we've just found instead.
10418 return SDValue(*UI, 0);
10423 if (isa<ConstantSDNode>(Add->getOperand(1))) {
10424 SDNode *BasePtr = Add->getOperand(0).getNode();
10425 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10426 UE = BasePtr->use_end(); UI != UE; ++UI) {
10427 if (UI->getOpcode() == ISD::ADD &&
10428 isa<ConstantSDNode>(UI->getOperand(1)) &&
10429 (cast<ConstantSDNode>(Add->getOperand(1))->getZExtValue() -
10430 cast<ConstantSDNode>(UI->getOperand(1))->getZExtValue()) %
10431 (1ULL << Bits) == 0) {
10432 SDNode *OtherAdd = *UI;
10433 for (SDNode::use_iterator VI = OtherAdd->use_begin(),
10434 VE = OtherAdd->use_end(); VI != VE; ++VI) {
10435 if (VI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10436 cast<ConstantSDNode>(VI->getOperand(0))->getZExtValue() == IID) {
10437 return SDValue(*VI, 0);
10447 case ISD::INTRINSIC_W_CHAIN: {
10448 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10449 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10450 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10453 case Intrinsic::ppc_vsx_lxvw4x:
10454 case Intrinsic::ppc_vsx_lxvd2x:
10455 return expandVSXLoadForLE(N, DCI);
10460 case ISD::INTRINSIC_VOID: {
10461 // For little endian, VSX stores require generating xxswapd/stxvd2x.
10462 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10463 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10466 case Intrinsic::ppc_vsx_stxvw4x:
10467 case Intrinsic::ppc_vsx_stxvd2x:
10468 return expandVSXStoreForLE(N, DCI);
10474 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
10475 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
10476 N->getOperand(0).hasOneUse() &&
10477 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
10478 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10479 N->getValueType(0) == MVT::i64))) {
10480 SDValue Load = N->getOperand(0);
10481 LoadSDNode *LD = cast<LoadSDNode>(Load);
10482 // Create the byte-swapping load.
10484 LD->getChain(), // Chain
10485 LD->getBasePtr(), // Ptr
10486 DAG.getValueType(N->getValueType(0)) // VT
10489 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
10490 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
10491 MVT::i64 : MVT::i32, MVT::Other),
10492 Ops, LD->getMemoryVT(), LD->getMemOperand());
10494 // If this is an i16 load, insert the truncate.
10495 SDValue ResVal = BSLoad;
10496 if (N->getValueType(0) == MVT::i16)
10497 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
10499 // First, combine the bswap away. This makes the value produced by the
10501 DCI.CombineTo(N, ResVal);
10503 // Next, combine the load away, we give it a bogus result value but a real
10504 // chain result. The result value is dead because the bswap is dead.
10505 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
10507 // Return N so it doesn't get rechecked!
10508 return SDValue(N, 0);
10512 case PPCISD::VCMP: {
10513 // If a VCMPo node already exists with exactly the same operands as this
10514 // node, use its result instead of this node (VCMPo computes both a CR6 and
10515 // a normal output).
10517 if (!N->getOperand(0).hasOneUse() &&
10518 !N->getOperand(1).hasOneUse() &&
10519 !N->getOperand(2).hasOneUse()) {
10521 // Scan all of the users of the LHS, looking for VCMPo's that match.
10522 SDNode *VCMPoNode = nullptr;
10524 SDNode *LHSN = N->getOperand(0).getNode();
10525 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
10527 if (UI->getOpcode() == PPCISD::VCMPo &&
10528 UI->getOperand(1) == N->getOperand(1) &&
10529 UI->getOperand(2) == N->getOperand(2) &&
10530 UI->getOperand(0) == N->getOperand(0)) {
10535 // If there is no VCMPo node, or if the flag value has a single use, don't
10537 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
10540 // Look at the (necessarily single) use of the flag value. If it has a
10541 // chain, this transformation is more complex. Note that multiple things
10542 // could use the value result, which we should ignore.
10543 SDNode *FlagUser = nullptr;
10544 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
10545 FlagUser == nullptr; ++UI) {
10546 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
10547 SDNode *User = *UI;
10548 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
10549 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
10556 // If the user is a MFOCRF instruction, we know this is safe.
10557 // Otherwise we give up for right now.
10558 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
10559 return SDValue(VCMPoNode, 0);
10563 case ISD::BRCOND: {
10564 SDValue Cond = N->getOperand(1);
10565 SDValue Target = N->getOperand(2);
10567 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10568 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
10569 Intrinsic::ppc_is_decremented_ctr_nonzero) {
10571 // We now need to make the intrinsic dead (it cannot be instruction
10573 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
10574 assert(Cond.getNode()->hasOneUse() &&
10575 "Counter decrement has more than one use");
10577 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
10578 N->getOperand(0), Target);
10583 // If this is a branch on an altivec predicate comparison, lower this so
10584 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
10585 // lowering is done pre-legalize, because the legalizer lowers the predicate
10586 // compare down to code that is difficult to reassemble.
10587 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
10588 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
10590 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
10591 // value. If so, pass-through the AND to get to the intrinsic.
10592 if (LHS.getOpcode() == ISD::AND &&
10593 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10594 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
10595 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10596 isa<ConstantSDNode>(LHS.getOperand(1)) &&
10597 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
10599 LHS = LHS.getOperand(0);
10601 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10602 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
10603 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10604 isa<ConstantSDNode>(RHS)) {
10605 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
10606 "Counter decrement comparison is not EQ or NE");
10608 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10609 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
10610 (CC == ISD::SETNE && !Val);
10612 // We now need to make the intrinsic dead (it cannot be instruction
10614 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
10615 assert(LHS.getNode()->hasOneUse() &&
10616 "Counter decrement has more than one use");
10618 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
10619 N->getOperand(0), N->getOperand(4));
10625 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10626 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
10627 getAltivecCompareInfo(LHS, CompareOpc, isDot, Subtarget)) {
10628 assert(isDot && "Can't compare against a vector result!");
10630 // If this is a comparison against something other than 0/1, then we know
10631 // that the condition is never/always true.
10632 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10633 if (Val != 0 && Val != 1) {
10634 if (CC == ISD::SETEQ) // Cond never true, remove branch.
10635 return N->getOperand(0);
10636 // Always !=, turn it into an unconditional branch.
10637 return DAG.getNode(ISD::BR, dl, MVT::Other,
10638 N->getOperand(0), N->getOperand(4));
10641 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
10643 // Create the PPCISD altivec 'dot' comparison node.
10645 LHS.getOperand(2), // LHS of compare
10646 LHS.getOperand(3), // RHS of compare
10647 DAG.getConstant(CompareOpc, dl, MVT::i32)
10649 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
10650 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
10652 // Unpack the result based on how the target uses it.
10653 PPC::Predicate CompOpc;
10654 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
10655 default: // Can't happen, don't crash on invalid number though.
10656 case 0: // Branch on the value of the EQ bit of CR6.
10657 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
10659 case 1: // Branch on the inverted value of the EQ bit of CR6.
10660 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
10662 case 2: // Branch on the value of the LT bit of CR6.
10663 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
10665 case 3: // Branch on the inverted value of the LT bit of CR6.
10666 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
10670 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
10671 DAG.getConstant(CompOpc, dl, MVT::i32),
10672 DAG.getRegister(PPC::CR6, MVT::i32),
10673 N->getOperand(4), CompNode.getValue(1));
10683 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
10685 std::vector<SDNode *> *Created) const {
10686 // fold (sdiv X, pow2)
10687 EVT VT = N->getValueType(0);
10688 if (VT == MVT::i64 && !Subtarget.isPPC64())
10690 if ((VT != MVT::i32 && VT != MVT::i64) ||
10691 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
10695 SDValue N0 = N->getOperand(0);
10697 bool IsNegPow2 = (-Divisor).isPowerOf2();
10698 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
10699 SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT);
10701 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
10703 Created->push_back(Op.getNode());
10706 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Op);
10708 Created->push_back(Op.getNode());
10714 //===----------------------------------------------------------------------===//
10715 // Inline Assembly Support
10716 //===----------------------------------------------------------------------===//
10718 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10721 const SelectionDAG &DAG,
10722 unsigned Depth) const {
10723 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
10724 switch (Op.getOpcode()) {
10726 case PPCISD::LBRX: {
10727 // lhbrx is known to have the top bits cleared out.
10728 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
10729 KnownZero = 0xFFFF0000;
10732 case ISD::INTRINSIC_WO_CHAIN: {
10733 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
10735 case Intrinsic::ppc_altivec_vcmpbfp_p:
10736 case Intrinsic::ppc_altivec_vcmpeqfp_p:
10737 case Intrinsic::ppc_altivec_vcmpequb_p:
10738 case Intrinsic::ppc_altivec_vcmpequh_p:
10739 case Intrinsic::ppc_altivec_vcmpequw_p:
10740 case Intrinsic::ppc_altivec_vcmpequd_p:
10741 case Intrinsic::ppc_altivec_vcmpgefp_p:
10742 case Intrinsic::ppc_altivec_vcmpgtfp_p:
10743 case Intrinsic::ppc_altivec_vcmpgtsb_p:
10744 case Intrinsic::ppc_altivec_vcmpgtsh_p:
10745 case Intrinsic::ppc_altivec_vcmpgtsw_p:
10746 case Intrinsic::ppc_altivec_vcmpgtsd_p:
10747 case Intrinsic::ppc_altivec_vcmpgtub_p:
10748 case Intrinsic::ppc_altivec_vcmpgtuh_p:
10749 case Intrinsic::ppc_altivec_vcmpgtuw_p:
10750 case Intrinsic::ppc_altivec_vcmpgtud_p:
10751 KnownZero = ~1U; // All bits but the low one are known to be zero.
10758 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
10759 switch (Subtarget.getDarwinDirective()) {
10762 case PPC::DIR_PWR4:
10763 case PPC::DIR_PWR5:
10764 case PPC::DIR_PWR5X:
10765 case PPC::DIR_PWR6:
10766 case PPC::DIR_PWR6X:
10767 case PPC::DIR_PWR7:
10768 case PPC::DIR_PWR8: {
10772 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
10774 // For small loops (between 5 and 8 instructions), align to a 32-byte
10775 // boundary so that the entire loop fits in one instruction-cache line.
10776 uint64_t LoopSize = 0;
10777 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
10778 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
10779 LoopSize += TII->GetInstSizeInBytes(J);
10781 if (LoopSize > 16 && LoopSize <= 32)
10788 return TargetLowering::getPrefLoopAlignment(ML);
10791 /// getConstraintType - Given a constraint, return the type of
10792 /// constraint it is for this target.
10793 PPCTargetLowering::ConstraintType
10794 PPCTargetLowering::getConstraintType(StringRef Constraint) const {
10795 if (Constraint.size() == 1) {
10796 switch (Constraint[0]) {
10803 return C_RegisterClass;
10805 // FIXME: While Z does indicate a memory constraint, it specifically
10806 // indicates an r+r address (used in conjunction with the 'y' modifier
10807 // in the replacement string). Currently, we're forcing the base
10808 // register to be r0 in the asm printer (which is interpreted as zero)
10809 // and forming the complete address in the second register. This is
10813 } else if (Constraint == "wc") { // individual CR bits.
10814 return C_RegisterClass;
10815 } else if (Constraint == "wa" || Constraint == "wd" ||
10816 Constraint == "wf" || Constraint == "ws") {
10817 return C_RegisterClass; // VSX registers.
10819 return TargetLowering::getConstraintType(Constraint);
10822 /// Examine constraint type and operand type and determine a weight value.
10823 /// This object must already have been set up with the operand type
10824 /// and the current alternative constraint selected.
10825 TargetLowering::ConstraintWeight
10826 PPCTargetLowering::getSingleConstraintMatchWeight(
10827 AsmOperandInfo &info, const char *constraint) const {
10828 ConstraintWeight weight = CW_Invalid;
10829 Value *CallOperandVal = info.CallOperandVal;
10830 // If we don't have a value, we can't do a match,
10831 // but allow it at the lowest weight.
10832 if (!CallOperandVal)
10834 Type *type = CallOperandVal->getType();
10836 // Look at the constraint type.
10837 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
10838 return CW_Register; // an individual CR bit.
10839 else if ((StringRef(constraint) == "wa" ||
10840 StringRef(constraint) == "wd" ||
10841 StringRef(constraint) == "wf") &&
10842 type->isVectorTy())
10843 return CW_Register;
10844 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
10845 return CW_Register;
10847 switch (*constraint) {
10849 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10852 if (type->isIntegerTy())
10853 weight = CW_Register;
10856 if (type->isFloatTy())
10857 weight = CW_Register;
10860 if (type->isDoubleTy())
10861 weight = CW_Register;
10864 if (type->isVectorTy())
10865 weight = CW_Register;
10868 weight = CW_Register;
10871 weight = CW_Memory;
10877 std::pair<unsigned, const TargetRegisterClass *>
10878 PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
10879 StringRef Constraint,
10881 if (Constraint.size() == 1) {
10882 // GCC RS6000 Constraint Letters
10883 switch (Constraint[0]) {
10884 case 'b': // R1-R31
10885 if (VT == MVT::i64 && Subtarget.isPPC64())
10886 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
10887 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
10888 case 'r': // R0-R31
10889 if (VT == MVT::i64 && Subtarget.isPPC64())
10890 return std::make_pair(0U, &PPC::G8RCRegClass);
10891 return std::make_pair(0U, &PPC::GPRCRegClass);
10893 if (VT == MVT::f32 || VT == MVT::i32)
10894 return std::make_pair(0U, &PPC::F4RCRegClass);
10895 if (VT == MVT::f64 || VT == MVT::i64)
10896 return std::make_pair(0U, &PPC::F8RCRegClass);
10897 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10898 return std::make_pair(0U, &PPC::QFRCRegClass);
10899 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10900 return std::make_pair(0U, &PPC::QSRCRegClass);
10903 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10904 return std::make_pair(0U, &PPC::QFRCRegClass);
10905 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10906 return std::make_pair(0U, &PPC::QSRCRegClass);
10907 return std::make_pair(0U, &PPC::VRRCRegClass);
10909 return std::make_pair(0U, &PPC::CRRCRegClass);
10911 } else if (Constraint == "wc") { // an individual CR bit.
10912 return std::make_pair(0U, &PPC::CRBITRCRegClass);
10913 } else if (Constraint == "wa" || Constraint == "wd" ||
10914 Constraint == "wf") {
10915 return std::make_pair(0U, &PPC::VSRCRegClass);
10916 } else if (Constraint == "ws") {
10917 if (VT == MVT::f32)
10918 return std::make_pair(0U, &PPC::VSSRCRegClass);
10920 return std::make_pair(0U, &PPC::VSFRCRegClass);
10923 std::pair<unsigned, const TargetRegisterClass *> R =
10924 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
10926 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
10927 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
10928 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
10930 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
10931 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
10932 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
10933 PPC::GPRCRegClass.contains(R.first))
10934 return std::make_pair(TRI->getMatchingSuperReg(R.first,
10935 PPC::sub_32, &PPC::G8RCRegClass),
10936 &PPC::G8RCRegClass);
10938 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
10939 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
10940 R.first = PPC::CR0;
10941 R.second = &PPC::CRRCRegClass;
10948 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10949 /// vector. If it is invalid, don't add anything to Ops.
10950 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10951 std::string &Constraint,
10952 std::vector<SDValue>&Ops,
10953 SelectionDAG &DAG) const {
10956 // Only support length 1 constraints.
10957 if (Constraint.length() > 1) return;
10959 char Letter = Constraint[0];
10970 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
10971 if (!CST) return; // Must be an immediate to match.
10973 int64_t Value = CST->getSExtValue();
10974 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
10975 // numbers are printed as such.
10977 default: llvm_unreachable("Unknown constraint letter!");
10978 case 'I': // "I" is a signed 16-bit constant.
10979 if (isInt<16>(Value))
10980 Result = DAG.getTargetConstant(Value, dl, TCVT);
10982 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
10983 if (isShiftedUInt<16, 16>(Value))
10984 Result = DAG.getTargetConstant(Value, dl, TCVT);
10986 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
10987 if (isShiftedInt<16, 16>(Value))
10988 Result = DAG.getTargetConstant(Value, dl, TCVT);
10990 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
10991 if (isUInt<16>(Value))
10992 Result = DAG.getTargetConstant(Value, dl, TCVT);
10994 case 'M': // "M" is a constant that is greater than 31.
10996 Result = DAG.getTargetConstant(Value, dl, TCVT);
10998 case 'N': // "N" is a positive constant that is an exact power of two.
10999 if (Value > 0 && isPowerOf2_64(Value))
11000 Result = DAG.getTargetConstant(Value, dl, TCVT);
11002 case 'O': // "O" is the constant zero.
11004 Result = DAG.getTargetConstant(Value, dl, TCVT);
11006 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
11007 if (isInt<16>(-Value))
11008 Result = DAG.getTargetConstant(Value, dl, TCVT);
11015 if (Result.getNode()) {
11016 Ops.push_back(Result);
11020 // Handle standard constraint letters.
11021 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
11024 // isLegalAddressingMode - Return true if the addressing mode represented
11025 // by AM is legal for this target, for a load/store of the specified type.
11026 bool PPCTargetLowering::isLegalAddressingMode(const DataLayout &DL,
11027 const AddrMode &AM, Type *Ty,
11028 unsigned AS) const {
11029 // PPC does not allow r+i addressing modes for vectors!
11030 if (Ty->isVectorTy() && AM.BaseOffs != 0)
11033 // PPC allows a sign-extended 16-bit immediate field.
11034 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
11037 // No global is ever allowed as a base.
11041 // PPC only support r+r,
11042 switch (AM.Scale) {
11043 case 0: // "r+i" or just "i", depending on HasBaseReg.
11046 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
11048 // Otherwise we have r+r or r+i.
11051 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
11053 // Allow 2*r as r+r.
11056 // No other scales are supported.
11063 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
11064 SelectionDAG &DAG) const {
11065 MachineFunction &MF = DAG.getMachineFunction();
11066 MachineFrameInfo *MFI = MF.getFrameInfo();
11067 MFI->setReturnAddressIsTaken(true);
11069 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
11073 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11075 // Make sure the function does not optimize away the store of the RA to
11077 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
11078 FuncInfo->setLRStoreRequired();
11079 bool isPPC64 = Subtarget.isPPC64();
11080 auto PtrVT = getPointerTy(MF.getDataLayout());
11083 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11085 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl,
11086 isPPC64 ? MVT::i64 : MVT::i32);
11087 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11088 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
11089 MachinePointerInfo(), false, false, false, 0);
11092 // Just load the return address off the stack.
11093 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
11094 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
11095 MachinePointerInfo(), false, false, false, 0);
11098 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
11099 SelectionDAG &DAG) const {
11101 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11103 MachineFunction &MF = DAG.getMachineFunction();
11104 MachineFrameInfo *MFI = MF.getFrameInfo();
11105 MFI->setFrameAddressIsTaken(true);
11107 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
11108 bool isPPC64 = PtrVT == MVT::i64;
11110 // Naked functions never have a frame pointer, and so we use r1. For all
11111 // other functions, this decision must be delayed until during PEI.
11113 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
11114 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
11116 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
11118 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
11121 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
11122 FrameAddr, MachinePointerInfo(), false, false,
11127 // FIXME? Maybe this could be a TableGen attribute on some registers and
11128 // this table could be generated automatically from RegInfo.
11129 unsigned PPCTargetLowering::getRegisterByName(const char* RegName, EVT VT,
11130 SelectionDAG &DAG) const {
11131 bool isPPC64 = Subtarget.isPPC64();
11132 bool isDarwinABI = Subtarget.isDarwinABI();
11134 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
11135 (!isPPC64 && VT != MVT::i32))
11136 report_fatal_error("Invalid register global variable type");
11138 bool is64Bit = isPPC64 && VT == MVT::i64;
11139 unsigned Reg = StringSwitch<unsigned>(RegName)
11140 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
11141 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2)
11142 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
11143 (is64Bit ? PPC::X13 : PPC::R13))
11148 report_fatal_error("Invalid register name global variable");
11152 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
11153 // The PowerPC target isn't yet aware of offsets.
11157 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
11159 unsigned Intrinsic) const {
11161 switch (Intrinsic) {
11162 case Intrinsic::ppc_qpx_qvlfd:
11163 case Intrinsic::ppc_qpx_qvlfs:
11164 case Intrinsic::ppc_qpx_qvlfcd:
11165 case Intrinsic::ppc_qpx_qvlfcs:
11166 case Intrinsic::ppc_qpx_qvlfiwa:
11167 case Intrinsic::ppc_qpx_qvlfiwz:
11168 case Intrinsic::ppc_altivec_lvx:
11169 case Intrinsic::ppc_altivec_lvxl:
11170 case Intrinsic::ppc_altivec_lvebx:
11171 case Intrinsic::ppc_altivec_lvehx:
11172 case Intrinsic::ppc_altivec_lvewx:
11173 case Intrinsic::ppc_vsx_lxvd2x:
11174 case Intrinsic::ppc_vsx_lxvw4x: {
11176 switch (Intrinsic) {
11177 case Intrinsic::ppc_altivec_lvebx:
11180 case Intrinsic::ppc_altivec_lvehx:
11183 case Intrinsic::ppc_altivec_lvewx:
11186 case Intrinsic::ppc_vsx_lxvd2x:
11189 case Intrinsic::ppc_qpx_qvlfd:
11192 case Intrinsic::ppc_qpx_qvlfs:
11195 case Intrinsic::ppc_qpx_qvlfcd:
11198 case Intrinsic::ppc_qpx_qvlfcs:
11206 Info.opc = ISD::INTRINSIC_W_CHAIN;
11208 Info.ptrVal = I.getArgOperand(0);
11209 Info.offset = -VT.getStoreSize()+1;
11210 Info.size = 2*VT.getStoreSize()-1;
11213 Info.readMem = true;
11214 Info.writeMem = false;
11217 case Intrinsic::ppc_qpx_qvlfda:
11218 case Intrinsic::ppc_qpx_qvlfsa:
11219 case Intrinsic::ppc_qpx_qvlfcda:
11220 case Intrinsic::ppc_qpx_qvlfcsa:
11221 case Intrinsic::ppc_qpx_qvlfiwaa:
11222 case Intrinsic::ppc_qpx_qvlfiwza: {
11224 switch (Intrinsic) {
11225 case Intrinsic::ppc_qpx_qvlfda:
11228 case Intrinsic::ppc_qpx_qvlfsa:
11231 case Intrinsic::ppc_qpx_qvlfcda:
11234 case Intrinsic::ppc_qpx_qvlfcsa:
11242 Info.opc = ISD::INTRINSIC_W_CHAIN;
11244 Info.ptrVal = I.getArgOperand(0);
11246 Info.size = VT.getStoreSize();
11249 Info.readMem = true;
11250 Info.writeMem = false;
11253 case Intrinsic::ppc_qpx_qvstfd:
11254 case Intrinsic::ppc_qpx_qvstfs:
11255 case Intrinsic::ppc_qpx_qvstfcd:
11256 case Intrinsic::ppc_qpx_qvstfcs:
11257 case Intrinsic::ppc_qpx_qvstfiw:
11258 case Intrinsic::ppc_altivec_stvx:
11259 case Intrinsic::ppc_altivec_stvxl:
11260 case Intrinsic::ppc_altivec_stvebx:
11261 case Intrinsic::ppc_altivec_stvehx:
11262 case Intrinsic::ppc_altivec_stvewx:
11263 case Intrinsic::ppc_vsx_stxvd2x:
11264 case Intrinsic::ppc_vsx_stxvw4x: {
11266 switch (Intrinsic) {
11267 case Intrinsic::ppc_altivec_stvebx:
11270 case Intrinsic::ppc_altivec_stvehx:
11273 case Intrinsic::ppc_altivec_stvewx:
11276 case Intrinsic::ppc_vsx_stxvd2x:
11279 case Intrinsic::ppc_qpx_qvstfd:
11282 case Intrinsic::ppc_qpx_qvstfs:
11285 case Intrinsic::ppc_qpx_qvstfcd:
11288 case Intrinsic::ppc_qpx_qvstfcs:
11296 Info.opc = ISD::INTRINSIC_VOID;
11298 Info.ptrVal = I.getArgOperand(1);
11299 Info.offset = -VT.getStoreSize()+1;
11300 Info.size = 2*VT.getStoreSize()-1;
11303 Info.readMem = false;
11304 Info.writeMem = true;
11307 case Intrinsic::ppc_qpx_qvstfda:
11308 case Intrinsic::ppc_qpx_qvstfsa:
11309 case Intrinsic::ppc_qpx_qvstfcda:
11310 case Intrinsic::ppc_qpx_qvstfcsa:
11311 case Intrinsic::ppc_qpx_qvstfiwa: {
11313 switch (Intrinsic) {
11314 case Intrinsic::ppc_qpx_qvstfda:
11317 case Intrinsic::ppc_qpx_qvstfsa:
11320 case Intrinsic::ppc_qpx_qvstfcda:
11323 case Intrinsic::ppc_qpx_qvstfcsa:
11331 Info.opc = ISD::INTRINSIC_VOID;
11333 Info.ptrVal = I.getArgOperand(1);
11335 Info.size = VT.getStoreSize();
11338 Info.readMem = false;
11339 Info.writeMem = true;
11349 /// getOptimalMemOpType - Returns the target specific optimal type for load
11350 /// and store operations as a result of memset, memcpy, and memmove
11351 /// lowering. If DstAlign is zero that means it's safe to destination
11352 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
11353 /// means there isn't a need to check it against alignment requirement,
11354 /// probably because the source does not need to be loaded. If 'IsMemset' is
11355 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
11356 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
11357 /// source is constant so it does not need to be loaded.
11358 /// It returns EVT::Other if the type should be determined using generic
11359 /// target-independent logic.
11360 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
11361 unsigned DstAlign, unsigned SrcAlign,
11362 bool IsMemset, bool ZeroMemset,
11364 MachineFunction &MF) const {
11365 if (getTargetMachine().getOptLevel() != CodeGenOpt::None) {
11366 const Function *F = MF.getFunction();
11367 // When expanding a memset, require at least two QPX instructions to cover
11368 // the cost of loading the value to be stored from the constant pool.
11369 if (Subtarget.hasQPX() && Size >= 32 && (!IsMemset || Size >= 64) &&
11370 (!SrcAlign || SrcAlign >= 32) && (!DstAlign || DstAlign >= 32) &&
11371 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
11375 // We should use Altivec/VSX loads and stores when available. For unaligned
11376 // addresses, unaligned VSX loads are only fast starting with the P8.
11377 if (Subtarget.hasAltivec() && Size >= 16 &&
11378 (((!SrcAlign || SrcAlign >= 16) && (!DstAlign || DstAlign >= 16)) ||
11379 ((IsMemset && Subtarget.hasVSX()) || Subtarget.hasP8Vector())))
11383 if (Subtarget.isPPC64()) {
11390 /// \brief Returns true if it is beneficial to convert a load of a constant
11391 /// to just the constant itself.
11392 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11394 assert(Ty->isIntegerTy());
11396 unsigned BitSize = Ty->getPrimitiveSizeInBits();
11397 if (BitSize == 0 || BitSize > 64)
11402 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11403 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11405 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11406 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11407 return NumBits1 == 64 && NumBits2 == 32;
11410 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11411 if (!VT1.isInteger() || !VT2.isInteger())
11413 unsigned NumBits1 = VT1.getSizeInBits();
11414 unsigned NumBits2 = VT2.getSizeInBits();
11415 return NumBits1 == 64 && NumBits2 == 32;
11418 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
11419 // Generally speaking, zexts are not free, but they are free when they can be
11420 // folded with other operations.
11421 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
11422 EVT MemVT = LD->getMemoryVT();
11423 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
11424 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
11425 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
11426 LD->getExtensionType() == ISD::ZEXTLOAD))
11430 // FIXME: Add other cases...
11431 // - 32-bit shifts with a zext to i64
11432 // - zext after ctlz, bswap, etc.
11433 // - zext after and by a constant mask
11435 return TargetLowering::isZExtFree(Val, VT2);
11438 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
11439 assert(VT.isFloatingPoint());
11443 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
11444 return isInt<16>(Imm) || isUInt<16>(Imm);
11447 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
11448 return isInt<16>(Imm) || isUInt<16>(Imm);
11451 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
11454 bool *Fast) const {
11455 if (DisablePPCUnaligned)
11458 // PowerPC supports unaligned memory access for simple non-vector types.
11459 // Although accessing unaligned addresses is not as efficient as accessing
11460 // aligned addresses, it is generally more efficient than manual expansion,
11461 // and generally only traps for software emulation when crossing page
11464 if (!VT.isSimple())
11467 if (VT.getSimpleVT().isVector()) {
11468 if (Subtarget.hasVSX()) {
11469 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
11470 VT != MVT::v4f32 && VT != MVT::v4i32)
11477 if (VT == MVT::ppcf128)
11486 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
11487 VT = VT.getScalarType();
11489 if (!VT.isSimple())
11492 switch (VT.getSimpleVT().SimpleTy) {
11504 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
11505 // LR is a callee-save register, but we must treat it as clobbered by any call
11506 // site. Hence we include LR in the scratch registers, which are in turn added
11507 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
11508 // to CTR, which is used by any indirect call.
11509 static const MCPhysReg ScratchRegs[] = {
11510 PPC::X12, PPC::LR8, PPC::CTR8, 0
11513 return ScratchRegs;
11517 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
11518 EVT VT , unsigned DefinedValues) const {
11519 if (VT == MVT::v2i64)
11520 return Subtarget.hasDirectMove(); // Don't need stack ops with direct moves
11522 if (Subtarget.hasQPX()) {
11523 if (VT == MVT::v4f32 || VT == MVT::v4f64 || VT == MVT::v4i1)
11527 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
11530 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
11531 if (DisableILPPref || Subtarget.enableMachineScheduler())
11532 return TargetLowering::getSchedulingPreference(N);
11537 // Create a fast isel object.
11539 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
11540 const TargetLibraryInfo *LibInfo) const {
11541 return PPC::createFastISel(FuncInfo, LibInfo);