1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
43 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
45 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
46 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
49 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
51 // FIXME: Remove this once the bug has been fixed!
52 extern cl::opt<bool> ANDIGlueBug;
54 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
55 // If it isn't a Mach-O file then it's going to be a linux ELF
58 return new TargetLoweringObjectFileMachO();
60 return new PPC64LinuxTargetObjectFile();
63 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
64 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))),
65 Subtarget(*TM.getSubtargetImpl()) {
68 // Use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(true);
72 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
73 // arguments are at least 4/8 bytes aligned.
74 bool isPPC64 = Subtarget.isPPC64();
75 setMinStackArgumentAlignment(isPPC64 ? 8:4);
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
82 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // PowerPC has pre-inc load and store's.
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
100 if (Subtarget.useCRBits()) {
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
103 if (isPPC64 || Subtarget.hasFPCVT()) {
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
108 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
109 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
115 // PowerPC does not support direct load / store of condition registers
116 setOperationAction(ISD::LOAD, MVT::i1, Custom);
117 setOperationAction(ISD::STORE, MVT::i1, Custom);
119 // FIXME: Remove this once the ANDI glue bug is fixed:
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
125 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
127 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
128 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath &&
180 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget.hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath &&
185 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget.hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget.hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget.hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget.useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget.isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget.isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget.has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget.use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget.hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
405 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
407 // add/sub are legal for all supported vector VT's.
408 setOperationAction(ISD::ADD , VT, Legal);
409 setOperationAction(ISD::SUB , VT, Legal);
411 // We promote all shuffles to v16i8.
412 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
413 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
415 // We promote all non-typed operations to v4i32.
416 setOperationAction(ISD::AND , VT, Promote);
417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
418 setOperationAction(ISD::OR , VT, Promote);
419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
420 setOperationAction(ISD::XOR , VT, Promote);
421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
422 setOperationAction(ISD::LOAD , VT, Promote);
423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
424 setOperationAction(ISD::SELECT, VT, Promote);
425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
426 setOperationAction(ISD::STORE, VT, Promote);
427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
429 // No other operations are legal.
430 setOperationAction(ISD::MUL , VT, Expand);
431 setOperationAction(ISD::SDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UDIV, VT, Expand);
434 setOperationAction(ISD::UREM, VT, Expand);
435 setOperationAction(ISD::FDIV, VT, Expand);
436 setOperationAction(ISD::FREM, VT, Expand);
437 setOperationAction(ISD::FNEG, VT, Expand);
438 setOperationAction(ISD::FSQRT, VT, Expand);
439 setOperationAction(ISD::FLOG, VT, Expand);
440 setOperationAction(ISD::FLOG10, VT, Expand);
441 setOperationAction(ISD::FLOG2, VT, Expand);
442 setOperationAction(ISD::FEXP, VT, Expand);
443 setOperationAction(ISD::FEXP2, VT, Expand);
444 setOperationAction(ISD::FSIN, VT, Expand);
445 setOperationAction(ISD::FCOS, VT, Expand);
446 setOperationAction(ISD::FABS, VT, Expand);
447 setOperationAction(ISD::FPOWI, VT, Expand);
448 setOperationAction(ISD::FFLOOR, VT, Expand);
449 setOperationAction(ISD::FCEIL, VT, Expand);
450 setOperationAction(ISD::FTRUNC, VT, Expand);
451 setOperationAction(ISD::FRINT, VT, Expand);
452 setOperationAction(ISD::FNEARBYINT, VT, Expand);
453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
455 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
456 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
457 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
458 setOperationAction(ISD::UDIVREM, VT, Expand);
459 setOperationAction(ISD::SDIVREM, VT, Expand);
460 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
461 setOperationAction(ISD::FPOW, VT, Expand);
462 setOperationAction(ISD::BSWAP, VT, Expand);
463 setOperationAction(ISD::CTPOP, VT, Expand);
464 setOperationAction(ISD::CTLZ, VT, Expand);
465 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
466 setOperationAction(ISD::CTTZ, VT, Expand);
467 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
468 setOperationAction(ISD::VSELECT, VT, Expand);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
471 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
472 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
473 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
474 setTruncStoreAction(VT, InnerVT, Expand);
476 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
477 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
478 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
481 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
482 // with merges, splats, etc.
483 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
485 setOperationAction(ISD::AND , MVT::v4i32, Legal);
486 setOperationAction(ISD::OR , MVT::v4i32, Legal);
487 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
488 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
489 setOperationAction(ISD::SELECT, MVT::v4i32,
490 Subtarget.useCRBits() ? Legal : Expand);
491 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
492 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
493 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
494 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
495 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
496 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
497 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
498 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
499 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
501 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
502 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
503 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
504 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
506 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
507 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
509 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
510 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
511 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
514 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
515 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
516 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
518 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
519 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
521 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
522 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
524 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
526 // Altivec does not contain unordered floating-point compare instructions
527 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
528 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
529 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
530 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
531 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
532 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
534 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
535 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
537 if (Subtarget.hasVSX()) {
538 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
541 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
542 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
543 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
544 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
545 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
547 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
549 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
550 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
552 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
553 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
559 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
561 // Share the Altivec comparison restrictions.
562 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
563 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
564 setCondCodeAction(ISD::SETUGT, MVT::v2f64, Expand);
565 setCondCodeAction(ISD::SETUGE, MVT::v2f64, Expand);
566 setCondCodeAction(ISD::SETULT, MVT::v2f64, Expand);
567 setCondCodeAction(ISD::SETULE, MVT::v2f64, Expand);
569 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
570 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
572 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
573 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
575 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
577 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
579 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
580 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
582 // VSX v2i64 only supports non-arithmetic operations.
583 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
584 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
586 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
587 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
588 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
590 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
592 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
593 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
594 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
595 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
597 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
599 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
600 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
601 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
602 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
604 // Vector operation legalization checks the result type of
605 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
608 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
611 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
615 if (Subtarget.has64BitSupport()) {
616 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
617 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
620 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
621 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
622 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
623 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
625 setBooleanContents(ZeroOrOneBooleanContent);
626 // Altivec instructions set fields to all zeros or all ones.
627 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
630 setStackPointerRegisterToSaveRestore(PPC::X1);
631 setExceptionPointerRegister(PPC::X3);
632 setExceptionSelectorRegister(PPC::X4);
634 setStackPointerRegisterToSaveRestore(PPC::R1);
635 setExceptionPointerRegister(PPC::R3);
636 setExceptionSelectorRegister(PPC::R4);
639 // We have target-specific dag combine patterns for the following nodes:
640 setTargetDAGCombine(ISD::SINT_TO_FP);
641 setTargetDAGCombine(ISD::LOAD);
642 setTargetDAGCombine(ISD::STORE);
643 setTargetDAGCombine(ISD::BR_CC);
644 if (Subtarget.useCRBits())
645 setTargetDAGCombine(ISD::BRCOND);
646 setTargetDAGCombine(ISD::BSWAP);
647 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
649 setTargetDAGCombine(ISD::SIGN_EXTEND);
650 setTargetDAGCombine(ISD::ZERO_EXTEND);
651 setTargetDAGCombine(ISD::ANY_EXTEND);
653 if (Subtarget.useCRBits()) {
654 setTargetDAGCombine(ISD::TRUNCATE);
655 setTargetDAGCombine(ISD::SETCC);
656 setTargetDAGCombine(ISD::SELECT_CC);
659 // Use reciprocal estimates.
660 if (TM.Options.UnsafeFPMath) {
661 setTargetDAGCombine(ISD::FDIV);
662 setTargetDAGCombine(ISD::FSQRT);
665 // Darwin long double math library functions have $LDBL128 appended.
666 if (Subtarget.isDarwin()) {
667 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
668 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
669 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
670 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
671 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
672 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
673 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
674 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
675 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
676 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
679 // With 32 condition bits, we don't need to sink (and duplicate) compares
680 // aggressively in CodeGenPrep.
681 if (Subtarget.useCRBits())
682 setHasMultipleConditionRegisters();
684 setMinFunctionAlignment(2);
685 if (Subtarget.isDarwin())
686 setPrefFunctionAlignment(4);
688 if (isPPC64 && Subtarget.isJITCodeModel())
689 // Temporary workaround for the inability of PPC64 JIT to handle jump
691 setSupportJumpTables(false);
693 setInsertFencesForAtomic(true);
695 if (Subtarget.enableMachineScheduler())
696 setSchedulingPreference(Sched::Source);
698 setSchedulingPreference(Sched::Hybrid);
700 computeRegisterProperties();
702 // The Freescale cores does better with aggressive inlining of memcpy and
703 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
704 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
705 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
706 MaxStoresPerMemset = 32;
707 MaxStoresPerMemsetOptSize = 16;
708 MaxStoresPerMemcpy = 32;
709 MaxStoresPerMemcpyOptSize = 8;
710 MaxStoresPerMemmove = 32;
711 MaxStoresPerMemmoveOptSize = 8;
713 setPrefFunctionAlignment(4);
717 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
718 /// the desired ByVal argument alignment.
719 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
720 unsigned MaxMaxAlign) {
721 if (MaxAlign == MaxMaxAlign)
723 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
724 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
726 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
728 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
729 unsigned EltAlign = 0;
730 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
731 if (EltAlign > MaxAlign)
733 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
734 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
735 unsigned EltAlign = 0;
736 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
737 if (EltAlign > MaxAlign)
739 if (MaxAlign == MaxMaxAlign)
745 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
746 /// function arguments in the caller parameter area.
747 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
748 // Darwin passes everything on 4 byte boundary.
749 if (Subtarget.isDarwin())
752 // 16byte and wider vectors are passed on 16byte boundary.
753 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
754 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
755 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
756 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
760 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
762 default: return nullptr;
763 case PPCISD::FSEL: return "PPCISD::FSEL";
764 case PPCISD::FCFID: return "PPCISD::FCFID";
765 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
766 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
767 case PPCISD::FRE: return "PPCISD::FRE";
768 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
769 case PPCISD::STFIWX: return "PPCISD::STFIWX";
770 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
771 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
772 case PPCISD::VPERM: return "PPCISD::VPERM";
773 case PPCISD::Hi: return "PPCISD::Hi";
774 case PPCISD::Lo: return "PPCISD::Lo";
775 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
776 case PPCISD::LOAD: return "PPCISD::LOAD";
777 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
778 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
779 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
780 case PPCISD::SRL: return "PPCISD::SRL";
781 case PPCISD::SRA: return "PPCISD::SRA";
782 case PPCISD::SHL: return "PPCISD::SHL";
783 case PPCISD::CALL: return "PPCISD::CALL";
784 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
785 case PPCISD::MTCTR: return "PPCISD::MTCTR";
786 case PPCISD::BCTRL: return "PPCISD::BCTRL";
787 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
788 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
789 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
790 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
791 case PPCISD::VCMP: return "PPCISD::VCMP";
792 case PPCISD::VCMPo: return "PPCISD::VCMPo";
793 case PPCISD::LBRX: return "PPCISD::LBRX";
794 case PPCISD::STBRX: return "PPCISD::STBRX";
795 case PPCISD::LARX: return "PPCISD::LARX";
796 case PPCISD::STCX: return "PPCISD::STCX";
797 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
798 case PPCISD::BDNZ: return "PPCISD::BDNZ";
799 case PPCISD::BDZ: return "PPCISD::BDZ";
800 case PPCISD::MFFS: return "PPCISD::MFFS";
801 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
802 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
803 case PPCISD::CR6SET: return "PPCISD::CR6SET";
804 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
805 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
806 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
807 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
808 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
809 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
810 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
811 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
812 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
813 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
814 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
815 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
816 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
817 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
818 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
819 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
820 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
821 case PPCISD::SC: return "PPCISD::SC";
825 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
827 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
828 return VT.changeVectorElementTypeToInteger();
831 //===----------------------------------------------------------------------===//
832 // Node matching predicates, for use by the tblgen matching code.
833 //===----------------------------------------------------------------------===//
835 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
836 static bool isFloatingPointZero(SDValue Op) {
837 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
838 return CFP->getValueAPF().isZero();
839 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
840 // Maybe this has already been legalized into the constant pool?
841 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
842 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
843 return CFP->getValueAPF().isZero();
848 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
849 /// true if Op is undef or if it matches the specified value.
850 static bool isConstantOrUndef(int Op, int Val) {
851 return Op < 0 || Op == Val;
854 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
855 /// VPKUHUM instruction.
856 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
858 unsigned j = DAG.getTarget().getDataLayout()->isLittleEndian() ? 0 : 1;
860 for (unsigned i = 0; i != 16; ++i)
861 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j))
864 for (unsigned i = 0; i != 8; ++i)
865 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
866 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
872 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
873 /// VPKUWUM instruction.
874 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
877 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
885 for (unsigned i = 0; i != 16; i += 2)
886 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
887 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k))
890 for (unsigned i = 0; i != 8; i += 2)
891 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
892 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k) ||
893 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
894 !isConstantOrUndef(N->getMaskElt(i+9), i*2+k))
900 /// isVMerge - Common function, used to match vmrg* shuffles.
902 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
903 unsigned LHSStart, unsigned RHSStart) {
904 if (N->getValueType(0) != MVT::v16i8)
906 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
907 "Unsupported merge size!");
909 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
910 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
911 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
912 LHSStart+j+i*UnitSize) ||
913 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
914 RHSStart+j+i*UnitSize))
920 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
921 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
922 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
923 bool isUnary, SelectionDAG &DAG) {
924 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
926 return isVMerge(N, UnitSize, 0, 16);
927 return isVMerge(N, UnitSize, 0, 0);
930 return isVMerge(N, UnitSize, 8, 24);
931 return isVMerge(N, UnitSize, 8, 8);
935 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
936 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
937 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
938 bool isUnary, SelectionDAG &DAG) {
939 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
941 return isVMerge(N, UnitSize, 8, 24);
942 return isVMerge(N, UnitSize, 8, 8);
945 return isVMerge(N, UnitSize, 0, 16);
946 return isVMerge(N, UnitSize, 0, 0);
951 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
952 /// amount, otherwise return -1.
953 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG) {
954 if (N->getValueType(0) != MVT::v16i8)
957 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
959 // Find the first non-undef value in the shuffle mask.
961 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
964 if (i == 16) return -1; // all undef.
966 // Otherwise, check to see if the rest of the elements are consecutively
967 // numbered from this value.
968 unsigned ShiftAmt = SVOp->getMaskElt(i);
969 if (ShiftAmt < i) return -1;
971 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
976 // Check the rest of the elements to see if they are consecutive.
977 for (++i; i != 16; ++i)
978 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt - i))
981 // Check the rest of the elements to see if they are consecutive.
982 for (++i; i != 16; ++i)
983 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt - i) & 15))
987 } else { // Big Endian
992 // Check the rest of the elements to see if they are consecutive.
993 for (++i; i != 16; ++i)
994 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
997 // Check the rest of the elements to see if they are consecutive.
998 for (++i; i != 16; ++i)
999 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1006 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1007 /// specifies a splat of a single element that is suitable for input to
1008 /// VSPLTB/VSPLTH/VSPLTW.
1009 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1010 assert(N->getValueType(0) == MVT::v16i8 &&
1011 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1013 // This is a splat operation if each element of the permute is the same, and
1014 // if the value doesn't reference the second vector.
1015 unsigned ElementBase = N->getMaskElt(0);
1017 // FIXME: Handle UNDEF elements too!
1018 if (ElementBase >= 16)
1021 // Check that the indices are consecutive, in the case of a multi-byte element
1022 // splatted with a v16i8 mask.
1023 for (unsigned i = 1; i != EltSize; ++i)
1024 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1027 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1028 if (N->getMaskElt(i) < 0) continue;
1029 for (unsigned j = 0; j != EltSize; ++j)
1030 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1036 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1038 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1039 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1041 APInt APVal, APUndef;
1045 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1046 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1047 return CFP->getValueAPF().isNegZero();
1052 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1053 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1054 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1055 SelectionDAG &DAG) {
1056 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1057 assert(isSplatShuffleMask(SVOp, EltSize));
1058 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1059 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1061 return SVOp->getMaskElt(0) / EltSize;
1064 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1065 /// by using a vspltis[bhw] instruction of the specified element size, return
1066 /// the constant being splatted. The ByteSize field indicates the number of
1067 /// bytes of each element [124] -> [bhw].
1068 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1069 SDValue OpVal(nullptr, 0);
1071 // If ByteSize of the splat is bigger than the element size of the
1072 // build_vector, then we have a case where we are checking for a splat where
1073 // multiple elements of the buildvector are folded together into a single
1074 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1075 unsigned EltSize = 16/N->getNumOperands();
1076 if (EltSize < ByteSize) {
1077 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1078 SDValue UniquedVals[4];
1079 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1081 // See if all of the elements in the buildvector agree across.
1082 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1083 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1084 // If the element isn't a constant, bail fully out.
1085 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1088 if (!UniquedVals[i&(Multiple-1)].getNode())
1089 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1090 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1091 return SDValue(); // no match.
1094 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1095 // either constant or undef values that are identical for each chunk. See
1096 // if these chunks can form into a larger vspltis*.
1098 // Check to see if all of the leading entries are either 0 or -1. If
1099 // neither, then this won't fit into the immediate field.
1100 bool LeadingZero = true;
1101 bool LeadingOnes = true;
1102 for (unsigned i = 0; i != Multiple-1; ++i) {
1103 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1105 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1106 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1108 // Finally, check the least significant entry.
1110 if (!UniquedVals[Multiple-1].getNode())
1111 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1112 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1114 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1117 if (!UniquedVals[Multiple-1].getNode())
1118 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1119 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1120 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1121 return DAG.getTargetConstant(Val, MVT::i32);
1127 // Check to see if this buildvec has a single non-undef value in its elements.
1128 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1129 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1130 if (!OpVal.getNode())
1131 OpVal = N->getOperand(i);
1132 else if (OpVal != N->getOperand(i))
1136 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1138 unsigned ValSizeInBytes = EltSize;
1140 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1141 Value = CN->getZExtValue();
1142 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1143 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1144 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1147 // If the splat value is larger than the element value, then we can never do
1148 // this splat. The only case that we could fit the replicated bits into our
1149 // immediate field for would be zero, and we prefer to use vxor for it.
1150 if (ValSizeInBytes < ByteSize) return SDValue();
1152 // If the element value is larger than the splat value, cut it in half and
1153 // check to see if the two halves are equal. Continue doing this until we
1154 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1155 while (ValSizeInBytes > ByteSize) {
1156 ValSizeInBytes >>= 1;
1158 // If the top half equals the bottom half, we're still ok.
1159 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1160 (Value & ((1 << (8*ValSizeInBytes))-1)))
1164 // Properly sign extend the value.
1165 int MaskVal = SignExtend32(Value, ByteSize * 8);
1167 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1168 if (MaskVal == 0) return SDValue();
1170 // Finally, if this value fits in a 5 bit sext field, return it
1171 if (SignExtend32<5>(MaskVal) == MaskVal)
1172 return DAG.getTargetConstant(MaskVal, MVT::i32);
1176 //===----------------------------------------------------------------------===//
1177 // Addressing Mode Selection
1178 //===----------------------------------------------------------------------===//
1180 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1181 /// or 64-bit immediate, and if the value can be accurately represented as a
1182 /// sign extension from a 16-bit value. If so, this returns true and the
1184 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1185 if (!isa<ConstantSDNode>(N))
1188 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1189 if (N->getValueType(0) == MVT::i32)
1190 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1192 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1194 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1195 return isIntS16Immediate(Op.getNode(), Imm);
1199 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1200 /// can be represented as an indexed [r+r] operation. Returns false if it
1201 /// can be more efficiently represented with [r+imm].
1202 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1204 SelectionDAG &DAG) const {
1206 if (N.getOpcode() == ISD::ADD) {
1207 if (isIntS16Immediate(N.getOperand(1), imm))
1208 return false; // r+i
1209 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1210 return false; // r+i
1212 Base = N.getOperand(0);
1213 Index = N.getOperand(1);
1215 } else if (N.getOpcode() == ISD::OR) {
1216 if (isIntS16Immediate(N.getOperand(1), imm))
1217 return false; // r+i can fold it if we can.
1219 // If this is an or of disjoint bitfields, we can codegen this as an add
1220 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1222 APInt LHSKnownZero, LHSKnownOne;
1223 APInt RHSKnownZero, RHSKnownOne;
1224 DAG.computeKnownBits(N.getOperand(0),
1225 LHSKnownZero, LHSKnownOne);
1227 if (LHSKnownZero.getBoolValue()) {
1228 DAG.computeKnownBits(N.getOperand(1),
1229 RHSKnownZero, RHSKnownOne);
1230 // If all of the bits are known zero on the LHS or RHS, the add won't
1232 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1233 Base = N.getOperand(0);
1234 Index = N.getOperand(1);
1243 // If we happen to be doing an i64 load or store into a stack slot that has
1244 // less than a 4-byte alignment, then the frame-index elimination may need to
1245 // use an indexed load or store instruction (because the offset may not be a
1246 // multiple of 4). The extra register needed to hold the offset comes from the
1247 // register scavenger, and it is possible that the scavenger will need to use
1248 // an emergency spill slot. As a result, we need to make sure that a spill slot
1249 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1251 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1252 // FIXME: This does not handle the LWA case.
1256 // NOTE: We'll exclude negative FIs here, which come from argument
1257 // lowering, because there are no known test cases triggering this problem
1258 // using packed structures (or similar). We can remove this exclusion if
1259 // we find such a test case. The reason why this is so test-case driven is
1260 // because this entire 'fixup' is only to prevent crashes (from the
1261 // register scavenger) on not-really-valid inputs. For example, if we have:
1263 // %b = bitcast i1* %a to i64*
1264 // store i64* a, i64 b
1265 // then the store should really be marked as 'align 1', but is not. If it
1266 // were marked as 'align 1' then the indexed form would have been
1267 // instruction-selected initially, and the problem this 'fixup' is preventing
1268 // won't happen regardless.
1272 MachineFunction &MF = DAG.getMachineFunction();
1273 MachineFrameInfo *MFI = MF.getFrameInfo();
1275 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1279 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1280 FuncInfo->setHasNonRISpills();
1283 /// Returns true if the address N can be represented by a base register plus
1284 /// a signed 16-bit displacement [r+imm], and if it is not better
1285 /// represented as reg+reg. If Aligned is true, only accept displacements
1286 /// suitable for STD and friends, i.e. multiples of 4.
1287 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1290 bool Aligned) const {
1291 // FIXME dl should come from parent load or store, not from address
1293 // If this can be more profitably realized as r+r, fail.
1294 if (SelectAddressRegReg(N, Disp, Base, DAG))
1297 if (N.getOpcode() == ISD::ADD) {
1299 if (isIntS16Immediate(N.getOperand(1), imm) &&
1300 (!Aligned || (imm & 3) == 0)) {
1301 Disp = DAG.getTargetConstant(imm, N.getValueType());
1302 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1303 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1304 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1306 Base = N.getOperand(0);
1308 return true; // [r+i]
1309 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1310 // Match LOAD (ADD (X, Lo(G))).
1311 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1312 && "Cannot handle constant offsets yet!");
1313 Disp = N.getOperand(1).getOperand(0); // The global address.
1314 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1315 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1316 Disp.getOpcode() == ISD::TargetConstantPool ||
1317 Disp.getOpcode() == ISD::TargetJumpTable);
1318 Base = N.getOperand(0);
1319 return true; // [&g+r]
1321 } else if (N.getOpcode() == ISD::OR) {
1323 if (isIntS16Immediate(N.getOperand(1), imm) &&
1324 (!Aligned || (imm & 3) == 0)) {
1325 // If this is an or of disjoint bitfields, we can codegen this as an add
1326 // (for better address arithmetic) if the LHS and RHS of the OR are
1327 // provably disjoint.
1328 APInt LHSKnownZero, LHSKnownOne;
1329 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1331 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1332 // If all of the bits are known zero on the LHS or RHS, the add won't
1334 if (FrameIndexSDNode *FI =
1335 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1336 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1337 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1339 Base = N.getOperand(0);
1341 Disp = DAG.getTargetConstant(imm, N.getValueType());
1345 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1346 // Loading from a constant address.
1348 // If this address fits entirely in a 16-bit sext immediate field, codegen
1351 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1352 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1353 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1354 CN->getValueType(0));
1358 // Handle 32-bit sext immediates with LIS + addr mode.
1359 if ((CN->getValueType(0) == MVT::i32 ||
1360 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1361 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1362 int Addr = (int)CN->getZExtValue();
1364 // Otherwise, break this down into an LIS + disp.
1365 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1367 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1368 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1369 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1374 Disp = DAG.getTargetConstant(0, getPointerTy());
1375 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1376 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1377 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1380 return true; // [r+0]
1383 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1384 /// represented as an indexed [r+r] operation.
1385 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1387 SelectionDAG &DAG) const {
1388 // Check to see if we can easily represent this as an [r+r] address. This
1389 // will fail if it thinks that the address is more profitably represented as
1390 // reg+imm, e.g. where imm = 0.
1391 if (SelectAddressRegReg(N, Base, Index, DAG))
1394 // If the operand is an addition, always emit this as [r+r], since this is
1395 // better (for code size, and execution, as the memop does the add for free)
1396 // than emitting an explicit add.
1397 if (N.getOpcode() == ISD::ADD) {
1398 Base = N.getOperand(0);
1399 Index = N.getOperand(1);
1403 // Otherwise, do it the hard way, using R0 as the base register.
1404 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1410 /// getPreIndexedAddressParts - returns true by value, base pointer and
1411 /// offset pointer and addressing mode by reference if the node's address
1412 /// can be legally represented as pre-indexed load / store address.
1413 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1415 ISD::MemIndexedMode &AM,
1416 SelectionDAG &DAG) const {
1417 if (DisablePPCPreinc) return false;
1423 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1424 Ptr = LD->getBasePtr();
1425 VT = LD->getMemoryVT();
1426 Alignment = LD->getAlignment();
1427 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1428 Ptr = ST->getBasePtr();
1429 VT = ST->getMemoryVT();
1430 Alignment = ST->getAlignment();
1435 // PowerPC doesn't have preinc load/store instructions for vectors.
1439 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1441 // Common code will reject creating a pre-inc form if the base pointer
1442 // is a frame index, or if N is a store and the base pointer is either
1443 // the same as or a predecessor of the value being stored. Check for
1444 // those situations here, and try with swapped Base/Offset instead.
1447 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1450 SDValue Val = cast<StoreSDNode>(N)->getValue();
1451 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1456 std::swap(Base, Offset);
1462 // LDU/STU can only handle immediates that are a multiple of 4.
1463 if (VT != MVT::i64) {
1464 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1467 // LDU/STU need an address with at least 4-byte alignment.
1471 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1475 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1476 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1477 // sext i32 to i64 when addr mode is r+i.
1478 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1479 LD->getExtensionType() == ISD::SEXTLOAD &&
1480 isa<ConstantSDNode>(Offset))
1488 //===----------------------------------------------------------------------===//
1489 // LowerOperation implementation
1490 //===----------------------------------------------------------------------===//
1492 /// GetLabelAccessInfo - Return true if we should reference labels using a
1493 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1494 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1495 unsigned &LoOpFlags,
1496 const GlobalValue *GV = nullptr) {
1497 HiOpFlags = PPCII::MO_HA;
1498 LoOpFlags = PPCII::MO_LO;
1500 // Don't use the pic base if not in PIC relocation model.
1501 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1504 HiOpFlags |= PPCII::MO_PIC_FLAG;
1505 LoOpFlags |= PPCII::MO_PIC_FLAG;
1508 // If this is a reference to a global value that requires a non-lazy-ptr, make
1509 // sure that instruction lowering adds it.
1510 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1511 HiOpFlags |= PPCII::MO_NLP_FLAG;
1512 LoOpFlags |= PPCII::MO_NLP_FLAG;
1514 if (GV->hasHiddenVisibility()) {
1515 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1516 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1523 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1524 SelectionDAG &DAG) {
1525 EVT PtrVT = HiPart.getValueType();
1526 SDValue Zero = DAG.getConstant(0, PtrVT);
1529 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1530 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1532 // With PIC, the first instruction is actually "GR+hi(&G)".
1534 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1535 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1537 // Generate non-pic code that has direct accesses to the constant pool.
1538 // The address of the global is just (hi(&g)+lo(&g)).
1539 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1542 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1543 SelectionDAG &DAG) const {
1544 EVT PtrVT = Op.getValueType();
1545 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1546 const Constant *C = CP->getConstVal();
1548 // 64-bit SVR4 ABI code is always position-independent.
1549 // The actual address of the GlobalValue is stored in the TOC.
1550 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1551 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1552 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1553 DAG.getRegister(PPC::X2, MVT::i64));
1556 unsigned MOHiFlag, MOLoFlag;
1557 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1559 if (isPIC && Subtarget.isSVR4ABI()) {
1560 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1561 PPCII::MO_PIC_FLAG);
1563 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1564 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1568 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1570 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1571 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1574 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1575 EVT PtrVT = Op.getValueType();
1576 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1578 // 64-bit SVR4 ABI code is always position-independent.
1579 // The actual address of the GlobalValue is stored in the TOC.
1580 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1581 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1582 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1583 DAG.getRegister(PPC::X2, MVT::i64));
1586 unsigned MOHiFlag, MOLoFlag;
1587 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1589 if (isPIC && Subtarget.isSVR4ABI()) {
1590 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1591 PPCII::MO_PIC_FLAG);
1593 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1594 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1597 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1598 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1599 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1602 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1603 SelectionDAG &DAG) const {
1604 EVT PtrVT = Op.getValueType();
1606 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1608 unsigned MOHiFlag, MOLoFlag;
1609 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1610 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1611 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1612 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1615 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1616 SelectionDAG &DAG) const {
1618 // FIXME: TLS addresses currently use medium model code sequences,
1619 // which is the most useful form. Eventually support for small and
1620 // large models could be added if users need it, at the cost of
1621 // additional complexity.
1622 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1624 const GlobalValue *GV = GA->getGlobal();
1625 EVT PtrVT = getPointerTy();
1626 bool is64bit = Subtarget.isPPC64();
1628 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1630 if (Model == TLSModel::LocalExec) {
1631 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1632 PPCII::MO_TPREL_HA);
1633 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1634 PPCII::MO_TPREL_LO);
1635 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1636 is64bit ? MVT::i64 : MVT::i32);
1637 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1638 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1641 if (Model == TLSModel::InitialExec) {
1642 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1643 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1647 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1648 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1649 PtrVT, GOTReg, TGA);
1651 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1652 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1653 PtrVT, TGA, GOTPtr);
1654 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1657 if (Model == TLSModel::GeneralDynamic) {
1658 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1659 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1660 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1662 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1665 // We need a chain node, and don't have one handy. The underlying
1666 // call has no side effects, so using the function entry node
1668 SDValue Chain = DAG.getEntryNode();
1669 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1670 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1671 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1672 PtrVT, ParmReg, TGA);
1673 // The return value from GET_TLS_ADDR really is in X3 already, but
1674 // some hacks are needed here to tie everything together. The extra
1675 // copies dissolve during subsequent transforms.
1676 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1677 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1680 if (Model == TLSModel::LocalDynamic) {
1681 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1682 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1683 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1685 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1688 // We need a chain node, and don't have one handy. The underlying
1689 // call has no side effects, so using the function entry node
1691 SDValue Chain = DAG.getEntryNode();
1692 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1693 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1694 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1695 PtrVT, ParmReg, TGA);
1696 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1697 // some hacks are needed here to tie everything together. The extra
1698 // copies dissolve during subsequent transforms.
1699 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1700 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1701 Chain, ParmReg, TGA);
1702 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1705 llvm_unreachable("Unknown TLS model!");
1708 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1709 SelectionDAG &DAG) const {
1710 EVT PtrVT = Op.getValueType();
1711 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1713 const GlobalValue *GV = GSDN->getGlobal();
1715 // 64-bit SVR4 ABI code is always position-independent.
1716 // The actual address of the GlobalValue is stored in the TOC.
1717 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1718 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1719 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1720 DAG.getRegister(PPC::X2, MVT::i64));
1723 unsigned MOHiFlag, MOLoFlag;
1724 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1726 if (isPIC && Subtarget.isSVR4ABI()) {
1727 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1729 PPCII::MO_PIC_FLAG);
1730 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1731 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1735 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1737 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1739 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1741 // If the global reference is actually to a non-lazy-pointer, we have to do an
1742 // extra load to get the address of the global.
1743 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1744 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1745 false, false, false, 0);
1749 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1750 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1753 if (Op.getValueType() == MVT::v2i64) {
1754 // When the operands themselves are v2i64 values, we need to do something
1755 // special because VSX has no underlying comparison operations for these.
1756 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1757 // Equality can be handled by casting to the legal type for Altivec
1758 // comparisons, everything else needs to be expanded.
1759 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1760 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1761 DAG.getSetCC(dl, MVT::v4i32,
1762 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1763 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1770 // We handle most of these in the usual way.
1774 // If we're comparing for equality to zero, expose the fact that this is
1775 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1776 // fold the new nodes.
1777 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1778 if (C->isNullValue() && CC == ISD::SETEQ) {
1779 EVT VT = Op.getOperand(0).getValueType();
1780 SDValue Zext = Op.getOperand(0);
1781 if (VT.bitsLT(MVT::i32)) {
1783 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1785 unsigned Log2b = Log2_32(VT.getSizeInBits());
1786 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1787 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1788 DAG.getConstant(Log2b, MVT::i32));
1789 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1791 // Leave comparisons against 0 and -1 alone for now, since they're usually
1792 // optimized. FIXME: revisit this when we can custom lower all setcc
1794 if (C->isAllOnesValue() || C->isNullValue())
1798 // If we have an integer seteq/setne, turn it into a compare against zero
1799 // by xor'ing the rhs with the lhs, which is faster than setting a
1800 // condition register, reading it back out, and masking the correct bit. The
1801 // normal approach here uses sub to do this instead of xor. Using xor exposes
1802 // the result to other bit-twiddling opportunities.
1803 EVT LHSVT = Op.getOperand(0).getValueType();
1804 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1805 EVT VT = Op.getValueType();
1806 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1808 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1813 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1814 const PPCSubtarget &Subtarget) const {
1815 SDNode *Node = Op.getNode();
1816 EVT VT = Node->getValueType(0);
1817 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1818 SDValue InChain = Node->getOperand(0);
1819 SDValue VAListPtr = Node->getOperand(1);
1820 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1823 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1826 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1827 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1829 InChain = GprIndex.getValue(1);
1831 if (VT == MVT::i64) {
1832 // Check if GprIndex is even
1833 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1834 DAG.getConstant(1, MVT::i32));
1835 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1836 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1837 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1838 DAG.getConstant(1, MVT::i32));
1839 // Align GprIndex to be even if it isn't
1840 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1844 // fpr index is 1 byte after gpr
1845 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1846 DAG.getConstant(1, MVT::i32));
1849 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1850 FprPtr, MachinePointerInfo(SV), MVT::i8,
1852 InChain = FprIndex.getValue(1);
1854 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1855 DAG.getConstant(8, MVT::i32));
1857 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1858 DAG.getConstant(4, MVT::i32));
1861 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1862 MachinePointerInfo(), false, false,
1864 InChain = OverflowArea.getValue(1);
1866 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1867 MachinePointerInfo(), false, false,
1869 InChain = RegSaveArea.getValue(1);
1871 // select overflow_area if index > 8
1872 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1873 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1875 // adjustment constant gpr_index * 4/8
1876 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1877 VT.isInteger() ? GprIndex : FprIndex,
1878 DAG.getConstant(VT.isInteger() ? 4 : 8,
1881 // OurReg = RegSaveArea + RegConstant
1882 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1885 // Floating types are 32 bytes into RegSaveArea
1886 if (VT.isFloatingPoint())
1887 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1888 DAG.getConstant(32, MVT::i32));
1890 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1891 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1892 VT.isInteger() ? GprIndex : FprIndex,
1893 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1896 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1897 VT.isInteger() ? VAListPtr : FprPtr,
1898 MachinePointerInfo(SV),
1899 MVT::i8, false, false, 0);
1901 // determine if we should load from reg_save_area or overflow_area
1902 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1904 // increase overflow_area by 4/8 if gpr/fpr > 8
1905 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1906 DAG.getConstant(VT.isInteger() ? 4 : 8,
1909 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1912 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1914 MachinePointerInfo(),
1915 MVT::i32, false, false, 0);
1917 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1918 false, false, false, 0);
1921 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1922 const PPCSubtarget &Subtarget) const {
1923 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1925 // We have to copy the entire va_list struct:
1926 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1927 return DAG.getMemcpy(Op.getOperand(0), Op,
1928 Op.getOperand(1), Op.getOperand(2),
1929 DAG.getConstant(12, MVT::i32), 8, false, true,
1930 MachinePointerInfo(), MachinePointerInfo());
1933 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1934 SelectionDAG &DAG) const {
1935 return Op.getOperand(0);
1938 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1939 SelectionDAG &DAG) const {
1940 SDValue Chain = Op.getOperand(0);
1941 SDValue Trmp = Op.getOperand(1); // trampoline
1942 SDValue FPtr = Op.getOperand(2); // nested function
1943 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1946 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1947 bool isPPC64 = (PtrVT == MVT::i64);
1949 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1952 TargetLowering::ArgListTy Args;
1953 TargetLowering::ArgListEntry Entry;
1955 Entry.Ty = IntPtrTy;
1956 Entry.Node = Trmp; Args.push_back(Entry);
1958 // TrampSize == (isPPC64 ? 48 : 40);
1959 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1960 isPPC64 ? MVT::i64 : MVT::i32);
1961 Args.push_back(Entry);
1963 Entry.Node = FPtr; Args.push_back(Entry);
1964 Entry.Node = Nest; Args.push_back(Entry);
1966 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1967 TargetLowering::CallLoweringInfo CLI(DAG);
1968 CLI.setDebugLoc(dl).setChain(Chain)
1969 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
1970 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1971 std::move(Args), 0);
1973 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1974 return CallResult.second;
1977 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1978 const PPCSubtarget &Subtarget) const {
1979 MachineFunction &MF = DAG.getMachineFunction();
1980 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1984 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1985 // vastart just stores the address of the VarArgsFrameIndex slot into the
1986 // memory location argument.
1987 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1988 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1989 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1990 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1991 MachinePointerInfo(SV),
1995 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1996 // We suppose the given va_list is already allocated.
1999 // char gpr; /* index into the array of 8 GPRs
2000 // * stored in the register save area
2001 // * gpr=0 corresponds to r3,
2002 // * gpr=1 to r4, etc.
2004 // char fpr; /* index into the array of 8 FPRs
2005 // * stored in the register save area
2006 // * fpr=0 corresponds to f1,
2007 // * fpr=1 to f2, etc.
2009 // char *overflow_arg_area;
2010 // /* location on stack that holds
2011 // * the next overflow argument
2013 // char *reg_save_area;
2014 // /* where r3:r10 and f1:f8 (if saved)
2020 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2021 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2024 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2026 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2028 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2031 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2032 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2034 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2035 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2037 uint64_t FPROffset = 1;
2038 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2040 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2042 // Store first byte : number of int regs
2043 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2045 MachinePointerInfo(SV),
2046 MVT::i8, false, false, 0);
2047 uint64_t nextOffset = FPROffset;
2048 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2051 // Store second byte : number of float regs
2052 SDValue secondStore =
2053 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2054 MachinePointerInfo(SV, nextOffset), MVT::i8,
2056 nextOffset += StackOffset;
2057 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2059 // Store second word : arguments given on stack
2060 SDValue thirdStore =
2061 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2062 MachinePointerInfo(SV, nextOffset),
2064 nextOffset += FrameOffset;
2065 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2067 // Store third word : arguments given in registers
2068 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2069 MachinePointerInfo(SV, nextOffset),
2074 #include "PPCGenCallingConv.inc"
2076 // Function whose sole purpose is to kill compiler warnings
2077 // stemming from unused functions included from PPCGenCallingConv.inc.
2078 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2079 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2082 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2083 CCValAssign::LocInfo &LocInfo,
2084 ISD::ArgFlagsTy &ArgFlags,
2089 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2091 CCValAssign::LocInfo &LocInfo,
2092 ISD::ArgFlagsTy &ArgFlags,
2094 static const MCPhysReg ArgRegs[] = {
2095 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2096 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2098 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2100 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2102 // Skip one register if the first unallocated register has an even register
2103 // number and there are still argument registers available which have not been
2104 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2105 // need to skip a register if RegNum is odd.
2106 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2107 State.AllocateReg(ArgRegs[RegNum]);
2110 // Always return false here, as this function only makes sure that the first
2111 // unallocated register has an odd register number and does not actually
2112 // allocate a register for the current argument.
2116 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2118 CCValAssign::LocInfo &LocInfo,
2119 ISD::ArgFlagsTy &ArgFlags,
2121 static const MCPhysReg ArgRegs[] = {
2122 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2126 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2128 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2130 // If there is only one Floating-point register left we need to put both f64
2131 // values of a split ppc_fp128 value on the stack.
2132 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2133 State.AllocateReg(ArgRegs[RegNum]);
2136 // Always return false here, as this function only makes sure that the two f64
2137 // values a ppc_fp128 value is split into are both passed in registers or both
2138 // passed on the stack and does not actually allocate a register for the
2139 // current argument.
2143 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2145 static const MCPhysReg *GetFPR() {
2146 static const MCPhysReg FPR[] = {
2147 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2148 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2154 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2156 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2157 unsigned PtrByteSize) {
2158 unsigned ArgSize = ArgVT.getStoreSize();
2159 if (Flags.isByVal())
2160 ArgSize = Flags.getByValSize();
2161 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2166 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2168 static unsigned CalculateStackSlotAlignment(EVT ArgVT, ISD::ArgFlagsTy Flags,
2169 unsigned PtrByteSize) {
2170 unsigned Align = PtrByteSize;
2172 // Altivec parameters are padded to a 16 byte boundary.
2173 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2174 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2175 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2178 // ByVal parameters are aligned as requested.
2179 if (Flags.isByVal()) {
2180 unsigned BVAlign = Flags.getByValAlign();
2181 if (BVAlign > PtrByteSize) {
2182 if (BVAlign % PtrByteSize != 0)
2184 "ByVal alignment is not a multiple of the pointer size");
2193 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2194 /// ensure minimum alignment required for target.
2195 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2196 unsigned NumBytes) {
2197 unsigned TargetAlign = Target.getFrameLowering()->getStackAlignment();
2198 unsigned AlignMask = TargetAlign - 1;
2199 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2204 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2205 CallingConv::ID CallConv, bool isVarArg,
2206 const SmallVectorImpl<ISD::InputArg>
2208 SDLoc dl, SelectionDAG &DAG,
2209 SmallVectorImpl<SDValue> &InVals)
2211 if (Subtarget.isSVR4ABI()) {
2212 if (Subtarget.isPPC64())
2213 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2216 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2219 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2225 PPCTargetLowering::LowerFormalArguments_32SVR4(
2227 CallingConv::ID CallConv, bool isVarArg,
2228 const SmallVectorImpl<ISD::InputArg>
2230 SDLoc dl, SelectionDAG &DAG,
2231 SmallVectorImpl<SDValue> &InVals) const {
2233 // 32-bit SVR4 ABI Stack Frame Layout:
2234 // +-----------------------------------+
2235 // +--> | Back chain |
2236 // | +-----------------------------------+
2237 // | | Floating-point register save area |
2238 // | +-----------------------------------+
2239 // | | General register save area |
2240 // | +-----------------------------------+
2241 // | | CR save word |
2242 // | +-----------------------------------+
2243 // | | VRSAVE save word |
2244 // | +-----------------------------------+
2245 // | | Alignment padding |
2246 // | +-----------------------------------+
2247 // | | Vector register save area |
2248 // | +-----------------------------------+
2249 // | | Local variable space |
2250 // | +-----------------------------------+
2251 // | | Parameter list area |
2252 // | +-----------------------------------+
2253 // | | LR save word |
2254 // | +-----------------------------------+
2255 // SP--> +--- | Back chain |
2256 // +-----------------------------------+
2259 // System V Application Binary Interface PowerPC Processor Supplement
2260 // AltiVec Technology Programming Interface Manual
2262 MachineFunction &MF = DAG.getMachineFunction();
2263 MachineFrameInfo *MFI = MF.getFrameInfo();
2264 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2266 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2267 // Potential tail calls could cause overwriting of argument stack slots.
2268 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2269 (CallConv == CallingConv::Fast));
2270 unsigned PtrByteSize = 4;
2272 // Assign locations to all of the incoming arguments.
2273 SmallVector<CCValAssign, 16> ArgLocs;
2274 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2275 getTargetMachine(), ArgLocs, *DAG.getContext());
2277 // Reserve space for the linkage area on the stack.
2278 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false);
2279 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2281 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2283 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2284 CCValAssign &VA = ArgLocs[i];
2286 // Arguments stored in registers.
2287 if (VA.isRegLoc()) {
2288 const TargetRegisterClass *RC;
2289 EVT ValVT = VA.getValVT();
2291 switch (ValVT.getSimpleVT().SimpleTy) {
2293 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2296 RC = &PPC::GPRCRegClass;
2299 RC = &PPC::F4RCRegClass;
2302 if (Subtarget.hasVSX())
2303 RC = &PPC::VSFRCRegClass;
2305 RC = &PPC::F8RCRegClass;
2311 RC = &PPC::VRRCRegClass;
2315 RC = &PPC::VSHRCRegClass;
2319 // Transform the arguments stored in physical registers into virtual ones.
2320 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2321 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2322 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2324 if (ValVT == MVT::i1)
2325 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2327 InVals.push_back(ArgValue);
2329 // Argument stored in memory.
2330 assert(VA.isMemLoc());
2332 unsigned ArgSize = VA.getLocVT().getStoreSize();
2333 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2336 // Create load nodes to retrieve arguments from the stack.
2337 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2338 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2339 MachinePointerInfo(),
2340 false, false, false, 0));
2344 // Assign locations to all of the incoming aggregate by value arguments.
2345 // Aggregates passed by value are stored in the local variable space of the
2346 // caller's stack frame, right above the parameter list area.
2347 SmallVector<CCValAssign, 16> ByValArgLocs;
2348 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2349 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2351 // Reserve stack space for the allocations in CCInfo.
2352 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2354 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2356 // Area that is at least reserved in the caller of this function.
2357 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2358 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2360 // Set the size that is at least reserved in caller of this function. Tail
2361 // call optimized function's reserved stack space needs to be aligned so that
2362 // taking the difference between two stack areas will result in an aligned
2364 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2365 FuncInfo->setMinReservedArea(MinReservedArea);
2367 SmallVector<SDValue, 8> MemOps;
2369 // If the function takes variable number of arguments, make a frame index for
2370 // the start of the first vararg value... for expansion of llvm.va_start.
2372 static const MCPhysReg GPArgRegs[] = {
2373 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2374 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2376 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2378 static const MCPhysReg FPArgRegs[] = {
2379 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2382 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2384 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2386 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2389 // Make room for NumGPArgRegs and NumFPArgRegs.
2390 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2391 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2393 FuncInfo->setVarArgsStackOffset(
2394 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2395 CCInfo.getNextStackOffset(), true));
2397 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2398 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2400 // The fixed integer arguments of a variadic function are stored to the
2401 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2402 // the result of va_next.
2403 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2404 // Get an existing live-in vreg, or add a new one.
2405 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2407 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2409 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2410 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2411 MachinePointerInfo(), false, false, 0);
2412 MemOps.push_back(Store);
2413 // Increment the address by four for the next argument to store
2414 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2415 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2418 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2420 // The double arguments are stored to the VarArgsFrameIndex
2422 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2423 // Get an existing live-in vreg, or add a new one.
2424 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2426 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2428 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2429 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2430 MachinePointerInfo(), false, false, 0);
2431 MemOps.push_back(Store);
2432 // Increment the address by eight for the next argument to store
2433 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2435 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2439 if (!MemOps.empty())
2440 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2445 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2446 // value to MVT::i64 and then truncate to the correct register size.
2448 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2449 SelectionDAG &DAG, SDValue ArgVal,
2452 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2453 DAG.getValueType(ObjectVT));
2454 else if (Flags.isZExt())
2455 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2456 DAG.getValueType(ObjectVT));
2458 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2462 PPCTargetLowering::LowerFormalArguments_64SVR4(
2464 CallingConv::ID CallConv, bool isVarArg,
2465 const SmallVectorImpl<ISD::InputArg>
2467 SDLoc dl, SelectionDAG &DAG,
2468 SmallVectorImpl<SDValue> &InVals) const {
2469 // TODO: add description of PPC stack frame format, or at least some docs.
2471 bool isLittleEndian = Subtarget.isLittleEndian();
2472 MachineFunction &MF = DAG.getMachineFunction();
2473 MachineFrameInfo *MFI = MF.getFrameInfo();
2474 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2476 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2477 // Potential tail calls could cause overwriting of argument stack slots.
2478 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2479 (CallConv == CallingConv::Fast));
2480 unsigned PtrByteSize = 8;
2482 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false);
2483 unsigned ArgOffset = LinkageSize;
2485 static const MCPhysReg GPR[] = {
2486 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2487 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2490 static const MCPhysReg *FPR = GetFPR();
2492 static const MCPhysReg VR[] = {
2493 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2494 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2496 static const MCPhysReg VSRH[] = {
2497 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2498 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2501 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2502 const unsigned Num_FPR_Regs = 13;
2503 const unsigned Num_VR_Regs = array_lengthof(VR);
2505 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
2507 // Add DAG nodes to load the arguments or copy them out of registers. On
2508 // entry to a function on PPC, the arguments start after the linkage area,
2509 // although the first ones are often in registers.
2511 SmallVector<SDValue, 8> MemOps;
2512 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2513 unsigned CurArgIdx = 0;
2514 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2516 bool needsLoad = false;
2517 EVT ObjectVT = Ins[ArgNo].VT;
2518 unsigned ObjSize = ObjectVT.getStoreSize();
2519 unsigned ArgSize = ObjSize;
2520 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2521 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2522 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2524 /* Respect alignment of argument on the stack. */
2526 CalculateStackSlotAlignment(ObjectVT, Flags, PtrByteSize);
2527 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2528 unsigned CurArgOffset = ArgOffset;
2530 /* Compute GPR index associated with argument offset. */
2531 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2532 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2534 // FIXME the codegen can be much improved in some cases.
2535 // We do not have to keep everything in memory.
2536 if (Flags.isByVal()) {
2537 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2538 ObjSize = Flags.getByValSize();
2539 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2540 // Empty aggregate parameters do not take up registers. Examples:
2544 // etc. However, we have to provide a place-holder in InVals, so
2545 // pretend we have an 8-byte item at the current address for that
2548 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2549 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2550 InVals.push_back(FIN);
2554 // All aggregates smaller than 8 bytes must be passed right-justified.
2555 if (ObjSize < PtrByteSize && !isLittleEndian)
2556 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2557 // The value of the object is its address.
2558 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2559 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2560 InVals.push_back(FIN);
2563 if (GPR_idx != Num_GPR_Regs) {
2564 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2565 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2568 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2569 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2570 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2571 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2572 MachinePointerInfo(FuncArg),
2573 ObjType, false, false, 0);
2575 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2576 // store the whole register as-is to the parameter save area
2577 // slot. The address of the parameter was already calculated
2578 // above (InVals.push_back(FIN)) to be the right-justified
2579 // offset within the slot. For this store, we need a new
2580 // frame index that points at the beginning of the slot.
2581 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2582 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2583 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2584 MachinePointerInfo(FuncArg),
2588 MemOps.push_back(Store);
2590 // Whether we copied from a register or not, advance the offset
2591 // into the parameter save area by a full doubleword.
2592 ArgOffset += PtrByteSize;
2596 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2597 // Store whatever pieces of the object are in registers
2598 // to memory. ArgOffset will be the address of the beginning
2600 if (GPR_idx != Num_GPR_Regs) {
2602 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2603 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2604 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2605 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2606 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2607 MachinePointerInfo(FuncArg, j),
2609 MemOps.push_back(Store);
2611 ArgOffset += PtrByteSize;
2613 ArgOffset += ArgSize - j;
2620 switch (ObjectVT.getSimpleVT().SimpleTy) {
2621 default: llvm_unreachable("Unhandled argument type!");
2625 if (GPR_idx != Num_GPR_Regs) {
2626 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2627 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2629 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2630 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2631 // value to MVT::i64 and then truncate to the correct register size.
2632 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2635 ArgSize = PtrByteSize;
2642 if (FPR_idx != Num_FPR_Regs) {
2645 if (ObjectVT == MVT::f32)
2646 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2648 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2649 &PPC::VSFRCRegClass :
2650 &PPC::F8RCRegClass);
2652 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2656 ArgSize = PtrByteSize;
2667 if (VR_idx != Num_VR_Regs) {
2668 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2669 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2670 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2671 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2680 // We need to load the argument to a virtual register if we determined
2681 // above that we ran out of physical registers of the appropriate type.
2683 if (ObjSize < ArgSize && !isLittleEndian)
2684 CurArgOffset += ArgSize - ObjSize;
2685 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2686 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2687 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2688 false, false, false, 0);
2691 InVals.push_back(ArgVal);
2694 // Area that is at least reserved in the caller of this function.
2695 unsigned MinReservedArea;
2696 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2698 // Set the size that is at least reserved in caller of this function. Tail
2699 // call optimized functions' reserved stack space needs to be aligned so that
2700 // taking the difference between two stack areas will result in an aligned
2702 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2703 FuncInfo->setMinReservedArea(MinReservedArea);
2705 // If the function takes variable number of arguments, make a frame index for
2706 // the start of the first vararg value... for expansion of llvm.va_start.
2708 int Depth = ArgOffset;
2710 FuncInfo->setVarArgsFrameIndex(
2711 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2712 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2714 // If this function is vararg, store any remaining integer argument regs
2715 // to their spots on the stack so that they may be loaded by deferencing the
2716 // result of va_next.
2717 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2718 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2719 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2720 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2721 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2722 MachinePointerInfo(), false, false, 0);
2723 MemOps.push_back(Store);
2724 // Increment the address by four for the next argument to store
2725 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2726 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2730 if (!MemOps.empty())
2731 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2737 PPCTargetLowering::LowerFormalArguments_Darwin(
2739 CallingConv::ID CallConv, bool isVarArg,
2740 const SmallVectorImpl<ISD::InputArg>
2742 SDLoc dl, SelectionDAG &DAG,
2743 SmallVectorImpl<SDValue> &InVals) const {
2744 // TODO: add description of PPC stack frame format, or at least some docs.
2746 MachineFunction &MF = DAG.getMachineFunction();
2747 MachineFrameInfo *MFI = MF.getFrameInfo();
2748 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2750 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2751 bool isPPC64 = PtrVT == MVT::i64;
2752 // Potential tail calls could cause overwriting of argument stack slots.
2753 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2754 (CallConv == CallingConv::Fast));
2755 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2757 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true);
2758 unsigned ArgOffset = LinkageSize;
2759 // Area that is at least reserved in caller of this function.
2760 unsigned MinReservedArea = ArgOffset;
2762 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2763 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2764 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2766 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2767 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2768 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2771 static const MCPhysReg *FPR = GetFPR();
2773 static const MCPhysReg VR[] = {
2774 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2775 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2778 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2779 const unsigned Num_FPR_Regs = 13;
2780 const unsigned Num_VR_Regs = array_lengthof( VR);
2782 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2784 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2786 // In 32-bit non-varargs functions, the stack space for vectors is after the
2787 // stack space for non-vectors. We do not use this space unless we have
2788 // too many vectors to fit in registers, something that only occurs in
2789 // constructed examples:), but we have to walk the arglist to figure
2790 // that out...for the pathological case, compute VecArgOffset as the
2791 // start of the vector parameter area. Computing VecArgOffset is the
2792 // entire point of the following loop.
2793 unsigned VecArgOffset = ArgOffset;
2794 if (!isVarArg && !isPPC64) {
2795 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2797 EVT ObjectVT = Ins[ArgNo].VT;
2798 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2800 if (Flags.isByVal()) {
2801 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2802 unsigned ObjSize = Flags.getByValSize();
2804 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2805 VecArgOffset += ArgSize;
2809 switch(ObjectVT.getSimpleVT().SimpleTy) {
2810 default: llvm_unreachable("Unhandled argument type!");
2816 case MVT::i64: // PPC64
2818 // FIXME: We are guaranteed to be !isPPC64 at this point.
2819 // Does MVT::i64 apply?
2826 // Nothing to do, we're only looking at Nonvector args here.
2831 // We've found where the vector parameter area in memory is. Skip the
2832 // first 12 parameters; these don't use that memory.
2833 VecArgOffset = ((VecArgOffset+15)/16)*16;
2834 VecArgOffset += 12*16;
2836 // Add DAG nodes to load the arguments or copy them out of registers. On
2837 // entry to a function on PPC, the arguments start after the linkage area,
2838 // although the first ones are often in registers.
2840 SmallVector<SDValue, 8> MemOps;
2841 unsigned nAltivecParamsAtEnd = 0;
2842 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2843 unsigned CurArgIdx = 0;
2844 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2846 bool needsLoad = false;
2847 EVT ObjectVT = Ins[ArgNo].VT;
2848 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2849 unsigned ArgSize = ObjSize;
2850 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2851 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2852 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2854 unsigned CurArgOffset = ArgOffset;
2856 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2857 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2858 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2859 if (isVarArg || isPPC64) {
2860 MinReservedArea = ((MinReservedArea+15)/16)*16;
2861 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2864 } else nAltivecParamsAtEnd++;
2866 // Calculate min reserved area.
2867 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2871 // FIXME the codegen can be much improved in some cases.
2872 // We do not have to keep everything in memory.
2873 if (Flags.isByVal()) {
2874 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2875 ObjSize = Flags.getByValSize();
2876 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2877 // Objects of size 1 and 2 are right justified, everything else is
2878 // left justified. This means the memory address is adjusted forwards.
2879 if (ObjSize==1 || ObjSize==2) {
2880 CurArgOffset = CurArgOffset + (4 - ObjSize);
2882 // The value of the object is its address.
2883 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2884 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2885 InVals.push_back(FIN);
2886 if (ObjSize==1 || ObjSize==2) {
2887 if (GPR_idx != Num_GPR_Regs) {
2890 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2892 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2893 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2894 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2895 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2896 MachinePointerInfo(FuncArg),
2897 ObjType, false, false, 0);
2898 MemOps.push_back(Store);
2902 ArgOffset += PtrByteSize;
2906 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2907 // Store whatever pieces of the object are in registers
2908 // to memory. ArgOffset will be the address of the beginning
2910 if (GPR_idx != Num_GPR_Regs) {
2913 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2915 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2916 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2917 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2918 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2919 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2920 MachinePointerInfo(FuncArg, j),
2922 MemOps.push_back(Store);
2924 ArgOffset += PtrByteSize;
2926 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2933 switch (ObjectVT.getSimpleVT().SimpleTy) {
2934 default: llvm_unreachable("Unhandled argument type!");
2938 if (GPR_idx != Num_GPR_Regs) {
2939 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2940 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2942 if (ObjectVT == MVT::i1)
2943 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
2948 ArgSize = PtrByteSize;
2950 // All int arguments reserve stack space in the Darwin ABI.
2951 ArgOffset += PtrByteSize;
2955 case MVT::i64: // PPC64
2956 if (GPR_idx != Num_GPR_Regs) {
2957 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2958 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2960 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2961 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2962 // value to MVT::i64 and then truncate to the correct register size.
2963 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2968 ArgSize = PtrByteSize;
2970 // All int arguments reserve stack space in the Darwin ABI.
2976 // Every 4 bytes of argument space consumes one of the GPRs available for
2977 // argument passing.
2978 if (GPR_idx != Num_GPR_Regs) {
2980 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2983 if (FPR_idx != Num_FPR_Regs) {
2986 if (ObjectVT == MVT::f32)
2987 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2989 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2991 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2997 // All FP arguments reserve stack space in the Darwin ABI.
2998 ArgOffset += isPPC64 ? 8 : ObjSize;
3004 // Note that vector arguments in registers don't reserve stack space,
3005 // except in varargs functions.
3006 if (VR_idx != Num_VR_Regs) {
3007 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3008 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3010 while ((ArgOffset % 16) != 0) {
3011 ArgOffset += PtrByteSize;
3012 if (GPR_idx != Num_GPR_Regs)
3016 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3020 if (!isVarArg && !isPPC64) {
3021 // Vectors go after all the nonvectors.
3022 CurArgOffset = VecArgOffset;
3025 // Vectors are aligned.
3026 ArgOffset = ((ArgOffset+15)/16)*16;
3027 CurArgOffset = ArgOffset;
3035 // We need to load the argument to a virtual register if we determined above
3036 // that we ran out of physical registers of the appropriate type.
3038 int FI = MFI->CreateFixedObject(ObjSize,
3039 CurArgOffset + (ArgSize - ObjSize),
3041 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3042 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3043 false, false, false, 0);
3046 InVals.push_back(ArgVal);
3049 // Allow for Altivec parameters at the end, if needed.
3050 if (nAltivecParamsAtEnd) {
3051 MinReservedArea = ((MinReservedArea+15)/16)*16;
3052 MinReservedArea += 16*nAltivecParamsAtEnd;
3055 // Area that is at least reserved in the caller of this function.
3056 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3058 // Set the size that is at least reserved in caller of this function. Tail
3059 // call optimized functions' reserved stack space needs to be aligned so that
3060 // taking the difference between two stack areas will result in an aligned
3062 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3063 FuncInfo->setMinReservedArea(MinReservedArea);
3065 // If the function takes variable number of arguments, make a frame index for
3066 // the start of the first vararg value... for expansion of llvm.va_start.
3068 int Depth = ArgOffset;
3070 FuncInfo->setVarArgsFrameIndex(
3071 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3073 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3075 // If this function is vararg, store any remaining integer argument regs
3076 // to their spots on the stack so that they may be loaded by deferencing the
3077 // result of va_next.
3078 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3082 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3084 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3086 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3087 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3088 MachinePointerInfo(), false, false, 0);
3089 MemOps.push_back(Store);
3090 // Increment the address by four for the next argument to store
3091 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3092 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3096 if (!MemOps.empty())
3097 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3102 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3103 /// adjusted to accommodate the arguments for the tailcall.
3104 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3105 unsigned ParamSize) {
3107 if (!isTailCall) return 0;
3109 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3110 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3111 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3112 // Remember only if the new adjustement is bigger.
3113 if (SPDiff < FI->getTailCallSPDelta())
3114 FI->setTailCallSPDelta(SPDiff);
3119 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3120 /// for tail call optimization. Targets which want to do tail call
3121 /// optimization should implement this function.
3123 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3124 CallingConv::ID CalleeCC,
3126 const SmallVectorImpl<ISD::InputArg> &Ins,
3127 SelectionDAG& DAG) const {
3128 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3131 // Variable argument functions are not supported.
3135 MachineFunction &MF = DAG.getMachineFunction();
3136 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3137 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3138 // Functions containing by val parameters are not supported.
3139 for (unsigned i = 0; i != Ins.size(); i++) {
3140 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3141 if (Flags.isByVal()) return false;
3144 // Non-PIC/GOT tail calls are supported.
3145 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3148 // At the moment we can only do local tail calls (in same module, hidden
3149 // or protected) if we are generating PIC.
3150 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3151 return G->getGlobal()->hasHiddenVisibility()
3152 || G->getGlobal()->hasProtectedVisibility();
3158 /// isCallCompatibleAddress - Return the immediate to use if the specified
3159 /// 32-bit value is representable in the immediate field of a BxA instruction.
3160 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3161 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3162 if (!C) return nullptr;
3164 int Addr = C->getZExtValue();
3165 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3166 SignExtend32<26>(Addr) != Addr)
3167 return nullptr; // Top 6 bits have to be sext of immediate.
3169 return DAG.getConstant((int)C->getZExtValue() >> 2,
3170 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3175 struct TailCallArgumentInfo {
3180 TailCallArgumentInfo() : FrameIdx(0) {}
3185 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3187 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3189 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3190 SmallVectorImpl<SDValue> &MemOpChains,
3192 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3193 SDValue Arg = TailCallArgs[i].Arg;
3194 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3195 int FI = TailCallArgs[i].FrameIdx;
3196 // Store relative to framepointer.
3197 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3198 MachinePointerInfo::getFixedStack(FI),
3203 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3204 /// the appropriate stack slot for the tail call optimized function call.
3205 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3206 MachineFunction &MF,
3215 // Calculate the new stack slot for the return address.
3216 int SlotSize = isPPC64 ? 8 : 4;
3217 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3219 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3220 NewRetAddrLoc, true);
3221 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3222 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3223 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3224 MachinePointerInfo::getFixedStack(NewRetAddr),
3227 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3228 // slot as the FP is never overwritten.
3231 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3232 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3234 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3235 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3236 MachinePointerInfo::getFixedStack(NewFPIdx),
3243 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3244 /// the position of the argument.
3246 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3247 SDValue Arg, int SPDiff, unsigned ArgOffset,
3248 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3249 int Offset = ArgOffset + SPDiff;
3250 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3251 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3252 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3253 SDValue FIN = DAG.getFrameIndex(FI, VT);
3254 TailCallArgumentInfo Info;
3256 Info.FrameIdxOp = FIN;
3258 TailCallArguments.push_back(Info);
3261 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3262 /// stack slot. Returns the chain as result and the loaded frame pointers in
3263 /// LROpOut/FPOpout. Used when tail calling.
3264 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3272 // Load the LR and FP stack slot for later adjusting.
3273 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3274 LROpOut = getReturnAddrFrameIndex(DAG);
3275 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3276 false, false, false, 0);
3277 Chain = SDValue(LROpOut.getNode(), 1);
3279 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3280 // slot as the FP is never overwritten.
3282 FPOpOut = getFramePointerFrameIndex(DAG);
3283 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3284 false, false, false, 0);
3285 Chain = SDValue(FPOpOut.getNode(), 1);
3291 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3292 /// by "Src" to address "Dst" of size "Size". Alignment information is
3293 /// specified by the specific parameter attribute. The copy will be passed as
3294 /// a byval function parameter.
3295 /// Sometimes what we are copying is the end of a larger object, the part that
3296 /// does not fit in registers.
3298 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3299 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3301 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3302 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3303 false, false, MachinePointerInfo(),
3304 MachinePointerInfo());
3307 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3310 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3311 SDValue Arg, SDValue PtrOff, int SPDiff,
3312 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3313 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3314 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3316 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3321 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3323 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3324 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3325 DAG.getConstant(ArgOffset, PtrVT));
3327 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3328 MachinePointerInfo(), false, false, 0));
3329 // Calculate and remember argument location.
3330 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3335 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3336 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3337 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3338 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3339 MachineFunction &MF = DAG.getMachineFunction();
3341 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3342 // might overwrite each other in case of tail call optimization.
3343 SmallVector<SDValue, 8> MemOpChains2;
3344 // Do not flag preceding copytoreg stuff together with the following stuff.
3346 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3348 if (!MemOpChains2.empty())
3349 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3351 // Store the return address to the appropriate stack slot.
3352 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3353 isPPC64, isDarwinABI, dl);
3355 // Emit callseq_end just before tailcall node.
3356 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3357 DAG.getIntPtrConstant(0, true), InFlag, dl);
3358 InFlag = Chain.getValue(1);
3362 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3363 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3364 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3365 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3366 const PPCSubtarget &Subtarget) {
3368 bool isPPC64 = Subtarget.isPPC64();
3369 bool isSVR4ABI = Subtarget.isSVR4ABI();
3371 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3372 NodeTys.push_back(MVT::Other); // Returns a chain
3373 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3375 unsigned CallOpc = PPCISD::CALL;
3377 bool needIndirectCall = true;
3378 if (!isSVR4ABI || !isPPC64)
3379 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3380 // If this is an absolute destination address, use the munged value.
3381 Callee = SDValue(Dest, 0);
3382 needIndirectCall = false;
3385 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3386 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3387 // Use indirect calls for ALL functions calls in JIT mode, since the
3388 // far-call stubs may be outside relocation limits for a BL instruction.
3389 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3390 unsigned OpFlags = 0;
3391 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3392 (Subtarget.getTargetTriple().isMacOSX() &&
3393 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3394 (G->getGlobal()->isDeclaration() ||
3395 G->getGlobal()->isWeakForLinker())) ||
3396 (Subtarget.isTargetELF() && !isPPC64 &&
3397 !G->getGlobal()->hasLocalLinkage() &&
3398 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3399 // PC-relative references to external symbols should go through $stub,
3400 // unless we're building with the leopard linker or later, which
3401 // automatically synthesizes these stubs.
3402 OpFlags = PPCII::MO_PLT_OR_STUB;
3405 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3406 // every direct call is) turn it into a TargetGlobalAddress /
3407 // TargetExternalSymbol node so that legalize doesn't hack it.
3408 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3409 Callee.getValueType(),
3411 needIndirectCall = false;
3415 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3416 unsigned char OpFlags = 0;
3418 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3419 (Subtarget.getTargetTriple().isMacOSX() &&
3420 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3421 (Subtarget.isTargetELF() && !isPPC64 &&
3422 DAG.getTarget().getRelocationModel() == Reloc::PIC_) ) {
3423 // PC-relative references to external symbols should go through $stub,
3424 // unless we're building with the leopard linker or later, which
3425 // automatically synthesizes these stubs.
3426 OpFlags = PPCII::MO_PLT_OR_STUB;
3429 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3431 needIndirectCall = false;
3434 if (needIndirectCall) {
3435 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3436 // to do the call, we can't use PPCISD::CALL.
3437 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3439 if (isSVR4ABI && isPPC64) {
3440 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3441 // entry point, but to the function descriptor (the function entry point
3442 // address is part of the function descriptor though).
3443 // The function descriptor is a three doubleword structure with the
3444 // following fields: function entry point, TOC base address and
3445 // environment pointer.
3446 // Thus for a call through a function pointer, the following actions need
3448 // 1. Save the TOC of the caller in the TOC save area of its stack
3449 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3450 // 2. Load the address of the function entry point from the function
3452 // 3. Load the TOC of the callee from the function descriptor into r2.
3453 // 4. Load the environment pointer from the function descriptor into
3455 // 5. Branch to the function entry point address.
3456 // 6. On return of the callee, the TOC of the caller needs to be
3457 // restored (this is done in FinishCall()).
3459 // All those operations are flagged together to ensure that no other
3460 // operations can be scheduled in between. E.g. without flagging the
3461 // operations together, a TOC access in the caller could be scheduled
3462 // between the load of the callee TOC and the branch to the callee, which
3463 // results in the TOC access going through the TOC of the callee instead
3464 // of going through the TOC of the caller, which leads to incorrect code.
3466 // Load the address of the function entry point from the function
3468 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3469 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3470 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3471 Chain = LoadFuncPtr.getValue(1);
3472 InFlag = LoadFuncPtr.getValue(2);
3474 // Load environment pointer into r11.
3475 // Offset of the environment pointer within the function descriptor.
3476 SDValue PtrOff = DAG.getIntPtrConstant(16);
3478 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3479 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3481 Chain = LoadEnvPtr.getValue(1);
3482 InFlag = LoadEnvPtr.getValue(2);
3484 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3486 Chain = EnvVal.getValue(0);
3487 InFlag = EnvVal.getValue(1);
3489 // Load TOC of the callee into r2. We are using a target-specific load
3490 // with r2 hard coded, because the result of a target-independent load
3491 // would never go directly into r2, since r2 is a reserved register (which
3492 // prevents the register allocator from allocating it), resulting in an
3493 // additional register being allocated and an unnecessary move instruction
3495 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3496 SDValue TOCOff = DAG.getIntPtrConstant(8);
3497 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3498 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3500 Chain = LoadTOCPtr.getValue(0);
3501 InFlag = LoadTOCPtr.getValue(1);
3503 MTCTROps[0] = Chain;
3504 MTCTROps[1] = LoadFuncPtr;
3505 MTCTROps[2] = InFlag;
3508 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3509 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3510 InFlag = Chain.getValue(1);
3513 NodeTys.push_back(MVT::Other);
3514 NodeTys.push_back(MVT::Glue);
3515 Ops.push_back(Chain);
3516 CallOpc = PPCISD::BCTRL;
3517 Callee.setNode(nullptr);
3518 // Add use of X11 (holding environment pointer)
3519 if (isSVR4ABI && isPPC64)
3520 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3521 // Add CTR register as callee so a bctr can be emitted later.
3523 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3526 // If this is a direct call, pass the chain and the callee.
3527 if (Callee.getNode()) {
3528 Ops.push_back(Chain);
3529 Ops.push_back(Callee);
3531 // If this is a tail call add stack pointer delta.
3533 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3535 // Add argument registers to the end of the list so that they are known live
3537 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3538 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3539 RegsToPass[i].second.getValueType()));
3545 bool isLocalCall(const SDValue &Callee)
3547 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3548 return !G->getGlobal()->isDeclaration() &&
3549 !G->getGlobal()->isWeakForLinker();
3554 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3555 CallingConv::ID CallConv, bool isVarArg,
3556 const SmallVectorImpl<ISD::InputArg> &Ins,
3557 SDLoc dl, SelectionDAG &DAG,
3558 SmallVectorImpl<SDValue> &InVals) const {
3560 SmallVector<CCValAssign, 16> RVLocs;
3561 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3562 getTargetMachine(), RVLocs, *DAG.getContext());
3563 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3565 // Copy all of the result registers out of their specified physreg.
3566 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3567 CCValAssign &VA = RVLocs[i];
3568 assert(VA.isRegLoc() && "Can only return in registers!");
3570 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3571 VA.getLocReg(), VA.getLocVT(), InFlag);
3572 Chain = Val.getValue(1);
3573 InFlag = Val.getValue(2);
3575 switch (VA.getLocInfo()) {
3576 default: llvm_unreachable("Unknown loc info!");
3577 case CCValAssign::Full: break;
3578 case CCValAssign::AExt:
3579 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3581 case CCValAssign::ZExt:
3582 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3583 DAG.getValueType(VA.getValVT()));
3584 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3586 case CCValAssign::SExt:
3587 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3588 DAG.getValueType(VA.getValVT()));
3589 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3593 InVals.push_back(Val);
3600 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3601 bool isTailCall, bool isVarArg,
3603 SmallVector<std::pair<unsigned, SDValue>, 8>
3605 SDValue InFlag, SDValue Chain,
3607 int SPDiff, unsigned NumBytes,
3608 const SmallVectorImpl<ISD::InputArg> &Ins,
3609 SmallVectorImpl<SDValue> &InVals) const {
3610 std::vector<EVT> NodeTys;
3611 SmallVector<SDValue, 8> Ops;
3612 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3613 isTailCall, RegsToPass, Ops, NodeTys,
3616 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3617 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3618 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3620 // When performing tail call optimization the callee pops its arguments off
3621 // the stack. Account for this here so these bytes can be pushed back on in
3622 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3623 int BytesCalleePops =
3624 (CallConv == CallingConv::Fast &&
3625 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3627 // Add a register mask operand representing the call-preserved registers.
3628 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3629 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3630 assert(Mask && "Missing call preserved mask for calling convention");
3631 Ops.push_back(DAG.getRegisterMask(Mask));
3633 if (InFlag.getNode())
3634 Ops.push_back(InFlag);
3638 assert(((Callee.getOpcode() == ISD::Register &&
3639 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3640 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3641 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3642 isa<ConstantSDNode>(Callee)) &&
3643 "Expecting an global address, external symbol, absolute value or register");
3645 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3648 // Add a NOP immediately after the branch instruction when using the 64-bit
3649 // SVR4 ABI. At link time, if caller and callee are in a different module and
3650 // thus have a different TOC, the call will be replaced with a call to a stub
3651 // function which saves the current TOC, loads the TOC of the callee and
3652 // branches to the callee. The NOP will be replaced with a load instruction
3653 // which restores the TOC of the caller from the TOC save slot of the current
3654 // stack frame. If caller and callee belong to the same module (and have the
3655 // same TOC), the NOP will remain unchanged.
3657 bool needsTOCRestore = false;
3658 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3659 if (CallOpc == PPCISD::BCTRL) {
3660 // This is a call through a function pointer.
3661 // Restore the caller TOC from the save area into R2.
3662 // See PrepareCall() for more information about calls through function
3663 // pointers in the 64-bit SVR4 ABI.
3664 // We are using a target-specific load with r2 hard coded, because the
3665 // result of a target-independent load would never go directly into r2,
3666 // since r2 is a reserved register (which prevents the register allocator
3667 // from allocating it), resulting in an additional register being
3668 // allocated and an unnecessary move instruction being generated.
3669 needsTOCRestore = true;
3670 } else if ((CallOpc == PPCISD::CALL) &&
3671 (!isLocalCall(Callee) ||
3672 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3673 // Otherwise insert NOP for non-local calls.
3674 CallOpc = PPCISD::CALL_NOP;
3678 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3679 InFlag = Chain.getValue(1);
3681 if (needsTOCRestore) {
3682 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3683 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3684 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3685 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset();
3686 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3687 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3688 Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag);
3689 InFlag = Chain.getValue(1);
3692 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3693 DAG.getIntPtrConstant(BytesCalleePops, true),
3696 InFlag = Chain.getValue(1);
3698 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3699 Ins, dl, DAG, InVals);
3703 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3704 SmallVectorImpl<SDValue> &InVals) const {
3705 SelectionDAG &DAG = CLI.DAG;
3707 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3708 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3709 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3710 SDValue Chain = CLI.Chain;
3711 SDValue Callee = CLI.Callee;
3712 bool &isTailCall = CLI.IsTailCall;
3713 CallingConv::ID CallConv = CLI.CallConv;
3714 bool isVarArg = CLI.IsVarArg;
3717 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3720 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3721 report_fatal_error("failed to perform tail call elimination on a call "
3722 "site marked musttail");
3724 if (Subtarget.isSVR4ABI()) {
3725 if (Subtarget.isPPC64())
3726 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3727 isTailCall, Outs, OutVals, Ins,
3730 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3731 isTailCall, Outs, OutVals, Ins,
3735 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3736 isTailCall, Outs, OutVals, Ins,
3741 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3742 CallingConv::ID CallConv, bool isVarArg,
3744 const SmallVectorImpl<ISD::OutputArg> &Outs,
3745 const SmallVectorImpl<SDValue> &OutVals,
3746 const SmallVectorImpl<ISD::InputArg> &Ins,
3747 SDLoc dl, SelectionDAG &DAG,
3748 SmallVectorImpl<SDValue> &InVals) const {
3749 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3750 // of the 32-bit SVR4 ABI stack frame layout.
3752 assert((CallConv == CallingConv::C ||
3753 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3755 unsigned PtrByteSize = 4;
3757 MachineFunction &MF = DAG.getMachineFunction();
3759 // Mark this function as potentially containing a function that contains a
3760 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3761 // and restoring the callers stack pointer in this functions epilog. This is
3762 // done because by tail calling the called function might overwrite the value
3763 // in this function's (MF) stack pointer stack slot 0(SP).
3764 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3765 CallConv == CallingConv::Fast)
3766 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3768 // Count how many bytes are to be pushed on the stack, including the linkage
3769 // area, parameter list area and the part of the local variable space which
3770 // contains copies of aggregates which are passed by value.
3772 // Assign locations to all of the outgoing arguments.
3773 SmallVector<CCValAssign, 16> ArgLocs;
3774 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3775 getTargetMachine(), ArgLocs, *DAG.getContext());
3777 // Reserve space for the linkage area on the stack.
3778 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3781 // Handle fixed and variable vector arguments differently.
3782 // Fixed vector arguments go into registers as long as registers are
3783 // available. Variable vector arguments always go into memory.
3784 unsigned NumArgs = Outs.size();
3786 for (unsigned i = 0; i != NumArgs; ++i) {
3787 MVT ArgVT = Outs[i].VT;
3788 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3791 if (Outs[i].IsFixed) {
3792 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3795 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3801 errs() << "Call operand #" << i << " has unhandled type "
3802 << EVT(ArgVT).getEVTString() << "\n";
3804 llvm_unreachable(nullptr);
3808 // All arguments are treated the same.
3809 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3812 // Assign locations to all of the outgoing aggregate by value arguments.
3813 SmallVector<CCValAssign, 16> ByValArgLocs;
3814 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3815 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3817 // Reserve stack space for the allocations in CCInfo.
3818 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3820 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3822 // Size of the linkage area, parameter list area and the part of the local
3823 // space variable where copies of aggregates which are passed by value are
3825 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3827 // Calculate by how many bytes the stack has to be adjusted in case of tail
3828 // call optimization.
3829 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3831 // Adjust the stack pointer for the new arguments...
3832 // These operations are automatically eliminated by the prolog/epilog pass
3833 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3835 SDValue CallSeqStart = Chain;
3837 // Load the return address and frame pointer so it can be moved somewhere else
3840 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3843 // Set up a copy of the stack pointer for use loading and storing any
3844 // arguments that may not fit in the registers available for argument
3846 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3848 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3849 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3850 SmallVector<SDValue, 8> MemOpChains;
3852 bool seenFloatArg = false;
3853 // Walk the register/memloc assignments, inserting copies/loads.
3854 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3857 CCValAssign &VA = ArgLocs[i];
3858 SDValue Arg = OutVals[i];
3859 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3861 if (Flags.isByVal()) {
3862 // Argument is an aggregate which is passed by value, thus we need to
3863 // create a copy of it in the local variable space of the current stack
3864 // frame (which is the stack frame of the caller) and pass the address of
3865 // this copy to the callee.
3866 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3867 CCValAssign &ByValVA = ByValArgLocs[j++];
3868 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3870 // Memory reserved in the local variable space of the callers stack frame.
3871 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3873 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3874 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3876 // Create a copy of the argument in the local area of the current
3878 SDValue MemcpyCall =
3879 CreateCopyOfByValArgument(Arg, PtrOff,
3880 CallSeqStart.getNode()->getOperand(0),
3883 // This must go outside the CALLSEQ_START..END.
3884 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3885 CallSeqStart.getNode()->getOperand(1),
3887 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3888 NewCallSeqStart.getNode());
3889 Chain = CallSeqStart = NewCallSeqStart;
3891 // Pass the address of the aggregate copy on the stack either in a
3892 // physical register or in the parameter list area of the current stack
3893 // frame to the callee.
3897 if (VA.isRegLoc()) {
3898 if (Arg.getValueType() == MVT::i1)
3899 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
3901 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3902 // Put argument in a physical register.
3903 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3905 // Put argument in the parameter list area of the current stack frame.
3906 assert(VA.isMemLoc());
3907 unsigned LocMemOffset = VA.getLocMemOffset();
3910 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3911 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3913 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3914 MachinePointerInfo(),
3917 // Calculate and remember argument location.
3918 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3924 if (!MemOpChains.empty())
3925 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3927 // Build a sequence of copy-to-reg nodes chained together with token chain
3928 // and flag operands which copy the outgoing args into the appropriate regs.
3930 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3931 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3932 RegsToPass[i].second, InFlag);
3933 InFlag = Chain.getValue(1);
3936 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3939 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3940 SDValue Ops[] = { Chain, InFlag };
3942 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3943 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
3945 InFlag = Chain.getValue(1);
3949 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3950 false, TailCallArguments);
3952 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3953 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3957 // Copy an argument into memory, being careful to do this outside the
3958 // call sequence for the call to which the argument belongs.
3960 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3961 SDValue CallSeqStart,
3962 ISD::ArgFlagsTy Flags,
3965 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3966 CallSeqStart.getNode()->getOperand(0),
3968 // The MEMCPY must go outside the CALLSEQ_START..END.
3969 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3970 CallSeqStart.getNode()->getOperand(1),
3972 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3973 NewCallSeqStart.getNode());
3974 return NewCallSeqStart;
3978 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3979 CallingConv::ID CallConv, bool isVarArg,
3981 const SmallVectorImpl<ISD::OutputArg> &Outs,
3982 const SmallVectorImpl<SDValue> &OutVals,
3983 const SmallVectorImpl<ISD::InputArg> &Ins,
3984 SDLoc dl, SelectionDAG &DAG,
3985 SmallVectorImpl<SDValue> &InVals) const {
3987 bool isLittleEndian = Subtarget.isLittleEndian();
3988 unsigned NumOps = Outs.size();
3990 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3991 unsigned PtrByteSize = 8;
3993 MachineFunction &MF = DAG.getMachineFunction();
3995 // Mark this function as potentially containing a function that contains a
3996 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3997 // and restoring the callers stack pointer in this functions epilog. This is
3998 // done because by tail calling the called function might overwrite the value
3999 // in this function's (MF) stack pointer stack slot 0(SP).
4000 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4001 CallConv == CallingConv::Fast)
4002 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4004 // Count how many bytes are to be pushed on the stack, including the linkage
4005 // area, and parameter passing area. We start with at least 48 bytes, which
4006 // is reserved space for [SP][CR][LR][3 x unused].
4007 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false);
4008 unsigned NumBytes = LinkageSize;
4010 // Add up all the space actually used.
4011 for (unsigned i = 0; i != NumOps; ++i) {
4012 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4013 EVT ArgVT = Outs[i].VT;
4015 /* Respect alignment of argument on the stack. */
4016 unsigned Align = CalculateStackSlotAlignment(ArgVT, Flags, PtrByteSize);
4017 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4019 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4022 unsigned NumBytesActuallyUsed = NumBytes;
4024 // The prolog code of the callee may store up to 8 GPR argument registers to
4025 // the stack, allowing va_start to index over them in memory if its varargs.
4026 // Because we cannot tell if this is needed on the caller side, we have to
4027 // conservatively assume that it is needed. As such, make sure we have at
4028 // least enough stack space for the caller to store the 8 GPRs.
4029 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4031 // Tail call needs the stack to be aligned.
4032 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4033 CallConv == CallingConv::Fast)
4034 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4036 // Calculate by how many bytes the stack has to be adjusted in case of tail
4037 // call optimization.
4038 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4040 // To protect arguments on the stack from being clobbered in a tail call,
4041 // force all the loads to happen before doing any other lowering.
4043 Chain = DAG.getStackArgumentTokenFactor(Chain);
4045 // Adjust the stack pointer for the new arguments...
4046 // These operations are automatically eliminated by the prolog/epilog pass
4047 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4049 SDValue CallSeqStart = Chain;
4051 // Load the return address and frame pointer so it can be move somewhere else
4054 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4057 // Set up a copy of the stack pointer for use loading and storing any
4058 // arguments that may not fit in the registers available for argument
4060 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4062 // Figure out which arguments are going to go in registers, and which in
4063 // memory. Also, if this is a vararg function, floating point operations
4064 // must be stored to our stack, and loaded into integer regs as well, if
4065 // any integer regs are available for argument passing.
4066 unsigned ArgOffset = LinkageSize;
4067 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
4069 static const MCPhysReg GPR[] = {
4070 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4071 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4073 static const MCPhysReg *FPR = GetFPR();
4075 static const MCPhysReg VR[] = {
4076 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4077 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4079 static const MCPhysReg VSRH[] = {
4080 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4081 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4084 const unsigned NumGPRs = array_lengthof(GPR);
4085 const unsigned NumFPRs = 13;
4086 const unsigned NumVRs = array_lengthof(VR);
4088 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4089 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4091 SmallVector<SDValue, 8> MemOpChains;
4092 for (unsigned i = 0; i != NumOps; ++i) {
4093 SDValue Arg = OutVals[i];
4094 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4096 /* Respect alignment of argument on the stack. */
4098 CalculateStackSlotAlignment(Outs[i].VT, Flags, PtrByteSize);
4099 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4101 /* Compute GPR index associated with argument offset. */
4102 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4103 GPR_idx = std::min(GPR_idx, NumGPRs);
4105 // PtrOff will be used to store the current argument to the stack if a
4106 // register cannot be found for it.
4109 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4111 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4113 // Promote integers to 64-bit values.
4114 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4115 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4116 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4117 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4120 // FIXME memcpy is used way more than necessary. Correctness first.
4121 // Note: "by value" is code for passing a structure by value, not
4123 if (Flags.isByVal()) {
4124 // Note: Size includes alignment padding, so
4125 // struct x { short a; char b; }
4126 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4127 // These are the proper values we need for right-justifying the
4128 // aggregate in a parameter register.
4129 unsigned Size = Flags.getByValSize();
4131 // An empty aggregate parameter takes up no storage and no
4136 // All aggregates smaller than 8 bytes must be passed right-justified.
4137 if (Size==1 || Size==2 || Size==4) {
4138 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4139 if (GPR_idx != NumGPRs) {
4140 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4141 MachinePointerInfo(), VT,
4143 MemOpChains.push_back(Load.getValue(1));
4144 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4146 ArgOffset += PtrByteSize;
4151 if (GPR_idx == NumGPRs && Size < 8) {
4152 SDValue AddPtr = PtrOff;
4153 if (!isLittleEndian) {
4154 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4155 PtrOff.getValueType());
4156 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4158 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4161 ArgOffset += PtrByteSize;
4164 // Copy entire object into memory. There are cases where gcc-generated
4165 // code assumes it is there, even if it could be put entirely into
4166 // registers. (This is not what the doc says.)
4168 // FIXME: The above statement is likely due to a misunderstanding of the
4169 // documents. All arguments must be copied into the parameter area BY
4170 // THE CALLEE in the event that the callee takes the address of any
4171 // formal argument. That has not yet been implemented. However, it is
4172 // reasonable to use the stack area as a staging area for the register
4175 // Skip this for small aggregates, as we will use the same slot for a
4176 // right-justified copy, below.
4178 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4182 // When a register is available, pass a small aggregate right-justified.
4183 if (Size < 8 && GPR_idx != NumGPRs) {
4184 // The easiest way to get this right-justified in a register
4185 // is to copy the structure into the rightmost portion of a
4186 // local variable slot, then load the whole slot into the
4188 // FIXME: The memcpy seems to produce pretty awful code for
4189 // small aggregates, particularly for packed ones.
4190 // FIXME: It would be preferable to use the slot in the
4191 // parameter save area instead of a new local variable.
4192 SDValue AddPtr = PtrOff;
4193 if (!isLittleEndian) {
4194 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4195 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4197 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4201 // Load the slot into the register.
4202 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4203 MachinePointerInfo(),
4204 false, false, false, 0);
4205 MemOpChains.push_back(Load.getValue(1));
4206 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4208 // Done with this argument.
4209 ArgOffset += PtrByteSize;
4213 // For aggregates larger than PtrByteSize, copy the pieces of the
4214 // object that fit into registers from the parameter save area.
4215 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4216 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4217 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4218 if (GPR_idx != NumGPRs) {
4219 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4220 MachinePointerInfo(),
4221 false, false, false, 0);
4222 MemOpChains.push_back(Load.getValue(1));
4223 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4224 ArgOffset += PtrByteSize;
4226 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4233 switch (Arg.getSimpleValueType().SimpleTy) {
4234 default: llvm_unreachable("Unexpected ValueType for argument!");
4238 if (GPR_idx != NumGPRs) {
4239 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Arg));
4241 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4242 true, isTailCall, false, MemOpChains,
4243 TailCallArguments, dl);
4245 ArgOffset += PtrByteSize;
4249 if (FPR_idx != NumFPRs) {
4250 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4253 // A single float or an aggregate containing only a single float
4254 // must be passed right-justified in the stack doubleword, and
4255 // in the GPR, if one is available.
4257 if (Arg.getSimpleValueType().SimpleTy == MVT::f32 &&
4259 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4260 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4264 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
4265 MachinePointerInfo(), false, false, 0);
4266 MemOpChains.push_back(Store);
4268 // Float varargs are always shadowed in available integer registers
4269 if (GPR_idx != NumGPRs) {
4270 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4271 MachinePointerInfo(), false, false,
4273 MemOpChains.push_back(Load.getValue(1));
4274 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4278 // Single-precision floating-point values are mapped to the
4279 // second (rightmost) word of the stack doubleword.
4280 if (Arg.getValueType() == MVT::f32 && !isLittleEndian) {
4281 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4282 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4285 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4286 true, isTailCall, false, MemOpChains,
4287 TailCallArguments, dl);
4297 // For a varargs call, named arguments go into VRs or on the stack as
4298 // usual; unnamed arguments always go to the stack or the corresponding
4299 // GPRs when within range. For now, we always put the value in both
4300 // locations (or even all three).
4302 // We could elide this store in the case where the object fits
4303 // entirely in R registers. Maybe later.
4304 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4305 MachinePointerInfo(), false, false, 0);
4306 MemOpChains.push_back(Store);
4307 if (VR_idx != NumVRs) {
4308 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4309 MachinePointerInfo(),
4310 false, false, false, 0);
4311 MemOpChains.push_back(Load.getValue(1));
4313 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4314 Arg.getSimpleValueType() == MVT::v2i64) ?
4315 VSRH[VR_idx] : VR[VR_idx];
4318 RegsToPass.push_back(std::make_pair(VReg, Load));
4321 for (unsigned i=0; i<16; i+=PtrByteSize) {
4322 if (GPR_idx == NumGPRs)
4324 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4325 DAG.getConstant(i, PtrVT));
4326 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4327 false, false, false, 0);
4328 MemOpChains.push_back(Load.getValue(1));
4329 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4334 // Non-varargs Altivec params go into VRs or on the stack.
4335 if (VR_idx != NumVRs) {
4336 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4337 Arg.getSimpleValueType() == MVT::v2i64) ?
4338 VSRH[VR_idx] : VR[VR_idx];
4341 RegsToPass.push_back(std::make_pair(VReg, Arg));
4343 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4344 true, isTailCall, true, MemOpChains,
4345 TailCallArguments, dl);
4352 assert(NumBytesActuallyUsed == ArgOffset);
4353 (void)NumBytesActuallyUsed;
4355 if (!MemOpChains.empty())
4356 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4358 // Check if this is an indirect call (MTCTR/BCTRL).
4359 // See PrepareCall() for more information about calls through function
4360 // pointers in the 64-bit SVR4 ABI.
4362 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4363 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4364 // Load r2 into a virtual register and store it to the TOC save area.
4365 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4366 // TOC save area offset.
4367 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset();
4368 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4369 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4370 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4374 // Build a sequence of copy-to-reg nodes chained together with token chain
4375 // and flag operands which copy the outgoing args into the appropriate regs.
4377 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4378 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4379 RegsToPass[i].second, InFlag);
4380 InFlag = Chain.getValue(1);
4384 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4385 FPOp, true, TailCallArguments);
4387 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4388 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4393 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4394 CallingConv::ID CallConv, bool isVarArg,
4396 const SmallVectorImpl<ISD::OutputArg> &Outs,
4397 const SmallVectorImpl<SDValue> &OutVals,
4398 const SmallVectorImpl<ISD::InputArg> &Ins,
4399 SDLoc dl, SelectionDAG &DAG,
4400 SmallVectorImpl<SDValue> &InVals) const {
4402 unsigned NumOps = Outs.size();
4404 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4405 bool isPPC64 = PtrVT == MVT::i64;
4406 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4408 MachineFunction &MF = DAG.getMachineFunction();
4410 // Mark this function as potentially containing a function that contains a
4411 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4412 // and restoring the callers stack pointer in this functions epilog. This is
4413 // done because by tail calling the called function might overwrite the value
4414 // in this function's (MF) stack pointer stack slot 0(SP).
4415 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4416 CallConv == CallingConv::Fast)
4417 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4419 // Count how many bytes are to be pushed on the stack, including the linkage
4420 // area, and parameter passing area. We start with 24/48 bytes, which is
4421 // prereserved space for [SP][CR][LR][3 x unused].
4422 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true);
4423 unsigned NumBytes = LinkageSize;
4425 // Add up all the space actually used.
4426 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4427 // they all go in registers, but we must reserve stack space for them for
4428 // possible use by the caller. In varargs or 64-bit calls, parameters are
4429 // assigned stack space in order, with padding so Altivec parameters are
4431 unsigned nAltivecParamsAtEnd = 0;
4432 for (unsigned i = 0; i != NumOps; ++i) {
4433 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4434 EVT ArgVT = Outs[i].VT;
4435 // Varargs Altivec parameters are padded to a 16 byte boundary.
4436 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4437 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4438 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4439 if (!isVarArg && !isPPC64) {
4440 // Non-varargs Altivec parameters go after all the non-Altivec
4441 // parameters; handle those later so we know how much padding we need.
4442 nAltivecParamsAtEnd++;
4445 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4446 NumBytes = ((NumBytes+15)/16)*16;
4448 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4451 // Allow for Altivec parameters at the end, if needed.
4452 if (nAltivecParamsAtEnd) {
4453 NumBytes = ((NumBytes+15)/16)*16;
4454 NumBytes += 16*nAltivecParamsAtEnd;
4457 // The prolog code of the callee may store up to 8 GPR argument registers to
4458 // the stack, allowing va_start to index over them in memory if its varargs.
4459 // Because we cannot tell if this is needed on the caller side, we have to
4460 // conservatively assume that it is needed. As such, make sure we have at
4461 // least enough stack space for the caller to store the 8 GPRs.
4462 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4464 // Tail call needs the stack to be aligned.
4465 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4466 CallConv == CallingConv::Fast)
4467 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4469 // Calculate by how many bytes the stack has to be adjusted in case of tail
4470 // call optimization.
4471 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4473 // To protect arguments on the stack from being clobbered in a tail call,
4474 // force all the loads to happen before doing any other lowering.
4476 Chain = DAG.getStackArgumentTokenFactor(Chain);
4478 // Adjust the stack pointer for the new arguments...
4479 // These operations are automatically eliminated by the prolog/epilog pass
4480 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4482 SDValue CallSeqStart = Chain;
4484 // Load the return address and frame pointer so it can be move somewhere else
4487 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4490 // Set up a copy of the stack pointer for use loading and storing any
4491 // arguments that may not fit in the registers available for argument
4495 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4497 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4499 // Figure out which arguments are going to go in registers, and which in
4500 // memory. Also, if this is a vararg function, floating point operations
4501 // must be stored to our stack, and loaded into integer regs as well, if
4502 // any integer regs are available for argument passing.
4503 unsigned ArgOffset = LinkageSize;
4504 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4506 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4507 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4508 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4510 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4511 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4512 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4514 static const MCPhysReg *FPR = GetFPR();
4516 static const MCPhysReg VR[] = {
4517 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4518 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4520 const unsigned NumGPRs = array_lengthof(GPR_32);
4521 const unsigned NumFPRs = 13;
4522 const unsigned NumVRs = array_lengthof(VR);
4524 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4526 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4527 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4529 SmallVector<SDValue, 8> MemOpChains;
4530 for (unsigned i = 0; i != NumOps; ++i) {
4531 SDValue Arg = OutVals[i];
4532 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4534 // PtrOff will be used to store the current argument to the stack if a
4535 // register cannot be found for it.
4538 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4540 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4542 // On PPC64, promote integers to 64-bit values.
4543 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4544 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4545 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4546 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4549 // FIXME memcpy is used way more than necessary. Correctness first.
4550 // Note: "by value" is code for passing a structure by value, not
4552 if (Flags.isByVal()) {
4553 unsigned Size = Flags.getByValSize();
4554 // Very small objects are passed right-justified. Everything else is
4555 // passed left-justified.
4556 if (Size==1 || Size==2) {
4557 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4558 if (GPR_idx != NumGPRs) {
4559 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4560 MachinePointerInfo(), VT,
4562 MemOpChains.push_back(Load.getValue(1));
4563 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4565 ArgOffset += PtrByteSize;
4567 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4568 PtrOff.getValueType());
4569 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4570 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4573 ArgOffset += PtrByteSize;
4577 // Copy entire object into memory. There are cases where gcc-generated
4578 // code assumes it is there, even if it could be put entirely into
4579 // registers. (This is not what the doc says.)
4580 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4584 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4585 // copy the pieces of the object that fit into registers from the
4586 // parameter save area.
4587 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4588 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4589 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4590 if (GPR_idx != NumGPRs) {
4591 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4592 MachinePointerInfo(),
4593 false, false, false, 0);
4594 MemOpChains.push_back(Load.getValue(1));
4595 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4596 ArgOffset += PtrByteSize;
4598 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4605 switch (Arg.getSimpleValueType().SimpleTy) {
4606 default: llvm_unreachable("Unexpected ValueType for argument!");
4610 if (GPR_idx != NumGPRs) {
4611 if (Arg.getValueType() == MVT::i1)
4612 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4614 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4616 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4617 isPPC64, isTailCall, false, MemOpChains,
4618 TailCallArguments, dl);
4620 ArgOffset += PtrByteSize;
4624 if (FPR_idx != NumFPRs) {
4625 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4628 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4629 MachinePointerInfo(), false, false, 0);
4630 MemOpChains.push_back(Store);
4632 // Float varargs are always shadowed in available integer registers
4633 if (GPR_idx != NumGPRs) {
4634 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4635 MachinePointerInfo(), false, false,
4637 MemOpChains.push_back(Load.getValue(1));
4638 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4640 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4641 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4642 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4643 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4644 MachinePointerInfo(),
4645 false, false, false, 0);
4646 MemOpChains.push_back(Load.getValue(1));
4647 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4650 // If we have any FPRs remaining, we may also have GPRs remaining.
4651 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4653 if (GPR_idx != NumGPRs)
4655 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4656 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4660 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4661 isPPC64, isTailCall, false, MemOpChains,
4662 TailCallArguments, dl);
4666 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4673 // These go aligned on the stack, or in the corresponding R registers
4674 // when within range. The Darwin PPC ABI doc claims they also go in
4675 // V registers; in fact gcc does this only for arguments that are
4676 // prototyped, not for those that match the ... We do it for all
4677 // arguments, seems to work.
4678 while (ArgOffset % 16 !=0) {
4679 ArgOffset += PtrByteSize;
4680 if (GPR_idx != NumGPRs)
4683 // We could elide this store in the case where the object fits
4684 // entirely in R registers. Maybe later.
4685 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4686 DAG.getConstant(ArgOffset, PtrVT));
4687 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4688 MachinePointerInfo(), false, false, 0);
4689 MemOpChains.push_back(Store);
4690 if (VR_idx != NumVRs) {
4691 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4692 MachinePointerInfo(),
4693 false, false, false, 0);
4694 MemOpChains.push_back(Load.getValue(1));
4695 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4698 for (unsigned i=0; i<16; i+=PtrByteSize) {
4699 if (GPR_idx == NumGPRs)
4701 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4702 DAG.getConstant(i, PtrVT));
4703 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4704 false, false, false, 0);
4705 MemOpChains.push_back(Load.getValue(1));
4706 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4711 // Non-varargs Altivec params generally go in registers, but have
4712 // stack space allocated at the end.
4713 if (VR_idx != NumVRs) {
4714 // Doesn't have GPR space allocated.
4715 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4716 } else if (nAltivecParamsAtEnd==0) {
4717 // We are emitting Altivec params in order.
4718 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4719 isPPC64, isTailCall, true, MemOpChains,
4720 TailCallArguments, dl);
4726 // If all Altivec parameters fit in registers, as they usually do,
4727 // they get stack space following the non-Altivec parameters. We
4728 // don't track this here because nobody below needs it.
4729 // If there are more Altivec parameters than fit in registers emit
4731 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4733 // Offset is aligned; skip 1st 12 params which go in V registers.
4734 ArgOffset = ((ArgOffset+15)/16)*16;
4736 for (unsigned i = 0; i != NumOps; ++i) {
4737 SDValue Arg = OutVals[i];
4738 EVT ArgType = Outs[i].VT;
4739 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4740 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4743 // We are emitting Altivec params in order.
4744 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4745 isPPC64, isTailCall, true, MemOpChains,
4746 TailCallArguments, dl);
4753 if (!MemOpChains.empty())
4754 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4756 // On Darwin, R12 must contain the address of an indirect callee. This does
4757 // not mean the MTCTR instruction must use R12; it's easier to model this as
4758 // an extra parameter, so do that.
4760 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4761 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4762 !isBLACompatibleAddress(Callee, DAG))
4763 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4764 PPC::R12), Callee));
4766 // Build a sequence of copy-to-reg nodes chained together with token chain
4767 // and flag operands which copy the outgoing args into the appropriate regs.
4769 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4770 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4771 RegsToPass[i].second, InFlag);
4772 InFlag = Chain.getValue(1);
4776 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4777 FPOp, true, TailCallArguments);
4779 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4780 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4785 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4786 MachineFunction &MF, bool isVarArg,
4787 const SmallVectorImpl<ISD::OutputArg> &Outs,
4788 LLVMContext &Context) const {
4789 SmallVector<CCValAssign, 16> RVLocs;
4790 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4792 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4796 PPCTargetLowering::LowerReturn(SDValue Chain,
4797 CallingConv::ID CallConv, bool isVarArg,
4798 const SmallVectorImpl<ISD::OutputArg> &Outs,
4799 const SmallVectorImpl<SDValue> &OutVals,
4800 SDLoc dl, SelectionDAG &DAG) const {
4802 SmallVector<CCValAssign, 16> RVLocs;
4803 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4804 getTargetMachine(), RVLocs, *DAG.getContext());
4805 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4808 SmallVector<SDValue, 4> RetOps(1, Chain);
4810 // Copy the result values into the output registers.
4811 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4812 CCValAssign &VA = RVLocs[i];
4813 assert(VA.isRegLoc() && "Can only return in registers!");
4815 SDValue Arg = OutVals[i];
4817 switch (VA.getLocInfo()) {
4818 default: llvm_unreachable("Unknown loc info!");
4819 case CCValAssign::Full: break;
4820 case CCValAssign::AExt:
4821 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4823 case CCValAssign::ZExt:
4824 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4826 case CCValAssign::SExt:
4827 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4831 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4832 Flag = Chain.getValue(1);
4833 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4836 RetOps[0] = Chain; // Update chain.
4838 // Add the flag if we have it.
4840 RetOps.push_back(Flag);
4842 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
4845 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4846 const PPCSubtarget &Subtarget) const {
4847 // When we pop the dynamic allocation we need to restore the SP link.
4850 // Get the corect type for pointers.
4851 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4853 // Construct the stack pointer operand.
4854 bool isPPC64 = Subtarget.isPPC64();
4855 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4856 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4858 // Get the operands for the STACKRESTORE.
4859 SDValue Chain = Op.getOperand(0);
4860 SDValue SaveSP = Op.getOperand(1);
4862 // Load the old link SP.
4863 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4864 MachinePointerInfo(),
4865 false, false, false, 0);
4867 // Restore the stack pointer.
4868 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4870 // Store the old link SP.
4871 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4878 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4879 MachineFunction &MF = DAG.getMachineFunction();
4880 bool isPPC64 = Subtarget.isPPC64();
4881 bool isDarwinABI = Subtarget.isDarwinABI();
4882 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4884 // Get current frame pointer save index. The users of this index will be
4885 // primarily DYNALLOC instructions.
4886 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4887 int RASI = FI->getReturnAddrSaveIndex();
4889 // If the frame pointer save index hasn't been defined yet.
4891 // Find out what the fix offset of the frame pointer save area.
4892 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4893 // Allocate the frame index for frame pointer save area.
4894 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4896 FI->setReturnAddrSaveIndex(RASI);
4898 return DAG.getFrameIndex(RASI, PtrVT);
4902 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4903 MachineFunction &MF = DAG.getMachineFunction();
4904 bool isPPC64 = Subtarget.isPPC64();
4905 bool isDarwinABI = Subtarget.isDarwinABI();
4906 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4908 // Get current frame pointer save index. The users of this index will be
4909 // primarily DYNALLOC instructions.
4910 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4911 int FPSI = FI->getFramePointerSaveIndex();
4913 // If the frame pointer save index hasn't been defined yet.
4915 // Find out what the fix offset of the frame pointer save area.
4916 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4919 // Allocate the frame index for frame pointer save area.
4920 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4922 FI->setFramePointerSaveIndex(FPSI);
4924 return DAG.getFrameIndex(FPSI, PtrVT);
4927 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4929 const PPCSubtarget &Subtarget) const {
4931 SDValue Chain = Op.getOperand(0);
4932 SDValue Size = Op.getOperand(1);
4935 // Get the corect type for pointers.
4936 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4938 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4939 DAG.getConstant(0, PtrVT), Size);
4940 // Construct a node for the frame pointer save index.
4941 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4942 // Build a DYNALLOC node.
4943 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4944 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4945 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
4948 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4949 SelectionDAG &DAG) const {
4951 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4952 DAG.getVTList(MVT::i32, MVT::Other),
4953 Op.getOperand(0), Op.getOperand(1));
4956 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4957 SelectionDAG &DAG) const {
4959 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4960 Op.getOperand(0), Op.getOperand(1));
4963 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
4964 assert(Op.getValueType() == MVT::i1 &&
4965 "Custom lowering only for i1 loads");
4967 // First, load 8 bits into 32 bits, then truncate to 1 bit.
4970 LoadSDNode *LD = cast<LoadSDNode>(Op);
4972 SDValue Chain = LD->getChain();
4973 SDValue BasePtr = LD->getBasePtr();
4974 MachineMemOperand *MMO = LD->getMemOperand();
4976 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
4977 BasePtr, MVT::i8, MMO);
4978 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
4980 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
4981 return DAG.getMergeValues(Ops, dl);
4984 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
4985 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
4986 "Custom lowering only for i1 stores");
4988 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
4991 StoreSDNode *ST = cast<StoreSDNode>(Op);
4993 SDValue Chain = ST->getChain();
4994 SDValue BasePtr = ST->getBasePtr();
4995 SDValue Value = ST->getValue();
4996 MachineMemOperand *MMO = ST->getMemOperand();
4998 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
4999 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5002 // FIXME: Remove this once the ANDI glue bug is fixed:
5003 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5004 assert(Op.getValueType() == MVT::i1 &&
5005 "Custom lowering only for i1 results");
5008 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5012 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5014 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5015 // Not FP? Not a fsel.
5016 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5017 !Op.getOperand(2).getValueType().isFloatingPoint())
5020 // We might be able to do better than this under some circumstances, but in
5021 // general, fsel-based lowering of select is a finite-math-only optimization.
5022 // For more information, see section F.3 of the 2.06 ISA specification.
5023 if (!DAG.getTarget().Options.NoInfsFPMath ||
5024 !DAG.getTarget().Options.NoNaNsFPMath)
5027 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5029 EVT ResVT = Op.getValueType();
5030 EVT CmpVT = Op.getOperand(0).getValueType();
5031 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5032 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5035 // If the RHS of the comparison is a 0.0, we don't need to do the
5036 // subtraction at all.
5038 if (isFloatingPointZero(RHS))
5040 default: break; // SETUO etc aren't handled by fsel.
5044 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5045 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5046 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5047 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5048 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5049 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5050 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5053 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5056 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5057 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5058 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5061 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5064 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5065 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5066 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5067 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5072 default: break; // SETUO etc aren't handled by fsel.
5076 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5077 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5078 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5079 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5080 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5081 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5082 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5083 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5086 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5087 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5088 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5089 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5092 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5093 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5094 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5095 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5098 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5099 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5100 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5101 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5104 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5105 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5106 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5107 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5112 // FIXME: Split this code up when LegalizeDAGTypes lands.
5113 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5115 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5116 SDValue Src = Op.getOperand(0);
5117 if (Src.getValueType() == MVT::f32)
5118 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5121 switch (Op.getSimpleValueType().SimpleTy) {
5122 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5124 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5125 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5130 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5131 "i64 FP_TO_UINT is supported only with FPCVT");
5132 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5138 // Convert the FP value to an int value through memory.
5139 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5140 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5141 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5142 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5143 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5145 // Emit a store to the stack slot.
5148 MachineFunction &MF = DAG.getMachineFunction();
5149 MachineMemOperand *MMO =
5150 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5151 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5152 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5153 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5155 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5156 MPI, false, false, 0);
5158 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5160 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5161 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5162 DAG.getConstant(4, FIPtr.getValueType()));
5163 MPI = MachinePointerInfo();
5166 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5167 false, false, false, 0);
5170 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5171 SelectionDAG &DAG) const {
5173 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5174 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5177 if (Op.getOperand(0).getValueType() == MVT::i1)
5178 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5179 DAG.getConstantFP(1.0, Op.getValueType()),
5180 DAG.getConstantFP(0.0, Op.getValueType()));
5182 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5183 "UINT_TO_FP is supported only with FPCVT");
5185 // If we have FCFIDS, then use it when converting to single-precision.
5186 // Otherwise, convert to double-precision and then round.
5187 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5188 (Op.getOpcode() == ISD::UINT_TO_FP ?
5189 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5190 (Op.getOpcode() == ISD::UINT_TO_FP ?
5191 PPCISD::FCFIDU : PPCISD::FCFID);
5192 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5193 MVT::f32 : MVT::f64;
5195 if (Op.getOperand(0).getValueType() == MVT::i64) {
5196 SDValue SINT = Op.getOperand(0);
5197 // When converting to single-precision, we actually need to convert
5198 // to double-precision first and then round to single-precision.
5199 // To avoid double-rounding effects during that operation, we have
5200 // to prepare the input operand. Bits that might be truncated when
5201 // converting to double-precision are replaced by a bit that won't
5202 // be lost at this stage, but is below the single-precision rounding
5205 // However, if -enable-unsafe-fp-math is in effect, accept double
5206 // rounding to avoid the extra overhead.
5207 if (Op.getValueType() == MVT::f32 &&
5208 !Subtarget.hasFPCVT() &&
5209 !DAG.getTarget().Options.UnsafeFPMath) {
5211 // Twiddle input to make sure the low 11 bits are zero. (If this
5212 // is the case, we are guaranteed the value will fit into the 53 bit
5213 // mantissa of an IEEE double-precision value without rounding.)
5214 // If any of those low 11 bits were not zero originally, make sure
5215 // bit 12 (value 2048) is set instead, so that the final rounding
5216 // to single-precision gets the correct result.
5217 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5218 SINT, DAG.getConstant(2047, MVT::i64));
5219 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5220 Round, DAG.getConstant(2047, MVT::i64));
5221 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5222 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5223 Round, DAG.getConstant(-2048, MVT::i64));
5225 // However, we cannot use that value unconditionally: if the magnitude
5226 // of the input value is small, the bit-twiddling we did above might
5227 // end up visibly changing the output. Fortunately, in that case, we
5228 // don't need to twiddle bits since the original input will convert
5229 // exactly to double-precision floating-point already. Therefore,
5230 // construct a conditional to use the original value if the top 11
5231 // bits are all sign-bit copies, and use the rounded value computed
5233 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5234 SINT, DAG.getConstant(53, MVT::i32));
5235 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5236 Cond, DAG.getConstant(1, MVT::i64));
5237 Cond = DAG.getSetCC(dl, MVT::i32,
5238 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5240 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5243 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5244 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5246 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5247 FP = DAG.getNode(ISD::FP_ROUND, dl,
5248 MVT::f32, FP, DAG.getIntPtrConstant(0));
5252 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5253 "Unhandled INT_TO_FP type in custom expander!");
5254 // Since we only generate this in 64-bit mode, we can take advantage of
5255 // 64-bit registers. In particular, sign extend the input value into the
5256 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5257 // then lfd it and fcfid it.
5258 MachineFunction &MF = DAG.getMachineFunction();
5259 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5260 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5263 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5264 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5265 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5267 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5268 MachinePointerInfo::getFixedStack(FrameIdx),
5271 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5272 "Expected an i32 store");
5273 MachineMemOperand *MMO =
5274 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5275 MachineMemOperand::MOLoad, 4, 4);
5276 SDValue Ops[] = { Store, FIdx };
5277 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5278 PPCISD::LFIWZX : PPCISD::LFIWAX,
5279 dl, DAG.getVTList(MVT::f64, MVT::Other),
5280 Ops, MVT::i32, MMO);
5282 assert(Subtarget.isPPC64() &&
5283 "i32->FP without LFIWAX supported only on PPC64");
5285 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5286 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5288 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5291 // STD the extended value into the stack slot.
5292 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5293 MachinePointerInfo::getFixedStack(FrameIdx),
5296 // Load the value as a double.
5297 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5298 MachinePointerInfo::getFixedStack(FrameIdx),
5299 false, false, false, 0);
5302 // FCFID it and return it.
5303 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5304 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5305 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5309 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5310 SelectionDAG &DAG) const {
5313 The rounding mode is in bits 30:31 of FPSR, and has the following
5320 FLT_ROUNDS, on the other hand, expects the following:
5327 To perform the conversion, we do:
5328 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5331 MachineFunction &MF = DAG.getMachineFunction();
5332 EVT VT = Op.getValueType();
5333 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5335 // Save FP Control Word to register
5337 MVT::f64, // return register
5338 MVT::Glue // unused in this context
5340 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5342 // Save FP register to stack slot
5343 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5344 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5345 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5346 StackSlot, MachinePointerInfo(), false, false,0);
5348 // Load FP Control Word from low 32 bits of stack slot.
5349 SDValue Four = DAG.getConstant(4, PtrVT);
5350 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5351 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5352 false, false, false, 0);
5354 // Transform as necessary
5356 DAG.getNode(ISD::AND, dl, MVT::i32,
5357 CWD, DAG.getConstant(3, MVT::i32));
5359 DAG.getNode(ISD::SRL, dl, MVT::i32,
5360 DAG.getNode(ISD::AND, dl, MVT::i32,
5361 DAG.getNode(ISD::XOR, dl, MVT::i32,
5362 CWD, DAG.getConstant(3, MVT::i32)),
5363 DAG.getConstant(3, MVT::i32)),
5364 DAG.getConstant(1, MVT::i32));
5367 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5369 return DAG.getNode((VT.getSizeInBits() < 16 ?
5370 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5373 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5374 EVT VT = Op.getValueType();
5375 unsigned BitWidth = VT.getSizeInBits();
5377 assert(Op.getNumOperands() == 3 &&
5378 VT == Op.getOperand(1).getValueType() &&
5381 // Expand into a bunch of logical ops. Note that these ops
5382 // depend on the PPC behavior for oversized shift amounts.
5383 SDValue Lo = Op.getOperand(0);
5384 SDValue Hi = Op.getOperand(1);
5385 SDValue Amt = Op.getOperand(2);
5386 EVT AmtVT = Amt.getValueType();
5388 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5389 DAG.getConstant(BitWidth, AmtVT), Amt);
5390 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5391 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5392 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5393 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5394 DAG.getConstant(-BitWidth, AmtVT));
5395 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5396 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5397 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5398 SDValue OutOps[] = { OutLo, OutHi };
5399 return DAG.getMergeValues(OutOps, dl);
5402 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5403 EVT VT = Op.getValueType();
5405 unsigned BitWidth = VT.getSizeInBits();
5406 assert(Op.getNumOperands() == 3 &&
5407 VT == Op.getOperand(1).getValueType() &&
5410 // Expand into a bunch of logical ops. Note that these ops
5411 // depend on the PPC behavior for oversized shift amounts.
5412 SDValue Lo = Op.getOperand(0);
5413 SDValue Hi = Op.getOperand(1);
5414 SDValue Amt = Op.getOperand(2);
5415 EVT AmtVT = Amt.getValueType();
5417 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5418 DAG.getConstant(BitWidth, AmtVT), Amt);
5419 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5420 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5421 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5422 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5423 DAG.getConstant(-BitWidth, AmtVT));
5424 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5425 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5426 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5427 SDValue OutOps[] = { OutLo, OutHi };
5428 return DAG.getMergeValues(OutOps, dl);
5431 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5433 EVT VT = Op.getValueType();
5434 unsigned BitWidth = VT.getSizeInBits();
5435 assert(Op.getNumOperands() == 3 &&
5436 VT == Op.getOperand(1).getValueType() &&
5439 // Expand into a bunch of logical ops, followed by a select_cc.
5440 SDValue Lo = Op.getOperand(0);
5441 SDValue Hi = Op.getOperand(1);
5442 SDValue Amt = Op.getOperand(2);
5443 EVT AmtVT = Amt.getValueType();
5445 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5446 DAG.getConstant(BitWidth, AmtVT), Amt);
5447 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5448 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5449 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5450 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5451 DAG.getConstant(-BitWidth, AmtVT));
5452 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5453 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5454 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5455 Tmp4, Tmp6, ISD::SETLE);
5456 SDValue OutOps[] = { OutLo, OutHi };
5457 return DAG.getMergeValues(OutOps, dl);
5460 //===----------------------------------------------------------------------===//
5461 // Vector related lowering.
5464 /// BuildSplatI - Build a canonical splati of Val with an element size of
5465 /// SplatSize. Cast the result to VT.
5466 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5467 SelectionDAG &DAG, SDLoc dl) {
5468 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5470 static const EVT VTys[] = { // canonical VT to use for each size.
5471 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5474 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5476 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5480 EVT CanonicalVT = VTys[SplatSize-1];
5482 // Build a canonical splat for this value.
5483 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5484 SmallVector<SDValue, 8> Ops;
5485 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5486 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5487 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5490 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5491 /// specified intrinsic ID.
5492 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5493 SelectionDAG &DAG, SDLoc dl,
5494 EVT DestVT = MVT::Other) {
5495 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5496 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5497 DAG.getConstant(IID, MVT::i32), Op);
5500 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5501 /// specified intrinsic ID.
5502 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5503 SelectionDAG &DAG, SDLoc dl,
5504 EVT DestVT = MVT::Other) {
5505 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5506 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5507 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5510 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5511 /// specified intrinsic ID.
5512 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5513 SDValue Op2, SelectionDAG &DAG,
5514 SDLoc dl, EVT DestVT = MVT::Other) {
5515 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5516 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5517 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5521 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5522 /// amount. The result has the specified value type.
5523 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5524 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5525 // Force LHS/RHS to be the right type.
5526 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5527 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5530 for (unsigned i = 0; i != 16; ++i)
5532 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5533 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5536 // If this is a case we can't handle, return null and let the default
5537 // expansion code take care of it. If we CAN select this case, and if it
5538 // selects to a single instruction, return Op. Otherwise, if we can codegen
5539 // this case more efficiently than a constant pool load, lower it to the
5540 // sequence of ops that should be used.
5541 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5542 SelectionDAG &DAG) const {
5544 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5545 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5547 // Check if this is a splat of a constant value.
5548 APInt APSplatBits, APSplatUndef;
5549 unsigned SplatBitSize;
5551 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5552 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5555 unsigned SplatBits = APSplatBits.getZExtValue();
5556 unsigned SplatUndef = APSplatUndef.getZExtValue();
5557 unsigned SplatSize = SplatBitSize / 8;
5559 // First, handle single instruction cases.
5562 if (SplatBits == 0) {
5563 // Canonicalize all zero vectors to be v4i32.
5564 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5565 SDValue Z = DAG.getConstant(0, MVT::i32);
5566 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5567 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5572 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5573 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5575 if (SextVal >= -16 && SextVal <= 15)
5576 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5579 // Two instruction sequences.
5581 // If this value is in the range [-32,30] and is even, use:
5582 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5583 // If this value is in the range [17,31] and is odd, use:
5584 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5585 // If this value is in the range [-31,-17] and is odd, use:
5586 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5587 // Note the last two are three-instruction sequences.
5588 if (SextVal >= -32 && SextVal <= 31) {
5589 // To avoid having these optimizations undone by constant folding,
5590 // we convert to a pseudo that will be expanded later into one of
5592 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5593 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5594 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5595 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5596 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5597 if (VT == Op.getValueType())
5600 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5603 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5604 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5606 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5607 // Make -1 and vspltisw -1:
5608 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5610 // Make the VSLW intrinsic, computing 0x8000_0000.
5611 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5614 // xor by OnesV to invert it.
5615 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5616 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5619 // The remaining cases assume either big endian element order or
5620 // a splat-size that equates to the element size of the vector
5621 // to be built. An example that doesn't work for little endian is
5622 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5623 // and a vector element size of 16 bits. The code below will
5624 // produce the vector in big endian element order, which for little
5625 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5627 // For now, just avoid these optimizations in that case.
5628 // FIXME: Develop correct optimizations for LE with mismatched
5629 // splat and element sizes.
5631 if (Subtarget.isLittleEndian() &&
5632 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5635 // Check to see if this is a wide variety of vsplti*, binop self cases.
5636 static const signed char SplatCsts[] = {
5637 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5638 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5641 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5642 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5643 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5644 int i = SplatCsts[idx];
5646 // Figure out what shift amount will be used by altivec if shifted by i in
5648 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5650 // vsplti + shl self.
5651 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5652 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5653 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5654 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5655 Intrinsic::ppc_altivec_vslw
5657 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5658 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5661 // vsplti + srl self.
5662 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5663 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5664 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5665 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5666 Intrinsic::ppc_altivec_vsrw
5668 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5669 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5672 // vsplti + sra self.
5673 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5674 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5675 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5676 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5677 Intrinsic::ppc_altivec_vsraw
5679 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5680 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5683 // vsplti + rol self.
5684 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5685 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5686 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5687 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5688 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5689 Intrinsic::ppc_altivec_vrlw
5691 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5692 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5695 // t = vsplti c, result = vsldoi t, t, 1
5696 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5697 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5698 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5700 // t = vsplti c, result = vsldoi t, t, 2
5701 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5702 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5703 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5705 // t = vsplti c, result = vsldoi t, t, 3
5706 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5707 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5708 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5715 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5716 /// the specified operations to build the shuffle.
5717 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5718 SDValue RHS, SelectionDAG &DAG,
5720 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5721 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5722 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5725 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5737 if (OpNum == OP_COPY) {
5738 if (LHSID == (1*9+2)*9+3) return LHS;
5739 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5743 SDValue OpLHS, OpRHS;
5744 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5745 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5749 default: llvm_unreachable("Unknown i32 permute!");
5751 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5752 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5753 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5754 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5757 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5758 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5759 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5760 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5763 for (unsigned i = 0; i != 16; ++i)
5764 ShufIdxs[i] = (i&3)+0;
5767 for (unsigned i = 0; i != 16; ++i)
5768 ShufIdxs[i] = (i&3)+4;
5771 for (unsigned i = 0; i != 16; ++i)
5772 ShufIdxs[i] = (i&3)+8;
5775 for (unsigned i = 0; i != 16; ++i)
5776 ShufIdxs[i] = (i&3)+12;
5779 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5781 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5783 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5785 EVT VT = OpLHS.getValueType();
5786 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5787 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5788 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5789 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5792 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5793 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5794 /// return the code it can be lowered into. Worst case, it can always be
5795 /// lowered into a vperm.
5796 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5797 SelectionDAG &DAG) const {
5799 SDValue V1 = Op.getOperand(0);
5800 SDValue V2 = Op.getOperand(1);
5801 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5802 EVT VT = Op.getValueType();
5803 bool isLittleEndian = Subtarget.isLittleEndian();
5805 // Cases that are handled by instructions that take permute immediates
5806 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5807 // selected by the instruction selector.
5808 if (V2.getOpcode() == ISD::UNDEF) {
5809 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5810 PPC::isSplatShuffleMask(SVOp, 2) ||
5811 PPC::isSplatShuffleMask(SVOp, 4) ||
5812 PPC::isVPKUWUMShuffleMask(SVOp, true, DAG) ||
5813 PPC::isVPKUHUMShuffleMask(SVOp, true, DAG) ||
5814 PPC::isVSLDOIShuffleMask(SVOp, true, DAG) != -1 ||
5815 PPC::isVMRGLShuffleMask(SVOp, 1, true, DAG) ||
5816 PPC::isVMRGLShuffleMask(SVOp, 2, true, DAG) ||
5817 PPC::isVMRGLShuffleMask(SVOp, 4, true, DAG) ||
5818 PPC::isVMRGHShuffleMask(SVOp, 1, true, DAG) ||
5819 PPC::isVMRGHShuffleMask(SVOp, 2, true, DAG) ||
5820 PPC::isVMRGHShuffleMask(SVOp, 4, true, DAG)) {
5825 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5826 // and produce a fixed permutation. If any of these match, do not lower to
5828 if (PPC::isVPKUWUMShuffleMask(SVOp, false, DAG) ||
5829 PPC::isVPKUHUMShuffleMask(SVOp, false, DAG) ||
5830 PPC::isVSLDOIShuffleMask(SVOp, false, DAG) != -1 ||
5831 PPC::isVMRGLShuffleMask(SVOp, 1, false, DAG) ||
5832 PPC::isVMRGLShuffleMask(SVOp, 2, false, DAG) ||
5833 PPC::isVMRGLShuffleMask(SVOp, 4, false, DAG) ||
5834 PPC::isVMRGHShuffleMask(SVOp, 1, false, DAG) ||
5835 PPC::isVMRGHShuffleMask(SVOp, 2, false, DAG) ||
5836 PPC::isVMRGHShuffleMask(SVOp, 4, false, DAG))
5839 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5840 // perfect shuffle table to emit an optimal matching sequence.
5841 ArrayRef<int> PermMask = SVOp->getMask();
5843 unsigned PFIndexes[4];
5844 bool isFourElementShuffle = true;
5845 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5846 unsigned EltNo = 8; // Start out undef.
5847 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5848 if (PermMask[i*4+j] < 0)
5849 continue; // Undef, ignore it.
5851 unsigned ByteSource = PermMask[i*4+j];
5852 if ((ByteSource & 3) != j) {
5853 isFourElementShuffle = false;
5858 EltNo = ByteSource/4;
5859 } else if (EltNo != ByteSource/4) {
5860 isFourElementShuffle = false;
5864 PFIndexes[i] = EltNo;
5867 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5868 // perfect shuffle vector to determine if it is cost effective to do this as
5869 // discrete instructions, or whether we should use a vperm.
5870 // For now, we skip this for little endian until such time as we have a
5871 // little-endian perfect shuffle table.
5872 if (isFourElementShuffle && !isLittleEndian) {
5873 // Compute the index in the perfect shuffle table.
5874 unsigned PFTableIndex =
5875 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5877 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5878 unsigned Cost = (PFEntry >> 30);
5880 // Determining when to avoid vperm is tricky. Many things affect the cost
5881 // of vperm, particularly how many times the perm mask needs to be computed.
5882 // For example, if the perm mask can be hoisted out of a loop or is already
5883 // used (perhaps because there are multiple permutes with the same shuffle
5884 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5885 // the loop requires an extra register.
5887 // As a compromise, we only emit discrete instructions if the shuffle can be
5888 // generated in 3 or fewer operations. When we have loop information
5889 // available, if this block is within a loop, we should avoid using vperm
5890 // for 3-operation perms and use a constant pool load instead.
5892 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5895 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5896 // vector that will get spilled to the constant pool.
5897 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5899 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5900 // that it is in input element units, not in bytes. Convert now.
5902 // For little endian, the order of the input vectors is reversed, and
5903 // the permutation mask is complemented with respect to 31. This is
5904 // necessary to produce proper semantics with the big-endian-biased vperm
5906 EVT EltVT = V1.getValueType().getVectorElementType();
5907 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5909 SmallVector<SDValue, 16> ResultMask;
5910 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5911 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5913 for (unsigned j = 0; j != BytesPerElement; ++j)
5915 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
5918 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5922 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5925 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
5928 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
5932 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5933 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5934 /// information about the intrinsic.
5935 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5937 unsigned IntrinsicID =
5938 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5941 switch (IntrinsicID) {
5942 default: return false;
5943 // Comparison predicates.
5944 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5945 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5946 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5947 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5948 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5949 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5950 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5951 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5952 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5953 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5954 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5955 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5956 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5958 // Normal Comparisons.
5959 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5960 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5961 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5962 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5963 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5964 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5965 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5966 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5967 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5968 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5969 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5970 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5971 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5976 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5977 /// lower, do it, otherwise return null.
5978 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5979 SelectionDAG &DAG) const {
5980 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5981 // opcode number of the comparison.
5985 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5986 return SDValue(); // Don't custom lower most intrinsics.
5988 // If this is a non-dot comparison, make the VCMP node and we are done.
5990 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5991 Op.getOperand(1), Op.getOperand(2),
5992 DAG.getConstant(CompareOpc, MVT::i32));
5993 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5996 // Create the PPCISD altivec 'dot' comparison node.
5998 Op.getOperand(2), // LHS
5999 Op.getOperand(3), // RHS
6000 DAG.getConstant(CompareOpc, MVT::i32)
6002 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6003 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6005 // Now that we have the comparison, emit a copy from the CR to a GPR.
6006 // This is flagged to the above dot comparison.
6007 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6008 DAG.getRegister(PPC::CR6, MVT::i32),
6009 CompNode.getValue(1));
6011 // Unpack the result based on how the target uses it.
6012 unsigned BitNo; // Bit # of CR6.
6013 bool InvertBit; // Invert result?
6014 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6015 default: // Can't happen, don't crash on invalid number though.
6016 case 0: // Return the value of the EQ bit of CR6.
6017 BitNo = 0; InvertBit = false;
6019 case 1: // Return the inverted value of the EQ bit of CR6.
6020 BitNo = 0; InvertBit = true;
6022 case 2: // Return the value of the LT bit of CR6.
6023 BitNo = 2; InvertBit = false;
6025 case 3: // Return the inverted value of the LT bit of CR6.
6026 BitNo = 2; InvertBit = true;
6030 // Shift the bit into the low position.
6031 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6032 DAG.getConstant(8-(3-BitNo), MVT::i32));
6034 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6035 DAG.getConstant(1, MVT::i32));
6037 // If we are supposed to, toggle the bit.
6039 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6040 DAG.getConstant(1, MVT::i32));
6044 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6045 SelectionDAG &DAG) const {
6047 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6048 // instructions), but for smaller types, we need to first extend up to v2i32
6049 // before doing going farther.
6050 if (Op.getValueType() == MVT::v2i64) {
6051 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6052 if (ExtVT != MVT::v2i32) {
6053 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6054 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6055 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6056 ExtVT.getVectorElementType(), 4)));
6057 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6058 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6059 DAG.getValueType(MVT::v2i32));
6068 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6069 SelectionDAG &DAG) const {
6071 // Create a stack slot that is 16-byte aligned.
6072 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6073 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6074 EVT PtrVT = getPointerTy();
6075 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6077 // Store the input value into Value#0 of the stack slot.
6078 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6079 Op.getOperand(0), FIdx, MachinePointerInfo(),
6082 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6083 false, false, false, 0);
6086 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6088 if (Op.getValueType() == MVT::v4i32) {
6089 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6091 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6092 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6094 SDValue RHSSwap = // = vrlw RHS, 16
6095 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6097 // Shrinkify inputs to v8i16.
6098 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6099 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6100 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6102 // Low parts multiplied together, generating 32-bit results (we ignore the
6104 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6105 LHS, RHS, DAG, dl, MVT::v4i32);
6107 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6108 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6109 // Shift the high parts up 16 bits.
6110 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6112 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6113 } else if (Op.getValueType() == MVT::v8i16) {
6114 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6116 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6118 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6119 LHS, RHS, Zero, DAG, dl);
6120 } else if (Op.getValueType() == MVT::v16i8) {
6121 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6122 bool isLittleEndian = Subtarget.isLittleEndian();
6124 // Multiply the even 8-bit parts, producing 16-bit sums.
6125 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6126 LHS, RHS, DAG, dl, MVT::v8i16);
6127 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6129 // Multiply the odd 8-bit parts, producing 16-bit sums.
6130 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6131 LHS, RHS, DAG, dl, MVT::v8i16);
6132 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6134 // Merge the results together. Because vmuleub and vmuloub are
6135 // instructions with a big-endian bias, we must reverse the
6136 // element numbering and reverse the meaning of "odd" and "even"
6137 // when generating little endian code.
6139 for (unsigned i = 0; i != 8; ++i) {
6140 if (isLittleEndian) {
6142 Ops[i*2+1] = 2*i+16;
6145 Ops[i*2+1] = 2*i+1+16;
6149 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6151 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6153 llvm_unreachable("Unknown mul to lower!");
6157 /// LowerOperation - Provide custom lowering hooks for some operations.
6159 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6160 switch (Op.getOpcode()) {
6161 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6162 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6163 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6164 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6165 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6166 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6167 case ISD::SETCC: return LowerSETCC(Op, DAG);
6168 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6169 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6171 return LowerVASTART(Op, DAG, Subtarget);
6174 return LowerVAARG(Op, DAG, Subtarget);
6177 return LowerVACOPY(Op, DAG, Subtarget);
6179 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6180 case ISD::DYNAMIC_STACKALLOC:
6181 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6183 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6184 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6186 case ISD::LOAD: return LowerLOAD(Op, DAG);
6187 case ISD::STORE: return LowerSTORE(Op, DAG);
6188 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6189 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6190 case ISD::FP_TO_UINT:
6191 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6193 case ISD::UINT_TO_FP:
6194 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6195 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6197 // Lower 64-bit shifts.
6198 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6199 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6200 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6202 // Vector-related lowering.
6203 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6204 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6205 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6206 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6207 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6208 case ISD::MUL: return LowerMUL(Op, DAG);
6210 // For counter-based loop handling.
6211 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6213 // Frame & Return address.
6214 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6215 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6219 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6220 SmallVectorImpl<SDValue>&Results,
6221 SelectionDAG &DAG) const {
6222 const TargetMachine &TM = getTargetMachine();
6224 switch (N->getOpcode()) {
6226 llvm_unreachable("Do not know how to custom type legalize this operation!");
6227 case ISD::INTRINSIC_W_CHAIN: {
6228 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6229 Intrinsic::ppc_is_decremented_ctr_nonzero)
6232 assert(N->getValueType(0) == MVT::i1 &&
6233 "Unexpected result type for CTR decrement intrinsic");
6234 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6235 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6236 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6239 Results.push_back(NewInt);
6240 Results.push_back(NewInt.getValue(1));
6244 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6245 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6248 EVT VT = N->getValueType(0);
6250 if (VT == MVT::i64) {
6251 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6253 Results.push_back(NewNode);
6254 Results.push_back(NewNode.getValue(1));
6258 case ISD::FP_ROUND_INREG: {
6259 assert(N->getValueType(0) == MVT::ppcf128);
6260 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6261 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6262 MVT::f64, N->getOperand(0),
6263 DAG.getIntPtrConstant(0));
6264 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6265 MVT::f64, N->getOperand(0),
6266 DAG.getIntPtrConstant(1));
6268 // Add the two halves of the long double in round-to-zero mode.
6269 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6271 // We know the low half is about to be thrown away, so just use something
6273 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6277 case ISD::FP_TO_SINT:
6278 // LowerFP_TO_INT() can only handle f32 and f64.
6279 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6281 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6287 //===----------------------------------------------------------------------===//
6288 // Other Lowering Code
6289 //===----------------------------------------------------------------------===//
6292 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6293 bool is64bit, unsigned BinOpcode) const {
6294 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6295 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6297 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6298 MachineFunction *F = BB->getParent();
6299 MachineFunction::iterator It = BB;
6302 unsigned dest = MI->getOperand(0).getReg();
6303 unsigned ptrA = MI->getOperand(1).getReg();
6304 unsigned ptrB = MI->getOperand(2).getReg();
6305 unsigned incr = MI->getOperand(3).getReg();
6306 DebugLoc dl = MI->getDebugLoc();
6308 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6309 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6310 F->insert(It, loopMBB);
6311 F->insert(It, exitMBB);
6312 exitMBB->splice(exitMBB->begin(), BB,
6313 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6314 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6316 MachineRegisterInfo &RegInfo = F->getRegInfo();
6317 unsigned TmpReg = (!BinOpcode) ? incr :
6318 RegInfo.createVirtualRegister(
6319 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6320 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6324 // fallthrough --> loopMBB
6325 BB->addSuccessor(loopMBB);
6328 // l[wd]arx dest, ptr
6329 // add r0, dest, incr
6330 // st[wd]cx. r0, ptr
6332 // fallthrough --> exitMBB
6334 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6335 .addReg(ptrA).addReg(ptrB);
6337 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6338 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6339 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6340 BuildMI(BB, dl, TII->get(PPC::BCC))
6341 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6342 BB->addSuccessor(loopMBB);
6343 BB->addSuccessor(exitMBB);
6352 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6353 MachineBasicBlock *BB,
6354 bool is8bit, // operation
6355 unsigned BinOpcode) const {
6356 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6357 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6358 // In 64 bit mode we have to use 64 bits for addresses, even though the
6359 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6360 // registers without caring whether they're 32 or 64, but here we're
6361 // doing actual arithmetic on the addresses.
6362 bool is64bit = Subtarget.isPPC64();
6363 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6365 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6366 MachineFunction *F = BB->getParent();
6367 MachineFunction::iterator It = BB;
6370 unsigned dest = MI->getOperand(0).getReg();
6371 unsigned ptrA = MI->getOperand(1).getReg();
6372 unsigned ptrB = MI->getOperand(2).getReg();
6373 unsigned incr = MI->getOperand(3).getReg();
6374 DebugLoc dl = MI->getDebugLoc();
6376 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6377 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6378 F->insert(It, loopMBB);
6379 F->insert(It, exitMBB);
6380 exitMBB->splice(exitMBB->begin(), BB,
6381 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6382 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6384 MachineRegisterInfo &RegInfo = F->getRegInfo();
6385 const TargetRegisterClass *RC =
6386 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6387 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6388 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6389 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6390 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6391 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6392 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6393 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6394 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6395 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6396 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6397 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6398 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6400 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6404 // fallthrough --> loopMBB
6405 BB->addSuccessor(loopMBB);
6407 // The 4-byte load must be aligned, while a char or short may be
6408 // anywhere in the word. Hence all this nasty bookkeeping code.
6409 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6410 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6411 // xori shift, shift1, 24 [16]
6412 // rlwinm ptr, ptr1, 0, 0, 29
6413 // slw incr2, incr, shift
6414 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6415 // slw mask, mask2, shift
6417 // lwarx tmpDest, ptr
6418 // add tmp, tmpDest, incr2
6419 // andc tmp2, tmpDest, mask
6420 // and tmp3, tmp, mask
6421 // or tmp4, tmp3, tmp2
6424 // fallthrough --> exitMBB
6425 // srw dest, tmpDest, shift
6426 if (ptrA != ZeroReg) {
6427 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6428 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6429 .addReg(ptrA).addReg(ptrB);
6433 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6434 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6435 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6436 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6438 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6439 .addReg(Ptr1Reg).addImm(0).addImm(61);
6441 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6442 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6443 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6444 .addReg(incr).addReg(ShiftReg);
6446 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6448 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6449 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6451 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6452 .addReg(Mask2Reg).addReg(ShiftReg);
6455 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6456 .addReg(ZeroReg).addReg(PtrReg);
6458 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6459 .addReg(Incr2Reg).addReg(TmpDestReg);
6460 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6461 .addReg(TmpDestReg).addReg(MaskReg);
6462 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6463 .addReg(TmpReg).addReg(MaskReg);
6464 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6465 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6466 BuildMI(BB, dl, TII->get(PPC::STWCX))
6467 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6468 BuildMI(BB, dl, TII->get(PPC::BCC))
6469 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6470 BB->addSuccessor(loopMBB);
6471 BB->addSuccessor(exitMBB);
6476 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6481 llvm::MachineBasicBlock*
6482 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6483 MachineBasicBlock *MBB) const {
6484 DebugLoc DL = MI->getDebugLoc();
6485 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6487 MachineFunction *MF = MBB->getParent();
6488 MachineRegisterInfo &MRI = MF->getRegInfo();
6490 const BasicBlock *BB = MBB->getBasicBlock();
6491 MachineFunction::iterator I = MBB;
6495 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6496 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6498 unsigned DstReg = MI->getOperand(0).getReg();
6499 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6500 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6501 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6502 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6504 MVT PVT = getPointerTy();
6505 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6506 "Invalid Pointer Size!");
6507 // For v = setjmp(buf), we generate
6510 // SjLjSetup mainMBB
6516 // buf[LabelOffset] = LR
6520 // v = phi(main, restore)
6523 MachineBasicBlock *thisMBB = MBB;
6524 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6525 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6526 MF->insert(I, mainMBB);
6527 MF->insert(I, sinkMBB);
6529 MachineInstrBuilder MIB;
6531 // Transfer the remainder of BB and its successor edges to sinkMBB.
6532 sinkMBB->splice(sinkMBB->begin(), MBB,
6533 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6534 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6536 // Note that the structure of the jmp_buf used here is not compatible
6537 // with that used by libc, and is not designed to be. Specifically, it
6538 // stores only those 'reserved' registers that LLVM does not otherwise
6539 // understand how to spill. Also, by convention, by the time this
6540 // intrinsic is called, Clang has already stored the frame address in the
6541 // first slot of the buffer and stack address in the third. Following the
6542 // X86 target code, we'll store the jump address in the second slot. We also
6543 // need to save the TOC pointer (R2) to handle jumps between shared
6544 // libraries, and that will be stored in the fourth slot. The thread
6545 // identifier (R13) is not affected.
6548 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6549 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6550 const int64_t BPOffset = 4 * PVT.getStoreSize();
6552 // Prepare IP either in reg.
6553 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6554 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6555 unsigned BufReg = MI->getOperand(1).getReg();
6557 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6558 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6562 MIB.setMemRefs(MMOBegin, MMOEnd);
6565 // Naked functions never have a base pointer, and so we use r1. For all
6566 // other functions, this decision must be delayed until during PEI.
6568 if (MF->getFunction()->getAttributes().hasAttribute(
6569 AttributeSet::FunctionIndex, Attribute::Naked))
6570 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6572 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6574 MIB = BuildMI(*thisMBB, MI, DL,
6575 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6579 MIB.setMemRefs(MMOBegin, MMOEnd);
6582 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6583 const PPCRegisterInfo *TRI =
6584 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6585 MIB.addRegMask(TRI->getNoPreservedMask());
6587 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6589 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6591 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6593 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6594 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6598 MIB = BuildMI(mainMBB, DL,
6599 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6602 if (Subtarget.isPPC64()) {
6603 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6605 .addImm(LabelOffset)
6608 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6610 .addImm(LabelOffset)
6614 MIB.setMemRefs(MMOBegin, MMOEnd);
6616 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6617 mainMBB->addSuccessor(sinkMBB);
6620 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6621 TII->get(PPC::PHI), DstReg)
6622 .addReg(mainDstReg).addMBB(mainMBB)
6623 .addReg(restoreDstReg).addMBB(thisMBB);
6625 MI->eraseFromParent();
6630 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6631 MachineBasicBlock *MBB) const {
6632 DebugLoc DL = MI->getDebugLoc();
6633 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6635 MachineFunction *MF = MBB->getParent();
6636 MachineRegisterInfo &MRI = MF->getRegInfo();
6639 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6640 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6642 MVT PVT = getPointerTy();
6643 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6644 "Invalid Pointer Size!");
6646 const TargetRegisterClass *RC =
6647 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6648 unsigned Tmp = MRI.createVirtualRegister(RC);
6649 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6650 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6651 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6652 unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
6653 (Subtarget.isSVR4ABI() &&
6654 MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
6655 PPC::R29 : PPC::R30);
6657 MachineInstrBuilder MIB;
6659 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6660 const int64_t SPOffset = 2 * PVT.getStoreSize();
6661 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6662 const int64_t BPOffset = 4 * PVT.getStoreSize();
6664 unsigned BufReg = MI->getOperand(0).getReg();
6666 // Reload FP (the jumped-to function may not have had a
6667 // frame pointer, and if so, then its r31 will be restored
6669 if (PVT == MVT::i64) {
6670 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6674 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6678 MIB.setMemRefs(MMOBegin, MMOEnd);
6681 if (PVT == MVT::i64) {
6682 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6683 .addImm(LabelOffset)
6686 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6687 .addImm(LabelOffset)
6690 MIB.setMemRefs(MMOBegin, MMOEnd);
6693 if (PVT == MVT::i64) {
6694 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6698 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6702 MIB.setMemRefs(MMOBegin, MMOEnd);
6705 if (PVT == MVT::i64) {
6706 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6710 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6714 MIB.setMemRefs(MMOBegin, MMOEnd);
6717 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
6718 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6722 MIB.setMemRefs(MMOBegin, MMOEnd);
6726 BuildMI(*MBB, MI, DL,
6727 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6728 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6730 MI->eraseFromParent();
6735 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6736 MachineBasicBlock *BB) const {
6737 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6738 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6739 return emitEHSjLjSetJmp(MI, BB);
6740 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6741 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6742 return emitEHSjLjLongJmp(MI, BB);
6745 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6747 // To "insert" these instructions we actually have to insert their
6748 // control-flow patterns.
6749 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6750 MachineFunction::iterator It = BB;
6753 MachineFunction *F = BB->getParent();
6755 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6756 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6757 MI->getOpcode() == PPC::SELECT_I4 ||
6758 MI->getOpcode() == PPC::SELECT_I8)) {
6759 SmallVector<MachineOperand, 2> Cond;
6760 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6761 MI->getOpcode() == PPC::SELECT_CC_I8)
6762 Cond.push_back(MI->getOperand(4));
6764 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
6765 Cond.push_back(MI->getOperand(1));
6767 DebugLoc dl = MI->getDebugLoc();
6768 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6769 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6770 Cond, MI->getOperand(2).getReg(),
6771 MI->getOperand(3).getReg());
6772 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6773 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6774 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6775 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6776 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
6777 MI->getOpcode() == PPC::SELECT_I4 ||
6778 MI->getOpcode() == PPC::SELECT_I8 ||
6779 MI->getOpcode() == PPC::SELECT_F4 ||
6780 MI->getOpcode() == PPC::SELECT_F8 ||
6781 MI->getOpcode() == PPC::SELECT_VRRC) {
6782 // The incoming instruction knows the destination vreg to set, the
6783 // condition code register to branch on, the true/false values to
6784 // select between, and a branch opcode to use.
6789 // cmpTY ccX, r1, r2
6791 // fallthrough --> copy0MBB
6792 MachineBasicBlock *thisMBB = BB;
6793 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6794 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6795 DebugLoc dl = MI->getDebugLoc();
6796 F->insert(It, copy0MBB);
6797 F->insert(It, sinkMBB);
6799 // Transfer the remainder of BB and its successor edges to sinkMBB.
6800 sinkMBB->splice(sinkMBB->begin(), BB,
6801 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6802 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6804 // Next, add the true and fallthrough blocks as its successors.
6805 BB->addSuccessor(copy0MBB);
6806 BB->addSuccessor(sinkMBB);
6808 if (MI->getOpcode() == PPC::SELECT_I4 ||
6809 MI->getOpcode() == PPC::SELECT_I8 ||
6810 MI->getOpcode() == PPC::SELECT_F4 ||
6811 MI->getOpcode() == PPC::SELECT_F8 ||
6812 MI->getOpcode() == PPC::SELECT_VRRC) {
6813 BuildMI(BB, dl, TII->get(PPC::BC))
6814 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6816 unsigned SelectPred = MI->getOperand(4).getImm();
6817 BuildMI(BB, dl, TII->get(PPC::BCC))
6818 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6822 // %FalseValue = ...
6823 // # fallthrough to sinkMBB
6826 // Update machine-CFG edges
6827 BB->addSuccessor(sinkMBB);
6830 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6833 BuildMI(*BB, BB->begin(), dl,
6834 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6835 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6836 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6838 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6839 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6840 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6841 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6842 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6843 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6844 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6845 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6847 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6848 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6849 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6850 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6851 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6852 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6853 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6854 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6856 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6857 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6858 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6859 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6860 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6861 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6862 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6863 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6865 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6866 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6867 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6868 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6869 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6870 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6871 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6872 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6874 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6875 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
6876 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6877 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
6878 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6879 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
6880 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6881 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
6883 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6884 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6885 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6886 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6887 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6888 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6889 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6890 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6892 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6893 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6894 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6895 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6896 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6897 BB = EmitAtomicBinary(MI, BB, false, 0);
6898 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6899 BB = EmitAtomicBinary(MI, BB, true, 0);
6901 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6902 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6903 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6905 unsigned dest = MI->getOperand(0).getReg();
6906 unsigned ptrA = MI->getOperand(1).getReg();
6907 unsigned ptrB = MI->getOperand(2).getReg();
6908 unsigned oldval = MI->getOperand(3).getReg();
6909 unsigned newval = MI->getOperand(4).getReg();
6910 DebugLoc dl = MI->getDebugLoc();
6912 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6913 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6914 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6915 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6916 F->insert(It, loop1MBB);
6917 F->insert(It, loop2MBB);
6918 F->insert(It, midMBB);
6919 F->insert(It, exitMBB);
6920 exitMBB->splice(exitMBB->begin(), BB,
6921 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6922 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6926 // fallthrough --> loopMBB
6927 BB->addSuccessor(loop1MBB);
6930 // l[wd]arx dest, ptr
6931 // cmp[wd] dest, oldval
6934 // st[wd]cx. newval, ptr
6938 // st[wd]cx. dest, ptr
6941 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6942 .addReg(ptrA).addReg(ptrB);
6943 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6944 .addReg(oldval).addReg(dest);
6945 BuildMI(BB, dl, TII->get(PPC::BCC))
6946 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6947 BB->addSuccessor(loop2MBB);
6948 BB->addSuccessor(midMBB);
6951 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6952 .addReg(newval).addReg(ptrA).addReg(ptrB);
6953 BuildMI(BB, dl, TII->get(PPC::BCC))
6954 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6955 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6956 BB->addSuccessor(loop1MBB);
6957 BB->addSuccessor(exitMBB);
6960 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6961 .addReg(dest).addReg(ptrA).addReg(ptrB);
6962 BB->addSuccessor(exitMBB);
6967 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6968 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6969 // We must use 64-bit registers for addresses when targeting 64-bit,
6970 // since we're actually doing arithmetic on them. Other registers
6972 bool is64bit = Subtarget.isPPC64();
6973 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6975 unsigned dest = MI->getOperand(0).getReg();
6976 unsigned ptrA = MI->getOperand(1).getReg();
6977 unsigned ptrB = MI->getOperand(2).getReg();
6978 unsigned oldval = MI->getOperand(3).getReg();
6979 unsigned newval = MI->getOperand(4).getReg();
6980 DebugLoc dl = MI->getDebugLoc();
6982 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6983 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6984 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6985 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6986 F->insert(It, loop1MBB);
6987 F->insert(It, loop2MBB);
6988 F->insert(It, midMBB);
6989 F->insert(It, exitMBB);
6990 exitMBB->splice(exitMBB->begin(), BB,
6991 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6992 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6994 MachineRegisterInfo &RegInfo = F->getRegInfo();
6995 const TargetRegisterClass *RC =
6996 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6997 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6998 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6999 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7000 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7001 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7002 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7003 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7004 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7005 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7006 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7007 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7008 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7009 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7010 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7012 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7013 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7016 // fallthrough --> loopMBB
7017 BB->addSuccessor(loop1MBB);
7019 // The 4-byte load must be aligned, while a char or short may be
7020 // anywhere in the word. Hence all this nasty bookkeeping code.
7021 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7022 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7023 // xori shift, shift1, 24 [16]
7024 // rlwinm ptr, ptr1, 0, 0, 29
7025 // slw newval2, newval, shift
7026 // slw oldval2, oldval,shift
7027 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7028 // slw mask, mask2, shift
7029 // and newval3, newval2, mask
7030 // and oldval3, oldval2, mask
7032 // lwarx tmpDest, ptr
7033 // and tmp, tmpDest, mask
7034 // cmpw tmp, oldval3
7037 // andc tmp2, tmpDest, mask
7038 // or tmp4, tmp2, newval3
7043 // stwcx. tmpDest, ptr
7045 // srw dest, tmpDest, shift
7046 if (ptrA != ZeroReg) {
7047 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7048 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7049 .addReg(ptrA).addReg(ptrB);
7053 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7054 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7055 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7056 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7058 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7059 .addReg(Ptr1Reg).addImm(0).addImm(61);
7061 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7062 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7063 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7064 .addReg(newval).addReg(ShiftReg);
7065 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7066 .addReg(oldval).addReg(ShiftReg);
7068 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7070 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7071 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7072 .addReg(Mask3Reg).addImm(65535);
7074 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7075 .addReg(Mask2Reg).addReg(ShiftReg);
7076 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7077 .addReg(NewVal2Reg).addReg(MaskReg);
7078 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7079 .addReg(OldVal2Reg).addReg(MaskReg);
7082 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7083 .addReg(ZeroReg).addReg(PtrReg);
7084 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7085 .addReg(TmpDestReg).addReg(MaskReg);
7086 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7087 .addReg(TmpReg).addReg(OldVal3Reg);
7088 BuildMI(BB, dl, TII->get(PPC::BCC))
7089 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7090 BB->addSuccessor(loop2MBB);
7091 BB->addSuccessor(midMBB);
7094 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7095 .addReg(TmpDestReg).addReg(MaskReg);
7096 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7097 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7098 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7099 .addReg(ZeroReg).addReg(PtrReg);
7100 BuildMI(BB, dl, TII->get(PPC::BCC))
7101 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7102 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7103 BB->addSuccessor(loop1MBB);
7104 BB->addSuccessor(exitMBB);
7107 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7108 .addReg(ZeroReg).addReg(PtrReg);
7109 BB->addSuccessor(exitMBB);
7114 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7116 } else if (MI->getOpcode() == PPC::FADDrtz) {
7117 // This pseudo performs an FADD with rounding mode temporarily forced
7118 // to round-to-zero. We emit this via custom inserter since the FPSCR
7119 // is not modeled at the SelectionDAG level.
7120 unsigned Dest = MI->getOperand(0).getReg();
7121 unsigned Src1 = MI->getOperand(1).getReg();
7122 unsigned Src2 = MI->getOperand(2).getReg();
7123 DebugLoc dl = MI->getDebugLoc();
7125 MachineRegisterInfo &RegInfo = F->getRegInfo();
7126 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7128 // Save FPSCR value.
7129 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7131 // Set rounding mode to round-to-zero.
7132 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7133 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7135 // Perform addition.
7136 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7138 // Restore FPSCR value.
7139 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7140 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7141 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7142 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7143 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7144 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7145 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7146 PPC::ANDIo8 : PPC::ANDIo;
7147 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7148 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7150 MachineRegisterInfo &RegInfo = F->getRegInfo();
7151 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7152 &PPC::GPRCRegClass :
7153 &PPC::G8RCRegClass);
7155 DebugLoc dl = MI->getDebugLoc();
7156 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7157 .addReg(MI->getOperand(1).getReg()).addImm(1);
7158 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7159 MI->getOperand(0).getReg())
7160 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7162 llvm_unreachable("Unexpected instr type to insert");
7165 MI->eraseFromParent(); // The pseudo instruction is gone now.
7169 //===----------------------------------------------------------------------===//
7170 // Target Optimization Hooks
7171 //===----------------------------------------------------------------------===//
7173 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
7174 DAGCombinerInfo &DCI) const {
7175 if (DCI.isAfterLegalizeVectorOps())
7178 EVT VT = Op.getValueType();
7180 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7181 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7182 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7183 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7185 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7186 // For the reciprocal, we need to find the zero of the function:
7187 // F(X) = A X - 1 [which has a zero at X = 1/A]
7189 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7190 // does not require additional intermediate precision]
7192 // Convergence is quadratic, so we essentially double the number of digits
7193 // correct after every iteration. The minimum architected relative
7194 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7195 // 23 digits and double has 52 digits.
7196 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7197 if (VT.getScalarType() == MVT::f64)
7200 SelectionDAG &DAG = DCI.DAG;
7204 DAG.getConstantFP(1.0, VT.getScalarType());
7205 if (VT.isVector()) {
7206 assert(VT.getVectorNumElements() == 4 &&
7207 "Unknown vector type");
7208 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7209 FPOne, FPOne, FPOne, FPOne);
7212 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
7213 DCI.AddToWorklist(Est.getNode());
7215 // Newton iterations: Est = Est + Est (1 - Arg * Est)
7216 for (int i = 0; i < Iterations; ++i) {
7217 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
7218 DCI.AddToWorklist(NewEst.getNode());
7220 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
7221 DCI.AddToWorklist(NewEst.getNode());
7223 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7224 DCI.AddToWorklist(NewEst.getNode());
7226 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
7227 DCI.AddToWorklist(Est.getNode());
7236 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
7237 DAGCombinerInfo &DCI) const {
7238 if (DCI.isAfterLegalizeVectorOps())
7241 EVT VT = Op.getValueType();
7243 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7244 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7245 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7246 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7248 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7249 // For the reciprocal sqrt, we need to find the zero of the function:
7250 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7252 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7253 // As a result, we precompute A/2 prior to the iteration loop.
7255 // Convergence is quadratic, so we essentially double the number of digits
7256 // correct after every iteration. The minimum architected relative
7257 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7258 // 23 digits and double has 52 digits.
7259 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7260 if (VT.getScalarType() == MVT::f64)
7263 SelectionDAG &DAG = DCI.DAG;
7266 SDValue FPThreeHalves =
7267 DAG.getConstantFP(1.5, VT.getScalarType());
7268 if (VT.isVector()) {
7269 assert(VT.getVectorNumElements() == 4 &&
7270 "Unknown vector type");
7271 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7272 FPThreeHalves, FPThreeHalves,
7273 FPThreeHalves, FPThreeHalves);
7276 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7277 DCI.AddToWorklist(Est.getNode());
7279 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7280 // this entire sequence requires only one FP constant.
7281 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7282 DCI.AddToWorklist(HalfArg.getNode());
7284 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7285 DCI.AddToWorklist(HalfArg.getNode());
7287 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7288 for (int i = 0; i < Iterations; ++i) {
7289 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7290 DCI.AddToWorklist(NewEst.getNode());
7292 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7293 DCI.AddToWorklist(NewEst.getNode());
7295 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7296 DCI.AddToWorklist(NewEst.getNode());
7298 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7299 DCI.AddToWorklist(Est.getNode());
7308 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7309 // not enforce equality of the chain operands.
7310 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
7311 unsigned Bytes, int Dist,
7312 SelectionDAG &DAG) {
7313 EVT VT = LS->getMemoryVT();
7314 if (VT.getSizeInBits() / 8 != Bytes)
7317 SDValue Loc = LS->getBasePtr();
7318 SDValue BaseLoc = Base->getBasePtr();
7319 if (Loc.getOpcode() == ISD::FrameIndex) {
7320 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7322 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7323 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7324 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7325 int FS = MFI->getObjectSize(FI);
7326 int BFS = MFI->getObjectSize(BFI);
7327 if (FS != BFS || FS != (int)Bytes) return false;
7328 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7332 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7333 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7336 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7337 const GlobalValue *GV1 = nullptr;
7338 const GlobalValue *GV2 = nullptr;
7339 int64_t Offset1 = 0;
7340 int64_t Offset2 = 0;
7341 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7342 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7343 if (isGA1 && isGA2 && GV1 == GV2)
7344 return Offset1 == (Offset2 + Dist*Bytes);
7348 // Return true is there is a nearyby consecutive load to the one provided
7349 // (regardless of alignment). We search up and down the chain, looking though
7350 // token factors and other loads (but nothing else). As a result, a true
7351 // results indicates that it is safe to create a new consecutive load adjacent
7352 // to the load provided.
7353 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7354 SDValue Chain = LD->getChain();
7355 EVT VT = LD->getMemoryVT();
7357 SmallSet<SDNode *, 16> LoadRoots;
7358 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7359 SmallSet<SDNode *, 16> Visited;
7361 // First, search up the chain, branching to follow all token-factor operands.
7362 // If we find a consecutive load, then we're done, otherwise, record all
7363 // nodes just above the top-level loads and token factors.
7364 while (!Queue.empty()) {
7365 SDNode *ChainNext = Queue.pop_back_val();
7366 if (!Visited.insert(ChainNext))
7369 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
7370 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7373 if (!Visited.count(ChainLD->getChain().getNode()))
7374 Queue.push_back(ChainLD->getChain().getNode());
7375 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7376 for (const SDUse &O : ChainNext->ops())
7377 if (!Visited.count(O.getNode()))
7378 Queue.push_back(O.getNode());
7380 LoadRoots.insert(ChainNext);
7383 // Second, search down the chain, starting from the top-level nodes recorded
7384 // in the first phase. These top-level nodes are the nodes just above all
7385 // loads and token factors. Starting with their uses, recursively look though
7386 // all loads (just the chain uses) and token factors to find a consecutive
7391 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7392 IE = LoadRoots.end(); I != IE; ++I) {
7393 Queue.push_back(*I);
7395 while (!Queue.empty()) {
7396 SDNode *LoadRoot = Queue.pop_back_val();
7397 if (!Visited.insert(LoadRoot))
7400 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
7401 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7404 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7405 UE = LoadRoot->use_end(); UI != UE; ++UI)
7406 if (((isa<LoadSDNode>(*UI) &&
7407 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7408 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7409 Queue.push_back(*UI);
7416 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7417 DAGCombinerInfo &DCI) const {
7418 SelectionDAG &DAG = DCI.DAG;
7421 assert(Subtarget.useCRBits() &&
7422 "Expecting to be tracking CR bits");
7423 // If we're tracking CR bits, we need to be careful that we don't have:
7424 // trunc(binary-ops(zext(x), zext(y)))
7426 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7427 // such that we're unnecessarily moving things into GPRs when it would be
7428 // better to keep them in CR bits.
7430 // Note that trunc here can be an actual i1 trunc, or can be the effective
7431 // truncation that comes from a setcc or select_cc.
7432 if (N->getOpcode() == ISD::TRUNCATE &&
7433 N->getValueType(0) != MVT::i1)
7436 if (N->getOperand(0).getValueType() != MVT::i32 &&
7437 N->getOperand(0).getValueType() != MVT::i64)
7440 if (N->getOpcode() == ISD::SETCC ||
7441 N->getOpcode() == ISD::SELECT_CC) {
7442 // If we're looking at a comparison, then we need to make sure that the
7443 // high bits (all except for the first) don't matter the result.
7445 cast<CondCodeSDNode>(N->getOperand(
7446 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7447 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7449 if (ISD::isSignedIntSetCC(CC)) {
7450 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7451 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7453 } else if (ISD::isUnsignedIntSetCC(CC)) {
7454 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7455 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7456 !DAG.MaskedValueIsZero(N->getOperand(1),
7457 APInt::getHighBitsSet(OpBits, OpBits-1)))
7460 // This is neither a signed nor an unsigned comparison, just make sure
7461 // that the high bits are equal.
7462 APInt Op1Zero, Op1One;
7463 APInt Op2Zero, Op2One;
7464 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7465 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7467 // We don't really care about what is known about the first bit (if
7468 // anything), so clear it in all masks prior to comparing them.
7469 Op1Zero.clearBit(0); Op1One.clearBit(0);
7470 Op2Zero.clearBit(0); Op2One.clearBit(0);
7472 if (Op1Zero != Op2Zero || Op1One != Op2One)
7477 // We now know that the higher-order bits are irrelevant, we just need to
7478 // make sure that all of the intermediate operations are bit operations, and
7479 // all inputs are extensions.
7480 if (N->getOperand(0).getOpcode() != ISD::AND &&
7481 N->getOperand(0).getOpcode() != ISD::OR &&
7482 N->getOperand(0).getOpcode() != ISD::XOR &&
7483 N->getOperand(0).getOpcode() != ISD::SELECT &&
7484 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7485 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7486 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7487 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7488 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7491 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7492 N->getOperand(1).getOpcode() != ISD::AND &&
7493 N->getOperand(1).getOpcode() != ISD::OR &&
7494 N->getOperand(1).getOpcode() != ISD::XOR &&
7495 N->getOperand(1).getOpcode() != ISD::SELECT &&
7496 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7497 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7498 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7499 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7500 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7503 SmallVector<SDValue, 4> Inputs;
7504 SmallVector<SDValue, 8> BinOps, PromOps;
7505 SmallPtrSet<SDNode *, 16> Visited;
7507 for (unsigned i = 0; i < 2; ++i) {
7508 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7509 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7510 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7511 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7512 isa<ConstantSDNode>(N->getOperand(i)))
7513 Inputs.push_back(N->getOperand(i));
7515 BinOps.push_back(N->getOperand(i));
7517 if (N->getOpcode() == ISD::TRUNCATE)
7521 // Visit all inputs, collect all binary operations (and, or, xor and
7522 // select) that are all fed by extensions.
7523 while (!BinOps.empty()) {
7524 SDValue BinOp = BinOps.back();
7527 if (!Visited.insert(BinOp.getNode()))
7530 PromOps.push_back(BinOp);
7532 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7533 // The condition of the select is not promoted.
7534 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7536 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7539 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7540 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7541 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7542 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7543 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7544 Inputs.push_back(BinOp.getOperand(i));
7545 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7546 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7547 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7548 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7549 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7550 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7551 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7552 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7553 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7554 BinOps.push_back(BinOp.getOperand(i));
7556 // We have an input that is not an extension or another binary
7557 // operation; we'll abort this transformation.
7563 // Make sure that this is a self-contained cluster of operations (which
7564 // is not quite the same thing as saying that everything has only one
7566 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7567 if (isa<ConstantSDNode>(Inputs[i]))
7570 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7571 UE = Inputs[i].getNode()->use_end();
7574 if (User != N && !Visited.count(User))
7577 // Make sure that we're not going to promote the non-output-value
7578 // operand(s) or SELECT or SELECT_CC.
7579 // FIXME: Although we could sometimes handle this, and it does occur in
7580 // practice that one of the condition inputs to the select is also one of
7581 // the outputs, we currently can't deal with this.
7582 if (User->getOpcode() == ISD::SELECT) {
7583 if (User->getOperand(0) == Inputs[i])
7585 } else if (User->getOpcode() == ISD::SELECT_CC) {
7586 if (User->getOperand(0) == Inputs[i] ||
7587 User->getOperand(1) == Inputs[i])
7593 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7594 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7595 UE = PromOps[i].getNode()->use_end();
7598 if (User != N && !Visited.count(User))
7601 // Make sure that we're not going to promote the non-output-value
7602 // operand(s) or SELECT or SELECT_CC.
7603 // FIXME: Although we could sometimes handle this, and it does occur in
7604 // practice that one of the condition inputs to the select is also one of
7605 // the outputs, we currently can't deal with this.
7606 if (User->getOpcode() == ISD::SELECT) {
7607 if (User->getOperand(0) == PromOps[i])
7609 } else if (User->getOpcode() == ISD::SELECT_CC) {
7610 if (User->getOperand(0) == PromOps[i] ||
7611 User->getOperand(1) == PromOps[i])
7617 // Replace all inputs with the extension operand.
7618 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7619 // Constants may have users outside the cluster of to-be-promoted nodes,
7620 // and so we need to replace those as we do the promotions.
7621 if (isa<ConstantSDNode>(Inputs[i]))
7624 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7627 // Replace all operations (these are all the same, but have a different
7628 // (i1) return type). DAG.getNode will validate that the types of
7629 // a binary operator match, so go through the list in reverse so that
7630 // we've likely promoted both operands first. Any intermediate truncations or
7631 // extensions disappear.
7632 while (!PromOps.empty()) {
7633 SDValue PromOp = PromOps.back();
7636 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7637 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7638 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7639 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7640 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7641 PromOp.getOperand(0).getValueType() != MVT::i1) {
7642 // The operand is not yet ready (see comment below).
7643 PromOps.insert(PromOps.begin(), PromOp);
7647 SDValue RepValue = PromOp.getOperand(0);
7648 if (isa<ConstantSDNode>(RepValue))
7649 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7651 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7656 switch (PromOp.getOpcode()) {
7657 default: C = 0; break;
7658 case ISD::SELECT: C = 1; break;
7659 case ISD::SELECT_CC: C = 2; break;
7662 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7663 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7664 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7665 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7666 // The to-be-promoted operands of this node have not yet been
7667 // promoted (this should be rare because we're going through the
7668 // list backward, but if one of the operands has several users in
7669 // this cluster of to-be-promoted nodes, it is possible).
7670 PromOps.insert(PromOps.begin(), PromOp);
7674 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7675 PromOp.getNode()->op_end());
7677 // If there are any constant inputs, make sure they're replaced now.
7678 for (unsigned i = 0; i < 2; ++i)
7679 if (isa<ConstantSDNode>(Ops[C+i]))
7680 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7682 DAG.ReplaceAllUsesOfValueWith(PromOp,
7683 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
7686 // Now we're left with the initial truncation itself.
7687 if (N->getOpcode() == ISD::TRUNCATE)
7688 return N->getOperand(0);
7690 // Otherwise, this is a comparison. The operands to be compared have just
7691 // changed type (to i1), but everything else is the same.
7692 return SDValue(N, 0);
7695 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7696 DAGCombinerInfo &DCI) const {
7697 SelectionDAG &DAG = DCI.DAG;
7700 // If we're tracking CR bits, we need to be careful that we don't have:
7701 // zext(binary-ops(trunc(x), trunc(y)))
7703 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
7704 // such that we're unnecessarily moving things into CR bits that can more
7705 // efficiently stay in GPRs. Note that if we're not certain that the high
7706 // bits are set as required by the final extension, we still may need to do
7707 // some masking to get the proper behavior.
7709 // This same functionality is important on PPC64 when dealing with
7710 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
7711 // the return values of functions. Because it is so similar, it is handled
7714 if (N->getValueType(0) != MVT::i32 &&
7715 N->getValueType(0) != MVT::i64)
7718 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
7719 Subtarget.useCRBits()) ||
7720 (N->getOperand(0).getValueType() == MVT::i32 &&
7721 Subtarget.isPPC64())))
7724 if (N->getOperand(0).getOpcode() != ISD::AND &&
7725 N->getOperand(0).getOpcode() != ISD::OR &&
7726 N->getOperand(0).getOpcode() != ISD::XOR &&
7727 N->getOperand(0).getOpcode() != ISD::SELECT &&
7728 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
7731 SmallVector<SDValue, 4> Inputs;
7732 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
7733 SmallPtrSet<SDNode *, 16> Visited;
7735 // Visit all inputs, collect all binary operations (and, or, xor and
7736 // select) that are all fed by truncations.
7737 while (!BinOps.empty()) {
7738 SDValue BinOp = BinOps.back();
7741 if (!Visited.insert(BinOp.getNode()))
7744 PromOps.push_back(BinOp);
7746 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7747 // The condition of the select is not promoted.
7748 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7750 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7753 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7754 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7755 Inputs.push_back(BinOp.getOperand(i));
7756 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7757 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7758 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7759 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7760 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
7761 BinOps.push_back(BinOp.getOperand(i));
7763 // We have an input that is not a truncation or another binary
7764 // operation; we'll abort this transformation.
7770 // Make sure that this is a self-contained cluster of operations (which
7771 // is not quite the same thing as saying that everything has only one
7773 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7774 if (isa<ConstantSDNode>(Inputs[i]))
7777 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7778 UE = Inputs[i].getNode()->use_end();
7781 if (User != N && !Visited.count(User))
7784 // Make sure that we're not going to promote the non-output-value
7785 // operand(s) or SELECT or SELECT_CC.
7786 // FIXME: Although we could sometimes handle this, and it does occur in
7787 // practice that one of the condition inputs to the select is also one of
7788 // the outputs, we currently can't deal with this.
7789 if (User->getOpcode() == ISD::SELECT) {
7790 if (User->getOperand(0) == Inputs[i])
7792 } else if (User->getOpcode() == ISD::SELECT_CC) {
7793 if (User->getOperand(0) == Inputs[i] ||
7794 User->getOperand(1) == Inputs[i])
7800 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7801 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7802 UE = PromOps[i].getNode()->use_end();
7805 if (User != N && !Visited.count(User))
7808 // Make sure that we're not going to promote the non-output-value
7809 // operand(s) or SELECT or SELECT_CC.
7810 // FIXME: Although we could sometimes handle this, and it does occur in
7811 // practice that one of the condition inputs to the select is also one of
7812 // the outputs, we currently can't deal with this.
7813 if (User->getOpcode() == ISD::SELECT) {
7814 if (User->getOperand(0) == PromOps[i])
7816 } else if (User->getOpcode() == ISD::SELECT_CC) {
7817 if (User->getOperand(0) == PromOps[i] ||
7818 User->getOperand(1) == PromOps[i])
7824 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
7825 bool ReallyNeedsExt = false;
7826 if (N->getOpcode() != ISD::ANY_EXTEND) {
7827 // If all of the inputs are not already sign/zero extended, then
7828 // we'll still need to do that at the end.
7829 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7830 if (isa<ConstantSDNode>(Inputs[i]))
7834 Inputs[i].getOperand(0).getValueSizeInBits();
7835 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
7837 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
7838 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
7839 APInt::getHighBitsSet(OpBits,
7840 OpBits-PromBits))) ||
7841 (N->getOpcode() == ISD::SIGN_EXTEND &&
7842 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
7843 (OpBits-(PromBits-1)))) {
7844 ReallyNeedsExt = true;
7850 // Replace all inputs, either with the truncation operand, or a
7851 // truncation or extension to the final output type.
7852 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7853 // Constant inputs need to be replaced with the to-be-promoted nodes that
7854 // use them because they might have users outside of the cluster of
7856 if (isa<ConstantSDNode>(Inputs[i]))
7859 SDValue InSrc = Inputs[i].getOperand(0);
7860 if (Inputs[i].getValueType() == N->getValueType(0))
7861 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
7862 else if (N->getOpcode() == ISD::SIGN_EXTEND)
7863 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7864 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
7865 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7866 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7867 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
7869 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7870 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
7873 // Replace all operations (these are all the same, but have a different
7874 // (promoted) return type). DAG.getNode will validate that the types of
7875 // a binary operator match, so go through the list in reverse so that
7876 // we've likely promoted both operands first.
7877 while (!PromOps.empty()) {
7878 SDValue PromOp = PromOps.back();
7882 switch (PromOp.getOpcode()) {
7883 default: C = 0; break;
7884 case ISD::SELECT: C = 1; break;
7885 case ISD::SELECT_CC: C = 2; break;
7888 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7889 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
7890 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7891 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
7892 // The to-be-promoted operands of this node have not yet been
7893 // promoted (this should be rare because we're going through the
7894 // list backward, but if one of the operands has several users in
7895 // this cluster of to-be-promoted nodes, it is possible).
7896 PromOps.insert(PromOps.begin(), PromOp);
7900 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7901 PromOp.getNode()->op_end());
7903 // If this node has constant inputs, then they'll need to be promoted here.
7904 for (unsigned i = 0; i < 2; ++i) {
7905 if (!isa<ConstantSDNode>(Ops[C+i]))
7907 if (Ops[C+i].getValueType() == N->getValueType(0))
7910 if (N->getOpcode() == ISD::SIGN_EXTEND)
7911 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7912 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7913 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7915 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7918 DAG.ReplaceAllUsesOfValueWith(PromOp,
7919 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
7922 // Now we're left with the initial extension itself.
7923 if (!ReallyNeedsExt)
7924 return N->getOperand(0);
7926 // To zero extend, just mask off everything except for the first bit (in the
7928 if (N->getOpcode() == ISD::ZERO_EXTEND)
7929 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
7930 DAG.getConstant(APInt::getLowBitsSet(
7931 N->getValueSizeInBits(0), PromBits),
7932 N->getValueType(0)));
7934 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
7935 "Invalid extension type");
7936 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
7938 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
7939 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
7940 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
7941 N->getOperand(0), ShiftCst), ShiftCst);
7944 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
7945 DAGCombinerInfo &DCI) const {
7946 const TargetMachine &TM = getTargetMachine();
7947 SelectionDAG &DAG = DCI.DAG;
7949 switch (N->getOpcode()) {
7952 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7953 if (C->isNullValue()) // 0 << V -> 0.
7954 return N->getOperand(0);
7958 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7959 if (C->isNullValue()) // 0 >>u V -> 0.
7960 return N->getOperand(0);
7964 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7965 if (C->isNullValue() || // 0 >>s V -> 0.
7966 C->isAllOnesValue()) // -1 >>s V -> -1.
7967 return N->getOperand(0);
7970 case ISD::SIGN_EXTEND:
7971 case ISD::ZERO_EXTEND:
7972 case ISD::ANY_EXTEND:
7973 return DAGCombineExtBoolTrunc(N, DCI);
7976 case ISD::SELECT_CC:
7977 return DAGCombineTruncBoolExt(N, DCI);
7979 assert(TM.Options.UnsafeFPMath &&
7980 "Reciprocal estimates require UnsafeFPMath");
7982 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
7984 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
7986 DCI.AddToWorklist(RV.getNode());
7987 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7988 N->getOperand(0), RV);
7990 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
7991 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7993 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7996 DCI.AddToWorklist(RV.getNode());
7997 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
7998 N->getValueType(0), RV);
7999 DCI.AddToWorklist(RV.getNode());
8000 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8001 N->getOperand(0), RV);
8003 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
8004 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
8006 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
8009 DCI.AddToWorklist(RV.getNode());
8010 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
8011 N->getValueType(0), RV,
8012 N->getOperand(1).getOperand(1));
8013 DCI.AddToWorklist(RV.getNode());
8014 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8015 N->getOperand(0), RV);
8019 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
8021 DCI.AddToWorklist(RV.getNode());
8022 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8023 N->getOperand(0), RV);
8029 assert(TM.Options.UnsafeFPMath &&
8030 "Reciprocal estimates require UnsafeFPMath");
8032 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
8034 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
8036 DCI.AddToWorklist(RV.getNode());
8037 RV = DAGCombineFastRecip(RV, DCI);
8039 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
8040 // this case and force the answer to 0.
8042 EVT VT = RV.getValueType();
8044 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
8045 if (VT.isVector()) {
8046 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
8047 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
8051 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
8052 N->getOperand(0), Zero, ISD::SETEQ);
8053 DCI.AddToWorklist(ZeroCmp.getNode());
8054 DCI.AddToWorklist(RV.getNode());
8056 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
8064 case ISD::SINT_TO_FP:
8065 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
8066 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8067 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8068 // We allow the src/dst to be either f32/f64, but the intermediate
8069 // type must be i64.
8070 if (N->getOperand(0).getValueType() == MVT::i64 &&
8071 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
8072 SDValue Val = N->getOperand(0).getOperand(0);
8073 if (Val.getValueType() == MVT::f32) {
8074 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8075 DCI.AddToWorklist(Val.getNode());
8078 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8079 DCI.AddToWorklist(Val.getNode());
8080 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8081 DCI.AddToWorklist(Val.getNode());
8082 if (N->getValueType(0) == MVT::f32) {
8083 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8084 DAG.getIntPtrConstant(0));
8085 DCI.AddToWorklist(Val.getNode());
8088 } else if (N->getOperand(0).getValueType() == MVT::i32) {
8089 // If the intermediate type is i32, we can avoid the load/store here
8096 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8097 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8098 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8099 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8100 N->getOperand(1).getValueType() == MVT::i32 &&
8101 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8102 SDValue Val = N->getOperand(1).getOperand(0);
8103 if (Val.getValueType() == MVT::f32) {
8104 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8105 DCI.AddToWorklist(Val.getNode());
8107 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8108 DCI.AddToWorklist(Val.getNode());
8111 N->getOperand(0), Val, N->getOperand(2),
8112 DAG.getValueType(N->getOperand(1).getValueType())
8115 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8116 DAG.getVTList(MVT::Other), Ops,
8117 cast<StoreSDNode>(N)->getMemoryVT(),
8118 cast<StoreSDNode>(N)->getMemOperand());
8119 DCI.AddToWorklist(Val.getNode());
8123 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8124 if (cast<StoreSDNode>(N)->isUnindexed() &&
8125 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8126 N->getOperand(1).getNode()->hasOneUse() &&
8127 (N->getOperand(1).getValueType() == MVT::i32 ||
8128 N->getOperand(1).getValueType() == MVT::i16 ||
8129 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8130 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8131 N->getOperand(1).getValueType() == MVT::i64))) {
8132 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8133 // Do an any-extend to 32-bits if this is a half-word input.
8134 if (BSwapOp.getValueType() == MVT::i16)
8135 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8138 N->getOperand(0), BSwapOp, N->getOperand(2),
8139 DAG.getValueType(N->getOperand(1).getValueType())
8142 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8143 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8144 cast<StoreSDNode>(N)->getMemOperand());
8148 LoadSDNode *LD = cast<LoadSDNode>(N);
8149 EVT VT = LD->getValueType(0);
8150 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8151 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8152 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8153 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8154 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8155 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8156 LD->getAlignment() < ABIAlignment) {
8157 // This is a type-legal unaligned Altivec load.
8158 SDValue Chain = LD->getChain();
8159 SDValue Ptr = LD->getBasePtr();
8160 bool isLittleEndian = Subtarget.isLittleEndian();
8162 // This implements the loading of unaligned vectors as described in
8163 // the venerable Apple Velocity Engine overview. Specifically:
8164 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8165 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8167 // The general idea is to expand a sequence of one or more unaligned
8168 // loads into an alignment-based permutation-control instruction (lvsl
8169 // or lvsr), a series of regular vector loads (which always truncate
8170 // their input address to an aligned address), and a series of
8171 // permutations. The results of these permutations are the requested
8172 // loaded values. The trick is that the last "extra" load is not taken
8173 // from the address you might suspect (sizeof(vector) bytes after the
8174 // last requested load), but rather sizeof(vector) - 1 bytes after the
8175 // last requested vector. The point of this is to avoid a page fault if
8176 // the base address happened to be aligned. This works because if the
8177 // base address is aligned, then adding less than a full vector length
8178 // will cause the last vector in the sequence to be (re)loaded.
8179 // Otherwise, the next vector will be fetched as you might suspect was
8182 // We might be able to reuse the permutation generation from
8183 // a different base address offset from this one by an aligned amount.
8184 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8185 // optimization later.
8186 Intrinsic::ID Intr = (isLittleEndian ?
8187 Intrinsic::ppc_altivec_lvsr :
8188 Intrinsic::ppc_altivec_lvsl);
8189 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8191 // Refine the alignment of the original load (a "new" load created here
8192 // which was identical to the first except for the alignment would be
8193 // merged with the existing node regardless).
8194 MachineFunction &MF = DAG.getMachineFunction();
8195 MachineMemOperand *MMO =
8196 MF.getMachineMemOperand(LD->getPointerInfo(),
8197 LD->getMemOperand()->getFlags(),
8198 LD->getMemoryVT().getStoreSize(),
8200 LD->refineAlignment(MMO);
8201 SDValue BaseLoad = SDValue(LD, 0);
8203 // Note that the value of IncOffset (which is provided to the next
8204 // load's pointer info offset value, and thus used to calculate the
8205 // alignment), and the value of IncValue (which is actually used to
8206 // increment the pointer value) are different! This is because we
8207 // require the next load to appear to be aligned, even though it
8208 // is actually offset from the base pointer by a lesser amount.
8209 int IncOffset = VT.getSizeInBits() / 8;
8210 int IncValue = IncOffset;
8212 // Walk (both up and down) the chain looking for another load at the real
8213 // (aligned) offset (the alignment of the other load does not matter in
8214 // this case). If found, then do not use the offset reduction trick, as
8215 // that will prevent the loads from being later combined (as they would
8216 // otherwise be duplicates).
8217 if (!findConsecutiveLoad(LD, DAG))
8220 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8221 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8224 DAG.getLoad(VT, dl, Chain, Ptr,
8225 LD->getPointerInfo().getWithOffset(IncOffset),
8226 LD->isVolatile(), LD->isNonTemporal(),
8227 LD->isInvariant(), ABIAlignment);
8229 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8230 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8232 if (BaseLoad.getValueType() != MVT::v4i32)
8233 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
8235 if (ExtraLoad.getValueType() != MVT::v4i32)
8236 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
8238 // Because vperm has a big-endian bias, we must reverse the order
8239 // of the input vectors and complement the permute control vector
8240 // when generating little endian code. We have already handled the
8241 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8242 // and ExtraLoad here.
8245 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8246 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8248 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8249 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8251 if (VT != MVT::v4i32)
8252 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8254 // Now we need to be really careful about how we update the users of the
8255 // original load. We cannot just call DCI.CombineTo (or
8256 // DAG.ReplaceAllUsesWith for that matter), because the load still has
8257 // uses created here (the permutation for example) that need to stay.
8258 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
8260 SDUse &Use = UI.getUse();
8262 // Note: BaseLoad is checked here because it might not be N, but a
8264 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
8265 User == TF.getNode() || Use.getResNo() > 1) {
8270 SDValue To = Use.getResNo() ? TF : Perm;
8273 SmallVector<SDValue, 8> Ops;
8274 for (const SDUse &O : User->ops()) {
8281 DAG.UpdateNodeOperands(User, Ops);
8284 return SDValue(N, 0);
8288 case ISD::INTRINSIC_WO_CHAIN: {
8289 bool isLittleEndian = Subtarget.isLittleEndian();
8290 Intrinsic::ID Intr = (isLittleEndian ?
8291 Intrinsic::ppc_altivec_lvsr :
8292 Intrinsic::ppc_altivec_lvsl);
8293 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8294 N->getOperand(1)->getOpcode() == ISD::ADD) {
8295 SDValue Add = N->getOperand(1);
8297 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8298 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8299 Add.getValueType().getScalarType().getSizeInBits()))) {
8300 SDNode *BasePtr = Add->getOperand(0).getNode();
8301 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8302 UE = BasePtr->use_end(); UI != UE; ++UI) {
8303 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8304 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8306 // We've found another LVSL/LVSR, and this address is an aligned
8307 // multiple of that one. The results will be the same, so use the
8308 // one we've just found instead.
8310 return SDValue(*UI, 0);
8319 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8320 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8321 N->getOperand(0).hasOneUse() &&
8322 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8323 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8324 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8325 N->getValueType(0) == MVT::i64))) {
8326 SDValue Load = N->getOperand(0);
8327 LoadSDNode *LD = cast<LoadSDNode>(Load);
8328 // Create the byte-swapping load.
8330 LD->getChain(), // Chain
8331 LD->getBasePtr(), // Ptr
8332 DAG.getValueType(N->getValueType(0)) // VT
8335 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8336 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8337 MVT::i64 : MVT::i32, MVT::Other),
8338 Ops, LD->getMemoryVT(), LD->getMemOperand());
8340 // If this is an i16 load, insert the truncate.
8341 SDValue ResVal = BSLoad;
8342 if (N->getValueType(0) == MVT::i16)
8343 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8345 // First, combine the bswap away. This makes the value produced by the
8347 DCI.CombineTo(N, ResVal);
8349 // Next, combine the load away, we give it a bogus result value but a real
8350 // chain result. The result value is dead because the bswap is dead.
8351 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8353 // Return N so it doesn't get rechecked!
8354 return SDValue(N, 0);
8358 case PPCISD::VCMP: {
8359 // If a VCMPo node already exists with exactly the same operands as this
8360 // node, use its result instead of this node (VCMPo computes both a CR6 and
8361 // a normal output).
8363 if (!N->getOperand(0).hasOneUse() &&
8364 !N->getOperand(1).hasOneUse() &&
8365 !N->getOperand(2).hasOneUse()) {
8367 // Scan all of the users of the LHS, looking for VCMPo's that match.
8368 SDNode *VCMPoNode = nullptr;
8370 SDNode *LHSN = N->getOperand(0).getNode();
8371 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8373 if (UI->getOpcode() == PPCISD::VCMPo &&
8374 UI->getOperand(1) == N->getOperand(1) &&
8375 UI->getOperand(2) == N->getOperand(2) &&
8376 UI->getOperand(0) == N->getOperand(0)) {
8381 // If there is no VCMPo node, or if the flag value has a single use, don't
8383 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8386 // Look at the (necessarily single) use of the flag value. If it has a
8387 // chain, this transformation is more complex. Note that multiple things
8388 // could use the value result, which we should ignore.
8389 SDNode *FlagUser = nullptr;
8390 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8391 FlagUser == nullptr; ++UI) {
8392 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8394 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8395 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8402 // If the user is a MFOCRF instruction, we know this is safe.
8403 // Otherwise we give up for right now.
8404 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8405 return SDValue(VCMPoNode, 0);
8410 SDValue Cond = N->getOperand(1);
8411 SDValue Target = N->getOperand(2);
8413 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8414 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8415 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8417 // We now need to make the intrinsic dead (it cannot be instruction
8419 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8420 assert(Cond.getNode()->hasOneUse() &&
8421 "Counter decrement has more than one use");
8423 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8424 N->getOperand(0), Target);
8429 // If this is a branch on an altivec predicate comparison, lower this so
8430 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8431 // lowering is done pre-legalize, because the legalizer lowers the predicate
8432 // compare down to code that is difficult to reassemble.
8433 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8434 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8436 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8437 // value. If so, pass-through the AND to get to the intrinsic.
8438 if (LHS.getOpcode() == ISD::AND &&
8439 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8440 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8441 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8442 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8443 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8445 LHS = LHS.getOperand(0);
8447 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8448 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8449 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8450 isa<ConstantSDNode>(RHS)) {
8451 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8452 "Counter decrement comparison is not EQ or NE");
8454 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8455 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8456 (CC == ISD::SETNE && !Val);
8458 // We now need to make the intrinsic dead (it cannot be instruction
8460 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8461 assert(LHS.getNode()->hasOneUse() &&
8462 "Counter decrement has more than one use");
8464 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8465 N->getOperand(0), N->getOperand(4));
8471 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8472 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8473 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8474 assert(isDot && "Can't compare against a vector result!");
8476 // If this is a comparison against something other than 0/1, then we know
8477 // that the condition is never/always true.
8478 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8479 if (Val != 0 && Val != 1) {
8480 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8481 return N->getOperand(0);
8482 // Always !=, turn it into an unconditional branch.
8483 return DAG.getNode(ISD::BR, dl, MVT::Other,
8484 N->getOperand(0), N->getOperand(4));
8487 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8489 // Create the PPCISD altivec 'dot' comparison node.
8491 LHS.getOperand(2), // LHS of compare
8492 LHS.getOperand(3), // RHS of compare
8493 DAG.getConstant(CompareOpc, MVT::i32)
8495 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8496 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8498 // Unpack the result based on how the target uses it.
8499 PPC::Predicate CompOpc;
8500 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8501 default: // Can't happen, don't crash on invalid number though.
8502 case 0: // Branch on the value of the EQ bit of CR6.
8503 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8505 case 1: // Branch on the inverted value of the EQ bit of CR6.
8506 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8508 case 2: // Branch on the value of the LT bit of CR6.
8509 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8511 case 3: // Branch on the inverted value of the LT bit of CR6.
8512 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8516 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8517 DAG.getConstant(CompOpc, MVT::i32),
8518 DAG.getRegister(PPC::CR6, MVT::i32),
8519 N->getOperand(4), CompNode.getValue(1));
8528 //===----------------------------------------------------------------------===//
8529 // Inline Assembly Support
8530 //===----------------------------------------------------------------------===//
8532 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8535 const SelectionDAG &DAG,
8536 unsigned Depth) const {
8537 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8538 switch (Op.getOpcode()) {
8540 case PPCISD::LBRX: {
8541 // lhbrx is known to have the top bits cleared out.
8542 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8543 KnownZero = 0xFFFF0000;
8546 case ISD::INTRINSIC_WO_CHAIN: {
8547 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8549 case Intrinsic::ppc_altivec_vcmpbfp_p:
8550 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8551 case Intrinsic::ppc_altivec_vcmpequb_p:
8552 case Intrinsic::ppc_altivec_vcmpequh_p:
8553 case Intrinsic::ppc_altivec_vcmpequw_p:
8554 case Intrinsic::ppc_altivec_vcmpgefp_p:
8555 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8556 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8557 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8558 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8559 case Intrinsic::ppc_altivec_vcmpgtub_p:
8560 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8561 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8562 KnownZero = ~1U; // All bits but the low one are known to be zero.
8570 /// getConstraintType - Given a constraint, return the type of
8571 /// constraint it is for this target.
8572 PPCTargetLowering::ConstraintType
8573 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8574 if (Constraint.size() == 1) {
8575 switch (Constraint[0]) {
8582 return C_RegisterClass;
8584 // FIXME: While Z does indicate a memory constraint, it specifically
8585 // indicates an r+r address (used in conjunction with the 'y' modifier
8586 // in the replacement string). Currently, we're forcing the base
8587 // register to be r0 in the asm printer (which is interpreted as zero)
8588 // and forming the complete address in the second register. This is
8592 } else if (Constraint == "wc") { // individual CR bits.
8593 return C_RegisterClass;
8594 } else if (Constraint == "wa" || Constraint == "wd" ||
8595 Constraint == "wf" || Constraint == "ws") {
8596 return C_RegisterClass; // VSX registers.
8598 return TargetLowering::getConstraintType(Constraint);
8601 /// Examine constraint type and operand type and determine a weight value.
8602 /// This object must already have been set up with the operand type
8603 /// and the current alternative constraint selected.
8604 TargetLowering::ConstraintWeight
8605 PPCTargetLowering::getSingleConstraintMatchWeight(
8606 AsmOperandInfo &info, const char *constraint) const {
8607 ConstraintWeight weight = CW_Invalid;
8608 Value *CallOperandVal = info.CallOperandVal;
8609 // If we don't have a value, we can't do a match,
8610 // but allow it at the lowest weight.
8611 if (!CallOperandVal)
8613 Type *type = CallOperandVal->getType();
8615 // Look at the constraint type.
8616 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8617 return CW_Register; // an individual CR bit.
8618 else if ((StringRef(constraint) == "wa" ||
8619 StringRef(constraint) == "wd" ||
8620 StringRef(constraint) == "wf") &&
8623 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8626 switch (*constraint) {
8628 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8631 if (type->isIntegerTy())
8632 weight = CW_Register;
8635 if (type->isFloatTy())
8636 weight = CW_Register;
8639 if (type->isDoubleTy())
8640 weight = CW_Register;
8643 if (type->isVectorTy())
8644 weight = CW_Register;
8647 weight = CW_Register;
8656 std::pair<unsigned, const TargetRegisterClass*>
8657 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8659 if (Constraint.size() == 1) {
8660 // GCC RS6000 Constraint Letters
8661 switch (Constraint[0]) {
8663 if (VT == MVT::i64 && Subtarget.isPPC64())
8664 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8665 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8667 if (VT == MVT::i64 && Subtarget.isPPC64())
8668 return std::make_pair(0U, &PPC::G8RCRegClass);
8669 return std::make_pair(0U, &PPC::GPRCRegClass);
8671 if (VT == MVT::f32 || VT == MVT::i32)
8672 return std::make_pair(0U, &PPC::F4RCRegClass);
8673 if (VT == MVT::f64 || VT == MVT::i64)
8674 return std::make_pair(0U, &PPC::F8RCRegClass);
8677 return std::make_pair(0U, &PPC::VRRCRegClass);
8679 return std::make_pair(0U, &PPC::CRRCRegClass);
8681 } else if (Constraint == "wc") { // an individual CR bit.
8682 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8683 } else if (Constraint == "wa" || Constraint == "wd" ||
8684 Constraint == "wf") {
8685 return std::make_pair(0U, &PPC::VSRCRegClass);
8686 } else if (Constraint == "ws") {
8687 return std::make_pair(0U, &PPC::VSFRCRegClass);
8690 std::pair<unsigned, const TargetRegisterClass*> R =
8691 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8693 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8694 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8695 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8697 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8698 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8699 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
8700 PPC::GPRCRegClass.contains(R.first)) {
8701 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
8702 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8703 PPC::sub_32, &PPC::G8RCRegClass),
8704 &PPC::G8RCRegClass);
8711 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8712 /// vector. If it is invalid, don't add anything to Ops.
8713 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8714 std::string &Constraint,
8715 std::vector<SDValue>&Ops,
8716 SelectionDAG &DAG) const {
8719 // Only support length 1 constraints.
8720 if (Constraint.length() > 1) return;
8722 char Letter = Constraint[0];
8733 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
8734 if (!CST) return; // Must be an immediate to match.
8735 unsigned Value = CST->getZExtValue();
8737 default: llvm_unreachable("Unknown constraint letter!");
8738 case 'I': // "I" is a signed 16-bit constant.
8739 if ((short)Value == (int)Value)
8740 Result = DAG.getTargetConstant(Value, Op.getValueType());
8742 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
8743 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
8744 if ((short)Value == 0)
8745 Result = DAG.getTargetConstant(Value, Op.getValueType());
8747 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
8748 if ((Value >> 16) == 0)
8749 Result = DAG.getTargetConstant(Value, Op.getValueType());
8751 case 'M': // "M" is a constant that is greater than 31.
8753 Result = DAG.getTargetConstant(Value, Op.getValueType());
8755 case 'N': // "N" is a positive constant that is an exact power of two.
8756 if ((int)Value > 0 && isPowerOf2_32(Value))
8757 Result = DAG.getTargetConstant(Value, Op.getValueType());
8759 case 'O': // "O" is the constant zero.
8761 Result = DAG.getTargetConstant(Value, Op.getValueType());
8763 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
8764 if ((short)-Value == (int)-Value)
8765 Result = DAG.getTargetConstant(Value, Op.getValueType());
8772 if (Result.getNode()) {
8773 Ops.push_back(Result);
8777 // Handle standard constraint letters.
8778 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8781 // isLegalAddressingMode - Return true if the addressing mode represented
8782 // by AM is legal for this target, for a load/store of the specified type.
8783 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
8785 // FIXME: PPC does not allow r+i addressing modes for vectors!
8787 // PPC allows a sign-extended 16-bit immediate field.
8788 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
8791 // No global is ever allowed as a base.
8795 // PPC only support r+r,
8797 case 0: // "r+i" or just "i", depending on HasBaseReg.
8800 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
8802 // Otherwise we have r+r or r+i.
8805 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
8807 // Allow 2*r as r+r.
8810 // No other scales are supported.
8817 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
8818 SelectionDAG &DAG) const {
8819 MachineFunction &MF = DAG.getMachineFunction();
8820 MachineFrameInfo *MFI = MF.getFrameInfo();
8821 MFI->setReturnAddressIsTaken(true);
8823 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
8827 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8829 // Make sure the function does not optimize away the store of the RA to
8831 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
8832 FuncInfo->setLRStoreRequired();
8833 bool isPPC64 = Subtarget.isPPC64();
8834 bool isDarwinABI = Subtarget.isDarwinABI();
8837 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
8840 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
8841 isPPC64? MVT::i64 : MVT::i32);
8842 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8843 DAG.getNode(ISD::ADD, dl, getPointerTy(),
8845 MachinePointerInfo(), false, false, false, 0);
8848 // Just load the return address off the stack.
8849 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
8850 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8851 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
8854 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
8855 SelectionDAG &DAG) const {
8857 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8859 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
8860 bool isPPC64 = PtrVT == MVT::i64;
8862 MachineFunction &MF = DAG.getMachineFunction();
8863 MachineFrameInfo *MFI = MF.getFrameInfo();
8864 MFI->setFrameAddressIsTaken(true);
8866 // Naked functions never have a frame pointer, and so we use r1. For all
8867 // other functions, this decision must be delayed until during PEI.
8869 if (MF.getFunction()->getAttributes().hasAttribute(
8870 AttributeSet::FunctionIndex, Attribute::Naked))
8871 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
8873 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
8875 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
8878 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
8879 FrameAddr, MachinePointerInfo(), false, false,
8884 // FIXME? Maybe this could be a TableGen attribute on some registers and
8885 // this table could be generated automatically from RegInfo.
8886 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
8888 bool isPPC64 = Subtarget.isPPC64();
8889 bool isDarwinABI = Subtarget.isDarwinABI();
8891 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
8892 (!isPPC64 && VT != MVT::i32))
8893 report_fatal_error("Invalid register global variable type");
8895 bool is64Bit = isPPC64 && VT == MVT::i64;
8896 unsigned Reg = StringSwitch<unsigned>(RegName)
8897 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
8898 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
8899 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
8900 (is64Bit ? PPC::X13 : PPC::R13))
8905 report_fatal_error("Invalid register name global variable");
8909 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
8910 // The PowerPC target isn't yet aware of offsets.
8914 /// getOptimalMemOpType - Returns the target specific optimal type for load
8915 /// and store operations as a result of memset, memcpy, and memmove
8916 /// lowering. If DstAlign is zero that means it's safe to destination
8917 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
8918 /// means there isn't a need to check it against alignment requirement,
8919 /// probably because the source does not need to be loaded. If 'IsMemset' is
8920 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
8921 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
8922 /// source is constant so it does not need to be loaded.
8923 /// It returns EVT::Other if the type should be determined using generic
8924 /// target-independent logic.
8925 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
8926 unsigned DstAlign, unsigned SrcAlign,
8927 bool IsMemset, bool ZeroMemset,
8929 MachineFunction &MF) const {
8930 if (Subtarget.isPPC64()) {
8937 /// \brief Returns true if it is beneficial to convert a load of a constant
8938 /// to just the constant itself.
8939 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
8941 assert(Ty->isIntegerTy());
8943 unsigned BitSize = Ty->getPrimitiveSizeInBits();
8944 if (BitSize == 0 || BitSize > 64)
8949 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
8950 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
8952 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
8953 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
8954 return NumBits1 == 64 && NumBits2 == 32;
8957 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
8958 if (!VT1.isInteger() || !VT2.isInteger())
8960 unsigned NumBits1 = VT1.getSizeInBits();
8961 unsigned NumBits2 = VT2.getSizeInBits();
8962 return NumBits1 == 64 && NumBits2 == 32;
8965 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
8966 return isInt<16>(Imm) || isUInt<16>(Imm);
8969 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
8970 return isInt<16>(Imm) || isUInt<16>(Imm);
8973 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
8976 if (DisablePPCUnaligned)
8979 // PowerPC supports unaligned memory access for simple non-vector types.
8980 // Although accessing unaligned addresses is not as efficient as accessing
8981 // aligned addresses, it is generally more efficient than manual expansion,
8982 // and generally only traps for software emulation when crossing page
8988 if (VT.getSimpleVT().isVector()) {
8989 if (Subtarget.hasVSX()) {
8990 if (VT != MVT::v2f64 && VT != MVT::v2i64)
8997 if (VT == MVT::ppcf128)
9006 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9007 VT = VT.getScalarType();
9012 switch (VT.getSimpleVT().SimpleTy) {
9024 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
9025 EVT VT , unsigned DefinedValues) const {
9026 if (VT == MVT::v2i64)
9029 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9032 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9033 if (DisableILPPref || Subtarget.enableMachineScheduler())
9034 return TargetLowering::getSchedulingPreference(N);
9039 // Create a fast isel object.
9041 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9042 const TargetLibraryInfo *LibInfo) const {
9043 return PPC::createFastISel(FuncInfo, LibInfo);