1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
45 // FIXME: Remove this once soft-float is supported.
46 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
47 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
49 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
50 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
52 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
53 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
55 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
56 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
58 // FIXME: Remove this once the bug has been fixed!
59 extern cl::opt<bool> ANDIGlueBug;
61 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
62 const PPCSubtarget &STI)
63 : TargetLowering(TM), Subtarget(STI) {
64 // Use _setjmp/_longjmp instead of setjmp/longjmp.
65 setUseUnderscoreSetJmp(true);
66 setUseUnderscoreLongJmp(true);
68 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
69 // arguments are at least 4/8 bytes aligned.
70 bool isPPC64 = Subtarget.isPPC64();
71 setMinStackArgumentAlignment(isPPC64 ? 8:4);
73 // Set up the register classes.
74 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
75 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
76 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
78 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
79 for (MVT VT : MVT::integer_valuetypes()) {
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
84 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
86 // PowerPC has pre-inc load and store's.
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
102 if (Subtarget.useCRBits()) {
103 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
105 if (isPPC64 || Subtarget.hasFPCVT()) {
106 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
107 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
108 isPPC64 ? MVT::i64 : MVT::i32);
109 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
110 AddPromotedToType(ISD::UINT_TO_FP, MVT::i1,
111 isPPC64 ? MVT::i64 : MVT::i32);
113 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
114 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
117 // PowerPC does not support direct load / store of condition registers
118 setOperationAction(ISD::LOAD, MVT::i1, Custom);
119 setOperationAction(ISD::STORE, MVT::i1, Custom);
121 // FIXME: Remove this once the ANDI glue bug is fixed:
123 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
125 for (MVT VT : MVT::integer_valuetypes()) {
126 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
127 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
128 setTruncStoreAction(VT, MVT::i1, Expand);
131 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
134 // This is used in the ppcf128->int sequence. Note it has different semantics
135 // from FP_ROUND: that rounds to nearest, this rounds to zero.
136 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
138 // We do not currently implement these libm ops for PowerPC.
139 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
144 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
146 // PowerPC has no SREM/UREM instructions
147 setOperationAction(ISD::SREM, MVT::i32, Expand);
148 setOperationAction(ISD::UREM, MVT::i32, Expand);
149 setOperationAction(ISD::SREM, MVT::i64, Expand);
150 setOperationAction(ISD::UREM, MVT::i64, Expand);
152 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
153 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
155 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
157 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
159 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
160 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
162 // We don't support sin/cos/sqrt/fmod/pow
163 setOperationAction(ISD::FSIN , MVT::f64, Expand);
164 setOperationAction(ISD::FCOS , MVT::f64, Expand);
165 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
166 setOperationAction(ISD::FREM , MVT::f64, Expand);
167 setOperationAction(ISD::FPOW , MVT::f64, Expand);
168 setOperationAction(ISD::FMA , MVT::f64, Legal);
169 setOperationAction(ISD::FSIN , MVT::f32, Expand);
170 setOperationAction(ISD::FCOS , MVT::f32, Expand);
171 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
172 setOperationAction(ISD::FREM , MVT::f32, Expand);
173 setOperationAction(ISD::FPOW , MVT::f32, Expand);
174 setOperationAction(ISD::FMA , MVT::f32, Legal);
176 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
178 // If we're enabling GP optimizations, use hardware square root
179 if (!Subtarget.hasFSQRT() &&
180 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
182 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
184 if (!Subtarget.hasFSQRT() &&
185 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
186 Subtarget.hasFRES()))
187 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
189 if (Subtarget.hasFCPSGN()) {
190 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
191 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
194 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
197 if (Subtarget.hasFPRND()) {
198 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
199 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
200 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
201 setOperationAction(ISD::FROUND, MVT::f64, Legal);
203 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
204 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
205 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
206 setOperationAction(ISD::FROUND, MVT::f32, Legal);
209 // PowerPC does not have BSWAP, CTPOP or CTTZ
210 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
212 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
214 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
216 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
217 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
219 if (Subtarget.hasPOPCNTD()) {
220 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
221 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
223 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
224 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
227 // PowerPC does not have ROTR
228 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
229 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
231 if (!Subtarget.useCRBits()) {
232 // PowerPC does not have Select
233 setOperationAction(ISD::SELECT, MVT::i32, Expand);
234 setOperationAction(ISD::SELECT, MVT::i64, Expand);
235 setOperationAction(ISD::SELECT, MVT::f32, Expand);
236 setOperationAction(ISD::SELECT, MVT::f64, Expand);
239 // PowerPC wants to turn select_cc of FP into fsel when possible.
240 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
241 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
243 // PowerPC wants to optimize integer setcc a bit
244 if (!Subtarget.useCRBits())
245 setOperationAction(ISD::SETCC, MVT::i32, Custom);
247 // PowerPC does not have BRCOND which requires SetCC
248 if (!Subtarget.useCRBits())
249 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
251 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
253 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
254 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
256 // PowerPC does not have [U|S]INT_TO_FP
257 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
258 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
262 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
263 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
265 // We cannot sextinreg(i1). Expand to shifts.
266 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
268 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
269 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
270 // support continuation, user-level threading, and etc.. As a result, no
271 // other SjLj exception interfaces are implemented and please don't build
272 // your own exception handling based on them.
273 // LLVM/Clang supports zero-cost DWARF exception handling.
274 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
275 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
277 // We want to legalize GlobalAddress and ConstantPool nodes into the
278 // appropriate instructions to materialize the address.
279 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
280 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
281 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
282 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
283 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
284 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
285 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
286 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
287 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
288 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
291 setOperationAction(ISD::TRAP, MVT::Other, Legal);
293 // TRAMPOLINE is custom lowered.
294 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
295 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
297 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
298 setOperationAction(ISD::VASTART , MVT::Other, Custom);
300 if (Subtarget.isSVR4ABI()) {
302 // VAARG always uses double-word chunks, so promote anything smaller.
303 setOperationAction(ISD::VAARG, MVT::i1, Promote);
304 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
305 setOperationAction(ISD::VAARG, MVT::i8, Promote);
306 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
307 setOperationAction(ISD::VAARG, MVT::i16, Promote);
308 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
309 setOperationAction(ISD::VAARG, MVT::i32, Promote);
310 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
311 setOperationAction(ISD::VAARG, MVT::Other, Expand);
313 // VAARG is custom lowered with the 32-bit SVR4 ABI.
314 setOperationAction(ISD::VAARG, MVT::Other, Custom);
315 setOperationAction(ISD::VAARG, MVT::i64, Custom);
318 setOperationAction(ISD::VAARG, MVT::Other, Expand);
320 if (Subtarget.isSVR4ABI() && !isPPC64)
321 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
322 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
324 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
326 // Use the default implementation.
327 setOperationAction(ISD::VAEND , MVT::Other, Expand);
328 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
329 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
331 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
333 // We want to custom lower some of our intrinsics.
334 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
336 // To handle counter-based loop conditions.
337 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
339 // Comparisons that require checking two conditions.
340 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
341 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
343 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
345 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
347 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
349 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
351 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
353 if (Subtarget.has64BitSupport()) {
354 // They also have instructions for converting between i64 and fp.
355 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
356 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
357 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
358 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
359 // This is just the low 32 bits of a (signed) fp->i64 conversion.
360 // We cannot do this with Promote because i64 is not a legal type.
361 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
363 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
364 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
366 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
367 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
370 // With the instructions enabled under FPCVT, we can do everything.
371 if (Subtarget.hasFPCVT()) {
372 if (Subtarget.has64BitSupport()) {
373 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
374 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
375 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
376 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
379 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
380 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
381 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
382 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
385 if (Subtarget.use64BitRegs()) {
386 // 64-bit PowerPC implementations can support i64 types directly
387 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
388 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
389 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
390 // 64-bit PowerPC wants to expand i128 shifts itself.
391 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
393 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
395 // 32-bit PowerPC wants to expand i64 shifts itself.
396 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
398 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
401 if (Subtarget.hasAltivec()) {
402 // First set operation action for all vector types to expand. Then we
403 // will selectively turn on ones that can be effectively codegen'd.
404 for (MVT VT : MVT::vector_valuetypes()) {
405 // add/sub are legal for all supported vector VT's.
406 setOperationAction(ISD::ADD, VT, Legal);
407 setOperationAction(ISD::SUB, VT, Legal);
409 // Vector instructions introduced in P8
410 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
411 setOperationAction(ISD::CTPOP, VT, Legal);
412 setOperationAction(ISD::CTLZ, VT, Legal);
415 setOperationAction(ISD::CTPOP, VT, Expand);
416 setOperationAction(ISD::CTLZ, VT, Expand);
419 // We promote all shuffles to v16i8.
420 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
421 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
423 // We promote all non-typed operations to v4i32.
424 setOperationAction(ISD::AND , VT, Promote);
425 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
426 setOperationAction(ISD::OR , VT, Promote);
427 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
428 setOperationAction(ISD::XOR , VT, Promote);
429 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
430 setOperationAction(ISD::LOAD , VT, Promote);
431 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
432 setOperationAction(ISD::SELECT, VT, Promote);
433 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
434 setOperationAction(ISD::SELECT_CC, VT, Promote);
435 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
436 setOperationAction(ISD::STORE, VT, Promote);
437 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
439 // No other operations are legal.
440 setOperationAction(ISD::MUL , VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::SREM, VT, Expand);
443 setOperationAction(ISD::UDIV, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
445 setOperationAction(ISD::FDIV, VT, Expand);
446 setOperationAction(ISD::FREM, VT, Expand);
447 setOperationAction(ISD::FNEG, VT, Expand);
448 setOperationAction(ISD::FSQRT, VT, Expand);
449 setOperationAction(ISD::FLOG, VT, Expand);
450 setOperationAction(ISD::FLOG10, VT, Expand);
451 setOperationAction(ISD::FLOG2, VT, Expand);
452 setOperationAction(ISD::FEXP, VT, Expand);
453 setOperationAction(ISD::FEXP2, VT, Expand);
454 setOperationAction(ISD::FSIN, VT, Expand);
455 setOperationAction(ISD::FCOS, VT, Expand);
456 setOperationAction(ISD::FABS, VT, Expand);
457 setOperationAction(ISD::FPOWI, VT, Expand);
458 setOperationAction(ISD::FFLOOR, VT, Expand);
459 setOperationAction(ISD::FCEIL, VT, Expand);
460 setOperationAction(ISD::FTRUNC, VT, Expand);
461 setOperationAction(ISD::FRINT, VT, Expand);
462 setOperationAction(ISD::FNEARBYINT, VT, Expand);
463 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
464 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
465 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
466 setOperationAction(ISD::MULHU, VT, Expand);
467 setOperationAction(ISD::MULHS, VT, Expand);
468 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
469 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
470 setOperationAction(ISD::UDIVREM, VT, Expand);
471 setOperationAction(ISD::SDIVREM, VT, Expand);
472 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
473 setOperationAction(ISD::FPOW, VT, Expand);
474 setOperationAction(ISD::BSWAP, VT, Expand);
475 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
476 setOperationAction(ISD::CTTZ, VT, Expand);
477 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
478 setOperationAction(ISD::VSELECT, VT, Expand);
479 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
481 for (MVT InnerVT : MVT::vector_valuetypes()) {
482 setTruncStoreAction(VT, InnerVT, Expand);
483 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
484 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
485 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
489 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
490 // with merges, splats, etc.
491 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
493 setOperationAction(ISD::AND , MVT::v4i32, Legal);
494 setOperationAction(ISD::OR , MVT::v4i32, Legal);
495 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
496 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
497 setOperationAction(ISD::SELECT, MVT::v4i32,
498 Subtarget.useCRBits() ? Legal : Expand);
499 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
500 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
501 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
502 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
503 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
504 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
505 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
506 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
507 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
509 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
510 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
511 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
512 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
514 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
515 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
517 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
518 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
519 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
522 if (Subtarget.hasP8Altivec())
523 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
525 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
527 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
528 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
530 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
531 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
533 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
534 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
535 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
536 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
538 // Altivec does not contain unordered floating-point compare instructions
539 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
540 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
541 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
542 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
544 if (Subtarget.hasVSX()) {
545 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
546 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
547 if (Subtarget.hasP8Vector()) {
548 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
549 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Legal);
551 if (Subtarget.hasDirectMove()) {
552 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
553 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
554 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
555 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
556 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Legal);
557 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Legal);
558 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
559 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal);
561 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
563 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
564 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
565 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
566 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
567 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
569 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
571 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
572 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
574 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
575 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
577 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
578 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
579 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
580 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
581 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
583 // Share the Altivec comparison restrictions.
584 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
585 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
586 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
587 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
589 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
590 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
592 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
594 if (Subtarget.hasP8Vector())
595 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
597 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
599 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
600 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
601 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
603 if (Subtarget.hasP8Altivec()) {
604 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
605 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
606 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
608 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
611 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
612 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
613 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
615 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
617 // VSX v2i64 only supports non-arithmetic operations.
618 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
619 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
622 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
623 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
624 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
625 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
627 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
629 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
630 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
631 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
632 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
634 // Vector operation legalization checks the result type of
635 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
636 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
637 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
638 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
639 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
641 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
644 if (Subtarget.hasP8Altivec()) {
645 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
646 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
650 if (Subtarget.hasQPX()) {
651 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
652 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
653 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
654 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
656 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
657 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand);
659 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
660 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
662 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
663 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
665 if (!Subtarget.useCRBits())
666 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
667 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
669 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);
670 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
671 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
672 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
673 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
674 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
675 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
677 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
678 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
680 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
681 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
682 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
684 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
685 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
686 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
687 setOperationAction(ISD::FCOS , MVT::v4f64, Expand);
688 setOperationAction(ISD::FPOWI , MVT::v4f64, Expand);
689 setOperationAction(ISD::FPOW , MVT::v4f64, Expand);
690 setOperationAction(ISD::FLOG , MVT::v4f64, Expand);
691 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
692 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand);
693 setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
694 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
696 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
697 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
699 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
700 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
702 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
704 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
705 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
706 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
707 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
709 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
710 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
712 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
713 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
715 if (!Subtarget.useCRBits())
716 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
717 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
719 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
720 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
721 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
722 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
723 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
724 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
725 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
727 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
728 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
730 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
731 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
732 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
733 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
734 setOperationAction(ISD::FPOWI , MVT::v4f32, Expand);
735 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
736 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
737 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
738 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
739 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
740 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
742 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
743 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
745 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
746 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
748 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
750 setOperationAction(ISD::AND , MVT::v4i1, Legal);
751 setOperationAction(ISD::OR , MVT::v4i1, Legal);
752 setOperationAction(ISD::XOR , MVT::v4i1, Legal);
754 if (!Subtarget.useCRBits())
755 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
756 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
758 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
759 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
761 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);
762 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
763 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
764 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand);
765 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
766 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
767 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
769 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
770 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
772 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
774 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
775 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
776 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
777 setOperationAction(ISD::FROUND, MVT::v4f64, Legal);
779 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
780 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
781 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
782 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
784 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
785 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
787 // These need to set FE_INEXACT, and so cannot be vectorized here.
788 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
789 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
791 if (TM.Options.UnsafeFPMath) {
792 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
793 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
795 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
796 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
798 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
799 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
801 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
802 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
806 if (Subtarget.has64BitSupport())
807 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
809 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
812 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
813 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
816 setBooleanContents(ZeroOrOneBooleanContent);
818 if (Subtarget.hasAltivec()) {
819 // Altivec instructions set fields to all zeros or all ones.
820 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
824 // These libcalls are not available in 32-bit.
825 setLibcallName(RTLIB::SHL_I128, nullptr);
826 setLibcallName(RTLIB::SRL_I128, nullptr);
827 setLibcallName(RTLIB::SRA_I128, nullptr);
830 setStackPointerRegisterToSaveRestore(isPPC64 ? PPC::X1 : PPC::R1);
832 // We have target-specific dag combine patterns for the following nodes:
833 setTargetDAGCombine(ISD::SINT_TO_FP);
834 if (Subtarget.hasFPCVT())
835 setTargetDAGCombine(ISD::UINT_TO_FP);
836 setTargetDAGCombine(ISD::LOAD);
837 setTargetDAGCombine(ISD::STORE);
838 setTargetDAGCombine(ISD::BR_CC);
839 if (Subtarget.useCRBits())
840 setTargetDAGCombine(ISD::BRCOND);
841 setTargetDAGCombine(ISD::BSWAP);
842 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
843 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
844 setTargetDAGCombine(ISD::INTRINSIC_VOID);
846 setTargetDAGCombine(ISD::SIGN_EXTEND);
847 setTargetDAGCombine(ISD::ZERO_EXTEND);
848 setTargetDAGCombine(ISD::ANY_EXTEND);
850 if (Subtarget.useCRBits()) {
851 setTargetDAGCombine(ISD::TRUNCATE);
852 setTargetDAGCombine(ISD::SETCC);
853 setTargetDAGCombine(ISD::SELECT_CC);
856 // Use reciprocal estimates.
857 if (TM.Options.UnsafeFPMath) {
858 setTargetDAGCombine(ISD::FDIV);
859 setTargetDAGCombine(ISD::FSQRT);
862 // Darwin long double math library functions have $LDBL128 appended.
863 if (Subtarget.isDarwin()) {
864 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
865 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
866 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
867 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
868 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
869 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
870 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
871 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
872 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
873 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
876 // With 32 condition bits, we don't need to sink (and duplicate) compares
877 // aggressively in CodeGenPrep.
878 if (Subtarget.useCRBits()) {
879 setHasMultipleConditionRegisters();
880 setJumpIsExpensive();
883 setMinFunctionAlignment(2);
884 if (Subtarget.isDarwin())
885 setPrefFunctionAlignment(4);
887 switch (Subtarget.getDarwinDirective()) {
891 case PPC::DIR_E500mc:
900 setPrefFunctionAlignment(4);
901 setPrefLoopAlignment(4);
905 setInsertFencesForAtomic(true);
907 if (Subtarget.enableMachineScheduler())
908 setSchedulingPreference(Sched::Source);
910 setSchedulingPreference(Sched::Hybrid);
912 computeRegisterProperties(STI.getRegisterInfo());
914 // The Freescale cores do better with aggressive inlining of memcpy and
915 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
916 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
917 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
918 MaxStoresPerMemset = 32;
919 MaxStoresPerMemsetOptSize = 16;
920 MaxStoresPerMemcpy = 32;
921 MaxStoresPerMemcpyOptSize = 8;
922 MaxStoresPerMemmove = 32;
923 MaxStoresPerMemmoveOptSize = 8;
924 } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) {
925 // The A2 also benefits from (very) aggressive inlining of memcpy and
926 // friends. The overhead of a the function call, even when warm, can be
927 // over one hundred cycles.
928 MaxStoresPerMemset = 128;
929 MaxStoresPerMemcpy = 128;
930 MaxStoresPerMemmove = 128;
934 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
935 /// the desired ByVal argument alignment.
936 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
937 unsigned MaxMaxAlign) {
938 if (MaxAlign == MaxMaxAlign)
940 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
941 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
943 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
945 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
946 unsigned EltAlign = 0;
947 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
948 if (EltAlign > MaxAlign)
950 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
951 for (auto *EltTy : STy->elements()) {
952 unsigned EltAlign = 0;
953 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
954 if (EltAlign > MaxAlign)
956 if (MaxAlign == MaxMaxAlign)
962 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
963 /// function arguments in the caller parameter area.
964 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
965 const DataLayout &DL) const {
966 // Darwin passes everything on 4 byte boundary.
967 if (Subtarget.isDarwin())
970 // 16byte and wider vectors are passed on 16byte boundary.
971 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
972 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
973 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
974 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
978 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
979 switch ((PPCISD::NodeType)Opcode) {
980 case PPCISD::FIRST_NUMBER: break;
981 case PPCISD::FSEL: return "PPCISD::FSEL";
982 case PPCISD::FCFID: return "PPCISD::FCFID";
983 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
984 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
985 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
986 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
987 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
988 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
989 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
990 case PPCISD::FRE: return "PPCISD::FRE";
991 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
992 case PPCISD::STFIWX: return "PPCISD::STFIWX";
993 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
994 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
995 case PPCISD::VPERM: return "PPCISD::VPERM";
996 case PPCISD::CMPB: return "PPCISD::CMPB";
997 case PPCISD::Hi: return "PPCISD::Hi";
998 case PPCISD::Lo: return "PPCISD::Lo";
999 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1000 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1001 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1002 case PPCISD::SRL: return "PPCISD::SRL";
1003 case PPCISD::SRA: return "PPCISD::SRA";
1004 case PPCISD::SHL: return "PPCISD::SHL";
1005 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1006 case PPCISD::CALL: return "PPCISD::CALL";
1007 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1008 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1009 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1010 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1011 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1012 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1013 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1014 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1015 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1016 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1017 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1018 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1019 case PPCISD::ANDIo_1_EQ_BIT: return "PPCISD::ANDIo_1_EQ_BIT";
1020 case PPCISD::ANDIo_1_GT_BIT: return "PPCISD::ANDIo_1_GT_BIT";
1021 case PPCISD::VCMP: return "PPCISD::VCMP";
1022 case PPCISD::VCMPo: return "PPCISD::VCMPo";
1023 case PPCISD::LBRX: return "PPCISD::LBRX";
1024 case PPCISD::STBRX: return "PPCISD::STBRX";
1025 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1026 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1027 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1028 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1029 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1030 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1031 case PPCISD::BDZ: return "PPCISD::BDZ";
1032 case PPCISD::MFFS: return "PPCISD::MFFS";
1033 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1034 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1035 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1036 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1037 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1038 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1039 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1040 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1041 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1042 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1043 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1044 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1045 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1046 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1047 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1048 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1049 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1050 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1051 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1052 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1053 case PPCISD::SC: return "PPCISD::SC";
1054 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1055 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1056 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1057 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1058 case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1059 case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1060 case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1061 case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1062 case PPCISD::QBFLT: return "PPCISD::QBFLT";
1063 case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1068 EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1071 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1073 if (Subtarget.hasQPX())
1074 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
1076 return VT.changeVectorElementTypeToInteger();
1079 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1080 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1084 //===----------------------------------------------------------------------===//
1085 // Node matching predicates, for use by the tblgen matching code.
1086 //===----------------------------------------------------------------------===//
1088 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1089 static bool isFloatingPointZero(SDValue Op) {
1090 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1091 return CFP->getValueAPF().isZero();
1092 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1093 // Maybe this has already been legalized into the constant pool?
1094 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1095 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1096 return CFP->getValueAPF().isZero();
1101 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1102 /// true if Op is undef or if it matches the specified value.
1103 static bool isConstantOrUndef(int Op, int Val) {
1104 return Op < 0 || Op == Val;
1107 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1108 /// VPKUHUM instruction.
1109 /// The ShuffleKind distinguishes between big-endian operations with
1110 /// two different inputs (0), either-endian operations with two identical
1111 /// inputs (1), and little-endian operations with two different inputs (2).
1112 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1113 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1114 SelectionDAG &DAG) {
1115 bool IsLE = DAG.getDataLayout().isLittleEndian();
1116 if (ShuffleKind == 0) {
1119 for (unsigned i = 0; i != 16; ++i)
1120 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1122 } else if (ShuffleKind == 2) {
1125 for (unsigned i = 0; i != 16; ++i)
1126 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1128 } else if (ShuffleKind == 1) {
1129 unsigned j = IsLE ? 0 : 1;
1130 for (unsigned i = 0; i != 8; ++i)
1131 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1132 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1138 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1139 /// VPKUWUM instruction.
1140 /// The ShuffleKind distinguishes between big-endian operations with
1141 /// two different inputs (0), either-endian operations with two identical
1142 /// inputs (1), and little-endian operations with two different inputs (2).
1143 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1144 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1145 SelectionDAG &DAG) {
1146 bool IsLE = DAG.getDataLayout().isLittleEndian();
1147 if (ShuffleKind == 0) {
1150 for (unsigned i = 0; i != 16; i += 2)
1151 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1152 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1154 } else if (ShuffleKind == 2) {
1157 for (unsigned i = 0; i != 16; i += 2)
1158 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1159 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1161 } else if (ShuffleKind == 1) {
1162 unsigned j = IsLE ? 0 : 2;
1163 for (unsigned i = 0; i != 8; i += 2)
1164 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1165 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1166 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1167 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1173 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1174 /// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1175 /// current subtarget.
1177 /// The ShuffleKind distinguishes between big-endian operations with
1178 /// two different inputs (0), either-endian operations with two identical
1179 /// inputs (1), and little-endian operations with two different inputs (2).
1180 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1181 bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1182 SelectionDAG &DAG) {
1183 const PPCSubtarget& Subtarget =
1184 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1185 if (!Subtarget.hasP8Vector())
1188 bool IsLE = DAG.getDataLayout().isLittleEndian();
1189 if (ShuffleKind == 0) {
1192 for (unsigned i = 0; i != 16; i += 4)
1193 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1194 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1195 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1196 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1198 } else if (ShuffleKind == 2) {
1201 for (unsigned i = 0; i != 16; i += 4)
1202 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1203 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1204 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1205 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1207 } else if (ShuffleKind == 1) {
1208 unsigned j = IsLE ? 0 : 4;
1209 for (unsigned i = 0; i != 8; i += 4)
1210 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1211 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1212 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1213 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1214 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1215 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1216 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1217 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1223 /// isVMerge - Common function, used to match vmrg* shuffles.
1225 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1226 unsigned LHSStart, unsigned RHSStart) {
1227 if (N->getValueType(0) != MVT::v16i8)
1229 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1230 "Unsupported merge size!");
1232 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1233 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1234 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1235 LHSStart+j+i*UnitSize) ||
1236 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1237 RHSStart+j+i*UnitSize))
1243 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1244 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1245 /// The ShuffleKind distinguishes between big-endian merges with two
1246 /// different inputs (0), either-endian merges with two identical inputs (1),
1247 /// and little-endian merges with two different inputs (2). For the latter,
1248 /// the input operands are swapped (see PPCInstrAltivec.td).
1249 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1250 unsigned ShuffleKind, SelectionDAG &DAG) {
1251 if (DAG.getDataLayout().isLittleEndian()) {
1252 if (ShuffleKind == 1) // unary
1253 return isVMerge(N, UnitSize, 0, 0);
1254 else if (ShuffleKind == 2) // swapped
1255 return isVMerge(N, UnitSize, 0, 16);
1259 if (ShuffleKind == 1) // unary
1260 return isVMerge(N, UnitSize, 8, 8);
1261 else if (ShuffleKind == 0) // normal
1262 return isVMerge(N, UnitSize, 8, 24);
1268 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1269 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1270 /// The ShuffleKind distinguishes between big-endian merges with two
1271 /// different inputs (0), either-endian merges with two identical inputs (1),
1272 /// and little-endian merges with two different inputs (2). For the latter,
1273 /// the input operands are swapped (see PPCInstrAltivec.td).
1274 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1275 unsigned ShuffleKind, SelectionDAG &DAG) {
1276 if (DAG.getDataLayout().isLittleEndian()) {
1277 if (ShuffleKind == 1) // unary
1278 return isVMerge(N, UnitSize, 8, 8);
1279 else if (ShuffleKind == 2) // swapped
1280 return isVMerge(N, UnitSize, 8, 24);
1284 if (ShuffleKind == 1) // unary
1285 return isVMerge(N, UnitSize, 0, 0);
1286 else if (ShuffleKind == 0) // normal
1287 return isVMerge(N, UnitSize, 0, 16);
1294 * \brief Common function used to match vmrgew and vmrgow shuffles
1296 * The indexOffset determines whether to look for even or odd words in
1297 * the shuffle mask. This is based on the of the endianness of the target
1300 * - Use offset of 0 to check for odd elements
1301 * - Use offset of 4 to check for even elements
1303 * - Use offset of 0 to check for even elements
1304 * - Use offset of 4 to check for odd elements
1305 * A detailed description of the vector element ordering for little endian and
1306 * big endian can be found at
1307 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1308 * Targeting your applications - what little endian and big endian IBM XL C/C++
1309 * compiler differences mean to you
1311 * The mask to the shuffle vector instruction specifies the indices of the
1312 * elements from the two input vectors to place in the result. The elements are
1313 * numbered in array-access order, starting with the first vector. These vectors
1314 * are always of type v16i8, thus each vector will contain 16 elements of size
1315 * 8. More info on the shuffle vector can be found in the
1316 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1317 * Language Reference.
1319 * The RHSStartValue indicates whether the same input vectors are used (unary)
1320 * or two different input vectors are used, based on the following:
1321 * - If the instruction uses the same vector for both inputs, the range of the
1322 * indices will be 0 to 15. In this case, the RHSStart value passed should
1324 * - If the instruction has two different vectors then the range of the
1325 * indices will be 0 to 31. In this case, the RHSStart value passed should
1326 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1327 * to 31 specify elements in the second vector).
1329 * \param[in] N The shuffle vector SD Node to analyze
1330 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1331 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1332 * vector to the shuffle_vector instruction
1333 * \return true iff this shuffle vector represents an even or odd word merge
1335 static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1336 unsigned RHSStartValue) {
1337 if (N->getValueType(0) != MVT::v16i8)
1340 for (unsigned i = 0; i < 2; ++i)
1341 for (unsigned j = 0; j < 4; ++j)
1342 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1343 i*RHSStartValue+j+IndexOffset) ||
1344 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1345 i*RHSStartValue+j+IndexOffset+8))
1351 * \brief Determine if the specified shuffle mask is suitable for the vmrgew or
1352 * vmrgow instructions.
1354 * \param[in] N The shuffle vector SD Node to analyze
1355 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1356 * \param[in] ShuffleKind Identify the type of merge:
1357 * - 0 = big-endian merge with two different inputs;
1358 * - 1 = either-endian merge with two identical inputs;
1359 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1360 * little-endian merges).
1361 * \param[in] DAG The current SelectionDAG
1362 * \return true iff this shuffle mask
1364 bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1365 unsigned ShuffleKind, SelectionDAG &DAG) {
1366 if (DAG.getDataLayout().isLittleEndian()) {
1367 unsigned indexOffset = CheckEven ? 4 : 0;
1368 if (ShuffleKind == 1) // Unary
1369 return isVMerge(N, indexOffset, 0);
1370 else if (ShuffleKind == 2) // swapped
1371 return isVMerge(N, indexOffset, 16);
1376 unsigned indexOffset = CheckEven ? 0 : 4;
1377 if (ShuffleKind == 1) // Unary
1378 return isVMerge(N, indexOffset, 0);
1379 else if (ShuffleKind == 0) // Normal
1380 return isVMerge(N, indexOffset, 16);
1387 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1388 /// amount, otherwise return -1.
1389 /// The ShuffleKind distinguishes between big-endian operations with two
1390 /// different inputs (0), either-endian operations with two identical inputs
1391 /// (1), and little-endian operations with two different inputs (2). For the
1392 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1393 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1394 SelectionDAG &DAG) {
1395 if (N->getValueType(0) != MVT::v16i8)
1398 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1400 // Find the first non-undef value in the shuffle mask.
1402 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1405 if (i == 16) return -1; // all undef.
1407 // Otherwise, check to see if the rest of the elements are consecutively
1408 // numbered from this value.
1409 unsigned ShiftAmt = SVOp->getMaskElt(i);
1410 if (ShiftAmt < i) return -1;
1413 bool isLE = DAG.getDataLayout().isLittleEndian();
1415 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1416 // Check the rest of the elements to see if they are consecutive.
1417 for (++i; i != 16; ++i)
1418 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1420 } else if (ShuffleKind == 1) {
1421 // Check the rest of the elements to see if they are consecutive.
1422 for (++i; i != 16; ++i)
1423 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1429 ShiftAmt = 16 - ShiftAmt;
1434 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1435 /// specifies a splat of a single element that is suitable for input to
1436 /// VSPLTB/VSPLTH/VSPLTW.
1437 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1438 assert(N->getValueType(0) == MVT::v16i8 &&
1439 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1441 // The consecutive indices need to specify an element, not part of two
1442 // different elements. So abandon ship early if this isn't the case.
1443 if (N->getMaskElt(0) % EltSize != 0)
1446 // This is a splat operation if each element of the permute is the same, and
1447 // if the value doesn't reference the second vector.
1448 unsigned ElementBase = N->getMaskElt(0);
1450 // FIXME: Handle UNDEF elements too!
1451 if (ElementBase >= 16)
1454 // Check that the indices are consecutive, in the case of a multi-byte element
1455 // splatted with a v16i8 mask.
1456 for (unsigned i = 1; i != EltSize; ++i)
1457 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1460 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1461 if (N->getMaskElt(i) < 0) continue;
1462 for (unsigned j = 0; j != EltSize; ++j)
1463 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1469 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1470 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1471 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1472 SelectionDAG &DAG) {
1473 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1474 assert(isSplatShuffleMask(SVOp, EltSize));
1475 if (DAG.getDataLayout().isLittleEndian())
1476 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1478 return SVOp->getMaskElt(0) / EltSize;
1481 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1482 /// by using a vspltis[bhw] instruction of the specified element size, return
1483 /// the constant being splatted. The ByteSize field indicates the number of
1484 /// bytes of each element [124] -> [bhw].
1485 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1486 SDValue OpVal(nullptr, 0);
1488 // If ByteSize of the splat is bigger than the element size of the
1489 // build_vector, then we have a case where we are checking for a splat where
1490 // multiple elements of the buildvector are folded together into a single
1491 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1492 unsigned EltSize = 16/N->getNumOperands();
1493 if (EltSize < ByteSize) {
1494 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1495 SDValue UniquedVals[4];
1496 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1498 // See if all of the elements in the buildvector agree across.
1499 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1500 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1501 // If the element isn't a constant, bail fully out.
1502 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1505 if (!UniquedVals[i&(Multiple-1)].getNode())
1506 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1507 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1508 return SDValue(); // no match.
1511 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1512 // either constant or undef values that are identical for each chunk. See
1513 // if these chunks can form into a larger vspltis*.
1515 // Check to see if all of the leading entries are either 0 or -1. If
1516 // neither, then this won't fit into the immediate field.
1517 bool LeadingZero = true;
1518 bool LeadingOnes = true;
1519 for (unsigned i = 0; i != Multiple-1; ++i) {
1520 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1522 LeadingZero &= isNullConstant(UniquedVals[i]);
1523 LeadingOnes &= isAllOnesConstant(UniquedVals[i]);
1525 // Finally, check the least significant entry.
1527 if (!UniquedVals[Multiple-1].getNode())
1528 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
1529 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1530 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
1531 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1534 if (!UniquedVals[Multiple-1].getNode())
1535 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
1536 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1537 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1538 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1544 // Check to see if this buildvec has a single non-undef value in its elements.
1545 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1546 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1547 if (!OpVal.getNode())
1548 OpVal = N->getOperand(i);
1549 else if (OpVal != N->getOperand(i))
1553 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1555 unsigned ValSizeInBytes = EltSize;
1557 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1558 Value = CN->getZExtValue();
1559 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1560 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1561 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1564 // If the splat value is larger than the element value, then we can never do
1565 // this splat. The only case that we could fit the replicated bits into our
1566 // immediate field for would be zero, and we prefer to use vxor for it.
1567 if (ValSizeInBytes < ByteSize) return SDValue();
1569 // If the element value is larger than the splat value, check if it consists
1570 // of a repeated bit pattern of size ByteSize.
1571 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
1574 // Properly sign extend the value.
1575 int MaskVal = SignExtend32(Value, ByteSize * 8);
1577 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1578 if (MaskVal == 0) return SDValue();
1580 // Finally, if this value fits in a 5 bit sext field, return it
1581 if (SignExtend32<5>(MaskVal) == MaskVal)
1582 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
1586 /// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
1587 /// amount, otherwise return -1.
1588 int PPC::isQVALIGNIShuffleMask(SDNode *N) {
1589 EVT VT = N->getValueType(0);
1590 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
1593 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1595 // Find the first non-undef value in the shuffle mask.
1597 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
1600 if (i == 4) return -1; // all undef.
1602 // Otherwise, check to see if the rest of the elements are consecutively
1603 // numbered from this value.
1604 unsigned ShiftAmt = SVOp->getMaskElt(i);
1605 if (ShiftAmt < i) return -1;
1608 // Check the rest of the elements to see if they are consecutive.
1609 for (++i; i != 4; ++i)
1610 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1616 //===----------------------------------------------------------------------===//
1617 // Addressing Mode Selection
1618 //===----------------------------------------------------------------------===//
1620 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1621 /// or 64-bit immediate, and if the value can be accurately represented as a
1622 /// sign extension from a 16-bit value. If so, this returns true and the
1624 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1625 if (!isa<ConstantSDNode>(N))
1628 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1629 if (N->getValueType(0) == MVT::i32)
1630 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1632 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1634 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1635 return isIntS16Immediate(Op.getNode(), Imm);
1638 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1639 /// can be represented as an indexed [r+r] operation. Returns false if it
1640 /// can be more efficiently represented with [r+imm].
1641 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1643 SelectionDAG &DAG) const {
1645 if (N.getOpcode() == ISD::ADD) {
1646 if (isIntS16Immediate(N.getOperand(1), imm))
1647 return false; // r+i
1648 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1649 return false; // r+i
1651 Base = N.getOperand(0);
1652 Index = N.getOperand(1);
1654 } else if (N.getOpcode() == ISD::OR) {
1655 if (isIntS16Immediate(N.getOperand(1), imm))
1656 return false; // r+i can fold it if we can.
1658 // If this is an or of disjoint bitfields, we can codegen this as an add
1659 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1661 APInt LHSKnownZero, LHSKnownOne;
1662 APInt RHSKnownZero, RHSKnownOne;
1663 DAG.computeKnownBits(N.getOperand(0),
1664 LHSKnownZero, LHSKnownOne);
1666 if (LHSKnownZero.getBoolValue()) {
1667 DAG.computeKnownBits(N.getOperand(1),
1668 RHSKnownZero, RHSKnownOne);
1669 // If all of the bits are known zero on the LHS or RHS, the add won't
1671 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1672 Base = N.getOperand(0);
1673 Index = N.getOperand(1);
1682 // If we happen to be doing an i64 load or store into a stack slot that has
1683 // less than a 4-byte alignment, then the frame-index elimination may need to
1684 // use an indexed load or store instruction (because the offset may not be a
1685 // multiple of 4). The extra register needed to hold the offset comes from the
1686 // register scavenger, and it is possible that the scavenger will need to use
1687 // an emergency spill slot. As a result, we need to make sure that a spill slot
1688 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1690 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1691 // FIXME: This does not handle the LWA case.
1695 // NOTE: We'll exclude negative FIs here, which come from argument
1696 // lowering, because there are no known test cases triggering this problem
1697 // using packed structures (or similar). We can remove this exclusion if
1698 // we find such a test case. The reason why this is so test-case driven is
1699 // because this entire 'fixup' is only to prevent crashes (from the
1700 // register scavenger) on not-really-valid inputs. For example, if we have:
1702 // %b = bitcast i1* %a to i64*
1703 // store i64* a, i64 b
1704 // then the store should really be marked as 'align 1', but is not. If it
1705 // were marked as 'align 1' then the indexed form would have been
1706 // instruction-selected initially, and the problem this 'fixup' is preventing
1707 // won't happen regardless.
1711 MachineFunction &MF = DAG.getMachineFunction();
1712 MachineFrameInfo *MFI = MF.getFrameInfo();
1714 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1718 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1719 FuncInfo->setHasNonRISpills();
1722 /// Returns true if the address N can be represented by a base register plus
1723 /// a signed 16-bit displacement [r+imm], and if it is not better
1724 /// represented as reg+reg. If Aligned is true, only accept displacements
1725 /// suitable for STD and friends, i.e. multiples of 4.
1726 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1729 bool Aligned) const {
1730 // FIXME dl should come from parent load or store, not from address
1732 // If this can be more profitably realized as r+r, fail.
1733 if (SelectAddressRegReg(N, Disp, Base, DAG))
1736 if (N.getOpcode() == ISD::ADD) {
1738 if (isIntS16Immediate(N.getOperand(1), imm) &&
1739 (!Aligned || (imm & 3) == 0)) {
1740 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1741 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1742 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1743 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1745 Base = N.getOperand(0);
1747 return true; // [r+i]
1748 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1749 // Match LOAD (ADD (X, Lo(G))).
1750 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1751 && "Cannot handle constant offsets yet!");
1752 Disp = N.getOperand(1).getOperand(0); // The global address.
1753 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1754 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1755 Disp.getOpcode() == ISD::TargetConstantPool ||
1756 Disp.getOpcode() == ISD::TargetJumpTable);
1757 Base = N.getOperand(0);
1758 return true; // [&g+r]
1760 } else if (N.getOpcode() == ISD::OR) {
1762 if (isIntS16Immediate(N.getOperand(1), imm) &&
1763 (!Aligned || (imm & 3) == 0)) {
1764 // If this is an or of disjoint bitfields, we can codegen this as an add
1765 // (for better address arithmetic) if the LHS and RHS of the OR are
1766 // provably disjoint.
1767 APInt LHSKnownZero, LHSKnownOne;
1768 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1770 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1771 // If all of the bits are known zero on the LHS or RHS, the add won't
1773 if (FrameIndexSDNode *FI =
1774 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1775 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1776 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1778 Base = N.getOperand(0);
1780 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1784 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1785 // Loading from a constant address.
1787 // If this address fits entirely in a 16-bit sext immediate field, codegen
1790 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1791 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
1792 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1793 CN->getValueType(0));
1797 // Handle 32-bit sext immediates with LIS + addr mode.
1798 if ((CN->getValueType(0) == MVT::i32 ||
1799 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1800 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1801 int Addr = (int)CN->getZExtValue();
1803 // Otherwise, break this down into an LIS + disp.
1804 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
1806 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
1808 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1809 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1814 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
1815 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1816 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1817 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1820 return true; // [r+0]
1823 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1824 /// represented as an indexed [r+r] operation.
1825 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1827 SelectionDAG &DAG) const {
1828 // Check to see if we can easily represent this as an [r+r] address. This
1829 // will fail if it thinks that the address is more profitably represented as
1830 // reg+imm, e.g. where imm = 0.
1831 if (SelectAddressRegReg(N, Base, Index, DAG))
1834 // If the operand is an addition, always emit this as [r+r], since this is
1835 // better (for code size, and execution, as the memop does the add for free)
1836 // than emitting an explicit add.
1837 if (N.getOpcode() == ISD::ADD) {
1838 Base = N.getOperand(0);
1839 Index = N.getOperand(1);
1843 // Otherwise, do it the hard way, using R0 as the base register.
1844 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1850 /// getPreIndexedAddressParts - returns true by value, base pointer and
1851 /// offset pointer and addressing mode by reference if the node's address
1852 /// can be legally represented as pre-indexed load / store address.
1853 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1855 ISD::MemIndexedMode &AM,
1856 SelectionDAG &DAG) const {
1857 if (DisablePPCPreinc) return false;
1863 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1864 Ptr = LD->getBasePtr();
1865 VT = LD->getMemoryVT();
1866 Alignment = LD->getAlignment();
1867 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1868 Ptr = ST->getBasePtr();
1869 VT = ST->getMemoryVT();
1870 Alignment = ST->getAlignment();
1875 // PowerPC doesn't have preinc load/store instructions for vectors (except
1876 // for QPX, which does have preinc r+r forms).
1877 if (VT.isVector()) {
1878 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
1880 } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
1886 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1888 // Common code will reject creating a pre-inc form if the base pointer
1889 // is a frame index, or if N is a store and the base pointer is either
1890 // the same as or a predecessor of the value being stored. Check for
1891 // those situations here, and try with swapped Base/Offset instead.
1894 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1897 SDValue Val = cast<StoreSDNode>(N)->getValue();
1898 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1903 std::swap(Base, Offset);
1909 // LDU/STU can only handle immediates that are a multiple of 4.
1910 if (VT != MVT::i64) {
1911 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1914 // LDU/STU need an address with at least 4-byte alignment.
1918 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1922 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1923 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1924 // sext i32 to i64 when addr mode is r+i.
1925 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1926 LD->getExtensionType() == ISD::SEXTLOAD &&
1927 isa<ConstantSDNode>(Offset))
1935 //===----------------------------------------------------------------------===//
1936 // LowerOperation implementation
1937 //===----------------------------------------------------------------------===//
1939 /// GetLabelAccessInfo - Return true if we should reference labels using a
1940 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1941 static bool GetLabelAccessInfo(const TargetMachine &TM,
1942 const PPCSubtarget &Subtarget,
1943 unsigned &HiOpFlags, unsigned &LoOpFlags,
1944 const GlobalValue *GV = nullptr) {
1945 HiOpFlags = PPCII::MO_HA;
1946 LoOpFlags = PPCII::MO_LO;
1948 // Don't use the pic base if not in PIC relocation model.
1949 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1952 HiOpFlags |= PPCII::MO_PIC_FLAG;
1953 LoOpFlags |= PPCII::MO_PIC_FLAG;
1956 // If this is a reference to a global value that requires a non-lazy-ptr, make
1957 // sure that instruction lowering adds it.
1958 if (GV && Subtarget.hasLazyResolverStub(GV)) {
1959 HiOpFlags |= PPCII::MO_NLP_FLAG;
1960 LoOpFlags |= PPCII::MO_NLP_FLAG;
1962 if (GV->hasHiddenVisibility()) {
1963 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1964 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1971 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1972 SelectionDAG &DAG) {
1974 EVT PtrVT = HiPart.getValueType();
1975 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
1977 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1978 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1980 // With PIC, the first instruction is actually "GR+hi(&G)".
1982 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1983 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1985 // Generate non-pic code that has direct accesses to the constant pool.
1986 // The address of the global is just (hi(&g)+lo(&g)).
1987 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1990 static void setUsesTOCBasePtr(MachineFunction &MF) {
1991 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1992 FuncInfo->setUsesTOCBasePtr();
1995 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
1996 setUsesTOCBasePtr(DAG.getMachineFunction());
1999 static SDValue getTOCEntry(SelectionDAG &DAG, SDLoc dl, bool Is64Bit,
2001 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2002 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
2003 DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
2005 SDValue Ops[] = { GA, Reg };
2006 return DAG.getMemIntrinsicNode(
2007 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
2008 MachinePointerInfo::getGOT(DAG.getMachineFunction()), 0, false, true,
2012 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2013 SelectionDAG &DAG) const {
2014 EVT PtrVT = Op.getValueType();
2015 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2016 const Constant *C = CP->getConstVal();
2018 // 64-bit SVR4 ABI code is always position-independent.
2019 // The actual address of the GlobalValue is stored in the TOC.
2020 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2021 setUsesTOCBasePtr(DAG);
2022 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
2023 return getTOCEntry(DAG, SDLoc(CP), true, GA);
2026 unsigned MOHiFlag, MOLoFlag;
2028 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2030 if (isPIC && Subtarget.isSVR4ABI()) {
2031 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
2032 PPCII::MO_PIC_FLAG);
2033 return getTOCEntry(DAG, SDLoc(CP), false, GA);
2037 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
2039 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
2040 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
2043 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2044 EVT PtrVT = Op.getValueType();
2045 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2047 // 64-bit SVR4 ABI code is always position-independent.
2048 // The actual address of the GlobalValue is stored in the TOC.
2049 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2050 setUsesTOCBasePtr(DAG);
2051 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2052 return getTOCEntry(DAG, SDLoc(JT), true, GA);
2055 unsigned MOHiFlag, MOLoFlag;
2057 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2059 if (isPIC && Subtarget.isSVR4ABI()) {
2060 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2061 PPCII::MO_PIC_FLAG);
2062 return getTOCEntry(DAG, SDLoc(GA), false, GA);
2065 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
2066 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
2067 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
2070 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2071 SelectionDAG &DAG) const {
2072 EVT PtrVT = Op.getValueType();
2073 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2074 const BlockAddress *BA = BASDN->getBlockAddress();
2076 // 64-bit SVR4 ABI code is always position-independent.
2077 // The actual BlockAddress is stored in the TOC.
2078 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2079 setUsesTOCBasePtr(DAG);
2080 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
2081 return getTOCEntry(DAG, SDLoc(BASDN), true, GA);
2084 unsigned MOHiFlag, MOLoFlag;
2086 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2087 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
2088 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
2089 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
2092 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2093 SelectionDAG &DAG) const {
2095 // FIXME: TLS addresses currently use medium model code sequences,
2096 // which is the most useful form. Eventually support for small and
2097 // large models could be added if users need it, at the cost of
2098 // additional complexity.
2099 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2100 if (DAG.getTarget().Options.EmulatedTLS)
2101 return LowerToTLSEmulatedModel(GA, DAG);
2104 const GlobalValue *GV = GA->getGlobal();
2105 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2106 bool is64bit = Subtarget.isPPC64();
2107 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
2108 PICLevel::Level picLevel = M->getPICLevel();
2110 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
2112 if (Model == TLSModel::LocalExec) {
2113 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2114 PPCII::MO_TPREL_HA);
2115 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2116 PPCII::MO_TPREL_LO);
2117 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
2118 is64bit ? MVT::i64 : MVT::i32);
2119 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
2120 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
2123 if (Model == TLSModel::InitialExec) {
2124 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2125 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2129 setUsesTOCBasePtr(DAG);
2130 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2131 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
2132 PtrVT, GOTReg, TGA);
2134 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
2135 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
2136 PtrVT, TGA, GOTPtr);
2137 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
2140 if (Model == TLSModel::GeneralDynamic) {
2141 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2144 setUsesTOCBasePtr(DAG);
2145 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2146 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
2149 if (picLevel == PICLevel::Small)
2150 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2152 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2154 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
2158 if (Model == TLSModel::LocalDynamic) {
2159 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2162 setUsesTOCBasePtr(DAG);
2163 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2164 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2167 if (picLevel == PICLevel::Small)
2168 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2170 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2172 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2173 PtrVT, GOTPtr, TGA, TGA);
2174 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2175 PtrVT, TLSAddr, TGA);
2176 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2179 llvm_unreachable("Unknown TLS model!");
2182 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2183 SelectionDAG &DAG) const {
2184 EVT PtrVT = Op.getValueType();
2185 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2187 const GlobalValue *GV = GSDN->getGlobal();
2189 // 64-bit SVR4 ABI code is always position-independent.
2190 // The actual address of the GlobalValue is stored in the TOC.
2191 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2192 setUsesTOCBasePtr(DAG);
2193 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2194 return getTOCEntry(DAG, DL, true, GA);
2197 unsigned MOHiFlag, MOLoFlag;
2199 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag, GV);
2201 if (isPIC && Subtarget.isSVR4ABI()) {
2202 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2204 PPCII::MO_PIC_FLAG);
2205 return getTOCEntry(DAG, DL, false, GA);
2209 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2211 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2213 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
2215 // If the global reference is actually to a non-lazy-pointer, we have to do an
2216 // extra load to get the address of the global.
2217 if (MOHiFlag & PPCII::MO_NLP_FLAG)
2218 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
2219 false, false, false, 0);
2223 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2224 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2227 if (Op.getValueType() == MVT::v2i64) {
2228 // When the operands themselves are v2i64 values, we need to do something
2229 // special because VSX has no underlying comparison operations for these.
2230 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2231 // Equality can be handled by casting to the legal type for Altivec
2232 // comparisons, everything else needs to be expanded.
2233 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2234 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2235 DAG.getSetCC(dl, MVT::v4i32,
2236 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2237 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2244 // We handle most of these in the usual way.
2248 // If we're comparing for equality to zero, expose the fact that this is
2249 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
2250 // fold the new nodes.
2251 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2252 if (C->isNullValue() && CC == ISD::SETEQ) {
2253 EVT VT = Op.getOperand(0).getValueType();
2254 SDValue Zext = Op.getOperand(0);
2255 if (VT.bitsLT(MVT::i32)) {
2257 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
2259 unsigned Log2b = Log2_32(VT.getSizeInBits());
2260 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
2261 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
2262 DAG.getConstant(Log2b, dl, MVT::i32));
2263 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
2265 // Leave comparisons against 0 and -1 alone for now, since they're usually
2266 // optimized. FIXME: revisit this when we can custom lower all setcc
2268 if (C->isAllOnesValue() || C->isNullValue())
2272 // If we have an integer seteq/setne, turn it into a compare against zero
2273 // by xor'ing the rhs with the lhs, which is faster than setting a
2274 // condition register, reading it back out, and masking the correct bit. The
2275 // normal approach here uses sub to do this instead of xor. Using xor exposes
2276 // the result to other bit-twiddling opportunities.
2277 EVT LHSVT = Op.getOperand(0).getValueType();
2278 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2279 EVT VT = Op.getValueType();
2280 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2282 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
2287 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
2288 const PPCSubtarget &Subtarget) const {
2289 SDNode *Node = Op.getNode();
2290 EVT VT = Node->getValueType(0);
2291 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2292 SDValue InChain = Node->getOperand(0);
2293 SDValue VAListPtr = Node->getOperand(1);
2294 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2297 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
2300 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2301 VAListPtr, MachinePointerInfo(SV), MVT::i8,
2302 false, false, false, 0);
2303 InChain = GprIndex.getValue(1);
2305 if (VT == MVT::i64) {
2306 // Check if GprIndex is even
2307 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2308 DAG.getConstant(1, dl, MVT::i32));
2309 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2310 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
2311 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2312 DAG.getConstant(1, dl, MVT::i32));
2313 // Align GprIndex to be even if it isn't
2314 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2318 // fpr index is 1 byte after gpr
2319 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2320 DAG.getConstant(1, dl, MVT::i32));
2323 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2324 FprPtr, MachinePointerInfo(SV), MVT::i8,
2325 false, false, false, 0);
2326 InChain = FprIndex.getValue(1);
2328 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2329 DAG.getConstant(8, dl, MVT::i32));
2331 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2332 DAG.getConstant(4, dl, MVT::i32));
2335 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
2336 MachinePointerInfo(), false, false,
2338 InChain = OverflowArea.getValue(1);
2340 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
2341 MachinePointerInfo(), false, false,
2343 InChain = RegSaveArea.getValue(1);
2345 // select overflow_area if index > 8
2346 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
2347 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
2349 // adjustment constant gpr_index * 4/8
2350 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
2351 VT.isInteger() ? GprIndex : FprIndex,
2352 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
2355 // OurReg = RegSaveArea + RegConstant
2356 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2359 // Floating types are 32 bytes into RegSaveArea
2360 if (VT.isFloatingPoint())
2361 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2362 DAG.getConstant(32, dl, MVT::i32));
2364 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
2365 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2366 VT.isInteger() ? GprIndex : FprIndex,
2367 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
2370 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
2371 VT.isInteger() ? VAListPtr : FprPtr,
2372 MachinePointerInfo(SV),
2373 MVT::i8, false, false, 0);
2375 // determine if we should load from reg_save_area or overflow_area
2376 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
2378 // increase overflow_area by 4/8 if gpr/fpr > 8
2379 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2380 DAG.getConstant(VT.isInteger() ? 4 : 8,
2383 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2386 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
2388 MachinePointerInfo(),
2389 MVT::i32, false, false, 0);
2391 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
2392 false, false, false, 0);
2395 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2396 const PPCSubtarget &Subtarget) const {
2397 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2399 // We have to copy the entire va_list struct:
2400 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2401 return DAG.getMemcpy(Op.getOperand(0), Op,
2402 Op.getOperand(1), Op.getOperand(2),
2403 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
2404 false, MachinePointerInfo(), MachinePointerInfo());
2407 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2408 SelectionDAG &DAG) const {
2409 return Op.getOperand(0);
2412 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2413 SelectionDAG &DAG) const {
2414 SDValue Chain = Op.getOperand(0);
2415 SDValue Trmp = Op.getOperand(1); // trampoline
2416 SDValue FPtr = Op.getOperand(2); // nested function
2417 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2420 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2421 bool isPPC64 = (PtrVT == MVT::i64);
2422 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
2424 TargetLowering::ArgListTy Args;
2425 TargetLowering::ArgListEntry Entry;
2427 Entry.Ty = IntPtrTy;
2428 Entry.Node = Trmp; Args.push_back(Entry);
2430 // TrampSize == (isPPC64 ? 48 : 40);
2431 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
2432 isPPC64 ? MVT::i64 : MVT::i32);
2433 Args.push_back(Entry);
2435 Entry.Node = FPtr; Args.push_back(Entry);
2436 Entry.Node = Nest; Args.push_back(Entry);
2438 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2439 TargetLowering::CallLoweringInfo CLI(DAG);
2440 CLI.setDebugLoc(dl).setChain(Chain)
2441 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2442 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2443 std::move(Args), 0);
2445 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2446 return CallResult.second;
2449 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2450 const PPCSubtarget &Subtarget) const {
2451 MachineFunction &MF = DAG.getMachineFunction();
2452 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2456 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2457 // vastart just stores the address of the VarArgsFrameIndex slot into the
2458 // memory location argument.
2459 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2460 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2461 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2462 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2463 MachinePointerInfo(SV),
2467 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2468 // We suppose the given va_list is already allocated.
2471 // char gpr; /* index into the array of 8 GPRs
2472 // * stored in the register save area
2473 // * gpr=0 corresponds to r3,
2474 // * gpr=1 to r4, etc.
2476 // char fpr; /* index into the array of 8 FPRs
2477 // * stored in the register save area
2478 // * fpr=0 corresponds to f1,
2479 // * fpr=1 to f2, etc.
2481 // char *overflow_arg_area;
2482 // /* location on stack that holds
2483 // * the next overflow argument
2485 // char *reg_save_area;
2486 // /* where r3:r10 and f1:f8 (if saved)
2491 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
2492 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
2494 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2496 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2498 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2501 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2502 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
2504 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2505 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
2507 uint64_t FPROffset = 1;
2508 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
2510 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2512 // Store first byte : number of int regs
2513 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2515 MachinePointerInfo(SV),
2516 MVT::i8, false, false, 0);
2517 uint64_t nextOffset = FPROffset;
2518 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2521 // Store second byte : number of float regs
2522 SDValue secondStore =
2523 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2524 MachinePointerInfo(SV, nextOffset), MVT::i8,
2526 nextOffset += StackOffset;
2527 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2529 // Store second word : arguments given on stack
2530 SDValue thirdStore =
2531 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2532 MachinePointerInfo(SV, nextOffset),
2534 nextOffset += FrameOffset;
2535 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2537 // Store third word : arguments given in registers
2538 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2539 MachinePointerInfo(SV, nextOffset),
2544 #include "PPCGenCallingConv.inc"
2546 // Function whose sole purpose is to kill compiler warnings
2547 // stemming from unused functions included from PPCGenCallingConv.inc.
2548 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2549 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2552 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2553 CCValAssign::LocInfo &LocInfo,
2554 ISD::ArgFlagsTy &ArgFlags,
2559 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2561 CCValAssign::LocInfo &LocInfo,
2562 ISD::ArgFlagsTy &ArgFlags,
2564 static const MCPhysReg ArgRegs[] = {
2565 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2566 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2568 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2570 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2572 // Skip one register if the first unallocated register has an even register
2573 // number and there are still argument registers available which have not been
2574 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2575 // need to skip a register if RegNum is odd.
2576 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2577 State.AllocateReg(ArgRegs[RegNum]);
2580 // Always return false here, as this function only makes sure that the first
2581 // unallocated register has an odd register number and does not actually
2582 // allocate a register for the current argument.
2586 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2588 CCValAssign::LocInfo &LocInfo,
2589 ISD::ArgFlagsTy &ArgFlags,
2591 static const MCPhysReg ArgRegs[] = {
2592 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2596 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2598 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2600 // If there is only one Floating-point register left we need to put both f64
2601 // values of a split ppc_fp128 value on the stack.
2602 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2603 State.AllocateReg(ArgRegs[RegNum]);
2606 // Always return false here, as this function only makes sure that the two f64
2607 // values a ppc_fp128 value is split into are both passed in registers or both
2608 // passed on the stack and does not actually allocate a register for the
2609 // current argument.
2613 /// FPR - The set of FP registers that should be allocated for arguments,
2615 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
2616 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
2617 PPC::F11, PPC::F12, PPC::F13};
2619 /// QFPR - The set of QPX registers that should be allocated for arguments.
2620 static const MCPhysReg QFPR[] = {
2621 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
2622 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
2624 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2626 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2627 unsigned PtrByteSize) {
2628 unsigned ArgSize = ArgVT.getStoreSize();
2629 if (Flags.isByVal())
2630 ArgSize = Flags.getByValSize();
2632 // Round up to multiples of the pointer size, except for array members,
2633 // which are always packed.
2634 if (!Flags.isInConsecutiveRegs())
2635 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2640 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2642 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2643 ISD::ArgFlagsTy Flags,
2644 unsigned PtrByteSize) {
2645 unsigned Align = PtrByteSize;
2647 // Altivec parameters are padded to a 16 byte boundary.
2648 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2649 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2650 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2651 ArgVT == MVT::v1i128)
2653 // QPX vector types stored in double-precision are padded to a 32 byte
2655 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
2658 // ByVal parameters are aligned as requested.
2659 if (Flags.isByVal()) {
2660 unsigned BVAlign = Flags.getByValAlign();
2661 if (BVAlign > PtrByteSize) {
2662 if (BVAlign % PtrByteSize != 0)
2664 "ByVal alignment is not a multiple of the pointer size");
2670 // Array members are always packed to their original alignment.
2671 if (Flags.isInConsecutiveRegs()) {
2672 // If the array member was split into multiple registers, the first
2673 // needs to be aligned to the size of the full type. (Except for
2674 // ppcf128, which is only aligned as its f64 components.)
2675 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2676 Align = OrigVT.getStoreSize();
2678 Align = ArgVT.getStoreSize();
2684 /// CalculateStackSlotUsed - Return whether this argument will use its
2685 /// stack slot (instead of being passed in registers). ArgOffset,
2686 /// AvailableFPRs, and AvailableVRs must hold the current argument
2687 /// position, and will be updated to account for this argument.
2688 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2689 ISD::ArgFlagsTy Flags,
2690 unsigned PtrByteSize,
2691 unsigned LinkageSize,
2692 unsigned ParamAreaSize,
2693 unsigned &ArgOffset,
2694 unsigned &AvailableFPRs,
2695 unsigned &AvailableVRs, bool HasQPX) {
2696 bool UseMemory = false;
2698 // Respect alignment of argument on the stack.
2700 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2701 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2702 // If there's no space left in the argument save area, we must
2703 // use memory (this check also catches zero-sized arguments).
2704 if (ArgOffset >= LinkageSize + ParamAreaSize)
2707 // Allocate argument on the stack.
2708 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2709 if (Flags.isInConsecutiveRegsLast())
2710 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2711 // If we overran the argument save area, we must use memory
2712 // (this check catches arguments passed partially in memory)
2713 if (ArgOffset > LinkageSize + ParamAreaSize)
2716 // However, if the argument is actually passed in an FPR or a VR,
2717 // we don't use memory after all.
2718 if (!Flags.isByVal()) {
2719 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
2720 // QPX registers overlap with the scalar FP registers.
2721 (HasQPX && (ArgVT == MVT::v4f32 ||
2722 ArgVT == MVT::v4f64 ||
2723 ArgVT == MVT::v4i1)))
2724 if (AvailableFPRs > 0) {
2728 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2729 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2730 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2731 ArgVT == MVT::v1i128)
2732 if (AvailableVRs > 0) {
2741 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2742 /// ensure minimum alignment required for target.
2743 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2744 unsigned NumBytes) {
2745 unsigned TargetAlign = Lowering->getStackAlignment();
2746 unsigned AlignMask = TargetAlign - 1;
2747 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2752 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2753 CallingConv::ID CallConv, bool isVarArg,
2754 const SmallVectorImpl<ISD::InputArg>
2756 SDLoc dl, SelectionDAG &DAG,
2757 SmallVectorImpl<SDValue> &InVals)
2759 if (Subtarget.isSVR4ABI()) {
2760 if (Subtarget.isPPC64())
2761 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2764 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2767 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2773 PPCTargetLowering::LowerFormalArguments_32SVR4(
2775 CallingConv::ID CallConv, bool isVarArg,
2776 const SmallVectorImpl<ISD::InputArg>
2778 SDLoc dl, SelectionDAG &DAG,
2779 SmallVectorImpl<SDValue> &InVals) const {
2781 // 32-bit SVR4 ABI Stack Frame Layout:
2782 // +-----------------------------------+
2783 // +--> | Back chain |
2784 // | +-----------------------------------+
2785 // | | Floating-point register save area |
2786 // | +-----------------------------------+
2787 // | | General register save area |
2788 // | +-----------------------------------+
2789 // | | CR save word |
2790 // | +-----------------------------------+
2791 // | | VRSAVE save word |
2792 // | +-----------------------------------+
2793 // | | Alignment padding |
2794 // | +-----------------------------------+
2795 // | | Vector register save area |
2796 // | +-----------------------------------+
2797 // | | Local variable space |
2798 // | +-----------------------------------+
2799 // | | Parameter list area |
2800 // | +-----------------------------------+
2801 // | | LR save word |
2802 // | +-----------------------------------+
2803 // SP--> +--- | Back chain |
2804 // +-----------------------------------+
2807 // System V Application Binary Interface PowerPC Processor Supplement
2808 // AltiVec Technology Programming Interface Manual
2810 MachineFunction &MF = DAG.getMachineFunction();
2811 MachineFrameInfo *MFI = MF.getFrameInfo();
2812 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2814 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2815 // Potential tail calls could cause overwriting of argument stack slots.
2816 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2817 (CallConv == CallingConv::Fast));
2818 unsigned PtrByteSize = 4;
2820 // Assign locations to all of the incoming arguments.
2821 SmallVector<CCValAssign, 16> ArgLocs;
2822 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2825 // Reserve space for the linkage area on the stack.
2826 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
2827 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2829 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2831 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2832 CCValAssign &VA = ArgLocs[i];
2834 // Arguments stored in registers.
2835 if (VA.isRegLoc()) {
2836 const TargetRegisterClass *RC;
2837 EVT ValVT = VA.getValVT();
2839 switch (ValVT.getSimpleVT().SimpleTy) {
2841 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2844 RC = &PPC::GPRCRegClass;
2847 if (Subtarget.hasP8Vector())
2848 RC = &PPC::VSSRCRegClass;
2850 RC = &PPC::F4RCRegClass;
2853 if (Subtarget.hasVSX())
2854 RC = &PPC::VSFRCRegClass;
2856 RC = &PPC::F8RCRegClass;
2861 RC = &PPC::VRRCRegClass;
2864 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
2868 RC = &PPC::VSHRCRegClass;
2871 RC = &PPC::QFRCRegClass;
2874 RC = &PPC::QBRCRegClass;
2878 // Transform the arguments stored in physical registers into virtual ones.
2879 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2880 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2881 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2883 if (ValVT == MVT::i1)
2884 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2886 InVals.push_back(ArgValue);
2888 // Argument stored in memory.
2889 assert(VA.isMemLoc());
2891 unsigned ArgSize = VA.getLocVT().getStoreSize();
2892 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2895 // Create load nodes to retrieve arguments from the stack.
2896 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2897 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2898 MachinePointerInfo(),
2899 false, false, false, 0));
2903 // Assign locations to all of the incoming aggregate by value arguments.
2904 // Aggregates passed by value are stored in the local variable space of the
2905 // caller's stack frame, right above the parameter list area.
2906 SmallVector<CCValAssign, 16> ByValArgLocs;
2907 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2908 ByValArgLocs, *DAG.getContext());
2910 // Reserve stack space for the allocations in CCInfo.
2911 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2913 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2915 // Area that is at least reserved in the caller of this function.
2916 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2917 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2919 // Set the size that is at least reserved in caller of this function. Tail
2920 // call optimized function's reserved stack space needs to be aligned so that
2921 // taking the difference between two stack areas will result in an aligned
2924 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2925 FuncInfo->setMinReservedArea(MinReservedArea);
2927 SmallVector<SDValue, 8> MemOps;
2929 // If the function takes variable number of arguments, make a frame index for
2930 // the start of the first vararg value... for expansion of llvm.va_start.
2932 static const MCPhysReg GPArgRegs[] = {
2933 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2934 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2936 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2938 static const MCPhysReg FPArgRegs[] = {
2939 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2942 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2943 if (DisablePPCFloatInVariadic)
2946 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
2947 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
2949 // Make room for NumGPArgRegs and NumFPArgRegs.
2950 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2951 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2953 FuncInfo->setVarArgsStackOffset(
2954 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2955 CCInfo.getNextStackOffset(), true));
2957 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2958 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2960 // The fixed integer arguments of a variadic function are stored to the
2961 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2962 // the result of va_next.
2963 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2964 // Get an existing live-in vreg, or add a new one.
2965 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2967 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2969 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2970 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2971 MachinePointerInfo(), false, false, 0);
2972 MemOps.push_back(Store);
2973 // Increment the address by four for the next argument to store
2974 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
2975 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2978 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2980 // The double arguments are stored to the VarArgsFrameIndex
2982 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2983 // Get an existing live-in vreg, or add a new one.
2984 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2986 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2988 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2989 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2990 MachinePointerInfo(), false, false, 0);
2991 MemOps.push_back(Store);
2992 // Increment the address by eight for the next argument to store
2993 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
2995 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2999 if (!MemOps.empty())
3000 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3005 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3006 // value to MVT::i64 and then truncate to the correct register size.
3008 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
3009 SelectionDAG &DAG, SDValue ArgVal,
3012 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
3013 DAG.getValueType(ObjectVT));
3014 else if (Flags.isZExt())
3015 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3016 DAG.getValueType(ObjectVT));
3018 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3022 PPCTargetLowering::LowerFormalArguments_64SVR4(
3024 CallingConv::ID CallConv, bool isVarArg,
3025 const SmallVectorImpl<ISD::InputArg>
3027 SDLoc dl, SelectionDAG &DAG,
3028 SmallVectorImpl<SDValue> &InVals) const {
3029 // TODO: add description of PPC stack frame format, or at least some docs.
3031 bool isELFv2ABI = Subtarget.isELFv2ABI();
3032 bool isLittleEndian = Subtarget.isLittleEndian();
3033 MachineFunction &MF = DAG.getMachineFunction();
3034 MachineFrameInfo *MFI = MF.getFrameInfo();
3035 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3037 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
3038 "fastcc not supported on varargs functions");
3040 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
3041 // Potential tail calls could cause overwriting of argument stack slots.
3042 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3043 (CallConv == CallingConv::Fast));
3044 unsigned PtrByteSize = 8;
3045 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3047 static const MCPhysReg GPR[] = {
3048 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3049 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3051 static const MCPhysReg VR[] = {
3052 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3053 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3055 static const MCPhysReg VSRH[] = {
3056 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
3057 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
3060 const unsigned Num_GPR_Regs = array_lengthof(GPR);
3061 const unsigned Num_FPR_Regs = 13;
3062 const unsigned Num_VR_Regs = array_lengthof(VR);
3063 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3065 // Do a first pass over the arguments to determine whether the ABI
3066 // guarantees that our caller has allocated the parameter save area
3067 // on its stack frame. In the ELFv1 ABI, this is always the case;
3068 // in the ELFv2 ABI, it is true if this is a vararg function or if
3069 // any parameter is located in a stack slot.
3071 bool HasParameterArea = !isELFv2ABI || isVarArg;
3072 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3073 unsigned NumBytes = LinkageSize;
3074 unsigned AvailableFPRs = Num_FPR_Regs;
3075 unsigned AvailableVRs = Num_VR_Regs;
3076 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3077 if (Ins[i].Flags.isNest())
3080 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3081 PtrByteSize, LinkageSize, ParamAreaSize,
3082 NumBytes, AvailableFPRs, AvailableVRs,
3083 Subtarget.hasQPX()))
3084 HasParameterArea = true;
3087 // Add DAG nodes to load the arguments or copy them out of registers. On
3088 // entry to a function on PPC, the arguments start after the linkage area,
3089 // although the first ones are often in registers.
3091 unsigned ArgOffset = LinkageSize;
3092 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3093 unsigned &QFPR_idx = FPR_idx;
3094 SmallVector<SDValue, 8> MemOps;
3095 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3096 unsigned CurArgIdx = 0;
3097 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3099 bool needsLoad = false;
3100 EVT ObjectVT = Ins[ArgNo].VT;
3101 EVT OrigVT = Ins[ArgNo].ArgVT;
3102 unsigned ObjSize = ObjectVT.getStoreSize();
3103 unsigned ArgSize = ObjSize;
3104 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3105 if (Ins[ArgNo].isOrigArg()) {
3106 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3107 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3109 // We re-align the argument offset for each argument, except when using the
3110 // fast calling convention, when we need to make sure we do that only when
3111 // we'll actually use a stack slot.
3112 unsigned CurArgOffset, Align;
3113 auto ComputeArgOffset = [&]() {
3114 /* Respect alignment of argument on the stack. */
3115 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
3116 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3117 CurArgOffset = ArgOffset;
3120 if (CallConv != CallingConv::Fast) {
3123 /* Compute GPR index associated with argument offset. */
3124 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3125 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
3128 // FIXME the codegen can be much improved in some cases.
3129 // We do not have to keep everything in memory.
3130 if (Flags.isByVal()) {
3131 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3133 if (CallConv == CallingConv::Fast)
3136 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3137 ObjSize = Flags.getByValSize();
3138 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3139 // Empty aggregate parameters do not take up registers. Examples:
3143 // etc. However, we have to provide a place-holder in InVals, so
3144 // pretend we have an 8-byte item at the current address for that
3147 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3148 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3149 InVals.push_back(FIN);
3153 // Create a stack object covering all stack doublewords occupied
3154 // by the argument. If the argument is (fully or partially) on
3155 // the stack, or if the argument is fully in registers but the
3156 // caller has allocated the parameter save anyway, we can refer
3157 // directly to the caller's stack frame. Otherwise, create a
3158 // local copy in our own frame.
3160 if (HasParameterArea ||
3161 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
3162 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
3164 FI = MFI->CreateStackObject(ArgSize, Align, false);
3165 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3167 // Handle aggregates smaller than 8 bytes.
3168 if (ObjSize < PtrByteSize) {
3169 // The value of the object is its address, which differs from the
3170 // address of the enclosing doubleword on big-endian systems.
3172 if (!isLittleEndian) {
3173 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
3174 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3176 InVals.push_back(Arg);
3178 if (GPR_idx != Num_GPR_Regs) {
3179 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3180 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3183 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3184 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3185 (ObjSize == 2 ? MVT::i16 : MVT::i32));
3186 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3187 MachinePointerInfo(&*FuncArg), ObjType,
3190 // For sizes that don't fit a truncating store (3, 5, 6, 7),
3191 // store the whole register as-is to the parameter save area
3194 DAG.getStore(Val.getValue(1), dl, Val, FIN,
3195 MachinePointerInfo(&*FuncArg), false, false, 0);
3198 MemOps.push_back(Store);
3200 // Whether we copied from a register or not, advance the offset
3201 // into the parameter save area by a full doubleword.
3202 ArgOffset += PtrByteSize;
3206 // The value of the object is its address, which is the address of
3207 // its first stack doubleword.
3208 InVals.push_back(FIN);
3210 // Store whatever pieces of the object are in registers to memory.
3211 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3212 if (GPR_idx == Num_GPR_Regs)
3215 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3216 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3219 SDValue Off = DAG.getConstant(j, dl, PtrVT);
3220 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3223 DAG.getStore(Val.getValue(1), dl, Val, Addr,
3224 MachinePointerInfo(&*FuncArg, j), false, false, 0);
3225 MemOps.push_back(Store);
3228 ArgOffset += ArgSize;
3232 switch (ObjectVT.getSimpleVT().SimpleTy) {
3233 default: llvm_unreachable("Unhandled argument type!");
3237 if (Flags.isNest()) {
3238 // The 'nest' parameter, if any, is passed in R11.
3239 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
3240 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3242 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3243 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3248 // These can be scalar arguments or elements of an integer array type
3249 // passed directly. Clang may use those instead of "byval" aggregate
3250 // types to avoid forcing arguments to memory unnecessarily.
3251 if (GPR_idx != Num_GPR_Regs) {
3252 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3253 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3255 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3256 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3257 // value to MVT::i64 and then truncate to the correct register size.
3258 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3260 if (CallConv == CallingConv::Fast)
3264 ArgSize = PtrByteSize;
3266 if (CallConv != CallingConv::Fast || needsLoad)
3272 // These can be scalar arguments or elements of a float array type
3273 // passed directly. The latter are used to implement ELFv2 homogenous
3274 // float aggregates.
3275 if (FPR_idx != Num_FPR_Regs) {
3278 if (ObjectVT == MVT::f32)
3279 VReg = MF.addLiveIn(FPR[FPR_idx],
3280 Subtarget.hasP8Vector()
3281 ? &PPC::VSSRCRegClass
3282 : &PPC::F4RCRegClass);
3284 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3285 ? &PPC::VSFRCRegClass
3286 : &PPC::F8RCRegClass);
3288 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3290 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3291 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3292 // once we support fp <-> gpr moves.
3294 // This can only ever happen in the presence of f32 array types,
3295 // since otherwise we never run out of FPRs before running out
3297 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3298 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3300 if (ObjectVT == MVT::f32) {
3301 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3302 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3303 DAG.getConstant(32, dl, MVT::i32));
3304 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3307 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3309 if (CallConv == CallingConv::Fast)
3315 // When passing an array of floats, the array occupies consecutive
3316 // space in the argument area; only round up to the next doubleword
3317 // at the end of the array. Otherwise, each float takes 8 bytes.
3318 if (CallConv != CallingConv::Fast || needsLoad) {
3319 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3320 ArgOffset += ArgSize;
3321 if (Flags.isInConsecutiveRegsLast())
3322 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3332 if (!Subtarget.hasQPX()) {
3333 // These can be scalar arguments or elements of a vector array type
3334 // passed directly. The latter are used to implement ELFv2 homogenous
3335 // vector aggregates.
3336 if (VR_idx != Num_VR_Regs) {
3337 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
3338 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
3339 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3340 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3343 if (CallConv == CallingConv::Fast)
3348 if (CallConv != CallingConv::Fast || needsLoad)
3353 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
3354 "Invalid QPX parameter type");
3359 // QPX vectors are treated like their scalar floating-point subregisters
3360 // (except that they're larger).
3361 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3362 if (QFPR_idx != Num_QFPR_Regs) {
3363 const TargetRegisterClass *RC;
3364 switch (ObjectVT.getSimpleVT().SimpleTy) {
3365 case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3366 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3367 default: RC = &PPC::QBRCRegClass; break;
3370 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3371 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3374 if (CallConv == CallingConv::Fast)
3378 if (CallConv != CallingConv::Fast || needsLoad)
3383 // We need to load the argument to a virtual register if we determined
3384 // above that we ran out of physical registers of the appropriate type.
3386 if (ObjSize < ArgSize && !isLittleEndian)
3387 CurArgOffset += ArgSize - ObjSize;
3388 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
3389 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3390 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3391 false, false, false, 0);
3394 InVals.push_back(ArgVal);
3397 // Area that is at least reserved in the caller of this function.
3398 unsigned MinReservedArea;
3399 if (HasParameterArea)
3400 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
3402 MinReservedArea = LinkageSize;
3404 // Set the size that is at least reserved in caller of this function. Tail
3405 // call optimized functions' reserved stack space needs to be aligned so that
3406 // taking the difference between two stack areas will result in an aligned
3409 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3410 FuncInfo->setMinReservedArea(MinReservedArea);
3412 // If the function takes variable number of arguments, make a frame index for
3413 // the start of the first vararg value... for expansion of llvm.va_start.
3415 int Depth = ArgOffset;
3417 FuncInfo->setVarArgsFrameIndex(
3418 MFI->CreateFixedObject(PtrByteSize, Depth, true));
3419 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3421 // If this function is vararg, store any remaining integer argument regs
3422 // to their spots on the stack so that they may be loaded by deferencing the
3423 // result of va_next.
3424 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3425 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
3426 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3427 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3428 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3429 MachinePointerInfo(), false, false, 0);
3430 MemOps.push_back(Store);
3431 // Increment the address by four for the next argument to store
3432 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
3433 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3437 if (!MemOps.empty())
3438 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3444 PPCTargetLowering::LowerFormalArguments_Darwin(
3446 CallingConv::ID CallConv, bool isVarArg,
3447 const SmallVectorImpl<ISD::InputArg>
3449 SDLoc dl, SelectionDAG &DAG,
3450 SmallVectorImpl<SDValue> &InVals) const {
3451 // TODO: add description of PPC stack frame format, or at least some docs.
3453 MachineFunction &MF = DAG.getMachineFunction();
3454 MachineFrameInfo *MFI = MF.getFrameInfo();
3455 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3457 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
3458 bool isPPC64 = PtrVT == MVT::i64;
3459 // Potential tail calls could cause overwriting of argument stack slots.
3460 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3461 (CallConv == CallingConv::Fast));
3462 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3463 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3464 unsigned ArgOffset = LinkageSize;
3465 // Area that is at least reserved in caller of this function.
3466 unsigned MinReservedArea = ArgOffset;
3468 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3469 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3470 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3472 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3473 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3474 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3476 static const MCPhysReg VR[] = {
3477 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3478 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3481 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3482 const unsigned Num_FPR_Regs = 13;
3483 const unsigned Num_VR_Regs = array_lengthof( VR);
3485 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3487 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3489 // In 32-bit non-varargs functions, the stack space for vectors is after the
3490 // stack space for non-vectors. We do not use this space unless we have
3491 // too many vectors to fit in registers, something that only occurs in
3492 // constructed examples:), but we have to walk the arglist to figure
3493 // that out...for the pathological case, compute VecArgOffset as the
3494 // start of the vector parameter area. Computing VecArgOffset is the
3495 // entire point of the following loop.
3496 unsigned VecArgOffset = ArgOffset;
3497 if (!isVarArg && !isPPC64) {
3498 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3500 EVT ObjectVT = Ins[ArgNo].VT;
3501 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3503 if (Flags.isByVal()) {
3504 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3505 unsigned ObjSize = Flags.getByValSize();
3507 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3508 VecArgOffset += ArgSize;
3512 switch(ObjectVT.getSimpleVT().SimpleTy) {
3513 default: llvm_unreachable("Unhandled argument type!");
3519 case MVT::i64: // PPC64
3521 // FIXME: We are guaranteed to be !isPPC64 at this point.
3522 // Does MVT::i64 apply?
3529 // Nothing to do, we're only looking at Nonvector args here.
3534 // We've found where the vector parameter area in memory is. Skip the
3535 // first 12 parameters; these don't use that memory.
3536 VecArgOffset = ((VecArgOffset+15)/16)*16;
3537 VecArgOffset += 12*16;
3539 // Add DAG nodes to load the arguments or copy them out of registers. On
3540 // entry to a function on PPC, the arguments start after the linkage area,
3541 // although the first ones are often in registers.
3543 SmallVector<SDValue, 8> MemOps;
3544 unsigned nAltivecParamsAtEnd = 0;
3545 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3546 unsigned CurArgIdx = 0;
3547 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3549 bool needsLoad = false;
3550 EVT ObjectVT = Ins[ArgNo].VT;
3551 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3552 unsigned ArgSize = ObjSize;
3553 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3554 if (Ins[ArgNo].isOrigArg()) {
3555 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3556 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3558 unsigned CurArgOffset = ArgOffset;
3560 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3561 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3562 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3563 if (isVarArg || isPPC64) {
3564 MinReservedArea = ((MinReservedArea+15)/16)*16;
3565 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3568 } else nAltivecParamsAtEnd++;
3570 // Calculate min reserved area.
3571 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3575 // FIXME the codegen can be much improved in some cases.
3576 // We do not have to keep everything in memory.
3577 if (Flags.isByVal()) {
3578 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3580 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3581 ObjSize = Flags.getByValSize();
3582 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3583 // Objects of size 1 and 2 are right justified, everything else is
3584 // left justified. This means the memory address is adjusted forwards.
3585 if (ObjSize==1 || ObjSize==2) {
3586 CurArgOffset = CurArgOffset + (4 - ObjSize);
3588 // The value of the object is its address.
3589 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3590 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3591 InVals.push_back(FIN);
3592 if (ObjSize==1 || ObjSize==2) {
3593 if (GPR_idx != Num_GPR_Regs) {
3596 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3598 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3599 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3600 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3601 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3602 MachinePointerInfo(&*FuncArg),
3603 ObjType, false, false, 0);
3604 MemOps.push_back(Store);
3608 ArgOffset += PtrByteSize;
3612 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3613 // Store whatever pieces of the object are in registers
3614 // to memory. ArgOffset will be the address of the beginning
3616 if (GPR_idx != Num_GPR_Regs) {
3619 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3621 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3622 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3623 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3624 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3626 DAG.getStore(Val.getValue(1), dl, Val, FIN,
3627 MachinePointerInfo(&*FuncArg, j), false, false, 0);
3628 MemOps.push_back(Store);
3630 ArgOffset += PtrByteSize;
3632 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3639 switch (ObjectVT.getSimpleVT().SimpleTy) {
3640 default: llvm_unreachable("Unhandled argument type!");
3644 if (GPR_idx != Num_GPR_Regs) {
3645 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3646 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3648 if (ObjectVT == MVT::i1)
3649 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3654 ArgSize = PtrByteSize;
3656 // All int arguments reserve stack space in the Darwin ABI.
3657 ArgOffset += PtrByteSize;
3661 case MVT::i64: // PPC64
3662 if (GPR_idx != Num_GPR_Regs) {
3663 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3664 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3666 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3667 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3668 // value to MVT::i64 and then truncate to the correct register size.
3669 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3674 ArgSize = PtrByteSize;
3676 // All int arguments reserve stack space in the Darwin ABI.
3682 // Every 4 bytes of argument space consumes one of the GPRs available for
3683 // argument passing.
3684 if (GPR_idx != Num_GPR_Regs) {
3686 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3689 if (FPR_idx != Num_FPR_Regs) {
3692 if (ObjectVT == MVT::f32)
3693 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3695 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3697 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3703 // All FP arguments reserve stack space in the Darwin ABI.
3704 ArgOffset += isPPC64 ? 8 : ObjSize;
3710 // Note that vector arguments in registers don't reserve stack space,
3711 // except in varargs functions.
3712 if (VR_idx != Num_VR_Regs) {
3713 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3714 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3716 while ((ArgOffset % 16) != 0) {
3717 ArgOffset += PtrByteSize;
3718 if (GPR_idx != Num_GPR_Regs)
3722 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3726 if (!isVarArg && !isPPC64) {
3727 // Vectors go after all the nonvectors.
3728 CurArgOffset = VecArgOffset;
3731 // Vectors are aligned.
3732 ArgOffset = ((ArgOffset+15)/16)*16;
3733 CurArgOffset = ArgOffset;
3741 // We need to load the argument to a virtual register if we determined above
3742 // that we ran out of physical registers of the appropriate type.
3744 int FI = MFI->CreateFixedObject(ObjSize,
3745 CurArgOffset + (ArgSize - ObjSize),
3747 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3748 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3749 false, false, false, 0);
3752 InVals.push_back(ArgVal);
3755 // Allow for Altivec parameters at the end, if needed.
3756 if (nAltivecParamsAtEnd) {
3757 MinReservedArea = ((MinReservedArea+15)/16)*16;
3758 MinReservedArea += 16*nAltivecParamsAtEnd;
3761 // Area that is at least reserved in the caller of this function.
3762 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3764 // Set the size that is at least reserved in caller of this function. Tail
3765 // call optimized functions' reserved stack space needs to be aligned so that
3766 // taking the difference between two stack areas will result in an aligned
3769 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3770 FuncInfo->setMinReservedArea(MinReservedArea);
3772 // If the function takes variable number of arguments, make a frame index for
3773 // the start of the first vararg value... for expansion of llvm.va_start.
3775 int Depth = ArgOffset;
3777 FuncInfo->setVarArgsFrameIndex(
3778 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3780 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3782 // If this function is vararg, store any remaining integer argument regs
3783 // to their spots on the stack so that they may be loaded by deferencing the
3784 // result of va_next.
3785 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3789 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3791 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3793 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3794 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3795 MachinePointerInfo(), false, false, 0);
3796 MemOps.push_back(Store);
3797 // Increment the address by four for the next argument to store
3798 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3799 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3803 if (!MemOps.empty())
3804 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3809 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3810 /// adjusted to accommodate the arguments for the tailcall.
3811 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3812 unsigned ParamSize) {
3814 if (!isTailCall) return 0;
3816 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3817 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3818 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3819 // Remember only if the new adjustement is bigger.
3820 if (SPDiff < FI->getTailCallSPDelta())
3821 FI->setTailCallSPDelta(SPDiff);
3826 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3827 /// for tail call optimization. Targets which want to do tail call
3828 /// optimization should implement this function.
3830 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3831 CallingConv::ID CalleeCC,
3833 const SmallVectorImpl<ISD::InputArg> &Ins,
3834 SelectionDAG& DAG) const {
3835 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3838 // Variable argument functions are not supported.
3842 MachineFunction &MF = DAG.getMachineFunction();
3843 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3844 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3845 // Functions containing by val parameters are not supported.
3846 for (unsigned i = 0; i != Ins.size(); i++) {
3847 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3848 if (Flags.isByVal()) return false;
3851 // Non-PIC/GOT tail calls are supported.
3852 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3855 // At the moment we can only do local tail calls (in same module, hidden
3856 // or protected) if we are generating PIC.
3857 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3858 return G->getGlobal()->hasHiddenVisibility()
3859 || G->getGlobal()->hasProtectedVisibility();
3865 /// isCallCompatibleAddress - Return the immediate to use if the specified
3866 /// 32-bit value is representable in the immediate field of a BxA instruction.
3867 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3868 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3869 if (!C) return nullptr;
3871 int Addr = C->getZExtValue();
3872 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3873 SignExtend32<26>(Addr) != Addr)
3874 return nullptr; // Top 6 bits have to be sext of immediate.
3876 return DAG.getConstant((int)C->getZExtValue() >> 2, SDLoc(Op),
3877 DAG.getTargetLoweringInfo().getPointerTy(
3878 DAG.getDataLayout())).getNode();
3883 struct TailCallArgumentInfo {
3888 TailCallArgumentInfo() : FrameIdx(0) {}
3892 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3894 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3896 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3897 SmallVectorImpl<SDValue> &MemOpChains,
3899 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3900 SDValue Arg = TailCallArgs[i].Arg;
3901 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3902 int FI = TailCallArgs[i].FrameIdx;
3903 // Store relative to framepointer.
3904 MemOpChains.push_back(DAG.getStore(
3905 Chain, dl, Arg, FIN,
3906 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
3911 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3912 /// the appropriate stack slot for the tail call optimized function call.
3913 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3914 MachineFunction &MF,
3923 // Calculate the new stack slot for the return address.
3924 int SlotSize = isPPC64 ? 8 : 4;
3925 const PPCFrameLowering *FL =
3926 MF.getSubtarget<PPCSubtarget>().getFrameLowering();
3927 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
3928 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3929 NewRetAddrLoc, true);
3930 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3931 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3932 Chain = DAG.getStore(
3933 Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3934 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), NewRetAddr),
3937 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3938 // slot as the FP is never overwritten.
3940 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
3941 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3943 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3944 Chain = DAG.getStore(
3945 Chain, dl, OldFP, NewFramePtrIdx,
3946 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), NewFPIdx),
3953 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3954 /// the position of the argument.
3956 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3957 SDValue Arg, int SPDiff, unsigned ArgOffset,
3958 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3959 int Offset = ArgOffset + SPDiff;
3960 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3961 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3962 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3963 SDValue FIN = DAG.getFrameIndex(FI, VT);
3964 TailCallArgumentInfo Info;
3966 Info.FrameIdxOp = FIN;
3968 TailCallArguments.push_back(Info);
3971 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3972 /// stack slot. Returns the chain as result and the loaded frame pointers in
3973 /// LROpOut/FPOpout. Used when tail calling.
3974 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3982 // Load the LR and FP stack slot for later adjusting.
3983 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3984 LROpOut = getReturnAddrFrameIndex(DAG);
3985 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3986 false, false, false, 0);
3987 Chain = SDValue(LROpOut.getNode(), 1);
3989 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3990 // slot as the FP is never overwritten.
3992 FPOpOut = getFramePointerFrameIndex(DAG);
3993 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3994 false, false, false, 0);
3995 Chain = SDValue(FPOpOut.getNode(), 1);
4001 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
4002 /// by "Src" to address "Dst" of size "Size". Alignment information is
4003 /// specified by the specific parameter attribute. The copy will be passed as
4004 /// a byval function parameter.
4005 /// Sometimes what we are copying is the end of a larger object, the part that
4006 /// does not fit in registers.
4008 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
4009 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
4011 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
4012 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
4013 false, false, false, MachinePointerInfo(),
4014 MachinePointerInfo());
4017 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
4020 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
4021 SDValue Arg, SDValue PtrOff, int SPDiff,
4022 unsigned ArgOffset, bool isPPC64, bool isTailCall,
4023 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
4024 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
4026 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4031 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4033 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4034 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4035 DAG.getConstant(ArgOffset, dl, PtrVT));
4037 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4038 MachinePointerInfo(), false, false, 0));
4039 // Calculate and remember argument location.
4040 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
4045 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
4046 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
4047 SDValue LROp, SDValue FPOp, bool isDarwinABI,
4048 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
4049 MachineFunction &MF = DAG.getMachineFunction();
4051 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
4052 // might overwrite each other in case of tail call optimization.
4053 SmallVector<SDValue, 8> MemOpChains2;
4054 // Do not flag preceding copytoreg stuff together with the following stuff.
4056 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
4058 if (!MemOpChains2.empty())
4059 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4061 // Store the return address to the appropriate stack slot.
4062 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
4063 isPPC64, isDarwinABI, dl);
4065 // Emit callseq_end just before tailcall node.
4066 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4067 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4068 InFlag = Chain.getValue(1);
4071 // Is this global address that of a function that can be called by name? (as
4072 // opposed to something that must hold a descriptor for an indirect call).
4073 static bool isFunctionGlobalAddress(SDValue Callee) {
4074 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
4075 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
4076 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
4079 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
4086 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
4087 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
4088 bool isTailCall, bool IsPatchPoint, bool hasNest,
4089 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
4090 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
4091 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
4093 bool isPPC64 = Subtarget.isPPC64();
4094 bool isSVR4ABI = Subtarget.isSVR4ABI();
4095 bool isELFv2ABI = Subtarget.isELFv2ABI();
4097 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4098 NodeTys.push_back(MVT::Other); // Returns a chain
4099 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
4101 unsigned CallOpc = PPCISD::CALL;
4103 bool needIndirectCall = true;
4104 if (!isSVR4ABI || !isPPC64)
4105 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
4106 // If this is an absolute destination address, use the munged value.
4107 Callee = SDValue(Dest, 0);
4108 needIndirectCall = false;
4111 if (isFunctionGlobalAddress(Callee)) {
4112 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
4113 // A call to a TLS address is actually an indirect call to a
4114 // thread-specific pointer.
4115 unsigned OpFlags = 0;
4116 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4117 (Subtarget.getTargetTriple().isMacOSX() &&
4118 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
4119 !G->getGlobal()->isStrongDefinitionForLinker()) ||
4120 (Subtarget.isTargetELF() && !isPPC64 &&
4121 !G->getGlobal()->hasLocalLinkage() &&
4122 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4123 // PC-relative references to external symbols should go through $stub,
4124 // unless we're building with the leopard linker or later, which
4125 // automatically synthesizes these stubs.
4126 OpFlags = PPCII::MO_PLT_OR_STUB;
4129 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
4130 // every direct call is) turn it into a TargetGlobalAddress /
4131 // TargetExternalSymbol node so that legalize doesn't hack it.
4132 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
4133 Callee.getValueType(), 0, OpFlags);
4134 needIndirectCall = false;
4137 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
4138 unsigned char OpFlags = 0;
4140 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4141 (Subtarget.getTargetTriple().isMacOSX() &&
4142 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
4143 (Subtarget.isTargetELF() && !isPPC64 &&
4144 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4145 // PC-relative references to external symbols should go through $stub,
4146 // unless we're building with the leopard linker or later, which
4147 // automatically synthesizes these stubs.
4148 OpFlags = PPCII::MO_PLT_OR_STUB;
4151 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
4153 needIndirectCall = false;
4157 // We'll form an invalid direct call when lowering a patchpoint; the full
4158 // sequence for an indirect call is complicated, and many of the
4159 // instructions introduced might have side effects (and, thus, can't be
4160 // removed later). The call itself will be removed as soon as the
4161 // argument/return lowering is complete, so the fact that it has the wrong
4162 // kind of operands should not really matter.
4163 needIndirectCall = false;
4166 if (needIndirectCall) {
4167 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
4168 // to do the call, we can't use PPCISD::CALL.
4169 SDValue MTCTROps[] = {Chain, Callee, InFlag};
4171 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
4172 // Function pointers in the 64-bit SVR4 ABI do not point to the function
4173 // entry point, but to the function descriptor (the function entry point
4174 // address is part of the function descriptor though).
4175 // The function descriptor is a three doubleword structure with the
4176 // following fields: function entry point, TOC base address and
4177 // environment pointer.
4178 // Thus for a call through a function pointer, the following actions need
4180 // 1. Save the TOC of the caller in the TOC save area of its stack
4181 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
4182 // 2. Load the address of the function entry point from the function
4184 // 3. Load the TOC of the callee from the function descriptor into r2.
4185 // 4. Load the environment pointer from the function descriptor into
4187 // 5. Branch to the function entry point address.
4188 // 6. On return of the callee, the TOC of the caller needs to be
4189 // restored (this is done in FinishCall()).
4191 // The loads are scheduled at the beginning of the call sequence, and the
4192 // register copies are flagged together to ensure that no other
4193 // operations can be scheduled in between. E.g. without flagging the
4194 // copies together, a TOC access in the caller could be scheduled between
4195 // the assignment of the callee TOC and the branch to the callee, which
4196 // results in the TOC access going through the TOC of the callee instead
4197 // of going through the TOC of the caller, which leads to incorrect code.
4199 // Load the address of the function entry point from the function
4201 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
4202 if (LDChain.getValueType() == MVT::Glue)
4203 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
4205 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
4207 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
4208 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
4209 false, false, LoadsInv, 8);
4211 // Load environment pointer into r11.
4212 SDValue PtrOff = DAG.getIntPtrConstant(16, dl);
4213 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
4214 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
4215 MPI.getWithOffset(16), false, false,
4218 SDValue TOCOff = DAG.getIntPtrConstant(8, dl);
4219 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
4220 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
4221 MPI.getWithOffset(8), false, false,
4224 setUsesTOCBasePtr(DAG);
4225 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
4227 Chain = TOCVal.getValue(0);
4228 InFlag = TOCVal.getValue(1);
4230 // If the function call has an explicit 'nest' parameter, it takes the
4231 // place of the environment pointer.
4233 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
4236 Chain = EnvVal.getValue(0);
4237 InFlag = EnvVal.getValue(1);
4240 MTCTROps[0] = Chain;
4241 MTCTROps[1] = LoadFuncPtr;
4242 MTCTROps[2] = InFlag;
4245 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
4246 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
4247 InFlag = Chain.getValue(1);
4250 NodeTys.push_back(MVT::Other);
4251 NodeTys.push_back(MVT::Glue);
4252 Ops.push_back(Chain);
4253 CallOpc = PPCISD::BCTRL;
4254 Callee.setNode(nullptr);
4255 // Add use of X11 (holding environment pointer)
4256 if (isSVR4ABI && isPPC64 && !isELFv2ABI && !hasNest)
4257 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
4258 // Add CTR register as callee so a bctr can be emitted later.
4260 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
4263 // If this is a direct call, pass the chain and the callee.
4264 if (Callee.getNode()) {
4265 Ops.push_back(Chain);
4266 Ops.push_back(Callee);
4268 // If this is a tail call add stack pointer delta.
4270 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
4272 // Add argument registers to the end of the list so that they are known live
4274 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4275 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4276 RegsToPass[i].second.getValueType()));
4278 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
4280 if (isSVR4ABI && isPPC64 && !IsPatchPoint) {
4281 setUsesTOCBasePtr(DAG);
4282 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
4289 bool isLocalCall(const SDValue &Callee)
4291 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4292 return G->getGlobal()->isStrongDefinitionForLinker();
4297 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
4298 CallingConv::ID CallConv, bool isVarArg,
4299 const SmallVectorImpl<ISD::InputArg> &Ins,
4300 SDLoc dl, SelectionDAG &DAG,
4301 SmallVectorImpl<SDValue> &InVals) const {
4303 SmallVector<CCValAssign, 16> RVLocs;
4304 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
4306 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
4308 // Copy all of the result registers out of their specified physreg.
4309 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4310 CCValAssign &VA = RVLocs[i];
4311 assert(VA.isRegLoc() && "Can only return in registers!");
4313 SDValue Val = DAG.getCopyFromReg(Chain, dl,
4314 VA.getLocReg(), VA.getLocVT(), InFlag);
4315 Chain = Val.getValue(1);
4316 InFlag = Val.getValue(2);
4318 switch (VA.getLocInfo()) {
4319 default: llvm_unreachable("Unknown loc info!");
4320 case CCValAssign::Full: break;
4321 case CCValAssign::AExt:
4322 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4324 case CCValAssign::ZExt:
4325 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
4326 DAG.getValueType(VA.getValVT()));
4327 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4329 case CCValAssign::SExt:
4330 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
4331 DAG.getValueType(VA.getValVT()));
4332 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4336 InVals.push_back(Val);
4343 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
4344 bool isTailCall, bool isVarArg, bool IsPatchPoint,
4345 bool hasNest, SelectionDAG &DAG,
4346 SmallVector<std::pair<unsigned, SDValue>, 8>
4348 SDValue InFlag, SDValue Chain,
4349 SDValue CallSeqStart, SDValue &Callee,
4350 int SPDiff, unsigned NumBytes,
4351 const SmallVectorImpl<ISD::InputArg> &Ins,
4352 SmallVectorImpl<SDValue> &InVals,
4353 ImmutableCallSite *CS) const {
4355 std::vector<EVT> NodeTys;
4356 SmallVector<SDValue, 8> Ops;
4357 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
4358 SPDiff, isTailCall, IsPatchPoint, hasNest,
4359 RegsToPass, Ops, NodeTys, CS, Subtarget);
4361 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
4362 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
4363 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
4365 // When performing tail call optimization the callee pops its arguments off
4366 // the stack. Account for this here so these bytes can be pushed back on in
4367 // PPCFrameLowering::eliminateCallFramePseudoInstr.
4368 int BytesCalleePops =
4369 (CallConv == CallingConv::Fast &&
4370 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
4372 // Add a register mask operand representing the call-preserved registers.
4373 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4374 const uint32_t *Mask =
4375 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
4376 assert(Mask && "Missing call preserved mask for calling convention");
4377 Ops.push_back(DAG.getRegisterMask(Mask));
4379 if (InFlag.getNode())
4380 Ops.push_back(InFlag);
4384 assert(((Callee.getOpcode() == ISD::Register &&
4385 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
4386 Callee.getOpcode() == ISD::TargetExternalSymbol ||
4387 Callee.getOpcode() == ISD::TargetGlobalAddress ||
4388 isa<ConstantSDNode>(Callee)) &&
4389 "Expecting an global address, external symbol, absolute value or register");
4391 DAG.getMachineFunction().getFrameInfo()->setHasTailCall();
4392 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
4395 // Add a NOP immediately after the branch instruction when using the 64-bit
4396 // SVR4 ABI. At link time, if caller and callee are in a different module and
4397 // thus have a different TOC, the call will be replaced with a call to a stub
4398 // function which saves the current TOC, loads the TOC of the callee and
4399 // branches to the callee. The NOP will be replaced with a load instruction
4400 // which restores the TOC of the caller from the TOC save slot of the current
4401 // stack frame. If caller and callee belong to the same module (and have the
4402 // same TOC), the NOP will remain unchanged.
4404 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
4406 if (CallOpc == PPCISD::BCTRL) {
4407 // This is a call through a function pointer.
4408 // Restore the caller TOC from the save area into R2.
4409 // See PrepareCall() for more information about calls through function
4410 // pointers in the 64-bit SVR4 ABI.
4411 // We are using a target-specific load with r2 hard coded, because the
4412 // result of a target-independent load would never go directly into r2,
4413 // since r2 is a reserved register (which prevents the register allocator
4414 // from allocating it), resulting in an additional register being
4415 // allocated and an unnecessary move instruction being generated.
4416 CallOpc = PPCISD::BCTRL_LOAD_TOC;
4418 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4419 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
4420 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
4421 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
4422 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
4424 // The address needs to go after the chain input but before the flag (or
4425 // any other variadic arguments).
4426 Ops.insert(std::next(Ops.begin()), AddTOC);
4427 } else if ((CallOpc == PPCISD::CALL) &&
4428 (!isLocalCall(Callee) ||
4429 DAG.getTarget().getRelocationModel() == Reloc::PIC_))
4430 // Otherwise insert NOP for non-local calls.
4431 CallOpc = PPCISD::CALL_NOP;
4434 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
4435 InFlag = Chain.getValue(1);
4437 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4438 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
4441 InFlag = Chain.getValue(1);
4443 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
4444 Ins, dl, DAG, InVals);
4448 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
4449 SmallVectorImpl<SDValue> &InVals) const {
4450 SelectionDAG &DAG = CLI.DAG;
4452 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
4453 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4454 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4455 SDValue Chain = CLI.Chain;
4456 SDValue Callee = CLI.Callee;
4457 bool &isTailCall = CLI.IsTailCall;
4458 CallingConv::ID CallConv = CLI.CallConv;
4459 bool isVarArg = CLI.IsVarArg;
4460 bool IsPatchPoint = CLI.IsPatchPoint;
4461 ImmutableCallSite *CS = CLI.CS;
4464 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
4467 if (!isTailCall && CS && CS->isMustTailCall())
4468 report_fatal_error("failed to perform tail call elimination on a call "
4469 "site marked musttail");
4471 if (Subtarget.isSVR4ABI()) {
4472 if (Subtarget.isPPC64())
4473 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4474 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4475 dl, DAG, InVals, CS);
4477 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4478 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4479 dl, DAG, InVals, CS);
4482 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4483 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4484 dl, DAG, InVals, CS);
4488 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4489 CallingConv::ID CallConv, bool isVarArg,
4490 bool isTailCall, bool IsPatchPoint,
4491 const SmallVectorImpl<ISD::OutputArg> &Outs,
4492 const SmallVectorImpl<SDValue> &OutVals,
4493 const SmallVectorImpl<ISD::InputArg> &Ins,
4494 SDLoc dl, SelectionDAG &DAG,
4495 SmallVectorImpl<SDValue> &InVals,
4496 ImmutableCallSite *CS) const {
4497 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4498 // of the 32-bit SVR4 ABI stack frame layout.
4500 assert((CallConv == CallingConv::C ||
4501 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4503 unsigned PtrByteSize = 4;
4505 MachineFunction &MF = DAG.getMachineFunction();
4507 // Mark this function as potentially containing a function that contains a
4508 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4509 // and restoring the callers stack pointer in this functions epilog. This is
4510 // done because by tail calling the called function might overwrite the value
4511 // in this function's (MF) stack pointer stack slot 0(SP).
4512 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4513 CallConv == CallingConv::Fast)
4514 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4516 // Count how many bytes are to be pushed on the stack, including the linkage
4517 // area, parameter list area and the part of the local variable space which
4518 // contains copies of aggregates which are passed by value.
4520 // Assign locations to all of the outgoing arguments.
4521 SmallVector<CCValAssign, 16> ArgLocs;
4522 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4525 // Reserve space for the linkage area on the stack.
4526 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
4530 // Handle fixed and variable vector arguments differently.
4531 // Fixed vector arguments go into registers as long as registers are
4532 // available. Variable vector arguments always go into memory.
4533 unsigned NumArgs = Outs.size();
4535 for (unsigned i = 0; i != NumArgs; ++i) {
4536 MVT ArgVT = Outs[i].VT;
4537 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4540 if (Outs[i].IsFixed) {
4541 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4544 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4550 errs() << "Call operand #" << i << " has unhandled type "
4551 << EVT(ArgVT).getEVTString() << "\n";
4553 llvm_unreachable(nullptr);
4557 // All arguments are treated the same.
4558 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4561 // Assign locations to all of the outgoing aggregate by value arguments.
4562 SmallVector<CCValAssign, 16> ByValArgLocs;
4563 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4564 ByValArgLocs, *DAG.getContext());
4566 // Reserve stack space for the allocations in CCInfo.
4567 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4569 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4571 // Size of the linkage area, parameter list area and the part of the local
4572 // space variable where copies of aggregates which are passed by value are
4574 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4576 // Calculate by how many bytes the stack has to be adjusted in case of tail
4577 // call optimization.
4578 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4580 // Adjust the stack pointer for the new arguments...
4581 // These operations are automatically eliminated by the prolog/epilog pass
4582 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4584 SDValue CallSeqStart = Chain;
4586 // Load the return address and frame pointer so it can be moved somewhere else
4589 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4592 // Set up a copy of the stack pointer for use loading and storing any
4593 // arguments that may not fit in the registers available for argument
4595 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4597 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4598 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4599 SmallVector<SDValue, 8> MemOpChains;
4601 bool seenFloatArg = false;
4602 // Walk the register/memloc assignments, inserting copies/loads.
4603 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4606 CCValAssign &VA = ArgLocs[i];
4607 SDValue Arg = OutVals[i];
4608 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4610 if (Flags.isByVal()) {
4611 // Argument is an aggregate which is passed by value, thus we need to
4612 // create a copy of it in the local variable space of the current stack
4613 // frame (which is the stack frame of the caller) and pass the address of
4614 // this copy to the callee.
4615 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4616 CCValAssign &ByValVA = ByValArgLocs[j++];
4617 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4619 // Memory reserved in the local variable space of the callers stack frame.
4620 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4622 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4623 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4626 // Create a copy of the argument in the local area of the current
4628 SDValue MemcpyCall =
4629 CreateCopyOfByValArgument(Arg, PtrOff,
4630 CallSeqStart.getNode()->getOperand(0),
4633 // This must go outside the CALLSEQ_START..END.
4634 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4635 CallSeqStart.getNode()->getOperand(1),
4637 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4638 NewCallSeqStart.getNode());
4639 Chain = CallSeqStart = NewCallSeqStart;
4641 // Pass the address of the aggregate copy on the stack either in a
4642 // physical register or in the parameter list area of the current stack
4643 // frame to the callee.
4647 if (VA.isRegLoc()) {
4648 if (Arg.getValueType() == MVT::i1)
4649 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4651 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4652 // Put argument in a physical register.
4653 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4655 // Put argument in the parameter list area of the current stack frame.
4656 assert(VA.isMemLoc());
4657 unsigned LocMemOffset = VA.getLocMemOffset();
4660 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4661 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4664 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4665 MachinePointerInfo(),
4668 // Calculate and remember argument location.
4669 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4675 if (!MemOpChains.empty())
4676 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4678 // Build a sequence of copy-to-reg nodes chained together with token chain
4679 // and flag operands which copy the outgoing args into the appropriate regs.
4681 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4682 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4683 RegsToPass[i].second, InFlag);
4684 InFlag = Chain.getValue(1);
4687 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4690 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4691 SDValue Ops[] = { Chain, InFlag };
4693 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4694 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4696 InFlag = Chain.getValue(1);
4700 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4701 false, TailCallArguments);
4703 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
4704 /* unused except on PPC64 ELFv1 */ false, DAG,
4705 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4706 NumBytes, Ins, InVals, CS);
4709 // Copy an argument into memory, being careful to do this outside the
4710 // call sequence for the call to which the argument belongs.
4712 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4713 SDValue CallSeqStart,
4714 ISD::ArgFlagsTy Flags,
4717 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4718 CallSeqStart.getNode()->getOperand(0),
4720 // The MEMCPY must go outside the CALLSEQ_START..END.
4721 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4722 CallSeqStart.getNode()->getOperand(1),
4724 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4725 NewCallSeqStart.getNode());
4726 return NewCallSeqStart;
4730 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4731 CallingConv::ID CallConv, bool isVarArg,
4732 bool isTailCall, bool IsPatchPoint,
4733 const SmallVectorImpl<ISD::OutputArg> &Outs,
4734 const SmallVectorImpl<SDValue> &OutVals,
4735 const SmallVectorImpl<ISD::InputArg> &Ins,
4736 SDLoc dl, SelectionDAG &DAG,
4737 SmallVectorImpl<SDValue> &InVals,
4738 ImmutableCallSite *CS) const {
4740 bool isELFv2ABI = Subtarget.isELFv2ABI();
4741 bool isLittleEndian = Subtarget.isLittleEndian();
4742 unsigned NumOps = Outs.size();
4743 bool hasNest = false;
4745 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4746 unsigned PtrByteSize = 8;
4748 MachineFunction &MF = DAG.getMachineFunction();
4750 // Mark this function as potentially containing a function that contains a
4751 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4752 // and restoring the callers stack pointer in this functions epilog. This is
4753 // done because by tail calling the called function might overwrite the value
4754 // in this function's (MF) stack pointer stack slot 0(SP).
4755 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4756 CallConv == CallingConv::Fast)
4757 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4759 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
4760 "fastcc not supported on varargs functions");
4762 // Count how many bytes are to be pushed on the stack, including the linkage
4763 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4764 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4765 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4766 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4767 unsigned NumBytes = LinkageSize;
4768 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4769 unsigned &QFPR_idx = FPR_idx;
4771 static const MCPhysReg GPR[] = {
4772 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4773 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4775 static const MCPhysReg VR[] = {
4776 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4777 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4779 static const MCPhysReg VSRH[] = {
4780 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4781 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4784 const unsigned NumGPRs = array_lengthof(GPR);
4785 const unsigned NumFPRs = 13;
4786 const unsigned NumVRs = array_lengthof(VR);
4787 const unsigned NumQFPRs = NumFPRs;
4789 // When using the fast calling convention, we don't provide backing for
4790 // arguments that will be in registers.
4791 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
4793 // Add up all the space actually used.
4794 for (unsigned i = 0; i != NumOps; ++i) {
4795 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4796 EVT ArgVT = Outs[i].VT;
4797 EVT OrigVT = Outs[i].ArgVT;
4802 if (CallConv == CallingConv::Fast) {
4803 if (Flags.isByVal())
4804 NumGPRsUsed += (Flags.getByValSize()+7)/8;
4806 switch (ArgVT.getSimpleVT().SimpleTy) {
4807 default: llvm_unreachable("Unexpected ValueType for argument!");
4811 if (++NumGPRsUsed <= NumGPRs)
4820 if (++NumVRsUsed <= NumVRs)
4824 // When using QPX, this is handled like a FP register, otherwise, it
4825 // is an Altivec register.
4826 if (Subtarget.hasQPX()) {
4827 if (++NumFPRsUsed <= NumFPRs)
4830 if (++NumVRsUsed <= NumVRs)
4836 case MVT::v4f64: // QPX
4837 case MVT::v4i1: // QPX
4838 if (++NumFPRsUsed <= NumFPRs)
4844 /* Respect alignment of argument on the stack. */
4846 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4847 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4849 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4850 if (Flags.isInConsecutiveRegsLast())
4851 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4854 unsigned NumBytesActuallyUsed = NumBytes;
4856 // The prolog code of the callee may store up to 8 GPR argument registers to
4857 // the stack, allowing va_start to index over them in memory if its varargs.
4858 // Because we cannot tell if this is needed on the caller side, we have to
4859 // conservatively assume that it is needed. As such, make sure we have at
4860 // least enough stack space for the caller to store the 8 GPRs.
4861 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4862 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4864 // Tail call needs the stack to be aligned.
4865 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4866 CallConv == CallingConv::Fast)
4867 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4869 // Calculate by how many bytes the stack has to be adjusted in case of tail
4870 // call optimization.
4871 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4873 // To protect arguments on the stack from being clobbered in a tail call,
4874 // force all the loads to happen before doing any other lowering.
4876 Chain = DAG.getStackArgumentTokenFactor(Chain);
4878 // Adjust the stack pointer for the new arguments...
4879 // These operations are automatically eliminated by the prolog/epilog pass
4880 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4882 SDValue CallSeqStart = Chain;
4884 // Load the return address and frame pointer so it can be move somewhere else
4887 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4890 // Set up a copy of the stack pointer for use loading and storing any
4891 // arguments that may not fit in the registers available for argument
4893 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4895 // Figure out which arguments are going to go in registers, and which in
4896 // memory. Also, if this is a vararg function, floating point operations
4897 // must be stored to our stack, and loaded into integer regs as well, if
4898 // any integer regs are available for argument passing.
4899 unsigned ArgOffset = LinkageSize;
4901 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4902 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4904 SmallVector<SDValue, 8> MemOpChains;
4905 for (unsigned i = 0; i != NumOps; ++i) {
4906 SDValue Arg = OutVals[i];
4907 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4908 EVT ArgVT = Outs[i].VT;
4909 EVT OrigVT = Outs[i].ArgVT;
4911 // PtrOff will be used to store the current argument to the stack if a
4912 // register cannot be found for it.
4915 // We re-align the argument offset for each argument, except when using the
4916 // fast calling convention, when we need to make sure we do that only when
4917 // we'll actually use a stack slot.
4918 auto ComputePtrOff = [&]() {
4919 /* Respect alignment of argument on the stack. */
4921 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4922 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4924 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
4926 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4929 if (CallConv != CallingConv::Fast) {
4932 /* Compute GPR index associated with argument offset. */
4933 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4934 GPR_idx = std::min(GPR_idx, NumGPRs);
4937 // Promote integers to 64-bit values.
4938 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4939 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4940 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4941 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4944 // FIXME memcpy is used way more than necessary. Correctness first.
4945 // Note: "by value" is code for passing a structure by value, not
4947 if (Flags.isByVal()) {
4948 // Note: Size includes alignment padding, so
4949 // struct x { short a; char b; }
4950 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4951 // These are the proper values we need for right-justifying the
4952 // aggregate in a parameter register.
4953 unsigned Size = Flags.getByValSize();
4955 // An empty aggregate parameter takes up no storage and no
4960 if (CallConv == CallingConv::Fast)
4963 // All aggregates smaller than 8 bytes must be passed right-justified.
4964 if (Size==1 || Size==2 || Size==4) {
4965 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4966 if (GPR_idx != NumGPRs) {
4967 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4968 MachinePointerInfo(), VT,
4969 false, false, false, 0);
4970 MemOpChains.push_back(Load.getValue(1));
4971 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4973 ArgOffset += PtrByteSize;
4978 if (GPR_idx == NumGPRs && Size < 8) {
4979 SDValue AddPtr = PtrOff;
4980 if (!isLittleEndian) {
4981 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
4982 PtrOff.getValueType());
4983 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4985 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4988 ArgOffset += PtrByteSize;
4991 // Copy entire object into memory. There are cases where gcc-generated
4992 // code assumes it is there, even if it could be put entirely into
4993 // registers. (This is not what the doc says.)
4995 // FIXME: The above statement is likely due to a misunderstanding of the
4996 // documents. All arguments must be copied into the parameter area BY
4997 // THE CALLEE in the event that the callee takes the address of any
4998 // formal argument. That has not yet been implemented. However, it is
4999 // reasonable to use the stack area as a staging area for the register
5002 // Skip this for small aggregates, as we will use the same slot for a
5003 // right-justified copy, below.
5005 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5009 // When a register is available, pass a small aggregate right-justified.
5010 if (Size < 8 && GPR_idx != NumGPRs) {
5011 // The easiest way to get this right-justified in a register
5012 // is to copy the structure into the rightmost portion of a
5013 // local variable slot, then load the whole slot into the
5015 // FIXME: The memcpy seems to produce pretty awful code for
5016 // small aggregates, particularly for packed ones.
5017 // FIXME: It would be preferable to use the slot in the
5018 // parameter save area instead of a new local variable.
5019 SDValue AddPtr = PtrOff;
5020 if (!isLittleEndian) {
5021 SDValue Const = DAG.getConstant(8 - Size, dl, PtrOff.getValueType());
5022 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5024 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5028 // Load the slot into the register.
5029 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
5030 MachinePointerInfo(),
5031 false, false, false, 0);
5032 MemOpChains.push_back(Load.getValue(1));
5033 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5035 // Done with this argument.
5036 ArgOffset += PtrByteSize;
5040 // For aggregates larger than PtrByteSize, copy the pieces of the
5041 // object that fit into registers from the parameter save area.
5042 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5043 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5044 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5045 if (GPR_idx != NumGPRs) {
5046 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5047 MachinePointerInfo(),
5048 false, false, false, 0);
5049 MemOpChains.push_back(Load.getValue(1));
5050 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5051 ArgOffset += PtrByteSize;
5053 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5060 switch (Arg.getSimpleValueType().SimpleTy) {
5061 default: llvm_unreachable("Unexpected ValueType for argument!");
5065 if (Flags.isNest()) {
5066 // The 'nest' parameter, if any, is passed in R11.
5067 RegsToPass.push_back(std::make_pair(PPC::X11, Arg));
5072 // These can be scalar arguments or elements of an integer array type
5073 // passed directly. Clang may use those instead of "byval" aggregate
5074 // types to avoid forcing arguments to memory unnecessarily.
5075 if (GPR_idx != NumGPRs) {
5076 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5078 if (CallConv == CallingConv::Fast)
5081 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5082 true, isTailCall, false, MemOpChains,
5083 TailCallArguments, dl);
5084 if (CallConv == CallingConv::Fast)
5085 ArgOffset += PtrByteSize;
5087 if (CallConv != CallingConv::Fast)
5088 ArgOffset += PtrByteSize;
5092 // These can be scalar arguments or elements of a float array type
5093 // passed directly. The latter are used to implement ELFv2 homogenous
5094 // float aggregates.
5096 // Named arguments go into FPRs first, and once they overflow, the
5097 // remaining arguments go into GPRs and then the parameter save area.
5098 // Unnamed arguments for vararg functions always go to GPRs and
5099 // then the parameter save area. For now, put all arguments to vararg
5100 // routines always in both locations (FPR *and* GPR or stack slot).
5101 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
5102 bool NeededLoad = false;
5104 // First load the argument into the next available FPR.
5105 if (FPR_idx != NumFPRs)
5106 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5108 // Next, load the argument into GPR or stack slot if needed.
5109 if (!NeedGPROrStack)
5111 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
5112 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
5113 // once we support fp <-> gpr moves.
5115 // In the non-vararg case, this can only ever happen in the
5116 // presence of f32 array types, since otherwise we never run
5117 // out of FPRs before running out of GPRs.
5120 // Double values are always passed in a single GPR.
5121 if (Arg.getValueType() != MVT::f32) {
5122 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
5124 // Non-array float values are extended and passed in a GPR.
5125 } else if (!Flags.isInConsecutiveRegs()) {
5126 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5127 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5129 // If we have an array of floats, we collect every odd element
5130 // together with its predecessor into one GPR.
5131 } else if (ArgOffset % PtrByteSize != 0) {
5133 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
5134 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5135 if (!isLittleEndian)
5137 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5139 // The final element, if even, goes into the first half of a GPR.
5140 } else if (Flags.isInConsecutiveRegsLast()) {
5141 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5142 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5143 if (!isLittleEndian)
5144 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
5145 DAG.getConstant(32, dl, MVT::i32));
5147 // Non-final even elements are skipped; they will be handled
5148 // together the with subsequent argument on the next go-around.
5152 if (ArgVal.getNode())
5153 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
5155 if (CallConv == CallingConv::Fast)
5158 // Single-precision floating-point values are mapped to the
5159 // second (rightmost) word of the stack doubleword.
5160 if (Arg.getValueType() == MVT::f32 &&
5161 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
5162 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5163 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5166 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5167 true, isTailCall, false, MemOpChains,
5168 TailCallArguments, dl);
5172 // When passing an array of floats, the array occupies consecutive
5173 // space in the argument area; only round up to the next doubleword
5174 // at the end of the array. Otherwise, each float takes 8 bytes.
5175 if (CallConv != CallingConv::Fast || NeededLoad) {
5176 ArgOffset += (Arg.getValueType() == MVT::f32 &&
5177 Flags.isInConsecutiveRegs()) ? 4 : 8;
5178 if (Flags.isInConsecutiveRegsLast())
5179 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
5190 if (!Subtarget.hasQPX()) {
5191 // These can be scalar arguments or elements of a vector array type
5192 // passed directly. The latter are used to implement ELFv2 homogenous
5193 // vector aggregates.
5195 // For a varargs call, named arguments go into VRs or on the stack as
5196 // usual; unnamed arguments always go to the stack or the corresponding
5197 // GPRs when within range. For now, we always put the value in both
5198 // locations (or even all three).
5200 // We could elide this store in the case where the object fits
5201 // entirely in R registers. Maybe later.
5202 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5203 MachinePointerInfo(), false, false, 0);
5204 MemOpChains.push_back(Store);
5205 if (VR_idx != NumVRs) {
5206 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5207 MachinePointerInfo(),
5208 false, false, false, 0);
5209 MemOpChains.push_back(Load.getValue(1));
5211 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5212 Arg.getSimpleValueType() == MVT::v2i64) ?
5213 VSRH[VR_idx] : VR[VR_idx];
5216 RegsToPass.push_back(std::make_pair(VReg, Load));
5219 for (unsigned i=0; i<16; i+=PtrByteSize) {
5220 if (GPR_idx == NumGPRs)
5222 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5223 DAG.getConstant(i, dl, PtrVT));
5224 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5225 false, false, false, 0);
5226 MemOpChains.push_back(Load.getValue(1));
5227 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5232 // Non-varargs Altivec params go into VRs or on the stack.
5233 if (VR_idx != NumVRs) {
5234 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5235 Arg.getSimpleValueType() == MVT::v2i64) ?
5236 VSRH[VR_idx] : VR[VR_idx];
5239 RegsToPass.push_back(std::make_pair(VReg, Arg));
5241 if (CallConv == CallingConv::Fast)
5244 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5245 true, isTailCall, true, MemOpChains,
5246 TailCallArguments, dl);
5247 if (CallConv == CallingConv::Fast)
5251 if (CallConv != CallingConv::Fast)
5256 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
5257 "Invalid QPX parameter type");
5262 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;
5264 // We could elide this store in the case where the object fits
5265 // entirely in R registers. Maybe later.
5266 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5267 MachinePointerInfo(), false, false, 0);
5268 MemOpChains.push_back(Store);
5269 if (QFPR_idx != NumQFPRs) {
5270 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl,
5271 Store, PtrOff, MachinePointerInfo(),
5272 false, false, false, 0);
5273 MemOpChains.push_back(Load.getValue(1));
5274 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Load));
5276 ArgOffset += (IsF32 ? 16 : 32);
5277 for (unsigned i = 0; i < (IsF32 ? 16U : 32U); i += PtrByteSize) {
5278 if (GPR_idx == NumGPRs)
5280 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5281 DAG.getConstant(i, dl, PtrVT));
5282 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5283 false, false, false, 0);
5284 MemOpChains.push_back(Load.getValue(1));
5285 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5290 // Non-varargs QPX params go into registers or on the stack.
5291 if (QFPR_idx != NumQFPRs) {
5292 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Arg));
5294 if (CallConv == CallingConv::Fast)
5297 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5298 true, isTailCall, true, MemOpChains,
5299 TailCallArguments, dl);
5300 if (CallConv == CallingConv::Fast)
5301 ArgOffset += (IsF32 ? 16 : 32);
5304 if (CallConv != CallingConv::Fast)
5305 ArgOffset += (IsF32 ? 16 : 32);
5311 assert(NumBytesActuallyUsed == ArgOffset);
5312 (void)NumBytesActuallyUsed;
5314 if (!MemOpChains.empty())
5315 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5317 // Check if this is an indirect call (MTCTR/BCTRL).
5318 // See PrepareCall() for more information about calls through function
5319 // pointers in the 64-bit SVR4 ABI.
5320 if (!isTailCall && !IsPatchPoint &&
5321 !isFunctionGlobalAddress(Callee) &&
5322 !isa<ExternalSymbolSDNode>(Callee)) {
5323 // Load r2 into a virtual register and store it to the TOC save area.
5324 setUsesTOCBasePtr(DAG);
5325 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
5326 // TOC save area offset.
5327 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5328 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5329 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5330 Chain = DAG.getStore(
5331 Val.getValue(1), dl, Val, AddPtr,
5332 MachinePointerInfo::getStack(DAG.getMachineFunction(), TOCSaveOffset),
5334 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
5335 // This does not mean the MTCTR instruction must use R12; it's easier
5336 // to model this as an extra parameter, so do that.
5337 if (isELFv2ABI && !IsPatchPoint)
5338 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
5341 // Build a sequence of copy-to-reg nodes chained together with token chain
5342 // and flag operands which copy the outgoing args into the appropriate regs.
5344 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5345 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5346 RegsToPass[i].second, InFlag);
5347 InFlag = Chain.getValue(1);
5351 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
5352 FPOp, true, TailCallArguments);
5354 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint, hasNest,
5355 DAG, RegsToPass, InFlag, Chain, CallSeqStart, Callee,
5356 SPDiff, NumBytes, Ins, InVals, CS);
5360 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
5361 CallingConv::ID CallConv, bool isVarArg,
5362 bool isTailCall, bool IsPatchPoint,
5363 const SmallVectorImpl<ISD::OutputArg> &Outs,
5364 const SmallVectorImpl<SDValue> &OutVals,
5365 const SmallVectorImpl<ISD::InputArg> &Ins,
5366 SDLoc dl, SelectionDAG &DAG,
5367 SmallVectorImpl<SDValue> &InVals,
5368 ImmutableCallSite *CS) const {
5370 unsigned NumOps = Outs.size();
5372 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5373 bool isPPC64 = PtrVT == MVT::i64;
5374 unsigned PtrByteSize = isPPC64 ? 8 : 4;
5376 MachineFunction &MF = DAG.getMachineFunction();
5378 // Mark this function as potentially containing a function that contains a
5379 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5380 // and restoring the callers stack pointer in this functions epilog. This is
5381 // done because by tail calling the called function might overwrite the value
5382 // in this function's (MF) stack pointer stack slot 0(SP).
5383 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5384 CallConv == CallingConv::Fast)
5385 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5387 // Count how many bytes are to be pushed on the stack, including the linkage
5388 // area, and parameter passing area. We start with 24/48 bytes, which is
5389 // prereserved space for [SP][CR][LR][3 x unused].
5390 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5391 unsigned NumBytes = LinkageSize;
5393 // Add up all the space actually used.
5394 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
5395 // they all go in registers, but we must reserve stack space for them for
5396 // possible use by the caller. In varargs or 64-bit calls, parameters are
5397 // assigned stack space in order, with padding so Altivec parameters are
5399 unsigned nAltivecParamsAtEnd = 0;
5400 for (unsigned i = 0; i != NumOps; ++i) {
5401 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5402 EVT ArgVT = Outs[i].VT;
5403 // Varargs Altivec parameters are padded to a 16 byte boundary.
5404 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
5405 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
5406 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
5407 if (!isVarArg && !isPPC64) {
5408 // Non-varargs Altivec parameters go after all the non-Altivec
5409 // parameters; handle those later so we know how much padding we need.
5410 nAltivecParamsAtEnd++;
5413 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
5414 NumBytes = ((NumBytes+15)/16)*16;
5416 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
5419 // Allow for Altivec parameters at the end, if needed.
5420 if (nAltivecParamsAtEnd) {
5421 NumBytes = ((NumBytes+15)/16)*16;
5422 NumBytes += 16*nAltivecParamsAtEnd;
5425 // The prolog code of the callee may store up to 8 GPR argument registers to
5426 // the stack, allowing va_start to index over them in memory if its varargs.
5427 // Because we cannot tell if this is needed on the caller side, we have to
5428 // conservatively assume that it is needed. As such, make sure we have at
5429 // least enough stack space for the caller to store the 8 GPRs.
5430 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
5432 // Tail call needs the stack to be aligned.
5433 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5434 CallConv == CallingConv::Fast)
5435 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
5437 // Calculate by how many bytes the stack has to be adjusted in case of tail
5438 // call optimization.
5439 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5441 // To protect arguments on the stack from being clobbered in a tail call,
5442 // force all the loads to happen before doing any other lowering.
5444 Chain = DAG.getStackArgumentTokenFactor(Chain);
5446 // Adjust the stack pointer for the new arguments...
5447 // These operations are automatically eliminated by the prolog/epilog pass
5448 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5450 SDValue CallSeqStart = Chain;
5452 // Load the return address and frame pointer so it can be move somewhere else
5455 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
5458 // Set up a copy of the stack pointer for use loading and storing any
5459 // arguments that may not fit in the registers available for argument
5463 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5465 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5467 // Figure out which arguments are going to go in registers, and which in
5468 // memory. Also, if this is a vararg function, floating point operations
5469 // must be stored to our stack, and loaded into integer regs as well, if
5470 // any integer regs are available for argument passing.
5471 unsigned ArgOffset = LinkageSize;
5472 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5474 static const MCPhysReg GPR_32[] = { // 32-bit registers.
5475 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
5476 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
5478 static const MCPhysReg GPR_64[] = { // 64-bit registers.
5479 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5480 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5482 static const MCPhysReg VR[] = {
5483 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5484 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5486 const unsigned NumGPRs = array_lengthof(GPR_32);
5487 const unsigned NumFPRs = 13;
5488 const unsigned NumVRs = array_lengthof(VR);
5490 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
5492 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5493 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5495 SmallVector<SDValue, 8> MemOpChains;
5496 for (unsigned i = 0; i != NumOps; ++i) {
5497 SDValue Arg = OutVals[i];
5498 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5500 // PtrOff will be used to store the current argument to the stack if a
5501 // register cannot be found for it.
5504 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
5506 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5508 // On PPC64, promote integers to 64-bit values.
5509 if (isPPC64 && Arg.getValueType() == MVT::i32) {
5510 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
5511 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5512 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
5515 // FIXME memcpy is used way more than necessary. Correctness first.
5516 // Note: "by value" is code for passing a structure by value, not
5518 if (Flags.isByVal()) {
5519 unsigned Size = Flags.getByValSize();
5520 // Very small objects are passed right-justified. Everything else is
5521 // passed left-justified.
5522 if (Size==1 || Size==2) {
5523 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
5524 if (GPR_idx != NumGPRs) {
5525 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5526 MachinePointerInfo(), VT,
5527 false, false, false, 0);
5528 MemOpChains.push_back(Load.getValue(1));
5529 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5531 ArgOffset += PtrByteSize;
5533 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
5534 PtrOff.getValueType());
5535 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5536 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5539 ArgOffset += PtrByteSize;
5543 // Copy entire object into memory. There are cases where gcc-generated
5544 // code assumes it is there, even if it could be put entirely into
5545 // registers. (This is not what the doc says.)
5546 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5550 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5551 // copy the pieces of the object that fit into registers from the
5552 // parameter save area.
5553 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5554 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5555 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5556 if (GPR_idx != NumGPRs) {
5557 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5558 MachinePointerInfo(),
5559 false, false, false, 0);
5560 MemOpChains.push_back(Load.getValue(1));
5561 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5562 ArgOffset += PtrByteSize;
5564 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5571 switch (Arg.getSimpleValueType().SimpleTy) {
5572 default: llvm_unreachable("Unexpected ValueType for argument!");
5576 if (GPR_idx != NumGPRs) {
5577 if (Arg.getValueType() == MVT::i1)
5578 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5580 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5582 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5583 isPPC64, isTailCall, false, MemOpChains,
5584 TailCallArguments, dl);
5586 ArgOffset += PtrByteSize;
5590 if (FPR_idx != NumFPRs) {
5591 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5594 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5595 MachinePointerInfo(), false, false, 0);
5596 MemOpChains.push_back(Store);
5598 // Float varargs are always shadowed in available integer registers
5599 if (GPR_idx != NumGPRs) {
5600 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5601 MachinePointerInfo(), false, false,
5603 MemOpChains.push_back(Load.getValue(1));
5604 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5606 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5607 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5608 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5609 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5610 MachinePointerInfo(),
5611 false, false, false, 0);
5612 MemOpChains.push_back(Load.getValue(1));
5613 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5616 // If we have any FPRs remaining, we may also have GPRs remaining.
5617 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5619 if (GPR_idx != NumGPRs)
5621 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5622 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5626 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5627 isPPC64, isTailCall, false, MemOpChains,
5628 TailCallArguments, dl);
5632 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5639 // These go aligned on the stack, or in the corresponding R registers
5640 // when within range. The Darwin PPC ABI doc claims they also go in
5641 // V registers; in fact gcc does this only for arguments that are
5642 // prototyped, not for those that match the ... We do it for all
5643 // arguments, seems to work.
5644 while (ArgOffset % 16 !=0) {
5645 ArgOffset += PtrByteSize;
5646 if (GPR_idx != NumGPRs)
5649 // We could elide this store in the case where the object fits
5650 // entirely in R registers. Maybe later.
5651 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5652 DAG.getConstant(ArgOffset, dl, PtrVT));
5653 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5654 MachinePointerInfo(), false, false, 0);
5655 MemOpChains.push_back(Store);
5656 if (VR_idx != NumVRs) {
5657 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5658 MachinePointerInfo(),
5659 false, false, false, 0);
5660 MemOpChains.push_back(Load.getValue(1));
5661 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5664 for (unsigned i=0; i<16; i+=PtrByteSize) {
5665 if (GPR_idx == NumGPRs)
5667 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5668 DAG.getConstant(i, dl, PtrVT));
5669 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5670 false, false, false, 0);
5671 MemOpChains.push_back(Load.getValue(1));
5672 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5677 // Non-varargs Altivec params generally go in registers, but have
5678 // stack space allocated at the end.
5679 if (VR_idx != NumVRs) {
5680 // Doesn't have GPR space allocated.
5681 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5682 } else if (nAltivecParamsAtEnd==0) {
5683 // We are emitting Altivec params in order.
5684 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5685 isPPC64, isTailCall, true, MemOpChains,
5686 TailCallArguments, dl);
5692 // If all Altivec parameters fit in registers, as they usually do,
5693 // they get stack space following the non-Altivec parameters. We
5694 // don't track this here because nobody below needs it.
5695 // If there are more Altivec parameters than fit in registers emit
5697 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5699 // Offset is aligned; skip 1st 12 params which go in V registers.
5700 ArgOffset = ((ArgOffset+15)/16)*16;
5702 for (unsigned i = 0; i != NumOps; ++i) {
5703 SDValue Arg = OutVals[i];
5704 EVT ArgType = Outs[i].VT;
5705 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5706 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5709 // We are emitting Altivec params in order.
5710 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5711 isPPC64, isTailCall, true, MemOpChains,
5712 TailCallArguments, dl);
5719 if (!MemOpChains.empty())
5720 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5722 // On Darwin, R12 must contain the address of an indirect callee. This does
5723 // not mean the MTCTR instruction must use R12; it's easier to model this as
5724 // an extra parameter, so do that.
5726 !isFunctionGlobalAddress(Callee) &&
5727 !isa<ExternalSymbolSDNode>(Callee) &&
5728 !isBLACompatibleAddress(Callee, DAG))
5729 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5730 PPC::R12), Callee));
5732 // Build a sequence of copy-to-reg nodes chained together with token chain
5733 // and flag operands which copy the outgoing args into the appropriate regs.
5735 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5736 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5737 RegsToPass[i].second, InFlag);
5738 InFlag = Chain.getValue(1);
5742 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5743 FPOp, true, TailCallArguments);
5745 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
5746 /* unused except on PPC64 ELFv1 */ false, DAG,
5747 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5748 NumBytes, Ins, InVals, CS);
5752 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5753 MachineFunction &MF, bool isVarArg,
5754 const SmallVectorImpl<ISD::OutputArg> &Outs,
5755 LLVMContext &Context) const {
5756 SmallVector<CCValAssign, 16> RVLocs;
5757 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5758 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5762 PPCTargetLowering::LowerReturn(SDValue Chain,
5763 CallingConv::ID CallConv, bool isVarArg,
5764 const SmallVectorImpl<ISD::OutputArg> &Outs,
5765 const SmallVectorImpl<SDValue> &OutVals,
5766 SDLoc dl, SelectionDAG &DAG) const {
5768 SmallVector<CCValAssign, 16> RVLocs;
5769 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5771 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5774 SmallVector<SDValue, 4> RetOps(1, Chain);
5776 // Copy the result values into the output registers.
5777 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5778 CCValAssign &VA = RVLocs[i];
5779 assert(VA.isRegLoc() && "Can only return in registers!");
5781 SDValue Arg = OutVals[i];
5783 switch (VA.getLocInfo()) {
5784 default: llvm_unreachable("Unknown loc info!");
5785 case CCValAssign::Full: break;
5786 case CCValAssign::AExt:
5787 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5789 case CCValAssign::ZExt:
5790 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5792 case CCValAssign::SExt:
5793 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5797 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5798 Flag = Chain.getValue(1);
5799 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5802 RetOps[0] = Chain; // Update chain.
5804 // Add the flag if we have it.
5806 RetOps.push_back(Flag);
5808 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5811 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5812 const PPCSubtarget &Subtarget) const {
5813 // When we pop the dynamic allocation we need to restore the SP link.
5816 // Get the corect type for pointers.
5817 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5819 // Construct the stack pointer operand.
5820 bool isPPC64 = Subtarget.isPPC64();
5821 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5822 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5824 // Get the operands for the STACKRESTORE.
5825 SDValue Chain = Op.getOperand(0);
5826 SDValue SaveSP = Op.getOperand(1);
5828 // Load the old link SP.
5829 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5830 MachinePointerInfo(),
5831 false, false, false, 0);
5833 // Restore the stack pointer.
5834 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5836 // Store the old link SP.
5837 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5841 SDValue PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG &DAG) const {
5842 MachineFunction &MF = DAG.getMachineFunction();
5843 bool isPPC64 = Subtarget.isPPC64();
5844 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
5846 // Get current frame pointer save index. The users of this index will be
5847 // primarily DYNALLOC instructions.
5848 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5849 int RASI = FI->getReturnAddrSaveIndex();
5851 // If the frame pointer save index hasn't been defined yet.
5853 // Find out what the fix offset of the frame pointer save area.
5854 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset();
5855 // Allocate the frame index for frame pointer save area.
5856 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5858 FI->setReturnAddrSaveIndex(RASI);
5860 return DAG.getFrameIndex(RASI, PtrVT);
5864 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5865 MachineFunction &MF = DAG.getMachineFunction();
5866 bool isPPC64 = Subtarget.isPPC64();
5867 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
5869 // Get current frame pointer save index. The users of this index will be
5870 // primarily DYNALLOC instructions.
5871 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5872 int FPSI = FI->getFramePointerSaveIndex();
5874 // If the frame pointer save index hasn't been defined yet.
5876 // Find out what the fix offset of the frame pointer save area.
5877 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset();
5878 // Allocate the frame index for frame pointer save area.
5879 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5881 FI->setFramePointerSaveIndex(FPSI);
5883 return DAG.getFrameIndex(FPSI, PtrVT);
5886 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5888 const PPCSubtarget &Subtarget) const {
5890 SDValue Chain = Op.getOperand(0);
5891 SDValue Size = Op.getOperand(1);
5894 // Get the corect type for pointers.
5895 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5897 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5898 DAG.getConstant(0, dl, PtrVT), Size);
5899 // Construct a node for the frame pointer save index.
5900 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5901 // Build a DYNALLOC node.
5902 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5903 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5904 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5907 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5908 SelectionDAG &DAG) const {
5910 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5911 DAG.getVTList(MVT::i32, MVT::Other),
5912 Op.getOperand(0), Op.getOperand(1));
5915 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5916 SelectionDAG &DAG) const {
5918 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5919 Op.getOperand(0), Op.getOperand(1));
5922 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5923 if (Op.getValueType().isVector())
5924 return LowerVectorLoad(Op, DAG);
5926 assert(Op.getValueType() == MVT::i1 &&
5927 "Custom lowering only for i1 loads");
5929 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5932 LoadSDNode *LD = cast<LoadSDNode>(Op);
5934 SDValue Chain = LD->getChain();
5935 SDValue BasePtr = LD->getBasePtr();
5936 MachineMemOperand *MMO = LD->getMemOperand();
5939 DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(DAG.getDataLayout()), Chain,
5940 BasePtr, MVT::i8, MMO);
5941 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5943 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5944 return DAG.getMergeValues(Ops, dl);
5947 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5948 if (Op.getOperand(1).getValueType().isVector())
5949 return LowerVectorStore(Op, DAG);
5951 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5952 "Custom lowering only for i1 stores");
5954 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5957 StoreSDNode *ST = cast<StoreSDNode>(Op);
5959 SDValue Chain = ST->getChain();
5960 SDValue BasePtr = ST->getBasePtr();
5961 SDValue Value = ST->getValue();
5962 MachineMemOperand *MMO = ST->getMemOperand();
5964 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(DAG.getDataLayout()),
5966 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5969 // FIXME: Remove this once the ANDI glue bug is fixed:
5970 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5971 assert(Op.getValueType() == MVT::i1 &&
5972 "Custom lowering only for i1 results");
5975 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5979 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5981 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5982 // Not FP? Not a fsel.
5983 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5984 !Op.getOperand(2).getValueType().isFloatingPoint())
5987 // We might be able to do better than this under some circumstances, but in
5988 // general, fsel-based lowering of select is a finite-math-only optimization.
5989 // For more information, see section F.3 of the 2.06 ISA specification.
5990 if (!DAG.getTarget().Options.NoInfsFPMath ||
5991 !DAG.getTarget().Options.NoNaNsFPMath)
5993 // TODO: Propagate flags from the select rather than global settings.
5995 Flags.setNoInfs(true);
5996 Flags.setNoNaNs(true);
5998 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
6000 EVT ResVT = Op.getValueType();
6001 EVT CmpVT = Op.getOperand(0).getValueType();
6002 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6003 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
6006 // If the RHS of the comparison is a 0.0, we don't need to do the
6007 // subtraction at all.
6009 if (isFloatingPointZero(RHS))
6011 default: break; // SETUO etc aren't handled by fsel.
6015 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6016 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6017 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6018 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6019 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6020 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6021 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
6024 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6027 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6028 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6029 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6032 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6035 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6036 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6037 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6038 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
6043 default: break; // SETUO etc aren't handled by fsel.
6047 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6048 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6049 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6050 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6051 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6052 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6053 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6054 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
6057 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6058 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6059 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6060 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6063 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6064 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6065 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6066 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6069 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, &Flags);
6070 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6071 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6072 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6075 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, &Flags);
6076 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6077 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6078 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6083 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
6086 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6087 SDValue Src = Op.getOperand(0);
6088 if (Src.getValueType() == MVT::f32)
6089 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6092 switch (Op.getSimpleValueType().SimpleTy) {
6093 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6096 Op.getOpcode() == ISD::FP_TO_SINT
6098 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6102 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6103 "i64 FP_TO_UINT is supported only with FPCVT");
6104 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6110 // Convert the FP value to an int value through memory.
6111 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
6112 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
6113 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
6114 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
6115 MachinePointerInfo MPI =
6116 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
6118 // Emit a store to the stack slot.
6121 MachineFunction &MF = DAG.getMachineFunction();
6122 MachineMemOperand *MMO =
6123 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
6124 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
6125 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
6126 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
6128 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
6129 MPI, false, false, 0);
6131 // Result is a load from the stack slot. If loading 4 bytes, make sure to
6133 if (Op.getValueType() == MVT::i32 && !i32Stack) {
6134 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
6135 DAG.getConstant(4, dl, FIPtr.getValueType()));
6136 MPI = MPI.getWithOffset(4);
6144 /// \brief Custom lowers floating point to integer conversions to use
6145 /// the direct move instructions available in ISA 2.07 to avoid the
6146 /// need for load/store combinations.
6147 SDValue PPCTargetLowering::LowerFP_TO_INTDirectMove(SDValue Op,
6150 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6151 SDValue Src = Op.getOperand(0);
6153 if (Src.getValueType() == MVT::f32)
6154 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6157 switch (Op.getSimpleValueType().SimpleTy) {
6158 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6161 Op.getOpcode() == ISD::FP_TO_SINT
6163 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6165 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp);
6168 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6169 "i64 FP_TO_UINT is supported only with FPCVT");
6170 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6173 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp);
6179 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
6181 if (Subtarget.hasDirectMove() && Subtarget.isPPC64())
6182 return LowerFP_TO_INTDirectMove(Op, DAG, dl);
6185 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6187 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6188 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6192 // We're trying to insert a regular store, S, and then a load, L. If the
6193 // incoming value, O, is a load, we might just be able to have our load use the
6194 // address used by O. However, we don't know if anything else will store to
6195 // that address before we can load from it. To prevent this situation, we need
6196 // to insert our load, L, into the chain as a peer of O. To do this, we give L
6197 // the same chain operand as O, we create a token factor from the chain results
6198 // of O and L, and we replace all uses of O's chain result with that token
6199 // factor (see spliceIntoChain below for this last part).
6200 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
6203 ISD::LoadExtType ET) const {
6205 if (ET == ISD::NON_EXTLOAD &&
6206 (Op.getOpcode() == ISD::FP_TO_UINT ||
6207 Op.getOpcode() == ISD::FP_TO_SINT) &&
6208 isOperationLegalOrCustom(Op.getOpcode(),
6209 Op.getOperand(0).getValueType())) {
6211 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6215 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
6216 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
6217 LD->isNonTemporal())
6219 if (LD->getMemoryVT() != MemVT)
6222 RLI.Ptr = LD->getBasePtr();
6223 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
6224 assert(LD->getAddressingMode() == ISD::PRE_INC &&
6225 "Non-pre-inc AM on PPC?");
6226 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
6230 RLI.Chain = LD->getChain();
6231 RLI.MPI = LD->getPointerInfo();
6232 RLI.IsInvariant = LD->isInvariant();
6233 RLI.Alignment = LD->getAlignment();
6234 RLI.AAInfo = LD->getAAInfo();
6235 RLI.Ranges = LD->getRanges();
6237 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
6241 // Given the head of the old chain, ResChain, insert a token factor containing
6242 // it and NewResChain, and make users of ResChain now be users of that token
6244 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
6245 SDValue NewResChain,
6246 SelectionDAG &DAG) const {
6250 SDLoc dl(NewResChain);
6252 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6253 NewResChain, DAG.getUNDEF(MVT::Other));
6254 assert(TF.getNode() != NewResChain.getNode() &&
6255 "A new TF really is required here");
6257 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
6258 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
6261 /// \brief Custom lowers integer to floating point conversions to use
6262 /// the direct move instructions available in ISA 2.07 to avoid the
6263 /// need for load/store combinations.
6264 SDValue PPCTargetLowering::LowerINT_TO_FPDirectMove(SDValue Op,
6267 assert((Op.getValueType() == MVT::f32 ||
6268 Op.getValueType() == MVT::f64) &&
6269 "Invalid floating point type as target of conversion");
6270 assert(Subtarget.hasFPCVT() &&
6271 "Int to FP conversions with direct moves require FPCVT");
6273 SDValue Src = Op.getOperand(0);
6274 bool SinglePrec = Op.getValueType() == MVT::f32;
6275 bool WordInt = Src.getSimpleValueType().SimpleTy == MVT::i32;
6276 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP;
6277 unsigned ConvOp = Signed ? (SinglePrec ? PPCISD::FCFIDS : PPCISD::FCFID) :
6278 (SinglePrec ? PPCISD::FCFIDUS : PPCISD::FCFIDU);
6281 FP = DAG.getNode(Signed ? PPCISD::MTVSRA : PPCISD::MTVSRZ,
6283 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6286 FP = DAG.getNode(PPCISD::MTVSRA, dl, MVT::f64, Src);
6287 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6293 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
6294 SelectionDAG &DAG) const {
6297 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) {
6298 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64)
6301 SDValue Value = Op.getOperand(0);
6302 // The values are now known to be -1 (false) or 1 (true). To convert this
6303 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
6304 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
6305 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
6307 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
6308 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64, FPHalfs, FPHalfs,
6311 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
6313 if (Op.getValueType() != MVT::v4f64)
6314 Value = DAG.getNode(ISD::FP_ROUND, dl,
6315 Op.getValueType(), Value,
6316 DAG.getIntPtrConstant(1, dl));
6320 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
6321 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
6324 if (Op.getOperand(0).getValueType() == MVT::i1)
6325 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
6326 DAG.getConstantFP(1.0, dl, Op.getValueType()),
6327 DAG.getConstantFP(0.0, dl, Op.getValueType()));
6329 // If we have direct moves, we can do all the conversion, skip the store/load
6330 // however, without FPCVT we can't do most conversions.
6331 if (Subtarget.hasDirectMove() && Subtarget.isPPC64() && Subtarget.hasFPCVT())
6332 return LowerINT_TO_FPDirectMove(Op, DAG, dl);
6334 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
6335 "UINT_TO_FP is supported only with FPCVT");
6337 // If we have FCFIDS, then use it when converting to single-precision.
6338 // Otherwise, convert to double-precision and then round.
6339 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6340 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
6342 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
6344 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6348 if (Op.getOperand(0).getValueType() == MVT::i64) {
6349 SDValue SINT = Op.getOperand(0);
6350 // When converting to single-precision, we actually need to convert
6351 // to double-precision first and then round to single-precision.
6352 // To avoid double-rounding effects during that operation, we have
6353 // to prepare the input operand. Bits that might be truncated when
6354 // converting to double-precision are replaced by a bit that won't
6355 // be lost at this stage, but is below the single-precision rounding
6358 // However, if -enable-unsafe-fp-math is in effect, accept double
6359 // rounding to avoid the extra overhead.
6360 if (Op.getValueType() == MVT::f32 &&
6361 !Subtarget.hasFPCVT() &&
6362 !DAG.getTarget().Options.UnsafeFPMath) {
6364 // Twiddle input to make sure the low 11 bits are zero. (If this
6365 // is the case, we are guaranteed the value will fit into the 53 bit
6366 // mantissa of an IEEE double-precision value without rounding.)
6367 // If any of those low 11 bits were not zero originally, make sure
6368 // bit 12 (value 2048) is set instead, so that the final rounding
6369 // to single-precision gets the correct result.
6370 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6371 SINT, DAG.getConstant(2047, dl, MVT::i64));
6372 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
6373 Round, DAG.getConstant(2047, dl, MVT::i64));
6374 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
6375 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6376 Round, DAG.getConstant(-2048, dl, MVT::i64));
6378 // However, we cannot use that value unconditionally: if the magnitude
6379 // of the input value is small, the bit-twiddling we did above might
6380 // end up visibly changing the output. Fortunately, in that case, we
6381 // don't need to twiddle bits since the original input will convert
6382 // exactly to double-precision floating-point already. Therefore,
6383 // construct a conditional to use the original value if the top 11
6384 // bits are all sign-bit copies, and use the rounded value computed
6386 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
6387 SINT, DAG.getConstant(53, dl, MVT::i32));
6388 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
6389 Cond, DAG.getConstant(1, dl, MVT::i64));
6390 Cond = DAG.getSetCC(dl, MVT::i32,
6391 Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT);
6393 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
6399 MachineFunction &MF = DAG.getMachineFunction();
6400 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
6401 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6402 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6404 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6405 } else if (Subtarget.hasLFIWAX() &&
6406 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
6407 MachineMemOperand *MMO =
6408 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6409 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6410 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6411 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
6412 DAG.getVTList(MVT::f64, MVT::Other),
6413 Ops, MVT::i32, MMO);
6414 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6415 } else if (Subtarget.hasFPCVT() &&
6416 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
6417 MachineMemOperand *MMO =
6418 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6419 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6420 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6421 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
6422 DAG.getVTList(MVT::f64, MVT::Other),
6423 Ops, MVT::i32, MMO);
6424 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6425 } else if (((Subtarget.hasLFIWAX() &&
6426 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
6427 (Subtarget.hasFPCVT() &&
6428 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
6429 SINT.getOperand(0).getValueType() == MVT::i32) {
6430 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6431 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
6433 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6434 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6436 SDValue Store = DAG.getStore(
6437 DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
6438 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6441 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6442 "Expected an i32 store");
6447 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6450 MachineMemOperand *MMO =
6451 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6452 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6453 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6454 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
6455 PPCISD::LFIWZX : PPCISD::LFIWAX,
6456 dl, DAG.getVTList(MVT::f64, MVT::Other),
6457 Ops, MVT::i32, MMO);
6459 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
6461 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
6463 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6464 FP = DAG.getNode(ISD::FP_ROUND, dl,
6465 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
6469 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
6470 "Unhandled INT_TO_FP type in custom expander!");
6471 // Since we only generate this in 64-bit mode, we can take advantage of
6472 // 64-bit registers. In particular, sign extend the input value into the
6473 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
6474 // then lfd it and fcfid it.
6475 MachineFunction &MF = DAG.getMachineFunction();
6476 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6477 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
6480 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
6483 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
6485 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6486 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6488 SDValue Store = DAG.getStore(
6489 DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
6490 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6493 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6494 "Expected an i32 store");
6499 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6503 MachineMemOperand *MMO =
6504 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6505 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6506 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6507 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
6508 PPCISD::LFIWZX : PPCISD::LFIWAX,
6509 dl, DAG.getVTList(MVT::f64, MVT::Other),
6510 Ops, MVT::i32, MMO);
6512 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
6514 assert(Subtarget.isPPC64() &&
6515 "i32->FP without LFIWAX supported only on PPC64");
6517 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
6518 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6520 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
6523 // STD the extended value into the stack slot.
6524 SDValue Store = DAG.getStore(
6525 DAG.getEntryNode(), dl, Ext64, FIdx,
6526 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6529 // Load the value as a double.
6531 MVT::f64, dl, Store, FIdx,
6532 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6533 false, false, false, 0);
6536 // FCFID it and return it.
6537 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
6538 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6539 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
6540 DAG.getIntPtrConstant(0, dl));
6544 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
6545 SelectionDAG &DAG) const {
6548 The rounding mode is in bits 30:31 of FPSR, and has the following
6555 FLT_ROUNDS, on the other hand, expects the following:
6562 To perform the conversion, we do:
6563 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
6566 MachineFunction &MF = DAG.getMachineFunction();
6567 EVT VT = Op.getValueType();
6568 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
6570 // Save FP Control Word to register
6572 MVT::f64, // return register
6573 MVT::Glue // unused in this context
6575 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
6577 // Save FP register to stack slot
6578 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
6579 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
6580 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
6581 StackSlot, MachinePointerInfo(), false, false,0);
6583 // Load FP Control Word from low 32 bits of stack slot.
6584 SDValue Four = DAG.getConstant(4, dl, PtrVT);
6585 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
6586 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
6587 false, false, false, 0);
6589 // Transform as necessary
6591 DAG.getNode(ISD::AND, dl, MVT::i32,
6592 CWD, DAG.getConstant(3, dl, MVT::i32));
6594 DAG.getNode(ISD::SRL, dl, MVT::i32,
6595 DAG.getNode(ISD::AND, dl, MVT::i32,
6596 DAG.getNode(ISD::XOR, dl, MVT::i32,
6597 CWD, DAG.getConstant(3, dl, MVT::i32)),
6598 DAG.getConstant(3, dl, MVT::i32)),
6599 DAG.getConstant(1, dl, MVT::i32));
6602 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
6604 return DAG.getNode((VT.getSizeInBits() < 16 ?
6605 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6608 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6609 EVT VT = Op.getValueType();
6610 unsigned BitWidth = VT.getSizeInBits();
6612 assert(Op.getNumOperands() == 3 &&
6613 VT == Op.getOperand(1).getValueType() &&
6616 // Expand into a bunch of logical ops. Note that these ops
6617 // depend on the PPC behavior for oversized shift amounts.
6618 SDValue Lo = Op.getOperand(0);
6619 SDValue Hi = Op.getOperand(1);
6620 SDValue Amt = Op.getOperand(2);
6621 EVT AmtVT = Amt.getValueType();
6623 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6624 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6625 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
6626 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
6627 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
6628 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6629 DAG.getConstant(-BitWidth, dl, AmtVT));
6630 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
6631 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6632 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
6633 SDValue OutOps[] = { OutLo, OutHi };
6634 return DAG.getMergeValues(OutOps, dl);
6637 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6638 EVT VT = Op.getValueType();
6640 unsigned BitWidth = VT.getSizeInBits();
6641 assert(Op.getNumOperands() == 3 &&
6642 VT == Op.getOperand(1).getValueType() &&
6645 // Expand into a bunch of logical ops. Note that these ops
6646 // depend on the PPC behavior for oversized shift amounts.
6647 SDValue Lo = Op.getOperand(0);
6648 SDValue Hi = Op.getOperand(1);
6649 SDValue Amt = Op.getOperand(2);
6650 EVT AmtVT = Amt.getValueType();
6652 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6653 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6654 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6655 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6656 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6657 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6658 DAG.getConstant(-BitWidth, dl, AmtVT));
6659 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
6660 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6661 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
6662 SDValue OutOps[] = { OutLo, OutHi };
6663 return DAG.getMergeValues(OutOps, dl);
6666 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6668 EVT VT = Op.getValueType();
6669 unsigned BitWidth = VT.getSizeInBits();
6670 assert(Op.getNumOperands() == 3 &&
6671 VT == Op.getOperand(1).getValueType() &&
6674 // Expand into a bunch of logical ops, followed by a select_cc.
6675 SDValue Lo = Op.getOperand(0);
6676 SDValue Hi = Op.getOperand(1);
6677 SDValue Amt = Op.getOperand(2);
6678 EVT AmtVT = Amt.getValueType();
6680 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6681 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6682 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6683 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6684 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6685 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6686 DAG.getConstant(-BitWidth, dl, AmtVT));
6687 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
6688 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
6689 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, dl, AmtVT),
6690 Tmp4, Tmp6, ISD::SETLE);
6691 SDValue OutOps[] = { OutLo, OutHi };
6692 return DAG.getMergeValues(OutOps, dl);
6695 //===----------------------------------------------------------------------===//
6696 // Vector related lowering.
6699 /// BuildSplatI - Build a canonical splati of Val with an element size of
6700 /// SplatSize. Cast the result to VT.
6701 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6702 SelectionDAG &DAG, SDLoc dl) {
6703 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
6705 static const MVT VTys[] = { // canonical VT to use for each size.
6706 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6709 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
6711 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
6715 EVT CanonicalVT = VTys[SplatSize-1];
6717 // Build a canonical splat for this value.
6718 SDValue Elt = DAG.getConstant(Val, dl, MVT::i32);
6719 SmallVector<SDValue, 8> Ops;
6720 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
6721 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
6722 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
6725 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
6726 /// specified intrinsic ID.
6727 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6728 SelectionDAG &DAG, SDLoc dl,
6729 EVT DestVT = MVT::Other) {
6730 if (DestVT == MVT::Other) DestVT = Op.getValueType();
6731 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6732 DAG.getConstant(IID, dl, MVT::i32), Op);
6735 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
6736 /// specified intrinsic ID.
6737 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6738 SelectionDAG &DAG, SDLoc dl,
6739 EVT DestVT = MVT::Other) {
6740 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
6741 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6742 DAG.getConstant(IID, dl, MVT::i32), LHS, RHS);
6745 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
6746 /// specified intrinsic ID.
6747 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6748 SDValue Op2, SelectionDAG &DAG,
6749 SDLoc dl, EVT DestVT = MVT::Other) {
6750 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6751 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6752 DAG.getConstant(IID, dl, MVT::i32), Op0, Op1, Op2);
6755 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6756 /// amount. The result has the specified value type.
6757 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6758 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6759 // Force LHS/RHS to be the right type.
6760 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6761 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6764 for (unsigned i = 0; i != 16; ++i)
6766 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6767 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6770 // If this is a case we can't handle, return null and let the default
6771 // expansion code take care of it. If we CAN select this case, and if it
6772 // selects to a single instruction, return Op. Otherwise, if we can codegen
6773 // this case more efficiently than a constant pool load, lower it to the
6774 // sequence of ops that should be used.
6775 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6776 SelectionDAG &DAG) const {
6778 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6779 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6781 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) {
6782 // We first build an i32 vector, load it into a QPX register,
6783 // then convert it to a floating-point vector and compare it
6784 // to a zero vector to get the boolean result.
6785 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6786 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6787 MachinePointerInfo PtrInfo =
6788 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6789 EVT PtrVT = getPointerTy(DAG.getDataLayout());
6790 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6792 assert(BVN->getNumOperands() == 4 &&
6793 "BUILD_VECTOR for v4i1 does not have 4 operands");
6795 bool IsConst = true;
6796 for (unsigned i = 0; i < 4; ++i) {
6797 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6798 if (!isa<ConstantSDNode>(BVN->getOperand(i))) {
6806 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), 1.0);
6808 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), -1.0);
6810 SmallVector<Constant*, 4> CV(4, NegOne);
6811 for (unsigned i = 0; i < 4; ++i) {
6812 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF)
6813 CV[i] = UndefValue::get(Type::getFloatTy(*DAG.getContext()));
6814 else if (isNullConstant(BVN->getOperand(i)))
6820 Constant *CP = ConstantVector::get(CV);
6821 SDValue CPIdx = DAG.getConstantPool(CP, getPointerTy(DAG.getDataLayout()),
6822 16 /* alignment */);
6824 SmallVector<SDValue, 2> Ops;
6825 Ops.push_back(DAG.getEntryNode());
6826 Ops.push_back(CPIdx);
6828 SmallVector<EVT, 2> ValueVTs;
6829 ValueVTs.push_back(MVT::v4i1);
6830 ValueVTs.push_back(MVT::Other); // chain
6831 SDVTList VTs = DAG.getVTList(ValueVTs);
6833 return DAG.getMemIntrinsicNode(
6834 PPCISD::QVLFSb, dl, VTs, Ops, MVT::v4f32,
6835 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
6838 SmallVector<SDValue, 4> Stores;
6839 for (unsigned i = 0; i < 4; ++i) {
6840 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6842 unsigned Offset = 4*i;
6843 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
6844 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
6846 unsigned StoreSize = BVN->getOperand(i).getValueType().getStoreSize();
6847 if (StoreSize > 4) {
6848 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
6849 BVN->getOperand(i), Idx,
6850 PtrInfo.getWithOffset(Offset),
6851 MVT::i32, false, false, 0));
6853 SDValue StoreValue = BVN->getOperand(i);
6855 StoreValue = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, StoreValue);
6857 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
6859 PtrInfo.getWithOffset(Offset),
6865 if (!Stores.empty())
6866 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
6868 StoreChain = DAG.getEntryNode();
6870 // Now load from v4i32 into the QPX register; this will extend it to
6871 // v4i64 but not yet convert it to a floating point. Nevertheless, this
6872 // is typed as v4f64 because the QPX register integer states are not
6873 // explicitly represented.
6875 SmallVector<SDValue, 2> Ops;
6876 Ops.push_back(StoreChain);
6877 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvlfiwz, dl, MVT::i32));
6878 Ops.push_back(FIdx);
6880 SmallVector<EVT, 2> ValueVTs;
6881 ValueVTs.push_back(MVT::v4f64);
6882 ValueVTs.push_back(MVT::Other); // chain
6883 SDVTList VTs = DAG.getVTList(ValueVTs);
6885 SDValue LoadedVect = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN,
6886 dl, VTs, Ops, MVT::v4i32, PtrInfo);
6887 LoadedVect = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
6888 DAG.getConstant(Intrinsic::ppc_qpx_qvfcfidu, dl, MVT::i32),
6891 SDValue FPZeros = DAG.getConstantFP(0.0, dl, MVT::f64);
6892 FPZeros = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6893 FPZeros, FPZeros, FPZeros, FPZeros);
6895 return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ);
6898 // All other QPX vectors are handled by generic code.
6899 if (Subtarget.hasQPX())
6902 // Check if this is a splat of a constant value.
6903 APInt APSplatBits, APSplatUndef;
6904 unsigned SplatBitSize;
6906 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6907 HasAnyUndefs, 0, !Subtarget.isLittleEndian()) ||
6911 unsigned SplatBits = APSplatBits.getZExtValue();
6912 unsigned SplatUndef = APSplatUndef.getZExtValue();
6913 unsigned SplatSize = SplatBitSize / 8;
6915 // First, handle single instruction cases.
6918 if (SplatBits == 0) {
6919 // Canonicalize all zero vectors to be v4i32.
6920 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6921 SDValue Z = DAG.getConstant(0, dl, MVT::i32);
6922 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6923 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6928 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6929 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6931 if (SextVal >= -16 && SextVal <= 15)
6932 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6934 // Two instruction sequences.
6936 // If this value is in the range [-32,30] and is even, use:
6937 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6938 // If this value is in the range [17,31] and is odd, use:
6939 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6940 // If this value is in the range [-31,-17] and is odd, use:
6941 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6942 // Note the last two are three-instruction sequences.
6943 if (SextVal >= -32 && SextVal <= 31) {
6944 // To avoid having these optimizations undone by constant folding,
6945 // we convert to a pseudo that will be expanded later into one of
6947 SDValue Elt = DAG.getConstant(SextVal, dl, MVT::i32);
6948 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6949 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6950 SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32);
6951 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6952 if (VT == Op.getValueType())
6955 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6958 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6959 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6961 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6962 // Make -1 and vspltisw -1:
6963 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6965 // Make the VSLW intrinsic, computing 0x8000_0000.
6966 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6969 // xor by OnesV to invert it.
6970 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6971 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6974 // Check to see if this is a wide variety of vsplti*, binop self cases.
6975 static const signed char SplatCsts[] = {
6976 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6977 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6980 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6981 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6982 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6983 int i = SplatCsts[idx];
6985 // Figure out what shift amount will be used by altivec if shifted by i in
6987 unsigned TypeShiftAmt = i & (SplatBitSize-1);
6989 // vsplti + shl self.
6990 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
6991 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6992 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6993 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
6994 Intrinsic::ppc_altivec_vslw
6996 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6997 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7000 // vsplti + srl self.
7001 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
7002 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7003 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7004 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
7005 Intrinsic::ppc_altivec_vsrw
7007 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7008 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7011 // vsplti + sra self.
7012 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
7013 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7014 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7015 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
7016 Intrinsic::ppc_altivec_vsraw
7018 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7019 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7022 // vsplti + rol self.
7023 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
7024 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
7025 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7026 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7027 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
7028 Intrinsic::ppc_altivec_vrlw
7030 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7031 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7034 // t = vsplti c, result = vsldoi t, t, 1
7035 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
7036 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7037 unsigned Amt = Subtarget.isLittleEndian() ? 15 : 1;
7038 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7040 // t = vsplti c, result = vsldoi t, t, 2
7041 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
7042 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7043 unsigned Amt = Subtarget.isLittleEndian() ? 14 : 2;
7044 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7046 // t = vsplti c, result = vsldoi t, t, 3
7047 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
7048 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7049 unsigned Amt = Subtarget.isLittleEndian() ? 13 : 3;
7050 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7057 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
7058 /// the specified operations to build the shuffle.
7059 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
7060 SDValue RHS, SelectionDAG &DAG,
7062 unsigned OpNum = (PFEntry >> 26) & 0x0F;
7063 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
7064 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
7067 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
7079 if (OpNum == OP_COPY) {
7080 if (LHSID == (1*9+2)*9+3) return LHS;
7081 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
7085 SDValue OpLHS, OpRHS;
7086 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
7087 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
7091 default: llvm_unreachable("Unknown i32 permute!");
7093 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
7094 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
7095 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
7096 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
7099 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
7100 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
7101 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
7102 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
7105 for (unsigned i = 0; i != 16; ++i)
7106 ShufIdxs[i] = (i&3)+0;
7109 for (unsigned i = 0; i != 16; ++i)
7110 ShufIdxs[i] = (i&3)+4;
7113 for (unsigned i = 0; i != 16; ++i)
7114 ShufIdxs[i] = (i&3)+8;
7117 for (unsigned i = 0; i != 16; ++i)
7118 ShufIdxs[i] = (i&3)+12;
7121 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
7123 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
7125 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
7127 EVT VT = OpLHS.getValueType();
7128 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
7129 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
7130 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
7131 return DAG.getNode(ISD::BITCAST, dl, VT, T);
7134 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
7135 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
7136 /// return the code it can be lowered into. Worst case, it can always be
7137 /// lowered into a vperm.
7138 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
7139 SelectionDAG &DAG) const {
7141 SDValue V1 = Op.getOperand(0);
7142 SDValue V2 = Op.getOperand(1);
7143 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7144 EVT VT = Op.getValueType();
7145 bool isLittleEndian = Subtarget.isLittleEndian();
7147 if (Subtarget.hasQPX()) {
7148 if (VT.getVectorNumElements() != 4)
7151 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7153 int AlignIdx = PPC::isQVALIGNIShuffleMask(SVOp);
7154 if (AlignIdx != -1) {
7155 return DAG.getNode(PPCISD::QVALIGNI, dl, VT, V1, V2,
7156 DAG.getConstant(AlignIdx, dl, MVT::i32));
7157 } else if (SVOp->isSplat()) {
7158 int SplatIdx = SVOp->getSplatIndex();
7159 if (SplatIdx >= 4) {
7164 // FIXME: If SplatIdx == 0 and the input came from a load, then there is
7167 return DAG.getNode(PPCISD::QVESPLATI, dl, VT, V1,
7168 DAG.getConstant(SplatIdx, dl, MVT::i32));
7171 // Lower this into a qvgpci/qvfperm pair.
7173 // Compute the qvgpci literal
7175 for (unsigned i = 0; i < 4; ++i) {
7176 int m = SVOp->getMaskElt(i);
7177 unsigned mm = m >= 0 ? (unsigned) m : i;
7178 idx |= mm << (3-i)*3;
7181 SDValue V3 = DAG.getNode(PPCISD::QVGPCI, dl, MVT::v4f64,
7182 DAG.getConstant(idx, dl, MVT::i32));
7183 return DAG.getNode(PPCISD::QVFPERM, dl, VT, V1, V2, V3);
7186 // Cases that are handled by instructions that take permute immediates
7187 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
7188 // selected by the instruction selector.
7189 if (V2.getOpcode() == ISD::UNDEF) {
7190 if (PPC::isSplatShuffleMask(SVOp, 1) ||
7191 PPC::isSplatShuffleMask(SVOp, 2) ||
7192 PPC::isSplatShuffleMask(SVOp, 4) ||
7193 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
7194 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
7195 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
7196 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
7197 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
7198 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
7199 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
7200 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
7201 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG) ||
7202 (Subtarget.hasP8Altivec() && (
7203 PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
7204 PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
7205 PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)))) {
7210 // Altivec has a variety of "shuffle immediates" that take two vector inputs
7211 // and produce a fixed permutation. If any of these match, do not lower to
7213 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
7214 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7215 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7216 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
7217 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7218 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7219 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7220 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7221 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7222 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7223 (Subtarget.hasP8Altivec() && (
7224 PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7225 PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
7226 PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))))
7229 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
7230 // perfect shuffle table to emit an optimal matching sequence.
7231 ArrayRef<int> PermMask = SVOp->getMask();
7233 unsigned PFIndexes[4];
7234 bool isFourElementShuffle = true;
7235 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
7236 unsigned EltNo = 8; // Start out undef.
7237 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
7238 if (PermMask[i*4+j] < 0)
7239 continue; // Undef, ignore it.
7241 unsigned ByteSource = PermMask[i*4+j];
7242 if ((ByteSource & 3) != j) {
7243 isFourElementShuffle = false;
7248 EltNo = ByteSource/4;
7249 } else if (EltNo != ByteSource/4) {
7250 isFourElementShuffle = false;
7254 PFIndexes[i] = EltNo;
7257 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
7258 // perfect shuffle vector to determine if it is cost effective to do this as
7259 // discrete instructions, or whether we should use a vperm.
7260 // For now, we skip this for little endian until such time as we have a
7261 // little-endian perfect shuffle table.
7262 if (isFourElementShuffle && !isLittleEndian) {
7263 // Compute the index in the perfect shuffle table.
7264 unsigned PFTableIndex =
7265 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
7267 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
7268 unsigned Cost = (PFEntry >> 30);
7270 // Determining when to avoid vperm is tricky. Many things affect the cost
7271 // of vperm, particularly how many times the perm mask needs to be computed.
7272 // For example, if the perm mask can be hoisted out of a loop or is already
7273 // used (perhaps because there are multiple permutes with the same shuffle
7274 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
7275 // the loop requires an extra register.
7277 // As a compromise, we only emit discrete instructions if the shuffle can be
7278 // generated in 3 or fewer operations. When we have loop information
7279 // available, if this block is within a loop, we should avoid using vperm
7280 // for 3-operation perms and use a constant pool load instead.
7282 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
7285 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
7286 // vector that will get spilled to the constant pool.
7287 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7289 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
7290 // that it is in input element units, not in bytes. Convert now.
7292 // For little endian, the order of the input vectors is reversed, and
7293 // the permutation mask is complemented with respect to 31. This is
7294 // necessary to produce proper semantics with the big-endian-biased vperm
7296 EVT EltVT = V1.getValueType().getVectorElementType();
7297 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
7299 SmallVector<SDValue, 16> ResultMask;
7300 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
7301 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
7303 for (unsigned j = 0; j != BytesPerElement; ++j)
7305 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement + j),
7308 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement + j, dl,
7312 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
7315 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7318 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7322 /// getVectorCompareInfo - Given an intrinsic, return false if it is not a
7323 /// vector comparison. If it is, return true and fill in Opc/isDot with
7324 /// information about the intrinsic.
7325 static bool getVectorCompareInfo(SDValue Intrin, int &CompareOpc,
7326 bool &isDot, const PPCSubtarget &Subtarget) {
7327 unsigned IntrinsicID =
7328 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
7331 switch (IntrinsicID) {
7332 default: return false;
7333 // Comparison predicates.
7334 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
7335 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
7336 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
7337 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
7338 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
7339 case Intrinsic::ppc_altivec_vcmpequd_p:
7340 if (Subtarget.hasP8Altivec()) {
7347 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
7348 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
7349 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
7350 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
7351 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
7352 case Intrinsic::ppc_altivec_vcmpgtsd_p:
7353 if (Subtarget.hasP8Altivec()) {
7360 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
7361 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
7362 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
7363 case Intrinsic::ppc_altivec_vcmpgtud_p:
7364 if (Subtarget.hasP8Altivec()) {
7371 // VSX predicate comparisons use the same infrastructure
7372 case Intrinsic::ppc_vsx_xvcmpeqdp_p:
7373 case Intrinsic::ppc_vsx_xvcmpgedp_p:
7374 case Intrinsic::ppc_vsx_xvcmpgtdp_p:
7375 case Intrinsic::ppc_vsx_xvcmpeqsp_p:
7376 case Intrinsic::ppc_vsx_xvcmpgesp_p:
7377 case Intrinsic::ppc_vsx_xvcmpgtsp_p:
7378 if (Subtarget.hasVSX()) {
7379 switch (IntrinsicID) {
7380 case Intrinsic::ppc_vsx_xvcmpeqdp_p: CompareOpc = 99; break;
7381 case Intrinsic::ppc_vsx_xvcmpgedp_p: CompareOpc = 115; break;
7382 case Intrinsic::ppc_vsx_xvcmpgtdp_p: CompareOpc = 107; break;
7383 case Intrinsic::ppc_vsx_xvcmpeqsp_p: CompareOpc = 67; break;
7384 case Intrinsic::ppc_vsx_xvcmpgesp_p: CompareOpc = 83; break;
7385 case Intrinsic::ppc_vsx_xvcmpgtsp_p: CompareOpc = 75; break;
7394 // Normal Comparisons.
7395 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
7396 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
7397 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
7398 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
7399 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
7400 case Intrinsic::ppc_altivec_vcmpequd:
7401 if (Subtarget.hasP8Altivec()) {
7408 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
7409 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
7410 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
7411 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
7412 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
7413 case Intrinsic::ppc_altivec_vcmpgtsd:
7414 if (Subtarget.hasP8Altivec()) {
7421 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
7422 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
7423 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
7424 case Intrinsic::ppc_altivec_vcmpgtud:
7425 if (Subtarget.hasP8Altivec()) {
7436 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
7437 /// lower, do it, otherwise return null.
7438 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
7439 SelectionDAG &DAG) const {
7440 // If this is a lowered altivec predicate compare, CompareOpc is set to the
7441 // opcode number of the comparison.
7445 if (!getVectorCompareInfo(Op, CompareOpc, isDot, Subtarget))
7446 return SDValue(); // Don't custom lower most intrinsics.
7448 // If this is a non-dot comparison, make the VCMP node and we are done.
7450 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
7451 Op.getOperand(1), Op.getOperand(2),
7452 DAG.getConstant(CompareOpc, dl, MVT::i32));
7453 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
7456 // Create the PPCISD altivec 'dot' comparison node.
7458 Op.getOperand(2), // LHS
7459 Op.getOperand(3), // RHS
7460 DAG.getConstant(CompareOpc, dl, MVT::i32)
7462 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
7463 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
7465 // Now that we have the comparison, emit a copy from the CR to a GPR.
7466 // This is flagged to the above dot comparison.
7467 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
7468 DAG.getRegister(PPC::CR6, MVT::i32),
7469 CompNode.getValue(1));
7471 // Unpack the result based on how the target uses it.
7472 unsigned BitNo; // Bit # of CR6.
7473 bool InvertBit; // Invert result?
7474 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
7475 default: // Can't happen, don't crash on invalid number though.
7476 case 0: // Return the value of the EQ bit of CR6.
7477 BitNo = 0; InvertBit = false;
7479 case 1: // Return the inverted value of the EQ bit of CR6.
7480 BitNo = 0; InvertBit = true;
7482 case 2: // Return the value of the LT bit of CR6.
7483 BitNo = 2; InvertBit = false;
7485 case 3: // Return the inverted value of the LT bit of CR6.
7486 BitNo = 2; InvertBit = true;
7490 // Shift the bit into the low position.
7491 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
7492 DAG.getConstant(8 - (3 - BitNo), dl, MVT::i32));
7494 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
7495 DAG.getConstant(1, dl, MVT::i32));
7497 // If we are supposed to, toggle the bit.
7499 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
7500 DAG.getConstant(1, dl, MVT::i32));
7504 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
7505 SelectionDAG &DAG) const {
7507 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
7508 // instructions), but for smaller types, we need to first extend up to v2i32
7509 // before doing going farther.
7510 if (Op.getValueType() == MVT::v2i64) {
7511 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
7512 if (ExtVT != MVT::v2i32) {
7513 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
7514 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
7515 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
7516 ExtVT.getVectorElementType(), 4)));
7517 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
7518 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
7519 DAG.getValueType(MVT::v2i32));
7528 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
7529 SelectionDAG &DAG) const {
7531 // Create a stack slot that is 16-byte aligned.
7532 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7533 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7534 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7535 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7537 // Store the input value into Value#0 of the stack slot.
7538 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
7539 Op.getOperand(0), FIdx, MachinePointerInfo(),
7542 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
7543 false, false, false, 0);
7546 SDValue PPCTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7547 SelectionDAG &DAG) const {
7549 SDNode *N = Op.getNode();
7551 assert(N->getOperand(0).getValueType() == MVT::v4i1 &&
7552 "Unknown extract_vector_elt type");
7554 SDValue Value = N->getOperand(0);
7556 // The first part of this is like the store lowering except that we don't
7557 // need to track the chain.
7559 // The values are now known to be -1 (false) or 1 (true). To convert this
7560 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7561 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7562 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7564 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7565 // understand how to form the extending load.
7566 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7567 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7568 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7570 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7572 // Now convert to an integer and store.
7573 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7574 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7577 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7578 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7579 MachinePointerInfo PtrInfo =
7580 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
7581 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7582 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7584 SDValue StoreChain = DAG.getEntryNode();
7585 SmallVector<SDValue, 2> Ops;
7586 Ops.push_back(StoreChain);
7587 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7588 Ops.push_back(Value);
7589 Ops.push_back(FIdx);
7591 SmallVector<EVT, 2> ValueVTs;
7592 ValueVTs.push_back(MVT::Other); // chain
7593 SDVTList VTs = DAG.getVTList(ValueVTs);
7595 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7596 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7598 // Extract the value requested.
7599 unsigned Offset = 4*cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7600 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7601 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7603 SDValue IntVal = DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7604 PtrInfo.getWithOffset(Offset),
7605 false, false, false, 0);
7607 if (!Subtarget.useCRBits())
7610 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, IntVal);
7613 /// Lowering for QPX v4i1 loads
7614 SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
7615 SelectionDAG &DAG) const {
7617 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
7618 SDValue LoadChain = LN->getChain();
7619 SDValue BasePtr = LN->getBasePtr();
7621 if (Op.getValueType() == MVT::v4f64 ||
7622 Op.getValueType() == MVT::v4f32) {
7623 EVT MemVT = LN->getMemoryVT();
7624 unsigned Alignment = LN->getAlignment();
7626 // If this load is properly aligned, then it is legal.
7627 if (Alignment >= MemVT.getStoreSize())
7630 EVT ScalarVT = Op.getValueType().getScalarType(),
7631 ScalarMemVT = MemVT.getScalarType();
7632 unsigned Stride = ScalarMemVT.getStoreSize();
7634 SmallVector<SDValue, 8> Vals, LoadChains;
7635 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7637 if (ScalarVT != ScalarMemVT)
7639 DAG.getExtLoad(LN->getExtensionType(), dl, ScalarVT, LoadChain,
7641 LN->getPointerInfo().getWithOffset(Idx*Stride),
7642 ScalarMemVT, LN->isVolatile(), LN->isNonTemporal(),
7643 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7647 DAG.getLoad(ScalarVT, dl, LoadChain, BasePtr,
7648 LN->getPointerInfo().getWithOffset(Idx*Stride),
7649 LN->isVolatile(), LN->isNonTemporal(),
7650 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7653 if (Idx == 0 && LN->isIndexed()) {
7654 assert(LN->getAddressingMode() == ISD::PRE_INC &&
7655 "Unknown addressing mode on vector load");
7656 Load = DAG.getIndexedLoad(Load, dl, BasePtr, LN->getOffset(),
7657 LN->getAddressingMode());
7660 Vals.push_back(Load);
7661 LoadChains.push_back(Load.getValue(1));
7663 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7664 DAG.getConstant(Stride, dl,
7665 BasePtr.getValueType()));
7668 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7669 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
7670 Op.getValueType(), Vals);
7672 if (LN->isIndexed()) {
7673 SDValue RetOps[] = { Value, Vals[0].getValue(1), TF };
7674 return DAG.getMergeValues(RetOps, dl);
7677 SDValue RetOps[] = { Value, TF };
7678 return DAG.getMergeValues(RetOps, dl);
7681 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower");
7682 assert(LN->isUnindexed() && "Indexed v4i1 loads are not supported");
7684 // To lower v4i1 from a byte array, we load the byte elements of the
7685 // vector and then reuse the BUILD_VECTOR logic.
7687 SmallVector<SDValue, 4> VectElmts, VectElmtChains;
7688 for (unsigned i = 0; i < 4; ++i) {
7689 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7690 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7692 VectElmts.push_back(DAG.getExtLoad(ISD::EXTLOAD,
7693 dl, MVT::i32, LoadChain, Idx,
7694 LN->getPointerInfo().getWithOffset(i),
7695 MVT::i8 /* memory type */,
7696 LN->isVolatile(), LN->isNonTemporal(),
7698 1 /* alignment */, LN->getAAInfo()));
7699 VectElmtChains.push_back(VectElmts[i].getValue(1));
7702 LoadChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, VectElmtChains);
7703 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i1, VectElmts);
7705 SDValue RVals[] = { Value, LoadChain };
7706 return DAG.getMergeValues(RVals, dl);
7709 /// Lowering for QPX v4i1 stores
7710 SDValue PPCTargetLowering::LowerVectorStore(SDValue Op,
7711 SelectionDAG &DAG) const {
7713 StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
7714 SDValue StoreChain = SN->getChain();
7715 SDValue BasePtr = SN->getBasePtr();
7716 SDValue Value = SN->getValue();
7718 if (Value.getValueType() == MVT::v4f64 ||
7719 Value.getValueType() == MVT::v4f32) {
7720 EVT MemVT = SN->getMemoryVT();
7721 unsigned Alignment = SN->getAlignment();
7723 // If this store is properly aligned, then it is legal.
7724 if (Alignment >= MemVT.getStoreSize())
7727 EVT ScalarVT = Value.getValueType().getScalarType(),
7728 ScalarMemVT = MemVT.getScalarType();
7729 unsigned Stride = ScalarMemVT.getStoreSize();
7731 SmallVector<SDValue, 8> Stores;
7732 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7733 SDValue Ex = DAG.getNode(
7734 ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, Value,
7735 DAG.getConstant(Idx, dl, getVectorIdxTy(DAG.getDataLayout())));
7737 if (ScalarVT != ScalarMemVT)
7739 DAG.getTruncStore(StoreChain, dl, Ex, BasePtr,
7740 SN->getPointerInfo().getWithOffset(Idx*Stride),
7741 ScalarMemVT, SN->isVolatile(), SN->isNonTemporal(),
7742 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7745 DAG.getStore(StoreChain, dl, Ex, BasePtr,
7746 SN->getPointerInfo().getWithOffset(Idx*Stride),
7747 SN->isVolatile(), SN->isNonTemporal(),
7748 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7750 if (Idx == 0 && SN->isIndexed()) {
7751 assert(SN->getAddressingMode() == ISD::PRE_INC &&
7752 "Unknown addressing mode on vector store");
7753 Store = DAG.getIndexedStore(Store, dl, BasePtr, SN->getOffset(),
7754 SN->getAddressingMode());
7757 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7758 DAG.getConstant(Stride, dl,
7759 BasePtr.getValueType()));
7760 Stores.push_back(Store);
7763 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7765 if (SN->isIndexed()) {
7766 SDValue RetOps[] = { TF, Stores[0].getValue(1) };
7767 return DAG.getMergeValues(RetOps, dl);
7773 assert(SN->isUnindexed() && "Indexed v4i1 stores are not supported");
7774 assert(Value.getValueType() == MVT::v4i1 && "Unknown store to lower");
7776 // The values are now known to be -1 (false) or 1 (true). To convert this
7777 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7778 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7779 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7781 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7782 // understand how to form the extending load.
7783 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7784 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7785 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7787 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7789 // Now convert to an integer and store.
7790 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7791 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7794 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7795 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7796 MachinePointerInfo PtrInfo =
7797 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
7798 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7799 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7801 SmallVector<SDValue, 2> Ops;
7802 Ops.push_back(StoreChain);
7803 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7804 Ops.push_back(Value);
7805 Ops.push_back(FIdx);
7807 SmallVector<EVT, 2> ValueVTs;
7808 ValueVTs.push_back(MVT::Other); // chain
7809 SDVTList VTs = DAG.getVTList(ValueVTs);
7811 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7812 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7814 // Move data into the byte array.
7815 SmallVector<SDValue, 4> Loads, LoadChains;
7816 for (unsigned i = 0; i < 4; ++i) {
7817 unsigned Offset = 4*i;
7818 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7819 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7821 Loads.push_back(DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7822 PtrInfo.getWithOffset(Offset),
7823 false, false, false, 0));
7824 LoadChains.push_back(Loads[i].getValue(1));
7827 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7829 SmallVector<SDValue, 4> Stores;
7830 for (unsigned i = 0; i < 4; ++i) {
7831 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7832 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7834 Stores.push_back(DAG.getTruncStore(
7835 StoreChain, dl, Loads[i], Idx, SN->getPointerInfo().getWithOffset(i),
7836 MVT::i8 /* memory type */, SN->isNonTemporal(), SN->isVolatile(),
7837 1 /* alignment */, SN->getAAInfo()));
7840 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7845 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
7847 if (Op.getValueType() == MVT::v4i32) {
7848 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7850 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
7851 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
7853 SDValue RHSSwap = // = vrlw RHS, 16
7854 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
7856 // Shrinkify inputs to v8i16.
7857 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
7858 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
7859 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
7861 // Low parts multiplied together, generating 32-bit results (we ignore the
7863 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
7864 LHS, RHS, DAG, dl, MVT::v4i32);
7866 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
7867 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
7868 // Shift the high parts up 16 bits.
7869 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
7871 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
7872 } else if (Op.getValueType() == MVT::v8i16) {
7873 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7875 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
7877 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
7878 LHS, RHS, Zero, DAG, dl);
7879 } else if (Op.getValueType() == MVT::v16i8) {
7880 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7881 bool isLittleEndian = Subtarget.isLittleEndian();
7883 // Multiply the even 8-bit parts, producing 16-bit sums.
7884 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
7885 LHS, RHS, DAG, dl, MVT::v8i16);
7886 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
7888 // Multiply the odd 8-bit parts, producing 16-bit sums.
7889 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
7890 LHS, RHS, DAG, dl, MVT::v8i16);
7891 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
7893 // Merge the results together. Because vmuleub and vmuloub are
7894 // instructions with a big-endian bias, we must reverse the
7895 // element numbering and reverse the meaning of "odd" and "even"
7896 // when generating little endian code.
7898 for (unsigned i = 0; i != 8; ++i) {
7899 if (isLittleEndian) {
7901 Ops[i*2+1] = 2*i+16;
7904 Ops[i*2+1] = 2*i+1+16;
7908 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
7910 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
7912 llvm_unreachable("Unknown mul to lower!");
7916 /// LowerOperation - Provide custom lowering hooks for some operations.
7918 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7919 switch (Op.getOpcode()) {
7920 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
7921 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7922 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7923 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7924 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7925 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7926 case ISD::SETCC: return LowerSETCC(Op, DAG);
7927 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
7928 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
7930 return LowerVASTART(Op, DAG, Subtarget);
7933 return LowerVAARG(Op, DAG, Subtarget);
7936 return LowerVACOPY(Op, DAG, Subtarget);
7938 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
7939 case ISD::DYNAMIC_STACKALLOC:
7940 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
7942 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
7943 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
7945 case ISD::LOAD: return LowerLOAD(Op, DAG);
7946 case ISD::STORE: return LowerSTORE(Op, DAG);
7947 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
7948 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
7949 case ISD::FP_TO_UINT:
7950 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
7952 case ISD::UINT_TO_FP:
7953 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
7954 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7956 // Lower 64-bit shifts.
7957 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
7958 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
7959 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
7961 // Vector-related lowering.
7962 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7963 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7964 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7965 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7966 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
7967 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7968 case ISD::MUL: return LowerMUL(Op, DAG);
7970 // For counter-based loop handling.
7971 case ISD::INTRINSIC_W_CHAIN: return SDValue();
7973 // Frame & Return address.
7974 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7975 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7979 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
7980 SmallVectorImpl<SDValue>&Results,
7981 SelectionDAG &DAG) const {
7983 switch (N->getOpcode()) {
7985 llvm_unreachable("Do not know how to custom type legalize this operation!");
7986 case ISD::READCYCLECOUNTER: {
7987 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7988 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
7990 Results.push_back(RTB);
7991 Results.push_back(RTB.getValue(1));
7992 Results.push_back(RTB.getValue(2));
7995 case ISD::INTRINSIC_W_CHAIN: {
7996 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
7997 Intrinsic::ppc_is_decremented_ctr_nonzero)
8000 assert(N->getValueType(0) == MVT::i1 &&
8001 "Unexpected result type for CTR decrement intrinsic");
8002 EVT SVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
8003 N->getValueType(0));
8004 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
8005 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
8008 Results.push_back(NewInt);
8009 Results.push_back(NewInt.getValue(1));
8013 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
8016 EVT VT = N->getValueType(0);
8018 if (VT == MVT::i64) {
8019 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
8021 Results.push_back(NewNode);
8022 Results.push_back(NewNode.getValue(1));
8026 case ISD::FP_ROUND_INREG: {
8027 assert(N->getValueType(0) == MVT::ppcf128);
8028 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
8029 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
8030 MVT::f64, N->getOperand(0),
8031 DAG.getIntPtrConstant(0, dl));
8032 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
8033 MVT::f64, N->getOperand(0),
8034 DAG.getIntPtrConstant(1, dl));
8036 // Add the two halves of the long double in round-to-zero mode.
8037 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
8039 // We know the low half is about to be thrown away, so just use something
8041 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
8045 case ISD::FP_TO_SINT:
8046 case ISD::FP_TO_UINT:
8047 // LowerFP_TO_INT() can only handle f32 and f64.
8048 if (N->getOperand(0).getValueType() == MVT::ppcf128)
8050 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
8055 //===----------------------------------------------------------------------===//
8056 // Other Lowering Code
8057 //===----------------------------------------------------------------------===//
8059 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
8060 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8061 Function *Func = Intrinsic::getDeclaration(M, Id);
8062 return Builder.CreateCall(Func, {});
8065 // The mappings for emitLeading/TrailingFence is taken from
8066 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
8067 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
8068 AtomicOrdering Ord, bool IsStore,
8069 bool IsLoad) const {
8070 if (Ord == SequentiallyConsistent)
8071 return callIntrinsic(Builder, Intrinsic::ppc_sync);
8072 if (isAtLeastRelease(Ord))
8073 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8077 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
8078 AtomicOrdering Ord, bool IsStore,
8079 bool IsLoad) const {
8080 if (IsLoad && isAtLeastAcquire(Ord))
8081 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8082 // FIXME: this is too conservative, a dependent branch + isync is enough.
8083 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
8084 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
8085 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
8090 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
8091 unsigned AtomicSize,
8092 unsigned BinOpcode) const {
8093 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8094 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8096 auto LoadMnemonic = PPC::LDARX;
8097 auto StoreMnemonic = PPC::STDCX;
8098 switch (AtomicSize) {
8100 llvm_unreachable("Unexpected size of atomic entity");
8102 LoadMnemonic = PPC::LBARX;
8103 StoreMnemonic = PPC::STBCX;
8104 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8107 LoadMnemonic = PPC::LHARX;
8108 StoreMnemonic = PPC::STHCX;
8109 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8112 LoadMnemonic = PPC::LWARX;
8113 StoreMnemonic = PPC::STWCX;
8116 LoadMnemonic = PPC::LDARX;
8117 StoreMnemonic = PPC::STDCX;
8121 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8122 MachineFunction *F = BB->getParent();
8123 MachineFunction::iterator It = ++BB->getIterator();
8125 unsigned dest = MI->getOperand(0).getReg();
8126 unsigned ptrA = MI->getOperand(1).getReg();
8127 unsigned ptrB = MI->getOperand(2).getReg();
8128 unsigned incr = MI->getOperand(3).getReg();
8129 DebugLoc dl = MI->getDebugLoc();
8131 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8132 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8133 F->insert(It, loopMBB);
8134 F->insert(It, exitMBB);
8135 exitMBB->splice(exitMBB->begin(), BB,
8136 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8137 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8139 MachineRegisterInfo &RegInfo = F->getRegInfo();
8140 unsigned TmpReg = (!BinOpcode) ? incr :
8141 RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass
8142 : &PPC::GPRCRegClass);
8146 // fallthrough --> loopMBB
8147 BB->addSuccessor(loopMBB);
8150 // l[wd]arx dest, ptr
8151 // add r0, dest, incr
8152 // st[wd]cx. r0, ptr
8154 // fallthrough --> exitMBB
8156 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8157 .addReg(ptrA).addReg(ptrB);
8159 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
8160 BuildMI(BB, dl, TII->get(StoreMnemonic))
8161 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
8162 BuildMI(BB, dl, TII->get(PPC::BCC))
8163 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8164 BB->addSuccessor(loopMBB);
8165 BB->addSuccessor(exitMBB);
8174 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
8175 MachineBasicBlock *BB,
8176 bool is8bit, // operation
8177 unsigned BinOpcode) const {
8178 // If we support part-word atomic mnemonics, just use them
8179 if (Subtarget.hasPartwordAtomics())
8180 return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode);
8182 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8183 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8184 // In 64 bit mode we have to use 64 bits for addresses, even though the
8185 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
8186 // registers without caring whether they're 32 or 64, but here we're
8187 // doing actual arithmetic on the addresses.
8188 bool is64bit = Subtarget.isPPC64();
8189 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8191 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8192 MachineFunction *F = BB->getParent();
8193 MachineFunction::iterator It = ++BB->getIterator();
8195 unsigned dest = MI->getOperand(0).getReg();
8196 unsigned ptrA = MI->getOperand(1).getReg();
8197 unsigned ptrB = MI->getOperand(2).getReg();
8198 unsigned incr = MI->getOperand(3).getReg();
8199 DebugLoc dl = MI->getDebugLoc();
8201 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8202 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8203 F->insert(It, loopMBB);
8204 F->insert(It, exitMBB);
8205 exitMBB->splice(exitMBB->begin(), BB,
8206 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8207 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8209 MachineRegisterInfo &RegInfo = F->getRegInfo();
8210 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8211 : &PPC::GPRCRegClass;
8212 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8213 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8214 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8215 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
8216 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8217 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8218 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8219 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8220 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
8221 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8222 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8224 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
8228 // fallthrough --> loopMBB
8229 BB->addSuccessor(loopMBB);
8231 // The 4-byte load must be aligned, while a char or short may be
8232 // anywhere in the word. Hence all this nasty bookkeeping code.
8233 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8234 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8235 // xori shift, shift1, 24 [16]
8236 // rlwinm ptr, ptr1, 0, 0, 29
8237 // slw incr2, incr, shift
8238 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8239 // slw mask, mask2, shift
8241 // lwarx tmpDest, ptr
8242 // add tmp, tmpDest, incr2
8243 // andc tmp2, tmpDest, mask
8244 // and tmp3, tmp, mask
8245 // or tmp4, tmp3, tmp2
8248 // fallthrough --> exitMBB
8249 // srw dest, tmpDest, shift
8250 if (ptrA != ZeroReg) {
8251 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8252 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8253 .addReg(ptrA).addReg(ptrB);
8257 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8258 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8259 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8260 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8262 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8263 .addReg(Ptr1Reg).addImm(0).addImm(61);
8265 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8266 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8267 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
8268 .addReg(incr).addReg(ShiftReg);
8270 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
8272 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
8273 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
8275 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
8276 .addReg(Mask2Reg).addReg(ShiftReg);
8279 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
8280 .addReg(ZeroReg).addReg(PtrReg);
8282 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
8283 .addReg(Incr2Reg).addReg(TmpDestReg);
8284 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
8285 .addReg(TmpDestReg).addReg(MaskReg);
8286 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
8287 .addReg(TmpReg).addReg(MaskReg);
8288 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
8289 .addReg(Tmp3Reg).addReg(Tmp2Reg);
8290 BuildMI(BB, dl, TII->get(PPC::STWCX))
8291 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
8292 BuildMI(BB, dl, TII->get(PPC::BCC))
8293 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8294 BB->addSuccessor(loopMBB);
8295 BB->addSuccessor(exitMBB);
8300 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
8305 llvm::MachineBasicBlock*
8306 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
8307 MachineBasicBlock *MBB) const {
8308 DebugLoc DL = MI->getDebugLoc();
8309 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8311 MachineFunction *MF = MBB->getParent();
8312 MachineRegisterInfo &MRI = MF->getRegInfo();
8314 const BasicBlock *BB = MBB->getBasicBlock();
8315 MachineFunction::iterator I = ++MBB->getIterator();
8318 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8319 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8321 unsigned DstReg = MI->getOperand(0).getReg();
8322 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
8323 assert(RC->hasType(MVT::i32) && "Invalid destination!");
8324 unsigned mainDstReg = MRI.createVirtualRegister(RC);
8325 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
8327 MVT PVT = getPointerTy(MF->getDataLayout());
8328 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8329 "Invalid Pointer Size!");
8330 // For v = setjmp(buf), we generate
8333 // SjLjSetup mainMBB
8339 // buf[LabelOffset] = LR
8343 // v = phi(main, restore)
8346 MachineBasicBlock *thisMBB = MBB;
8347 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
8348 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
8349 MF->insert(I, mainMBB);
8350 MF->insert(I, sinkMBB);
8352 MachineInstrBuilder MIB;
8354 // Transfer the remainder of BB and its successor edges to sinkMBB.
8355 sinkMBB->splice(sinkMBB->begin(), MBB,
8356 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
8357 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
8359 // Note that the structure of the jmp_buf used here is not compatible
8360 // with that used by libc, and is not designed to be. Specifically, it
8361 // stores only those 'reserved' registers that LLVM does not otherwise
8362 // understand how to spill. Also, by convention, by the time this
8363 // intrinsic is called, Clang has already stored the frame address in the
8364 // first slot of the buffer and stack address in the third. Following the
8365 // X86 target code, we'll store the jump address in the second slot. We also
8366 // need to save the TOC pointer (R2) to handle jumps between shared
8367 // libraries, and that will be stored in the fourth slot. The thread
8368 // identifier (R13) is not affected.
8371 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8372 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8373 const int64_t BPOffset = 4 * PVT.getStoreSize();
8375 // Prepare IP either in reg.
8376 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
8377 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
8378 unsigned BufReg = MI->getOperand(1).getReg();
8380 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
8381 setUsesTOCBasePtr(*MBB->getParent());
8382 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
8386 MIB.setMemRefs(MMOBegin, MMOEnd);
8389 // Naked functions never have a base pointer, and so we use r1. For all
8390 // other functions, this decision must be delayed until during PEI.
8392 if (MF->getFunction()->hasFnAttribute(Attribute::Naked))
8393 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
8395 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
8397 MIB = BuildMI(*thisMBB, MI, DL,
8398 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
8402 MIB.setMemRefs(MMOBegin, MMOEnd);
8405 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
8406 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
8407 MIB.addRegMask(TRI->getNoPreservedMask());
8409 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
8411 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
8413 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
8415 thisMBB->addSuccessor(mainMBB, BranchProbability::getZero());
8416 thisMBB->addSuccessor(sinkMBB, BranchProbability::getOne());
8421 BuildMI(mainMBB, DL,
8422 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
8425 if (Subtarget.isPPC64()) {
8426 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
8428 .addImm(LabelOffset)
8431 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
8433 .addImm(LabelOffset)
8437 MIB.setMemRefs(MMOBegin, MMOEnd);
8439 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
8440 mainMBB->addSuccessor(sinkMBB);
8443 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
8444 TII->get(PPC::PHI), DstReg)
8445 .addReg(mainDstReg).addMBB(mainMBB)
8446 .addReg(restoreDstReg).addMBB(thisMBB);
8448 MI->eraseFromParent();
8453 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
8454 MachineBasicBlock *MBB) const {
8455 DebugLoc DL = MI->getDebugLoc();
8456 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8458 MachineFunction *MF = MBB->getParent();
8459 MachineRegisterInfo &MRI = MF->getRegInfo();
8462 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8463 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8465 MVT PVT = getPointerTy(MF->getDataLayout());
8466 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8467 "Invalid Pointer Size!");
8469 const TargetRegisterClass *RC =
8470 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
8471 unsigned Tmp = MRI.createVirtualRegister(RC);
8472 // Since FP is only updated here but NOT referenced, it's treated as GPR.
8473 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
8474 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
8478 : (Subtarget.isSVR4ABI() &&
8479 MF->getTarget().getRelocationModel() == Reloc::PIC_
8483 MachineInstrBuilder MIB;
8485 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8486 const int64_t SPOffset = 2 * PVT.getStoreSize();
8487 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8488 const int64_t BPOffset = 4 * PVT.getStoreSize();
8490 unsigned BufReg = MI->getOperand(0).getReg();
8492 // Reload FP (the jumped-to function may not have had a
8493 // frame pointer, and if so, then its r31 will be restored
8495 if (PVT == MVT::i64) {
8496 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
8500 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
8504 MIB.setMemRefs(MMOBegin, MMOEnd);
8507 if (PVT == MVT::i64) {
8508 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
8509 .addImm(LabelOffset)
8512 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
8513 .addImm(LabelOffset)
8516 MIB.setMemRefs(MMOBegin, MMOEnd);
8519 if (PVT == MVT::i64) {
8520 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
8524 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
8528 MIB.setMemRefs(MMOBegin, MMOEnd);
8531 if (PVT == MVT::i64) {
8532 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
8536 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
8540 MIB.setMemRefs(MMOBegin, MMOEnd);
8543 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
8544 setUsesTOCBasePtr(*MBB->getParent());
8545 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
8549 MIB.setMemRefs(MMOBegin, MMOEnd);
8553 BuildMI(*MBB, MI, DL,
8554 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
8555 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
8557 MI->eraseFromParent();
8562 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8563 MachineBasicBlock *BB) const {
8564 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
8565 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8566 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
8567 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8568 // Call lowering should have added an r2 operand to indicate a dependence
8569 // on the TOC base pointer value. It can't however, because there is no
8570 // way to mark the dependence as implicit there, and so the stackmap code
8571 // will confuse it with a regular operand. Instead, add the dependence
8573 setUsesTOCBasePtr(*BB->getParent());
8574 MI->addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
8577 return emitPatchPoint(MI, BB);
8580 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
8581 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
8582 return emitEHSjLjSetJmp(MI, BB);
8583 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
8584 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
8585 return emitEHSjLjLongJmp(MI, BB);
8588 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8590 // To "insert" these instructions we actually have to insert their
8591 // control-flow patterns.
8592 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8593 MachineFunction::iterator It = ++BB->getIterator();
8595 MachineFunction *F = BB->getParent();
8597 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8598 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8599 MI->getOpcode() == PPC::SELECT_I4 ||
8600 MI->getOpcode() == PPC::SELECT_I8)) {
8601 SmallVector<MachineOperand, 2> Cond;
8602 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8603 MI->getOpcode() == PPC::SELECT_CC_I8)
8604 Cond.push_back(MI->getOperand(4));
8606 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
8607 Cond.push_back(MI->getOperand(1));
8609 DebugLoc dl = MI->getDebugLoc();
8610 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
8611 Cond, MI->getOperand(2).getReg(),
8612 MI->getOperand(3).getReg());
8613 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8614 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8615 MI->getOpcode() == PPC::SELECT_CC_F4 ||
8616 MI->getOpcode() == PPC::SELECT_CC_F8 ||
8617 MI->getOpcode() == PPC::SELECT_CC_QFRC ||
8618 MI->getOpcode() == PPC::SELECT_CC_QSRC ||
8619 MI->getOpcode() == PPC::SELECT_CC_QBRC ||
8620 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
8621 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
8622 MI->getOpcode() == PPC::SELECT_CC_VSSRC ||
8623 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
8624 MI->getOpcode() == PPC::SELECT_I4 ||
8625 MI->getOpcode() == PPC::SELECT_I8 ||
8626 MI->getOpcode() == PPC::SELECT_F4 ||
8627 MI->getOpcode() == PPC::SELECT_F8 ||
8628 MI->getOpcode() == PPC::SELECT_QFRC ||
8629 MI->getOpcode() == PPC::SELECT_QSRC ||
8630 MI->getOpcode() == PPC::SELECT_QBRC ||
8631 MI->getOpcode() == PPC::SELECT_VRRC ||
8632 MI->getOpcode() == PPC::SELECT_VSFRC ||
8633 MI->getOpcode() == PPC::SELECT_VSSRC ||
8634 MI->getOpcode() == PPC::SELECT_VSRC) {
8635 // The incoming instruction knows the destination vreg to set, the
8636 // condition code register to branch on, the true/false values to
8637 // select between, and a branch opcode to use.
8642 // cmpTY ccX, r1, r2
8644 // fallthrough --> copy0MBB
8645 MachineBasicBlock *thisMBB = BB;
8646 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8647 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8648 DebugLoc dl = MI->getDebugLoc();
8649 F->insert(It, copy0MBB);
8650 F->insert(It, sinkMBB);
8652 // Transfer the remainder of BB and its successor edges to sinkMBB.
8653 sinkMBB->splice(sinkMBB->begin(), BB,
8654 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8655 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8657 // Next, add the true and fallthrough blocks as its successors.
8658 BB->addSuccessor(copy0MBB);
8659 BB->addSuccessor(sinkMBB);
8661 if (MI->getOpcode() == PPC::SELECT_I4 ||
8662 MI->getOpcode() == PPC::SELECT_I8 ||
8663 MI->getOpcode() == PPC::SELECT_F4 ||
8664 MI->getOpcode() == PPC::SELECT_F8 ||
8665 MI->getOpcode() == PPC::SELECT_QFRC ||
8666 MI->getOpcode() == PPC::SELECT_QSRC ||
8667 MI->getOpcode() == PPC::SELECT_QBRC ||
8668 MI->getOpcode() == PPC::SELECT_VRRC ||
8669 MI->getOpcode() == PPC::SELECT_VSFRC ||
8670 MI->getOpcode() == PPC::SELECT_VSSRC ||
8671 MI->getOpcode() == PPC::SELECT_VSRC) {
8672 BuildMI(BB, dl, TII->get(PPC::BC))
8673 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8675 unsigned SelectPred = MI->getOperand(4).getImm();
8676 BuildMI(BB, dl, TII->get(PPC::BCC))
8677 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8681 // %FalseValue = ...
8682 // # fallthrough to sinkMBB
8685 // Update machine-CFG edges
8686 BB->addSuccessor(sinkMBB);
8689 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8692 BuildMI(*BB, BB->begin(), dl,
8693 TII->get(PPC::PHI), MI->getOperand(0).getReg())
8694 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
8695 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8696 } else if (MI->getOpcode() == PPC::ReadTB) {
8697 // To read the 64-bit time-base register on a 32-bit target, we read the
8698 // two halves. Should the counter have wrapped while it was being read, we
8699 // need to try again.
8702 // mfspr Rx,TBU # load from TBU
8703 // mfspr Ry,TB # load from TB
8704 // mfspr Rz,TBU # load from TBU
8705 // cmpw crX,Rx,Rz # check if 'old'='new'
8706 // bne readLoop # branch if they're not equal
8709 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
8710 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8711 DebugLoc dl = MI->getDebugLoc();
8712 F->insert(It, readMBB);
8713 F->insert(It, sinkMBB);
8715 // Transfer the remainder of BB and its successor edges to sinkMBB.
8716 sinkMBB->splice(sinkMBB->begin(), BB,
8717 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8718 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8720 BB->addSuccessor(readMBB);
8723 MachineRegisterInfo &RegInfo = F->getRegInfo();
8724 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
8725 unsigned LoReg = MI->getOperand(0).getReg();
8726 unsigned HiReg = MI->getOperand(1).getReg();
8728 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
8729 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
8730 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
8732 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
8734 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
8735 .addReg(HiReg).addReg(ReadAgainReg);
8736 BuildMI(BB, dl, TII->get(PPC::BCC))
8737 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
8739 BB->addSuccessor(readMBB);
8740 BB->addSuccessor(sinkMBB);
8742 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
8743 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
8744 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
8745 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
8746 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
8747 BB = EmitAtomicBinary(MI, BB, 4, PPC::ADD4);
8748 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
8749 BB = EmitAtomicBinary(MI, BB, 8, PPC::ADD8);
8751 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
8752 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
8753 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
8754 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
8755 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
8756 BB = EmitAtomicBinary(MI, BB, 4, PPC::AND);
8757 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
8758 BB = EmitAtomicBinary(MI, BB, 8, PPC::AND8);
8760 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
8761 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
8762 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
8763 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
8764 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
8765 BB = EmitAtomicBinary(MI, BB, 4, PPC::OR);
8766 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
8767 BB = EmitAtomicBinary(MI, BB, 8, PPC::OR8);
8769 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
8770 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
8771 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
8772 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
8773 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
8774 BB = EmitAtomicBinary(MI, BB, 4, PPC::XOR);
8775 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
8776 BB = EmitAtomicBinary(MI, BB, 8, PPC::XOR8);
8778 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
8779 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
8780 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
8781 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
8782 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
8783 BB = EmitAtomicBinary(MI, BB, 4, PPC::NAND);
8784 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
8785 BB = EmitAtomicBinary(MI, BB, 8, PPC::NAND8);
8787 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
8788 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
8789 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
8790 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
8791 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
8792 BB = EmitAtomicBinary(MI, BB, 4, PPC::SUBF);
8793 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
8794 BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8);
8796 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
8797 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
8798 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
8799 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
8800 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
8801 BB = EmitAtomicBinary(MI, BB, 4, 0);
8802 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
8803 BB = EmitAtomicBinary(MI, BB, 8, 0);
8805 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
8806 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 ||
8807 (Subtarget.hasPartwordAtomics() &&
8808 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) ||
8809 (Subtarget.hasPartwordAtomics() &&
8810 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) {
8811 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
8813 auto LoadMnemonic = PPC::LDARX;
8814 auto StoreMnemonic = PPC::STDCX;
8815 switch(MI->getOpcode()) {
8817 llvm_unreachable("Compare and swap of unknown size");
8818 case PPC::ATOMIC_CMP_SWAP_I8:
8819 LoadMnemonic = PPC::LBARX;
8820 StoreMnemonic = PPC::STBCX;
8821 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8823 case PPC::ATOMIC_CMP_SWAP_I16:
8824 LoadMnemonic = PPC::LHARX;
8825 StoreMnemonic = PPC::STHCX;
8826 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8828 case PPC::ATOMIC_CMP_SWAP_I32:
8829 LoadMnemonic = PPC::LWARX;
8830 StoreMnemonic = PPC::STWCX;
8832 case PPC::ATOMIC_CMP_SWAP_I64:
8833 LoadMnemonic = PPC::LDARX;
8834 StoreMnemonic = PPC::STDCX;
8837 unsigned dest = MI->getOperand(0).getReg();
8838 unsigned ptrA = MI->getOperand(1).getReg();
8839 unsigned ptrB = MI->getOperand(2).getReg();
8840 unsigned oldval = MI->getOperand(3).getReg();
8841 unsigned newval = MI->getOperand(4).getReg();
8842 DebugLoc dl = MI->getDebugLoc();
8844 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8845 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8846 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8847 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8848 F->insert(It, loop1MBB);
8849 F->insert(It, loop2MBB);
8850 F->insert(It, midMBB);
8851 F->insert(It, exitMBB);
8852 exitMBB->splice(exitMBB->begin(), BB,
8853 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8854 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8858 // fallthrough --> loopMBB
8859 BB->addSuccessor(loop1MBB);
8862 // l[bhwd]arx dest, ptr
8863 // cmp[wd] dest, oldval
8866 // st[bhwd]cx. newval, ptr
8870 // st[bhwd]cx. dest, ptr
8873 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8874 .addReg(ptrA).addReg(ptrB);
8875 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
8876 .addReg(oldval).addReg(dest);
8877 BuildMI(BB, dl, TII->get(PPC::BCC))
8878 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
8879 BB->addSuccessor(loop2MBB);
8880 BB->addSuccessor(midMBB);
8883 BuildMI(BB, dl, TII->get(StoreMnemonic))
8884 .addReg(newval).addReg(ptrA).addReg(ptrB);
8885 BuildMI(BB, dl, TII->get(PPC::BCC))
8886 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
8887 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
8888 BB->addSuccessor(loop1MBB);
8889 BB->addSuccessor(exitMBB);
8892 BuildMI(BB, dl, TII->get(StoreMnemonic))
8893 .addReg(dest).addReg(ptrA).addReg(ptrB);
8894 BB->addSuccessor(exitMBB);
8899 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
8900 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
8901 // We must use 64-bit registers for addresses when targeting 64-bit,
8902 // since we're actually doing arithmetic on them. Other registers
8904 bool is64bit = Subtarget.isPPC64();
8905 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
8907 unsigned dest = MI->getOperand(0).getReg();
8908 unsigned ptrA = MI->getOperand(1).getReg();
8909 unsigned ptrB = MI->getOperand(2).getReg();
8910 unsigned oldval = MI->getOperand(3).getReg();
8911 unsigned newval = MI->getOperand(4).getReg();
8912 DebugLoc dl = MI->getDebugLoc();
8914 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8915 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8916 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8917 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8918 F->insert(It, loop1MBB);
8919 F->insert(It, loop2MBB);
8920 F->insert(It, midMBB);
8921 F->insert(It, exitMBB);
8922 exitMBB->splice(exitMBB->begin(), BB,
8923 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8924 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8926 MachineRegisterInfo &RegInfo = F->getRegInfo();
8927 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8928 : &PPC::GPRCRegClass;
8929 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8930 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8931 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8932 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
8933 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
8934 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
8935 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
8936 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8937 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8938 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8939 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8940 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8941 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8943 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
8944 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8947 // fallthrough --> loopMBB
8948 BB->addSuccessor(loop1MBB);
8950 // The 4-byte load must be aligned, while a char or short may be
8951 // anywhere in the word. Hence all this nasty bookkeeping code.
8952 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8953 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8954 // xori shift, shift1, 24 [16]
8955 // rlwinm ptr, ptr1, 0, 0, 29
8956 // slw newval2, newval, shift
8957 // slw oldval2, oldval,shift
8958 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8959 // slw mask, mask2, shift
8960 // and newval3, newval2, mask
8961 // and oldval3, oldval2, mask
8963 // lwarx tmpDest, ptr
8964 // and tmp, tmpDest, mask
8965 // cmpw tmp, oldval3
8968 // andc tmp2, tmpDest, mask
8969 // or tmp4, tmp2, newval3
8974 // stwcx. tmpDest, ptr
8976 // srw dest, tmpDest, shift
8977 if (ptrA != ZeroReg) {
8978 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8979 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8980 .addReg(ptrA).addReg(ptrB);
8984 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8985 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8986 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8987 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8989 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8990 .addReg(Ptr1Reg).addImm(0).addImm(61);
8992 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8993 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8994 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
8995 .addReg(newval).addReg(ShiftReg);
8996 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
8997 .addReg(oldval).addReg(ShiftReg);
8999 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
9001 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
9002 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
9003 .addReg(Mask3Reg).addImm(65535);
9005 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
9006 .addReg(Mask2Reg).addReg(ShiftReg);
9007 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
9008 .addReg(NewVal2Reg).addReg(MaskReg);
9009 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
9010 .addReg(OldVal2Reg).addReg(MaskReg);
9013 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
9014 .addReg(ZeroReg).addReg(PtrReg);
9015 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
9016 .addReg(TmpDestReg).addReg(MaskReg);
9017 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
9018 .addReg(TmpReg).addReg(OldVal3Reg);
9019 BuildMI(BB, dl, TII->get(PPC::BCC))
9020 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
9021 BB->addSuccessor(loop2MBB);
9022 BB->addSuccessor(midMBB);
9025 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
9026 .addReg(TmpDestReg).addReg(MaskReg);
9027 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
9028 .addReg(Tmp2Reg).addReg(NewVal3Reg);
9029 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
9030 .addReg(ZeroReg).addReg(PtrReg);
9031 BuildMI(BB, dl, TII->get(PPC::BCC))
9032 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
9033 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
9034 BB->addSuccessor(loop1MBB);
9035 BB->addSuccessor(exitMBB);
9038 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
9039 .addReg(ZeroReg).addReg(PtrReg);
9040 BB->addSuccessor(exitMBB);
9045 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
9047 } else if (MI->getOpcode() == PPC::FADDrtz) {
9048 // This pseudo performs an FADD with rounding mode temporarily forced
9049 // to round-to-zero. We emit this via custom inserter since the FPSCR
9050 // is not modeled at the SelectionDAG level.
9051 unsigned Dest = MI->getOperand(0).getReg();
9052 unsigned Src1 = MI->getOperand(1).getReg();
9053 unsigned Src2 = MI->getOperand(2).getReg();
9054 DebugLoc dl = MI->getDebugLoc();
9056 MachineRegisterInfo &RegInfo = F->getRegInfo();
9057 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
9059 // Save FPSCR value.
9060 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
9062 // Set rounding mode to round-to-zero.
9063 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
9064 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
9066 // Perform addition.
9067 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
9069 // Restore FPSCR value.
9070 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
9071 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9072 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
9073 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9074 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
9075 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9076 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
9077 PPC::ANDIo8 : PPC::ANDIo;
9078 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9079 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
9081 MachineRegisterInfo &RegInfo = F->getRegInfo();
9082 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
9083 &PPC::GPRCRegClass :
9084 &PPC::G8RCRegClass);
9086 DebugLoc dl = MI->getDebugLoc();
9087 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
9088 .addReg(MI->getOperand(1).getReg()).addImm(1);
9089 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
9090 MI->getOperand(0).getReg())
9091 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
9092 } else if (MI->getOpcode() == PPC::TCHECK_RET) {
9093 DebugLoc Dl = MI->getDebugLoc();
9094 MachineRegisterInfo &RegInfo = F->getRegInfo();
9095 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
9096 BuildMI(*BB, MI, Dl, TII->get(PPC::TCHECK), CRReg);
9099 llvm_unreachable("Unexpected instr type to insert");
9102 MI->eraseFromParent(); // The pseudo instruction is gone now.
9106 //===----------------------------------------------------------------------===//
9107 // Target Optimization Hooks
9108 //===----------------------------------------------------------------------===//
9110 static std::string getRecipOp(const char *Base, EVT VT) {
9111 std::string RecipOp(Base);
9112 if (VT.getScalarType() == MVT::f64)
9118 RecipOp = "vec-" + RecipOp;
9123 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
9124 DAGCombinerInfo &DCI,
9125 unsigned &RefinementSteps,
9126 bool &UseOneConstNR) const {
9127 EVT VT = Operand.getValueType();
9128 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
9129 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
9130 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9131 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9132 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9133 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9134 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
9135 std::string RecipOp = getRecipOp("sqrt", VT);
9136 if (!Recips.isEnabled(RecipOp))
9139 RefinementSteps = Recips.getRefinementSteps(RecipOp);
9140 UseOneConstNR = true;
9141 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
9146 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
9147 DAGCombinerInfo &DCI,
9148 unsigned &RefinementSteps) const {
9149 EVT VT = Operand.getValueType();
9150 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
9151 (VT == MVT::f64 && Subtarget.hasFRE()) ||
9152 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9153 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9154 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9155 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9156 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
9157 std::string RecipOp = getRecipOp("div", VT);
9158 if (!Recips.isEnabled(RecipOp))
9161 RefinementSteps = Recips.getRefinementSteps(RecipOp);
9162 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
9167 unsigned PPCTargetLowering::combineRepeatedFPDivisors() const {
9168 // Note: This functionality is used only when unsafe-fp-math is enabled, and
9169 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
9170 // enabled for division), this functionality is redundant with the default
9171 // combiner logic (once the division -> reciprocal/multiply transformation
9172 // has taken place). As a result, this matters more for older cores than for
9175 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9176 // reciprocal if there are two or more FDIVs (for embedded cores with only
9177 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
9178 switch (Subtarget.getDarwinDirective()) {
9183 case PPC::DIR_E500mc:
9184 case PPC::DIR_E5500:
9189 // isConsecutiveLSLoc needs to work even if all adds have not yet been
9190 // collapsed, and so we need to look through chains of them.
9191 static void getBaseWithConstantOffset(SDValue Loc, SDValue &Base,
9192 int64_t& Offset, SelectionDAG &DAG) {
9193 if (DAG.isBaseWithConstantOffset(Loc)) {
9194 Base = Loc.getOperand(0);
9195 Offset += cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue();
9197 // The base might itself be a base plus an offset, and if so, accumulate
9199 getBaseWithConstantOffset(Loc.getOperand(0), Base, Offset, DAG);
9203 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
9204 unsigned Bytes, int Dist,
9205 SelectionDAG &DAG) {
9206 if (VT.getSizeInBits() / 8 != Bytes)
9209 SDValue BaseLoc = Base->getBasePtr();
9210 if (Loc.getOpcode() == ISD::FrameIndex) {
9211 if (BaseLoc.getOpcode() != ISD::FrameIndex)
9213 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9214 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
9215 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
9216 int FS = MFI->getObjectSize(FI);
9217 int BFS = MFI->getObjectSize(BFI);
9218 if (FS != BFS || FS != (int)Bytes) return false;
9219 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
9222 SDValue Base1 = Loc, Base2 = BaseLoc;
9223 int64_t Offset1 = 0, Offset2 = 0;
9224 getBaseWithConstantOffset(Loc, Base1, Offset1, DAG);
9225 getBaseWithConstantOffset(BaseLoc, Base2, Offset2, DAG);
9226 if (Base1 == Base2 && Offset1 == (Offset2 + Dist * Bytes))
9229 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9230 const GlobalValue *GV1 = nullptr;
9231 const GlobalValue *GV2 = nullptr;
9234 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
9235 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
9236 if (isGA1 && isGA2 && GV1 == GV2)
9237 return Offset1 == (Offset2 + Dist*Bytes);
9241 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
9242 // not enforce equality of the chain operands.
9243 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
9244 unsigned Bytes, int Dist,
9245 SelectionDAG &DAG) {
9246 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
9247 EVT VT = LS->getMemoryVT();
9248 SDValue Loc = LS->getBasePtr();
9249 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
9252 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
9254 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9255 default: return false;
9256 case Intrinsic::ppc_qpx_qvlfd:
9257 case Intrinsic::ppc_qpx_qvlfda:
9260 case Intrinsic::ppc_qpx_qvlfs:
9261 case Intrinsic::ppc_qpx_qvlfsa:
9264 case Intrinsic::ppc_qpx_qvlfcd:
9265 case Intrinsic::ppc_qpx_qvlfcda:
9268 case Intrinsic::ppc_qpx_qvlfcs:
9269 case Intrinsic::ppc_qpx_qvlfcsa:
9272 case Intrinsic::ppc_qpx_qvlfiwa:
9273 case Intrinsic::ppc_qpx_qvlfiwz:
9274 case Intrinsic::ppc_altivec_lvx:
9275 case Intrinsic::ppc_altivec_lvxl:
9276 case Intrinsic::ppc_vsx_lxvw4x:
9279 case Intrinsic::ppc_vsx_lxvd2x:
9282 case Intrinsic::ppc_altivec_lvebx:
9285 case Intrinsic::ppc_altivec_lvehx:
9288 case Intrinsic::ppc_altivec_lvewx:
9293 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
9296 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
9298 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9299 default: return false;
9300 case Intrinsic::ppc_qpx_qvstfd:
9301 case Intrinsic::ppc_qpx_qvstfda:
9304 case Intrinsic::ppc_qpx_qvstfs:
9305 case Intrinsic::ppc_qpx_qvstfsa:
9308 case Intrinsic::ppc_qpx_qvstfcd:
9309 case Intrinsic::ppc_qpx_qvstfcda:
9312 case Intrinsic::ppc_qpx_qvstfcs:
9313 case Intrinsic::ppc_qpx_qvstfcsa:
9316 case Intrinsic::ppc_qpx_qvstfiw:
9317 case Intrinsic::ppc_qpx_qvstfiwa:
9318 case Intrinsic::ppc_altivec_stvx:
9319 case Intrinsic::ppc_altivec_stvxl:
9320 case Intrinsic::ppc_vsx_stxvw4x:
9323 case Intrinsic::ppc_vsx_stxvd2x:
9326 case Intrinsic::ppc_altivec_stvebx:
9329 case Intrinsic::ppc_altivec_stvehx:
9332 case Intrinsic::ppc_altivec_stvewx:
9337 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
9343 // Return true is there is a nearyby consecutive load to the one provided
9344 // (regardless of alignment). We search up and down the chain, looking though
9345 // token factors and other loads (but nothing else). As a result, a true result
9346 // indicates that it is safe to create a new consecutive load adjacent to the
9348 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
9349 SDValue Chain = LD->getChain();
9350 EVT VT = LD->getMemoryVT();
9352 SmallSet<SDNode *, 16> LoadRoots;
9353 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
9354 SmallSet<SDNode *, 16> Visited;
9356 // First, search up the chain, branching to follow all token-factor operands.
9357 // If we find a consecutive load, then we're done, otherwise, record all
9358 // nodes just above the top-level loads and token factors.
9359 while (!Queue.empty()) {
9360 SDNode *ChainNext = Queue.pop_back_val();
9361 if (!Visited.insert(ChainNext).second)
9364 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
9365 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9368 if (!Visited.count(ChainLD->getChain().getNode()))
9369 Queue.push_back(ChainLD->getChain().getNode());
9370 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
9371 for (const SDUse &O : ChainNext->ops())
9372 if (!Visited.count(O.getNode()))
9373 Queue.push_back(O.getNode());
9375 LoadRoots.insert(ChainNext);
9378 // Second, search down the chain, starting from the top-level nodes recorded
9379 // in the first phase. These top-level nodes are the nodes just above all
9380 // loads and token factors. Starting with their uses, recursively look though
9381 // all loads (just the chain uses) and token factors to find a consecutive
9386 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
9387 IE = LoadRoots.end(); I != IE; ++I) {
9388 Queue.push_back(*I);
9390 while (!Queue.empty()) {
9391 SDNode *LoadRoot = Queue.pop_back_val();
9392 if (!Visited.insert(LoadRoot).second)
9395 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
9396 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9399 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
9400 UE = LoadRoot->use_end(); UI != UE; ++UI)
9401 if (((isa<MemSDNode>(*UI) &&
9402 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
9403 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
9404 Queue.push_back(*UI);
9411 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
9412 DAGCombinerInfo &DCI) const {
9413 SelectionDAG &DAG = DCI.DAG;
9416 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits");
9417 // If we're tracking CR bits, we need to be careful that we don't have:
9418 // trunc(binary-ops(zext(x), zext(y)))
9420 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
9421 // such that we're unnecessarily moving things into GPRs when it would be
9422 // better to keep them in CR bits.
9424 // Note that trunc here can be an actual i1 trunc, or can be the effective
9425 // truncation that comes from a setcc or select_cc.
9426 if (N->getOpcode() == ISD::TRUNCATE &&
9427 N->getValueType(0) != MVT::i1)
9430 if (N->getOperand(0).getValueType() != MVT::i32 &&
9431 N->getOperand(0).getValueType() != MVT::i64)
9434 if (N->getOpcode() == ISD::SETCC ||
9435 N->getOpcode() == ISD::SELECT_CC) {
9436 // If we're looking at a comparison, then we need to make sure that the
9437 // high bits (all except for the first) don't matter the result.
9439 cast<CondCodeSDNode>(N->getOperand(
9440 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
9441 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
9443 if (ISD::isSignedIntSetCC(CC)) {
9444 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
9445 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
9447 } else if (ISD::isUnsignedIntSetCC(CC)) {
9448 if (!DAG.MaskedValueIsZero(N->getOperand(0),
9449 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
9450 !DAG.MaskedValueIsZero(N->getOperand(1),
9451 APInt::getHighBitsSet(OpBits, OpBits-1)))
9454 // This is neither a signed nor an unsigned comparison, just make sure
9455 // that the high bits are equal.
9456 APInt Op1Zero, Op1One;
9457 APInt Op2Zero, Op2One;
9458 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
9459 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
9461 // We don't really care about what is known about the first bit (if
9462 // anything), so clear it in all masks prior to comparing them.
9463 Op1Zero.clearBit(0); Op1One.clearBit(0);
9464 Op2Zero.clearBit(0); Op2One.clearBit(0);
9466 if (Op1Zero != Op2Zero || Op1One != Op2One)
9471 // We now know that the higher-order bits are irrelevant, we just need to
9472 // make sure that all of the intermediate operations are bit operations, and
9473 // all inputs are extensions.
9474 if (N->getOperand(0).getOpcode() != ISD::AND &&
9475 N->getOperand(0).getOpcode() != ISD::OR &&
9476 N->getOperand(0).getOpcode() != ISD::XOR &&
9477 N->getOperand(0).getOpcode() != ISD::SELECT &&
9478 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
9479 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
9480 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
9481 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
9482 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
9485 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
9486 N->getOperand(1).getOpcode() != ISD::AND &&
9487 N->getOperand(1).getOpcode() != ISD::OR &&
9488 N->getOperand(1).getOpcode() != ISD::XOR &&
9489 N->getOperand(1).getOpcode() != ISD::SELECT &&
9490 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
9491 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
9492 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
9493 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
9494 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
9497 SmallVector<SDValue, 4> Inputs;
9498 SmallVector<SDValue, 8> BinOps, PromOps;
9499 SmallPtrSet<SDNode *, 16> Visited;
9501 for (unsigned i = 0; i < 2; ++i) {
9502 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9503 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9504 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9505 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9506 isa<ConstantSDNode>(N->getOperand(i)))
9507 Inputs.push_back(N->getOperand(i));
9509 BinOps.push_back(N->getOperand(i));
9511 if (N->getOpcode() == ISD::TRUNCATE)
9515 // Visit all inputs, collect all binary operations (and, or, xor and
9516 // select) that are all fed by extensions.
9517 while (!BinOps.empty()) {
9518 SDValue BinOp = BinOps.back();
9521 if (!Visited.insert(BinOp.getNode()).second)
9524 PromOps.push_back(BinOp);
9526 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9527 // The condition of the select is not promoted.
9528 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9530 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9533 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9534 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9535 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9536 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9537 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9538 Inputs.push_back(BinOp.getOperand(i));
9539 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9540 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9541 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9542 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9543 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
9544 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9545 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9546 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9547 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
9548 BinOps.push_back(BinOp.getOperand(i));
9550 // We have an input that is not an extension or another binary
9551 // operation; we'll abort this transformation.
9557 // Make sure that this is a self-contained cluster of operations (which
9558 // is not quite the same thing as saying that everything has only one
9560 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9561 if (isa<ConstantSDNode>(Inputs[i]))
9564 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9565 UE = Inputs[i].getNode()->use_end();
9568 if (User != N && !Visited.count(User))
9571 // Make sure that we're not going to promote the non-output-value
9572 // operand(s) or SELECT or SELECT_CC.
9573 // FIXME: Although we could sometimes handle this, and it does occur in
9574 // practice that one of the condition inputs to the select is also one of
9575 // the outputs, we currently can't deal with this.
9576 if (User->getOpcode() == ISD::SELECT) {
9577 if (User->getOperand(0) == Inputs[i])
9579 } else if (User->getOpcode() == ISD::SELECT_CC) {
9580 if (User->getOperand(0) == Inputs[i] ||
9581 User->getOperand(1) == Inputs[i])
9587 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9588 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9589 UE = PromOps[i].getNode()->use_end();
9592 if (User != N && !Visited.count(User))
9595 // Make sure that we're not going to promote the non-output-value
9596 // operand(s) or SELECT or SELECT_CC.
9597 // FIXME: Although we could sometimes handle this, and it does occur in
9598 // practice that one of the condition inputs to the select is also one of
9599 // the outputs, we currently can't deal with this.
9600 if (User->getOpcode() == ISD::SELECT) {
9601 if (User->getOperand(0) == PromOps[i])
9603 } else if (User->getOpcode() == ISD::SELECT_CC) {
9604 if (User->getOperand(0) == PromOps[i] ||
9605 User->getOperand(1) == PromOps[i])
9611 // Replace all inputs with the extension operand.
9612 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9613 // Constants may have users outside the cluster of to-be-promoted nodes,
9614 // and so we need to replace those as we do the promotions.
9615 if (isa<ConstantSDNode>(Inputs[i]))
9618 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
9621 // Replace all operations (these are all the same, but have a different
9622 // (i1) return type). DAG.getNode will validate that the types of
9623 // a binary operator match, so go through the list in reverse so that
9624 // we've likely promoted both operands first. Any intermediate truncations or
9625 // extensions disappear.
9626 while (!PromOps.empty()) {
9627 SDValue PromOp = PromOps.back();
9630 if (PromOp.getOpcode() == ISD::TRUNCATE ||
9631 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
9632 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
9633 PromOp.getOpcode() == ISD::ANY_EXTEND) {
9634 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
9635 PromOp.getOperand(0).getValueType() != MVT::i1) {
9636 // The operand is not yet ready (see comment below).
9637 PromOps.insert(PromOps.begin(), PromOp);
9641 SDValue RepValue = PromOp.getOperand(0);
9642 if (isa<ConstantSDNode>(RepValue))
9643 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
9645 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
9650 switch (PromOp.getOpcode()) {
9651 default: C = 0; break;
9652 case ISD::SELECT: C = 1; break;
9653 case ISD::SELECT_CC: C = 2; break;
9656 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9657 PromOp.getOperand(C).getValueType() != MVT::i1) ||
9658 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9659 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
9660 // The to-be-promoted operands of this node have not yet been
9661 // promoted (this should be rare because we're going through the
9662 // list backward, but if one of the operands has several users in
9663 // this cluster of to-be-promoted nodes, it is possible).
9664 PromOps.insert(PromOps.begin(), PromOp);
9668 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9669 PromOp.getNode()->op_end());
9671 // If there are any constant inputs, make sure they're replaced now.
9672 for (unsigned i = 0; i < 2; ++i)
9673 if (isa<ConstantSDNode>(Ops[C+i]))
9674 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
9676 DAG.ReplaceAllUsesOfValueWith(PromOp,
9677 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
9680 // Now we're left with the initial truncation itself.
9681 if (N->getOpcode() == ISD::TRUNCATE)
9682 return N->getOperand(0);
9684 // Otherwise, this is a comparison. The operands to be compared have just
9685 // changed type (to i1), but everything else is the same.
9686 return SDValue(N, 0);
9689 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
9690 DAGCombinerInfo &DCI) const {
9691 SelectionDAG &DAG = DCI.DAG;
9694 // If we're tracking CR bits, we need to be careful that we don't have:
9695 // zext(binary-ops(trunc(x), trunc(y)))
9697 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
9698 // such that we're unnecessarily moving things into CR bits that can more
9699 // efficiently stay in GPRs. Note that if we're not certain that the high
9700 // bits are set as required by the final extension, we still may need to do
9701 // some masking to get the proper behavior.
9703 // This same functionality is important on PPC64 when dealing with
9704 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
9705 // the return values of functions. Because it is so similar, it is handled
9708 if (N->getValueType(0) != MVT::i32 &&
9709 N->getValueType(0) != MVT::i64)
9712 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
9713 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
9716 if (N->getOperand(0).getOpcode() != ISD::AND &&
9717 N->getOperand(0).getOpcode() != ISD::OR &&
9718 N->getOperand(0).getOpcode() != ISD::XOR &&
9719 N->getOperand(0).getOpcode() != ISD::SELECT &&
9720 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
9723 SmallVector<SDValue, 4> Inputs;
9724 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
9725 SmallPtrSet<SDNode *, 16> Visited;
9727 // Visit all inputs, collect all binary operations (and, or, xor and
9728 // select) that are all fed by truncations.
9729 while (!BinOps.empty()) {
9730 SDValue BinOp = BinOps.back();
9733 if (!Visited.insert(BinOp.getNode()).second)
9736 PromOps.push_back(BinOp);
9738 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9739 // The condition of the select is not promoted.
9740 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9742 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9745 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9746 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9747 Inputs.push_back(BinOp.getOperand(i));
9748 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9749 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9750 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9751 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9752 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
9753 BinOps.push_back(BinOp.getOperand(i));
9755 // We have an input that is not a truncation or another binary
9756 // operation; we'll abort this transformation.
9762 // The operands of a select that must be truncated when the select is
9763 // promoted because the operand is actually part of the to-be-promoted set.
9764 DenseMap<SDNode *, EVT> SelectTruncOp[2];
9766 // Make sure that this is a self-contained cluster of operations (which
9767 // is not quite the same thing as saying that everything has only one
9769 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9770 if (isa<ConstantSDNode>(Inputs[i]))
9773 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9774 UE = Inputs[i].getNode()->use_end();
9777 if (User != N && !Visited.count(User))
9780 // If we're going to promote the non-output-value operand(s) or SELECT or
9781 // SELECT_CC, record them for truncation.
9782 if (User->getOpcode() == ISD::SELECT) {
9783 if (User->getOperand(0) == Inputs[i])
9784 SelectTruncOp[0].insert(std::make_pair(User,
9785 User->getOperand(0).getValueType()));
9786 } else if (User->getOpcode() == ISD::SELECT_CC) {
9787 if (User->getOperand(0) == Inputs[i])
9788 SelectTruncOp[0].insert(std::make_pair(User,
9789 User->getOperand(0).getValueType()));
9790 if (User->getOperand(1) == Inputs[i])
9791 SelectTruncOp[1].insert(std::make_pair(User,
9792 User->getOperand(1).getValueType()));
9797 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9798 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9799 UE = PromOps[i].getNode()->use_end();
9802 if (User != N && !Visited.count(User))
9805 // If we're going to promote the non-output-value operand(s) or SELECT or
9806 // SELECT_CC, record them for truncation.
9807 if (User->getOpcode() == ISD::SELECT) {
9808 if (User->getOperand(0) == PromOps[i])
9809 SelectTruncOp[0].insert(std::make_pair(User,
9810 User->getOperand(0).getValueType()));
9811 } else if (User->getOpcode() == ISD::SELECT_CC) {
9812 if (User->getOperand(0) == PromOps[i])
9813 SelectTruncOp[0].insert(std::make_pair(User,
9814 User->getOperand(0).getValueType()));
9815 if (User->getOperand(1) == PromOps[i])
9816 SelectTruncOp[1].insert(std::make_pair(User,
9817 User->getOperand(1).getValueType()));
9822 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
9823 bool ReallyNeedsExt = false;
9824 if (N->getOpcode() != ISD::ANY_EXTEND) {
9825 // If all of the inputs are not already sign/zero extended, then
9826 // we'll still need to do that at the end.
9827 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9828 if (isa<ConstantSDNode>(Inputs[i]))
9832 Inputs[i].getOperand(0).getValueSizeInBits();
9833 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
9835 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
9836 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
9837 APInt::getHighBitsSet(OpBits,
9838 OpBits-PromBits))) ||
9839 (N->getOpcode() == ISD::SIGN_EXTEND &&
9840 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
9841 (OpBits-(PromBits-1)))) {
9842 ReallyNeedsExt = true;
9848 // Replace all inputs, either with the truncation operand, or a
9849 // truncation or extension to the final output type.
9850 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9851 // Constant inputs need to be replaced with the to-be-promoted nodes that
9852 // use them because they might have users outside of the cluster of
9854 if (isa<ConstantSDNode>(Inputs[i]))
9857 SDValue InSrc = Inputs[i].getOperand(0);
9858 if (Inputs[i].getValueType() == N->getValueType(0))
9859 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
9860 else if (N->getOpcode() == ISD::SIGN_EXTEND)
9861 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9862 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
9863 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9864 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9865 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
9867 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9868 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
9871 // Replace all operations (these are all the same, but have a different
9872 // (promoted) return type). DAG.getNode will validate that the types of
9873 // a binary operator match, so go through the list in reverse so that
9874 // we've likely promoted both operands first.
9875 while (!PromOps.empty()) {
9876 SDValue PromOp = PromOps.back();
9880 switch (PromOp.getOpcode()) {
9881 default: C = 0; break;
9882 case ISD::SELECT: C = 1; break;
9883 case ISD::SELECT_CC: C = 2; break;
9886 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9887 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
9888 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9889 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
9890 // The to-be-promoted operands of this node have not yet been
9891 // promoted (this should be rare because we're going through the
9892 // list backward, but if one of the operands has several users in
9893 // this cluster of to-be-promoted nodes, it is possible).
9894 PromOps.insert(PromOps.begin(), PromOp);
9898 // For SELECT and SELECT_CC nodes, we do a similar check for any
9899 // to-be-promoted comparison inputs.
9900 if (PromOp.getOpcode() == ISD::SELECT ||
9901 PromOp.getOpcode() == ISD::SELECT_CC) {
9902 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
9903 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
9904 (SelectTruncOp[1].count(PromOp.getNode()) &&
9905 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
9906 PromOps.insert(PromOps.begin(), PromOp);
9911 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9912 PromOp.getNode()->op_end());
9914 // If this node has constant inputs, then they'll need to be promoted here.
9915 for (unsigned i = 0; i < 2; ++i) {
9916 if (!isa<ConstantSDNode>(Ops[C+i]))
9918 if (Ops[C+i].getValueType() == N->getValueType(0))
9921 if (N->getOpcode() == ISD::SIGN_EXTEND)
9922 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9923 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9924 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9926 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9929 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
9930 // truncate them again to the original value type.
9931 if (PromOp.getOpcode() == ISD::SELECT ||
9932 PromOp.getOpcode() == ISD::SELECT_CC) {
9933 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
9934 if (SI0 != SelectTruncOp[0].end())
9935 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
9936 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
9937 if (SI1 != SelectTruncOp[1].end())
9938 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
9941 DAG.ReplaceAllUsesOfValueWith(PromOp,
9942 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
9945 // Now we're left with the initial extension itself.
9946 if (!ReallyNeedsExt)
9947 return N->getOperand(0);
9949 // To zero extend, just mask off everything except for the first bit (in the
9951 if (N->getOpcode() == ISD::ZERO_EXTEND)
9952 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
9953 DAG.getConstant(APInt::getLowBitsSet(
9954 N->getValueSizeInBits(0), PromBits),
9955 dl, N->getValueType(0)));
9957 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
9958 "Invalid extension type");
9959 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0), DAG.getDataLayout());
9961 DAG.getConstant(N->getValueSizeInBits(0) - PromBits, dl, ShiftAmountTy);
9963 ISD::SRA, dl, N->getValueType(0),
9964 DAG.getNode(ISD::SHL, dl, N->getValueType(0), N->getOperand(0), ShiftCst),
9968 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
9969 DAGCombinerInfo &DCI) const {
9970 assert((N->getOpcode() == ISD::SINT_TO_FP ||
9971 N->getOpcode() == ISD::UINT_TO_FP) &&
9972 "Need an int -> FP conversion node here");
9974 if (!Subtarget.has64BitSupport())
9977 SelectionDAG &DAG = DCI.DAG;
9981 // Don't handle ppc_fp128 here or i1 conversions.
9982 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
9984 if (Op.getOperand(0).getValueType() == MVT::i1)
9987 // For i32 intermediate values, unfortunately, the conversion functions
9988 // leave the upper 32 bits of the value are undefined. Within the set of
9989 // scalar instructions, we have no method for zero- or sign-extending the
9990 // value. Thus, we cannot handle i32 intermediate values here.
9991 if (Op.getOperand(0).getValueType() == MVT::i32)
9994 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
9995 "UINT_TO_FP is supported only with FPCVT");
9997 // If we have FCFIDS, then use it when converting to single-precision.
9998 // Otherwise, convert to double-precision and then round.
9999 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
10000 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
10002 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
10004 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
10008 // If we're converting from a float, to an int, and back to a float again,
10009 // then we don't need the store/load pair at all.
10010 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
10011 Subtarget.hasFPCVT()) ||
10012 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
10013 SDValue Src = Op.getOperand(0).getOperand(0);
10014 if (Src.getValueType() == MVT::f32) {
10015 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
10016 DCI.AddToWorklist(Src.getNode());
10017 } else if (Src.getValueType() != MVT::f64) {
10018 // Make sure that we don't pick up a ppc_fp128 source value.
10023 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
10026 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
10027 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
10029 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
10030 FP = DAG.getNode(ISD::FP_ROUND, dl,
10031 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
10032 DCI.AddToWorklist(FP.getNode());
10041 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
10042 // builtins) into loads with swaps.
10043 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
10044 DAGCombinerInfo &DCI) const {
10045 SelectionDAG &DAG = DCI.DAG;
10049 MachineMemOperand *MMO;
10051 switch (N->getOpcode()) {
10053 llvm_unreachable("Unexpected opcode for little endian VSX load");
10055 LoadSDNode *LD = cast<LoadSDNode>(N);
10056 Chain = LD->getChain();
10057 Base = LD->getBasePtr();
10058 MMO = LD->getMemOperand();
10059 // If the MMO suggests this isn't a load of a full vector, leave
10060 // things alone. For a built-in, we have to make the change for
10061 // correctness, so if there is a size problem that will be a bug.
10062 if (MMO->getSize() < 16)
10066 case ISD::INTRINSIC_W_CHAIN: {
10067 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
10068 Chain = Intrin->getChain();
10069 // Similarly to the store case below, Intrin->getBasePtr() doesn't get
10070 // us what we want. Get operand 2 instead.
10071 Base = Intrin->getOperand(2);
10072 MMO = Intrin->getMemOperand();
10077 MVT VecTy = N->getValueType(0).getSimpleVT();
10078 SDValue LoadOps[] = { Chain, Base };
10079 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
10080 DAG.getVTList(VecTy, MVT::Other),
10081 LoadOps, VecTy, MMO);
10082 DCI.AddToWorklist(Load.getNode());
10083 Chain = Load.getValue(1);
10084 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10085 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
10086 DCI.AddToWorklist(Swap.getNode());
10090 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
10091 // builtins) into stores with swaps.
10092 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
10093 DAGCombinerInfo &DCI) const {
10094 SelectionDAG &DAG = DCI.DAG;
10099 MachineMemOperand *MMO;
10101 switch (N->getOpcode()) {
10103 llvm_unreachable("Unexpected opcode for little endian VSX store");
10105 StoreSDNode *ST = cast<StoreSDNode>(N);
10106 Chain = ST->getChain();
10107 Base = ST->getBasePtr();
10108 MMO = ST->getMemOperand();
10110 // If the MMO suggests this isn't a store of a full vector, leave
10111 // things alone. For a built-in, we have to make the change for
10112 // correctness, so if there is a size problem that will be a bug.
10113 if (MMO->getSize() < 16)
10117 case ISD::INTRINSIC_VOID: {
10118 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
10119 Chain = Intrin->getChain();
10120 // Intrin->getBasePtr() oddly does not get what we want.
10121 Base = Intrin->getOperand(3);
10122 MMO = Intrin->getMemOperand();
10128 SDValue Src = N->getOperand(SrcOpnd);
10129 MVT VecTy = Src.getValueType().getSimpleVT();
10130 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10131 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
10132 DCI.AddToWorklist(Swap.getNode());
10133 Chain = Swap.getValue(1);
10134 SDValue StoreOps[] = { Chain, Swap, Base };
10135 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
10136 DAG.getVTList(MVT::Other),
10137 StoreOps, VecTy, MMO);
10138 DCI.AddToWorklist(Store.getNode());
10142 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
10143 DAGCombinerInfo &DCI) const {
10144 SelectionDAG &DAG = DCI.DAG;
10146 switch (N->getOpcode()) {
10149 if (isNullConstant(N->getOperand(0))) // 0 << V -> 0.
10150 return N->getOperand(0);
10153 if (isNullConstant(N->getOperand(0))) // 0 >>u V -> 0.
10154 return N->getOperand(0);
10157 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10158 if (C->isNullValue() || // 0 >>s V -> 0.
10159 C->isAllOnesValue()) // -1 >>s V -> -1.
10160 return N->getOperand(0);
10163 case ISD::SIGN_EXTEND:
10164 case ISD::ZERO_EXTEND:
10165 case ISD::ANY_EXTEND:
10166 return DAGCombineExtBoolTrunc(N, DCI);
10167 case ISD::TRUNCATE:
10169 case ISD::SELECT_CC:
10170 return DAGCombineTruncBoolExt(N, DCI);
10171 case ISD::SINT_TO_FP:
10172 case ISD::UINT_TO_FP:
10173 return combineFPToIntToFP(N, DCI);
10175 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
10176 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() &&
10177 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
10178 N->getOperand(1).getValueType() == MVT::i32 &&
10179 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
10180 SDValue Val = N->getOperand(1).getOperand(0);
10181 if (Val.getValueType() == MVT::f32) {
10182 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
10183 DCI.AddToWorklist(Val.getNode());
10185 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
10186 DCI.AddToWorklist(Val.getNode());
10189 N->getOperand(0), Val, N->getOperand(2),
10190 DAG.getValueType(N->getOperand(1).getValueType())
10193 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
10194 DAG.getVTList(MVT::Other), Ops,
10195 cast<StoreSDNode>(N)->getMemoryVT(),
10196 cast<StoreSDNode>(N)->getMemOperand());
10197 DCI.AddToWorklist(Val.getNode());
10201 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
10202 if (cast<StoreSDNode>(N)->isUnindexed() &&
10203 N->getOperand(1).getOpcode() == ISD::BSWAP &&
10204 N->getOperand(1).getNode()->hasOneUse() &&
10205 (N->getOperand(1).getValueType() == MVT::i32 ||
10206 N->getOperand(1).getValueType() == MVT::i16 ||
10207 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10208 N->getOperand(1).getValueType() == MVT::i64))) {
10209 SDValue BSwapOp = N->getOperand(1).getOperand(0);
10210 // Do an any-extend to 32-bits if this is a half-word input.
10211 if (BSwapOp.getValueType() == MVT::i16)
10212 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
10215 N->getOperand(0), BSwapOp, N->getOperand(2),
10216 DAG.getValueType(N->getOperand(1).getValueType())
10219 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
10220 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
10221 cast<StoreSDNode>(N)->getMemOperand());
10224 // For little endian, VSX stores require generating xxswapd/lxvd2x.
10225 EVT VT = N->getOperand(1).getValueType();
10226 if (VT.isSimple()) {
10227 MVT StoreVT = VT.getSimpleVT();
10228 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10229 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
10230 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
10231 return expandVSXStoreForLE(N, DCI);
10236 LoadSDNode *LD = cast<LoadSDNode>(N);
10237 EVT VT = LD->getValueType(0);
10239 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10240 if (VT.isSimple()) {
10241 MVT LoadVT = VT.getSimpleVT();
10242 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10243 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
10244 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
10245 return expandVSXLoadForLE(N, DCI);
10248 EVT MemVT = LD->getMemoryVT();
10249 Type *Ty = MemVT.getTypeForEVT(*DAG.getContext());
10250 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(Ty);
10251 Type *STy = MemVT.getScalarType().getTypeForEVT(*DAG.getContext());
10252 unsigned ScalarABIAlignment = DAG.getDataLayout().getABITypeAlignment(STy);
10253 if (LD->isUnindexed() && VT.isVector() &&
10254 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) &&
10255 // P8 and later hardware should just use LOAD.
10256 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 ||
10257 VT == MVT::v4i32 || VT == MVT::v4f32)) ||
10258 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) &&
10259 LD->getAlignment() >= ScalarABIAlignment)) &&
10260 LD->getAlignment() < ABIAlignment) {
10261 // This is a type-legal unaligned Altivec or QPX load.
10262 SDValue Chain = LD->getChain();
10263 SDValue Ptr = LD->getBasePtr();
10264 bool isLittleEndian = Subtarget.isLittleEndian();
10266 // This implements the loading of unaligned vectors as described in
10267 // the venerable Apple Velocity Engine overview. Specifically:
10268 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
10269 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
10271 // The general idea is to expand a sequence of one or more unaligned
10272 // loads into an alignment-based permutation-control instruction (lvsl
10273 // or lvsr), a series of regular vector loads (which always truncate
10274 // their input address to an aligned address), and a series of
10275 // permutations. The results of these permutations are the requested
10276 // loaded values. The trick is that the last "extra" load is not taken
10277 // from the address you might suspect (sizeof(vector) bytes after the
10278 // last requested load), but rather sizeof(vector) - 1 bytes after the
10279 // last requested vector. The point of this is to avoid a page fault if
10280 // the base address happened to be aligned. This works because if the
10281 // base address is aligned, then adding less than a full vector length
10282 // will cause the last vector in the sequence to be (re)loaded.
10283 // Otherwise, the next vector will be fetched as you might suspect was
10286 // We might be able to reuse the permutation generation from
10287 // a different base address offset from this one by an aligned amount.
10288 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
10289 // optimization later.
10290 Intrinsic::ID Intr, IntrLD, IntrPerm;
10291 MVT PermCntlTy, PermTy, LDTy;
10292 if (Subtarget.hasAltivec()) {
10293 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr :
10294 Intrinsic::ppc_altivec_lvsl;
10295 IntrLD = Intrinsic::ppc_altivec_lvx;
10296 IntrPerm = Intrinsic::ppc_altivec_vperm;
10297 PermCntlTy = MVT::v16i8;
10298 PermTy = MVT::v4i32;
10301 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld :
10302 Intrinsic::ppc_qpx_qvlpcls;
10303 IntrLD = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlfd :
10304 Intrinsic::ppc_qpx_qvlfs;
10305 IntrPerm = Intrinsic::ppc_qpx_qvfperm;
10306 PermCntlTy = MVT::v4f64;
10307 PermTy = MVT::v4f64;
10308 LDTy = MemVT.getSimpleVT();
10311 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, PermCntlTy);
10313 // Create the new MMO for the new base load. It is like the original MMO,
10314 // but represents an area in memory almost twice the vector size centered
10315 // on the original address. If the address is unaligned, we might start
10316 // reading up to (sizeof(vector)-1) bytes below the address of the
10317 // original unaligned load.
10318 MachineFunction &MF = DAG.getMachineFunction();
10319 MachineMemOperand *BaseMMO =
10320 MF.getMachineMemOperand(LD->getMemOperand(),
10321 -(long)MemVT.getStoreSize()+1,
10322 2*MemVT.getStoreSize()-1);
10324 // Create the new base load.
10326 DAG.getTargetConstant(IntrLD, dl, getPointerTy(MF.getDataLayout()));
10327 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
10329 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10330 DAG.getVTList(PermTy, MVT::Other),
10331 BaseLoadOps, LDTy, BaseMMO);
10333 // Note that the value of IncOffset (which is provided to the next
10334 // load's pointer info offset value, and thus used to calculate the
10335 // alignment), and the value of IncValue (which is actually used to
10336 // increment the pointer value) are different! This is because we
10337 // require the next load to appear to be aligned, even though it
10338 // is actually offset from the base pointer by a lesser amount.
10339 int IncOffset = VT.getSizeInBits() / 8;
10340 int IncValue = IncOffset;
10342 // Walk (both up and down) the chain looking for another load at the real
10343 // (aligned) offset (the alignment of the other load does not matter in
10344 // this case). If found, then do not use the offset reduction trick, as
10345 // that will prevent the loads from being later combined (as they would
10346 // otherwise be duplicates).
10347 if (!findConsecutiveLoad(LD, DAG))
10350 SDValue Increment =
10351 DAG.getConstant(IncValue, dl, getPointerTy(MF.getDataLayout()));
10352 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
10354 MachineMemOperand *ExtraMMO =
10355 MF.getMachineMemOperand(LD->getMemOperand(),
10356 1, 2*MemVT.getStoreSize()-1);
10357 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
10358 SDValue ExtraLoad =
10359 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10360 DAG.getVTList(PermTy, MVT::Other),
10361 ExtraLoadOps, LDTy, ExtraMMO);
10363 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
10364 BaseLoad.getValue(1), ExtraLoad.getValue(1));
10366 // Because vperm has a big-endian bias, we must reverse the order
10367 // of the input vectors and complement the permute control vector
10368 // when generating little endian code. We have already handled the
10369 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
10370 // and ExtraLoad here.
10372 if (isLittleEndian)
10373 Perm = BuildIntrinsicOp(IntrPerm,
10374 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
10376 Perm = BuildIntrinsicOp(IntrPerm,
10377 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
10380 Perm = Subtarget.hasAltivec() ?
10381 DAG.getNode(ISD::BITCAST, dl, VT, Perm) :
10382 DAG.getNode(ISD::FP_ROUND, dl, VT, Perm, // QPX
10383 DAG.getTargetConstant(1, dl, MVT::i64));
10384 // second argument is 1 because this rounding
10385 // is always exact.
10387 // The output of the permutation is our loaded result, the TokenFactor is
10389 DCI.CombineTo(N, Perm, TF);
10390 return SDValue(N, 0);
10394 case ISD::INTRINSIC_WO_CHAIN: {
10395 bool isLittleEndian = Subtarget.isLittleEndian();
10396 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
10397 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
10398 : Intrinsic::ppc_altivec_lvsl);
10399 if ((IID == Intr ||
10400 IID == Intrinsic::ppc_qpx_qvlpcld ||
10401 IID == Intrinsic::ppc_qpx_qvlpcls) &&
10402 N->getOperand(1)->getOpcode() == ISD::ADD) {
10403 SDValue Add = N->getOperand(1);
10405 int Bits = IID == Intrinsic::ppc_qpx_qvlpcld ?
10406 5 /* 32 byte alignment */ : 4 /* 16 byte alignment */;
10408 if (DAG.MaskedValueIsZero(
10409 Add->getOperand(1),
10410 APInt::getAllOnesValue(Bits /* alignment */)
10412 Add.getValueType().getScalarType().getSizeInBits()))) {
10413 SDNode *BasePtr = Add->getOperand(0).getNode();
10414 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10415 UE = BasePtr->use_end();
10417 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10418 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() == IID) {
10419 // We've found another LVSL/LVSR, and this address is an aligned
10420 // multiple of that one. The results will be the same, so use the
10421 // one we've just found instead.
10423 return SDValue(*UI, 0);
10428 if (isa<ConstantSDNode>(Add->getOperand(1))) {
10429 SDNode *BasePtr = Add->getOperand(0).getNode();
10430 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10431 UE = BasePtr->use_end(); UI != UE; ++UI) {
10432 if (UI->getOpcode() == ISD::ADD &&
10433 isa<ConstantSDNode>(UI->getOperand(1)) &&
10434 (cast<ConstantSDNode>(Add->getOperand(1))->getZExtValue() -
10435 cast<ConstantSDNode>(UI->getOperand(1))->getZExtValue()) %
10436 (1ULL << Bits) == 0) {
10437 SDNode *OtherAdd = *UI;
10438 for (SDNode::use_iterator VI = OtherAdd->use_begin(),
10439 VE = OtherAdd->use_end(); VI != VE; ++VI) {
10440 if (VI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10441 cast<ConstantSDNode>(VI->getOperand(0))->getZExtValue() == IID) {
10442 return SDValue(*VI, 0);
10452 case ISD::INTRINSIC_W_CHAIN: {
10453 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10454 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10455 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10458 case Intrinsic::ppc_vsx_lxvw4x:
10459 case Intrinsic::ppc_vsx_lxvd2x:
10460 return expandVSXLoadForLE(N, DCI);
10465 case ISD::INTRINSIC_VOID: {
10466 // For little endian, VSX stores require generating xxswapd/stxvd2x.
10467 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10468 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10471 case Intrinsic::ppc_vsx_stxvw4x:
10472 case Intrinsic::ppc_vsx_stxvd2x:
10473 return expandVSXStoreForLE(N, DCI);
10479 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
10480 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
10481 N->getOperand(0).hasOneUse() &&
10482 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
10483 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10484 N->getValueType(0) == MVT::i64))) {
10485 SDValue Load = N->getOperand(0);
10486 LoadSDNode *LD = cast<LoadSDNode>(Load);
10487 // Create the byte-swapping load.
10489 LD->getChain(), // Chain
10490 LD->getBasePtr(), // Ptr
10491 DAG.getValueType(N->getValueType(0)) // VT
10494 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
10495 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
10496 MVT::i64 : MVT::i32, MVT::Other),
10497 Ops, LD->getMemoryVT(), LD->getMemOperand());
10499 // If this is an i16 load, insert the truncate.
10500 SDValue ResVal = BSLoad;
10501 if (N->getValueType(0) == MVT::i16)
10502 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
10504 // First, combine the bswap away. This makes the value produced by the
10506 DCI.CombineTo(N, ResVal);
10508 // Next, combine the load away, we give it a bogus result value but a real
10509 // chain result. The result value is dead because the bswap is dead.
10510 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
10512 // Return N so it doesn't get rechecked!
10513 return SDValue(N, 0);
10517 case PPCISD::VCMP: {
10518 // If a VCMPo node already exists with exactly the same operands as this
10519 // node, use its result instead of this node (VCMPo computes both a CR6 and
10520 // a normal output).
10522 if (!N->getOperand(0).hasOneUse() &&
10523 !N->getOperand(1).hasOneUse() &&
10524 !N->getOperand(2).hasOneUse()) {
10526 // Scan all of the users of the LHS, looking for VCMPo's that match.
10527 SDNode *VCMPoNode = nullptr;
10529 SDNode *LHSN = N->getOperand(0).getNode();
10530 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
10532 if (UI->getOpcode() == PPCISD::VCMPo &&
10533 UI->getOperand(1) == N->getOperand(1) &&
10534 UI->getOperand(2) == N->getOperand(2) &&
10535 UI->getOperand(0) == N->getOperand(0)) {
10540 // If there is no VCMPo node, or if the flag value has a single use, don't
10542 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
10545 // Look at the (necessarily single) use of the flag value. If it has a
10546 // chain, this transformation is more complex. Note that multiple things
10547 // could use the value result, which we should ignore.
10548 SDNode *FlagUser = nullptr;
10549 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
10550 FlagUser == nullptr; ++UI) {
10551 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
10552 SDNode *User = *UI;
10553 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
10554 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
10561 // If the user is a MFOCRF instruction, we know this is safe.
10562 // Otherwise we give up for right now.
10563 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
10564 return SDValue(VCMPoNode, 0);
10568 case ISD::BRCOND: {
10569 SDValue Cond = N->getOperand(1);
10570 SDValue Target = N->getOperand(2);
10572 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10573 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
10574 Intrinsic::ppc_is_decremented_ctr_nonzero) {
10576 // We now need to make the intrinsic dead (it cannot be instruction
10578 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
10579 assert(Cond.getNode()->hasOneUse() &&
10580 "Counter decrement has more than one use");
10582 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
10583 N->getOperand(0), Target);
10588 // If this is a branch on an altivec predicate comparison, lower this so
10589 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
10590 // lowering is done pre-legalize, because the legalizer lowers the predicate
10591 // compare down to code that is difficult to reassemble.
10592 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
10593 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
10595 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
10596 // value. If so, pass-through the AND to get to the intrinsic.
10597 if (LHS.getOpcode() == ISD::AND &&
10598 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10599 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
10600 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10601 isa<ConstantSDNode>(LHS.getOperand(1)) &&
10602 !isNullConstant(LHS.getOperand(1)))
10603 LHS = LHS.getOperand(0);
10605 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10606 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
10607 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10608 isa<ConstantSDNode>(RHS)) {
10609 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
10610 "Counter decrement comparison is not EQ or NE");
10612 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10613 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
10614 (CC == ISD::SETNE && !Val);
10616 // We now need to make the intrinsic dead (it cannot be instruction
10618 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
10619 assert(LHS.getNode()->hasOneUse() &&
10620 "Counter decrement has more than one use");
10622 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
10623 N->getOperand(0), N->getOperand(4));
10629 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10630 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
10631 getVectorCompareInfo(LHS, CompareOpc, isDot, Subtarget)) {
10632 assert(isDot && "Can't compare against a vector result!");
10634 // If this is a comparison against something other than 0/1, then we know
10635 // that the condition is never/always true.
10636 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10637 if (Val != 0 && Val != 1) {
10638 if (CC == ISD::SETEQ) // Cond never true, remove branch.
10639 return N->getOperand(0);
10640 // Always !=, turn it into an unconditional branch.
10641 return DAG.getNode(ISD::BR, dl, MVT::Other,
10642 N->getOperand(0), N->getOperand(4));
10645 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
10647 // Create the PPCISD altivec 'dot' comparison node.
10649 LHS.getOperand(2), // LHS of compare
10650 LHS.getOperand(3), // RHS of compare
10651 DAG.getConstant(CompareOpc, dl, MVT::i32)
10653 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
10654 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
10656 // Unpack the result based on how the target uses it.
10657 PPC::Predicate CompOpc;
10658 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
10659 default: // Can't happen, don't crash on invalid number though.
10660 case 0: // Branch on the value of the EQ bit of CR6.
10661 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
10663 case 1: // Branch on the inverted value of the EQ bit of CR6.
10664 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
10666 case 2: // Branch on the value of the LT bit of CR6.
10667 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
10669 case 3: // Branch on the inverted value of the LT bit of CR6.
10670 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
10674 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
10675 DAG.getConstant(CompOpc, dl, MVT::i32),
10676 DAG.getRegister(PPC::CR6, MVT::i32),
10677 N->getOperand(4), CompNode.getValue(1));
10687 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
10689 std::vector<SDNode *> *Created) const {
10690 // fold (sdiv X, pow2)
10691 EVT VT = N->getValueType(0);
10692 if (VT == MVT::i64 && !Subtarget.isPPC64())
10694 if ((VT != MVT::i32 && VT != MVT::i64) ||
10695 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
10699 SDValue N0 = N->getOperand(0);
10701 bool IsNegPow2 = (-Divisor).isPowerOf2();
10702 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
10703 SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT);
10705 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
10707 Created->push_back(Op.getNode());
10710 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Op);
10712 Created->push_back(Op.getNode());
10718 //===----------------------------------------------------------------------===//
10719 // Inline Assembly Support
10720 //===----------------------------------------------------------------------===//
10722 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10725 const SelectionDAG &DAG,
10726 unsigned Depth) const {
10727 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
10728 switch (Op.getOpcode()) {
10730 case PPCISD::LBRX: {
10731 // lhbrx is known to have the top bits cleared out.
10732 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
10733 KnownZero = 0xFFFF0000;
10736 case ISD::INTRINSIC_WO_CHAIN: {
10737 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
10739 case Intrinsic::ppc_altivec_vcmpbfp_p:
10740 case Intrinsic::ppc_altivec_vcmpeqfp_p:
10741 case Intrinsic::ppc_altivec_vcmpequb_p:
10742 case Intrinsic::ppc_altivec_vcmpequh_p:
10743 case Intrinsic::ppc_altivec_vcmpequw_p:
10744 case Intrinsic::ppc_altivec_vcmpequd_p:
10745 case Intrinsic::ppc_altivec_vcmpgefp_p:
10746 case Intrinsic::ppc_altivec_vcmpgtfp_p:
10747 case Intrinsic::ppc_altivec_vcmpgtsb_p:
10748 case Intrinsic::ppc_altivec_vcmpgtsh_p:
10749 case Intrinsic::ppc_altivec_vcmpgtsw_p:
10750 case Intrinsic::ppc_altivec_vcmpgtsd_p:
10751 case Intrinsic::ppc_altivec_vcmpgtub_p:
10752 case Intrinsic::ppc_altivec_vcmpgtuh_p:
10753 case Intrinsic::ppc_altivec_vcmpgtuw_p:
10754 case Intrinsic::ppc_altivec_vcmpgtud_p:
10755 KnownZero = ~1U; // All bits but the low one are known to be zero.
10762 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
10763 switch (Subtarget.getDarwinDirective()) {
10766 case PPC::DIR_PWR4:
10767 case PPC::DIR_PWR5:
10768 case PPC::DIR_PWR5X:
10769 case PPC::DIR_PWR6:
10770 case PPC::DIR_PWR6X:
10771 case PPC::DIR_PWR7:
10772 case PPC::DIR_PWR8: {
10776 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
10778 // For small loops (between 5 and 8 instructions), align to a 32-byte
10779 // boundary so that the entire loop fits in one instruction-cache line.
10780 uint64_t LoopSize = 0;
10781 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
10782 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
10783 LoopSize += TII->GetInstSizeInBytes(J);
10785 if (LoopSize > 16 && LoopSize <= 32)
10792 return TargetLowering::getPrefLoopAlignment(ML);
10795 /// getConstraintType - Given a constraint, return the type of
10796 /// constraint it is for this target.
10797 PPCTargetLowering::ConstraintType
10798 PPCTargetLowering::getConstraintType(StringRef Constraint) const {
10799 if (Constraint.size() == 1) {
10800 switch (Constraint[0]) {
10807 return C_RegisterClass;
10809 // FIXME: While Z does indicate a memory constraint, it specifically
10810 // indicates an r+r address (used in conjunction with the 'y' modifier
10811 // in the replacement string). Currently, we're forcing the base
10812 // register to be r0 in the asm printer (which is interpreted as zero)
10813 // and forming the complete address in the second register. This is
10817 } else if (Constraint == "wc") { // individual CR bits.
10818 return C_RegisterClass;
10819 } else if (Constraint == "wa" || Constraint == "wd" ||
10820 Constraint == "wf" || Constraint == "ws") {
10821 return C_RegisterClass; // VSX registers.
10823 return TargetLowering::getConstraintType(Constraint);
10826 /// Examine constraint type and operand type and determine a weight value.
10827 /// This object must already have been set up with the operand type
10828 /// and the current alternative constraint selected.
10829 TargetLowering::ConstraintWeight
10830 PPCTargetLowering::getSingleConstraintMatchWeight(
10831 AsmOperandInfo &info, const char *constraint) const {
10832 ConstraintWeight weight = CW_Invalid;
10833 Value *CallOperandVal = info.CallOperandVal;
10834 // If we don't have a value, we can't do a match,
10835 // but allow it at the lowest weight.
10836 if (!CallOperandVal)
10838 Type *type = CallOperandVal->getType();
10840 // Look at the constraint type.
10841 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
10842 return CW_Register; // an individual CR bit.
10843 else if ((StringRef(constraint) == "wa" ||
10844 StringRef(constraint) == "wd" ||
10845 StringRef(constraint) == "wf") &&
10846 type->isVectorTy())
10847 return CW_Register;
10848 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
10849 return CW_Register;
10851 switch (*constraint) {
10853 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10856 if (type->isIntegerTy())
10857 weight = CW_Register;
10860 if (type->isFloatTy())
10861 weight = CW_Register;
10864 if (type->isDoubleTy())
10865 weight = CW_Register;
10868 if (type->isVectorTy())
10869 weight = CW_Register;
10872 weight = CW_Register;
10875 weight = CW_Memory;
10881 std::pair<unsigned, const TargetRegisterClass *>
10882 PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
10883 StringRef Constraint,
10885 if (Constraint.size() == 1) {
10886 // GCC RS6000 Constraint Letters
10887 switch (Constraint[0]) {
10888 case 'b': // R1-R31
10889 if (VT == MVT::i64 && Subtarget.isPPC64())
10890 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
10891 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
10892 case 'r': // R0-R31
10893 if (VT == MVT::i64 && Subtarget.isPPC64())
10894 return std::make_pair(0U, &PPC::G8RCRegClass);
10895 return std::make_pair(0U, &PPC::GPRCRegClass);
10897 if (VT == MVT::f32 || VT == MVT::i32)
10898 return std::make_pair(0U, &PPC::F4RCRegClass);
10899 if (VT == MVT::f64 || VT == MVT::i64)
10900 return std::make_pair(0U, &PPC::F8RCRegClass);
10901 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10902 return std::make_pair(0U, &PPC::QFRCRegClass);
10903 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10904 return std::make_pair(0U, &PPC::QSRCRegClass);
10907 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10908 return std::make_pair(0U, &PPC::QFRCRegClass);
10909 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10910 return std::make_pair(0U, &PPC::QSRCRegClass);
10911 if (Subtarget.hasAltivec())
10912 return std::make_pair(0U, &PPC::VRRCRegClass);
10914 return std::make_pair(0U, &PPC::CRRCRegClass);
10916 } else if (Constraint == "wc" && Subtarget.useCRBits()) {
10917 // An individual CR bit.
10918 return std::make_pair(0U, &PPC::CRBITRCRegClass);
10919 } else if ((Constraint == "wa" || Constraint == "wd" ||
10920 Constraint == "wf") && Subtarget.hasVSX()) {
10921 return std::make_pair(0U, &PPC::VSRCRegClass);
10922 } else if (Constraint == "ws" && Subtarget.hasVSX()) {
10923 if (VT == MVT::f32 && Subtarget.hasP8Vector())
10924 return std::make_pair(0U, &PPC::VSSRCRegClass);
10926 return std::make_pair(0U, &PPC::VSFRCRegClass);
10929 std::pair<unsigned, const TargetRegisterClass *> R =
10930 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
10932 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
10933 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
10934 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
10936 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
10937 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
10938 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
10939 PPC::GPRCRegClass.contains(R.first))
10940 return std::make_pair(TRI->getMatchingSuperReg(R.first,
10941 PPC::sub_32, &PPC::G8RCRegClass),
10942 &PPC::G8RCRegClass);
10944 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
10945 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
10946 R.first = PPC::CR0;
10947 R.second = &PPC::CRRCRegClass;
10953 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10954 /// vector. If it is invalid, don't add anything to Ops.
10955 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10956 std::string &Constraint,
10957 std::vector<SDValue>&Ops,
10958 SelectionDAG &DAG) const {
10961 // Only support length 1 constraints.
10962 if (Constraint.length() > 1) return;
10964 char Letter = Constraint[0];
10975 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
10976 if (!CST) return; // Must be an immediate to match.
10978 int64_t Value = CST->getSExtValue();
10979 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
10980 // numbers are printed as such.
10982 default: llvm_unreachable("Unknown constraint letter!");
10983 case 'I': // "I" is a signed 16-bit constant.
10984 if (isInt<16>(Value))
10985 Result = DAG.getTargetConstant(Value, dl, TCVT);
10987 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
10988 if (isShiftedUInt<16, 16>(Value))
10989 Result = DAG.getTargetConstant(Value, dl, TCVT);
10991 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
10992 if (isShiftedInt<16, 16>(Value))
10993 Result = DAG.getTargetConstant(Value, dl, TCVT);
10995 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
10996 if (isUInt<16>(Value))
10997 Result = DAG.getTargetConstant(Value, dl, TCVT);
10999 case 'M': // "M" is a constant that is greater than 31.
11001 Result = DAG.getTargetConstant(Value, dl, TCVT);
11003 case 'N': // "N" is a positive constant that is an exact power of two.
11004 if (Value > 0 && isPowerOf2_64(Value))
11005 Result = DAG.getTargetConstant(Value, dl, TCVT);
11007 case 'O': // "O" is the constant zero.
11009 Result = DAG.getTargetConstant(Value, dl, TCVT);
11011 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
11012 if (isInt<16>(-Value))
11013 Result = DAG.getTargetConstant(Value, dl, TCVT);
11020 if (Result.getNode()) {
11021 Ops.push_back(Result);
11025 // Handle standard constraint letters.
11026 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
11029 // isLegalAddressingMode - Return true if the addressing mode represented
11030 // by AM is legal for this target, for a load/store of the specified type.
11031 bool PPCTargetLowering::isLegalAddressingMode(const DataLayout &DL,
11032 const AddrMode &AM, Type *Ty,
11033 unsigned AS) const {
11034 // PPC does not allow r+i addressing modes for vectors!
11035 if (Ty->isVectorTy() && AM.BaseOffs != 0)
11038 // PPC allows a sign-extended 16-bit immediate field.
11039 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
11042 // No global is ever allowed as a base.
11046 // PPC only support r+r,
11047 switch (AM.Scale) {
11048 case 0: // "r+i" or just "i", depending on HasBaseReg.
11051 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
11053 // Otherwise we have r+r or r+i.
11056 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
11058 // Allow 2*r as r+r.
11061 // No other scales are supported.
11068 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
11069 SelectionDAG &DAG) const {
11070 MachineFunction &MF = DAG.getMachineFunction();
11071 MachineFrameInfo *MFI = MF.getFrameInfo();
11072 MFI->setReturnAddressIsTaken(true);
11074 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
11078 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11080 // Make sure the function does not optimize away the store of the RA to
11082 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
11083 FuncInfo->setLRStoreRequired();
11084 bool isPPC64 = Subtarget.isPPC64();
11085 auto PtrVT = getPointerTy(MF.getDataLayout());
11088 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11090 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl,
11091 isPPC64 ? MVT::i64 : MVT::i32);
11092 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11093 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
11094 MachinePointerInfo(), false, false, false, 0);
11097 // Just load the return address off the stack.
11098 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
11099 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
11100 MachinePointerInfo(), false, false, false, 0);
11103 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
11104 SelectionDAG &DAG) const {
11106 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11108 MachineFunction &MF = DAG.getMachineFunction();
11109 MachineFrameInfo *MFI = MF.getFrameInfo();
11110 MFI->setFrameAddressIsTaken(true);
11112 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
11113 bool isPPC64 = PtrVT == MVT::i64;
11115 // Naked functions never have a frame pointer, and so we use r1. For all
11116 // other functions, this decision must be delayed until during PEI.
11118 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
11119 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
11121 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
11123 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
11126 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
11127 FrameAddr, MachinePointerInfo(), false, false,
11132 // FIXME? Maybe this could be a TableGen attribute on some registers and
11133 // this table could be generated automatically from RegInfo.
11134 unsigned PPCTargetLowering::getRegisterByName(const char* RegName, EVT VT,
11135 SelectionDAG &DAG) const {
11136 bool isPPC64 = Subtarget.isPPC64();
11137 bool isDarwinABI = Subtarget.isDarwinABI();
11139 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
11140 (!isPPC64 && VT != MVT::i32))
11141 report_fatal_error("Invalid register global variable type");
11143 bool is64Bit = isPPC64 && VT == MVT::i64;
11144 unsigned Reg = StringSwitch<unsigned>(RegName)
11145 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
11146 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2)
11147 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
11148 (is64Bit ? PPC::X13 : PPC::R13))
11153 report_fatal_error("Invalid register name global variable");
11157 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
11158 // The PowerPC target isn't yet aware of offsets.
11162 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
11164 unsigned Intrinsic) const {
11166 switch (Intrinsic) {
11167 case Intrinsic::ppc_qpx_qvlfd:
11168 case Intrinsic::ppc_qpx_qvlfs:
11169 case Intrinsic::ppc_qpx_qvlfcd:
11170 case Intrinsic::ppc_qpx_qvlfcs:
11171 case Intrinsic::ppc_qpx_qvlfiwa:
11172 case Intrinsic::ppc_qpx_qvlfiwz:
11173 case Intrinsic::ppc_altivec_lvx:
11174 case Intrinsic::ppc_altivec_lvxl:
11175 case Intrinsic::ppc_altivec_lvebx:
11176 case Intrinsic::ppc_altivec_lvehx:
11177 case Intrinsic::ppc_altivec_lvewx:
11178 case Intrinsic::ppc_vsx_lxvd2x:
11179 case Intrinsic::ppc_vsx_lxvw4x: {
11181 switch (Intrinsic) {
11182 case Intrinsic::ppc_altivec_lvebx:
11185 case Intrinsic::ppc_altivec_lvehx:
11188 case Intrinsic::ppc_altivec_lvewx:
11191 case Intrinsic::ppc_vsx_lxvd2x:
11194 case Intrinsic::ppc_qpx_qvlfd:
11197 case Intrinsic::ppc_qpx_qvlfs:
11200 case Intrinsic::ppc_qpx_qvlfcd:
11203 case Intrinsic::ppc_qpx_qvlfcs:
11211 Info.opc = ISD::INTRINSIC_W_CHAIN;
11213 Info.ptrVal = I.getArgOperand(0);
11214 Info.offset = -VT.getStoreSize()+1;
11215 Info.size = 2*VT.getStoreSize()-1;
11218 Info.readMem = true;
11219 Info.writeMem = false;
11222 case Intrinsic::ppc_qpx_qvlfda:
11223 case Intrinsic::ppc_qpx_qvlfsa:
11224 case Intrinsic::ppc_qpx_qvlfcda:
11225 case Intrinsic::ppc_qpx_qvlfcsa:
11226 case Intrinsic::ppc_qpx_qvlfiwaa:
11227 case Intrinsic::ppc_qpx_qvlfiwza: {
11229 switch (Intrinsic) {
11230 case Intrinsic::ppc_qpx_qvlfda:
11233 case Intrinsic::ppc_qpx_qvlfsa:
11236 case Intrinsic::ppc_qpx_qvlfcda:
11239 case Intrinsic::ppc_qpx_qvlfcsa:
11247 Info.opc = ISD::INTRINSIC_W_CHAIN;
11249 Info.ptrVal = I.getArgOperand(0);
11251 Info.size = VT.getStoreSize();
11254 Info.readMem = true;
11255 Info.writeMem = false;
11258 case Intrinsic::ppc_qpx_qvstfd:
11259 case Intrinsic::ppc_qpx_qvstfs:
11260 case Intrinsic::ppc_qpx_qvstfcd:
11261 case Intrinsic::ppc_qpx_qvstfcs:
11262 case Intrinsic::ppc_qpx_qvstfiw:
11263 case Intrinsic::ppc_altivec_stvx:
11264 case Intrinsic::ppc_altivec_stvxl:
11265 case Intrinsic::ppc_altivec_stvebx:
11266 case Intrinsic::ppc_altivec_stvehx:
11267 case Intrinsic::ppc_altivec_stvewx:
11268 case Intrinsic::ppc_vsx_stxvd2x:
11269 case Intrinsic::ppc_vsx_stxvw4x: {
11271 switch (Intrinsic) {
11272 case Intrinsic::ppc_altivec_stvebx:
11275 case Intrinsic::ppc_altivec_stvehx:
11278 case Intrinsic::ppc_altivec_stvewx:
11281 case Intrinsic::ppc_vsx_stxvd2x:
11284 case Intrinsic::ppc_qpx_qvstfd:
11287 case Intrinsic::ppc_qpx_qvstfs:
11290 case Intrinsic::ppc_qpx_qvstfcd:
11293 case Intrinsic::ppc_qpx_qvstfcs:
11301 Info.opc = ISD::INTRINSIC_VOID;
11303 Info.ptrVal = I.getArgOperand(1);
11304 Info.offset = -VT.getStoreSize()+1;
11305 Info.size = 2*VT.getStoreSize()-1;
11308 Info.readMem = false;
11309 Info.writeMem = true;
11312 case Intrinsic::ppc_qpx_qvstfda:
11313 case Intrinsic::ppc_qpx_qvstfsa:
11314 case Intrinsic::ppc_qpx_qvstfcda:
11315 case Intrinsic::ppc_qpx_qvstfcsa:
11316 case Intrinsic::ppc_qpx_qvstfiwa: {
11318 switch (Intrinsic) {
11319 case Intrinsic::ppc_qpx_qvstfda:
11322 case Intrinsic::ppc_qpx_qvstfsa:
11325 case Intrinsic::ppc_qpx_qvstfcda:
11328 case Intrinsic::ppc_qpx_qvstfcsa:
11336 Info.opc = ISD::INTRINSIC_VOID;
11338 Info.ptrVal = I.getArgOperand(1);
11340 Info.size = VT.getStoreSize();
11343 Info.readMem = false;
11344 Info.writeMem = true;
11354 /// getOptimalMemOpType - Returns the target specific optimal type for load
11355 /// and store operations as a result of memset, memcpy, and memmove
11356 /// lowering. If DstAlign is zero that means it's safe to destination
11357 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
11358 /// means there isn't a need to check it against alignment requirement,
11359 /// probably because the source does not need to be loaded. If 'IsMemset' is
11360 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
11361 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
11362 /// source is constant so it does not need to be loaded.
11363 /// It returns EVT::Other if the type should be determined using generic
11364 /// target-independent logic.
11365 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
11366 unsigned DstAlign, unsigned SrcAlign,
11367 bool IsMemset, bool ZeroMemset,
11369 MachineFunction &MF) const {
11370 if (getTargetMachine().getOptLevel() != CodeGenOpt::None) {
11371 const Function *F = MF.getFunction();
11372 // When expanding a memset, require at least two QPX instructions to cover
11373 // the cost of loading the value to be stored from the constant pool.
11374 if (Subtarget.hasQPX() && Size >= 32 && (!IsMemset || Size >= 64) &&
11375 (!SrcAlign || SrcAlign >= 32) && (!DstAlign || DstAlign >= 32) &&
11376 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
11380 // We should use Altivec/VSX loads and stores when available. For unaligned
11381 // addresses, unaligned VSX loads are only fast starting with the P8.
11382 if (Subtarget.hasAltivec() && Size >= 16 &&
11383 (((!SrcAlign || SrcAlign >= 16) && (!DstAlign || DstAlign >= 16)) ||
11384 ((IsMemset && Subtarget.hasVSX()) || Subtarget.hasP8Vector())))
11388 if (Subtarget.isPPC64()) {
11395 /// \brief Returns true if it is beneficial to convert a load of a constant
11396 /// to just the constant itself.
11397 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11399 assert(Ty->isIntegerTy());
11401 unsigned BitSize = Ty->getPrimitiveSizeInBits();
11402 if (BitSize == 0 || BitSize > 64)
11407 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11408 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11410 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11411 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11412 return NumBits1 == 64 && NumBits2 == 32;
11415 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11416 if (!VT1.isInteger() || !VT2.isInteger())
11418 unsigned NumBits1 = VT1.getSizeInBits();
11419 unsigned NumBits2 = VT2.getSizeInBits();
11420 return NumBits1 == 64 && NumBits2 == 32;
11423 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
11424 // Generally speaking, zexts are not free, but they are free when they can be
11425 // folded with other operations.
11426 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
11427 EVT MemVT = LD->getMemoryVT();
11428 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
11429 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
11430 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
11431 LD->getExtensionType() == ISD::ZEXTLOAD))
11435 // FIXME: Add other cases...
11436 // - 32-bit shifts with a zext to i64
11437 // - zext after ctlz, bswap, etc.
11438 // - zext after and by a constant mask
11440 return TargetLowering::isZExtFree(Val, VT2);
11443 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
11444 assert(VT.isFloatingPoint());
11448 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
11449 return isInt<16>(Imm) || isUInt<16>(Imm);
11452 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
11453 return isInt<16>(Imm) || isUInt<16>(Imm);
11456 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
11459 bool *Fast) const {
11460 if (DisablePPCUnaligned)
11463 // PowerPC supports unaligned memory access for simple non-vector types.
11464 // Although accessing unaligned addresses is not as efficient as accessing
11465 // aligned addresses, it is generally more efficient than manual expansion,
11466 // and generally only traps for software emulation when crossing page
11469 if (!VT.isSimple())
11472 if (VT.getSimpleVT().isVector()) {
11473 if (Subtarget.hasVSX()) {
11474 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
11475 VT != MVT::v4f32 && VT != MVT::v4i32)
11482 if (VT == MVT::ppcf128)
11491 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
11492 VT = VT.getScalarType();
11494 if (!VT.isSimple())
11497 switch (VT.getSimpleVT().SimpleTy) {
11509 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
11510 // LR is a callee-save register, but we must treat it as clobbered by any call
11511 // site. Hence we include LR in the scratch registers, which are in turn added
11512 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
11513 // to CTR, which is used by any indirect call.
11514 static const MCPhysReg ScratchRegs[] = {
11515 PPC::X12, PPC::LR8, PPC::CTR8, 0
11518 return ScratchRegs;
11521 unsigned PPCTargetLowering::getExceptionPointerRegister(
11522 const Constant *PersonalityFn) const {
11523 return Subtarget.isPPC64() ? PPC::X3 : PPC::R3;
11526 unsigned PPCTargetLowering::getExceptionSelectorRegister(
11527 const Constant *PersonalityFn) const {
11528 return Subtarget.isPPC64() ? PPC::X4 : PPC::R4;
11532 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
11533 EVT VT , unsigned DefinedValues) const {
11534 if (VT == MVT::v2i64)
11535 return Subtarget.hasDirectMove(); // Don't need stack ops with direct moves
11537 if (Subtarget.hasQPX()) {
11538 if (VT == MVT::v4f32 || VT == MVT::v4f64 || VT == MVT::v4i1)
11542 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
11545 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
11546 if (DisableILPPref || Subtarget.enableMachineScheduler())
11547 return TargetLowering::getSchedulingPreference(N);
11552 // Create a fast isel object.
11554 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
11555 const TargetLibraryInfo *LibInfo) const {
11556 return PPC::createFastISel(FuncInfo, LibInfo);