1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CallingConv.h"
29 #include "llvm/Constants.h"
30 #include "llvm/Function.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
37 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
38 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
41 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
42 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
46 // Use _setjmp/_longjmp instead of setjmp/longjmp.
47 setUseUnderscoreSetJmp(true);
48 setUseUnderscoreLongJmp(true);
50 // Set up the register classes.
51 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
52 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
53 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
55 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
56 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
57 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
59 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
61 // PowerPC has pre-inc load and store's.
62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
65 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
67 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
70 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
73 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg)
74 setConvertAction(MVT::ppcf128, MVT::f64, Expand);
75 setConvertAction(MVT::ppcf128, MVT::f32, Expand);
76 // This is used in the ppcf128->int sequence. Note it has different semantics
77 // from FP_ROUND: that rounds to nearest, this rounds to zero.
78 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
80 // PowerPC has no SREM/UREM instructions
81 setOperationAction(ISD::SREM, MVT::i32, Expand);
82 setOperationAction(ISD::UREM, MVT::i32, Expand);
83 setOperationAction(ISD::SREM, MVT::i64, Expand);
84 setOperationAction(ISD::UREM, MVT::i64, Expand);
86 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
87 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
88 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
89 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
90 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
91 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
92 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
93 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
94 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
96 // We don't support sin/cos/sqrt/fmod/pow
97 setOperationAction(ISD::FSIN , MVT::f64, Expand);
98 setOperationAction(ISD::FCOS , MVT::f64, Expand);
99 setOperationAction(ISD::FREM , MVT::f64, Expand);
100 setOperationAction(ISD::FPOW , MVT::f64, Expand);
101 setOperationAction(ISD::FSIN , MVT::f32, Expand);
102 setOperationAction(ISD::FCOS , MVT::f32, Expand);
103 setOperationAction(ISD::FREM , MVT::f32, Expand);
104 setOperationAction(ISD::FPOW , MVT::f32, Expand);
106 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
108 // If we're enabling GP optimizations, use hardware square root
109 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
110 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
111 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
114 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
115 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
117 // PowerPC does not have BSWAP, CTPOP or CTTZ
118 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
119 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
120 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
121 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
122 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
123 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
125 // PowerPC does not have ROTR
126 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
127 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
129 // PowerPC does not have Select
130 setOperationAction(ISD::SELECT, MVT::i32, Expand);
131 setOperationAction(ISD::SELECT, MVT::i64, Expand);
132 setOperationAction(ISD::SELECT, MVT::f32, Expand);
133 setOperationAction(ISD::SELECT, MVT::f64, Expand);
135 // PowerPC wants to turn select_cc of FP into fsel when possible.
136 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
137 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
139 // PowerPC wants to optimize integer setcc a bit
140 setOperationAction(ISD::SETCC, MVT::i32, Custom);
142 // PowerPC does not have BRCOND which requires SetCC
143 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
145 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
147 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
148 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
150 // PowerPC does not have [U|S]INT_TO_FP
151 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
152 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
154 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
155 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
156 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
157 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
159 // We cannot sextinreg(i1). Expand to shifts.
160 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
162 // Support label based line numbers.
163 setOperationAction(ISD::DBG_STOPPOINT, MVT::Other, Expand);
164 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
166 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
167 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
168 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
169 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
172 // We want to legalize GlobalAddress and ConstantPool nodes into the
173 // appropriate instructions to materialize the address.
174 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
175 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
176 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
177 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
178 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
179 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
180 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
181 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
183 // RET must be custom lowered, to meet ABI requirements.
184 setOperationAction(ISD::RET , MVT::Other, Custom);
187 setOperationAction(ISD::TRAP, MVT::Other, Legal);
189 // TRAMPOLINE is custom lowered.
190 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
192 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
193 setOperationAction(ISD::VASTART , MVT::Other, Custom);
195 // VAARG is custom lowered with ELF 32 ABI
196 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
197 setOperationAction(ISD::VAARG, MVT::Other, Custom);
199 setOperationAction(ISD::VAARG, MVT::Other, Expand);
201 // Use the default implementation.
202 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
203 setOperationAction(ISD::VAEND , MVT::Other, Expand);
204 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
205 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
206 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
209 // We want to custom lower some of our intrinsics.
210 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
212 // Comparisons that require checking two conditions.
213 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
214 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
215 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
216 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
217 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
218 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
219 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
220 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
221 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
222 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
223 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
224 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
226 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
227 // They also have instructions for converting between i64 and fp.
228 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
229 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
230 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
231 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
232 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
234 // FIXME: disable this lowered code. This generates 64-bit register values,
235 // and we don't model the fact that the top part is clobbered by calls. We
236 // need to flag these together so that the value isn't live across a call.
237 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
239 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
240 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
242 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
243 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
246 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
247 // 64-bit PowerPC implementations can support i64 types directly
248 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
249 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
250 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
251 // 64-bit PowerPC wants to expand i128 shifts itself.
252 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
253 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
254 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
256 // 32-bit PowerPC wants to expand i64 shifts itself.
257 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
258 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
259 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
262 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
263 // First set operation action for all vector types to expand. Then we
264 // will selectively turn on ones that can be effectively codegen'd.
265 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
266 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
267 MVT VT = (MVT::SimpleValueType)i;
269 // add/sub are legal for all supported vector VT's.
270 setOperationAction(ISD::ADD , VT, Legal);
271 setOperationAction(ISD::SUB , VT, Legal);
273 // We promote all shuffles to v16i8.
274 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
275 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
277 // We promote all non-typed operations to v4i32.
278 setOperationAction(ISD::AND , VT, Promote);
279 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
280 setOperationAction(ISD::OR , VT, Promote);
281 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
282 setOperationAction(ISD::XOR , VT, Promote);
283 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
284 setOperationAction(ISD::LOAD , VT, Promote);
285 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
286 setOperationAction(ISD::SELECT, VT, Promote);
287 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
288 setOperationAction(ISD::STORE, VT, Promote);
289 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
291 // No other operations are legal.
292 setOperationAction(ISD::MUL , VT, Expand);
293 setOperationAction(ISD::SDIV, VT, Expand);
294 setOperationAction(ISD::SREM, VT, Expand);
295 setOperationAction(ISD::UDIV, VT, Expand);
296 setOperationAction(ISD::UREM, VT, Expand);
297 setOperationAction(ISD::FDIV, VT, Expand);
298 setOperationAction(ISD::FNEG, VT, Expand);
299 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
300 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
301 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
302 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
303 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
304 setOperationAction(ISD::UDIVREM, VT, Expand);
305 setOperationAction(ISD::SDIVREM, VT, Expand);
306 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
307 setOperationAction(ISD::FPOW, VT, Expand);
308 setOperationAction(ISD::CTPOP, VT, Expand);
309 setOperationAction(ISD::CTLZ, VT, Expand);
310 setOperationAction(ISD::CTTZ, VT, Expand);
313 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
314 // with merges, splats, etc.
315 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
317 setOperationAction(ISD::AND , MVT::v4i32, Legal);
318 setOperationAction(ISD::OR , MVT::v4i32, Legal);
319 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
320 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
321 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
322 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
324 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
325 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
326 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
327 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
329 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
330 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
331 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
332 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
334 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
335 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
337 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
338 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
339 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
340 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
343 setShiftAmountType(MVT::i32);
344 setBooleanContents(ZeroOrOneBooleanContent);
346 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
347 setStackPointerRegisterToSaveRestore(PPC::X1);
348 setExceptionPointerRegister(PPC::X3);
349 setExceptionSelectorRegister(PPC::X4);
351 setStackPointerRegisterToSaveRestore(PPC::R1);
352 setExceptionPointerRegister(PPC::R3);
353 setExceptionSelectorRegister(PPC::R4);
356 // We have target-specific dag combine patterns for the following nodes:
357 setTargetDAGCombine(ISD::SINT_TO_FP);
358 setTargetDAGCombine(ISD::STORE);
359 setTargetDAGCombine(ISD::BR_CC);
360 setTargetDAGCombine(ISD::BSWAP);
362 // Darwin long double math library functions have $LDBL128 appended.
363 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
364 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
365 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
366 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
367 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
368 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
369 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
370 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
371 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
372 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
373 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
376 computeRegisterProperties();
379 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
380 /// function arguments in the caller parameter area.
381 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
382 TargetMachine &TM = getTargetMachine();
383 // Darwin passes everything on 4 byte boundary.
384 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
390 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
393 case PPCISD::FSEL: return "PPCISD::FSEL";
394 case PPCISD::FCFID: return "PPCISD::FCFID";
395 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
396 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
397 case PPCISD::STFIWX: return "PPCISD::STFIWX";
398 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
399 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
400 case PPCISD::VPERM: return "PPCISD::VPERM";
401 case PPCISD::Hi: return "PPCISD::Hi";
402 case PPCISD::Lo: return "PPCISD::Lo";
403 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
404 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
405 case PPCISD::SRL: return "PPCISD::SRL";
406 case PPCISD::SRA: return "PPCISD::SRA";
407 case PPCISD::SHL: return "PPCISD::SHL";
408 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
409 case PPCISD::STD_32: return "PPCISD::STD_32";
410 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
411 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
412 case PPCISD::MTCTR: return "PPCISD::MTCTR";
413 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
414 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
415 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
416 case PPCISD::MFCR: return "PPCISD::MFCR";
417 case PPCISD::VCMP: return "PPCISD::VCMP";
418 case PPCISD::VCMPo: return "PPCISD::VCMPo";
419 case PPCISD::LBRX: return "PPCISD::LBRX";
420 case PPCISD::STBRX: return "PPCISD::STBRX";
421 case PPCISD::LARX: return "PPCISD::LARX";
422 case PPCISD::STCX: return "PPCISD::STCX";
423 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
424 case PPCISD::MFFS: return "PPCISD::MFFS";
425 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
426 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
427 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
428 case PPCISD::MTFSF: return "PPCISD::MTFSF";
429 case PPCISD::TAILCALL: return "PPCISD::TAILCALL";
430 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
435 MVT PPCTargetLowering::getSetCCResultType(MVT VT) const {
440 //===----------------------------------------------------------------------===//
441 // Node matching predicates, for use by the tblgen matching code.
442 //===----------------------------------------------------------------------===//
444 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
445 static bool isFloatingPointZero(SDValue Op) {
446 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
447 return CFP->getValueAPF().isZero();
448 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
449 // Maybe this has already been legalized into the constant pool?
450 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
451 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
452 return CFP->getValueAPF().isZero();
457 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
458 /// true if Op is undef or if it matches the specified value.
459 static bool isConstantOrUndef(SDValue Op, unsigned Val) {
460 return Op.getOpcode() == ISD::UNDEF ||
461 cast<ConstantSDNode>(Op)->getZExtValue() == Val;
464 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
465 /// VPKUHUM instruction.
466 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
468 for (unsigned i = 0; i != 16; ++i)
469 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
472 for (unsigned i = 0; i != 8; ++i)
473 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
474 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
480 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
481 /// VPKUWUM instruction.
482 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
484 for (unsigned i = 0; i != 16; i += 2)
485 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
486 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
489 for (unsigned i = 0; i != 8; i += 2)
490 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
491 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
492 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
493 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
499 /// isVMerge - Common function, used to match vmrg* shuffles.
501 static bool isVMerge(SDNode *N, unsigned UnitSize,
502 unsigned LHSStart, unsigned RHSStart) {
503 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
504 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
505 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
506 "Unsupported merge size!");
508 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
509 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
510 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
511 LHSStart+j+i*UnitSize) ||
512 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
513 RHSStart+j+i*UnitSize))
519 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
520 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
521 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
523 return isVMerge(N, UnitSize, 8, 24);
524 return isVMerge(N, UnitSize, 8, 8);
527 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
528 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
529 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
531 return isVMerge(N, UnitSize, 0, 16);
532 return isVMerge(N, UnitSize, 0, 0);
536 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
537 /// amount, otherwise return -1.
538 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
539 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
540 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
541 // Find the first non-undef value in the shuffle mask.
543 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
546 if (i == 16) return -1; // all undef.
548 // Otherwise, check to see if the rest of the elements are consequtively
549 // numbered from this value.
550 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getZExtValue();
551 if (ShiftAmt < i) return -1;
555 // Check the rest of the elements to see if they are consequtive.
556 for (++i; i != 16; ++i)
557 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
560 // Check the rest of the elements to see if they are consequtive.
561 for (++i; i != 16; ++i)
562 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
569 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
570 /// specifies a splat of a single element that is suitable for input to
571 /// VSPLTB/VSPLTH/VSPLTW.
572 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
573 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
574 N->getNumOperands() == 16 &&
575 (EltSize == 1 || EltSize == 2 || EltSize == 4));
577 // This is a splat operation if each element of the permute is the same, and
578 // if the value doesn't reference the second vector.
579 unsigned ElementBase = 0;
580 SDValue Elt = N->getOperand(0);
581 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
582 ElementBase = EltV->getZExtValue();
584 return false; // FIXME: Handle UNDEF elements too!
586 if (cast<ConstantSDNode>(Elt)->getZExtValue() >= 16)
589 // Check that they are consequtive.
590 for (unsigned i = 1; i != EltSize; ++i) {
591 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
592 cast<ConstantSDNode>(N->getOperand(i))->getZExtValue() != i+ElementBase)
596 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
597 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
598 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
599 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
600 "Invalid VECTOR_SHUFFLE mask!");
601 for (unsigned j = 0; j != EltSize; ++j)
602 if (N->getOperand(i+j) != N->getOperand(j))
609 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
611 bool PPC::isAllNegativeZeroVector(SDNode *N) {
612 assert(N->getOpcode() == ISD::BUILD_VECTOR);
613 if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
614 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
615 return CFP->getValueAPF().isNegZero();
619 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
620 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
621 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
622 assert(isSplatShuffleMask(N, EltSize));
623 return cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() / EltSize;
626 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
627 /// by using a vspltis[bhw] instruction of the specified element size, return
628 /// the constant being splatted. The ByteSize field indicates the number of
629 /// bytes of each element [124] -> [bhw].
630 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
633 // If ByteSize of the splat is bigger than the element size of the
634 // build_vector, then we have a case where we are checking for a splat where
635 // multiple elements of the buildvector are folded together into a single
636 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
637 unsigned EltSize = 16/N->getNumOperands();
638 if (EltSize < ByteSize) {
639 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
640 SDValue UniquedVals[4];
641 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
643 // See if all of the elements in the buildvector agree across.
644 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
645 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
646 // If the element isn't a constant, bail fully out.
647 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
650 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
651 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
652 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
653 return SDValue(); // no match.
656 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
657 // either constant or undef values that are identical for each chunk. See
658 // if these chunks can form into a larger vspltis*.
660 // Check to see if all of the leading entries are either 0 or -1. If
661 // neither, then this won't fit into the immediate field.
662 bool LeadingZero = true;
663 bool LeadingOnes = true;
664 for (unsigned i = 0; i != Multiple-1; ++i) {
665 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
667 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
668 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
670 // Finally, check the least significant entry.
672 if (UniquedVals[Multiple-1].getNode() == 0)
673 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
674 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
676 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
679 if (UniquedVals[Multiple-1].getNode() == 0)
680 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
681 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
682 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
683 return DAG.getTargetConstant(Val, MVT::i32);
689 // Check to see if this buildvec has a single non-undef value in its elements.
690 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
691 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
692 if (OpVal.getNode() == 0)
693 OpVal = N->getOperand(i);
694 else if (OpVal != N->getOperand(i))
698 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
700 unsigned ValSizeInBytes = 0;
702 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
703 Value = CN->getZExtValue();
704 ValSizeInBytes = CN->getValueType(0).getSizeInBits()/8;
705 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
706 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
707 Value = FloatToBits(CN->getValueAPF().convertToFloat());
711 // If the splat value is larger than the element value, then we can never do
712 // this splat. The only case that we could fit the replicated bits into our
713 // immediate field for would be zero, and we prefer to use vxor for it.
714 if (ValSizeInBytes < ByteSize) return SDValue();
716 // If the element value is larger than the splat value, cut it in half and
717 // check to see if the two halves are equal. Continue doing this until we
718 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
719 while (ValSizeInBytes > ByteSize) {
720 ValSizeInBytes >>= 1;
722 // If the top half equals the bottom half, we're still ok.
723 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
724 (Value & ((1 << (8*ValSizeInBytes))-1)))
728 // Properly sign extend the value.
729 int ShAmt = (4-ByteSize)*8;
730 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
732 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
733 if (MaskVal == 0) return SDValue();
735 // Finally, if this value fits in a 5 bit sext field, return it
736 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
737 return DAG.getTargetConstant(MaskVal, MVT::i32);
741 //===----------------------------------------------------------------------===//
742 // Addressing Mode Selection
743 //===----------------------------------------------------------------------===//
745 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
746 /// or 64-bit immediate, and if the value can be accurately represented as a
747 /// sign extension from a 16-bit value. If so, this returns true and the
749 static bool isIntS16Immediate(SDNode *N, short &Imm) {
750 if (N->getOpcode() != ISD::Constant)
753 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
754 if (N->getValueType(0) == MVT::i32)
755 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
757 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
759 static bool isIntS16Immediate(SDValue Op, short &Imm) {
760 return isIntS16Immediate(Op.getNode(), Imm);
764 /// SelectAddressRegReg - Given the specified addressed, check to see if it
765 /// can be represented as an indexed [r+r] operation. Returns false if it
766 /// can be more efficiently represented with [r+imm].
767 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
769 SelectionDAG &DAG) const {
771 if (N.getOpcode() == ISD::ADD) {
772 if (isIntS16Immediate(N.getOperand(1), imm))
774 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
777 Base = N.getOperand(0);
778 Index = N.getOperand(1);
780 } else if (N.getOpcode() == ISD::OR) {
781 if (isIntS16Immediate(N.getOperand(1), imm))
782 return false; // r+i can fold it if we can.
784 // If this is an or of disjoint bitfields, we can codegen this as an add
785 // (for better address arithmetic) if the LHS and RHS of the OR are provably
787 APInt LHSKnownZero, LHSKnownOne;
788 APInt RHSKnownZero, RHSKnownOne;
789 DAG.ComputeMaskedBits(N.getOperand(0),
790 APInt::getAllOnesValue(N.getOperand(0)
791 .getValueSizeInBits()),
792 LHSKnownZero, LHSKnownOne);
794 if (LHSKnownZero.getBoolValue()) {
795 DAG.ComputeMaskedBits(N.getOperand(1),
796 APInt::getAllOnesValue(N.getOperand(1)
797 .getValueSizeInBits()),
798 RHSKnownZero, RHSKnownOne);
799 // If all of the bits are known zero on the LHS or RHS, the add won't
801 if (~(LHSKnownZero | RHSKnownZero) == 0) {
802 Base = N.getOperand(0);
803 Index = N.getOperand(1);
812 /// Returns true if the address N can be represented by a base register plus
813 /// a signed 16-bit displacement [r+imm], and if it is not better
814 /// represented as reg+reg.
815 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
817 SelectionDAG &DAG) const {
818 // If this can be more profitably realized as r+r, fail.
819 if (SelectAddressRegReg(N, Disp, Base, DAG))
822 if (N.getOpcode() == ISD::ADD) {
824 if (isIntS16Immediate(N.getOperand(1), imm)) {
825 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
826 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
827 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
829 Base = N.getOperand(0);
831 return true; // [r+i]
832 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
833 // Match LOAD (ADD (X, Lo(G))).
834 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
835 && "Cannot handle constant offsets yet!");
836 Disp = N.getOperand(1).getOperand(0); // The global address.
837 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
838 Disp.getOpcode() == ISD::TargetConstantPool ||
839 Disp.getOpcode() == ISD::TargetJumpTable);
840 Base = N.getOperand(0);
841 return true; // [&g+r]
843 } else if (N.getOpcode() == ISD::OR) {
845 if (isIntS16Immediate(N.getOperand(1), imm)) {
846 // If this is an or of disjoint bitfields, we can codegen this as an add
847 // (for better address arithmetic) if the LHS and RHS of the OR are
848 // provably disjoint.
849 APInt LHSKnownZero, LHSKnownOne;
850 DAG.ComputeMaskedBits(N.getOperand(0),
851 APInt::getAllOnesValue(N.getOperand(0)
852 .getValueSizeInBits()),
853 LHSKnownZero, LHSKnownOne);
855 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
856 // If all of the bits are known zero on the LHS or RHS, the add won't
858 Base = N.getOperand(0);
859 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
863 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
864 // Loading from a constant address.
866 // If this address fits entirely in a 16-bit sext immediate field, codegen
869 if (isIntS16Immediate(CN, Imm)) {
870 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
871 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
875 // Handle 32-bit sext immediates with LIS + addr mode.
876 if (CN->getValueType(0) == MVT::i32 ||
877 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
878 int Addr = (int)CN->getZExtValue();
880 // Otherwise, break this down into an LIS + disp.
881 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
883 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
884 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
885 Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
890 Disp = DAG.getTargetConstant(0, getPointerTy());
891 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
892 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
895 return true; // [r+0]
898 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
899 /// represented as an indexed [r+r] operation.
900 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
902 SelectionDAG &DAG) const {
903 // Check to see if we can easily represent this as an [r+r] address. This
904 // will fail if it thinks that the address is more profitably represented as
905 // reg+imm, e.g. where imm = 0.
906 if (SelectAddressRegReg(N, Base, Index, DAG))
909 // If the operand is an addition, always emit this as [r+r], since this is
910 // better (for code size, and execution, as the memop does the add for free)
911 // than emitting an explicit add.
912 if (N.getOpcode() == ISD::ADD) {
913 Base = N.getOperand(0);
914 Index = N.getOperand(1);
918 // Otherwise, do it the hard way, using R0 as the base register.
919 Base = DAG.getRegister(PPC::R0, N.getValueType());
924 /// SelectAddressRegImmShift - Returns true if the address N can be
925 /// represented by a base register plus a signed 14-bit displacement
926 /// [r+imm*4]. Suitable for use by STD and friends.
927 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
929 SelectionDAG &DAG) const {
930 // If this can be more profitably realized as r+r, fail.
931 if (SelectAddressRegReg(N, Disp, Base, DAG))
934 if (N.getOpcode() == ISD::ADD) {
936 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
937 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
938 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
939 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
941 Base = N.getOperand(0);
943 return true; // [r+i]
944 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
945 // Match LOAD (ADD (X, Lo(G))).
946 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
947 && "Cannot handle constant offsets yet!");
948 Disp = N.getOperand(1).getOperand(0); // The global address.
949 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
950 Disp.getOpcode() == ISD::TargetConstantPool ||
951 Disp.getOpcode() == ISD::TargetJumpTable);
952 Base = N.getOperand(0);
953 return true; // [&g+r]
955 } else if (N.getOpcode() == ISD::OR) {
957 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
958 // If this is an or of disjoint bitfields, we can codegen this as an add
959 // (for better address arithmetic) if the LHS and RHS of the OR are
960 // provably disjoint.
961 APInt LHSKnownZero, LHSKnownOne;
962 DAG.ComputeMaskedBits(N.getOperand(0),
963 APInt::getAllOnesValue(N.getOperand(0)
964 .getValueSizeInBits()),
965 LHSKnownZero, LHSKnownOne);
966 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
967 // If all of the bits are known zero on the LHS or RHS, the add won't
969 Base = N.getOperand(0);
970 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
974 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
975 // Loading from a constant address. Verify low two bits are clear.
976 if ((CN->getZExtValue() & 3) == 0) {
977 // If this address fits entirely in a 14-bit sext immediate field, codegen
980 if (isIntS16Immediate(CN, Imm)) {
981 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
982 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
986 // Fold the low-part of 32-bit absolute addresses into addr mode.
987 if (CN->getValueType(0) == MVT::i32 ||
988 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
989 int Addr = (int)CN->getZExtValue();
991 // Otherwise, break this down into an LIS + disp.
992 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
994 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
995 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
996 Base = SDValue(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
1002 Disp = DAG.getTargetConstant(0, getPointerTy());
1003 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1004 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1007 return true; // [r+0]
1011 /// getPreIndexedAddressParts - returns true by value, base pointer and
1012 /// offset pointer and addressing mode by reference if the node's address
1013 /// can be legally represented as pre-indexed load / store address.
1014 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1016 ISD::MemIndexedMode &AM,
1017 SelectionDAG &DAG) const {
1018 // Disabled by default for now.
1019 if (!EnablePPCPreinc) return false;
1023 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1024 Ptr = LD->getBasePtr();
1025 VT = LD->getMemoryVT();
1027 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1029 Ptr = ST->getBasePtr();
1030 VT = ST->getMemoryVT();
1034 // PowerPC doesn't have preinc load/store instructions for vectors.
1038 // TODO: Check reg+reg first.
1040 // LDU/STU use reg+imm*4, others use reg+imm.
1041 if (VT != MVT::i64) {
1043 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1047 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1051 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1052 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1053 // sext i32 to i64 when addr mode is r+i.
1054 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1055 LD->getExtensionType() == ISD::SEXTLOAD &&
1056 isa<ConstantSDNode>(Offset))
1064 //===----------------------------------------------------------------------===//
1065 // LowerOperation implementation
1066 //===----------------------------------------------------------------------===//
1068 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1069 SelectionDAG &DAG) {
1070 MVT PtrVT = Op.getValueType();
1071 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1072 Constant *C = CP->getConstVal();
1073 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1074 SDValue Zero = DAG.getConstant(0, PtrVT);
1076 const TargetMachine &TM = DAG.getTarget();
1078 SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
1079 SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
1081 // If this is a non-darwin platform, we don't support non-static relo models
1083 if (TM.getRelocationModel() == Reloc::Static ||
1084 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1085 // Generate non-pic code that has direct accesses to the constant pool.
1086 // The address of the global is just (hi(&g)+lo(&g)).
1087 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1090 if (TM.getRelocationModel() == Reloc::PIC_) {
1091 // With PIC, the first instruction is actually "GR+hi(&G)".
1092 Hi = DAG.getNode(ISD::ADD, PtrVT,
1093 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1096 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1100 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) {
1101 MVT PtrVT = Op.getValueType();
1102 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1103 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1104 SDValue Zero = DAG.getConstant(0, PtrVT);
1106 const TargetMachine &TM = DAG.getTarget();
1108 SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
1109 SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
1111 // If this is a non-darwin platform, we don't support non-static relo models
1113 if (TM.getRelocationModel() == Reloc::Static ||
1114 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1115 // Generate non-pic code that has direct accesses to the constant pool.
1116 // The address of the global is just (hi(&g)+lo(&g)).
1117 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1120 if (TM.getRelocationModel() == Reloc::PIC_) {
1121 // With PIC, the first instruction is actually "GR+hi(&G)".
1122 Hi = DAG.getNode(ISD::ADD, PtrVT,
1123 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1126 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1130 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1131 SelectionDAG &DAG) {
1132 assert(0 && "TLS not implemented for PPC.");
1133 return SDValue(); // Not reached
1136 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1137 SelectionDAG &DAG) {
1138 MVT PtrVT = Op.getValueType();
1139 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1140 GlobalValue *GV = GSDN->getGlobal();
1141 SDValue GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1142 SDValue Zero = DAG.getConstant(0, PtrVT);
1144 const TargetMachine &TM = DAG.getTarget();
1146 SDValue Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
1147 SDValue Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
1149 // If this is a non-darwin platform, we don't support non-static relo models
1151 if (TM.getRelocationModel() == Reloc::Static ||
1152 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1153 // Generate non-pic code that has direct accesses to globals.
1154 // The address of the global is just (hi(&g)+lo(&g)).
1155 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1158 if (TM.getRelocationModel() == Reloc::PIC_) {
1159 // With PIC, the first instruction is actually "GR+hi(&G)".
1160 Hi = DAG.getNode(ISD::ADD, PtrVT,
1161 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1164 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1166 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1169 // If the global is weak or external, we have to go through the lazy
1171 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
1174 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) {
1175 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1177 // If we're comparing for equality to zero, expose the fact that this is
1178 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1179 // fold the new nodes.
1180 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1181 if (C->isNullValue() && CC == ISD::SETEQ) {
1182 MVT VT = Op.getOperand(0).getValueType();
1183 SDValue Zext = Op.getOperand(0);
1184 if (VT.bitsLT(MVT::i32)) {
1186 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1188 unsigned Log2b = Log2_32(VT.getSizeInBits());
1189 SDValue Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1190 SDValue Scc = DAG.getNode(ISD::SRL, VT, Clz,
1191 DAG.getConstant(Log2b, MVT::i32));
1192 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1194 // Leave comparisons against 0 and -1 alone for now, since they're usually
1195 // optimized. FIXME: revisit this when we can custom lower all setcc
1197 if (C->isAllOnesValue() || C->isNullValue())
1201 // If we have an integer seteq/setne, turn it into a compare against zero
1202 // by xor'ing the rhs with the lhs, which is faster than setting a
1203 // condition register, reading it back out, and masking the correct bit. The
1204 // normal approach here uses sub to do this instead of xor. Using xor exposes
1205 // the result to other bit-twiddling opportunities.
1206 MVT LHSVT = Op.getOperand(0).getValueType();
1207 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1208 MVT VT = Op.getValueType();
1209 SDValue Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
1211 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1216 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1217 int VarArgsFrameIndex,
1218 int VarArgsStackOffset,
1219 unsigned VarArgsNumGPR,
1220 unsigned VarArgsNumFPR,
1221 const PPCSubtarget &Subtarget) {
1223 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1224 return SDValue(); // Not reached
1227 SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) {
1228 SDValue Chain = Op.getOperand(0);
1229 SDValue Trmp = Op.getOperand(1); // trampoline
1230 SDValue FPtr = Op.getOperand(2); // nested function
1231 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1232 DebugLoc dl = Op.getNode()->getDebugLoc();
1234 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1235 bool isPPC64 = (PtrVT == MVT::i64);
1236 const Type *IntPtrTy =
1237 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType();
1239 TargetLowering::ArgListTy Args;
1240 TargetLowering::ArgListEntry Entry;
1242 Entry.Ty = IntPtrTy;
1243 Entry.Node = Trmp; Args.push_back(Entry);
1245 // TrampSize == (isPPC64 ? 48 : 40);
1246 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1247 isPPC64 ? MVT::i64 : MVT::i32);
1248 Args.push_back(Entry);
1250 Entry.Node = FPtr; Args.push_back(Entry);
1251 Entry.Node = Nest; Args.push_back(Entry);
1253 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1254 std::pair<SDValue, SDValue> CallResult =
1255 LowerCallTo(Chain, Op.getValueType().getTypeForMVT(), false, false,
1256 false, false, CallingConv::C, false,
1257 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1261 { CallResult.first, CallResult.second };
1263 return DAG.getMergeValues(Ops, 2);
1266 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1267 int VarArgsFrameIndex,
1268 int VarArgsStackOffset,
1269 unsigned VarArgsNumGPR,
1270 unsigned VarArgsNumFPR,
1271 const PPCSubtarget &Subtarget) {
1273 if (Subtarget.isMachoABI()) {
1274 // vastart just stores the address of the VarArgsFrameIndex slot into the
1275 // memory location argument.
1276 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1277 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1278 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1279 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
1282 // For ELF 32 ABI we follow the layout of the va_list struct.
1283 // We suppose the given va_list is already allocated.
1286 // char gpr; /* index into the array of 8 GPRs
1287 // * stored in the register save area
1288 // * gpr=0 corresponds to r3,
1289 // * gpr=1 to r4, etc.
1291 // char fpr; /* index into the array of 8 FPRs
1292 // * stored in the register save area
1293 // * fpr=0 corresponds to f1,
1294 // * fpr=1 to f2, etc.
1296 // char *overflow_arg_area;
1297 // /* location on stack that holds
1298 // * the next overflow argument
1300 // char *reg_save_area;
1301 // /* where r3:r10 and f1:f8 (if saved)
1307 SDValue ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1308 SDValue ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1311 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1313 SDValue StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1314 SDValue FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1316 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1317 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1319 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1320 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1322 uint64_t FPROffset = 1;
1323 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1325 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1327 // Store first byte : number of int regs
1328 SDValue firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
1329 Op.getOperand(1), SV, 0);
1330 uint64_t nextOffset = FPROffset;
1331 SDValue nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
1334 // Store second byte : number of float regs
1335 SDValue secondStore =
1336 DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset);
1337 nextOffset += StackOffset;
1338 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
1340 // Store second word : arguments given on stack
1341 SDValue thirdStore =
1342 DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset);
1343 nextOffset += FrameOffset;
1344 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
1346 // Store third word : arguments given in registers
1347 return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset);
1351 #include "PPCGenCallingConv.inc"
1353 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1354 /// depending on which subtarget is selected.
1355 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1356 if (Subtarget.isMachoABI()) {
1357 static const unsigned FPR[] = {
1358 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1359 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1365 static const unsigned FPR[] = {
1366 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1372 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1374 static unsigned CalculateStackSlotSize(SDValue Arg, ISD::ArgFlagsTy Flags,
1375 bool isVarArg, unsigned PtrByteSize) {
1376 MVT ArgVT = Arg.getValueType();
1377 unsigned ArgSize =ArgVT.getSizeInBits()/8;
1378 if (Flags.isByVal())
1379 ArgSize = Flags.getByValSize();
1380 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1386 PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
1388 int &VarArgsFrameIndex,
1389 int &VarArgsStackOffset,
1390 unsigned &VarArgsNumGPR,
1391 unsigned &VarArgsNumFPR,
1392 const PPCSubtarget &Subtarget) {
1393 // TODO: add description of PPC stack frame format, or at least some docs.
1395 MachineFunction &MF = DAG.getMachineFunction();
1396 MachineFrameInfo *MFI = MF.getFrameInfo();
1397 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1398 SmallVector<SDValue, 8> ArgValues;
1399 SDValue Root = Op.getOperand(0);
1400 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
1402 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1403 bool isPPC64 = PtrVT == MVT::i64;
1404 bool isMachoABI = Subtarget.isMachoABI();
1405 bool isELF32_ABI = Subtarget.isELF32_ABI();
1406 // Potential tail calls could cause overwriting of argument stack slots.
1407 unsigned CC = MF.getFunction()->getCallingConv();
1408 bool isImmutable = !(PerformTailCallOpt && (CC==CallingConv::Fast));
1409 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1411 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1412 // Area that is at least reserved in caller of this function.
1413 unsigned MinReservedArea = ArgOffset;
1415 static const unsigned GPR_32[] = { // 32-bit registers.
1416 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1417 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1419 static const unsigned GPR_64[] = { // 64-bit registers.
1420 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1421 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1424 static const unsigned *FPR = GetFPR(Subtarget);
1426 static const unsigned VR[] = {
1427 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1428 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1431 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1432 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
1433 const unsigned Num_VR_Regs = array_lengthof( VR);
1435 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1437 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1439 // In 32-bit non-varargs functions, the stack space for vectors is after the
1440 // stack space for non-vectors. We do not use this space unless we have
1441 // too many vectors to fit in registers, something that only occurs in
1442 // constructed examples:), but we have to walk the arglist to figure
1443 // that out...for the pathological case, compute VecArgOffset as the
1444 // start of the vector parameter area. Computing VecArgOffset is the
1445 // entire point of the following loop.
1446 // Altivec is not mentioned in the ppc32 Elf Supplement, so I'm not trying
1447 // to handle Elf here.
1448 unsigned VecArgOffset = ArgOffset;
1449 if (!isVarArg && !isPPC64) {
1450 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e;
1452 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
1453 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1454 ISD::ArgFlagsTy Flags =
1455 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
1457 if (Flags.isByVal()) {
1458 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1459 ObjSize = Flags.getByValSize();
1461 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1462 VecArgOffset += ArgSize;
1466 switch(ObjectVT.getSimpleVT()) {
1467 default: assert(0 && "Unhandled argument type!");
1470 VecArgOffset += isPPC64 ? 8 : 4;
1472 case MVT::i64: // PPC64
1480 // Nothing to do, we're only looking at Nonvector args here.
1485 // We've found where the vector parameter area in memory is. Skip the
1486 // first 12 parameters; these don't use that memory.
1487 VecArgOffset = ((VecArgOffset+15)/16)*16;
1488 VecArgOffset += 12*16;
1490 // Add DAG nodes to load the arguments or copy them out of registers. On
1491 // entry to a function on PPC, the arguments start after the linkage area,
1492 // although the first ones are often in registers.
1494 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
1495 // represented with two words (long long or double) must be copied to an
1496 // even GPR_idx value or to an even ArgOffset value.
1498 SmallVector<SDValue, 8> MemOps;
1499 unsigned nAltivecParamsAtEnd = 0;
1500 for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues() - 1;
1501 ArgNo != e; ++ArgNo) {
1503 bool needsLoad = false;
1504 MVT ObjectVT = Op.getValue(ArgNo).getValueType();
1505 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1506 unsigned ArgSize = ObjSize;
1507 ISD::ArgFlagsTy Flags =
1508 cast<ARG_FLAGSSDNode>(Op.getOperand(ArgNo+3))->getArgFlags();
1509 // See if next argument requires stack alignment in ELF
1510 bool Align = Flags.isSplit();
1512 unsigned CurArgOffset = ArgOffset;
1514 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1515 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1516 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1517 if (isVarArg || isPPC64) {
1518 MinReservedArea = ((MinReservedArea+15)/16)*16;
1519 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
1523 } else nAltivecParamsAtEnd++;
1525 // Calculate min reserved area.
1526 MinReservedArea += CalculateStackSlotSize(Op.getValue(ArgNo),
1531 // FIXME alignment for ELF may not be right
1532 // FIXME the codegen can be much improved in some cases.
1533 // We do not have to keep everything in memory.
1534 if (Flags.isByVal()) {
1535 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1536 ObjSize = Flags.getByValSize();
1537 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1538 // Double word align in ELF
1539 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1540 // Objects of size 1 and 2 are right justified, everything else is
1541 // left justified. This means the memory address is adjusted forwards.
1542 if (ObjSize==1 || ObjSize==2) {
1543 CurArgOffset = CurArgOffset + (4 - ObjSize);
1545 // The value of the object is its address.
1546 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
1547 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1548 ArgValues.push_back(FIN);
1549 if (ObjSize==1 || ObjSize==2) {
1550 if (GPR_idx != Num_GPR_Regs) {
1551 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1552 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1553 SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1554 SDValue Store = DAG.getTruncStore(Val.getValue(1), Val, FIN,
1555 NULL, 0, ObjSize==1 ? MVT::i8 : MVT::i16 );
1556 MemOps.push_back(Store);
1558 if (isMachoABI) ArgOffset += PtrByteSize;
1560 ArgOffset += PtrByteSize;
1564 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1565 // Store whatever pieces of the object are in registers
1566 // to memory. ArgVal will be address of the beginning of
1568 if (GPR_idx != Num_GPR_Regs) {
1569 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1570 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1571 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset);
1572 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1573 SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1574 SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1575 MemOps.push_back(Store);
1577 if (isMachoABI) ArgOffset += PtrByteSize;
1579 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1586 switch (ObjectVT.getSimpleVT()) {
1587 default: assert(0 && "Unhandled argument type!");
1590 // Double word align in ELF
1591 if (Align && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1593 if (GPR_idx != Num_GPR_Regs) {
1594 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1595 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1596 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1600 ArgSize = PtrByteSize;
1602 // Stack align in ELF
1603 if (needsLoad && Align && isELF32_ABI)
1604 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1605 // All int arguments reserve stack space in Macho ABI.
1606 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1610 case MVT::i64: // PPC64
1611 if (GPR_idx != Num_GPR_Regs) {
1612 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1613 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1614 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1616 if (ObjectVT == MVT::i32) {
1617 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1618 // value to MVT::i64 and then truncate to the correct register size.
1620 ArgVal = DAG.getNode(ISD::AssertSext, MVT::i64, ArgVal,
1621 DAG.getValueType(ObjectVT));
1622 else if (Flags.isZExt())
1623 ArgVal = DAG.getNode(ISD::AssertZext, MVT::i64, ArgVal,
1624 DAG.getValueType(ObjectVT));
1626 ArgVal = DAG.getNode(ISD::TRUNCATE, MVT::i32, ArgVal);
1632 ArgSize = PtrByteSize;
1634 // All int arguments reserve stack space in Macho ABI.
1635 if (isMachoABI || needsLoad) ArgOffset += 8;
1640 // Every 4 bytes of argument space consumes one of the GPRs available for
1641 // argument passing.
1642 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
1644 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1647 if (FPR_idx != Num_FPR_Regs) {
1649 if (ObjectVT == MVT::f32)
1650 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass);
1652 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1653 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1654 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1660 // Stack align in ELF
1661 if (needsLoad && Align && isELF32_ABI)
1662 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1663 // All FP arguments reserve stack space in Macho ABI.
1664 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
1670 // Note that vector arguments in registers don't reserve stack space,
1671 // except in varargs functions.
1672 if (VR_idx != Num_VR_Regs) {
1673 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass);
1674 RegInfo.addLiveIn(VR[VR_idx], VReg);
1675 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1677 while ((ArgOffset % 16) != 0) {
1678 ArgOffset += PtrByteSize;
1679 if (GPR_idx != Num_GPR_Regs)
1683 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs);
1687 if (!isVarArg && !isPPC64) {
1688 // Vectors go after all the nonvectors.
1689 CurArgOffset = VecArgOffset;
1692 // Vectors are aligned.
1693 ArgOffset = ((ArgOffset+15)/16)*16;
1694 CurArgOffset = ArgOffset;
1702 // We need to load the argument to a virtual register if we determined above
1703 // that we ran out of physical registers of the appropriate type.
1705 int FI = MFI->CreateFixedObject(ObjSize,
1706 CurArgOffset + (ArgSize - ObjSize),
1708 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1709 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1712 ArgValues.push_back(ArgVal);
1715 // Set the size that is at least reserved in caller of this function. Tail
1716 // call optimized function's reserved stack space needs to be aligned so that
1717 // taking the difference between two stack areas will result in an aligned
1719 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1720 // Add the Altivec parameters at the end, if needed.
1721 if (nAltivecParamsAtEnd) {
1722 MinReservedArea = ((MinReservedArea+15)/16)*16;
1723 MinReservedArea += 16*nAltivecParamsAtEnd;
1726 std::max(MinReservedArea,
1727 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1728 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1729 getStackAlignment();
1730 unsigned AlignMask = TargetAlign-1;
1731 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1732 FI->setMinReservedArea(MinReservedArea);
1734 // If the function takes variable number of arguments, make a frame index for
1735 // the start of the first vararg value... for expansion of llvm.va_start.
1740 VarArgsNumGPR = GPR_idx;
1741 VarArgsNumFPR = FPR_idx;
1743 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1745 depth = -(Num_GPR_Regs * PtrVT.getSizeInBits()/8 +
1746 Num_FPR_Regs * MVT(MVT::f64).getSizeInBits()/8 +
1747 PtrVT.getSizeInBits()/8);
1749 VarArgsStackOffset = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1756 VarArgsFrameIndex = MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1758 SDValue FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1760 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1761 // stored to the VarArgsFrameIndex on the stack.
1763 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1764 SDValue Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1765 SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1766 MemOps.push_back(Store);
1767 // Increment the address by four for the next argument to store
1768 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1769 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1773 // If this function is vararg, store any remaining integer argument regs
1774 // to their spots on the stack so that they may be loaded by deferencing the
1775 // result of va_next.
1776 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1779 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1781 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1783 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1784 SDValue Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1785 SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1786 MemOps.push_back(Store);
1787 // Increment the address by four for the next argument to store
1788 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1789 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1792 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1795 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1796 SDValue Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1797 SDValue Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1798 MemOps.push_back(Store);
1799 // Increment the address by eight for the next argument to store
1800 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
1802 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1805 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1807 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1809 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1810 SDValue Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
1811 SDValue Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1812 MemOps.push_back(Store);
1813 // Increment the address by eight for the next argument to store
1814 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
1816 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1821 if (!MemOps.empty())
1822 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1824 ArgValues.push_back(Root);
1826 // Return the new list of results.
1827 return DAG.getNode(ISD::MERGE_VALUES, Op.getNode()->getVTList(),
1828 &ArgValues[0], ArgValues.size());
1831 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
1834 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
1839 CallSDNode *TheCall,
1840 unsigned &nAltivecParamsAtEnd) {
1841 // Count how many bytes are to be pushed on the stack, including the linkage
1842 // area, and parameter passing area. We start with 24/48 bytes, which is
1843 // prereserved space for [SP][CR][LR][3 x unused].
1844 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1845 unsigned NumOps = TheCall->getNumArgs();
1846 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1848 // Add up all the space actually used.
1849 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
1850 // they all go in registers, but we must reserve stack space for them for
1851 // possible use by the caller. In varargs or 64-bit calls, parameters are
1852 // assigned stack space in order, with padding so Altivec parameters are
1854 nAltivecParamsAtEnd = 0;
1855 for (unsigned i = 0; i != NumOps; ++i) {
1856 SDValue Arg = TheCall->getArg(i);
1857 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1858 MVT ArgVT = Arg.getValueType();
1859 // Varargs Altivec parameters are padded to a 16 byte boundary.
1860 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
1861 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
1862 if (!isVarArg && !isPPC64) {
1863 // Non-varargs Altivec parameters go after all the non-Altivec
1864 // parameters; handle those later so we know how much padding we need.
1865 nAltivecParamsAtEnd++;
1868 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
1869 NumBytes = ((NumBytes+15)/16)*16;
1871 NumBytes += CalculateStackSlotSize(Arg, Flags, isVarArg, PtrByteSize);
1874 // Allow for Altivec parameters at the end, if needed.
1875 if (nAltivecParamsAtEnd) {
1876 NumBytes = ((NumBytes+15)/16)*16;
1877 NumBytes += 16*nAltivecParamsAtEnd;
1880 // The prolog code of the callee may store up to 8 GPR argument registers to
1881 // the stack, allowing va_start to index over them in memory if its varargs.
1882 // Because we cannot tell if this is needed on the caller side, we have to
1883 // conservatively assume that it is needed. As such, make sure we have at
1884 // least enough stack space for the caller to store the 8 GPRs.
1885 NumBytes = std::max(NumBytes,
1886 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1888 // Tail call needs the stack to be aligned.
1889 if (CC==CallingConv::Fast && PerformTailCallOpt) {
1890 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1891 getStackAlignment();
1892 unsigned AlignMask = TargetAlign-1;
1893 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
1899 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
1900 /// adjusted to accomodate the arguments for the tailcall.
1901 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool IsTailCall,
1902 unsigned ParamSize) {
1904 if (!IsTailCall) return 0;
1906 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
1907 unsigned CallerMinReservedArea = FI->getMinReservedArea();
1908 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
1909 // Remember only if the new adjustement is bigger.
1910 if (SPDiff < FI->getTailCallSPDelta())
1911 FI->setTailCallSPDelta(SPDiff);
1916 /// IsEligibleForTailCallElimination - Check to see whether the next instruction
1917 /// following the call is a return. A function is eligible if caller/callee
1918 /// calling conventions match, currently only fastcc supports tail calls, and
1919 /// the function CALL is immediatly followed by a RET.
1921 PPCTargetLowering::IsEligibleForTailCallOptimization(CallSDNode *TheCall,
1923 SelectionDAG& DAG) const {
1924 // Variable argument functions are not supported.
1925 if (!PerformTailCallOpt || TheCall->isVarArg())
1928 if (CheckTailCallReturnConstraints(TheCall, Ret)) {
1929 MachineFunction &MF = DAG.getMachineFunction();
1930 unsigned CallerCC = MF.getFunction()->getCallingConv();
1931 unsigned CalleeCC = TheCall->getCallingConv();
1932 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
1933 // Functions containing by val parameters are not supported.
1934 for (unsigned i = 0; i != TheCall->getNumArgs(); i++) {
1935 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
1936 if (Flags.isByVal()) return false;
1939 SDValue Callee = TheCall->getCallee();
1940 // Non PIC/GOT tail calls are supported.
1941 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
1944 // At the moment we can only do local tail calls (in same module, hidden
1945 // or protected) if we are generating PIC.
1946 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1947 return G->getGlobal()->hasHiddenVisibility()
1948 || G->getGlobal()->hasProtectedVisibility();
1955 /// isCallCompatibleAddress - Return the immediate to use if the specified
1956 /// 32-bit value is representable in the immediate field of a BxA instruction.
1957 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
1958 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1961 int Addr = C->getZExtValue();
1962 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1963 (Addr << 6 >> 6) != Addr)
1964 return 0; // Top 6 bits have to be sext of immediate.
1966 return DAG.getConstant((int)C->getZExtValue() >> 2,
1967 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
1972 struct TailCallArgumentInfo {
1977 TailCallArgumentInfo() : FrameIdx(0) {}
1982 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
1984 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
1986 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
1987 SmallVector<SDValue, 8> &MemOpChains) {
1988 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
1989 SDValue Arg = TailCallArgs[i].Arg;
1990 SDValue FIN = TailCallArgs[i].FrameIdxOp;
1991 int FI = TailCallArgs[i].FrameIdx;
1992 // Store relative to framepointer.
1993 MemOpChains.push_back(DAG.getStore(Chain, Arg, FIN,
1994 PseudoSourceValue::getFixedStack(FI),
1999 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2000 /// the appropriate stack slot for the tail call optimized function call.
2001 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2002 MachineFunction &MF,
2010 // Calculate the new stack slot for the return address.
2011 int SlotSize = isPPC64 ? 8 : 4;
2012 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
2014 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2016 int NewFPLoc = SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64,
2018 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc);
2020 MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2021 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2022 Chain = DAG.getStore(Chain, OldRetAddr, NewRetAddrFrIdx,
2023 PseudoSourceValue::getFixedStack(NewRetAddr), 0);
2024 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2025 Chain = DAG.getStore(Chain, OldFP, NewFramePtrIdx,
2026 PseudoSourceValue::getFixedStack(NewFPIdx), 0);
2031 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2032 /// the position of the argument.
2034 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2035 SDValue Arg, int SPDiff, unsigned ArgOffset,
2036 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2037 int Offset = ArgOffset + SPDiff;
2038 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2039 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset);
2040 MVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2041 SDValue FIN = DAG.getFrameIndex(FI, VT);
2042 TailCallArgumentInfo Info;
2044 Info.FrameIdxOp = FIN;
2046 TailCallArguments.push_back(Info);
2049 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2050 /// stack slot. Returns the chain as result and the loaded frame pointers in
2051 /// LROpOut/FPOpout. Used when tail calling.
2052 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2058 // Load the LR and FP stack slot for later adjusting.
2059 MVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2060 LROpOut = getReturnAddrFrameIndex(DAG);
2061 LROpOut = DAG.getLoad(VT, Chain, LROpOut, NULL, 0);
2062 Chain = SDValue(LROpOut.getNode(), 1);
2063 FPOpOut = getFramePointerFrameIndex(DAG);
2064 FPOpOut = DAG.getLoad(VT, Chain, FPOpOut, NULL, 0);
2065 Chain = SDValue(FPOpOut.getNode(), 1);
2070 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2071 /// by "Src" to address "Dst" of size "Size". Alignment information is
2072 /// specified by the specific parameter attribute. The copy will be passed as
2073 /// a byval function parameter.
2074 /// Sometimes what we are copying is the end of a larger object, the part that
2075 /// does not fit in registers.
2077 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2078 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2080 SDValue SizeNode = DAG.getConstant(Size, MVT::i32);
2081 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, Flags.getByValAlign(), false,
2085 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2088 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2089 SDValue Arg, SDValue PtrOff, int SPDiff,
2090 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2091 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2092 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2093 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2098 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2100 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2101 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr,
2102 DAG.getConstant(ArgOffset, PtrVT));
2104 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
2105 // Calculate and remember argument location.
2106 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2110 SDValue PPCTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG,
2111 const PPCSubtarget &Subtarget,
2112 TargetMachine &TM) {
2113 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
2114 SDValue Chain = TheCall->getChain();
2115 bool isVarArg = TheCall->isVarArg();
2116 unsigned CC = TheCall->getCallingConv();
2117 bool isTailCall = TheCall->isTailCall()
2118 && CC == CallingConv::Fast && PerformTailCallOpt;
2119 SDValue Callee = TheCall->getCallee();
2120 unsigned NumOps = TheCall->getNumArgs();
2122 bool isMachoABI = Subtarget.isMachoABI();
2123 bool isELF32_ABI = Subtarget.isELF32_ABI();
2125 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2126 bool isPPC64 = PtrVT == MVT::i64;
2127 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2129 MachineFunction &MF = DAG.getMachineFunction();
2131 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
2132 // SelectExpr to use to put the arguments in the appropriate registers.
2133 std::vector<SDValue> args_to_use;
2135 // Mark this function as potentially containing a function that contains a
2136 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2137 // and restoring the callers stack pointer in this functions epilog. This is
2138 // done because by tail calling the called function might overwrite the value
2139 // in this function's (MF) stack pointer stack slot 0(SP).
2140 if (PerformTailCallOpt && CC==CallingConv::Fast)
2141 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2143 unsigned nAltivecParamsAtEnd = 0;
2145 // Count how many bytes are to be pushed on the stack, including the linkage
2146 // area, and parameter passing area. We start with 24/48 bytes, which is
2147 // prereserved space for [SP][CR][LR][3 x unused].
2149 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isMachoABI, isVarArg, CC,
2150 TheCall, nAltivecParamsAtEnd);
2152 // Calculate by how many bytes the stack has to be adjusted in case of tail
2153 // call optimization.
2154 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2156 // Adjust the stack pointer for the new arguments...
2157 // These operations are automatically eliminated by the prolog/epilog pass
2158 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2159 SDValue CallSeqStart = Chain;
2161 // Load the return address and frame pointer so it can be move somewhere else
2164 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp);
2166 // Set up a copy of the stack pointer for use loading and storing any
2167 // arguments that may not fit in the registers available for argument
2171 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2173 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2175 // Figure out which arguments are going to go in registers, and which in
2176 // memory. Also, if this is a vararg function, floating point operations
2177 // must be stored to our stack, and loaded into integer regs as well, if
2178 // any integer regs are available for argument passing.
2179 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
2180 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2182 static const unsigned GPR_32[] = { // 32-bit registers.
2183 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2184 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2186 static const unsigned GPR_64[] = { // 64-bit registers.
2187 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2188 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2190 static const unsigned *FPR = GetFPR(Subtarget);
2192 static const unsigned VR[] = {
2193 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2194 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2196 const unsigned NumGPRs = array_lengthof(GPR_32);
2197 const unsigned NumFPRs = isMachoABI ? 13 : 8;
2198 const unsigned NumVRs = array_lengthof( VR);
2200 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
2202 std::vector<std::pair<unsigned, SDValue> > RegsToPass;
2203 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2205 SmallVector<SDValue, 8> MemOpChains;
2206 for (unsigned i = 0; i != NumOps; ++i) {
2208 SDValue Arg = TheCall->getArg(i);
2209 ISD::ArgFlagsTy Flags = TheCall->getArgFlags(i);
2210 // See if next argument requires stack alignment in ELF
2211 bool Align = Flags.isSplit();
2213 // PtrOff will be used to store the current argument to the stack if a
2214 // register cannot be found for it.
2217 // Stack align in ELF 32
2218 if (isELF32_ABI && Align)
2219 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
2220 StackPtr.getValueType());
2222 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
2224 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
2226 // On PPC64, promote integers to 64-bit values.
2227 if (isPPC64 && Arg.getValueType() == MVT::i32) {
2228 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
2229 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
2230 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
2233 // FIXME Elf untested, what are alignment rules?
2234 // FIXME memcpy is used way more than necessary. Correctness first.
2235 if (Flags.isByVal()) {
2236 unsigned Size = Flags.getByValSize();
2237 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2);
2238 if (Size==1 || Size==2) {
2239 // Very small objects are passed right-justified.
2240 // Everything else is passed left-justified.
2241 MVT VT = (Size==1) ? MVT::i8 : MVT::i16;
2242 if (GPR_idx != NumGPRs) {
2243 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg,
2245 MemOpChains.push_back(Load.getValue(1));
2246 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2248 ArgOffset += PtrByteSize;
2250 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
2251 SDValue AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const);
2252 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
2253 CallSeqStart.getNode()->getOperand(0),
2255 // This must go outside the CALLSEQ_START..END.
2256 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2257 CallSeqStart.getNode()->getOperand(1));
2258 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2259 NewCallSeqStart.getNode());
2260 Chain = CallSeqStart = NewCallSeqStart;
2261 ArgOffset += PtrByteSize;
2265 // Copy entire object into memory. There are cases where gcc-generated
2266 // code assumes it is there, even if it could be put entirely into
2267 // registers. (This is not what the doc says.)
2268 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
2269 CallSeqStart.getNode()->getOperand(0),
2271 // This must go outside the CALLSEQ_START..END.
2272 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2273 CallSeqStart.getNode()->getOperand(1));
2274 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
2275 Chain = CallSeqStart = NewCallSeqStart;
2276 // And copy the pieces of it that fit into registers.
2277 for (unsigned j=0; j<Size; j+=PtrByteSize) {
2278 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
2279 SDValue AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const);
2280 if (GPR_idx != NumGPRs) {
2281 SDValue Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0);
2282 MemOpChains.push_back(Load.getValue(1));
2283 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2285 ArgOffset += PtrByteSize;
2287 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
2294 switch (Arg.getValueType().getSimpleVT()) {
2295 default: assert(0 && "Unexpected ValueType for argument!");
2298 // Double word align in ELF
2299 if (isELF32_ABI && Align) GPR_idx += (GPR_idx % 2);
2300 if (GPR_idx != NumGPRs) {
2301 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
2303 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2304 isPPC64, isTailCall, false, MemOpChains,
2308 if (inMem || isMachoABI) {
2309 // Stack align in ELF
2310 if (isELF32_ABI && Align)
2311 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
2313 ArgOffset += PtrByteSize;
2318 if (FPR_idx != NumFPRs) {
2319 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
2322 SDValue Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
2323 MemOpChains.push_back(Store);
2325 // Float varargs are always shadowed in available integer registers
2326 if (GPR_idx != NumGPRs) {
2327 SDValue Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
2328 MemOpChains.push_back(Load.getValue(1));
2329 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
2332 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
2333 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
2334 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
2335 SDValue Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
2336 MemOpChains.push_back(Load.getValue(1));
2337 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
2341 // If we have any FPRs remaining, we may also have GPRs remaining.
2342 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
2345 if (GPR_idx != NumGPRs)
2347 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
2348 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
2353 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2354 isPPC64, isTailCall, false, MemOpChains,
2358 if (inMem || isMachoABI) {
2359 // Stack align in ELF
2360 if (isELF32_ABI && Align)
2361 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
2365 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
2373 // These go aligned on the stack, or in the corresponding R registers
2374 // when within range. The Darwin PPC ABI doc claims they also go in
2375 // V registers; in fact gcc does this only for arguments that are
2376 // prototyped, not for those that match the ... We do it for all
2377 // arguments, seems to work.
2378 while (ArgOffset % 16 !=0) {
2379 ArgOffset += PtrByteSize;
2380 if (GPR_idx != NumGPRs)
2383 // We could elide this store in the case where the object fits
2384 // entirely in R registers. Maybe later.
2385 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr,
2386 DAG.getConstant(ArgOffset, PtrVT));
2387 SDValue Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
2388 MemOpChains.push_back(Store);
2389 if (VR_idx != NumVRs) {
2390 SDValue Load = DAG.getLoad(MVT::v4f32, Store, PtrOff, NULL, 0);
2391 MemOpChains.push_back(Load.getValue(1));
2392 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
2395 for (unsigned i=0; i<16; i+=PtrByteSize) {
2396 if (GPR_idx == NumGPRs)
2398 SDValue Ix = DAG.getNode(ISD::ADD, PtrVT, PtrOff,
2399 DAG.getConstant(i, PtrVT));
2400 SDValue Load = DAG.getLoad(PtrVT, Store, Ix, NULL, 0);
2401 MemOpChains.push_back(Load.getValue(1));
2402 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
2407 // Non-varargs Altivec params generally go in registers, but have
2408 // stack space allocated at the end.
2409 if (VR_idx != NumVRs) {
2410 // Doesn't have GPR space allocated.
2411 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
2412 } else if (nAltivecParamsAtEnd==0) {
2413 // We are emitting Altivec params in order.
2414 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2415 isPPC64, isTailCall, true, MemOpChains,
2422 // If all Altivec parameters fit in registers, as they usually do,
2423 // they get stack space following the non-Altivec parameters. We
2424 // don't track this here because nobody below needs it.
2425 // If there are more Altivec parameters than fit in registers emit
2427 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
2429 // Offset is aligned; skip 1st 12 params which go in V registers.
2430 ArgOffset = ((ArgOffset+15)/16)*16;
2432 for (unsigned i = 0; i != NumOps; ++i) {
2433 SDValue Arg = TheCall->getArg(i);
2434 MVT ArgType = Arg.getValueType();
2435 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
2436 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
2439 // We are emitting Altivec params in order.
2440 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
2441 isPPC64, isTailCall, true, MemOpChains,
2449 if (!MemOpChains.empty())
2450 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2451 &MemOpChains[0], MemOpChains.size());
2453 // Build a sequence of copy-to-reg nodes chained together with token chain
2454 // and flag operands which copy the outgoing args into the appropriate regs.
2456 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2457 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
2459 InFlag = Chain.getValue(1);
2462 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
2463 if (isVarArg && isELF32_ABI) {
2464 SDValue SetCR(DAG.getTargetNode(PPC::CRSET, MVT::i32), 0);
2465 Chain = DAG.getCopyToReg(Chain, PPC::CR1EQ, SetCR, InFlag);
2466 InFlag = Chain.getValue(1);
2469 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2470 // might overwrite each other in case of tail call optimization.
2472 SmallVector<SDValue, 8> MemOpChains2;
2473 // Do not flag preceeding copytoreg stuff together with the following stuff.
2475 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2477 if (!MemOpChains2.empty())
2478 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
2479 &MemOpChains2[0], MemOpChains2.size());
2481 // Store the return address to the appropriate stack slot.
2482 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2483 isPPC64, isMachoABI);
2486 // Emit callseq_end just before tailcall node.
2488 SmallVector<SDValue, 8> CallSeqOps;
2489 SDVTList CallSeqNodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
2490 CallSeqOps.push_back(Chain);
2491 CallSeqOps.push_back(DAG.getIntPtrConstant(NumBytes, true));
2492 CallSeqOps.push_back(DAG.getIntPtrConstant(0, true));
2493 if (InFlag.getNode())
2494 CallSeqOps.push_back(InFlag);
2495 Chain = DAG.getNode(ISD::CALLSEQ_END, CallSeqNodeTys, &CallSeqOps[0],
2497 InFlag = Chain.getValue(1);
2500 std::vector<MVT> NodeTys;
2501 NodeTys.push_back(MVT::Other); // Returns a chain
2502 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
2504 SmallVector<SDValue, 8> Ops;
2505 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
2507 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2508 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2509 // node so that legalize doesn't hack it.
2510 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2511 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
2512 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
2513 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
2514 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
2515 // If this is an absolute destination address, use the munged value.
2516 Callee = SDValue(Dest, 0);
2518 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2519 // to do the call, we can't use PPCISD::CALL.
2520 SDValue MTCTROps[] = {Chain, Callee, InFlag};
2521 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps,
2522 2 + (InFlag.getNode() != 0));
2523 InFlag = Chain.getValue(1);
2525 // Copy the callee address into R12/X12 on darwin.
2527 unsigned Reg = Callee.getValueType() == MVT::i32 ? PPC::R12 : PPC::X12;
2528 Chain = DAG.getCopyToReg(Chain, Reg, Callee, InFlag);
2529 InFlag = Chain.getValue(1);
2533 NodeTys.push_back(MVT::Other);
2534 NodeTys.push_back(MVT::Flag);
2535 Ops.push_back(Chain);
2536 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
2538 // Add CTR register as callee so a bctr can be emitted later.
2540 Ops.push_back(DAG.getRegister(PPC::CTR, getPointerTy()));
2543 // If this is a direct call, pass the chain and the callee.
2544 if (Callee.getNode()) {
2545 Ops.push_back(Chain);
2546 Ops.push_back(Callee);
2548 // If this is a tail call add stack pointer delta.
2550 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2552 // Add argument registers to the end of the list so that they are known live
2554 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2555 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2556 RegsToPass[i].second.getValueType()));
2558 // When performing tail call optimization the callee pops its arguments off
2559 // the stack. Account for this here so these bytes can be pushed back on in
2560 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2561 int BytesCalleePops =
2562 (CC==CallingConv::Fast && PerformTailCallOpt) ? NumBytes : 0;
2564 if (InFlag.getNode())
2565 Ops.push_back(InFlag);
2569 assert(InFlag.getNode() &&
2570 "Flag must be set. Depend on flag being set in LowerRET");
2571 Chain = DAG.getNode(PPCISD::TAILCALL,
2572 TheCall->getVTList(), &Ops[0], Ops.size());
2573 return SDValue(Chain.getNode(), Op.getResNo());
2576 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
2577 InFlag = Chain.getValue(1);
2579 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2580 DAG.getIntPtrConstant(BytesCalleePops, true),
2582 if (TheCall->getValueType(0) != MVT::Other)
2583 InFlag = Chain.getValue(1);
2585 SmallVector<SDValue, 16> ResultVals;
2586 SmallVector<CCValAssign, 16> RVLocs;
2587 unsigned CallerCC = DAG.getMachineFunction().getFunction()->getCallingConv();
2588 CCState CCInfo(CallerCC, isVarArg, TM, RVLocs);
2589 CCInfo.AnalyzeCallResult(TheCall, RetCC_PPC);
2591 // Copy all of the result registers out of their specified physreg.
2592 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2593 CCValAssign &VA = RVLocs[i];
2594 MVT VT = VA.getValVT();
2595 assert(VA.isRegLoc() && "Can only return in registers!");
2596 Chain = DAG.getCopyFromReg(Chain, VA.getLocReg(), VT, InFlag).getValue(1);
2597 ResultVals.push_back(Chain.getValue(0));
2598 InFlag = Chain.getValue(2);
2601 // If the function returns void, just return the chain.
2605 // Otherwise, merge everything together with a MERGE_VALUES node.
2606 ResultVals.push_back(Chain);
2607 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, TheCall->getVTList(),
2608 &ResultVals[0], ResultVals.size());
2609 return Res.getValue(Op.getResNo());
2612 SDValue PPCTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG,
2613 TargetMachine &TM) {
2614 SmallVector<CCValAssign, 16> RVLocs;
2615 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
2616 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
2617 CCState CCInfo(CC, isVarArg, TM, RVLocs);
2618 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_PPC);
2620 // If this is the first return lowered for this function, add the regs to the
2621 // liveout set for the function.
2622 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2623 for (unsigned i = 0; i != RVLocs.size(); ++i)
2624 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2627 SDValue Chain = Op.getOperand(0);
2629 Chain = GetPossiblePreceedingTailCall(Chain, PPCISD::TAILCALL);
2630 if (Chain.getOpcode() == PPCISD::TAILCALL) {
2631 SDValue TailCall = Chain;
2632 SDValue TargetAddress = TailCall.getOperand(1);
2633 SDValue StackAdjustment = TailCall.getOperand(2);
2635 assert(((TargetAddress.getOpcode() == ISD::Register &&
2636 cast<RegisterSDNode>(TargetAddress)->getReg() == PPC::CTR) ||
2637 TargetAddress.getOpcode() == ISD::TargetExternalSymbol ||
2638 TargetAddress.getOpcode() == ISD::TargetGlobalAddress ||
2639 isa<ConstantSDNode>(TargetAddress)) &&
2640 "Expecting an global address, external symbol, absolute value or register");
2642 assert(StackAdjustment.getOpcode() == ISD::Constant &&
2643 "Expecting a const value");
2645 SmallVector<SDValue,8> Operands;
2646 Operands.push_back(Chain.getOperand(0));
2647 Operands.push_back(TargetAddress);
2648 Operands.push_back(StackAdjustment);
2649 // Copy registers used by the call. Last operand is a flag so it is not
2651 for (unsigned i=3; i < TailCall.getNumOperands()-1; i++) {
2652 Operands.push_back(Chain.getOperand(i));
2654 return DAG.getNode(PPCISD::TC_RETURN, MVT::Other, &Operands[0],
2660 // Copy the result values into the output registers.
2661 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2662 CCValAssign &VA = RVLocs[i];
2663 assert(VA.isRegLoc() && "Can only return in registers!");
2664 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
2665 Flag = Chain.getValue(1);
2669 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
2671 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
2674 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
2675 const PPCSubtarget &Subtarget) {
2676 // When we pop the dynamic allocation we need to restore the SP link.
2678 // Get the corect type for pointers.
2679 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2681 // Construct the stack pointer operand.
2682 bool IsPPC64 = Subtarget.isPPC64();
2683 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
2684 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
2686 // Get the operands for the STACKRESTORE.
2687 SDValue Chain = Op.getOperand(0);
2688 SDValue SaveSP = Op.getOperand(1);
2690 // Load the old link SP.
2691 SDValue LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
2693 // Restore the stack pointer.
2694 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
2696 // Store the old link SP.
2697 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
2703 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
2704 MachineFunction &MF = DAG.getMachineFunction();
2705 bool IsPPC64 = PPCSubTarget.isPPC64();
2706 bool isMachoABI = PPCSubTarget.isMachoABI();
2707 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2709 // Get current frame pointer save index. The users of this index will be
2710 // primarily DYNALLOC instructions.
2711 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2712 int RASI = FI->getReturnAddrSaveIndex();
2714 // If the frame pointer save index hasn't been defined yet.
2716 // Find out what the fix offset of the frame pointer save area.
2717 int LROffset = PPCFrameInfo::getReturnSaveOffset(IsPPC64, isMachoABI);
2718 // Allocate the frame index for frame pointer save area.
2719 RASI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, LROffset);
2721 FI->setReturnAddrSaveIndex(RASI);
2723 return DAG.getFrameIndex(RASI, PtrVT);
2727 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
2728 MachineFunction &MF = DAG.getMachineFunction();
2729 bool IsPPC64 = PPCSubTarget.isPPC64();
2730 bool isMachoABI = PPCSubTarget.isMachoABI();
2731 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2733 // Get current frame pointer save index. The users of this index will be
2734 // primarily DYNALLOC instructions.
2735 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2736 int FPSI = FI->getFramePointerSaveIndex();
2738 // If the frame pointer save index hasn't been defined yet.
2740 // Find out what the fix offset of the frame pointer save area.
2741 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
2743 // Allocate the frame index for frame pointer save area.
2744 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
2746 FI->setFramePointerSaveIndex(FPSI);
2748 return DAG.getFrameIndex(FPSI, PtrVT);
2751 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
2753 const PPCSubtarget &Subtarget) {
2755 SDValue Chain = Op.getOperand(0);
2756 SDValue Size = Op.getOperand(1);
2758 // Get the corect type for pointers.
2759 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2761 SDValue NegSize = DAG.getNode(ISD::SUB, PtrVT,
2762 DAG.getConstant(0, PtrVT), Size);
2763 // Construct a node for the frame pointer save index.
2764 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
2765 // Build a DYNALLOC node.
2766 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
2767 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
2768 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
2771 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
2773 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
2774 // Not FP? Not a fsel.
2775 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
2776 !Op.getOperand(2).getValueType().isFloatingPoint())
2779 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2781 // Cannot handle SETEQ/SETNE.
2782 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDValue();
2784 MVT ResVT = Op.getValueType();
2785 MVT CmpVT = Op.getOperand(0).getValueType();
2786 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2787 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
2789 // If the RHS of the comparison is a 0.0, we don't need to do the
2790 // subtraction at all.
2791 if (isFloatingPointZero(RHS))
2793 default: break; // SETUO etc aren't handled by fsel.
2796 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2799 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2800 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2801 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
2804 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2807 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2808 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2809 return DAG.getNode(PPCISD::FSEL, ResVT,
2810 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
2815 default: break; // SETUO etc aren't handled by fsel.
2818 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2819 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2820 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2821 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2824 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2825 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2826 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2827 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2830 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2831 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2832 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2833 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2836 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2837 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2838 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2839 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2844 // FIXME: Split this code up when LegalizeDAGTypes lands.
2845 SDValue PPCTargetLowering::LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) {
2846 assert(Op.getOperand(0).getValueType().isFloatingPoint());
2847 SDValue Src = Op.getOperand(0);
2848 if (Src.getValueType() == MVT::f32)
2849 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
2852 switch (Op.getValueType().getSimpleVT()) {
2853 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
2855 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
2858 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
2862 // Convert the FP value to an int value through memory.
2863 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
2865 // Emit a store to the stack slot.
2866 SDValue Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0);
2868 // Result is a load from the stack slot. If loading 4 bytes, make sure to
2870 if (Op.getValueType() == MVT::i32)
2871 FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr,
2872 DAG.getConstant(4, FIPtr.getValueType()));
2873 return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0);
2876 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) {
2877 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
2878 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
2881 if (Op.getOperand(0).getValueType() == MVT::i64) {
2882 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
2883 SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
2884 if (Op.getValueType() == MVT::f32)
2885 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
2889 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
2890 "Unhandled SINT_TO_FP type in custom expander!");
2891 // Since we only generate this in 64-bit mode, we can take advantage of
2892 // 64-bit registers. In particular, sign extend the input value into the
2893 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
2894 // then lfd it and fcfid it.
2895 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2896 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
2897 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2898 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2900 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
2903 // STD the extended value into the stack slot.
2904 MachineMemOperand MO(PseudoSourceValue::getFixedStack(FrameIdx),
2905 MachineMemOperand::MOStore, 0, 8, 8);
2906 SDValue Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
2907 DAG.getEntryNode(), Ext64, FIdx,
2908 DAG.getMemOperand(MO));
2909 // Load the value as a double.
2910 SDValue Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
2912 // FCFID it and return it.
2913 SDValue FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
2914 if (Op.getValueType() == MVT::f32)
2915 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
2919 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) {
2921 The rounding mode is in bits 30:31 of FPSR, and has the following
2928 FLT_ROUNDS, on the other hand, expects the following:
2935 To perform the conversion, we do:
2936 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
2939 MachineFunction &MF = DAG.getMachineFunction();
2940 MVT VT = Op.getValueType();
2941 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2942 std::vector<MVT> NodeTys;
2943 SDValue MFFSreg, InFlag;
2945 // Save FP Control Word to register
2946 NodeTys.push_back(MVT::f64); // return register
2947 NodeTys.push_back(MVT::Flag); // unused in this context
2948 SDValue Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2950 // Save FP register to stack slot
2951 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
2952 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
2953 SDValue Store = DAG.getStore(DAG.getEntryNode(), Chain,
2954 StackSlot, NULL, 0);
2956 // Load FP Control Word from low 32 bits of stack slot.
2957 SDValue Four = DAG.getConstant(4, PtrVT);
2958 SDValue Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four);
2959 SDValue CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0);
2961 // Transform as necessary
2963 DAG.getNode(ISD::AND, MVT::i32,
2964 CWD, DAG.getConstant(3, MVT::i32));
2966 DAG.getNode(ISD::SRL, MVT::i32,
2967 DAG.getNode(ISD::AND, MVT::i32,
2968 DAG.getNode(ISD::XOR, MVT::i32,
2969 CWD, DAG.getConstant(3, MVT::i32)),
2970 DAG.getConstant(3, MVT::i32)),
2971 DAG.getConstant(1, MVT::i32));
2974 DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2);
2976 return DAG.getNode((VT.getSizeInBits() < 16 ?
2977 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
2980 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) {
2981 MVT VT = Op.getValueType();
2982 unsigned BitWidth = VT.getSizeInBits();
2983 assert(Op.getNumOperands() == 3 &&
2984 VT == Op.getOperand(1).getValueType() &&
2987 // Expand into a bunch of logical ops. Note that these ops
2988 // depend on the PPC behavior for oversized shift amounts.
2989 SDValue Lo = Op.getOperand(0);
2990 SDValue Hi = Op.getOperand(1);
2991 SDValue Amt = Op.getOperand(2);
2992 MVT AmtVT = Amt.getValueType();
2994 SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
2995 DAG.getConstant(BitWidth, AmtVT), Amt);
2996 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt);
2997 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1);
2998 SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
2999 SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
3000 DAG.getConstant(-BitWidth, AmtVT));
3001 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5);
3002 SDValue OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
3003 SDValue OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt);
3004 SDValue OutOps[] = { OutLo, OutHi };
3005 return DAG.getMergeValues(OutOps, 2);
3008 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) {
3009 MVT VT = Op.getValueType();
3010 unsigned BitWidth = VT.getSizeInBits();
3011 assert(Op.getNumOperands() == 3 &&
3012 VT == Op.getOperand(1).getValueType() &&
3015 // Expand into a bunch of logical ops. Note that these ops
3016 // depend on the PPC behavior for oversized shift amounts.
3017 SDValue Lo = Op.getOperand(0);
3018 SDValue Hi = Op.getOperand(1);
3019 SDValue Amt = Op.getOperand(2);
3020 MVT AmtVT = Amt.getValueType();
3022 SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
3023 DAG.getConstant(BitWidth, AmtVT), Amt);
3024 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
3025 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
3026 SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
3027 SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
3028 DAG.getConstant(-BitWidth, AmtVT));
3029 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5);
3030 SDValue OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
3031 SDValue OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt);
3032 SDValue OutOps[] = { OutLo, OutHi };
3033 return DAG.getMergeValues(OutOps, 2);
3036 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) {
3037 MVT VT = Op.getValueType();
3038 unsigned BitWidth = VT.getSizeInBits();
3039 assert(Op.getNumOperands() == 3 &&
3040 VT == Op.getOperand(1).getValueType() &&
3043 // Expand into a bunch of logical ops, followed by a select_cc.
3044 SDValue Lo = Op.getOperand(0);
3045 SDValue Hi = Op.getOperand(1);
3046 SDValue Amt = Op.getOperand(2);
3047 MVT AmtVT = Amt.getValueType();
3049 SDValue Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
3050 DAG.getConstant(BitWidth, AmtVT), Amt);
3051 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
3052 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
3053 SDValue Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
3054 SDValue Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
3055 DAG.getConstant(-BitWidth, AmtVT));
3056 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5);
3057 SDValue OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt);
3058 SDValue OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT),
3059 Tmp4, Tmp6, ISD::SETLE);
3060 SDValue OutOps[] = { OutLo, OutHi };
3061 return DAG.getMergeValues(OutOps, 2);
3064 //===----------------------------------------------------------------------===//
3065 // Vector related lowering.
3068 // If this is a vector of constants or undefs, get the bits. A bit in
3069 // UndefBits is set if the corresponding element of the vector is an
3070 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
3071 // zero. Return true if this is not an array of constants, false if it is.
3073 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
3074 uint64_t UndefBits[2]) {
3075 // Start with zero'd results.
3076 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
3078 unsigned EltBitSize = BV->getOperand(0).getValueType().getSizeInBits();
3079 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3080 SDValue OpVal = BV->getOperand(i);
3082 unsigned PartNo = i >= e/2; // In the upper 128 bits?
3083 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
3085 uint64_t EltBits = 0;
3086 if (OpVal.getOpcode() == ISD::UNDEF) {
3087 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
3088 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
3090 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
3091 EltBits = CN->getZExtValue() & (~0U >> (32-EltBitSize));
3092 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
3093 assert(CN->getValueType(0) == MVT::f32 &&
3094 "Only one legal FP vector type!");
3095 EltBits = FloatToBits(CN->getValueAPF().convertToFloat());
3097 // Nonconstant element.
3101 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
3104 //printf("%llx %llx %llx %llx\n",
3105 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
3109 // If this is a splat (repetition) of a value across the whole vector, return
3110 // the smallest size that splats it. For example, "0x01010101010101..." is a
3111 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
3112 // SplatSize = 1 byte.
3113 static bool isConstantSplat(const uint64_t Bits128[2],
3114 const uint64_t Undef128[2],
3115 unsigned &SplatBits, unsigned &SplatUndef,
3116 unsigned &SplatSize) {
3118 // Don't let undefs prevent splats from matching. See if the top 64-bits are
3119 // the same as the lower 64-bits, ignoring undefs.
3120 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
3121 return false; // Can't be a splat if two pieces don't match.
3123 uint64_t Bits64 = Bits128[0] | Bits128[1];
3124 uint64_t Undef64 = Undef128[0] & Undef128[1];
3126 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
3128 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
3129 return false; // Can't be a splat if two pieces don't match.
3131 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
3132 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
3134 // If the top 16-bits are different than the lower 16-bits, ignoring
3135 // undefs, we have an i32 splat.
3136 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
3138 SplatUndef = Undef32;
3143 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
3144 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
3146 // If the top 8-bits are different than the lower 8-bits, ignoring
3147 // undefs, we have an i16 splat.
3148 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
3150 SplatUndef = Undef16;
3155 // Otherwise, we have an 8-bit splat.
3156 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
3157 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
3162 /// BuildSplatI - Build a canonical splati of Val with an element size of
3163 /// SplatSize. Cast the result to VT.
3164 static SDValue BuildSplatI(int Val, unsigned SplatSize, MVT VT,
3165 SelectionDAG &DAG) {
3166 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3168 static const MVT VTys[] = { // canonical VT to use for each size.
3169 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3172 MVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3174 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3178 MVT CanonicalVT = VTys[SplatSize-1];
3180 // Build a canonical splat for this value.
3181 SDValue Elt = DAG.getConstant(Val, CanonicalVT.getVectorElementType());
3182 SmallVector<SDValue, 8> Ops;
3183 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3184 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
3185 &Ops[0], Ops.size());
3186 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
3189 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3190 /// specified intrinsic ID.
3191 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3193 MVT DestVT = MVT::Other) {
3194 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3195 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
3196 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3199 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3200 /// specified intrinsic ID.
3201 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3202 SDValue Op2, SelectionDAG &DAG,
3203 MVT DestVT = MVT::Other) {
3204 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3205 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
3206 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3210 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3211 /// amount. The result has the specified value type.
3212 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3213 MVT VT, SelectionDAG &DAG) {
3214 // Force LHS/RHS to be the right type.
3215 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
3216 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
3219 for (unsigned i = 0; i != 16; ++i)
3220 Ops[i] = DAG.getConstant(i+Amt, MVT::i8);
3221 SDValue T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
3222 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
3223 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
3226 // If this is a case we can't handle, return null and let the default
3227 // expansion code take care of it. If we CAN select this case, and if it
3228 // selects to a single instruction, return Op. Otherwise, if we can codegen
3229 // this case more efficiently than a constant pool load, lower it to the
3230 // sequence of ops that should be used.
3231 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
3232 SelectionDAG &DAG) {
3233 // If this is a vector of constants or undefs, get the bits. A bit in
3234 // UndefBits is set if the corresponding element of the vector is an
3235 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
3237 uint64_t VectorBits[2];
3238 uint64_t UndefBits[2];
3239 if (GetConstantBuildVectorBits(Op.getNode(), VectorBits, UndefBits))
3240 return SDValue(); // Not a constant vector.
3242 // If this is a splat (repetition) of a value across the whole vector, return
3243 // the smallest size that splats it. For example, "0x01010101010101..." is a
3244 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
3245 // SplatSize = 1 byte.
3246 unsigned SplatBits, SplatUndef, SplatSize;
3247 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
3248 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
3250 // First, handle single instruction cases.
3253 if (SplatBits == 0) {
3254 // Canonicalize all zero vectors to be v4i32.
3255 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3256 SDValue Z = DAG.getConstant(0, MVT::i32);
3257 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
3258 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
3263 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3264 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
3265 if (SextVal >= -16 && SextVal <= 15)
3266 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
3269 // Two instruction sequences.
3271 // If this value is in the range [-32,30] and is even, use:
3272 // tmp = VSPLTI[bhw], result = add tmp, tmp
3273 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
3274 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG);
3275 Res = DAG.getNode(ISD::ADD, Res.getValueType(), Res, Res);
3276 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3279 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
3280 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
3282 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
3283 // Make -1 and vspltisw -1:
3284 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
3286 // Make the VSLW intrinsic, computing 0x8000_0000.
3287 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
3290 // xor by OnesV to invert it.
3291 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
3292 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3295 // Check to see if this is a wide variety of vsplti*, binop self cases.
3296 unsigned SplatBitSize = SplatSize*8;
3297 static const signed char SplatCsts[] = {
3298 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
3299 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
3302 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
3303 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
3304 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
3305 int i = SplatCsts[idx];
3307 // Figure out what shift amount will be used by altivec if shifted by i in
3309 unsigned TypeShiftAmt = i & (SplatBitSize-1);
3311 // vsplti + shl self.
3312 if (SextVal == (i << (int)TypeShiftAmt)) {
3313 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
3314 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3315 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
3316 Intrinsic::ppc_altivec_vslw
3318 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
3319 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3322 // vsplti + srl self.
3323 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3324 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
3325 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3326 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
3327 Intrinsic::ppc_altivec_vsrw
3329 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
3330 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3333 // vsplti + sra self.
3334 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3335 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
3336 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3337 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
3338 Intrinsic::ppc_altivec_vsraw
3340 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
3341 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3344 // vsplti + rol self.
3345 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
3346 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
3347 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
3348 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3349 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
3350 Intrinsic::ppc_altivec_vrlw
3352 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
3353 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
3356 // t = vsplti c, result = vsldoi t, t, 1
3357 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
3358 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
3359 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
3361 // t = vsplti c, result = vsldoi t, t, 2
3362 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
3363 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
3364 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
3366 // t = vsplti c, result = vsldoi t, t, 3
3367 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
3368 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
3369 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
3373 // Three instruction sequences.
3375 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
3376 if (SextVal >= 0 && SextVal <= 31) {
3377 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
3378 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
3379 LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS);
3380 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
3382 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
3383 if (SextVal >= -31 && SextVal <= 0) {
3384 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
3385 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
3386 LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
3387 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
3394 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3395 /// the specified operations to build the shuffle.
3396 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3397 SDValue RHS, SelectionDAG &DAG) {
3398 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3399 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3400 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3403 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
3415 if (OpNum == OP_COPY) {
3416 if (LHSID == (1*9+2)*9+3) return LHS;
3417 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
3421 SDValue OpLHS, OpRHS;
3422 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
3423 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
3425 unsigned ShufIdxs[16];
3427 default: assert(0 && "Unknown i32 permute!");
3429 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
3430 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
3431 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
3432 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
3435 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
3436 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
3437 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
3438 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
3441 for (unsigned i = 0; i != 16; ++i)
3442 ShufIdxs[i] = (i&3)+0;
3445 for (unsigned i = 0; i != 16; ++i)
3446 ShufIdxs[i] = (i&3)+4;
3449 for (unsigned i = 0; i != 16; ++i)
3450 ShufIdxs[i] = (i&3)+8;
3453 for (unsigned i = 0; i != 16; ++i)
3454 ShufIdxs[i] = (i&3)+12;
3457 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
3459 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
3461 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
3464 for (unsigned i = 0; i != 16; ++i)
3465 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i8);
3467 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
3468 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
3471 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
3472 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
3473 /// return the code it can be lowered into. Worst case, it can always be
3474 /// lowered into a vperm.
3475 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
3476 SelectionDAG &DAG) {
3477 SDValue V1 = Op.getOperand(0);
3478 SDValue V2 = Op.getOperand(1);
3479 SDValue PermMask = Op.getOperand(2);
3481 // Cases that are handled by instructions that take permute immediates
3482 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
3483 // selected by the instruction selector.
3484 if (V2.getOpcode() == ISD::UNDEF) {
3485 if (PPC::isSplatShuffleMask(PermMask.getNode(), 1) ||
3486 PPC::isSplatShuffleMask(PermMask.getNode(), 2) ||
3487 PPC::isSplatShuffleMask(PermMask.getNode(), 4) ||
3488 PPC::isVPKUWUMShuffleMask(PermMask.getNode(), true) ||
3489 PPC::isVPKUHUMShuffleMask(PermMask.getNode(), true) ||
3490 PPC::isVSLDOIShuffleMask(PermMask.getNode(), true) != -1 ||
3491 PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, true) ||
3492 PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, true) ||
3493 PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, true) ||
3494 PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, true) ||
3495 PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, true) ||
3496 PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, true)) {
3501 // Altivec has a variety of "shuffle immediates" that take two vector inputs
3502 // and produce a fixed permutation. If any of these match, do not lower to
3504 if (PPC::isVPKUWUMShuffleMask(PermMask.getNode(), false) ||
3505 PPC::isVPKUHUMShuffleMask(PermMask.getNode(), false) ||
3506 PPC::isVSLDOIShuffleMask(PermMask.getNode(), false) != -1 ||
3507 PPC::isVMRGLShuffleMask(PermMask.getNode(), 1, false) ||
3508 PPC::isVMRGLShuffleMask(PermMask.getNode(), 2, false) ||
3509 PPC::isVMRGLShuffleMask(PermMask.getNode(), 4, false) ||
3510 PPC::isVMRGHShuffleMask(PermMask.getNode(), 1, false) ||
3511 PPC::isVMRGHShuffleMask(PermMask.getNode(), 2, false) ||
3512 PPC::isVMRGHShuffleMask(PermMask.getNode(), 4, false))
3515 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
3516 // perfect shuffle table to emit an optimal matching sequence.
3517 unsigned PFIndexes[4];
3518 bool isFourElementShuffle = true;
3519 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
3520 unsigned EltNo = 8; // Start out undef.
3521 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
3522 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
3523 continue; // Undef, ignore it.
3525 unsigned ByteSource =
3526 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getZExtValue();
3527 if ((ByteSource & 3) != j) {
3528 isFourElementShuffle = false;
3533 EltNo = ByteSource/4;
3534 } else if (EltNo != ByteSource/4) {
3535 isFourElementShuffle = false;
3539 PFIndexes[i] = EltNo;
3542 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
3543 // perfect shuffle vector to determine if it is cost effective to do this as
3544 // discrete instructions, or whether we should use a vperm.
3545 if (isFourElementShuffle) {
3546 // Compute the index in the perfect shuffle table.
3547 unsigned PFTableIndex =
3548 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3550 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3551 unsigned Cost = (PFEntry >> 30);
3553 // Determining when to avoid vperm is tricky. Many things affect the cost
3554 // of vperm, particularly how many times the perm mask needs to be computed.
3555 // For example, if the perm mask can be hoisted out of a loop or is already
3556 // used (perhaps because there are multiple permutes with the same shuffle
3557 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
3558 // the loop requires an extra register.
3560 // As a compromise, we only emit discrete instructions if the shuffle can be
3561 // generated in 3 or fewer operations. When we have loop information
3562 // available, if this block is within a loop, we should avoid using vperm
3563 // for 3-operation perms and use a constant pool load instead.
3565 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
3568 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
3569 // vector that will get spilled to the constant pool.
3570 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
3572 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
3573 // that it is in input element units, not in bytes. Convert now.
3574 MVT EltVT = V1.getValueType().getVectorElementType();
3575 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
3577 SmallVector<SDValue, 16> ResultMask;
3578 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
3580 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
3583 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getZExtValue();
3585 for (unsigned j = 0; j != BytesPerElement; ++j)
3586 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
3590 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
3591 &ResultMask[0], ResultMask.size());
3592 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
3595 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
3596 /// altivec comparison. If it is, return true and fill in Opc/isDot with
3597 /// information about the intrinsic.
3598 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
3600 unsigned IntrinsicID =
3601 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
3604 switch (IntrinsicID) {
3605 default: return false;
3606 // Comparison predicates.
3607 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
3608 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
3609 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
3610 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
3611 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
3612 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
3613 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
3614 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
3615 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
3616 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
3617 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
3618 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
3619 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
3621 // Normal Comparisons.
3622 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
3623 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
3624 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
3625 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
3626 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
3627 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
3628 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
3629 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
3630 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
3631 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
3632 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
3633 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
3634 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
3639 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
3640 /// lower, do it, otherwise return null.
3641 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
3642 SelectionDAG &DAG) {
3643 // If this is a lowered altivec predicate compare, CompareOpc is set to the
3644 // opcode number of the comparison.
3647 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
3648 return SDValue(); // Don't custom lower most intrinsics.
3650 // If this is a non-dot comparison, make the VCMP node and we are done.
3652 SDValue Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
3653 Op.getOperand(1), Op.getOperand(2),
3654 DAG.getConstant(CompareOpc, MVT::i32));
3655 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
3658 // Create the PPCISD altivec 'dot' comparison node.
3660 Op.getOperand(2), // LHS
3661 Op.getOperand(3), // RHS
3662 DAG.getConstant(CompareOpc, MVT::i32)
3664 std::vector<MVT> VTs;
3665 VTs.push_back(Op.getOperand(2).getValueType());
3666 VTs.push_back(MVT::Flag);
3667 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
3669 // Now that we have the comparison, emit a copy from the CR to a GPR.
3670 // This is flagged to the above dot comparison.
3671 SDValue Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
3672 DAG.getRegister(PPC::CR6, MVT::i32),
3673 CompNode.getValue(1));
3675 // Unpack the result based on how the target uses it.
3676 unsigned BitNo; // Bit # of CR6.
3677 bool InvertBit; // Invert result?
3678 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
3679 default: // Can't happen, don't crash on invalid number though.
3680 case 0: // Return the value of the EQ bit of CR6.
3681 BitNo = 0; InvertBit = false;
3683 case 1: // Return the inverted value of the EQ bit of CR6.
3684 BitNo = 0; InvertBit = true;
3686 case 2: // Return the value of the LT bit of CR6.
3687 BitNo = 2; InvertBit = false;
3689 case 3: // Return the inverted value of the LT bit of CR6.
3690 BitNo = 2; InvertBit = true;
3694 // Shift the bit into the low position.
3695 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
3696 DAG.getConstant(8-(3-BitNo), MVT::i32));
3698 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
3699 DAG.getConstant(1, MVT::i32));
3701 // If we are supposed to, toggle the bit.
3703 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
3704 DAG.getConstant(1, MVT::i32));
3708 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
3709 SelectionDAG &DAG) {
3710 // Create a stack slot that is 16-byte aligned.
3711 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3712 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
3713 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3714 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3716 // Store the input value into Value#0 of the stack slot.
3717 SDValue Store = DAG.getStore(DAG.getEntryNode(),
3718 Op.getOperand(0), FIdx, NULL, 0);
3720 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
3723 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) {
3724 if (Op.getValueType() == MVT::v4i32) {
3725 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3727 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
3728 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
3730 SDValue RHSSwap = // = vrlw RHS, 16
3731 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
3733 // Shrinkify inputs to v8i16.
3734 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
3735 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
3736 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
3738 // Low parts multiplied together, generating 32-bit results (we ignore the
3740 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
3741 LHS, RHS, DAG, MVT::v4i32);
3743 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
3744 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
3745 // Shift the high parts up 16 bits.
3746 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
3747 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
3748 } else if (Op.getValueType() == MVT::v8i16) {
3749 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3751 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
3753 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
3754 LHS, RHS, Zero, DAG);
3755 } else if (Op.getValueType() == MVT::v16i8) {
3756 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3758 // Multiply the even 8-bit parts, producing 16-bit sums.
3759 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
3760 LHS, RHS, DAG, MVT::v8i16);
3761 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
3763 // Multiply the odd 8-bit parts, producing 16-bit sums.
3764 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
3765 LHS, RHS, DAG, MVT::v8i16);
3766 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
3768 // Merge the results together.
3770 for (unsigned i = 0; i != 8; ++i) {
3771 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
3772 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
3774 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
3775 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
3777 assert(0 && "Unknown mul to lower!");
3782 /// LowerOperation - Provide custom lowering hooks for some operations.
3784 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
3785 switch (Op.getOpcode()) {
3786 default: assert(0 && "Wasn't expecting to be able to lower this!");
3787 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3788 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3789 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3790 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3791 case ISD::SETCC: return LowerSETCC(Op, DAG);
3792 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
3794 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3795 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3798 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3799 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3801 case ISD::FORMAL_ARGUMENTS:
3802 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
3803 VarArgsStackOffset, VarArgsNumGPR,
3804 VarArgsNumFPR, PPCSubTarget);
3806 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget,
3807 getTargetMachine());
3808 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
3809 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
3810 case ISD::DYNAMIC_STACKALLOC:
3811 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
3813 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3814 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
3815 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
3816 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3818 // Lower 64-bit shifts.
3819 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
3820 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
3821 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
3823 // Vector-related lowering.
3824 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3825 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3826 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3827 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
3828 case ISD::MUL: return LowerMUL(Op, DAG);
3830 // Frame & Return address.
3831 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3832 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3837 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
3838 SmallVectorImpl<SDValue>&Results,
3839 SelectionDAG &DAG) {
3840 switch (N->getOpcode()) {
3842 assert(false && "Do not know how to custom type legalize this operation!");
3844 case ISD::FP_ROUND_INREG: {
3845 assert(N->getValueType(0) == MVT::ppcf128);
3846 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
3847 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::f64, N->getOperand(0),
3848 DAG.getIntPtrConstant(0));
3849 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::f64, N->getOperand(0),
3850 DAG.getIntPtrConstant(1));
3852 // This sequence changes FPSCR to do round-to-zero, adds the two halves
3853 // of the long double, and puts FPSCR back the way it was. We do not
3854 // actually model FPSCR.
3855 std::vector<MVT> NodeTys;
3856 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
3858 NodeTys.push_back(MVT::f64); // Return register
3859 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
3860 Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
3861 MFFSreg = Result.getValue(0);
3862 InFlag = Result.getValue(1);
3865 NodeTys.push_back(MVT::Flag); // Returns a flag
3866 Ops[0] = DAG.getConstant(31, MVT::i32);
3868 Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2);
3869 InFlag = Result.getValue(0);
3872 NodeTys.push_back(MVT::Flag); // Returns a flag
3873 Ops[0] = DAG.getConstant(30, MVT::i32);
3875 Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2);
3876 InFlag = Result.getValue(0);
3879 NodeTys.push_back(MVT::f64); // result of add
3880 NodeTys.push_back(MVT::Flag); // Returns a flag
3884 Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3);
3885 FPreg = Result.getValue(0);
3886 InFlag = Result.getValue(1);
3889 NodeTys.push_back(MVT::f64);
3890 Ops[0] = DAG.getConstant(1, MVT::i32);
3894 Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4);
3895 FPreg = Result.getValue(0);
3897 // We know the low half is about to be thrown away, so just use something
3899 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, MVT::ppcf128, FPreg, FPreg));
3902 case ISD::FP_TO_SINT:
3903 Results.push_back(LowerFP_TO_SINT(SDValue(N, 0), DAG));
3909 //===----------------------------------------------------------------------===//
3910 // Other Lowering Code
3911 //===----------------------------------------------------------------------===//
3914 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
3915 bool is64bit, unsigned BinOpcode) {
3916 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3917 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3919 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3920 MachineFunction *F = BB->getParent();
3921 MachineFunction::iterator It = BB;
3924 unsigned dest = MI->getOperand(0).getReg();
3925 unsigned ptrA = MI->getOperand(1).getReg();
3926 unsigned ptrB = MI->getOperand(2).getReg();
3927 unsigned incr = MI->getOperand(3).getReg();
3929 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
3930 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
3931 F->insert(It, loopMBB);
3932 F->insert(It, exitMBB);
3933 exitMBB->transferSuccessors(BB);
3935 MachineRegisterInfo &RegInfo = F->getRegInfo();
3936 unsigned TmpReg = (!BinOpcode) ? incr :
3937 RegInfo.createVirtualRegister(
3938 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
3939 (const TargetRegisterClass *) &PPC::GPRCRegClass);
3943 // fallthrough --> loopMBB
3944 BB->addSuccessor(loopMBB);
3947 // l[wd]arx dest, ptr
3948 // add r0, dest, incr
3949 // st[wd]cx. r0, ptr
3951 // fallthrough --> exitMBB
3953 BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
3954 .addReg(ptrA).addReg(ptrB);
3956 BuildMI(BB, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
3957 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
3958 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
3959 BuildMI(BB, TII->get(PPC::BCC))
3960 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
3961 BB->addSuccessor(loopMBB);
3962 BB->addSuccessor(exitMBB);
3971 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
3972 MachineBasicBlock *BB,
3973 bool is8bit, // operation
3974 unsigned BinOpcode) {
3975 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
3976 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3977 // In 64 bit mode we have to use 64 bits for addresses, even though the
3978 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
3979 // registers without caring whether they're 32 or 64, but here we're
3980 // doing actual arithmetic on the addresses.
3981 bool is64bit = PPCSubTarget.isPPC64();
3983 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3984 MachineFunction *F = BB->getParent();
3985 MachineFunction::iterator It = BB;
3988 unsigned dest = MI->getOperand(0).getReg();
3989 unsigned ptrA = MI->getOperand(1).getReg();
3990 unsigned ptrB = MI->getOperand(2).getReg();
3991 unsigned incr = MI->getOperand(3).getReg();
3993 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
3994 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
3995 F->insert(It, loopMBB);
3996 F->insert(It, exitMBB);
3997 exitMBB->transferSuccessors(BB);
3999 MachineRegisterInfo &RegInfo = F->getRegInfo();
4000 const TargetRegisterClass *RC =
4001 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4002 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4003 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4004 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4005 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4006 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4007 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4008 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4009 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4010 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4011 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
4012 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4013 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4015 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
4019 // fallthrough --> loopMBB
4020 BB->addSuccessor(loopMBB);
4022 // The 4-byte load must be aligned, while a char or short may be
4023 // anywhere in the word. Hence all this nasty bookkeeping code.
4024 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4025 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4026 // xori shift, shift1, 24 [16]
4027 // rlwinm ptr, ptr1, 0, 0, 29
4028 // slw incr2, incr, shift
4029 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4030 // slw mask, mask2, shift
4032 // lwarx tmpDest, ptr
4033 // add tmp, tmpDest, incr2
4034 // andc tmp2, tmpDest, mask
4035 // and tmp3, tmp, mask
4036 // or tmp4, tmp3, tmp2
4039 // fallthrough --> exitMBB
4040 // srw dest, tmpDest, shift
4042 if (ptrA!=PPC::R0) {
4043 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4044 BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4045 .addReg(ptrA).addReg(ptrB);
4049 BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4050 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4051 BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4052 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4054 BuildMI(BB, TII->get(PPC::RLDICR), PtrReg)
4055 .addReg(Ptr1Reg).addImm(0).addImm(61);
4057 BuildMI(BB, TII->get(PPC::RLWINM), PtrReg)
4058 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4059 BuildMI(BB, TII->get(PPC::SLW), Incr2Reg)
4060 .addReg(incr).addReg(ShiftReg);
4062 BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255);
4064 BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0);
4065 BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535);
4067 BuildMI(BB, TII->get(PPC::SLW), MaskReg)
4068 .addReg(Mask2Reg).addReg(ShiftReg);
4071 BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg)
4072 .addReg(PPC::R0).addReg(PtrReg);
4074 BuildMI(BB, TII->get(BinOpcode), TmpReg)
4075 .addReg(Incr2Reg).addReg(TmpDestReg);
4076 BuildMI(BB, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4077 .addReg(TmpDestReg).addReg(MaskReg);
4078 BuildMI(BB, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4079 .addReg(TmpReg).addReg(MaskReg);
4080 BuildMI(BB, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4081 .addReg(Tmp3Reg).addReg(Tmp2Reg);
4082 BuildMI(BB, TII->get(PPC::STWCX))
4083 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
4084 BuildMI(BB, TII->get(PPC::BCC))
4085 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4086 BB->addSuccessor(loopMBB);
4087 BB->addSuccessor(exitMBB);
4092 BuildMI(BB, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
4097 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4098 MachineBasicBlock *BB) {
4099 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4101 // To "insert" these instructions we actually have to insert their
4102 // control-flow patterns.
4103 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4104 MachineFunction::iterator It = BB;
4107 MachineFunction *F = BB->getParent();
4109 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4110 MI->getOpcode() == PPC::SELECT_CC_I8 ||
4111 MI->getOpcode() == PPC::SELECT_CC_F4 ||
4112 MI->getOpcode() == PPC::SELECT_CC_F8 ||
4113 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4115 // The incoming instruction knows the destination vreg to set, the
4116 // condition code register to branch on, the true/false values to
4117 // select between, and a branch opcode to use.
4122 // cmpTY ccX, r1, r2
4124 // fallthrough --> copy0MBB
4125 MachineBasicBlock *thisMBB = BB;
4126 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4127 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4128 unsigned SelectPred = MI->getOperand(4).getImm();
4129 BuildMI(BB, TII->get(PPC::BCC))
4130 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4131 F->insert(It, copy0MBB);
4132 F->insert(It, sinkMBB);
4133 // Update machine-CFG edges by transferring all successors of the current
4134 // block to the new block which will contain the Phi node for the select.
4135 sinkMBB->transferSuccessors(BB);
4136 // Next, add the true and fallthrough blocks as its successors.
4137 BB->addSuccessor(copy0MBB);
4138 BB->addSuccessor(sinkMBB);
4141 // %FalseValue = ...
4142 // # fallthrough to sinkMBB
4145 // Update machine-CFG edges
4146 BB->addSuccessor(sinkMBB);
4149 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4152 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
4153 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4154 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4156 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4157 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4158 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4159 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4160 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4161 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4162 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4163 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4165 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4166 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4167 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4168 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4169 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4170 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4171 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4172 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4174 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4175 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4176 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4177 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4178 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4179 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4180 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4181 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4183 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4184 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4185 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4186 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4187 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4188 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4189 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4190 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4192 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4193 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
4194 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4195 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
4196 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4197 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
4198 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4199 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
4201 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
4202 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
4203 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
4204 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
4205 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
4206 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
4207 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
4208 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
4210 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
4211 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
4212 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
4213 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
4214 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
4215 BB = EmitAtomicBinary(MI, BB, false, 0);
4216 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
4217 BB = EmitAtomicBinary(MI, BB, true, 0);
4219 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
4220 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
4221 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
4223 unsigned dest = MI->getOperand(0).getReg();
4224 unsigned ptrA = MI->getOperand(1).getReg();
4225 unsigned ptrB = MI->getOperand(2).getReg();
4226 unsigned oldval = MI->getOperand(3).getReg();
4227 unsigned newval = MI->getOperand(4).getReg();
4229 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4230 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4231 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4232 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4233 F->insert(It, loop1MBB);
4234 F->insert(It, loop2MBB);
4235 F->insert(It, midMBB);
4236 F->insert(It, exitMBB);
4237 exitMBB->transferSuccessors(BB);
4241 // fallthrough --> loopMBB
4242 BB->addSuccessor(loop1MBB);
4245 // l[wd]arx dest, ptr
4246 // cmp[wd] dest, oldval
4249 // st[wd]cx. newval, ptr
4253 // st[wd]cx. dest, ptr
4256 BuildMI(BB, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4257 .addReg(ptrA).addReg(ptrB);
4258 BuildMI(BB, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
4259 .addReg(oldval).addReg(dest);
4260 BuildMI(BB, TII->get(PPC::BCC))
4261 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4262 BB->addSuccessor(loop2MBB);
4263 BB->addSuccessor(midMBB);
4266 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4267 .addReg(newval).addReg(ptrA).addReg(ptrB);
4268 BuildMI(BB, TII->get(PPC::BCC))
4269 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4270 BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB);
4271 BB->addSuccessor(loop1MBB);
4272 BB->addSuccessor(exitMBB);
4275 BuildMI(BB, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4276 .addReg(dest).addReg(ptrA).addReg(ptrB);
4277 BB->addSuccessor(exitMBB);
4282 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
4283 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
4284 // We must use 64-bit registers for addresses when targeting 64-bit,
4285 // since we're actually doing arithmetic on them. Other registers
4287 bool is64bit = PPCSubTarget.isPPC64();
4288 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
4290 unsigned dest = MI->getOperand(0).getReg();
4291 unsigned ptrA = MI->getOperand(1).getReg();
4292 unsigned ptrB = MI->getOperand(2).getReg();
4293 unsigned oldval = MI->getOperand(3).getReg();
4294 unsigned newval = MI->getOperand(4).getReg();
4296 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4297 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4298 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4299 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4300 F->insert(It, loop1MBB);
4301 F->insert(It, loop2MBB);
4302 F->insert(It, midMBB);
4303 F->insert(It, exitMBB);
4304 exitMBB->transferSuccessors(BB);
4306 MachineRegisterInfo &RegInfo = F->getRegInfo();
4307 const TargetRegisterClass *RC =
4308 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4309 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4310 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4311 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4312 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4313 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
4314 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
4315 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
4316 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
4317 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4318 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4319 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4320 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4321 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4322 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4324 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
4327 // fallthrough --> loopMBB
4328 BB->addSuccessor(loop1MBB);
4330 // The 4-byte load must be aligned, while a char or short may be
4331 // anywhere in the word. Hence all this nasty bookkeeping code.
4332 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4333 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4334 // xori shift, shift1, 24 [16]
4335 // rlwinm ptr, ptr1, 0, 0, 29
4336 // slw newval2, newval, shift
4337 // slw oldval2, oldval,shift
4338 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4339 // slw mask, mask2, shift
4340 // and newval3, newval2, mask
4341 // and oldval3, oldval2, mask
4343 // lwarx tmpDest, ptr
4344 // and tmp, tmpDest, mask
4345 // cmpw tmp, oldval3
4348 // andc tmp2, tmpDest, mask
4349 // or tmp4, tmp2, newval3
4354 // stwcx. tmpDest, ptr
4356 // srw dest, tmpDest, shift
4357 if (ptrA!=PPC::R0) {
4358 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4359 BuildMI(BB, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4360 .addReg(ptrA).addReg(ptrB);
4364 BuildMI(BB, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4365 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4366 BuildMI(BB, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4367 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4369 BuildMI(BB, TII->get(PPC::RLDICR), PtrReg)
4370 .addReg(Ptr1Reg).addImm(0).addImm(61);
4372 BuildMI(BB, TII->get(PPC::RLWINM), PtrReg)
4373 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4374 BuildMI(BB, TII->get(PPC::SLW), NewVal2Reg)
4375 .addReg(newval).addReg(ShiftReg);
4376 BuildMI(BB, TII->get(PPC::SLW), OldVal2Reg)
4377 .addReg(oldval).addReg(ShiftReg);
4379 BuildMI(BB, TII->get(PPC::LI), Mask2Reg).addImm(255);
4381 BuildMI(BB, TII->get(PPC::LI), Mask3Reg).addImm(0);
4382 BuildMI(BB, TII->get(PPC::ORI), Mask2Reg).addReg(Mask3Reg).addImm(65535);
4384 BuildMI(BB, TII->get(PPC::SLW), MaskReg)
4385 .addReg(Mask2Reg).addReg(ShiftReg);
4386 BuildMI(BB, TII->get(PPC::AND), NewVal3Reg)
4387 .addReg(NewVal2Reg).addReg(MaskReg);
4388 BuildMI(BB, TII->get(PPC::AND), OldVal3Reg)
4389 .addReg(OldVal2Reg).addReg(MaskReg);
4392 BuildMI(BB, TII->get(PPC::LWARX), TmpDestReg)
4393 .addReg(PPC::R0).addReg(PtrReg);
4394 BuildMI(BB, TII->get(PPC::AND),TmpReg).addReg(TmpDestReg).addReg(MaskReg);
4395 BuildMI(BB, TII->get(PPC::CMPW), PPC::CR0)
4396 .addReg(TmpReg).addReg(OldVal3Reg);
4397 BuildMI(BB, TII->get(PPC::BCC))
4398 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4399 BB->addSuccessor(loop2MBB);
4400 BB->addSuccessor(midMBB);
4403 BuildMI(BB, TII->get(PPC::ANDC),Tmp2Reg).addReg(TmpDestReg).addReg(MaskReg);
4404 BuildMI(BB, TII->get(PPC::OR),Tmp4Reg).addReg(Tmp2Reg).addReg(NewVal3Reg);
4405 BuildMI(BB, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
4406 .addReg(PPC::R0).addReg(PtrReg);
4407 BuildMI(BB, TII->get(PPC::BCC))
4408 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4409 BuildMI(BB, TII->get(PPC::B)).addMBB(exitMBB);
4410 BB->addSuccessor(loop1MBB);
4411 BB->addSuccessor(exitMBB);
4414 BuildMI(BB, TII->get(PPC::STWCX)).addReg(TmpDestReg)
4415 .addReg(PPC::R0).addReg(PtrReg);
4416 BB->addSuccessor(exitMBB);
4421 BuildMI(BB, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
4423 assert(0 && "Unexpected instr type to insert");
4426 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
4430 //===----------------------------------------------------------------------===//
4431 // Target Optimization Hooks
4432 //===----------------------------------------------------------------------===//
4434 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
4435 DAGCombinerInfo &DCI) const {
4436 TargetMachine &TM = getTargetMachine();
4437 SelectionDAG &DAG = DCI.DAG;
4438 switch (N->getOpcode()) {
4441 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4442 if (C->getZExtValue() == 0) // 0 << V -> 0.
4443 return N->getOperand(0);
4447 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4448 if (C->getZExtValue() == 0) // 0 >>u V -> 0.
4449 return N->getOperand(0);
4453 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
4454 if (C->getZExtValue() == 0 || // 0 >>s V -> 0.
4455 C->isAllOnesValue()) // -1 >>s V -> -1.
4456 return N->getOperand(0);
4460 case ISD::SINT_TO_FP:
4461 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
4462 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
4463 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
4464 // We allow the src/dst to be either f32/f64, but the intermediate
4465 // type must be i64.
4466 if (N->getOperand(0).getValueType() == MVT::i64 &&
4467 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
4468 SDValue Val = N->getOperand(0).getOperand(0);
4469 if (Val.getValueType() == MVT::f32) {
4470 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
4471 DCI.AddToWorklist(Val.getNode());
4474 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
4475 DCI.AddToWorklist(Val.getNode());
4476 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
4477 DCI.AddToWorklist(Val.getNode());
4478 if (N->getValueType(0) == MVT::f32) {
4479 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val,
4480 DAG.getIntPtrConstant(0));
4481 DCI.AddToWorklist(Val.getNode());
4484 } else if (N->getOperand(0).getValueType() == MVT::i32) {
4485 // If the intermediate type is i32, we can avoid the load/store here
4492 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
4493 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
4494 !cast<StoreSDNode>(N)->isTruncatingStore() &&
4495 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
4496 N->getOperand(1).getValueType() == MVT::i32 &&
4497 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
4498 SDValue Val = N->getOperand(1).getOperand(0);
4499 if (Val.getValueType() == MVT::f32) {
4500 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
4501 DCI.AddToWorklist(Val.getNode());
4503 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
4504 DCI.AddToWorklist(Val.getNode());
4506 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
4507 N->getOperand(2), N->getOperand(3));
4508 DCI.AddToWorklist(Val.getNode());
4512 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
4513 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
4514 N->getOperand(1).getNode()->hasOneUse() &&
4515 (N->getOperand(1).getValueType() == MVT::i32 ||
4516 N->getOperand(1).getValueType() == MVT::i16)) {
4517 SDValue BSwapOp = N->getOperand(1).getOperand(0);
4518 // Do an any-extend to 32-bits if this is a half-word input.
4519 if (BSwapOp.getValueType() == MVT::i16)
4520 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
4522 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
4523 N->getOperand(2), N->getOperand(3),
4524 DAG.getValueType(N->getOperand(1).getValueType()));
4528 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
4529 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
4530 N->getOperand(0).hasOneUse() &&
4531 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
4532 SDValue Load = N->getOperand(0);
4533 LoadSDNode *LD = cast<LoadSDNode>(Load);
4534 // Create the byte-swapping load.
4535 std::vector<MVT> VTs;
4536 VTs.push_back(MVT::i32);
4537 VTs.push_back(MVT::Other);
4538 SDValue MO = DAG.getMemOperand(LD->getMemOperand());
4540 LD->getChain(), // Chain
4541 LD->getBasePtr(), // Ptr
4543 DAG.getValueType(N->getValueType(0)) // VT
4545 SDValue BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
4547 // If this is an i16 load, insert the truncate.
4548 SDValue ResVal = BSLoad;
4549 if (N->getValueType(0) == MVT::i16)
4550 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
4552 // First, combine the bswap away. This makes the value produced by the
4554 DCI.CombineTo(N, ResVal);
4556 // Next, combine the load away, we give it a bogus result value but a real
4557 // chain result. The result value is dead because the bswap is dead.
4558 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
4560 // Return N so it doesn't get rechecked!
4561 return SDValue(N, 0);
4565 case PPCISD::VCMP: {
4566 // If a VCMPo node already exists with exactly the same operands as this
4567 // node, use its result instead of this node (VCMPo computes both a CR6 and
4568 // a normal output).
4570 if (!N->getOperand(0).hasOneUse() &&
4571 !N->getOperand(1).hasOneUse() &&
4572 !N->getOperand(2).hasOneUse()) {
4574 // Scan all of the users of the LHS, looking for VCMPo's that match.
4575 SDNode *VCMPoNode = 0;
4577 SDNode *LHSN = N->getOperand(0).getNode();
4578 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
4580 if (UI->getOpcode() == PPCISD::VCMPo &&
4581 UI->getOperand(1) == N->getOperand(1) &&
4582 UI->getOperand(2) == N->getOperand(2) &&
4583 UI->getOperand(0) == N->getOperand(0)) {
4588 // If there is no VCMPo node, or if the flag value has a single use, don't
4590 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
4593 // Look at the (necessarily single) use of the flag value. If it has a
4594 // chain, this transformation is more complex. Note that multiple things
4595 // could use the value result, which we should ignore.
4596 SDNode *FlagUser = 0;
4597 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
4598 FlagUser == 0; ++UI) {
4599 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
4601 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
4602 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
4609 // If the user is a MFCR instruction, we know this is safe. Otherwise we
4610 // give up for right now.
4611 if (FlagUser->getOpcode() == PPCISD::MFCR)
4612 return SDValue(VCMPoNode, 0);
4617 // If this is a branch on an altivec predicate comparison, lower this so
4618 // that we don't have to do a MFCR: instead, branch directly on CR6. This
4619 // lowering is done pre-legalize, because the legalizer lowers the predicate
4620 // compare down to code that is difficult to reassemble.
4621 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
4622 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
4626 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
4627 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
4628 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
4629 assert(isDot && "Can't compare against a vector result!");
4631 // If this is a comparison against something other than 0/1, then we know
4632 // that the condition is never/always true.
4633 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
4634 if (Val != 0 && Val != 1) {
4635 if (CC == ISD::SETEQ) // Cond never true, remove branch.
4636 return N->getOperand(0);
4637 // Always !=, turn it into an unconditional branch.
4638 return DAG.getNode(ISD::BR, MVT::Other,
4639 N->getOperand(0), N->getOperand(4));
4642 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
4644 // Create the PPCISD altivec 'dot' comparison node.
4645 std::vector<MVT> VTs;
4647 LHS.getOperand(2), // LHS of compare
4648 LHS.getOperand(3), // RHS of compare
4649 DAG.getConstant(CompareOpc, MVT::i32)
4651 VTs.push_back(LHS.getOperand(2).getValueType());
4652 VTs.push_back(MVT::Flag);
4653 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
4655 // Unpack the result based on how the target uses it.
4656 PPC::Predicate CompOpc;
4657 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
4658 default: // Can't happen, don't crash on invalid number though.
4659 case 0: // Branch on the value of the EQ bit of CR6.
4660 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
4662 case 1: // Branch on the inverted value of the EQ bit of CR6.
4663 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
4665 case 2: // Branch on the value of the LT bit of CR6.
4666 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
4668 case 3: // Branch on the inverted value of the LT bit of CR6.
4669 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
4673 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
4674 DAG.getConstant(CompOpc, MVT::i32),
4675 DAG.getRegister(PPC::CR6, MVT::i32),
4676 N->getOperand(4), CompNode.getValue(1));
4685 //===----------------------------------------------------------------------===//
4686 // Inline Assembly Support
4687 //===----------------------------------------------------------------------===//
4689 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
4693 const SelectionDAG &DAG,
4694 unsigned Depth) const {
4695 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
4696 switch (Op.getOpcode()) {
4698 case PPCISD::LBRX: {
4699 // lhbrx is known to have the top bits cleared out.
4700 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
4701 KnownZero = 0xFFFF0000;
4704 case ISD::INTRINSIC_WO_CHAIN: {
4705 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
4707 case Intrinsic::ppc_altivec_vcmpbfp_p:
4708 case Intrinsic::ppc_altivec_vcmpeqfp_p:
4709 case Intrinsic::ppc_altivec_vcmpequb_p:
4710 case Intrinsic::ppc_altivec_vcmpequh_p:
4711 case Intrinsic::ppc_altivec_vcmpequw_p:
4712 case Intrinsic::ppc_altivec_vcmpgefp_p:
4713 case Intrinsic::ppc_altivec_vcmpgtfp_p:
4714 case Intrinsic::ppc_altivec_vcmpgtsb_p:
4715 case Intrinsic::ppc_altivec_vcmpgtsh_p:
4716 case Intrinsic::ppc_altivec_vcmpgtsw_p:
4717 case Intrinsic::ppc_altivec_vcmpgtub_p:
4718 case Intrinsic::ppc_altivec_vcmpgtuh_p:
4719 case Intrinsic::ppc_altivec_vcmpgtuw_p:
4720 KnownZero = ~1U; // All bits but the low one are known to be zero.
4728 /// getConstraintType - Given a constraint, return the type of
4729 /// constraint it is for this target.
4730 PPCTargetLowering::ConstraintType
4731 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
4732 if (Constraint.size() == 1) {
4733 switch (Constraint[0]) {
4740 return C_RegisterClass;
4743 return TargetLowering::getConstraintType(Constraint);
4746 std::pair<unsigned, const TargetRegisterClass*>
4747 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
4749 if (Constraint.size() == 1) {
4750 // GCC RS6000 Constraint Letters
4751 switch (Constraint[0]) {
4754 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
4755 return std::make_pair(0U, PPC::G8RCRegisterClass);
4756 return std::make_pair(0U, PPC::GPRCRegisterClass);
4759 return std::make_pair(0U, PPC::F4RCRegisterClass);
4760 else if (VT == MVT::f64)
4761 return std::make_pair(0U, PPC::F8RCRegisterClass);
4764 return std::make_pair(0U, PPC::VRRCRegisterClass);
4766 return std::make_pair(0U, PPC::CRRCRegisterClass);
4770 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
4774 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
4775 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is true
4776 /// it means one of the asm constraint of the inline asm instruction being
4777 /// processed is 'm'.
4778 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
4780 std::vector<SDValue>&Ops,
4781 SelectionDAG &DAG) const {
4782 SDValue Result(0,0);
4793 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
4794 if (!CST) return; // Must be an immediate to match.
4795 unsigned Value = CST->getZExtValue();
4797 default: assert(0 && "Unknown constraint letter!");
4798 case 'I': // "I" is a signed 16-bit constant.
4799 if ((short)Value == (int)Value)
4800 Result = DAG.getTargetConstant(Value, Op.getValueType());
4802 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
4803 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
4804 if ((short)Value == 0)
4805 Result = DAG.getTargetConstant(Value, Op.getValueType());
4807 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
4808 if ((Value >> 16) == 0)
4809 Result = DAG.getTargetConstant(Value, Op.getValueType());
4811 case 'M': // "M" is a constant that is greater than 31.
4813 Result = DAG.getTargetConstant(Value, Op.getValueType());
4815 case 'N': // "N" is a positive constant that is an exact power of two.
4816 if ((int)Value > 0 && isPowerOf2_32(Value))
4817 Result = DAG.getTargetConstant(Value, Op.getValueType());
4819 case 'O': // "O" is the constant zero.
4821 Result = DAG.getTargetConstant(Value, Op.getValueType());
4823 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
4824 if ((short)-Value == (int)-Value)
4825 Result = DAG.getTargetConstant(Value, Op.getValueType());
4832 if (Result.getNode()) {
4833 Ops.push_back(Result);
4837 // Handle standard constraint letters.
4838 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, hasMemory, Ops, DAG);
4841 // isLegalAddressingMode - Return true if the addressing mode represented
4842 // by AM is legal for this target, for a load/store of the specified type.
4843 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
4844 const Type *Ty) const {
4845 // FIXME: PPC does not allow r+i addressing modes for vectors!
4847 // PPC allows a sign-extended 16-bit immediate field.
4848 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
4851 // No global is ever allowed as a base.
4855 // PPC only support r+r,
4857 case 0: // "r+i" or just "i", depending on HasBaseReg.
4860 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
4862 // Otherwise we have r+r or r+i.
4865 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
4867 // Allow 2*r as r+r.
4870 // No other scales are supported.
4877 /// isLegalAddressImmediate - Return true if the integer value can be used
4878 /// as the offset of the target addressing mode for load / store of the
4880 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
4881 // PPC allows a sign-extended 16-bit immediate field.
4882 return (V > -(1 << 16) && V < (1 << 16)-1);
4885 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
4889 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) {
4890 // Depths > 0 not supported yet!
4891 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
4894 MachineFunction &MF = DAG.getMachineFunction();
4895 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
4897 // Just load the return address off the stack.
4898 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
4900 // Make sure the function really does not optimize away the store of the RA
4902 FuncInfo->setLRStoreRequired();
4903 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
4906 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) {
4907 // Depths > 0 not supported yet!
4908 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
4911 MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4912 bool isPPC64 = PtrVT == MVT::i64;
4914 MachineFunction &MF = DAG.getMachineFunction();
4915 MachineFrameInfo *MFI = MF.getFrameInfo();
4916 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
4917 && MFI->getStackSize();
4920 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
4923 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,
4928 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
4929 // The PowerPC target isn't yet aware of offsets.