1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPerfectShuffle.h"
17 #include "PPCTargetMachine.h"
18 #include "MCTargetDesc/PPCPredicates.h"
19 #include "llvm/CallingConv.h"
20 #include "llvm/Constants.h"
21 #include "llvm/DerivedTypes.h"
22 #include "llvm/Function.h"
23 #include "llvm/Intrinsics.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/CallingConvLower.h"
26 #include "llvm/CodeGen/MachineFrameInfo.h"
27 #include "llvm/CodeGen/MachineFunction.h"
28 #include "llvm/CodeGen/MachineInstrBuilder.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetOptions.h"
39 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
40 CCValAssign::LocInfo &LocInfo,
41 ISD::ArgFlagsTy &ArgFlags,
43 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
45 CCValAssign::LocInfo &LocInfo,
46 ISD::ArgFlagsTy &ArgFlags,
48 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
50 CCValAssign::LocInfo &LocInfo,
51 ISD::ArgFlagsTy &ArgFlags,
54 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
55 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
57 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
58 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
60 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
61 if (TM.getSubtargetImpl()->isDarwin())
62 return new TargetLoweringObjectFileMachO();
64 return new TargetLoweringObjectFileELF();
67 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
69 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
73 // Use _setjmp/_longjmp instead of setjmp/longjmp.
74 setUseUnderscoreSetJmp(true);
75 setUseUnderscoreLongJmp(true);
77 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
78 // arguments are at least 4/8 bytes aligned.
79 bool isPPC64 = Subtarget->isPPC64();
80 setMinStackArgumentAlignment(isPPC64 ? 8:4);
82 // Set up the register classes.
83 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
84 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
85 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
87 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
88 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
91 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
93 // PowerPC has pre-inc load and store's.
94 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
101 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
102 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
103 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
105 // This is used in the ppcf128->int sequence. Note it has different semantics
106 // from FP_ROUND: that rounds to nearest, this rounds to zero.
107 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
109 // We do not currently implment this libm ops for PowerPC.
110 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
111 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
112 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
113 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
114 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
116 // PowerPC has no SREM/UREM instructions
117 setOperationAction(ISD::SREM, MVT::i32, Expand);
118 setOperationAction(ISD::UREM, MVT::i32, Expand);
119 setOperationAction(ISD::SREM, MVT::i64, Expand);
120 setOperationAction(ISD::UREM, MVT::i64, Expand);
122 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
123 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
124 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
125 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
126 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
127 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
128 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
129 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
130 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
132 // We don't support sin/cos/sqrt/fmod/pow
133 setOperationAction(ISD::FSIN , MVT::f64, Expand);
134 setOperationAction(ISD::FCOS , MVT::f64, Expand);
135 setOperationAction(ISD::FREM , MVT::f64, Expand);
136 setOperationAction(ISD::FPOW , MVT::f64, Expand);
137 setOperationAction(ISD::FMA , MVT::f64, Legal);
138 setOperationAction(ISD::FSIN , MVT::f32, Expand);
139 setOperationAction(ISD::FCOS , MVT::f32, Expand);
140 setOperationAction(ISD::FREM , MVT::f32, Expand);
141 setOperationAction(ISD::FPOW , MVT::f32, Expand);
142 setOperationAction(ISD::FMA , MVT::f32, Legal);
144 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
146 // If we're enabling GP optimizations, use hardware square root
147 if (!Subtarget->hasFSQRT()) {
148 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
149 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
152 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
153 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
155 // PowerPC does not have BSWAP, CTPOP or CTTZ
156 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
157 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
158 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
159 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
160 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
161 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
162 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
163 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
164 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
165 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
167 // PowerPC does not have ROTR
168 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
169 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
171 // PowerPC does not have Select
172 setOperationAction(ISD::SELECT, MVT::i32, Expand);
173 setOperationAction(ISD::SELECT, MVT::i64, Expand);
174 setOperationAction(ISD::SELECT, MVT::f32, Expand);
175 setOperationAction(ISD::SELECT, MVT::f64, Expand);
177 // PowerPC wants to turn select_cc of FP into fsel when possible.
178 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
179 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
181 // PowerPC wants to optimize integer setcc a bit
182 setOperationAction(ISD::SETCC, MVT::i32, Custom);
184 // PowerPC does not have BRCOND which requires SetCC
185 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
187 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
189 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
190 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
192 // PowerPC does not have [U|S]INT_TO_FP
193 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
194 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
196 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
197 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
198 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
199 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
201 // We cannot sextinreg(i1). Expand to shifts.
202 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
204 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
205 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
206 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
207 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
210 // We want to legalize GlobalAddress and ConstantPool nodes into the
211 // appropriate instructions to materialize the address.
212 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
213 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
214 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
215 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
216 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
217 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
218 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
219 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
220 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
221 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
224 setOperationAction(ISD::TRAP, MVT::Other, Legal);
226 // TRAMPOLINE is custom lowered.
227 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
228 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
230 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
231 setOperationAction(ISD::VASTART , MVT::Other, Custom);
233 if (Subtarget->isSVR4ABI()) {
235 // VAARG always uses double-word chunks, so promote anything smaller.
236 setOperationAction(ISD::VAARG, MVT::i1, Promote);
237 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
238 setOperationAction(ISD::VAARG, MVT::i8, Promote);
239 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
240 setOperationAction(ISD::VAARG, MVT::i16, Promote);
241 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
242 setOperationAction(ISD::VAARG, MVT::i32, Promote);
243 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
244 setOperationAction(ISD::VAARG, MVT::Other, Expand);
246 // VAARG is custom lowered with the 32-bit SVR4 ABI.
247 setOperationAction(ISD::VAARG, MVT::Other, Custom);
248 setOperationAction(ISD::VAARG, MVT::i64, Custom);
251 setOperationAction(ISD::VAARG, MVT::Other, Expand);
253 // Use the default implementation.
254 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
255 setOperationAction(ISD::VAEND , MVT::Other, Expand);
256 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
257 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
258 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
259 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
261 // We want to custom lower some of our intrinsics.
262 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
264 // Comparisons that require checking two conditions.
265 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
266 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
267 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
268 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
269 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
270 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
271 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
272 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
273 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
274 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
275 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
276 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
278 if (Subtarget->has64BitSupport()) {
279 // They also have instructions for converting between i64 and fp.
280 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
281 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
282 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
283 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
284 // This is just the low 32 bits of a (signed) fp->i64 conversion.
285 // We cannot do this with Promote because i64 is not a legal type.
286 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
288 // FIXME: disable this lowered code. This generates 64-bit register values,
289 // and we don't model the fact that the top part is clobbered by calls. We
290 // need to flag these together so that the value isn't live across a call.
291 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
293 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
294 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
297 if (Subtarget->use64BitRegs()) {
298 // 64-bit PowerPC implementations can support i64 types directly
299 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
300 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
301 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
302 // 64-bit PowerPC wants to expand i128 shifts itself.
303 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
304 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
305 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
307 // 32-bit PowerPC wants to expand i64 shifts itself.
308 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
309 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
310 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
313 if (Subtarget->hasAltivec()) {
314 // First set operation action for all vector types to expand. Then we
315 // will selectively turn on ones that can be effectively codegen'd.
316 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
317 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
318 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
320 // add/sub are legal for all supported vector VT's.
321 setOperationAction(ISD::ADD , VT, Legal);
322 setOperationAction(ISD::SUB , VT, Legal);
324 // We promote all shuffles to v16i8.
325 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
326 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
328 // We promote all non-typed operations to v4i32.
329 setOperationAction(ISD::AND , VT, Promote);
330 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
331 setOperationAction(ISD::OR , VT, Promote);
332 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
333 setOperationAction(ISD::XOR , VT, Promote);
334 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
335 setOperationAction(ISD::LOAD , VT, Promote);
336 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
337 setOperationAction(ISD::SELECT, VT, Promote);
338 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
339 setOperationAction(ISD::STORE, VT, Promote);
340 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
342 // No other operations are legal.
343 setOperationAction(ISD::MUL , VT, Expand);
344 setOperationAction(ISD::SDIV, VT, Expand);
345 setOperationAction(ISD::SREM, VT, Expand);
346 setOperationAction(ISD::UDIV, VT, Expand);
347 setOperationAction(ISD::UREM, VT, Expand);
348 setOperationAction(ISD::FDIV, VT, Expand);
349 setOperationAction(ISD::FNEG, VT, Expand);
350 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
351 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
352 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
353 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
354 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
355 setOperationAction(ISD::UDIVREM, VT, Expand);
356 setOperationAction(ISD::SDIVREM, VT, Expand);
357 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
358 setOperationAction(ISD::FPOW, VT, Expand);
359 setOperationAction(ISD::CTPOP, VT, Expand);
360 setOperationAction(ISD::CTLZ, VT, Expand);
361 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
362 setOperationAction(ISD::CTTZ, VT, Expand);
363 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
366 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
367 // with merges, splats, etc.
368 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
370 setOperationAction(ISD::AND , MVT::v4i32, Legal);
371 setOperationAction(ISD::OR , MVT::v4i32, Legal);
372 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
373 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
374 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
375 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
377 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
378 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
379 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
380 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
382 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
383 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
384 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
385 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
386 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
388 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
389 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
391 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
392 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
393 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
394 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
397 if (Subtarget->has64BitSupport())
398 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
400 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
401 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
403 setBooleanContents(ZeroOrOneBooleanContent);
404 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
407 setStackPointerRegisterToSaveRestore(PPC::X1);
408 setExceptionPointerRegister(PPC::X3);
409 setExceptionSelectorRegister(PPC::X4);
411 setStackPointerRegisterToSaveRestore(PPC::R1);
412 setExceptionPointerRegister(PPC::R3);
413 setExceptionSelectorRegister(PPC::R4);
416 // We have target-specific dag combine patterns for the following nodes:
417 setTargetDAGCombine(ISD::SINT_TO_FP);
418 setTargetDAGCombine(ISD::STORE);
419 setTargetDAGCombine(ISD::BR_CC);
420 setTargetDAGCombine(ISD::BSWAP);
422 // Darwin long double math library functions have $LDBL128 appended.
423 if (Subtarget->isDarwin()) {
424 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
425 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
426 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
427 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
428 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
429 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
430 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
431 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
432 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
433 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
436 setMinFunctionAlignment(2);
437 if (PPCSubTarget.isDarwin())
438 setPrefFunctionAlignment(4);
440 if (isPPC64 && Subtarget->isJITCodeModel())
441 // Temporary workaround for the inability of PPC64 JIT to handle jump
443 setSupportJumpTables(false);
445 setInsertFencesForAtomic(true);
447 setSchedulingPreference(Sched::Hybrid);
449 computeRegisterProperties();
452 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
453 /// function arguments in the caller parameter area.
454 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
455 const TargetMachine &TM = getTargetMachine();
456 // Darwin passes everything on 4 byte boundary.
457 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
460 // 16byte and wider vectors are passed on 16byte boundary.
461 if (VectorType *VTy = dyn_cast<VectorType>(Ty))
462 if (VTy->getBitWidth() >= 128)
465 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
466 if (PPCSubTarget.isPPC64())
472 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
475 case PPCISD::FSEL: return "PPCISD::FSEL";
476 case PPCISD::FCFID: return "PPCISD::FCFID";
477 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
478 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
479 case PPCISD::STFIWX: return "PPCISD::STFIWX";
480 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
481 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
482 case PPCISD::VPERM: return "PPCISD::VPERM";
483 case PPCISD::Hi: return "PPCISD::Hi";
484 case PPCISD::Lo: return "PPCISD::Lo";
485 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
486 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
487 case PPCISD::LOAD: return "PPCISD::LOAD";
488 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
489 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
490 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
491 case PPCISD::SRL: return "PPCISD::SRL";
492 case PPCISD::SRA: return "PPCISD::SRA";
493 case PPCISD::SHL: return "PPCISD::SHL";
494 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
495 case PPCISD::STD_32: return "PPCISD::STD_32";
496 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4";
497 case PPCISD::CALL_NOP_SVR4: return "PPCISD::CALL_NOP_SVR4";
498 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin";
499 case PPCISD::NOP: return "PPCISD::NOP";
500 case PPCISD::MTCTR: return "PPCISD::MTCTR";
501 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin";
502 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4";
503 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
504 case PPCISD::MFCR: return "PPCISD::MFCR";
505 case PPCISD::VCMP: return "PPCISD::VCMP";
506 case PPCISD::VCMPo: return "PPCISD::VCMPo";
507 case PPCISD::LBRX: return "PPCISD::LBRX";
508 case PPCISD::STBRX: return "PPCISD::STBRX";
509 case PPCISD::LARX: return "PPCISD::LARX";
510 case PPCISD::STCX: return "PPCISD::STCX";
511 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
512 case PPCISD::MFFS: return "PPCISD::MFFS";
513 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
514 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
515 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
516 case PPCISD::MTFSF: return "PPCISD::MTFSF";
517 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
521 EVT PPCTargetLowering::getSetCCResultType(EVT VT) const {
525 //===----------------------------------------------------------------------===//
526 // Node matching predicates, for use by the tblgen matching code.
527 //===----------------------------------------------------------------------===//
529 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
530 static bool isFloatingPointZero(SDValue Op) {
531 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
532 return CFP->getValueAPF().isZero();
533 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
534 // Maybe this has already been legalized into the constant pool?
535 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
536 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
537 return CFP->getValueAPF().isZero();
542 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
543 /// true if Op is undef or if it matches the specified value.
544 static bool isConstantOrUndef(int Op, int Val) {
545 return Op < 0 || Op == Val;
548 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
549 /// VPKUHUM instruction.
550 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
552 for (unsigned i = 0; i != 16; ++i)
553 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
556 for (unsigned i = 0; i != 8; ++i)
557 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
558 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
564 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
565 /// VPKUWUM instruction.
566 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
568 for (unsigned i = 0; i != 16; i += 2)
569 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
570 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
573 for (unsigned i = 0; i != 8; i += 2)
574 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
575 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
576 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
577 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
583 /// isVMerge - Common function, used to match vmrg* shuffles.
585 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
586 unsigned LHSStart, unsigned RHSStart) {
587 assert(N->getValueType(0) == MVT::v16i8 &&
588 "PPC only supports shuffles by bytes!");
589 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
590 "Unsupported merge size!");
592 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
593 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
594 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
595 LHSStart+j+i*UnitSize) ||
596 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
597 RHSStart+j+i*UnitSize))
603 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
604 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
605 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
608 return isVMerge(N, UnitSize, 8, 24);
609 return isVMerge(N, UnitSize, 8, 8);
612 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
613 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
614 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
617 return isVMerge(N, UnitSize, 0, 16);
618 return isVMerge(N, UnitSize, 0, 0);
622 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
623 /// amount, otherwise return -1.
624 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
625 assert(N->getValueType(0) == MVT::v16i8 &&
626 "PPC only supports shuffles by bytes!");
628 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
630 // Find the first non-undef value in the shuffle mask.
632 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
635 if (i == 16) return -1; // all undef.
637 // Otherwise, check to see if the rest of the elements are consecutively
638 // numbered from this value.
639 unsigned ShiftAmt = SVOp->getMaskElt(i);
640 if (ShiftAmt < i) return -1;
644 // Check the rest of the elements to see if they are consecutive.
645 for (++i; i != 16; ++i)
646 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
649 // Check the rest of the elements to see if they are consecutive.
650 for (++i; i != 16; ++i)
651 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
657 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
658 /// specifies a splat of a single element that is suitable for input to
659 /// VSPLTB/VSPLTH/VSPLTW.
660 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
661 assert(N->getValueType(0) == MVT::v16i8 &&
662 (EltSize == 1 || EltSize == 2 || EltSize == 4));
664 // This is a splat operation if each element of the permute is the same, and
665 // if the value doesn't reference the second vector.
666 unsigned ElementBase = N->getMaskElt(0);
668 // FIXME: Handle UNDEF elements too!
669 if (ElementBase >= 16)
672 // Check that the indices are consecutive, in the case of a multi-byte element
673 // splatted with a v16i8 mask.
674 for (unsigned i = 1; i != EltSize; ++i)
675 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
678 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
679 if (N->getMaskElt(i) < 0) continue;
680 for (unsigned j = 0; j != EltSize; ++j)
681 if (N->getMaskElt(i+j) != N->getMaskElt(j))
687 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
689 bool PPC::isAllNegativeZeroVector(SDNode *N) {
690 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
692 APInt APVal, APUndef;
696 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
697 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
698 return CFP->getValueAPF().isNegZero();
703 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
704 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
705 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
706 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
707 assert(isSplatShuffleMask(SVOp, EltSize));
708 return SVOp->getMaskElt(0) / EltSize;
711 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
712 /// by using a vspltis[bhw] instruction of the specified element size, return
713 /// the constant being splatted. The ByteSize field indicates the number of
714 /// bytes of each element [124] -> [bhw].
715 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
718 // If ByteSize of the splat is bigger than the element size of the
719 // build_vector, then we have a case where we are checking for a splat where
720 // multiple elements of the buildvector are folded together into a single
721 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
722 unsigned EltSize = 16/N->getNumOperands();
723 if (EltSize < ByteSize) {
724 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
725 SDValue UniquedVals[4];
726 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
728 // See if all of the elements in the buildvector agree across.
729 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
730 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
731 // If the element isn't a constant, bail fully out.
732 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
735 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
736 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
737 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
738 return SDValue(); // no match.
741 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
742 // either constant or undef values that are identical for each chunk. See
743 // if these chunks can form into a larger vspltis*.
745 // Check to see if all of the leading entries are either 0 or -1. If
746 // neither, then this won't fit into the immediate field.
747 bool LeadingZero = true;
748 bool LeadingOnes = true;
749 for (unsigned i = 0; i != Multiple-1; ++i) {
750 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
752 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
753 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
755 // Finally, check the least significant entry.
757 if (UniquedVals[Multiple-1].getNode() == 0)
758 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
759 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
761 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
764 if (UniquedVals[Multiple-1].getNode() == 0)
765 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
766 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
767 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
768 return DAG.getTargetConstant(Val, MVT::i32);
774 // Check to see if this buildvec has a single non-undef value in its elements.
775 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
776 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
777 if (OpVal.getNode() == 0)
778 OpVal = N->getOperand(i);
779 else if (OpVal != N->getOperand(i))
783 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
785 unsigned ValSizeInBytes = EltSize;
787 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
788 Value = CN->getZExtValue();
789 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
790 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
791 Value = FloatToBits(CN->getValueAPF().convertToFloat());
794 // If the splat value is larger than the element value, then we can never do
795 // this splat. The only case that we could fit the replicated bits into our
796 // immediate field for would be zero, and we prefer to use vxor for it.
797 if (ValSizeInBytes < ByteSize) return SDValue();
799 // If the element value is larger than the splat value, cut it in half and
800 // check to see if the two halves are equal. Continue doing this until we
801 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
802 while (ValSizeInBytes > ByteSize) {
803 ValSizeInBytes >>= 1;
805 // If the top half equals the bottom half, we're still ok.
806 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
807 (Value & ((1 << (8*ValSizeInBytes))-1)))
811 // Properly sign extend the value.
812 int ShAmt = (4-ByteSize)*8;
813 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
815 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
816 if (MaskVal == 0) return SDValue();
818 // Finally, if this value fits in a 5 bit sext field, return it
819 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
820 return DAG.getTargetConstant(MaskVal, MVT::i32);
824 //===----------------------------------------------------------------------===//
825 // Addressing Mode Selection
826 //===----------------------------------------------------------------------===//
828 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
829 /// or 64-bit immediate, and if the value can be accurately represented as a
830 /// sign extension from a 16-bit value. If so, this returns true and the
832 static bool isIntS16Immediate(SDNode *N, short &Imm) {
833 if (N->getOpcode() != ISD::Constant)
836 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
837 if (N->getValueType(0) == MVT::i32)
838 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
840 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
842 static bool isIntS16Immediate(SDValue Op, short &Imm) {
843 return isIntS16Immediate(Op.getNode(), Imm);
847 /// SelectAddressRegReg - Given the specified addressed, check to see if it
848 /// can be represented as an indexed [r+r] operation. Returns false if it
849 /// can be more efficiently represented with [r+imm].
850 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
852 SelectionDAG &DAG) const {
854 if (N.getOpcode() == ISD::ADD) {
855 if (isIntS16Immediate(N.getOperand(1), imm))
857 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
860 Base = N.getOperand(0);
861 Index = N.getOperand(1);
863 } else if (N.getOpcode() == ISD::OR) {
864 if (isIntS16Immediate(N.getOperand(1), imm))
865 return false; // r+i can fold it if we can.
867 // If this is an or of disjoint bitfields, we can codegen this as an add
868 // (for better address arithmetic) if the LHS and RHS of the OR are provably
870 APInt LHSKnownZero, LHSKnownOne;
871 APInt RHSKnownZero, RHSKnownOne;
872 DAG.ComputeMaskedBits(N.getOperand(0),
873 LHSKnownZero, LHSKnownOne);
875 if (LHSKnownZero.getBoolValue()) {
876 DAG.ComputeMaskedBits(N.getOperand(1),
877 RHSKnownZero, RHSKnownOne);
878 // If all of the bits are known zero on the LHS or RHS, the add won't
880 if (~(LHSKnownZero | RHSKnownZero) == 0) {
881 Base = N.getOperand(0);
882 Index = N.getOperand(1);
891 /// Returns true if the address N can be represented by a base register plus
892 /// a signed 16-bit displacement [r+imm], and if it is not better
893 /// represented as reg+reg.
894 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
896 SelectionDAG &DAG) const {
897 // FIXME dl should come from parent load or store, not from address
898 DebugLoc dl = N.getDebugLoc();
899 // If this can be more profitably realized as r+r, fail.
900 if (SelectAddressRegReg(N, Disp, Base, DAG))
903 if (N.getOpcode() == ISD::ADD) {
905 if (isIntS16Immediate(N.getOperand(1), imm)) {
906 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
907 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
908 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
910 Base = N.getOperand(0);
912 return true; // [r+i]
913 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
914 // Match LOAD (ADD (X, Lo(G))).
915 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
916 && "Cannot handle constant offsets yet!");
917 Disp = N.getOperand(1).getOperand(0); // The global address.
918 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
919 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
920 Disp.getOpcode() == ISD::TargetConstantPool ||
921 Disp.getOpcode() == ISD::TargetJumpTable);
922 Base = N.getOperand(0);
923 return true; // [&g+r]
925 } else if (N.getOpcode() == ISD::OR) {
927 if (isIntS16Immediate(N.getOperand(1), imm)) {
928 // If this is an or of disjoint bitfields, we can codegen this as an add
929 // (for better address arithmetic) if the LHS and RHS of the OR are
930 // provably disjoint.
931 APInt LHSKnownZero, LHSKnownOne;
932 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
934 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
935 // If all of the bits are known zero on the LHS or RHS, the add won't
937 Base = N.getOperand(0);
938 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
942 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
943 // Loading from a constant address.
945 // If this address fits entirely in a 16-bit sext immediate field, codegen
948 if (isIntS16Immediate(CN, Imm)) {
949 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
950 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
951 CN->getValueType(0));
955 // Handle 32-bit sext immediates with LIS + addr mode.
956 if (CN->getValueType(0) == MVT::i32 ||
957 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
958 int Addr = (int)CN->getZExtValue();
960 // Otherwise, break this down into an LIS + disp.
961 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
963 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
964 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
965 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
970 Disp = DAG.getTargetConstant(0, getPointerTy());
971 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
972 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
975 return true; // [r+0]
978 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
979 /// represented as an indexed [r+r] operation.
980 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
982 SelectionDAG &DAG) const {
983 // Check to see if we can easily represent this as an [r+r] address. This
984 // will fail if it thinks that the address is more profitably represented as
985 // reg+imm, e.g. where imm = 0.
986 if (SelectAddressRegReg(N, Base, Index, DAG))
989 // If the operand is an addition, always emit this as [r+r], since this is
990 // better (for code size, and execution, as the memop does the add for free)
991 // than emitting an explicit add.
992 if (N.getOpcode() == ISD::ADD) {
993 Base = N.getOperand(0);
994 Index = N.getOperand(1);
998 // Otherwise, do it the hard way, using R0 as the base register.
999 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
1005 /// SelectAddressRegImmShift - Returns true if the address N can be
1006 /// represented by a base register plus a signed 14-bit displacement
1007 /// [r+imm*4]. Suitable for use by STD and friends.
1008 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
1010 SelectionDAG &DAG) const {
1011 // FIXME dl should come from the parent load or store, not the address
1012 DebugLoc dl = N.getDebugLoc();
1013 // If this can be more profitably realized as r+r, fail.
1014 if (SelectAddressRegReg(N, Disp, Base, DAG))
1017 if (N.getOpcode() == ISD::ADD) {
1019 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1020 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1021 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1022 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1024 Base = N.getOperand(0);
1026 return true; // [r+i]
1027 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1028 // Match LOAD (ADD (X, Lo(G))).
1029 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1030 && "Cannot handle constant offsets yet!");
1031 Disp = N.getOperand(1).getOperand(0); // The global address.
1032 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1033 Disp.getOpcode() == ISD::TargetConstantPool ||
1034 Disp.getOpcode() == ISD::TargetJumpTable);
1035 Base = N.getOperand(0);
1036 return true; // [&g+r]
1038 } else if (N.getOpcode() == ISD::OR) {
1040 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1041 // If this is an or of disjoint bitfields, we can codegen this as an add
1042 // (for better address arithmetic) if the LHS and RHS of the OR are
1043 // provably disjoint.
1044 APInt LHSKnownZero, LHSKnownOne;
1045 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1046 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1047 // If all of the bits are known zero on the LHS or RHS, the add won't
1049 Base = N.getOperand(0);
1050 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1054 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1055 // Loading from a constant address. Verify low two bits are clear.
1056 if ((CN->getZExtValue() & 3) == 0) {
1057 // If this address fits entirely in a 14-bit sext immediate field, codegen
1060 if (isIntS16Immediate(CN, Imm)) {
1061 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1062 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
1063 CN->getValueType(0));
1067 // Fold the low-part of 32-bit absolute addresses into addr mode.
1068 if (CN->getValueType(0) == MVT::i32 ||
1069 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1070 int Addr = (int)CN->getZExtValue();
1072 // Otherwise, break this down into an LIS + disp.
1073 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1074 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1075 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1076 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1082 Disp = DAG.getTargetConstant(0, getPointerTy());
1083 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1084 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1087 return true; // [r+0]
1091 /// getPreIndexedAddressParts - returns true by value, base pointer and
1092 /// offset pointer and addressing mode by reference if the node's address
1093 /// can be legally represented as pre-indexed load / store address.
1094 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1096 ISD::MemIndexedMode &AM,
1097 SelectionDAG &DAG) const {
1098 if (DisablePPCPreinc) return false;
1102 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1103 Ptr = LD->getBasePtr();
1104 VT = LD->getMemoryVT();
1106 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1107 Ptr = ST->getBasePtr();
1108 VT = ST->getMemoryVT();
1112 // PowerPC doesn't have preinc load/store instructions for vectors.
1116 if (SelectAddressRegReg(Ptr, Offset, Base, DAG)) {
1121 // LDU/STU use reg+imm*4, others use reg+imm.
1122 if (VT != MVT::i64) {
1124 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1128 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1132 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1133 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1134 // sext i32 to i64 when addr mode is r+i.
1135 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1136 LD->getExtensionType() == ISD::SEXTLOAD &&
1137 isa<ConstantSDNode>(Offset))
1145 //===----------------------------------------------------------------------===//
1146 // LowerOperation implementation
1147 //===----------------------------------------------------------------------===//
1149 /// GetLabelAccessInfo - Return true if we should reference labels using a
1150 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1151 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1152 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1153 HiOpFlags = PPCII::MO_HA16;
1154 LoOpFlags = PPCII::MO_LO16;
1156 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1157 // non-darwin platform. We don't support PIC on other platforms yet.
1158 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1159 TM.getSubtarget<PPCSubtarget>().isDarwin();
1161 HiOpFlags |= PPCII::MO_PIC_FLAG;
1162 LoOpFlags |= PPCII::MO_PIC_FLAG;
1165 // If this is a reference to a global value that requires a non-lazy-ptr, make
1166 // sure that instruction lowering adds it.
1167 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1168 HiOpFlags |= PPCII::MO_NLP_FLAG;
1169 LoOpFlags |= PPCII::MO_NLP_FLAG;
1171 if (GV->hasHiddenVisibility()) {
1172 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1173 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1180 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1181 SelectionDAG &DAG) {
1182 EVT PtrVT = HiPart.getValueType();
1183 SDValue Zero = DAG.getConstant(0, PtrVT);
1184 DebugLoc DL = HiPart.getDebugLoc();
1186 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1187 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1189 // With PIC, the first instruction is actually "GR+hi(&G)".
1191 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1192 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1194 // Generate non-pic code that has direct accesses to the constant pool.
1195 // The address of the global is just (hi(&g)+lo(&g)).
1196 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1199 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1200 SelectionDAG &DAG) const {
1201 EVT PtrVT = Op.getValueType();
1202 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1203 const Constant *C = CP->getConstVal();
1205 unsigned MOHiFlag, MOLoFlag;
1206 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1208 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1210 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1211 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1214 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1215 EVT PtrVT = Op.getValueType();
1216 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1218 unsigned MOHiFlag, MOLoFlag;
1219 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1220 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1221 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1222 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1225 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1226 SelectionDAG &DAG) const {
1227 EVT PtrVT = Op.getValueType();
1229 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1231 unsigned MOHiFlag, MOLoFlag;
1232 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1233 SDValue TgtBAHi = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOHiFlag);
1234 SDValue TgtBALo = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOLoFlag);
1235 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1238 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1239 SelectionDAG &DAG) const {
1241 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1242 DebugLoc dl = GA->getDebugLoc();
1243 const GlobalValue *GV = GA->getGlobal();
1244 EVT PtrVT = getPointerTy();
1245 bool is64bit = PPCSubTarget.isPPC64();
1247 TLSModel::Model model = getTargetMachine().getTLSModel(GV);
1249 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1250 PPCII::MO_TPREL16_HA);
1251 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1252 PPCII::MO_TPREL16_LO);
1254 if (model != TLSModel::LocalExec)
1255 llvm_unreachable("only local-exec TLS mode supported");
1256 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1257 is64bit ? MVT::i64 : MVT::i32);
1258 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1259 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1262 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1263 SelectionDAG &DAG) const {
1264 EVT PtrVT = Op.getValueType();
1265 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1266 DebugLoc DL = GSDN->getDebugLoc();
1267 const GlobalValue *GV = GSDN->getGlobal();
1269 // 64-bit SVR4 ABI code is always position-independent.
1270 // The actual address of the GlobalValue is stored in the TOC.
1271 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1272 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1273 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1274 DAG.getRegister(PPC::X2, MVT::i64));
1277 unsigned MOHiFlag, MOLoFlag;
1278 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1281 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1283 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1285 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1287 // If the global reference is actually to a non-lazy-pointer, we have to do an
1288 // extra load to get the address of the global.
1289 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1290 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1291 false, false, false, 0);
1295 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1296 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1297 DebugLoc dl = Op.getDebugLoc();
1299 // If we're comparing for equality to zero, expose the fact that this is
1300 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1301 // fold the new nodes.
1302 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1303 if (C->isNullValue() && CC == ISD::SETEQ) {
1304 EVT VT = Op.getOperand(0).getValueType();
1305 SDValue Zext = Op.getOperand(0);
1306 if (VT.bitsLT(MVT::i32)) {
1308 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1310 unsigned Log2b = Log2_32(VT.getSizeInBits());
1311 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1312 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1313 DAG.getConstant(Log2b, MVT::i32));
1314 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1316 // Leave comparisons against 0 and -1 alone for now, since they're usually
1317 // optimized. FIXME: revisit this when we can custom lower all setcc
1319 if (C->isAllOnesValue() || C->isNullValue())
1323 // If we have an integer seteq/setne, turn it into a compare against zero
1324 // by xor'ing the rhs with the lhs, which is faster than setting a
1325 // condition register, reading it back out, and masking the correct bit. The
1326 // normal approach here uses sub to do this instead of xor. Using xor exposes
1327 // the result to other bit-twiddling opportunities.
1328 EVT LHSVT = Op.getOperand(0).getValueType();
1329 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1330 EVT VT = Op.getValueType();
1331 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1333 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1338 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1339 const PPCSubtarget &Subtarget) const {
1340 SDNode *Node = Op.getNode();
1341 EVT VT = Node->getValueType(0);
1342 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1343 SDValue InChain = Node->getOperand(0);
1344 SDValue VAListPtr = Node->getOperand(1);
1345 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1346 DebugLoc dl = Node->getDebugLoc();
1348 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1351 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1352 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1354 InChain = GprIndex.getValue(1);
1356 if (VT == MVT::i64) {
1357 // Check if GprIndex is even
1358 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1359 DAG.getConstant(1, MVT::i32));
1360 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1361 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1362 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1363 DAG.getConstant(1, MVT::i32));
1364 // Align GprIndex to be even if it isn't
1365 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1369 // fpr index is 1 byte after gpr
1370 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1371 DAG.getConstant(1, MVT::i32));
1374 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1375 FprPtr, MachinePointerInfo(SV), MVT::i8,
1377 InChain = FprIndex.getValue(1);
1379 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1380 DAG.getConstant(8, MVT::i32));
1382 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1383 DAG.getConstant(4, MVT::i32));
1386 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1387 MachinePointerInfo(), false, false,
1389 InChain = OverflowArea.getValue(1);
1391 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1392 MachinePointerInfo(), false, false,
1394 InChain = RegSaveArea.getValue(1);
1396 // select overflow_area if index > 8
1397 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1398 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1400 // adjustment constant gpr_index * 4/8
1401 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1402 VT.isInteger() ? GprIndex : FprIndex,
1403 DAG.getConstant(VT.isInteger() ? 4 : 8,
1406 // OurReg = RegSaveArea + RegConstant
1407 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1410 // Floating types are 32 bytes into RegSaveArea
1411 if (VT.isFloatingPoint())
1412 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1413 DAG.getConstant(32, MVT::i32));
1415 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1416 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1417 VT.isInteger() ? GprIndex : FprIndex,
1418 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1421 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1422 VT.isInteger() ? VAListPtr : FprPtr,
1423 MachinePointerInfo(SV),
1424 MVT::i8, false, false, 0);
1426 // determine if we should load from reg_save_area or overflow_area
1427 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1429 // increase overflow_area by 4/8 if gpr/fpr > 8
1430 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1431 DAG.getConstant(VT.isInteger() ? 4 : 8,
1434 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1437 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1439 MachinePointerInfo(),
1440 MVT::i32, false, false, 0);
1442 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1443 false, false, false, 0);
1446 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1447 SelectionDAG &DAG) const {
1448 return Op.getOperand(0);
1451 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1452 SelectionDAG &DAG) const {
1453 SDValue Chain = Op.getOperand(0);
1454 SDValue Trmp = Op.getOperand(1); // trampoline
1455 SDValue FPtr = Op.getOperand(2); // nested function
1456 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1457 DebugLoc dl = Op.getDebugLoc();
1459 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1460 bool isPPC64 = (PtrVT == MVT::i64);
1462 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType(
1465 TargetLowering::ArgListTy Args;
1466 TargetLowering::ArgListEntry Entry;
1468 Entry.Ty = IntPtrTy;
1469 Entry.Node = Trmp; Args.push_back(Entry);
1471 // TrampSize == (isPPC64 ? 48 : 40);
1472 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1473 isPPC64 ? MVT::i64 : MVT::i32);
1474 Args.push_back(Entry);
1476 Entry.Node = FPtr; Args.push_back(Entry);
1477 Entry.Node = Nest; Args.push_back(Entry);
1479 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1480 TargetLowering::CallLoweringInfo CLI(Chain,
1481 Type::getVoidTy(*DAG.getContext()),
1482 false, false, false, false, 0,
1484 /*isTailCall=*/false,
1485 /*doesNotRet=*/false,
1486 /*isReturnValueUsed=*/true,
1487 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1489 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1491 return CallResult.second;
1494 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1495 const PPCSubtarget &Subtarget) const {
1496 MachineFunction &MF = DAG.getMachineFunction();
1497 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1499 DebugLoc dl = Op.getDebugLoc();
1501 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1502 // vastart just stores the address of the VarArgsFrameIndex slot into the
1503 // memory location argument.
1504 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1505 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1506 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1507 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1508 MachinePointerInfo(SV),
1512 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1513 // We suppose the given va_list is already allocated.
1516 // char gpr; /* index into the array of 8 GPRs
1517 // * stored in the register save area
1518 // * gpr=0 corresponds to r3,
1519 // * gpr=1 to r4, etc.
1521 // char fpr; /* index into the array of 8 FPRs
1522 // * stored in the register save area
1523 // * fpr=0 corresponds to f1,
1524 // * fpr=1 to f2, etc.
1526 // char *overflow_arg_area;
1527 // /* location on stack that holds
1528 // * the next overflow argument
1530 // char *reg_save_area;
1531 // /* where r3:r10 and f1:f8 (if saved)
1537 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1538 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1541 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1543 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1545 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1548 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1549 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1551 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1552 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1554 uint64_t FPROffset = 1;
1555 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1557 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1559 // Store first byte : number of int regs
1560 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1562 MachinePointerInfo(SV),
1563 MVT::i8, false, false, 0);
1564 uint64_t nextOffset = FPROffset;
1565 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1568 // Store second byte : number of float regs
1569 SDValue secondStore =
1570 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1571 MachinePointerInfo(SV, nextOffset), MVT::i8,
1573 nextOffset += StackOffset;
1574 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1576 // Store second word : arguments given on stack
1577 SDValue thirdStore =
1578 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1579 MachinePointerInfo(SV, nextOffset),
1581 nextOffset += FrameOffset;
1582 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1584 // Store third word : arguments given in registers
1585 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1586 MachinePointerInfo(SV, nextOffset),
1591 #include "PPCGenCallingConv.inc"
1593 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1594 CCValAssign::LocInfo &LocInfo,
1595 ISD::ArgFlagsTy &ArgFlags,
1600 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1602 CCValAssign::LocInfo &LocInfo,
1603 ISD::ArgFlagsTy &ArgFlags,
1605 static const uint16_t ArgRegs[] = {
1606 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1607 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1609 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1611 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1613 // Skip one register if the first unallocated register has an even register
1614 // number and there are still argument registers available which have not been
1615 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1616 // need to skip a register if RegNum is odd.
1617 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1618 State.AllocateReg(ArgRegs[RegNum]);
1621 // Always return false here, as this function only makes sure that the first
1622 // unallocated register has an odd register number and does not actually
1623 // allocate a register for the current argument.
1627 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1629 CCValAssign::LocInfo &LocInfo,
1630 ISD::ArgFlagsTy &ArgFlags,
1632 static const uint16_t ArgRegs[] = {
1633 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1637 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1639 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1641 // If there is only one Floating-point register left we need to put both f64
1642 // values of a split ppc_fp128 value on the stack.
1643 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1644 State.AllocateReg(ArgRegs[RegNum]);
1647 // Always return false here, as this function only makes sure that the two f64
1648 // values a ppc_fp128 value is split into are both passed in registers or both
1649 // passed on the stack and does not actually allocate a register for the
1650 // current argument.
1654 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1656 static const uint16_t *GetFPR() {
1657 static const uint16_t FPR[] = {
1658 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1659 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1665 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1667 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1668 unsigned PtrByteSize) {
1669 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1670 if (Flags.isByVal())
1671 ArgSize = Flags.getByValSize();
1672 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1678 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1679 CallingConv::ID CallConv, bool isVarArg,
1680 const SmallVectorImpl<ISD::InputArg>
1682 DebugLoc dl, SelectionDAG &DAG,
1683 SmallVectorImpl<SDValue> &InVals)
1685 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
1686 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins,
1689 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1695 PPCTargetLowering::LowerFormalArguments_SVR4(
1697 CallingConv::ID CallConv, bool isVarArg,
1698 const SmallVectorImpl<ISD::InputArg>
1700 DebugLoc dl, SelectionDAG &DAG,
1701 SmallVectorImpl<SDValue> &InVals) const {
1703 // 32-bit SVR4 ABI Stack Frame Layout:
1704 // +-----------------------------------+
1705 // +--> | Back chain |
1706 // | +-----------------------------------+
1707 // | | Floating-point register save area |
1708 // | +-----------------------------------+
1709 // | | General register save area |
1710 // | +-----------------------------------+
1711 // | | CR save word |
1712 // | +-----------------------------------+
1713 // | | VRSAVE save word |
1714 // | +-----------------------------------+
1715 // | | Alignment padding |
1716 // | +-----------------------------------+
1717 // | | Vector register save area |
1718 // | +-----------------------------------+
1719 // | | Local variable space |
1720 // | +-----------------------------------+
1721 // | | Parameter list area |
1722 // | +-----------------------------------+
1723 // | | LR save word |
1724 // | +-----------------------------------+
1725 // SP--> +--- | Back chain |
1726 // +-----------------------------------+
1729 // System V Application Binary Interface PowerPC Processor Supplement
1730 // AltiVec Technology Programming Interface Manual
1732 MachineFunction &MF = DAG.getMachineFunction();
1733 MachineFrameInfo *MFI = MF.getFrameInfo();
1734 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1736 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1737 // Potential tail calls could cause overwriting of argument stack slots.
1738 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1739 (CallConv == CallingConv::Fast));
1740 unsigned PtrByteSize = 4;
1742 // Assign locations to all of the incoming arguments.
1743 SmallVector<CCValAssign, 16> ArgLocs;
1744 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1745 getTargetMachine(), ArgLocs, *DAG.getContext());
1747 // Reserve space for the linkage area on the stack.
1748 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
1750 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4);
1752 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1753 CCValAssign &VA = ArgLocs[i];
1755 // Arguments stored in registers.
1756 if (VA.isRegLoc()) {
1757 const TargetRegisterClass *RC;
1758 EVT ValVT = VA.getValVT();
1760 switch (ValVT.getSimpleVT().SimpleTy) {
1762 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1764 RC = &PPC::GPRCRegClass;
1767 RC = &PPC::F4RCRegClass;
1770 RC = &PPC::F8RCRegClass;
1776 RC = &PPC::VRRCRegClass;
1780 // Transform the arguments stored in physical registers into virtual ones.
1781 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1782 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1784 InVals.push_back(ArgValue);
1786 // Argument stored in memory.
1787 assert(VA.isMemLoc());
1789 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1790 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1793 // Create load nodes to retrieve arguments from the stack.
1794 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1795 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1796 MachinePointerInfo(),
1797 false, false, false, 0));
1801 // Assign locations to all of the incoming aggregate by value arguments.
1802 // Aggregates passed by value are stored in the local variable space of the
1803 // caller's stack frame, right above the parameter list area.
1804 SmallVector<CCValAssign, 16> ByValArgLocs;
1805 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1806 getTargetMachine(), ByValArgLocs, *DAG.getContext());
1808 // Reserve stack space for the allocations in CCInfo.
1809 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1811 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal);
1813 // Area that is at least reserved in the caller of this function.
1814 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1816 // Set the size that is at least reserved in caller of this function. Tail
1817 // call optimized function's reserved stack space needs to be aligned so that
1818 // taking the difference between two stack areas will result in an aligned
1820 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1823 std::max(MinReservedArea,
1824 PPCFrameLowering::getMinCallFrameSize(false, false));
1826 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
1827 getStackAlignment();
1828 unsigned AlignMask = TargetAlign-1;
1829 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1831 FI->setMinReservedArea(MinReservedArea);
1833 SmallVector<SDValue, 8> MemOps;
1835 // If the function takes variable number of arguments, make a frame index for
1836 // the start of the first vararg value... for expansion of llvm.va_start.
1838 static const uint16_t GPArgRegs[] = {
1839 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1840 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1842 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
1844 static const uint16_t FPArgRegs[] = {
1845 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1848 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
1850 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
1852 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
1855 // Make room for NumGPArgRegs and NumFPArgRegs.
1856 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
1857 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
1859 FuncInfo->setVarArgsStackOffset(
1860 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1861 CCInfo.getNextStackOffset(), true));
1863 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
1864 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1866 // The fixed integer arguments of a variadic function are stored to the
1867 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
1868 // the result of va_next.
1869 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
1870 // Get an existing live-in vreg, or add a new one.
1871 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
1873 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
1875 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1876 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1877 MachinePointerInfo(), false, false, 0);
1878 MemOps.push_back(Store);
1879 // Increment the address by four for the next argument to store
1880 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1881 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1884 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
1886 // The double arguments are stored to the VarArgsFrameIndex
1888 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
1889 // Get an existing live-in vreg, or add a new one.
1890 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
1892 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
1894 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
1895 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1896 MachinePointerInfo(), false, false, 0);
1897 MemOps.push_back(Store);
1898 // Increment the address by eight for the next argument to store
1899 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1901 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1905 if (!MemOps.empty())
1906 Chain = DAG.getNode(ISD::TokenFactor, dl,
1907 MVT::Other, &MemOps[0], MemOps.size());
1913 PPCTargetLowering::LowerFormalArguments_Darwin(
1915 CallingConv::ID CallConv, bool isVarArg,
1916 const SmallVectorImpl<ISD::InputArg>
1918 DebugLoc dl, SelectionDAG &DAG,
1919 SmallVectorImpl<SDValue> &InVals) const {
1920 // TODO: add description of PPC stack frame format, or at least some docs.
1922 MachineFunction &MF = DAG.getMachineFunction();
1923 MachineFrameInfo *MFI = MF.getFrameInfo();
1924 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1926 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1927 bool isPPC64 = PtrVT == MVT::i64;
1928 // Potential tail calls could cause overwriting of argument stack slots.
1929 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1930 (CallConv == CallingConv::Fast));
1931 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1933 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
1934 // Area that is at least reserved in caller of this function.
1935 unsigned MinReservedArea = ArgOffset;
1937 static const uint16_t GPR_32[] = { // 32-bit registers.
1938 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1939 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1941 static const uint16_t GPR_64[] = { // 64-bit registers.
1942 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1943 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1946 static const uint16_t *FPR = GetFPR();
1948 static const uint16_t VR[] = {
1949 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1950 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1953 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1954 const unsigned Num_FPR_Regs = 13;
1955 const unsigned Num_VR_Regs = array_lengthof( VR);
1957 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1959 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
1961 // In 32-bit non-varargs functions, the stack space for vectors is after the
1962 // stack space for non-vectors. We do not use this space unless we have
1963 // too many vectors to fit in registers, something that only occurs in
1964 // constructed examples:), but we have to walk the arglist to figure
1965 // that out...for the pathological case, compute VecArgOffset as the
1966 // start of the vector parameter area. Computing VecArgOffset is the
1967 // entire point of the following loop.
1968 unsigned VecArgOffset = ArgOffset;
1969 if (!isVarArg && !isPPC64) {
1970 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
1972 EVT ObjectVT = Ins[ArgNo].VT;
1973 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1975 if (Flags.isByVal()) {
1976 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1977 unsigned ObjSize = Flags.getByValSize();
1979 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1980 VecArgOffset += ArgSize;
1984 switch(ObjectVT.getSimpleVT().SimpleTy) {
1985 default: llvm_unreachable("Unhandled argument type!");
1988 VecArgOffset += isPPC64 ? 8 : 4;
1990 case MVT::i64: // PPC64
1998 // Nothing to do, we're only looking at Nonvector args here.
2003 // We've found where the vector parameter area in memory is. Skip the
2004 // first 12 parameters; these don't use that memory.
2005 VecArgOffset = ((VecArgOffset+15)/16)*16;
2006 VecArgOffset += 12*16;
2008 // Add DAG nodes to load the arguments or copy them out of registers. On
2009 // entry to a function on PPC, the arguments start after the linkage area,
2010 // although the first ones are often in registers.
2012 SmallVector<SDValue, 8> MemOps;
2013 unsigned nAltivecParamsAtEnd = 0;
2014 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2016 bool needsLoad = false;
2017 EVT ObjectVT = Ins[ArgNo].VT;
2018 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2019 unsigned ArgSize = ObjSize;
2020 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2022 unsigned CurArgOffset = ArgOffset;
2024 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2025 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2026 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2027 if (isVarArg || isPPC64) {
2028 MinReservedArea = ((MinReservedArea+15)/16)*16;
2029 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2032 } else nAltivecParamsAtEnd++;
2034 // Calculate min reserved area.
2035 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2039 // FIXME the codegen can be much improved in some cases.
2040 // We do not have to keep everything in memory.
2041 if (Flags.isByVal()) {
2042 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2043 ObjSize = Flags.getByValSize();
2044 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2045 // Objects of size 1 and 2 are right justified, everything else is
2046 // left justified. This means the memory address is adjusted forwards.
2047 if (ObjSize==1 || ObjSize==2) {
2048 CurArgOffset = CurArgOffset + (4 - ObjSize);
2050 // The value of the object is its address.
2051 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2052 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2053 InVals.push_back(FIN);
2054 if (ObjSize==1 || ObjSize==2) {
2055 if (GPR_idx != Num_GPR_Regs) {
2058 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2060 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2061 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2062 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2063 MachinePointerInfo(),
2064 ObjSize==1 ? MVT::i8 : MVT::i16,
2066 MemOps.push_back(Store);
2070 ArgOffset += PtrByteSize;
2074 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2075 // Store whatever pieces of the object are in registers
2076 // to memory. ArgVal will be address of the beginning of
2078 if (GPR_idx != Num_GPR_Regs) {
2081 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2083 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2084 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2085 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2086 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2087 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2088 MachinePointerInfo(),
2090 MemOps.push_back(Store);
2092 ArgOffset += PtrByteSize;
2094 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2101 switch (ObjectVT.getSimpleVT().SimpleTy) {
2102 default: llvm_unreachable("Unhandled argument type!");
2105 if (GPR_idx != Num_GPR_Regs) {
2106 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2107 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2111 ArgSize = PtrByteSize;
2113 // All int arguments reserve stack space in the Darwin ABI.
2114 ArgOffset += PtrByteSize;
2118 case MVT::i64: // PPC64
2119 if (GPR_idx != Num_GPR_Regs) {
2120 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2121 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2123 if (ObjectVT == MVT::i32) {
2124 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2125 // value to MVT::i64 and then truncate to the correct register size.
2127 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2128 DAG.getValueType(ObjectVT));
2129 else if (Flags.isZExt())
2130 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2131 DAG.getValueType(ObjectVT));
2133 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2139 ArgSize = PtrByteSize;
2141 // All int arguments reserve stack space in the Darwin ABI.
2147 // Every 4 bytes of argument space consumes one of the GPRs available for
2148 // argument passing.
2149 if (GPR_idx != Num_GPR_Regs) {
2151 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2154 if (FPR_idx != Num_FPR_Regs) {
2157 if (ObjectVT == MVT::f32)
2158 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2160 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2162 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2168 // All FP arguments reserve stack space in the Darwin ABI.
2169 ArgOffset += isPPC64 ? 8 : ObjSize;
2175 // Note that vector arguments in registers don't reserve stack space,
2176 // except in varargs functions.
2177 if (VR_idx != Num_VR_Regs) {
2178 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2179 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2181 while ((ArgOffset % 16) != 0) {
2182 ArgOffset += PtrByteSize;
2183 if (GPR_idx != Num_GPR_Regs)
2187 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2191 if (!isVarArg && !isPPC64) {
2192 // Vectors go after all the nonvectors.
2193 CurArgOffset = VecArgOffset;
2196 // Vectors are aligned.
2197 ArgOffset = ((ArgOffset+15)/16)*16;
2198 CurArgOffset = ArgOffset;
2206 // We need to load the argument to a virtual register if we determined above
2207 // that we ran out of physical registers of the appropriate type.
2209 int FI = MFI->CreateFixedObject(ObjSize,
2210 CurArgOffset + (ArgSize - ObjSize),
2212 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2213 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2214 false, false, false, 0);
2217 InVals.push_back(ArgVal);
2220 // Set the size that is at least reserved in caller of this function. Tail
2221 // call optimized function's reserved stack space needs to be aligned so that
2222 // taking the difference between two stack areas will result in an aligned
2224 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2225 // Add the Altivec parameters at the end, if needed.
2226 if (nAltivecParamsAtEnd) {
2227 MinReservedArea = ((MinReservedArea+15)/16)*16;
2228 MinReservedArea += 16*nAltivecParamsAtEnd;
2231 std::max(MinReservedArea,
2232 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2233 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2234 getStackAlignment();
2235 unsigned AlignMask = TargetAlign-1;
2236 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2237 FI->setMinReservedArea(MinReservedArea);
2239 // If the function takes variable number of arguments, make a frame index for
2240 // the start of the first vararg value... for expansion of llvm.va_start.
2242 int Depth = ArgOffset;
2244 FuncInfo->setVarArgsFrameIndex(
2245 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2247 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2249 // If this function is vararg, store any remaining integer argument regs
2250 // to their spots on the stack so that they may be loaded by deferencing the
2251 // result of va_next.
2252 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2256 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2258 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2260 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2261 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2262 MachinePointerInfo(), false, false, 0);
2263 MemOps.push_back(Store);
2264 // Increment the address by four for the next argument to store
2265 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2266 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2270 if (!MemOps.empty())
2271 Chain = DAG.getNode(ISD::TokenFactor, dl,
2272 MVT::Other, &MemOps[0], MemOps.size());
2277 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
2278 /// linkage area for the Darwin ABI.
2280 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2284 const SmallVectorImpl<ISD::OutputArg>
2286 const SmallVectorImpl<SDValue> &OutVals,
2287 unsigned &nAltivecParamsAtEnd) {
2288 // Count how many bytes are to be pushed on the stack, including the linkage
2289 // area, and parameter passing area. We start with 24/48 bytes, which is
2290 // prereserved space for [SP][CR][LR][3 x unused].
2291 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2292 unsigned NumOps = Outs.size();
2293 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2295 // Add up all the space actually used.
2296 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2297 // they all go in registers, but we must reserve stack space for them for
2298 // possible use by the caller. In varargs or 64-bit calls, parameters are
2299 // assigned stack space in order, with padding so Altivec parameters are
2301 nAltivecParamsAtEnd = 0;
2302 for (unsigned i = 0; i != NumOps; ++i) {
2303 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2304 EVT ArgVT = Outs[i].VT;
2305 // Varargs Altivec parameters are padded to a 16 byte boundary.
2306 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2307 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2308 if (!isVarArg && !isPPC64) {
2309 // Non-varargs Altivec parameters go after all the non-Altivec
2310 // parameters; handle those later so we know how much padding we need.
2311 nAltivecParamsAtEnd++;
2314 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2315 NumBytes = ((NumBytes+15)/16)*16;
2317 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2320 // Allow for Altivec parameters at the end, if needed.
2321 if (nAltivecParamsAtEnd) {
2322 NumBytes = ((NumBytes+15)/16)*16;
2323 NumBytes += 16*nAltivecParamsAtEnd;
2326 // The prolog code of the callee may store up to 8 GPR argument registers to
2327 // the stack, allowing va_start to index over them in memory if its varargs.
2328 // Because we cannot tell if this is needed on the caller side, we have to
2329 // conservatively assume that it is needed. As such, make sure we have at
2330 // least enough stack space for the caller to store the 8 GPRs.
2331 NumBytes = std::max(NumBytes,
2332 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2334 // Tail call needs the stack to be aligned.
2335 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2336 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2337 getFrameLowering()->getStackAlignment();
2338 unsigned AlignMask = TargetAlign-1;
2339 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2345 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2346 /// adjusted to accommodate the arguments for the tailcall.
2347 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2348 unsigned ParamSize) {
2350 if (!isTailCall) return 0;
2352 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2353 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2354 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2355 // Remember only if the new adjustement is bigger.
2356 if (SPDiff < FI->getTailCallSPDelta())
2357 FI->setTailCallSPDelta(SPDiff);
2362 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2363 /// for tail call optimization. Targets which want to do tail call
2364 /// optimization should implement this function.
2366 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2367 CallingConv::ID CalleeCC,
2369 const SmallVectorImpl<ISD::InputArg> &Ins,
2370 SelectionDAG& DAG) const {
2371 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2374 // Variable argument functions are not supported.
2378 MachineFunction &MF = DAG.getMachineFunction();
2379 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2380 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2381 // Functions containing by val parameters are not supported.
2382 for (unsigned i = 0; i != Ins.size(); i++) {
2383 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2384 if (Flags.isByVal()) return false;
2387 // Non PIC/GOT tail calls are supported.
2388 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2391 // At the moment we can only do local tail calls (in same module, hidden
2392 // or protected) if we are generating PIC.
2393 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2394 return G->getGlobal()->hasHiddenVisibility()
2395 || G->getGlobal()->hasProtectedVisibility();
2401 /// isCallCompatibleAddress - Return the immediate to use if the specified
2402 /// 32-bit value is representable in the immediate field of a BxA instruction.
2403 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2404 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2407 int Addr = C->getZExtValue();
2408 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2409 (Addr << 6 >> 6) != Addr)
2410 return 0; // Top 6 bits have to be sext of immediate.
2412 return DAG.getConstant((int)C->getZExtValue() >> 2,
2413 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2418 struct TailCallArgumentInfo {
2423 TailCallArgumentInfo() : FrameIdx(0) {}
2428 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2430 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2432 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2433 SmallVector<SDValue, 8> &MemOpChains,
2435 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2436 SDValue Arg = TailCallArgs[i].Arg;
2437 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2438 int FI = TailCallArgs[i].FrameIdx;
2439 // Store relative to framepointer.
2440 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2441 MachinePointerInfo::getFixedStack(FI),
2446 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2447 /// the appropriate stack slot for the tail call optimized function call.
2448 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2449 MachineFunction &MF,
2458 // Calculate the new stack slot for the return address.
2459 int SlotSize = isPPC64 ? 8 : 4;
2460 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
2462 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2463 NewRetAddrLoc, true);
2464 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2465 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2466 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2467 MachinePointerInfo::getFixedStack(NewRetAddr),
2470 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2471 // slot as the FP is never overwritten.
2474 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2475 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
2477 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2478 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2479 MachinePointerInfo::getFixedStack(NewFPIdx),
2486 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2487 /// the position of the argument.
2489 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2490 SDValue Arg, int SPDiff, unsigned ArgOffset,
2491 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2492 int Offset = ArgOffset + SPDiff;
2493 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2494 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2495 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2496 SDValue FIN = DAG.getFrameIndex(FI, VT);
2497 TailCallArgumentInfo Info;
2499 Info.FrameIdxOp = FIN;
2501 TailCallArguments.push_back(Info);
2504 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2505 /// stack slot. Returns the chain as result and the loaded frame pointers in
2506 /// LROpOut/FPOpout. Used when tail calling.
2507 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2513 DebugLoc dl) const {
2515 // Load the LR and FP stack slot for later adjusting.
2516 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2517 LROpOut = getReturnAddrFrameIndex(DAG);
2518 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
2519 false, false, false, 0);
2520 Chain = SDValue(LROpOut.getNode(), 1);
2522 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
2523 // slot as the FP is never overwritten.
2525 FPOpOut = getFramePointerFrameIndex(DAG);
2526 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
2527 false, false, false, 0);
2528 Chain = SDValue(FPOpOut.getNode(), 1);
2534 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2535 /// by "Src" to address "Dst" of size "Size". Alignment information is
2536 /// specified by the specific parameter attribute. The copy will be passed as
2537 /// a byval function parameter.
2538 /// Sometimes what we are copying is the end of a larger object, the part that
2539 /// does not fit in registers.
2541 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2542 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2544 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2545 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2546 false, false, MachinePointerInfo(0),
2547 MachinePointerInfo(0));
2550 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2553 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2554 SDValue Arg, SDValue PtrOff, int SPDiff,
2555 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2556 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2557 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
2559 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2564 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2566 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2567 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2568 DAG.getConstant(ArgOffset, PtrVT));
2570 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2571 MachinePointerInfo(), false, false, 0));
2572 // Calculate and remember argument location.
2573 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2578 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
2579 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
2580 SDValue LROp, SDValue FPOp, bool isDarwinABI,
2581 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
2582 MachineFunction &MF = DAG.getMachineFunction();
2584 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2585 // might overwrite each other in case of tail call optimization.
2586 SmallVector<SDValue, 8> MemOpChains2;
2587 // Do not flag preceding copytoreg stuff together with the following stuff.
2589 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2591 if (!MemOpChains2.empty())
2592 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2593 &MemOpChains2[0], MemOpChains2.size());
2595 // Store the return address to the appropriate stack slot.
2596 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2597 isPPC64, isDarwinABI, dl);
2599 // Emit callseq_end just before tailcall node.
2600 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2601 DAG.getIntPtrConstant(0, true), InFlag);
2602 InFlag = Chain.getValue(1);
2606 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
2607 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
2608 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
2609 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
2610 const PPCSubtarget &PPCSubTarget) {
2612 bool isPPC64 = PPCSubTarget.isPPC64();
2613 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
2615 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2616 NodeTys.push_back(MVT::Other); // Returns a chain
2617 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
2619 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
2621 bool needIndirectCall = true;
2622 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
2623 // If this is an absolute destination address, use the munged value.
2624 Callee = SDValue(Dest, 0);
2625 needIndirectCall = false;
2628 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2629 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
2630 // Use indirect calls for ALL functions calls in JIT mode, since the
2631 // far-call stubs may be outside relocation limits for a BL instruction.
2632 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
2633 unsigned OpFlags = 0;
2634 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
2635 (PPCSubTarget.getTargetTriple().isMacOSX() &&
2636 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
2637 (G->getGlobal()->isDeclaration() ||
2638 G->getGlobal()->isWeakForLinker())) {
2639 // PC-relative references to external symbols should go through $stub,
2640 // unless we're building with the leopard linker or later, which
2641 // automatically synthesizes these stubs.
2642 OpFlags = PPCII::MO_DARWIN_STUB;
2645 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
2646 // every direct call is) turn it into a TargetGlobalAddress /
2647 // TargetExternalSymbol node so that legalize doesn't hack it.
2648 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2649 Callee.getValueType(),
2651 needIndirectCall = false;
2655 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2656 unsigned char OpFlags = 0;
2658 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
2659 (PPCSubTarget.getTargetTriple().isMacOSX() &&
2660 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
2661 // PC-relative references to external symbols should go through $stub,
2662 // unless we're building with the leopard linker or later, which
2663 // automatically synthesizes these stubs.
2664 OpFlags = PPCII::MO_DARWIN_STUB;
2667 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
2669 needIndirectCall = false;
2672 if (needIndirectCall) {
2673 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2674 // to do the call, we can't use PPCISD::CALL.
2675 SDValue MTCTROps[] = {Chain, Callee, InFlag};
2677 if (isSVR4ABI && isPPC64) {
2678 // Function pointers in the 64-bit SVR4 ABI do not point to the function
2679 // entry point, but to the function descriptor (the function entry point
2680 // address is part of the function descriptor though).
2681 // The function descriptor is a three doubleword structure with the
2682 // following fields: function entry point, TOC base address and
2683 // environment pointer.
2684 // Thus for a call through a function pointer, the following actions need
2686 // 1. Save the TOC of the caller in the TOC save area of its stack
2687 // frame (this is done in LowerCall_Darwin()).
2688 // 2. Load the address of the function entry point from the function
2690 // 3. Load the TOC of the callee from the function descriptor into r2.
2691 // 4. Load the environment pointer from the function descriptor into
2693 // 5. Branch to the function entry point address.
2694 // 6. On return of the callee, the TOC of the caller needs to be
2695 // restored (this is done in FinishCall()).
2697 // All those operations are flagged together to ensure that no other
2698 // operations can be scheduled in between. E.g. without flagging the
2699 // operations together, a TOC access in the caller could be scheduled
2700 // between the load of the callee TOC and the branch to the callee, which
2701 // results in the TOC access going through the TOC of the callee instead
2702 // of going through the TOC of the caller, which leads to incorrect code.
2704 // Load the address of the function entry point from the function
2706 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
2707 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
2708 InFlag.getNode() ? 3 : 2);
2709 Chain = LoadFuncPtr.getValue(1);
2710 InFlag = LoadFuncPtr.getValue(2);
2712 // Load environment pointer into r11.
2713 // Offset of the environment pointer within the function descriptor.
2714 SDValue PtrOff = DAG.getIntPtrConstant(16);
2716 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
2717 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
2719 Chain = LoadEnvPtr.getValue(1);
2720 InFlag = LoadEnvPtr.getValue(2);
2722 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
2724 Chain = EnvVal.getValue(0);
2725 InFlag = EnvVal.getValue(1);
2727 // Load TOC of the callee into r2. We are using a target-specific load
2728 // with r2 hard coded, because the result of a target-independent load
2729 // would never go directly into r2, since r2 is a reserved register (which
2730 // prevents the register allocator from allocating it), resulting in an
2731 // additional register being allocated and an unnecessary move instruction
2733 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2734 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
2736 Chain = LoadTOCPtr.getValue(0);
2737 InFlag = LoadTOCPtr.getValue(1);
2739 MTCTROps[0] = Chain;
2740 MTCTROps[1] = LoadFuncPtr;
2741 MTCTROps[2] = InFlag;
2744 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2745 2 + (InFlag.getNode() != 0));
2746 InFlag = Chain.getValue(1);
2749 NodeTys.push_back(MVT::Other);
2750 NodeTys.push_back(MVT::Glue);
2751 Ops.push_back(Chain);
2752 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
2754 // Add CTR register as callee so a bctr can be emitted later.
2756 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
2759 // If this is a direct call, pass the chain and the callee.
2760 if (Callee.getNode()) {
2761 Ops.push_back(Chain);
2762 Ops.push_back(Callee);
2764 // If this is a tail call add stack pointer delta.
2766 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2768 // Add argument registers to the end of the list so that they are known live
2770 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2771 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2772 RegsToPass[i].second.getValueType()));
2778 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2779 CallingConv::ID CallConv, bool isVarArg,
2780 const SmallVectorImpl<ISD::InputArg> &Ins,
2781 DebugLoc dl, SelectionDAG &DAG,
2782 SmallVectorImpl<SDValue> &InVals) const {
2784 SmallVector<CCValAssign, 16> RVLocs;
2785 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2786 getTargetMachine(), RVLocs, *DAG.getContext());
2787 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2789 // Copy all of the result registers out of their specified physreg.
2790 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2791 CCValAssign &VA = RVLocs[i];
2792 EVT VT = VA.getValVT();
2793 assert(VA.isRegLoc() && "Can only return in registers!");
2794 Chain = DAG.getCopyFromReg(Chain, dl,
2795 VA.getLocReg(), VT, InFlag).getValue(1);
2796 InVals.push_back(Chain.getValue(0));
2797 InFlag = Chain.getValue(2);
2804 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
2805 bool isTailCall, bool isVarArg,
2807 SmallVector<std::pair<unsigned, SDValue>, 8>
2809 SDValue InFlag, SDValue Chain,
2811 int SPDiff, unsigned NumBytes,
2812 const SmallVectorImpl<ISD::InputArg> &Ins,
2813 SmallVectorImpl<SDValue> &InVals) const {
2814 std::vector<EVT> NodeTys;
2815 SmallVector<SDValue, 8> Ops;
2816 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
2817 isTailCall, RegsToPass, Ops, NodeTys,
2820 // When performing tail call optimization the callee pops its arguments off
2821 // the stack. Account for this here so these bytes can be pushed back on in
2822 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2823 int BytesCalleePops =
2824 (CallConv == CallingConv::Fast &&
2825 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
2827 // Add a register mask operand representing the call-preserved registers.
2828 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
2829 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
2830 assert(Mask && "Missing call preserved mask for calling convention");
2831 Ops.push_back(DAG.getRegisterMask(Mask));
2833 if (InFlag.getNode())
2834 Ops.push_back(InFlag);
2838 // If this is the first return lowered for this function, add the regs
2839 // to the liveout set for the function.
2840 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2841 SmallVector<CCValAssign, 16> RVLocs;
2842 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2843 getTargetMachine(), RVLocs, *DAG.getContext());
2844 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2845 for (unsigned i = 0; i != RVLocs.size(); ++i)
2846 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2849 assert(((Callee.getOpcode() == ISD::Register &&
2850 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
2851 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2852 Callee.getOpcode() == ISD::TargetGlobalAddress ||
2853 isa<ConstantSDNode>(Callee)) &&
2854 "Expecting an global address, external symbol, absolute value or register");
2856 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
2859 // Add a NOP immediately after the branch instruction when using the 64-bit
2860 // SVR4 ABI. At link time, if caller and callee are in a different module and
2861 // thus have a different TOC, the call will be replaced with a call to a stub
2862 // function which saves the current TOC, loads the TOC of the callee and
2863 // branches to the callee. The NOP will be replaced with a load instruction
2864 // which restores the TOC of the caller from the TOC save slot of the current
2865 // stack frame. If caller and callee belong to the same module (and have the
2866 // same TOC), the NOP will remain unchanged.
2868 bool needsTOCRestore = false;
2869 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
2870 if (CallOpc == PPCISD::BCTRL_SVR4) {
2871 // This is a call through a function pointer.
2872 // Restore the caller TOC from the save area into R2.
2873 // See PrepareCall() for more information about calls through function
2874 // pointers in the 64-bit SVR4 ABI.
2875 // We are using a target-specific load with r2 hard coded, because the
2876 // result of a target-independent load would never go directly into r2,
2877 // since r2 is a reserved register (which prevents the register allocator
2878 // from allocating it), resulting in an additional register being
2879 // allocated and an unnecessary move instruction being generated.
2880 needsTOCRestore = true;
2881 } else if (CallOpc == PPCISD::CALL_SVR4) {
2882 // Otherwise insert NOP.
2883 CallOpc = PPCISD::CALL_NOP_SVR4;
2887 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
2888 InFlag = Chain.getValue(1);
2890 if (needsTOCRestore) {
2891 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2892 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
2893 InFlag = Chain.getValue(1);
2896 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2897 DAG.getIntPtrConstant(BytesCalleePops, true),
2900 InFlag = Chain.getValue(1);
2902 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2903 Ins, dl, DAG, InVals);
2907 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
2908 SmallVectorImpl<SDValue> &InVals) const {
2909 SelectionDAG &DAG = CLI.DAG;
2910 DebugLoc &dl = CLI.DL;
2911 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
2912 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
2913 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
2914 SDValue Chain = CLI.Chain;
2915 SDValue Callee = CLI.Callee;
2916 bool &isTailCall = CLI.IsTailCall;
2917 CallingConv::ID CallConv = CLI.CallConv;
2918 bool isVarArg = CLI.IsVarArg;
2921 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
2924 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
2925 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg,
2926 isTailCall, Outs, OutVals, Ins,
2929 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
2930 isTailCall, Outs, OutVals, Ins,
2935 PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
2936 CallingConv::ID CallConv, bool isVarArg,
2938 const SmallVectorImpl<ISD::OutputArg> &Outs,
2939 const SmallVectorImpl<SDValue> &OutVals,
2940 const SmallVectorImpl<ISD::InputArg> &Ins,
2941 DebugLoc dl, SelectionDAG &DAG,
2942 SmallVectorImpl<SDValue> &InVals) const {
2943 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description
2944 // of the 32-bit SVR4 ABI stack frame layout.
2946 assert((CallConv == CallingConv::C ||
2947 CallConv == CallingConv::Fast) && "Unknown calling convention!");
2949 unsigned PtrByteSize = 4;
2951 MachineFunction &MF = DAG.getMachineFunction();
2953 // Mark this function as potentially containing a function that contains a
2954 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2955 // and restoring the callers stack pointer in this functions epilog. This is
2956 // done because by tail calling the called function might overwrite the value
2957 // in this function's (MF) stack pointer stack slot 0(SP).
2958 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
2959 CallConv == CallingConv::Fast)
2960 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2962 // Count how many bytes are to be pushed on the stack, including the linkage
2963 // area, parameter list area and the part of the local variable space which
2964 // contains copies of aggregates which are passed by value.
2966 // Assign locations to all of the outgoing arguments.
2967 SmallVector<CCValAssign, 16> ArgLocs;
2968 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2969 getTargetMachine(), ArgLocs, *DAG.getContext());
2971 // Reserve space for the linkage area on the stack.
2972 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2975 // Handle fixed and variable vector arguments differently.
2976 // Fixed vector arguments go into registers as long as registers are
2977 // available. Variable vector arguments always go into memory.
2978 unsigned NumArgs = Outs.size();
2980 for (unsigned i = 0; i != NumArgs; ++i) {
2981 MVT ArgVT = Outs[i].VT;
2982 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2985 if (Outs[i].IsFixed) {
2986 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
2989 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
2995 errs() << "Call operand #" << i << " has unhandled type "
2996 << EVT(ArgVT).getEVTString() << "\n";
2998 llvm_unreachable(0);
3002 // All arguments are treated the same.
3003 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4);
3006 // Assign locations to all of the outgoing aggregate by value arguments.
3007 SmallVector<CCValAssign, 16> ByValArgLocs;
3008 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3009 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3011 // Reserve stack space for the allocations in CCInfo.
3012 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3014 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal);
3016 // Size of the linkage area, parameter list area and the part of the local
3017 // space variable where copies of aggregates which are passed by value are
3019 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3021 // Calculate by how many bytes the stack has to be adjusted in case of tail
3022 // call optimization.
3023 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3025 // Adjust the stack pointer for the new arguments...
3026 // These operations are automatically eliminated by the prolog/epilog pass
3027 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3028 SDValue CallSeqStart = Chain;
3030 // Load the return address and frame pointer so it can be moved somewhere else
3033 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3036 // Set up a copy of the stack pointer for use loading and storing any
3037 // arguments that may not fit in the registers available for argument
3039 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3041 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3042 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3043 SmallVector<SDValue, 8> MemOpChains;
3045 bool seenFloatArg = false;
3046 // Walk the register/memloc assignments, inserting copies/loads.
3047 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3050 CCValAssign &VA = ArgLocs[i];
3051 SDValue Arg = OutVals[i];
3052 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3054 if (Flags.isByVal()) {
3055 // Argument is an aggregate which is passed by value, thus we need to
3056 // create a copy of it in the local variable space of the current stack
3057 // frame (which is the stack frame of the caller) and pass the address of
3058 // this copy to the callee.
3059 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3060 CCValAssign &ByValVA = ByValArgLocs[j++];
3061 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3063 // Memory reserved in the local variable space of the callers stack frame.
3064 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3066 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3067 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3069 // Create a copy of the argument in the local area of the current
3071 SDValue MemcpyCall =
3072 CreateCopyOfByValArgument(Arg, PtrOff,
3073 CallSeqStart.getNode()->getOperand(0),
3076 // This must go outside the CALLSEQ_START..END.
3077 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3078 CallSeqStart.getNode()->getOperand(1));
3079 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3080 NewCallSeqStart.getNode());
3081 Chain = CallSeqStart = NewCallSeqStart;
3083 // Pass the address of the aggregate copy on the stack either in a
3084 // physical register or in the parameter list area of the current stack
3085 // frame to the callee.
3089 if (VA.isRegLoc()) {
3090 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3091 // Put argument in a physical register.
3092 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3094 // Put argument in the parameter list area of the current stack frame.
3095 assert(VA.isMemLoc());
3096 unsigned LocMemOffset = VA.getLocMemOffset();
3099 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3100 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3102 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3103 MachinePointerInfo(),
3106 // Calculate and remember argument location.
3107 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3113 if (!MemOpChains.empty())
3114 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3115 &MemOpChains[0], MemOpChains.size());
3117 // Set CR6 to true if this is a vararg call with floating args passed in
3120 SDValue SetCR(DAG.getMachineNode(seenFloatArg ? PPC::CRSET : PPC::CRUNSET,
3122 RegsToPass.push_back(std::make_pair(unsigned(PPC::CR1EQ), SetCR));
3125 // Build a sequence of copy-to-reg nodes chained together with token chain
3126 // and flag operands which copy the outgoing args into the appropriate regs.
3128 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3129 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3130 RegsToPass[i].second, InFlag);
3131 InFlag = Chain.getValue(1);
3135 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3136 false, TailCallArguments);
3138 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3139 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3144 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
3145 CallingConv::ID CallConv, bool isVarArg,
3147 const SmallVectorImpl<ISD::OutputArg> &Outs,
3148 const SmallVectorImpl<SDValue> &OutVals,
3149 const SmallVectorImpl<ISD::InputArg> &Ins,
3150 DebugLoc dl, SelectionDAG &DAG,
3151 SmallVectorImpl<SDValue> &InVals) const {
3153 unsigned NumOps = Outs.size();
3155 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3156 bool isPPC64 = PtrVT == MVT::i64;
3157 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3159 MachineFunction &MF = DAG.getMachineFunction();
3161 // Mark this function as potentially containing a function that contains a
3162 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3163 // and restoring the callers stack pointer in this functions epilog. This is
3164 // done because by tail calling the called function might overwrite the value
3165 // in this function's (MF) stack pointer stack slot 0(SP).
3166 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3167 CallConv == CallingConv::Fast)
3168 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3170 unsigned nAltivecParamsAtEnd = 0;
3172 // Count how many bytes are to be pushed on the stack, including the linkage
3173 // area, and parameter passing area. We start with 24/48 bytes, which is
3174 // prereserved space for [SP][CR][LR][3 x unused].
3176 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
3178 nAltivecParamsAtEnd);
3180 // Calculate by how many bytes the stack has to be adjusted in case of tail
3181 // call optimization.
3182 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3184 // To protect arguments on the stack from being clobbered in a tail call,
3185 // force all the loads to happen before doing any other lowering.
3187 Chain = DAG.getStackArgumentTokenFactor(Chain);
3189 // Adjust the stack pointer for the new arguments...
3190 // These operations are automatically eliminated by the prolog/epilog pass
3191 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3192 SDValue CallSeqStart = Chain;
3194 // Load the return address and frame pointer so it can be move somewhere else
3197 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3200 // Set up a copy of the stack pointer for use loading and storing any
3201 // arguments that may not fit in the registers available for argument
3205 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3207 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3209 // Figure out which arguments are going to go in registers, and which in
3210 // memory. Also, if this is a vararg function, floating point operations
3211 // must be stored to our stack, and loaded into integer regs as well, if
3212 // any integer regs are available for argument passing.
3213 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
3214 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3216 static const uint16_t GPR_32[] = { // 32-bit registers.
3217 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3218 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3220 static const uint16_t GPR_64[] = { // 64-bit registers.
3221 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3222 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3224 static const uint16_t *FPR = GetFPR();
3226 static const uint16_t VR[] = {
3227 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3228 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3230 const unsigned NumGPRs = array_lengthof(GPR_32);
3231 const unsigned NumFPRs = 13;
3232 const unsigned NumVRs = array_lengthof(VR);
3234 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
3236 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3237 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3239 SmallVector<SDValue, 8> MemOpChains;
3240 for (unsigned i = 0; i != NumOps; ++i) {
3241 SDValue Arg = OutVals[i];
3242 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3244 // PtrOff will be used to store the current argument to the stack if a
3245 // register cannot be found for it.
3248 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3250 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3252 // On PPC64, promote integers to 64-bit values.
3253 if (isPPC64 && Arg.getValueType() == MVT::i32) {
3254 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3255 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3256 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3259 // FIXME memcpy is used way more than necessary. Correctness first.
3260 if (Flags.isByVal()) {
3261 unsigned Size = Flags.getByValSize();
3262 if (Size==1 || Size==2) {
3263 // Very small objects are passed right-justified.
3264 // Everything else is passed left-justified.
3265 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
3266 if (GPR_idx != NumGPRs) {
3267 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3268 MachinePointerInfo(), VT,
3270 MemOpChains.push_back(Load.getValue(1));
3271 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3273 ArgOffset += PtrByteSize;
3275 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
3276 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3277 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
3278 CallSeqStart.getNode()->getOperand(0),
3280 // This must go outside the CALLSEQ_START..END.
3281 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3282 CallSeqStart.getNode()->getOperand(1));
3283 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3284 NewCallSeqStart.getNode());
3285 Chain = CallSeqStart = NewCallSeqStart;
3286 ArgOffset += PtrByteSize;
3290 // Copy entire object into memory. There are cases where gcc-generated
3291 // code assumes it is there, even if it could be put entirely into
3292 // registers. (This is not what the doc says.)
3293 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3294 CallSeqStart.getNode()->getOperand(0),
3296 // This must go outside the CALLSEQ_START..END.
3297 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3298 CallSeqStart.getNode()->getOperand(1));
3299 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
3300 Chain = CallSeqStart = NewCallSeqStart;
3301 // And copy the pieces of it that fit into registers.
3302 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3303 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3304 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3305 if (GPR_idx != NumGPRs) {
3306 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3307 MachinePointerInfo(),
3308 false, false, false, 0);
3309 MemOpChains.push_back(Load.getValue(1));
3310 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3311 ArgOffset += PtrByteSize;
3313 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3320 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3321 default: llvm_unreachable("Unexpected ValueType for argument!");
3324 if (GPR_idx != NumGPRs) {
3325 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3327 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3328 isPPC64, isTailCall, false, MemOpChains,
3329 TailCallArguments, dl);
3331 ArgOffset += PtrByteSize;
3335 if (FPR_idx != NumFPRs) {
3336 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3339 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3340 MachinePointerInfo(), false, false, 0);
3341 MemOpChains.push_back(Store);
3343 // Float varargs are always shadowed in available integer registers
3344 if (GPR_idx != NumGPRs) {
3345 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3346 MachinePointerInfo(), false, false,
3348 MemOpChains.push_back(Load.getValue(1));
3349 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3351 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
3352 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3353 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3354 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3355 MachinePointerInfo(),
3356 false, false, false, 0);
3357 MemOpChains.push_back(Load.getValue(1));
3358 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3361 // If we have any FPRs remaining, we may also have GPRs remaining.
3362 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
3364 if (GPR_idx != NumGPRs)
3366 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
3367 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
3371 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3372 isPPC64, isTailCall, false, MemOpChains,
3373 TailCallArguments, dl);
3378 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
3385 // These go aligned on the stack, or in the corresponding R registers
3386 // when within range. The Darwin PPC ABI doc claims they also go in
3387 // V registers; in fact gcc does this only for arguments that are
3388 // prototyped, not for those that match the ... We do it for all
3389 // arguments, seems to work.
3390 while (ArgOffset % 16 !=0) {
3391 ArgOffset += PtrByteSize;
3392 if (GPR_idx != NumGPRs)
3395 // We could elide this store in the case where the object fits
3396 // entirely in R registers. Maybe later.
3397 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3398 DAG.getConstant(ArgOffset, PtrVT));
3399 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3400 MachinePointerInfo(), false, false, 0);
3401 MemOpChains.push_back(Store);
3402 if (VR_idx != NumVRs) {
3403 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
3404 MachinePointerInfo(),
3405 false, false, false, 0);
3406 MemOpChains.push_back(Load.getValue(1));
3407 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
3410 for (unsigned i=0; i<16; i+=PtrByteSize) {
3411 if (GPR_idx == NumGPRs)
3413 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
3414 DAG.getConstant(i, PtrVT));
3415 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
3416 false, false, false, 0);
3417 MemOpChains.push_back(Load.getValue(1));
3418 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3423 // Non-varargs Altivec params generally go in registers, but have
3424 // stack space allocated at the end.
3425 if (VR_idx != NumVRs) {
3426 // Doesn't have GPR space allocated.
3427 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
3428 } else if (nAltivecParamsAtEnd==0) {
3429 // We are emitting Altivec params in order.
3430 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3431 isPPC64, isTailCall, true, MemOpChains,
3432 TailCallArguments, dl);
3438 // If all Altivec parameters fit in registers, as they usually do,
3439 // they get stack space following the non-Altivec parameters. We
3440 // don't track this here because nobody below needs it.
3441 // If there are more Altivec parameters than fit in registers emit
3443 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
3445 // Offset is aligned; skip 1st 12 params which go in V registers.
3446 ArgOffset = ((ArgOffset+15)/16)*16;
3448 for (unsigned i = 0; i != NumOps; ++i) {
3449 SDValue Arg = OutVals[i];
3450 EVT ArgType = Outs[i].VT;
3451 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
3452 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
3455 // We are emitting Altivec params in order.
3456 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3457 isPPC64, isTailCall, true, MemOpChains,
3458 TailCallArguments, dl);
3465 if (!MemOpChains.empty())
3466 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3467 &MemOpChains[0], MemOpChains.size());
3469 // Check if this is an indirect call (MTCTR/BCTRL).
3470 // See PrepareCall() for more information about calls through function
3471 // pointers in the 64-bit SVR4 ABI.
3472 if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() &&
3473 !dyn_cast<GlobalAddressSDNode>(Callee) &&
3474 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3475 !isBLACompatibleAddress(Callee, DAG)) {
3476 // Load r2 into a virtual register and store it to the TOC save area.
3477 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
3478 // TOC save area offset.
3479 SDValue PtrOff = DAG.getIntPtrConstant(40);
3480 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3481 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
3485 // On Darwin, R12 must contain the address of an indirect callee. This does
3486 // not mean the MTCTR instruction must use R12; it's easier to model this as
3487 // an extra parameter, so do that.
3489 !dyn_cast<GlobalAddressSDNode>(Callee) &&
3490 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3491 !isBLACompatibleAddress(Callee, DAG))
3492 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
3493 PPC::R12), Callee));
3495 // Build a sequence of copy-to-reg nodes chained together with token chain
3496 // and flag operands which copy the outgoing args into the appropriate regs.
3498 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3499 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3500 RegsToPass[i].second, InFlag);
3501 InFlag = Chain.getValue(1);
3505 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
3506 FPOp, true, TailCallArguments);
3508 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3509 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3514 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3515 MachineFunction &MF, bool isVarArg,
3516 const SmallVectorImpl<ISD::OutputArg> &Outs,
3517 LLVMContext &Context) const {
3518 SmallVector<CCValAssign, 16> RVLocs;
3519 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
3521 return CCInfo.CheckReturn(Outs, RetCC_PPC);
3525 PPCTargetLowering::LowerReturn(SDValue Chain,
3526 CallingConv::ID CallConv, bool isVarArg,
3527 const SmallVectorImpl<ISD::OutputArg> &Outs,
3528 const SmallVectorImpl<SDValue> &OutVals,
3529 DebugLoc dl, SelectionDAG &DAG) const {
3531 SmallVector<CCValAssign, 16> RVLocs;
3532 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3533 getTargetMachine(), RVLocs, *DAG.getContext());
3534 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
3536 // If this is the first return lowered for this function, add the regs to the
3537 // liveout set for the function.
3538 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3539 for (unsigned i = 0; i != RVLocs.size(); ++i)
3540 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3545 // Copy the result values into the output registers.
3546 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3547 CCValAssign &VA = RVLocs[i];
3548 assert(VA.isRegLoc() && "Can only return in registers!");
3549 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3551 Flag = Chain.getValue(1);
3555 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
3557 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
3560 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
3561 const PPCSubtarget &Subtarget) const {
3562 // When we pop the dynamic allocation we need to restore the SP link.
3563 DebugLoc dl = Op.getDebugLoc();
3565 // Get the corect type for pointers.
3566 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3568 // Construct the stack pointer operand.
3569 bool isPPC64 = Subtarget.isPPC64();
3570 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
3571 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
3573 // Get the operands for the STACKRESTORE.
3574 SDValue Chain = Op.getOperand(0);
3575 SDValue SaveSP = Op.getOperand(1);
3577 // Load the old link SP.
3578 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
3579 MachinePointerInfo(),
3580 false, false, false, 0);
3582 // Restore the stack pointer.
3583 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
3585 // Store the old link SP.
3586 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
3593 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
3594 MachineFunction &MF = DAG.getMachineFunction();
3595 bool isPPC64 = PPCSubTarget.isPPC64();
3596 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3597 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3599 // Get current frame pointer save index. The users of this index will be
3600 // primarily DYNALLOC instructions.
3601 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3602 int RASI = FI->getReturnAddrSaveIndex();
3604 // If the frame pointer save index hasn't been defined yet.
3606 // Find out what the fix offset of the frame pointer save area.
3607 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
3608 // Allocate the frame index for frame pointer save area.
3609 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
3611 FI->setReturnAddrSaveIndex(RASI);
3613 return DAG.getFrameIndex(RASI, PtrVT);
3617 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
3618 MachineFunction &MF = DAG.getMachineFunction();
3619 bool isPPC64 = PPCSubTarget.isPPC64();
3620 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3621 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3623 // Get current frame pointer save index. The users of this index will be
3624 // primarily DYNALLOC instructions.
3625 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3626 int FPSI = FI->getFramePointerSaveIndex();
3628 // If the frame pointer save index hasn't been defined yet.
3630 // Find out what the fix offset of the frame pointer save area.
3631 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
3634 // Allocate the frame index for frame pointer save area.
3635 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
3637 FI->setFramePointerSaveIndex(FPSI);
3639 return DAG.getFrameIndex(FPSI, PtrVT);
3642 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3644 const PPCSubtarget &Subtarget) const {
3646 SDValue Chain = Op.getOperand(0);
3647 SDValue Size = Op.getOperand(1);
3648 DebugLoc dl = Op.getDebugLoc();
3650 // Get the corect type for pointers.
3651 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3653 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
3654 DAG.getConstant(0, PtrVT), Size);
3655 // Construct a node for the frame pointer save index.
3656 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
3657 // Build a DYNALLOC node.
3658 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
3659 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
3660 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
3663 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
3665 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3666 // Not FP? Not a fsel.
3667 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
3668 !Op.getOperand(2).getValueType().isFloatingPoint())
3671 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3673 // Cannot handle SETEQ/SETNE.
3674 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
3676 EVT ResVT = Op.getValueType();
3677 EVT CmpVT = Op.getOperand(0).getValueType();
3678 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3679 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
3680 DebugLoc dl = Op.getDebugLoc();
3682 // If the RHS of the comparison is a 0.0, we don't need to do the
3683 // subtraction at all.
3684 if (isFloatingPointZero(RHS))
3686 default: break; // SETUO etc aren't handled by fsel.
3689 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3692 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3693 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3694 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
3697 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3700 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3701 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3702 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
3703 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
3708 default: break; // SETUO etc aren't handled by fsel.
3711 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3712 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3713 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3714 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3717 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3718 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3719 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3720 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3723 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3724 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3725 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3726 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3729 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3730 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3731 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3732 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3737 // FIXME: Split this code up when LegalizeDAGTypes lands.
3738 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
3739 DebugLoc dl) const {
3740 assert(Op.getOperand(0).getValueType().isFloatingPoint());
3741 SDValue Src = Op.getOperand(0);
3742 if (Src.getValueType() == MVT::f32)
3743 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
3746 switch (Op.getValueType().getSimpleVT().SimpleTy) {
3747 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
3749 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
3754 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
3758 // Convert the FP value to an int value through memory.
3759 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
3761 // Emit a store to the stack slot.
3762 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
3763 MachinePointerInfo(), false, false, 0);
3765 // Result is a load from the stack slot. If loading 4 bytes, make sure to
3767 if (Op.getValueType() == MVT::i32)
3768 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
3769 DAG.getConstant(4, FIPtr.getValueType()));
3770 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(),
3771 false, false, false, 0);
3774 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op,
3775 SelectionDAG &DAG) const {
3776 DebugLoc dl = Op.getDebugLoc();
3777 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
3778 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
3781 if (Op.getOperand(0).getValueType() == MVT::i64) {
3782 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0));
3783 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
3784 if (Op.getValueType() == MVT::f32)
3785 FP = DAG.getNode(ISD::FP_ROUND, dl,
3786 MVT::f32, FP, DAG.getIntPtrConstant(0));
3790 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
3791 "Unhandled SINT_TO_FP type in custom expander!");
3792 // Since we only generate this in 64-bit mode, we can take advantage of
3793 // 64-bit registers. In particular, sign extend the input value into the
3794 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
3795 // then lfd it and fcfid it.
3796 MachineFunction &MF = DAG.getMachineFunction();
3797 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
3798 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
3799 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3800 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3802 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
3805 // STD the extended value into the stack slot.
3806 MachineMemOperand *MMO =
3807 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
3808 MachineMemOperand::MOStore, 8, 8);
3809 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
3811 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other),
3812 Ops, 4, MVT::i64, MMO);
3813 // Load the value as a double.
3814 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(),
3815 false, false, false, 0);
3817 // FCFID it and return it.
3818 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
3819 if (Op.getValueType() == MVT::f32)
3820 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
3824 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3825 SelectionDAG &DAG) const {
3826 DebugLoc dl = Op.getDebugLoc();
3828 The rounding mode is in bits 30:31 of FPSR, and has the following
3835 FLT_ROUNDS, on the other hand, expects the following:
3842 To perform the conversion, we do:
3843 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
3846 MachineFunction &MF = DAG.getMachineFunction();
3847 EVT VT = Op.getValueType();
3848 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3849 std::vector<EVT> NodeTys;
3850 SDValue MFFSreg, InFlag;
3852 // Save FP Control Word to register
3853 NodeTys.push_back(MVT::f64); // return register
3854 NodeTys.push_back(MVT::Glue); // unused in this context
3855 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
3857 // Save FP register to stack slot
3858 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
3859 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
3860 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
3861 StackSlot, MachinePointerInfo(), false, false,0);
3863 // Load FP Control Word from low 32 bits of stack slot.
3864 SDValue Four = DAG.getConstant(4, PtrVT);
3865 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
3866 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
3867 false, false, false, 0);
3869 // Transform as necessary
3871 DAG.getNode(ISD::AND, dl, MVT::i32,
3872 CWD, DAG.getConstant(3, MVT::i32));
3874 DAG.getNode(ISD::SRL, dl, MVT::i32,
3875 DAG.getNode(ISD::AND, dl, MVT::i32,
3876 DAG.getNode(ISD::XOR, dl, MVT::i32,
3877 CWD, DAG.getConstant(3, MVT::i32)),
3878 DAG.getConstant(3, MVT::i32)),
3879 DAG.getConstant(1, MVT::i32));
3882 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
3884 return DAG.getNode((VT.getSizeInBits() < 16 ?
3885 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3888 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3889 EVT VT = Op.getValueType();
3890 unsigned BitWidth = VT.getSizeInBits();
3891 DebugLoc dl = Op.getDebugLoc();
3892 assert(Op.getNumOperands() == 3 &&
3893 VT == Op.getOperand(1).getValueType() &&
3896 // Expand into a bunch of logical ops. Note that these ops
3897 // depend on the PPC behavior for oversized shift amounts.
3898 SDValue Lo = Op.getOperand(0);
3899 SDValue Hi = Op.getOperand(1);
3900 SDValue Amt = Op.getOperand(2);
3901 EVT AmtVT = Amt.getValueType();
3903 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3904 DAG.getConstant(BitWidth, AmtVT), Amt);
3905 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3906 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3907 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3908 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3909 DAG.getConstant(-BitWidth, AmtVT));
3910 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3911 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3912 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3913 SDValue OutOps[] = { OutLo, OutHi };
3914 return DAG.getMergeValues(OutOps, 2, dl);
3917 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3918 EVT VT = Op.getValueType();
3919 DebugLoc dl = Op.getDebugLoc();
3920 unsigned BitWidth = VT.getSizeInBits();
3921 assert(Op.getNumOperands() == 3 &&
3922 VT == Op.getOperand(1).getValueType() &&
3925 // Expand into a bunch of logical ops. Note that these ops
3926 // depend on the PPC behavior for oversized shift amounts.
3927 SDValue Lo = Op.getOperand(0);
3928 SDValue Hi = Op.getOperand(1);
3929 SDValue Amt = Op.getOperand(2);
3930 EVT AmtVT = Amt.getValueType();
3932 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3933 DAG.getConstant(BitWidth, AmtVT), Amt);
3934 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3935 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3936 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3937 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3938 DAG.getConstant(-BitWidth, AmtVT));
3939 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3940 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3941 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3942 SDValue OutOps[] = { OutLo, OutHi };
3943 return DAG.getMergeValues(OutOps, 2, dl);
3946 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
3947 DebugLoc dl = Op.getDebugLoc();
3948 EVT VT = Op.getValueType();
3949 unsigned BitWidth = VT.getSizeInBits();
3950 assert(Op.getNumOperands() == 3 &&
3951 VT == Op.getOperand(1).getValueType() &&
3954 // Expand into a bunch of logical ops, followed by a select_cc.
3955 SDValue Lo = Op.getOperand(0);
3956 SDValue Hi = Op.getOperand(1);
3957 SDValue Amt = Op.getOperand(2);
3958 EVT AmtVT = Amt.getValueType();
3960 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3961 DAG.getConstant(BitWidth, AmtVT), Amt);
3962 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3963 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3964 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3965 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3966 DAG.getConstant(-BitWidth, AmtVT));
3967 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3968 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3969 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
3970 Tmp4, Tmp6, ISD::SETLE);
3971 SDValue OutOps[] = { OutLo, OutHi };
3972 return DAG.getMergeValues(OutOps, 2, dl);
3975 //===----------------------------------------------------------------------===//
3976 // Vector related lowering.
3979 /// BuildSplatI - Build a canonical splati of Val with an element size of
3980 /// SplatSize. Cast the result to VT.
3981 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
3982 SelectionDAG &DAG, DebugLoc dl) {
3983 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3985 static const EVT VTys[] = { // canonical VT to use for each size.
3986 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3989 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3991 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3995 EVT CanonicalVT = VTys[SplatSize-1];
3997 // Build a canonical splat for this value.
3998 SDValue Elt = DAG.getConstant(Val, MVT::i32);
3999 SmallVector<SDValue, 8> Ops;
4000 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
4001 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
4002 &Ops[0], Ops.size());
4003 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
4006 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
4007 /// specified intrinsic ID.
4008 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
4009 SelectionDAG &DAG, DebugLoc dl,
4010 EVT DestVT = MVT::Other) {
4011 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
4012 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4013 DAG.getConstant(IID, MVT::i32), LHS, RHS);
4016 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
4017 /// specified intrinsic ID.
4018 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
4019 SDValue Op2, SelectionDAG &DAG,
4020 DebugLoc dl, EVT DestVT = MVT::Other) {
4021 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
4022 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4023 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
4027 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
4028 /// amount. The result has the specified value type.
4029 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
4030 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
4031 // Force LHS/RHS to be the right type.
4032 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
4033 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
4036 for (unsigned i = 0; i != 16; ++i)
4038 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
4039 return DAG.getNode(ISD::BITCAST, dl, VT, T);
4042 // If this is a case we can't handle, return null and let the default
4043 // expansion code take care of it. If we CAN select this case, and if it
4044 // selects to a single instruction, return Op. Otherwise, if we can codegen
4045 // this case more efficiently than a constant pool load, lower it to the
4046 // sequence of ops that should be used.
4047 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
4048 SelectionDAG &DAG) const {
4049 DebugLoc dl = Op.getDebugLoc();
4050 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
4051 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
4053 // Check if this is a splat of a constant value.
4054 APInt APSplatBits, APSplatUndef;
4055 unsigned SplatBitSize;
4057 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
4058 HasAnyUndefs, 0, true) || SplatBitSize > 32)
4061 unsigned SplatBits = APSplatBits.getZExtValue();
4062 unsigned SplatUndef = APSplatUndef.getZExtValue();
4063 unsigned SplatSize = SplatBitSize / 8;
4065 // First, handle single instruction cases.
4068 if (SplatBits == 0) {
4069 // Canonicalize all zero vectors to be v4i32.
4070 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
4071 SDValue Z = DAG.getConstant(0, MVT::i32);
4072 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
4073 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
4078 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
4079 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
4081 if (SextVal >= -16 && SextVal <= 15)
4082 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
4085 // Two instruction sequences.
4087 // If this value is in the range [-32,30] and is even, use:
4088 // tmp = VSPLTI[bhw], result = add tmp, tmp
4089 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
4090 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
4091 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
4092 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4095 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
4096 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
4098 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
4099 // Make -1 and vspltisw -1:
4100 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
4102 // Make the VSLW intrinsic, computing 0x8000_0000.
4103 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
4106 // xor by OnesV to invert it.
4107 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
4108 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4111 // Check to see if this is a wide variety of vsplti*, binop self cases.
4112 static const signed char SplatCsts[] = {
4113 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
4114 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
4117 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
4118 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
4119 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
4120 int i = SplatCsts[idx];
4122 // Figure out what shift amount will be used by altivec if shifted by i in
4124 unsigned TypeShiftAmt = i & (SplatBitSize-1);
4126 // vsplti + shl self.
4127 if (SextVal == (i << (int)TypeShiftAmt)) {
4128 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
4129 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4130 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
4131 Intrinsic::ppc_altivec_vslw
4133 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
4134 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4137 // vsplti + srl self.
4138 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
4139 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
4140 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4141 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
4142 Intrinsic::ppc_altivec_vsrw
4144 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
4145 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4148 // vsplti + sra self.
4149 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
4150 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
4151 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4152 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
4153 Intrinsic::ppc_altivec_vsraw
4155 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
4156 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4159 // vsplti + rol self.
4160 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
4161 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
4162 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
4163 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4164 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
4165 Intrinsic::ppc_altivec_vrlw
4167 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
4168 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4171 // t = vsplti c, result = vsldoi t, t, 1
4172 if (SextVal == ((i << 8) | (i < 0 ? 0xFF : 0))) {
4173 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
4174 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
4176 // t = vsplti c, result = vsldoi t, t, 2
4177 if (SextVal == ((i << 16) | (i < 0 ? 0xFFFF : 0))) {
4178 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
4179 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
4181 // t = vsplti c, result = vsldoi t, t, 3
4182 if (SextVal == ((i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
4183 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
4184 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
4188 // Three instruction sequences.
4190 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
4191 if (SextVal >= 0 && SextVal <= 31) {
4192 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
4193 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
4194 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
4195 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
4197 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
4198 if (SextVal >= -31 && SextVal <= 0) {
4199 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
4200 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
4201 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
4202 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
4208 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4209 /// the specified operations to build the shuffle.
4210 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4211 SDValue RHS, SelectionDAG &DAG,
4213 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4214 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4215 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4218 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4230 if (OpNum == OP_COPY) {
4231 if (LHSID == (1*9+2)*9+3) return LHS;
4232 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4236 SDValue OpLHS, OpRHS;
4237 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4238 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4242 default: llvm_unreachable("Unknown i32 permute!");
4244 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
4245 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
4246 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
4247 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
4250 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
4251 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
4252 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
4253 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
4256 for (unsigned i = 0; i != 16; ++i)
4257 ShufIdxs[i] = (i&3)+0;
4260 for (unsigned i = 0; i != 16; ++i)
4261 ShufIdxs[i] = (i&3)+4;
4264 for (unsigned i = 0; i != 16; ++i)
4265 ShufIdxs[i] = (i&3)+8;
4268 for (unsigned i = 0; i != 16; ++i)
4269 ShufIdxs[i] = (i&3)+12;
4272 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
4274 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
4276 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
4278 EVT VT = OpLHS.getValueType();
4279 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
4280 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
4281 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
4282 return DAG.getNode(ISD::BITCAST, dl, VT, T);
4285 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
4286 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
4287 /// return the code it can be lowered into. Worst case, it can always be
4288 /// lowered into a vperm.
4289 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4290 SelectionDAG &DAG) const {
4291 DebugLoc dl = Op.getDebugLoc();
4292 SDValue V1 = Op.getOperand(0);
4293 SDValue V2 = Op.getOperand(1);
4294 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4295 EVT VT = Op.getValueType();
4297 // Cases that are handled by instructions that take permute immediates
4298 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
4299 // selected by the instruction selector.
4300 if (V2.getOpcode() == ISD::UNDEF) {
4301 if (PPC::isSplatShuffleMask(SVOp, 1) ||
4302 PPC::isSplatShuffleMask(SVOp, 2) ||
4303 PPC::isSplatShuffleMask(SVOp, 4) ||
4304 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
4305 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
4306 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
4307 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
4308 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
4309 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
4310 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
4311 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
4312 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
4317 // Altivec has a variety of "shuffle immediates" that take two vector inputs
4318 // and produce a fixed permutation. If any of these match, do not lower to
4320 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
4321 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
4322 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
4323 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
4324 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
4325 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
4326 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
4327 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
4328 PPC::isVMRGHShuffleMask(SVOp, 4, false))
4331 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
4332 // perfect shuffle table to emit an optimal matching sequence.
4333 ArrayRef<int> PermMask = SVOp->getMask();
4335 unsigned PFIndexes[4];
4336 bool isFourElementShuffle = true;
4337 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
4338 unsigned EltNo = 8; // Start out undef.
4339 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
4340 if (PermMask[i*4+j] < 0)
4341 continue; // Undef, ignore it.
4343 unsigned ByteSource = PermMask[i*4+j];
4344 if ((ByteSource & 3) != j) {
4345 isFourElementShuffle = false;
4350 EltNo = ByteSource/4;
4351 } else if (EltNo != ByteSource/4) {
4352 isFourElementShuffle = false;
4356 PFIndexes[i] = EltNo;
4359 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
4360 // perfect shuffle vector to determine if it is cost effective to do this as
4361 // discrete instructions, or whether we should use a vperm.
4362 if (isFourElementShuffle) {
4363 // Compute the index in the perfect shuffle table.
4364 unsigned PFTableIndex =
4365 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4367 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4368 unsigned Cost = (PFEntry >> 30);
4370 // Determining when to avoid vperm is tricky. Many things affect the cost
4371 // of vperm, particularly how many times the perm mask needs to be computed.
4372 // For example, if the perm mask can be hoisted out of a loop or is already
4373 // used (perhaps because there are multiple permutes with the same shuffle
4374 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
4375 // the loop requires an extra register.
4377 // As a compromise, we only emit discrete instructions if the shuffle can be
4378 // generated in 3 or fewer operations. When we have loop information
4379 // available, if this block is within a loop, we should avoid using vperm
4380 // for 3-operation perms and use a constant pool load instead.
4382 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4385 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
4386 // vector that will get spilled to the constant pool.
4387 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
4389 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
4390 // that it is in input element units, not in bytes. Convert now.
4391 EVT EltVT = V1.getValueType().getVectorElementType();
4392 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
4394 SmallVector<SDValue, 16> ResultMask;
4395 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
4396 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
4398 for (unsigned j = 0; j != BytesPerElement; ++j)
4399 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
4403 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
4404 &ResultMask[0], ResultMask.size());
4405 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
4408 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
4409 /// altivec comparison. If it is, return true and fill in Opc/isDot with
4410 /// information about the intrinsic.
4411 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
4413 unsigned IntrinsicID =
4414 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
4417 switch (IntrinsicID) {
4418 default: return false;
4419 // Comparison predicates.
4420 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
4421 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
4422 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
4423 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
4424 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
4425 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
4426 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
4427 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
4428 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
4429 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
4430 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
4431 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
4432 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
4434 // Normal Comparisons.
4435 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
4436 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
4437 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
4438 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
4439 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
4440 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
4441 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
4442 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
4443 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
4444 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
4445 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
4446 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
4447 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
4452 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
4453 /// lower, do it, otherwise return null.
4454 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
4455 SelectionDAG &DAG) const {
4456 // If this is a lowered altivec predicate compare, CompareOpc is set to the
4457 // opcode number of the comparison.
4458 DebugLoc dl = Op.getDebugLoc();
4461 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
4462 return SDValue(); // Don't custom lower most intrinsics.
4464 // If this is a non-dot comparison, make the VCMP node and we are done.
4466 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
4467 Op.getOperand(1), Op.getOperand(2),
4468 DAG.getConstant(CompareOpc, MVT::i32));
4469 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
4472 // Create the PPCISD altivec 'dot' comparison node.
4474 Op.getOperand(2), // LHS
4475 Op.getOperand(3), // RHS
4476 DAG.getConstant(CompareOpc, MVT::i32)
4478 std::vector<EVT> VTs;
4479 VTs.push_back(Op.getOperand(2).getValueType());
4480 VTs.push_back(MVT::Glue);
4481 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
4483 // Now that we have the comparison, emit a copy from the CR to a GPR.
4484 // This is flagged to the above dot comparison.
4485 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
4486 DAG.getRegister(PPC::CR6, MVT::i32),
4487 CompNode.getValue(1));
4489 // Unpack the result based on how the target uses it.
4490 unsigned BitNo; // Bit # of CR6.
4491 bool InvertBit; // Invert result?
4492 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
4493 default: // Can't happen, don't crash on invalid number though.
4494 case 0: // Return the value of the EQ bit of CR6.
4495 BitNo = 0; InvertBit = false;
4497 case 1: // Return the inverted value of the EQ bit of CR6.
4498 BitNo = 0; InvertBit = true;
4500 case 2: // Return the value of the LT bit of CR6.
4501 BitNo = 2; InvertBit = false;
4503 case 3: // Return the inverted value of the LT bit of CR6.
4504 BitNo = 2; InvertBit = true;
4508 // Shift the bit into the low position.
4509 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
4510 DAG.getConstant(8-(3-BitNo), MVT::i32));
4512 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
4513 DAG.getConstant(1, MVT::i32));
4515 // If we are supposed to, toggle the bit.
4517 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
4518 DAG.getConstant(1, MVT::i32));
4522 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
4523 SelectionDAG &DAG) const {
4524 DebugLoc dl = Op.getDebugLoc();
4525 // Create a stack slot that is 16-byte aligned.
4526 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4527 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
4528 EVT PtrVT = getPointerTy();
4529 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4531 // Store the input value into Value#0 of the stack slot.
4532 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
4533 Op.getOperand(0), FIdx, MachinePointerInfo(),
4536 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
4537 false, false, false, 0);
4540 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
4541 DebugLoc dl = Op.getDebugLoc();
4542 if (Op.getValueType() == MVT::v4i32) {
4543 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4545 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
4546 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
4548 SDValue RHSSwap = // = vrlw RHS, 16
4549 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
4551 // Shrinkify inputs to v8i16.
4552 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
4553 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
4554 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
4556 // Low parts multiplied together, generating 32-bit results (we ignore the
4558 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
4559 LHS, RHS, DAG, dl, MVT::v4i32);
4561 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
4562 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
4563 // Shift the high parts up 16 bits.
4564 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
4566 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
4567 } else if (Op.getValueType() == MVT::v8i16) {
4568 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4570 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
4572 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
4573 LHS, RHS, Zero, DAG, dl);
4574 } else if (Op.getValueType() == MVT::v16i8) {
4575 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4577 // Multiply the even 8-bit parts, producing 16-bit sums.
4578 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
4579 LHS, RHS, DAG, dl, MVT::v8i16);
4580 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
4582 // Multiply the odd 8-bit parts, producing 16-bit sums.
4583 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
4584 LHS, RHS, DAG, dl, MVT::v8i16);
4585 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
4587 // Merge the results together.
4589 for (unsigned i = 0; i != 8; ++i) {
4591 Ops[i*2+1] = 2*i+1+16;
4593 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
4595 llvm_unreachable("Unknown mul to lower!");
4599 /// LowerOperation - Provide custom lowering hooks for some operations.
4601 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4602 switch (Op.getOpcode()) {
4603 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
4604 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4605 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4606 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4607 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4608 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4609 case ISD::SETCC: return LowerSETCC(Op, DAG);
4610 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
4611 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
4613 return LowerVASTART(Op, DAG, PPCSubTarget);
4616 return LowerVAARG(Op, DAG, PPCSubTarget);
4618 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
4619 case ISD::DYNAMIC_STACKALLOC:
4620 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
4622 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4623 case ISD::FP_TO_UINT:
4624 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
4626 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4627 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4629 // Lower 64-bit shifts.
4630 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
4631 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
4632 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
4634 // Vector-related lowering.
4635 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4636 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4637 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4638 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4639 case ISD::MUL: return LowerMUL(Op, DAG);
4641 // Frame & Return address.
4642 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4643 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4647 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
4648 SmallVectorImpl<SDValue>&Results,
4649 SelectionDAG &DAG) const {
4650 const TargetMachine &TM = getTargetMachine();
4651 DebugLoc dl = N->getDebugLoc();
4652 switch (N->getOpcode()) {
4654 llvm_unreachable("Do not know how to custom type legalize this operation!");
4656 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
4657 || TM.getSubtarget<PPCSubtarget>().isPPC64())
4660 EVT VT = N->getValueType(0);
4662 if (VT == MVT::i64) {
4663 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
4665 Results.push_back(NewNode);
4666 Results.push_back(NewNode.getValue(1));
4670 case ISD::FP_ROUND_INREG: {
4671 assert(N->getValueType(0) == MVT::ppcf128);
4672 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
4673 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4674 MVT::f64, N->getOperand(0),
4675 DAG.getIntPtrConstant(0));
4676 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4677 MVT::f64, N->getOperand(0),
4678 DAG.getIntPtrConstant(1));
4680 // This sequence changes FPSCR to do round-to-zero, adds the two halves
4681 // of the long double, and puts FPSCR back the way it was. We do not
4682 // actually model FPSCR.
4683 std::vector<EVT> NodeTys;
4684 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
4686 NodeTys.push_back(MVT::f64); // Return register
4687 NodeTys.push_back(MVT::Glue); // Returns a flag for later insns
4688 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4689 MFFSreg = Result.getValue(0);
4690 InFlag = Result.getValue(1);
4693 NodeTys.push_back(MVT::Glue); // Returns a flag
4694 Ops[0] = DAG.getConstant(31, MVT::i32);
4696 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
4697 InFlag = Result.getValue(0);
4700 NodeTys.push_back(MVT::Glue); // Returns a flag
4701 Ops[0] = DAG.getConstant(30, MVT::i32);
4703 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
4704 InFlag = Result.getValue(0);
4707 NodeTys.push_back(MVT::f64); // result of add
4708 NodeTys.push_back(MVT::Glue); // Returns a flag
4712 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
4713 FPreg = Result.getValue(0);
4714 InFlag = Result.getValue(1);
4717 NodeTys.push_back(MVT::f64);
4718 Ops[0] = DAG.getConstant(1, MVT::i32);
4722 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
4723 FPreg = Result.getValue(0);
4725 // We know the low half is about to be thrown away, so just use something
4727 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
4731 case ISD::FP_TO_SINT:
4732 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
4738 //===----------------------------------------------------------------------===//
4739 // Other Lowering Code
4740 //===----------------------------------------------------------------------===//
4743 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4744 bool is64bit, unsigned BinOpcode) const {
4745 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4746 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4748 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4749 MachineFunction *F = BB->getParent();
4750 MachineFunction::iterator It = BB;
4753 unsigned dest = MI->getOperand(0).getReg();
4754 unsigned ptrA = MI->getOperand(1).getReg();
4755 unsigned ptrB = MI->getOperand(2).getReg();
4756 unsigned incr = MI->getOperand(3).getReg();
4757 DebugLoc dl = MI->getDebugLoc();
4759 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4760 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4761 F->insert(It, loopMBB);
4762 F->insert(It, exitMBB);
4763 exitMBB->splice(exitMBB->begin(), BB,
4764 llvm::next(MachineBasicBlock::iterator(MI)),
4766 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4768 MachineRegisterInfo &RegInfo = F->getRegInfo();
4769 unsigned TmpReg = (!BinOpcode) ? incr :
4770 RegInfo.createVirtualRegister(
4771 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4772 (const TargetRegisterClass *) &PPC::GPRCRegClass);
4776 // fallthrough --> loopMBB
4777 BB->addSuccessor(loopMBB);
4780 // l[wd]arx dest, ptr
4781 // add r0, dest, incr
4782 // st[wd]cx. r0, ptr
4784 // fallthrough --> exitMBB
4786 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4787 .addReg(ptrA).addReg(ptrB);
4789 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
4790 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4791 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
4792 BuildMI(BB, dl, TII->get(PPC::BCC))
4793 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4794 BB->addSuccessor(loopMBB);
4795 BB->addSuccessor(exitMBB);
4804 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
4805 MachineBasicBlock *BB,
4806 bool is8bit, // operation
4807 unsigned BinOpcode) const {
4808 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4809 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4810 // In 64 bit mode we have to use 64 bits for addresses, even though the
4811 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
4812 // registers without caring whether they're 32 or 64, but here we're
4813 // doing actual arithmetic on the addresses.
4814 bool is64bit = PPCSubTarget.isPPC64();
4815 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
4817 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4818 MachineFunction *F = BB->getParent();
4819 MachineFunction::iterator It = BB;
4822 unsigned dest = MI->getOperand(0).getReg();
4823 unsigned ptrA = MI->getOperand(1).getReg();
4824 unsigned ptrB = MI->getOperand(2).getReg();
4825 unsigned incr = MI->getOperand(3).getReg();
4826 DebugLoc dl = MI->getDebugLoc();
4828 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4829 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4830 F->insert(It, loopMBB);
4831 F->insert(It, exitMBB);
4832 exitMBB->splice(exitMBB->begin(), BB,
4833 llvm::next(MachineBasicBlock::iterator(MI)),
4835 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4837 MachineRegisterInfo &RegInfo = F->getRegInfo();
4838 const TargetRegisterClass *RC =
4839 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4840 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4841 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4842 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4843 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4844 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4845 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4846 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4847 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4848 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4849 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
4850 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4851 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4853 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
4857 // fallthrough --> loopMBB
4858 BB->addSuccessor(loopMBB);
4860 // The 4-byte load must be aligned, while a char or short may be
4861 // anywhere in the word. Hence all this nasty bookkeeping code.
4862 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4863 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4864 // xori shift, shift1, 24 [16]
4865 // rlwinm ptr, ptr1, 0, 0, 29
4866 // slw incr2, incr, shift
4867 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4868 // slw mask, mask2, shift
4870 // lwarx tmpDest, ptr
4871 // add tmp, tmpDest, incr2
4872 // andc tmp2, tmpDest, mask
4873 // and tmp3, tmp, mask
4874 // or tmp4, tmp3, tmp2
4877 // fallthrough --> exitMBB
4878 // srw dest, tmpDest, shift
4879 if (ptrA != ZeroReg) {
4880 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4881 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4882 .addReg(ptrA).addReg(ptrB);
4886 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4887 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4888 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4889 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4891 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4892 .addReg(Ptr1Reg).addImm(0).addImm(61);
4894 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4895 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4896 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
4897 .addReg(incr).addReg(ShiftReg);
4899 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4901 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4902 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
4904 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4905 .addReg(Mask2Reg).addReg(ShiftReg);
4908 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4909 .addReg(ZeroReg).addReg(PtrReg);
4911 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
4912 .addReg(Incr2Reg).addReg(TmpDestReg);
4913 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4914 .addReg(TmpDestReg).addReg(MaskReg);
4915 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4916 .addReg(TmpReg).addReg(MaskReg);
4917 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4918 .addReg(Tmp3Reg).addReg(Tmp2Reg);
4919 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4920 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
4921 BuildMI(BB, dl, TII->get(PPC::BCC))
4922 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4923 BB->addSuccessor(loopMBB);
4924 BB->addSuccessor(exitMBB);
4929 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
4935 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4936 MachineBasicBlock *BB) const {
4937 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4939 // To "insert" these instructions we actually have to insert their
4940 // control-flow patterns.
4941 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4942 MachineFunction::iterator It = BB;
4945 MachineFunction *F = BB->getParent();
4947 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4948 MI->getOpcode() == PPC::SELECT_CC_I8)) {
4949 unsigned OpCode = MI->getOpcode() == PPC::SELECT_CC_I8 ?
4950 PPC::ISEL8 : PPC::ISEL;
4951 unsigned SelectPred = MI->getOperand(4).getImm();
4952 DebugLoc dl = MI->getDebugLoc();
4954 // The SelectPred is ((BI << 5) | BO) for a BCC
4955 unsigned BO = SelectPred & 0xF;
4956 assert((BO == 12 || BO == 4) && "invalid predicate BO field for isel");
4958 unsigned TrueOpNo, FalseOpNo;
4965 SelectPred = PPC::InvertPredicate((PPC::Predicate)SelectPred);
4968 BuildMI(*BB, MI, dl, TII->get(OpCode), MI->getOperand(0).getReg())
4969 .addReg(MI->getOperand(TrueOpNo).getReg())
4970 .addReg(MI->getOperand(FalseOpNo).getReg())
4971 .addImm(SelectPred).addReg(MI->getOperand(1).getReg());
4972 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4973 MI->getOpcode() == PPC::SELECT_CC_I8 ||
4974 MI->getOpcode() == PPC::SELECT_CC_F4 ||
4975 MI->getOpcode() == PPC::SELECT_CC_F8 ||
4976 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4979 // The incoming instruction knows the destination vreg to set, the
4980 // condition code register to branch on, the true/false values to
4981 // select between, and a branch opcode to use.
4986 // cmpTY ccX, r1, r2
4988 // fallthrough --> copy0MBB
4989 MachineBasicBlock *thisMBB = BB;
4990 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4991 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4992 unsigned SelectPred = MI->getOperand(4).getImm();
4993 DebugLoc dl = MI->getDebugLoc();
4994 F->insert(It, copy0MBB);
4995 F->insert(It, sinkMBB);
4997 // Transfer the remainder of BB and its successor edges to sinkMBB.
4998 sinkMBB->splice(sinkMBB->begin(), BB,
4999 llvm::next(MachineBasicBlock::iterator(MI)),
5001 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
5003 // Next, add the true and fallthrough blocks as its successors.
5004 BB->addSuccessor(copy0MBB);
5005 BB->addSuccessor(sinkMBB);
5007 BuildMI(BB, dl, TII->get(PPC::BCC))
5008 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
5011 // %FalseValue = ...
5012 // # fallthrough to sinkMBB
5015 // Update machine-CFG edges
5016 BB->addSuccessor(sinkMBB);
5019 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
5022 BuildMI(*BB, BB->begin(), dl,
5023 TII->get(PPC::PHI), MI->getOperand(0).getReg())
5024 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
5025 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
5027 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
5028 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
5029 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
5030 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
5031 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
5032 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
5033 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
5034 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
5036 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
5037 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
5038 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
5039 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
5040 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
5041 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
5042 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
5043 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
5045 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
5046 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
5047 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
5048 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
5049 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
5050 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
5051 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
5052 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
5054 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
5055 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
5056 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
5057 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
5058 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
5059 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
5060 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
5061 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
5063 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
5064 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
5065 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
5066 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
5067 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
5068 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
5069 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
5070 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
5072 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
5073 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
5074 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
5075 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
5076 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
5077 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
5078 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
5079 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
5081 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
5082 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
5083 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
5084 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
5085 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
5086 BB = EmitAtomicBinary(MI, BB, false, 0);
5087 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
5088 BB = EmitAtomicBinary(MI, BB, true, 0);
5090 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
5091 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
5092 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
5094 unsigned dest = MI->getOperand(0).getReg();
5095 unsigned ptrA = MI->getOperand(1).getReg();
5096 unsigned ptrB = MI->getOperand(2).getReg();
5097 unsigned oldval = MI->getOperand(3).getReg();
5098 unsigned newval = MI->getOperand(4).getReg();
5099 DebugLoc dl = MI->getDebugLoc();
5101 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
5102 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
5103 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
5104 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5105 F->insert(It, loop1MBB);
5106 F->insert(It, loop2MBB);
5107 F->insert(It, midMBB);
5108 F->insert(It, exitMBB);
5109 exitMBB->splice(exitMBB->begin(), BB,
5110 llvm::next(MachineBasicBlock::iterator(MI)),
5112 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5116 // fallthrough --> loopMBB
5117 BB->addSuccessor(loop1MBB);
5120 // l[wd]arx dest, ptr
5121 // cmp[wd] dest, oldval
5124 // st[wd]cx. newval, ptr
5128 // st[wd]cx. dest, ptr
5131 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5132 .addReg(ptrA).addReg(ptrB);
5133 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
5134 .addReg(oldval).addReg(dest);
5135 BuildMI(BB, dl, TII->get(PPC::BCC))
5136 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
5137 BB->addSuccessor(loop2MBB);
5138 BB->addSuccessor(midMBB);
5141 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5142 .addReg(newval).addReg(ptrA).addReg(ptrB);
5143 BuildMI(BB, dl, TII->get(PPC::BCC))
5144 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
5145 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
5146 BB->addSuccessor(loop1MBB);
5147 BB->addSuccessor(exitMBB);
5150 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5151 .addReg(dest).addReg(ptrA).addReg(ptrB);
5152 BB->addSuccessor(exitMBB);
5157 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
5158 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
5159 // We must use 64-bit registers for addresses when targeting 64-bit,
5160 // since we're actually doing arithmetic on them. Other registers
5162 bool is64bit = PPCSubTarget.isPPC64();
5163 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
5165 unsigned dest = MI->getOperand(0).getReg();
5166 unsigned ptrA = MI->getOperand(1).getReg();
5167 unsigned ptrB = MI->getOperand(2).getReg();
5168 unsigned oldval = MI->getOperand(3).getReg();
5169 unsigned newval = MI->getOperand(4).getReg();
5170 DebugLoc dl = MI->getDebugLoc();
5172 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
5173 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
5174 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
5175 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5176 F->insert(It, loop1MBB);
5177 F->insert(It, loop2MBB);
5178 F->insert(It, midMBB);
5179 F->insert(It, exitMBB);
5180 exitMBB->splice(exitMBB->begin(), BB,
5181 llvm::next(MachineBasicBlock::iterator(MI)),
5183 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5185 MachineRegisterInfo &RegInfo = F->getRegInfo();
5186 const TargetRegisterClass *RC =
5187 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5188 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5189 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5190 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5191 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5192 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
5193 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
5194 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
5195 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
5196 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
5197 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
5198 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
5199 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
5200 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
5201 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
5203 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
5204 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
5207 // fallthrough --> loopMBB
5208 BB->addSuccessor(loop1MBB);
5210 // The 4-byte load must be aligned, while a char or short may be
5211 // anywhere in the word. Hence all this nasty bookkeeping code.
5212 // add ptr1, ptrA, ptrB [copy if ptrA==0]
5213 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
5214 // xori shift, shift1, 24 [16]
5215 // rlwinm ptr, ptr1, 0, 0, 29
5216 // slw newval2, newval, shift
5217 // slw oldval2, oldval,shift
5218 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
5219 // slw mask, mask2, shift
5220 // and newval3, newval2, mask
5221 // and oldval3, oldval2, mask
5223 // lwarx tmpDest, ptr
5224 // and tmp, tmpDest, mask
5225 // cmpw tmp, oldval3
5228 // andc tmp2, tmpDest, mask
5229 // or tmp4, tmp2, newval3
5234 // stwcx. tmpDest, ptr
5236 // srw dest, tmpDest, shift
5237 if (ptrA != ZeroReg) {
5238 Ptr1Reg = RegInfo.createVirtualRegister(RC);
5239 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
5240 .addReg(ptrA).addReg(ptrB);
5244 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5245 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
5246 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5247 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
5249 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
5250 .addReg(Ptr1Reg).addImm(0).addImm(61);
5252 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
5253 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
5254 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
5255 .addReg(newval).addReg(ShiftReg);
5256 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
5257 .addReg(oldval).addReg(ShiftReg);
5259 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
5261 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
5262 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
5263 .addReg(Mask3Reg).addImm(65535);
5265 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
5266 .addReg(Mask2Reg).addReg(ShiftReg);
5267 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
5268 .addReg(NewVal2Reg).addReg(MaskReg);
5269 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
5270 .addReg(OldVal2Reg).addReg(MaskReg);
5273 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
5274 .addReg(ZeroReg).addReg(PtrReg);
5275 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
5276 .addReg(TmpDestReg).addReg(MaskReg);
5277 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
5278 .addReg(TmpReg).addReg(OldVal3Reg);
5279 BuildMI(BB, dl, TII->get(PPC::BCC))
5280 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
5281 BB->addSuccessor(loop2MBB);
5282 BB->addSuccessor(midMBB);
5285 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
5286 .addReg(TmpDestReg).addReg(MaskReg);
5287 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
5288 .addReg(Tmp2Reg).addReg(NewVal3Reg);
5289 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
5290 .addReg(ZeroReg).addReg(PtrReg);
5291 BuildMI(BB, dl, TII->get(PPC::BCC))
5292 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
5293 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
5294 BB->addSuccessor(loop1MBB);
5295 BB->addSuccessor(exitMBB);
5298 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
5299 .addReg(ZeroReg).addReg(PtrReg);
5300 BB->addSuccessor(exitMBB);
5305 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
5308 llvm_unreachable("Unexpected instr type to insert");
5311 MI->eraseFromParent(); // The pseudo instruction is gone now.
5315 //===----------------------------------------------------------------------===//
5316 // Target Optimization Hooks
5317 //===----------------------------------------------------------------------===//
5319 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
5320 DAGCombinerInfo &DCI) const {
5321 const TargetMachine &TM = getTargetMachine();
5322 SelectionDAG &DAG = DCI.DAG;
5323 DebugLoc dl = N->getDebugLoc();
5324 switch (N->getOpcode()) {
5327 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5328 if (C->isNullValue()) // 0 << V -> 0.
5329 return N->getOperand(0);
5333 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5334 if (C->isNullValue()) // 0 >>u V -> 0.
5335 return N->getOperand(0);
5339 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5340 if (C->isNullValue() || // 0 >>s V -> 0.
5341 C->isAllOnesValue()) // -1 >>s V -> -1.
5342 return N->getOperand(0);
5346 case ISD::SINT_TO_FP:
5347 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
5348 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
5349 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
5350 // We allow the src/dst to be either f32/f64, but the intermediate
5351 // type must be i64.
5352 if (N->getOperand(0).getValueType() == MVT::i64 &&
5353 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
5354 SDValue Val = N->getOperand(0).getOperand(0);
5355 if (Val.getValueType() == MVT::f32) {
5356 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5357 DCI.AddToWorklist(Val.getNode());
5360 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
5361 DCI.AddToWorklist(Val.getNode());
5362 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
5363 DCI.AddToWorklist(Val.getNode());
5364 if (N->getValueType(0) == MVT::f32) {
5365 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
5366 DAG.getIntPtrConstant(0));
5367 DCI.AddToWorklist(Val.getNode());
5370 } else if (N->getOperand(0).getValueType() == MVT::i32) {
5371 // If the intermediate type is i32, we can avoid the load/store here
5378 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
5379 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
5380 !cast<StoreSDNode>(N)->isTruncatingStore() &&
5381 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
5382 N->getOperand(1).getValueType() == MVT::i32 &&
5383 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
5384 SDValue Val = N->getOperand(1).getOperand(0);
5385 if (Val.getValueType() == MVT::f32) {
5386 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5387 DCI.AddToWorklist(Val.getNode());
5389 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
5390 DCI.AddToWorklist(Val.getNode());
5392 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
5393 N->getOperand(2), N->getOperand(3));
5394 DCI.AddToWorklist(Val.getNode());
5398 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
5399 if (cast<StoreSDNode>(N)->isUnindexed() &&
5400 N->getOperand(1).getOpcode() == ISD::BSWAP &&
5401 N->getOperand(1).getNode()->hasOneUse() &&
5402 (N->getOperand(1).getValueType() == MVT::i32 ||
5403 N->getOperand(1).getValueType() == MVT::i16)) {
5404 SDValue BSwapOp = N->getOperand(1).getOperand(0);
5405 // Do an any-extend to 32-bits if this is a half-word input.
5406 if (BSwapOp.getValueType() == MVT::i16)
5407 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
5410 N->getOperand(0), BSwapOp, N->getOperand(2),
5411 DAG.getValueType(N->getOperand(1).getValueType())
5414 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
5415 Ops, array_lengthof(Ops),
5416 cast<StoreSDNode>(N)->getMemoryVT(),
5417 cast<StoreSDNode>(N)->getMemOperand());
5421 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
5422 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
5423 N->getOperand(0).hasOneUse() &&
5424 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
5425 SDValue Load = N->getOperand(0);
5426 LoadSDNode *LD = cast<LoadSDNode>(Load);
5427 // Create the byte-swapping load.
5429 LD->getChain(), // Chain
5430 LD->getBasePtr(), // Ptr
5431 DAG.getValueType(N->getValueType(0)) // VT
5434 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
5435 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3,
5436 LD->getMemoryVT(), LD->getMemOperand());
5438 // If this is an i16 load, insert the truncate.
5439 SDValue ResVal = BSLoad;
5440 if (N->getValueType(0) == MVT::i16)
5441 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
5443 // First, combine the bswap away. This makes the value produced by the
5445 DCI.CombineTo(N, ResVal);
5447 // Next, combine the load away, we give it a bogus result value but a real
5448 // chain result. The result value is dead because the bswap is dead.
5449 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
5451 // Return N so it doesn't get rechecked!
5452 return SDValue(N, 0);
5456 case PPCISD::VCMP: {
5457 // If a VCMPo node already exists with exactly the same operands as this
5458 // node, use its result instead of this node (VCMPo computes both a CR6 and
5459 // a normal output).
5461 if (!N->getOperand(0).hasOneUse() &&
5462 !N->getOperand(1).hasOneUse() &&
5463 !N->getOperand(2).hasOneUse()) {
5465 // Scan all of the users of the LHS, looking for VCMPo's that match.
5466 SDNode *VCMPoNode = 0;
5468 SDNode *LHSN = N->getOperand(0).getNode();
5469 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
5471 if (UI->getOpcode() == PPCISD::VCMPo &&
5472 UI->getOperand(1) == N->getOperand(1) &&
5473 UI->getOperand(2) == N->getOperand(2) &&
5474 UI->getOperand(0) == N->getOperand(0)) {
5479 // If there is no VCMPo node, or if the flag value has a single use, don't
5481 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
5484 // Look at the (necessarily single) use of the flag value. If it has a
5485 // chain, this transformation is more complex. Note that multiple things
5486 // could use the value result, which we should ignore.
5487 SDNode *FlagUser = 0;
5488 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
5489 FlagUser == 0; ++UI) {
5490 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
5492 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
5493 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
5500 // If the user is a MFCR instruction, we know this is safe. Otherwise we
5501 // give up for right now.
5502 if (FlagUser->getOpcode() == PPCISD::MFCR)
5503 return SDValue(VCMPoNode, 0);
5508 // If this is a branch on an altivec predicate comparison, lower this so
5509 // that we don't have to do a MFCR: instead, branch directly on CR6. This
5510 // lowering is done pre-legalize, because the legalizer lowers the predicate
5511 // compare down to code that is difficult to reassemble.
5512 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
5513 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
5517 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
5518 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
5519 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
5520 assert(isDot && "Can't compare against a vector result!");
5522 // If this is a comparison against something other than 0/1, then we know
5523 // that the condition is never/always true.
5524 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
5525 if (Val != 0 && Val != 1) {
5526 if (CC == ISD::SETEQ) // Cond never true, remove branch.
5527 return N->getOperand(0);
5528 // Always !=, turn it into an unconditional branch.
5529 return DAG.getNode(ISD::BR, dl, MVT::Other,
5530 N->getOperand(0), N->getOperand(4));
5533 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
5535 // Create the PPCISD altivec 'dot' comparison node.
5536 std::vector<EVT> VTs;
5538 LHS.getOperand(2), // LHS of compare
5539 LHS.getOperand(3), // RHS of compare
5540 DAG.getConstant(CompareOpc, MVT::i32)
5542 VTs.push_back(LHS.getOperand(2).getValueType());
5543 VTs.push_back(MVT::Glue);
5544 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5546 // Unpack the result based on how the target uses it.
5547 PPC::Predicate CompOpc;
5548 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
5549 default: // Can't happen, don't crash on invalid number though.
5550 case 0: // Branch on the value of the EQ bit of CR6.
5551 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
5553 case 1: // Branch on the inverted value of the EQ bit of CR6.
5554 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
5556 case 2: // Branch on the value of the LT bit of CR6.
5557 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
5559 case 3: // Branch on the inverted value of the LT bit of CR6.
5560 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
5564 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
5565 DAG.getConstant(CompOpc, MVT::i32),
5566 DAG.getRegister(PPC::CR6, MVT::i32),
5567 N->getOperand(4), CompNode.getValue(1));
5576 //===----------------------------------------------------------------------===//
5577 // Inline Assembly Support
5578 //===----------------------------------------------------------------------===//
5580 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5583 const SelectionDAG &DAG,
5584 unsigned Depth) const {
5585 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
5586 switch (Op.getOpcode()) {
5588 case PPCISD::LBRX: {
5589 // lhbrx is known to have the top bits cleared out.
5590 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
5591 KnownZero = 0xFFFF0000;
5594 case ISD::INTRINSIC_WO_CHAIN: {
5595 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
5597 case Intrinsic::ppc_altivec_vcmpbfp_p:
5598 case Intrinsic::ppc_altivec_vcmpeqfp_p:
5599 case Intrinsic::ppc_altivec_vcmpequb_p:
5600 case Intrinsic::ppc_altivec_vcmpequh_p:
5601 case Intrinsic::ppc_altivec_vcmpequw_p:
5602 case Intrinsic::ppc_altivec_vcmpgefp_p:
5603 case Intrinsic::ppc_altivec_vcmpgtfp_p:
5604 case Intrinsic::ppc_altivec_vcmpgtsb_p:
5605 case Intrinsic::ppc_altivec_vcmpgtsh_p:
5606 case Intrinsic::ppc_altivec_vcmpgtsw_p:
5607 case Intrinsic::ppc_altivec_vcmpgtub_p:
5608 case Intrinsic::ppc_altivec_vcmpgtuh_p:
5609 case Intrinsic::ppc_altivec_vcmpgtuw_p:
5610 KnownZero = ~1U; // All bits but the low one are known to be zero.
5618 /// getConstraintType - Given a constraint, return the type of
5619 /// constraint it is for this target.
5620 PPCTargetLowering::ConstraintType
5621 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
5622 if (Constraint.size() == 1) {
5623 switch (Constraint[0]) {
5630 return C_RegisterClass;
5633 return TargetLowering::getConstraintType(Constraint);
5636 /// Examine constraint type and operand type and determine a weight value.
5637 /// This object must already have been set up with the operand type
5638 /// and the current alternative constraint selected.
5639 TargetLowering::ConstraintWeight
5640 PPCTargetLowering::getSingleConstraintMatchWeight(
5641 AsmOperandInfo &info, const char *constraint) const {
5642 ConstraintWeight weight = CW_Invalid;
5643 Value *CallOperandVal = info.CallOperandVal;
5644 // If we don't have a value, we can't do a match,
5645 // but allow it at the lowest weight.
5646 if (CallOperandVal == NULL)
5648 Type *type = CallOperandVal->getType();
5649 // Look at the constraint type.
5650 switch (*constraint) {
5652 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
5655 if (type->isIntegerTy())
5656 weight = CW_Register;
5659 if (type->isFloatTy())
5660 weight = CW_Register;
5663 if (type->isDoubleTy())
5664 weight = CW_Register;
5667 if (type->isVectorTy())
5668 weight = CW_Register;
5671 weight = CW_Register;
5677 std::pair<unsigned, const TargetRegisterClass*>
5678 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5680 if (Constraint.size() == 1) {
5681 // GCC RS6000 Constraint Letters
5682 switch (Constraint[0]) {
5685 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
5686 return std::make_pair(0U, &PPC::G8RCRegClass);
5687 return std::make_pair(0U, &PPC::GPRCRegClass);
5690 return std::make_pair(0U, &PPC::F4RCRegClass);
5692 return std::make_pair(0U, &PPC::F8RCRegClass);
5695 return std::make_pair(0U, &PPC::VRRCRegClass);
5697 return std::make_pair(0U, &PPC::CRRCRegClass);
5701 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5705 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5706 /// vector. If it is invalid, don't add anything to Ops.
5707 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5708 std::string &Constraint,
5709 std::vector<SDValue>&Ops,
5710 SelectionDAG &DAG) const {
5711 SDValue Result(0,0);
5713 // Only support length 1 constraints.
5714 if (Constraint.length() > 1) return;
5716 char Letter = Constraint[0];
5727 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
5728 if (!CST) return; // Must be an immediate to match.
5729 unsigned Value = CST->getZExtValue();
5731 default: llvm_unreachable("Unknown constraint letter!");
5732 case 'I': // "I" is a signed 16-bit constant.
5733 if ((short)Value == (int)Value)
5734 Result = DAG.getTargetConstant(Value, Op.getValueType());
5736 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
5737 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
5738 if ((short)Value == 0)
5739 Result = DAG.getTargetConstant(Value, Op.getValueType());
5741 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
5742 if ((Value >> 16) == 0)
5743 Result = DAG.getTargetConstant(Value, Op.getValueType());
5745 case 'M': // "M" is a constant that is greater than 31.
5747 Result = DAG.getTargetConstant(Value, Op.getValueType());
5749 case 'N': // "N" is a positive constant that is an exact power of two.
5750 if ((int)Value > 0 && isPowerOf2_32(Value))
5751 Result = DAG.getTargetConstant(Value, Op.getValueType());
5753 case 'O': // "O" is the constant zero.
5755 Result = DAG.getTargetConstant(Value, Op.getValueType());
5757 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
5758 if ((short)-Value == (int)-Value)
5759 Result = DAG.getTargetConstant(Value, Op.getValueType());
5766 if (Result.getNode()) {
5767 Ops.push_back(Result);
5771 // Handle standard constraint letters.
5772 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5775 // isLegalAddressingMode - Return true if the addressing mode represented
5776 // by AM is legal for this target, for a load/store of the specified type.
5777 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5779 // FIXME: PPC does not allow r+i addressing modes for vectors!
5781 // PPC allows a sign-extended 16-bit immediate field.
5782 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
5785 // No global is ever allowed as a base.
5789 // PPC only support r+r,
5791 case 0: // "r+i" or just "i", depending on HasBaseReg.
5794 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
5796 // Otherwise we have r+r or r+i.
5799 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
5801 // Allow 2*r as r+r.
5804 // No other scales are supported.
5811 /// isLegalAddressImmediate - Return true if the integer value can be used
5812 /// as the offset of the target addressing mode for load / store of the
5814 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,Type *Ty) const{
5815 // PPC allows a sign-extended 16-bit immediate field.
5816 return (V > -(1 << 16) && V < (1 << 16)-1);
5819 bool PPCTargetLowering::isLegalAddressImmediate(GlobalValue* GV) const {
5823 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
5824 SelectionDAG &DAG) const {
5825 MachineFunction &MF = DAG.getMachineFunction();
5826 MachineFrameInfo *MFI = MF.getFrameInfo();
5827 MFI->setReturnAddressIsTaken(true);
5829 DebugLoc dl = Op.getDebugLoc();
5830 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5832 // Make sure the function does not optimize away the store of the RA to
5834 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
5835 FuncInfo->setLRStoreRequired();
5836 bool isPPC64 = PPCSubTarget.isPPC64();
5837 bool isDarwinABI = PPCSubTarget.isDarwinABI();
5840 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5843 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
5844 isPPC64? MVT::i64 : MVT::i32);
5845 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
5846 DAG.getNode(ISD::ADD, dl, getPointerTy(),
5848 MachinePointerInfo(), false, false, false, 0);
5851 // Just load the return address off the stack.
5852 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
5853 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
5854 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
5857 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
5858 SelectionDAG &DAG) const {
5859 DebugLoc dl = Op.getDebugLoc();
5860 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5862 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5863 bool isPPC64 = PtrVT == MVT::i64;
5865 MachineFunction &MF = DAG.getMachineFunction();
5866 MachineFrameInfo *MFI = MF.getFrameInfo();
5867 MFI->setFrameAddressIsTaken(true);
5868 bool is31 = (getTargetMachine().Options.DisableFramePointerElim(MF) ||
5869 MFI->hasVarSizedObjects()) &&
5870 MFI->getStackSize() &&
5871 !MF.getFunction()->hasFnAttr(Attribute::Naked);
5872 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) :
5873 (is31 ? PPC::R31 : PPC::R1);
5874 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
5877 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
5878 FrameAddr, MachinePointerInfo(), false, false,
5884 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5885 // The PowerPC target isn't yet aware of offsets.
5889 /// getOptimalMemOpType - Returns the target specific optimal type for load
5890 /// and store operations as a result of memset, memcpy, and memmove
5891 /// lowering. If DstAlign is zero that means it's safe to destination
5892 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
5893 /// means there isn't a need to check it against alignment requirement,
5894 /// probably because the source does not need to be loaded. If
5895 /// 'IsZeroVal' is true, that means it's safe to return a
5896 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
5897 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
5898 /// constant so it does not need to be loaded.
5899 /// It returns EVT::Other if the type should be determined using generic
5900 /// target-independent logic.
5901 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
5902 unsigned DstAlign, unsigned SrcAlign,
5905 MachineFunction &MF) const {
5906 if (this->PPCSubTarget.isPPC64()) {
5913 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
5914 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
5915 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
5916 /// is expanded to mul + add.
5917 bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const {
5921 switch (VT.getSimpleVT().SimpleTy) {
5933 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
5935 return TargetLowering::getSchedulingPreference(N);