1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/Constants.h"
30 #include "llvm/Function.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
37 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
38 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
41 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
42 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
46 // Use _setjmp/_longjmp instead of setjmp/longjmp.
47 setUseUnderscoreSetJmp(true);
48 setUseUnderscoreLongJmp(true);
50 // Set up the register classes.
51 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
52 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
53 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
55 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
56 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
57 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
59 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
61 // PowerPC has pre-inc load and store's.
62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
65 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
67 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
70 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
73 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg)
74 setConvertAction(MVT::ppcf128, MVT::f64, Expand);
75 setConvertAction(MVT::ppcf128, MVT::f32, Expand);
76 // This is used in the ppcf128->int sequence. Note it has different semantics
77 // from FP_ROUND: that rounds to nearest, this rounds to zero.
78 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
80 // PowerPC has no intrinsics for these particular operations
81 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
82 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
83 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
84 setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
86 // PowerPC has no SREM/UREM instructions
87 setOperationAction(ISD::SREM, MVT::i32, Expand);
88 setOperationAction(ISD::UREM, MVT::i32, Expand);
89 setOperationAction(ISD::SREM, MVT::i64, Expand);
90 setOperationAction(ISD::UREM, MVT::i64, Expand);
92 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
93 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
94 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
95 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
96 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
97 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
98 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
99 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
100 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
102 // We don't support sin/cos/sqrt/fmod/pow
103 setOperationAction(ISD::FSIN , MVT::f64, Expand);
104 setOperationAction(ISD::FCOS , MVT::f64, Expand);
105 setOperationAction(ISD::FREM , MVT::f64, Expand);
106 setOperationAction(ISD::FPOW , MVT::f64, Expand);
107 setOperationAction(ISD::FSIN , MVT::f32, Expand);
108 setOperationAction(ISD::FCOS , MVT::f32, Expand);
109 setOperationAction(ISD::FREM , MVT::f32, Expand);
110 setOperationAction(ISD::FPOW , MVT::f32, Expand);
112 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
114 // If we're enabling GP optimizations, use hardware square root
115 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
116 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
117 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
120 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
121 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
123 // PowerPC does not have BSWAP, CTPOP or CTTZ
124 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
125 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
126 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
127 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
128 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
129 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
131 // PowerPC does not have ROTR
132 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
134 // PowerPC does not have Select
135 setOperationAction(ISD::SELECT, MVT::i32, Expand);
136 setOperationAction(ISD::SELECT, MVT::i64, Expand);
137 setOperationAction(ISD::SELECT, MVT::f32, Expand);
138 setOperationAction(ISD::SELECT, MVT::f64, Expand);
140 // PowerPC wants to turn select_cc of FP into fsel when possible.
141 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
142 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
144 // PowerPC wants to optimize integer setcc a bit
145 setOperationAction(ISD::SETCC, MVT::i32, Custom);
147 // PowerPC does not have BRCOND which requires SetCC
148 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
150 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
152 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
153 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
155 // PowerPC does not have [U|S]INT_TO_FP
156 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
157 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
159 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
160 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
161 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
162 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
164 // We cannot sextinreg(i1). Expand to shifts.
165 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
167 // Support label based line numbers.
168 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
169 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
171 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
172 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
173 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
174 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
177 // We want to legalize GlobalAddress and ConstantPool nodes into the
178 // appropriate instructions to materialize the address.
179 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
180 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
181 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
182 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
183 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
184 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
185 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
186 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
188 // RET must be custom lowered, to meet ABI requirements
189 setOperationAction(ISD::RET , MVT::Other, Custom);
191 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
192 setOperationAction(ISD::VASTART , MVT::Other, Custom);
194 // VAARG is custom lowered with ELF 32 ABI
195 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
196 setOperationAction(ISD::VAARG, MVT::Other, Custom);
198 setOperationAction(ISD::VAARG, MVT::Other, Expand);
200 // Use the default implementation.
201 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
202 setOperationAction(ISD::VAEND , MVT::Other, Expand);
203 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
204 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
205 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
206 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
208 // We want to custom lower some of our intrinsics.
209 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
211 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
212 // They also have instructions for converting between i64 and fp.
213 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
214 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
215 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
216 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
217 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
219 // FIXME: disable this lowered code. This generates 64-bit register values,
220 // and we don't model the fact that the top part is clobbered by calls. We
221 // need to flag these together so that the value isn't live across a call.
222 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
224 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
225 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
227 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
228 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
231 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
232 // 64-bit PowerPC implementations can support i64 types directly
233 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
234 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
235 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
236 // 64-bit PowerPC wants to expand i128 shifts itself.
237 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
238 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
239 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
241 // 32-bit PowerPC wants to expand i64 shifts itself.
242 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
243 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
244 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
247 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
248 // First set operation action for all vector types to expand. Then we
249 // will selectively turn on ones that can be effectively codegen'd.
250 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
251 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
252 // add/sub are legal for all supported vector VT's.
253 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
254 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
256 // We promote all shuffles to v16i8.
257 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
258 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
260 // We promote all non-typed operations to v4i32.
261 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
262 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
263 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
264 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
265 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
266 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
267 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
268 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
269 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
270 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
271 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
272 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
274 // No other operations are legal.
275 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
276 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
277 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
278 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
279 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
280 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
281 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
282 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
283 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
284 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
285 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand);
286 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand);
287 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand);
288 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand);
289 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
290 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand);
291 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
292 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
293 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
296 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
297 // with merges, splats, etc.
298 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
300 setOperationAction(ISD::AND , MVT::v4i32, Legal);
301 setOperationAction(ISD::OR , MVT::v4i32, Legal);
302 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
303 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
304 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
305 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
307 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
308 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
309 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
310 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
312 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
313 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
314 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
315 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
317 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
318 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
320 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
321 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
322 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
323 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
326 setSetCCResultType(MVT::i32);
327 setShiftAmountType(MVT::i32);
328 setSetCCResultContents(ZeroOrOneSetCCResult);
330 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
331 setStackPointerRegisterToSaveRestore(PPC::X1);
332 setExceptionPointerRegister(PPC::X3);
333 setExceptionSelectorRegister(PPC::X4);
335 setStackPointerRegisterToSaveRestore(PPC::R1);
336 setExceptionPointerRegister(PPC::R3);
337 setExceptionSelectorRegister(PPC::R4);
340 // We have target-specific dag combine patterns for the following nodes:
341 setTargetDAGCombine(ISD::SINT_TO_FP);
342 setTargetDAGCombine(ISD::STORE);
343 setTargetDAGCombine(ISD::BR_CC);
344 setTargetDAGCombine(ISD::BSWAP);
346 // Darwin long double math library functions have $LDBL128 appended.
347 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
348 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
349 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
350 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
351 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
352 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
355 computeRegisterProperties();
358 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
359 /// function arguments in the caller parameter area.
360 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
361 TargetMachine &TM = getTargetMachine();
362 // Darwin passes everything on 4 byte boundary.
363 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
369 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
372 case PPCISD::FSEL: return "PPCISD::FSEL";
373 case PPCISD::FCFID: return "PPCISD::FCFID";
374 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
375 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
376 case PPCISD::STFIWX: return "PPCISD::STFIWX";
377 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
378 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
379 case PPCISD::VPERM: return "PPCISD::VPERM";
380 case PPCISD::Hi: return "PPCISD::Hi";
381 case PPCISD::Lo: return "PPCISD::Lo";
382 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
383 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
384 case PPCISD::SRL: return "PPCISD::SRL";
385 case PPCISD::SRA: return "PPCISD::SRA";
386 case PPCISD::SHL: return "PPCISD::SHL";
387 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
388 case PPCISD::STD_32: return "PPCISD::STD_32";
389 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
390 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
391 case PPCISD::MTCTR: return "PPCISD::MTCTR";
392 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
393 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
394 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
395 case PPCISD::MFCR: return "PPCISD::MFCR";
396 case PPCISD::VCMP: return "PPCISD::VCMP";
397 case PPCISD::VCMPo: return "PPCISD::VCMPo";
398 case PPCISD::LBRX: return "PPCISD::LBRX";
399 case PPCISD::STBRX: return "PPCISD::STBRX";
400 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
401 case PPCISD::MFFS: return "PPCISD::MFFS";
402 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
403 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
404 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
405 case PPCISD::MTFSF: return "PPCISD::MTFSF";
409 //===----------------------------------------------------------------------===//
410 // Node matching predicates, for use by the tblgen matching code.
411 //===----------------------------------------------------------------------===//
413 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
414 static bool isFloatingPointZero(SDOperand Op) {
415 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
416 return CFP->getValueAPF().isZero();
417 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
418 // Maybe this has already been legalized into the constant pool?
419 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
420 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
421 return CFP->getValueAPF().isZero();
426 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
427 /// true if Op is undef or if it matches the specified value.
428 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
429 return Op.getOpcode() == ISD::UNDEF ||
430 cast<ConstantSDNode>(Op)->getValue() == Val;
433 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
434 /// VPKUHUM instruction.
435 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
437 for (unsigned i = 0; i != 16; ++i)
438 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
441 for (unsigned i = 0; i != 8; ++i)
442 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
443 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
449 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
450 /// VPKUWUM instruction.
451 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
453 for (unsigned i = 0; i != 16; i += 2)
454 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
455 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
458 for (unsigned i = 0; i != 8; i += 2)
459 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
460 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
461 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
462 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
468 /// isVMerge - Common function, used to match vmrg* shuffles.
470 static bool isVMerge(SDNode *N, unsigned UnitSize,
471 unsigned LHSStart, unsigned RHSStart) {
472 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
473 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
474 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
475 "Unsupported merge size!");
477 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
478 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
479 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
480 LHSStart+j+i*UnitSize) ||
481 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
482 RHSStart+j+i*UnitSize))
488 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
489 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
490 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
492 return isVMerge(N, UnitSize, 8, 24);
493 return isVMerge(N, UnitSize, 8, 8);
496 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
497 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
498 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
500 return isVMerge(N, UnitSize, 0, 16);
501 return isVMerge(N, UnitSize, 0, 0);
505 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
506 /// amount, otherwise return -1.
507 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
508 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
509 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
510 // Find the first non-undef value in the shuffle mask.
512 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
515 if (i == 16) return -1; // all undef.
517 // Otherwise, check to see if the rest of the elements are consequtively
518 // numbered from this value.
519 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
520 if (ShiftAmt < i) return -1;
524 // Check the rest of the elements to see if they are consequtive.
525 for (++i; i != 16; ++i)
526 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
529 // Check the rest of the elements to see if they are consequtive.
530 for (++i; i != 16; ++i)
531 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
538 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
539 /// specifies a splat of a single element that is suitable for input to
540 /// VSPLTB/VSPLTH/VSPLTW.
541 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
542 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
543 N->getNumOperands() == 16 &&
544 (EltSize == 1 || EltSize == 2 || EltSize == 4));
546 // This is a splat operation if each element of the permute is the same, and
547 // if the value doesn't reference the second vector.
548 unsigned ElementBase = 0;
549 SDOperand Elt = N->getOperand(0);
550 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
551 ElementBase = EltV->getValue();
553 return false; // FIXME: Handle UNDEF elements too!
555 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
558 // Check that they are consequtive.
559 for (unsigned i = 1; i != EltSize; ++i) {
560 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
561 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
565 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
566 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
567 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
568 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
569 "Invalid VECTOR_SHUFFLE mask!");
570 for (unsigned j = 0; j != EltSize; ++j)
571 if (N->getOperand(i+j) != N->getOperand(j))
578 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
580 bool PPC::isAllNegativeZeroVector(SDNode *N) {
581 assert(N->getOpcode() == ISD::BUILD_VECTOR);
582 if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
583 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
584 return CFP->getValueAPF().isNegZero();
588 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
589 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
590 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
591 assert(isSplatShuffleMask(N, EltSize));
592 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
595 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
596 /// by using a vspltis[bhw] instruction of the specified element size, return
597 /// the constant being splatted. The ByteSize field indicates the number of
598 /// bytes of each element [124] -> [bhw].
599 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
600 SDOperand OpVal(0, 0);
602 // If ByteSize of the splat is bigger than the element size of the
603 // build_vector, then we have a case where we are checking for a splat where
604 // multiple elements of the buildvector are folded together into a single
605 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
606 unsigned EltSize = 16/N->getNumOperands();
607 if (EltSize < ByteSize) {
608 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
609 SDOperand UniquedVals[4];
610 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
612 // See if all of the elements in the buildvector agree across.
613 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
614 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
615 // If the element isn't a constant, bail fully out.
616 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
619 if (UniquedVals[i&(Multiple-1)].Val == 0)
620 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
621 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
622 return SDOperand(); // no match.
625 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
626 // either constant or undef values that are identical for each chunk. See
627 // if these chunks can form into a larger vspltis*.
629 // Check to see if all of the leading entries are either 0 or -1. If
630 // neither, then this won't fit into the immediate field.
631 bool LeadingZero = true;
632 bool LeadingOnes = true;
633 for (unsigned i = 0; i != Multiple-1; ++i) {
634 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
636 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
637 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
639 // Finally, check the least significant entry.
641 if (UniquedVals[Multiple-1].Val == 0)
642 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
643 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
645 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
648 if (UniquedVals[Multiple-1].Val == 0)
649 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
650 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
651 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
652 return DAG.getTargetConstant(Val, MVT::i32);
658 // Check to see if this buildvec has a single non-undef value in its elements.
659 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
660 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
662 OpVal = N->getOperand(i);
663 else if (OpVal != N->getOperand(i))
667 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
669 unsigned ValSizeInBytes = 0;
671 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
672 Value = CN->getValue();
673 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
674 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
675 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
676 Value = FloatToBits(CN->getValueAPF().convertToFloat());
680 // If the splat value is larger than the element value, then we can never do
681 // this splat. The only case that we could fit the replicated bits into our
682 // immediate field for would be zero, and we prefer to use vxor for it.
683 if (ValSizeInBytes < ByteSize) return SDOperand();
685 // If the element value is larger than the splat value, cut it in half and
686 // check to see if the two halves are equal. Continue doing this until we
687 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
688 while (ValSizeInBytes > ByteSize) {
689 ValSizeInBytes >>= 1;
691 // If the top half equals the bottom half, we're still ok.
692 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
693 (Value & ((1 << (8*ValSizeInBytes))-1)))
697 // Properly sign extend the value.
698 int ShAmt = (4-ByteSize)*8;
699 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
701 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
702 if (MaskVal == 0) return SDOperand();
704 // Finally, if this value fits in a 5 bit sext field, return it
705 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
706 return DAG.getTargetConstant(MaskVal, MVT::i32);
710 //===----------------------------------------------------------------------===//
711 // Addressing Mode Selection
712 //===----------------------------------------------------------------------===//
714 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
715 /// or 64-bit immediate, and if the value can be accurately represented as a
716 /// sign extension from a 16-bit value. If so, this returns true and the
718 static bool isIntS16Immediate(SDNode *N, short &Imm) {
719 if (N->getOpcode() != ISD::Constant)
722 Imm = (short)cast<ConstantSDNode>(N)->getValue();
723 if (N->getValueType(0) == MVT::i32)
724 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
726 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
728 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
729 return isIntS16Immediate(Op.Val, Imm);
733 /// SelectAddressRegReg - Given the specified addressed, check to see if it
734 /// can be represented as an indexed [r+r] operation. Returns false if it
735 /// can be more efficiently represented with [r+imm].
736 bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
740 if (N.getOpcode() == ISD::ADD) {
741 if (isIntS16Immediate(N.getOperand(1), imm))
743 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
746 Base = N.getOperand(0);
747 Index = N.getOperand(1);
749 } else if (N.getOpcode() == ISD::OR) {
750 if (isIntS16Immediate(N.getOperand(1), imm))
751 return false; // r+i can fold it if we can.
753 // If this is an or of disjoint bitfields, we can codegen this as an add
754 // (for better address arithmetic) if the LHS and RHS of the OR are provably
756 APInt LHSKnownZero, LHSKnownOne;
757 APInt RHSKnownZero, RHSKnownOne;
758 DAG.ComputeMaskedBits(N.getOperand(0),
759 APInt::getAllOnesValue(N.getOperand(0)
760 .getValueSizeInBits()),
761 LHSKnownZero, LHSKnownOne);
763 if (LHSKnownZero.getBoolValue()) {
764 DAG.ComputeMaskedBits(N.getOperand(1),
765 APInt::getAllOnesValue(N.getOperand(1)
766 .getValueSizeInBits()),
767 RHSKnownZero, RHSKnownOne);
768 // If all of the bits are known zero on the LHS or RHS, the add won't
770 if (~(LHSKnownZero | RHSKnownZero) == 0) {
771 Base = N.getOperand(0);
772 Index = N.getOperand(1);
781 /// Returns true if the address N can be represented by a base register plus
782 /// a signed 16-bit displacement [r+imm], and if it is not better
783 /// represented as reg+reg.
784 bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
785 SDOperand &Base, SelectionDAG &DAG){
786 // If this can be more profitably realized as r+r, fail.
787 if (SelectAddressRegReg(N, Disp, Base, DAG))
790 if (N.getOpcode() == ISD::ADD) {
792 if (isIntS16Immediate(N.getOperand(1), imm)) {
793 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
794 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
795 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
797 Base = N.getOperand(0);
799 return true; // [r+i]
800 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
801 // Match LOAD (ADD (X, Lo(G))).
802 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
803 && "Cannot handle constant offsets yet!");
804 Disp = N.getOperand(1).getOperand(0); // The global address.
805 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
806 Disp.getOpcode() == ISD::TargetConstantPool ||
807 Disp.getOpcode() == ISD::TargetJumpTable);
808 Base = N.getOperand(0);
809 return true; // [&g+r]
811 } else if (N.getOpcode() == ISD::OR) {
813 if (isIntS16Immediate(N.getOperand(1), imm)) {
814 // If this is an or of disjoint bitfields, we can codegen this as an add
815 // (for better address arithmetic) if the LHS and RHS of the OR are
816 // provably disjoint.
817 APInt LHSKnownZero, LHSKnownOne;
818 DAG.ComputeMaskedBits(N.getOperand(0),
819 APInt::getAllOnesValue(32),
820 LHSKnownZero, LHSKnownOne);
821 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
822 // If all of the bits are known zero on the LHS or RHS, the add won't
824 Base = N.getOperand(0);
825 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
829 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
830 // Loading from a constant address.
832 // If this address fits entirely in a 16-bit sext immediate field, codegen
835 if (isIntS16Immediate(CN, Imm)) {
836 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
837 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
841 // Handle 32-bit sext immediates with LIS + addr mode.
842 if (CN->getValueType(0) == MVT::i32 ||
843 (int64_t)CN->getValue() == (int)CN->getValue()) {
844 int Addr = (int)CN->getValue();
846 // Otherwise, break this down into an LIS + disp.
847 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
849 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
850 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
851 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
856 Disp = DAG.getTargetConstant(0, getPointerTy());
857 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
858 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
861 return true; // [r+0]
864 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
865 /// represented as an indexed [r+r] operation.
866 bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
869 // Check to see if we can easily represent this as an [r+r] address. This
870 // will fail if it thinks that the address is more profitably represented as
871 // reg+imm, e.g. where imm = 0.
872 if (SelectAddressRegReg(N, Base, Index, DAG))
875 // If the operand is an addition, always emit this as [r+r], since this is
876 // better (for code size, and execution, as the memop does the add for free)
877 // than emitting an explicit add.
878 if (N.getOpcode() == ISD::ADD) {
879 Base = N.getOperand(0);
880 Index = N.getOperand(1);
884 // Otherwise, do it the hard way, using R0 as the base register.
885 Base = DAG.getRegister(PPC::R0, N.getValueType());
890 /// SelectAddressRegImmShift - Returns true if the address N can be
891 /// represented by a base register plus a signed 14-bit displacement
892 /// [r+imm*4]. Suitable for use by STD and friends.
893 bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
896 // If this can be more profitably realized as r+r, fail.
897 if (SelectAddressRegReg(N, Disp, Base, DAG))
900 if (N.getOpcode() == ISD::ADD) {
902 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
903 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
904 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
905 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
907 Base = N.getOperand(0);
909 return true; // [r+i]
910 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
911 // Match LOAD (ADD (X, Lo(G))).
912 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
913 && "Cannot handle constant offsets yet!");
914 Disp = N.getOperand(1).getOperand(0); // The global address.
915 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
916 Disp.getOpcode() == ISD::TargetConstantPool ||
917 Disp.getOpcode() == ISD::TargetJumpTable);
918 Base = N.getOperand(0);
919 return true; // [&g+r]
921 } else if (N.getOpcode() == ISD::OR) {
923 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
924 // If this is an or of disjoint bitfields, we can codegen this as an add
925 // (for better address arithmetic) if the LHS and RHS of the OR are
926 // provably disjoint.
927 APInt LHSKnownZero, LHSKnownOne;
928 DAG.ComputeMaskedBits(N.getOperand(0),
929 APInt::getAllOnesValue(32),
930 LHSKnownZero, LHSKnownOne);
931 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
932 // If all of the bits are known zero on the LHS or RHS, the add won't
934 Base = N.getOperand(0);
935 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
939 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
940 // Loading from a constant address. Verify low two bits are clear.
941 if ((CN->getValue() & 3) == 0) {
942 // If this address fits entirely in a 14-bit sext immediate field, codegen
945 if (isIntS16Immediate(CN, Imm)) {
946 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
947 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
951 // Fold the low-part of 32-bit absolute addresses into addr mode.
952 if (CN->getValueType(0) == MVT::i32 ||
953 (int64_t)CN->getValue() == (int)CN->getValue()) {
954 int Addr = (int)CN->getValue();
956 // Otherwise, break this down into an LIS + disp.
957 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
959 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
960 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
961 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
967 Disp = DAG.getTargetConstant(0, getPointerTy());
968 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
969 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
972 return true; // [r+0]
976 /// getPreIndexedAddressParts - returns true by value, base pointer and
977 /// offset pointer and addressing mode by reference if the node's address
978 /// can be legally represented as pre-indexed load / store address.
979 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
981 ISD::MemIndexedMode &AM,
983 // Disabled by default for now.
984 if (!EnablePPCPreinc) return false;
988 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
989 Ptr = LD->getBasePtr();
990 VT = LD->getMemoryVT();
992 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
994 Ptr = ST->getBasePtr();
995 VT = ST->getMemoryVT();
999 // PowerPC doesn't have preinc load/store instructions for vectors.
1000 if (MVT::isVector(VT))
1003 // TODO: Check reg+reg first.
1005 // LDU/STU use reg+imm*4, others use reg+imm.
1006 if (VT != MVT::i64) {
1008 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1012 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1016 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1017 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1018 // sext i32 to i64 when addr mode is r+i.
1019 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1020 LD->getExtensionType() == ISD::SEXTLOAD &&
1021 isa<ConstantSDNode>(Offset))
1029 //===----------------------------------------------------------------------===//
1030 // LowerOperation implementation
1031 //===----------------------------------------------------------------------===//
1033 SDOperand PPCTargetLowering::LowerConstantPool(SDOperand Op,
1034 SelectionDAG &DAG) {
1035 MVT::ValueType PtrVT = Op.getValueType();
1036 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1037 Constant *C = CP->getConstVal();
1038 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1039 SDOperand Zero = DAG.getConstant(0, PtrVT);
1041 const TargetMachine &TM = DAG.getTarget();
1043 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
1044 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
1046 // If this is a non-darwin platform, we don't support non-static relo models
1048 if (TM.getRelocationModel() == Reloc::Static ||
1049 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1050 // Generate non-pic code that has direct accesses to the constant pool.
1051 // The address of the global is just (hi(&g)+lo(&g)).
1052 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1055 if (TM.getRelocationModel() == Reloc::PIC_) {
1056 // With PIC, the first instruction is actually "GR+hi(&G)".
1057 Hi = DAG.getNode(ISD::ADD, PtrVT,
1058 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1061 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1065 SDOperand PPCTargetLowering::LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
1066 MVT::ValueType PtrVT = Op.getValueType();
1067 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1068 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1069 SDOperand Zero = DAG.getConstant(0, PtrVT);
1071 const TargetMachine &TM = DAG.getTarget();
1073 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
1074 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
1076 // If this is a non-darwin platform, we don't support non-static relo models
1078 if (TM.getRelocationModel() == Reloc::Static ||
1079 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1080 // Generate non-pic code that has direct accesses to the constant pool.
1081 // The address of the global is just (hi(&g)+lo(&g)).
1082 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1085 if (TM.getRelocationModel() == Reloc::PIC_) {
1086 // With PIC, the first instruction is actually "GR+hi(&G)".
1087 Hi = DAG.getNode(ISD::ADD, PtrVT,
1088 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1091 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1095 SDOperand PPCTargetLowering::LowerGlobalTLSAddress(SDOperand Op,
1096 SelectionDAG &DAG) {
1097 assert(0 && "TLS not implemented for PPC.");
1100 SDOperand PPCTargetLowering::LowerGlobalAddress(SDOperand Op,
1101 SelectionDAG &DAG) {
1102 MVT::ValueType PtrVT = Op.getValueType();
1103 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1104 GlobalValue *GV = GSDN->getGlobal();
1105 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1106 // If it's a debug information descriptor, don't mess with it.
1107 if (DAG.isVerifiedDebugInfoDesc(Op))
1109 SDOperand Zero = DAG.getConstant(0, PtrVT);
1111 const TargetMachine &TM = DAG.getTarget();
1113 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
1114 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
1116 // If this is a non-darwin platform, we don't support non-static relo models
1118 if (TM.getRelocationModel() == Reloc::Static ||
1119 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1120 // Generate non-pic code that has direct accesses to globals.
1121 // The address of the global is just (hi(&g)+lo(&g)).
1122 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1125 if (TM.getRelocationModel() == Reloc::PIC_) {
1126 // With PIC, the first instruction is actually "GR+hi(&G)".
1127 Hi = DAG.getNode(ISD::ADD, PtrVT,
1128 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1131 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1133 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1136 // If the global is weak or external, we have to go through the lazy
1138 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
1141 SDOperand PPCTargetLowering::LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
1142 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1144 // If we're comparing for equality to zero, expose the fact that this is
1145 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1146 // fold the new nodes.
1147 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1148 if (C->isNullValue() && CC == ISD::SETEQ) {
1149 MVT::ValueType VT = Op.getOperand(0).getValueType();
1150 SDOperand Zext = Op.getOperand(0);
1151 if (VT < MVT::i32) {
1153 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1155 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
1156 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1157 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
1158 DAG.getConstant(Log2b, MVT::i32));
1159 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1161 // Leave comparisons against 0 and -1 alone for now, since they're usually
1162 // optimized. FIXME: revisit this when we can custom lower all setcc
1164 if (C->isAllOnesValue() || C->isNullValue())
1168 // If we have an integer seteq/setne, turn it into a compare against zero
1169 // by xor'ing the rhs with the lhs, which is faster than setting a
1170 // condition register, reading it back out, and masking the correct bit. The
1171 // normal approach here uses sub to do this instead of xor. Using xor exposes
1172 // the result to other bit-twiddling opportunities.
1173 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
1174 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1175 MVT::ValueType VT = Op.getValueType();
1176 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
1178 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1183 SDOperand PPCTargetLowering::LowerVAARG(SDOperand Op, SelectionDAG &DAG,
1184 int VarArgsFrameIndex,
1185 int VarArgsStackOffset,
1186 unsigned VarArgsNumGPR,
1187 unsigned VarArgsNumFPR,
1188 const PPCSubtarget &Subtarget) {
1190 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1193 SDOperand PPCTargetLowering::LowerVASTART(SDOperand Op, SelectionDAG &DAG,
1194 int VarArgsFrameIndex,
1195 int VarArgsStackOffset,
1196 unsigned VarArgsNumGPR,
1197 unsigned VarArgsNumFPR,
1198 const PPCSubtarget &Subtarget) {
1200 if (Subtarget.isMachoABI()) {
1201 // vastart just stores the address of the VarArgsFrameIndex slot into the
1202 // memory location argument.
1203 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1204 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1205 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1206 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
1209 // For ELF 32 ABI we follow the layout of the va_list struct.
1210 // We suppose the given va_list is already allocated.
1213 // char gpr; /* index into the array of 8 GPRs
1214 // * stored in the register save area
1215 // * gpr=0 corresponds to r3,
1216 // * gpr=1 to r4, etc.
1218 // char fpr; /* index into the array of 8 FPRs
1219 // * stored in the register save area
1220 // * fpr=0 corresponds to f1,
1221 // * fpr=1 to f2, etc.
1223 // char *overflow_arg_area;
1224 // /* location on stack that holds
1225 // * the next overflow argument
1227 // char *reg_save_area;
1228 // /* where r3:r10 and f1:f8 (if saved)
1234 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1235 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1238 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1240 SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1241 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1243 uint64_t FrameOffset = MVT::getSizeInBits(PtrVT)/8;
1244 SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1246 uint64_t StackOffset = MVT::getSizeInBits(PtrVT)/8 - 1;
1247 SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1249 uint64_t FPROffset = 1;
1250 SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1252 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1254 // Store first byte : number of int regs
1255 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
1256 Op.getOperand(1), SV, 0);
1257 uint64_t nextOffset = FPROffset;
1258 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
1261 // Store second byte : number of float regs
1262 SDOperand secondStore =
1263 DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset);
1264 nextOffset += StackOffset;
1265 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
1267 // Store second word : arguments given on stack
1268 SDOperand thirdStore =
1269 DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset);
1270 nextOffset += FrameOffset;
1271 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
1273 // Store third word : arguments given in registers
1274 return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset);
1278 #include "PPCGenCallingConv.inc"
1280 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1281 /// depending on which subtarget is selected.
1282 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1283 if (Subtarget.isMachoABI()) {
1284 static const unsigned FPR[] = {
1285 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1286 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1292 static const unsigned FPR[] = {
1293 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1300 PPCTargetLowering::LowerFORMAL_ARGUMENTS(SDOperand Op,
1302 int &VarArgsFrameIndex,
1303 int &VarArgsStackOffset,
1304 unsigned &VarArgsNumGPR,
1305 unsigned &VarArgsNumFPR,
1306 const PPCSubtarget &Subtarget) {
1307 // TODO: add description of PPC stack frame format, or at least some docs.
1309 MachineFunction &MF = DAG.getMachineFunction();
1310 MachineFrameInfo *MFI = MF.getFrameInfo();
1311 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1312 SmallVector<SDOperand, 8> ArgValues;
1313 SDOperand Root = Op.getOperand(0);
1315 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1316 bool isPPC64 = PtrVT == MVT::i64;
1317 bool isMachoABI = Subtarget.isMachoABI();
1318 bool isELF32_ABI = Subtarget.isELF32_ABI();
1319 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1321 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1323 static const unsigned GPR_32[] = { // 32-bit registers.
1324 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1325 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1327 static const unsigned GPR_64[] = { // 64-bit registers.
1328 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1329 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1332 static const unsigned *FPR = GetFPR(Subtarget);
1334 static const unsigned VR[] = {
1335 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1336 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1339 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1340 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
1341 const unsigned Num_VR_Regs = array_lengthof( VR);
1343 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1345 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1347 // Add DAG nodes to load the arguments or copy them out of registers. On
1348 // entry to a function on PPC, the arguments start after the linkage area,
1349 // although the first ones are often in registers.
1351 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
1352 // represented with two words (long long or double) must be copied to an
1353 // even GPR_idx value or to an even ArgOffset value.
1355 SmallVector<SDOperand, 8> MemOps;
1357 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
1359 bool needsLoad = false;
1360 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
1361 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
1362 unsigned ArgSize = ObjSize;
1363 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue();
1364 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1365 unsigned isByVal = Flags & ISD::ParamFlags::ByVal;
1366 // See if next argument requires stack alignment in ELF
1367 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) &&
1368 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) &&
1369 (!(Flags & AlignFlag)));
1371 unsigned CurArgOffset = ArgOffset;
1373 // FIXME alignment for ELF may not be right
1374 // FIXME the codegen can be much improved in some cases.
1375 // We do not have to keep everything in memory.
1377 // Double word align in ELF
1378 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1379 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1380 ObjSize = (Flags & ISD::ParamFlags::ByValSize) >>
1381 ISD::ParamFlags::ByValSizeOffs;
1382 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1383 // The value of the object is its address.
1384 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset);
1385 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1386 ArgValues.push_back(FIN);
1387 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1388 // Store whatever pieces of the object are in registers
1389 // to memory. ArgVal will be address of the beginning of
1391 if (GPR_idx != Num_GPR_Regs) {
1392 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1393 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1394 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset);
1395 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1396 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1397 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1398 MemOps.push_back(Store);
1400 if (isMachoABI) ArgOffset += PtrByteSize;
1402 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1410 default: assert(0 && "Unhandled argument type!");
1413 // Double word align in ELF
1414 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1416 if (GPR_idx != Num_GPR_Regs) {
1417 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1418 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1419 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1423 ArgSize = PtrByteSize;
1425 // Stack align in ELF
1426 if (needsLoad && Expand && isELF32_ABI)
1427 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1428 // All int arguments reserve stack space in Macho ABI.
1429 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1433 case MVT::i64: // PPC64
1434 if (GPR_idx != Num_GPR_Regs) {
1435 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1436 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1437 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1439 if (ObjectVT == MVT::i32) {
1440 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1441 // value to MVT::i64 and then truncate to the correct register size.
1442 if (Flags & ISD::ParamFlags::SExt)
1443 ArgVal = DAG.getNode(ISD::AssertSext, MVT::i64, ArgVal,
1444 DAG.getValueType(ObjectVT));
1445 else if (Flags & ISD::ParamFlags::ZExt)
1446 ArgVal = DAG.getNode(ISD::AssertZext, MVT::i64, ArgVal,
1447 DAG.getValueType(ObjectVT));
1449 ArgVal = DAG.getNode(ISD::TRUNCATE, MVT::i32, ArgVal);
1456 // All int arguments reserve stack space in Macho ABI.
1457 if (isMachoABI || needsLoad) ArgOffset += 8;
1462 // Every 4 bytes of argument space consumes one of the GPRs available for
1463 // argument passing.
1464 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
1466 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1469 if (FPR_idx != Num_FPR_Regs) {
1471 if (ObjectVT == MVT::f32)
1472 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass);
1474 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1475 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1476 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1482 // Stack align in ELF
1483 if (needsLoad && Expand && isELF32_ABI)
1484 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1485 // All FP arguments reserve stack space in Macho ABI.
1486 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
1492 // Note that vector arguments in registers don't reserve stack space.
1493 if (VR_idx != Num_VR_Regs) {
1494 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass);
1495 RegInfo.addLiveIn(VR[VR_idx], VReg);
1496 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1499 // This should be simple, but requires getting 16-byte aligned stack
1501 assert(0 && "Loading VR argument not implemented yet!");
1507 // We need to load the argument to a virtual register if we determined above
1508 // that we ran out of physical registers of the appropriate type.
1510 int FI = MFI->CreateFixedObject(ObjSize,
1511 CurArgOffset + (ArgSize - ObjSize));
1512 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1513 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1516 ArgValues.push_back(ArgVal);
1519 // If the function takes variable number of arguments, make a frame index for
1520 // the start of the first vararg value... for expansion of llvm.va_start.
1521 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1526 VarArgsNumGPR = GPR_idx;
1527 VarArgsNumFPR = FPR_idx;
1529 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1531 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 +
1532 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 +
1533 MVT::getSizeInBits(PtrVT)/8);
1535 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1542 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1544 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1546 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1547 // stored to the VarArgsFrameIndex on the stack.
1549 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1550 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1551 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1552 MemOps.push_back(Store);
1553 // Increment the address by four for the next argument to store
1554 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1555 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1559 // If this function is vararg, store any remaining integer argument regs
1560 // to their spots on the stack so that they may be loaded by deferencing the
1561 // result of va_next.
1562 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1565 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1567 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1569 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1570 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1571 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1572 MemOps.push_back(Store);
1573 // Increment the address by four for the next argument to store
1574 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1575 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1578 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1581 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1582 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1583 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1584 MemOps.push_back(Store);
1585 // Increment the address by eight for the next argument to store
1586 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1588 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1591 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1593 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1595 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1596 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
1597 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1598 MemOps.push_back(Store);
1599 // Increment the address by eight for the next argument to store
1600 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1602 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1607 if (!MemOps.empty())
1608 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1610 ArgValues.push_back(Root);
1612 // Return the new list of results.
1613 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1614 Op.Val->value_end());
1615 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1618 /// isCallCompatibleAddress - Return the immediate to use if the specified
1619 /// 32-bit value is representable in the immediate field of a BxA instruction.
1620 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
1621 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1624 int Addr = C->getValue();
1625 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1626 (Addr << 6 >> 6) != Addr)
1627 return 0; // Top 6 bits have to be sext of immediate.
1629 return DAG.getConstant((int)C->getValue() >> 2,
1630 DAG.getTargetLoweringInfo().getPointerTy()).Val;
1633 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
1634 /// by "Src" to address "Dst" of size "Size". Alignment information is
1635 /// specified by the specific parameter attribute. The copy will be passed as
1636 /// a byval function parameter.
1637 /// Sometimes what we are copying is the end of a larger object, the part that
1638 /// does not fit in registers.
1640 CreateCopyOfByValArgument(SDOperand Src, SDOperand Dst, SDOperand Chain,
1641 unsigned Flags, SelectionDAG &DAG, unsigned Size) {
1642 unsigned Align = 1 <<
1643 ((Flags & ISD::ParamFlags::ByValAlign) >> ISD::ParamFlags::ByValAlignOffs);
1644 SDOperand AlignNode = DAG.getConstant(Align, MVT::i32);
1645 SDOperand SizeNode = DAG.getConstant(Size, MVT::i32);
1646 SDOperand AlwaysInline = DAG.getConstant(0, MVT::i32);
1647 return DAG.getMemcpy(Chain, Dst, Src, SizeNode, AlignNode, AlwaysInline);
1650 SDOperand PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG,
1651 const PPCSubtarget &Subtarget) {
1652 SDOperand Chain = Op.getOperand(0);
1653 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1654 SDOperand Callee = Op.getOperand(4);
1655 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1657 bool isMachoABI = Subtarget.isMachoABI();
1658 bool isELF32_ABI = Subtarget.isELF32_ABI();
1660 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1661 bool isPPC64 = PtrVT == MVT::i64;
1662 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1664 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1665 // SelectExpr to use to put the arguments in the appropriate registers.
1666 std::vector<SDOperand> args_to_use;
1668 // Count how many bytes are to be pushed on the stack, including the linkage
1669 // area, and parameter passing area. We start with 24/48 bytes, which is
1670 // prereserved space for [SP][CR][LR][3 x unused].
1671 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1673 // Add up all the space actually used.
1674 for (unsigned i = 0; i != NumOps; ++i) {
1675 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
1676 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
1677 if (Flags & ISD::ParamFlags::ByVal)
1678 ArgSize = (Flags & ISD::ParamFlags::ByValSize) >>
1679 ISD::ParamFlags::ByValSizeOffs;
1680 ArgSize = std::max(ArgSize, PtrByteSize);
1681 NumBytes += ArgSize;
1684 // The prolog code of the callee may store up to 8 GPR argument registers to
1685 // the stack, allowing va_start to index over them in memory if its varargs.
1686 // Because we cannot tell if this is needed on the caller side, we have to
1687 // conservatively assume that it is needed. As such, make sure we have at
1688 // least enough stack space for the caller to store the 8 GPRs.
1689 NumBytes = std::max(NumBytes,
1690 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1692 // Adjust the stack pointer for the new arguments...
1693 // These operations are automatically eliminated by the prolog/epilog pass
1694 Chain = DAG.getCALLSEQ_START(Chain,
1695 DAG.getConstant(NumBytes, PtrVT));
1696 SDOperand CallSeqStart = Chain;
1698 // Set up a copy of the stack pointer for use loading and storing any
1699 // arguments that may not fit in the registers available for argument
1703 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
1705 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
1707 // Figure out which arguments are going to go in registers, and which in
1708 // memory. Also, if this is a vararg function, floating point operations
1709 // must be stored to our stack, and loaded into integer regs as well, if
1710 // any integer regs are available for argument passing.
1711 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1712 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1714 static const unsigned GPR_32[] = { // 32-bit registers.
1715 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1716 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1718 static const unsigned GPR_64[] = { // 64-bit registers.
1719 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1720 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1722 static const unsigned *FPR = GetFPR(Subtarget);
1724 static const unsigned VR[] = {
1725 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1726 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1728 const unsigned NumGPRs = array_lengthof(GPR_32);
1729 const unsigned NumFPRs = isMachoABI ? 13 : 8;
1730 const unsigned NumVRs = array_lengthof( VR);
1732 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1734 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1735 SmallVector<SDOperand, 8> MemOpChains;
1736 for (unsigned i = 0; i != NumOps; ++i) {
1738 SDOperand Arg = Op.getOperand(5+2*i);
1739 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
1740 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1741 // See if next argument requires stack alignment in ELF
1742 unsigned next = 5+2*(i+1)+1;
1743 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) &&
1744 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) &&
1745 (!(Flags & AlignFlag)));
1747 // PtrOff will be used to store the current argument to the stack if a
1748 // register cannot be found for it.
1751 // Stack align in ELF 32
1752 if (isELF32_ABI && Expand)
1753 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
1754 StackPtr.getValueType());
1756 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1758 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1760 // On PPC64, promote integers to 64-bit values.
1761 if (isPPC64 && Arg.getValueType() == MVT::i32) {
1762 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1763 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1766 // FIXME Elf untested, what are alignment rules?
1767 // FIXME memcpy is used way more than necessary. Correctness first.
1768 if (Flags & ISD::ParamFlags::ByVal) {
1769 unsigned Size = (Flags & ISD::ParamFlags::ByValSize) >>
1770 ISD::ParamFlags::ByValSizeOffs;
1771 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
1772 if (Size==1 || Size==2) {
1773 // Very small objects are passed right-justified.
1774 // Everything else is passed left-justified.
1775 MVT::ValueType VT = (Size==1) ? MVT::i8 : MVT::i16;
1776 if (GPR_idx != NumGPRs) {
1777 SDOperand Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, Chain, Arg,
1779 MemOpChains.push_back(Load.getValue(1));
1780 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1782 ArgOffset += PtrByteSize;
1784 SDOperand Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
1785 SDOperand AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const);
1786 SDOperand MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
1787 CallSeqStart.Val->getOperand(0),
1789 // This must go outside the CALLSEQ_START..END.
1790 SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
1791 CallSeqStart.Val->getOperand(1));
1792 DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val);
1793 Chain = CallSeqStart = NewCallSeqStart;
1794 ArgOffset += PtrByteSize;
1798 for (unsigned j=0; j<Size; j+=PtrByteSize) {
1799 SDOperand Const = DAG.getConstant(j, PtrOff.getValueType());
1800 SDOperand AddArg = DAG.getNode(ISD::ADD, PtrVT, Arg, Const);
1801 if (GPR_idx != NumGPRs) {
1802 SDOperand Load = DAG.getLoad(PtrVT, Chain, AddArg, NULL, 0);
1803 MemOpChains.push_back(Load.getValue(1));
1804 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
1806 ArgOffset += PtrByteSize;
1808 SDOperand AddPtr = DAG.getNode(ISD::ADD, PtrVT, PtrOff, Const);
1809 SDOperand MemcpyCall = CreateCopyOfByValArgument(AddArg, AddPtr,
1810 CallSeqStart.Val->getOperand(0),
1811 Flags, DAG, Size - j);
1812 // This must go outside the CALLSEQ_START..END.
1813 SDOperand NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
1814 CallSeqStart.Val->getOperand(1));
1815 DAG.ReplaceAllUsesWith(CallSeqStart.Val, NewCallSeqStart.Val);
1816 Chain = CallSeqStart = NewCallSeqStart;
1817 ArgOffset += ((Size - j + 3)/4)*4;
1824 switch (Arg.getValueType()) {
1825 default: assert(0 && "Unexpected ValueType for argument!");
1828 // Double word align in ELF
1829 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
1830 if (GPR_idx != NumGPRs) {
1831 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
1833 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1836 if (inMem || isMachoABI) {
1837 // Stack align in ELF
1838 if (isELF32_ABI && Expand)
1839 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1841 ArgOffset += PtrByteSize;
1847 // Float varargs need to be promoted to double.
1848 if (Arg.getValueType() == MVT::f32)
1849 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
1852 if (FPR_idx != NumFPRs) {
1853 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1856 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1857 MemOpChains.push_back(Store);
1859 // Float varargs are always shadowed in available integer registers
1860 if (GPR_idx != NumGPRs) {
1861 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1862 MemOpChains.push_back(Load.getValue(1));
1863 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1866 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
1867 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1868 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
1869 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1870 MemOpChains.push_back(Load.getValue(1));
1871 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1875 // If we have any FPRs remaining, we may also have GPRs remaining.
1876 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1879 if (GPR_idx != NumGPRs)
1881 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
1882 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
1887 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1890 if (inMem || isMachoABI) {
1891 // Stack align in ELF
1892 if (isELF32_ABI && Expand)
1893 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1897 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1904 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1905 assert(VR_idx != NumVRs &&
1906 "Don't support passing more than 12 vector args yet!");
1907 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1911 if (!MemOpChains.empty())
1912 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1913 &MemOpChains[0], MemOpChains.size());
1915 // Build a sequence of copy-to-reg nodes chained together with token chain
1916 // and flag operands which copy the outgoing args into the appropriate regs.
1918 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1919 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1921 InFlag = Chain.getValue(1);
1924 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
1925 if (isVarArg && isELF32_ABI) {
1926 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0);
1927 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag);
1928 InFlag = Chain.getValue(1);
1931 std::vector<MVT::ValueType> NodeTys;
1932 NodeTys.push_back(MVT::Other); // Returns a chain
1933 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1935 SmallVector<SDOperand, 8> Ops;
1936 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
1938 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1939 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1940 // node so that legalize doesn't hack it.
1941 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1942 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1943 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1944 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1945 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1946 // If this is an absolute destination address, use the munged value.
1947 Callee = SDOperand(Dest, 0);
1949 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1950 // to do the call, we can't use PPCISD::CALL.
1951 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
1952 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
1953 InFlag = Chain.getValue(1);
1955 // Copy the callee address into R12 on darwin.
1957 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1958 InFlag = Chain.getValue(1);
1962 NodeTys.push_back(MVT::Other);
1963 NodeTys.push_back(MVT::Flag);
1964 Ops.push_back(Chain);
1965 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
1969 // If this is a direct call, pass the chain and the callee.
1971 Ops.push_back(Chain);
1972 Ops.push_back(Callee);
1975 // Add argument registers to the end of the list so that they are known live
1977 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1978 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1979 RegsToPass[i].second.getValueType()));
1982 Ops.push_back(InFlag);
1983 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
1984 InFlag = Chain.getValue(1);
1986 Chain = DAG.getCALLSEQ_END(Chain,
1987 DAG.getConstant(NumBytes, PtrVT),
1988 DAG.getConstant(0, PtrVT),
1990 if (Op.Val->getValueType(0) != MVT::Other)
1991 InFlag = Chain.getValue(1);
1993 SDOperand ResultVals[3];
1994 unsigned NumResults = 0;
1997 // If the call has results, copy the values out of the ret val registers.
1998 switch (Op.Val->getValueType(0)) {
1999 default: assert(0 && "Unexpected ret value!");
2000 case MVT::Other: break;
2002 if (Op.Val->getValueType(1) == MVT::i32) {
2003 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
2004 ResultVals[0] = Chain.getValue(0);
2005 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32,
2006 Chain.getValue(2)).getValue(1);
2007 ResultVals[1] = Chain.getValue(0);
2009 NodeTys.push_back(MVT::i32);
2011 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
2012 ResultVals[0] = Chain.getValue(0);
2015 NodeTys.push_back(MVT::i32);
2018 if (Op.Val->getValueType(1) == MVT::i64) {
2019 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
2020 ResultVals[0] = Chain.getValue(0);
2021 Chain = DAG.getCopyFromReg(Chain, PPC::X4, MVT::i64,
2022 Chain.getValue(2)).getValue(1);
2023 ResultVals[1] = Chain.getValue(0);
2025 NodeTys.push_back(MVT::i64);
2027 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
2028 ResultVals[0] = Chain.getValue(0);
2031 NodeTys.push_back(MVT::i64);
2034 if (Op.Val->getValueType(1) == MVT::f64) {
2035 Chain = DAG.getCopyFromReg(Chain, PPC::F1, MVT::f64, InFlag).getValue(1);
2036 ResultVals[0] = Chain.getValue(0);
2037 Chain = DAG.getCopyFromReg(Chain, PPC::F2, MVT::f64,
2038 Chain.getValue(2)).getValue(1);
2039 ResultVals[1] = Chain.getValue(0);
2041 NodeTys.push_back(MVT::f64);
2042 NodeTys.push_back(MVT::f64);
2045 // else fall through
2047 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
2048 InFlag).getValue(1);
2049 ResultVals[0] = Chain.getValue(0);
2051 NodeTys.push_back(Op.Val->getValueType(0));
2057 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
2058 InFlag).getValue(1);
2059 ResultVals[0] = Chain.getValue(0);
2061 NodeTys.push_back(Op.Val->getValueType(0));
2065 NodeTys.push_back(MVT::Other);
2067 // If the function returns void, just return the chain.
2068 if (NumResults == 0)
2071 // Otherwise, merge everything together with a MERGE_VALUES node.
2072 ResultVals[NumResults++] = Chain;
2073 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
2074 ResultVals, NumResults);
2075 return Res.getValue(Op.ResNo);
2078 SDOperand PPCTargetLowering::LowerRET(SDOperand Op, SelectionDAG &DAG,
2079 TargetMachine &TM) {
2080 SmallVector<CCValAssign, 16> RVLocs;
2081 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
2082 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
2083 CCState CCInfo(CC, isVarArg, TM, RVLocs);
2084 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
2086 // If this is the first return lowered for this function, add the regs to the
2087 // liveout set for the function.
2088 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2089 for (unsigned i = 0; i != RVLocs.size(); ++i)
2090 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2093 SDOperand Chain = Op.getOperand(0);
2096 // Copy the result values into the output registers.
2097 for (unsigned i = 0; i != RVLocs.size(); ++i) {
2098 CCValAssign &VA = RVLocs[i];
2099 assert(VA.isRegLoc() && "Can only return in registers!");
2100 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
2101 Flag = Chain.getValue(1);
2105 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
2107 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
2110 SDOperand PPCTargetLowering::LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
2111 const PPCSubtarget &Subtarget) {
2112 // When we pop the dynamic allocation we need to restore the SP link.
2114 // Get the corect type for pointers.
2115 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2117 // Construct the stack pointer operand.
2118 bool IsPPC64 = Subtarget.isPPC64();
2119 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
2120 SDOperand StackPtr = DAG.getRegister(SP, PtrVT);
2122 // Get the operands for the STACKRESTORE.
2123 SDOperand Chain = Op.getOperand(0);
2124 SDOperand SaveSP = Op.getOperand(1);
2126 // Load the old link SP.
2127 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
2129 // Restore the stack pointer.
2130 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
2132 // Store the old link SP.
2133 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
2136 SDOperand PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDOperand Op,
2138 const PPCSubtarget &Subtarget) {
2139 MachineFunction &MF = DAG.getMachineFunction();
2140 bool IsPPC64 = Subtarget.isPPC64();
2141 bool isMachoABI = Subtarget.isMachoABI();
2143 // Get current frame pointer save index. The users of this index will be
2144 // primarily DYNALLOC instructions.
2145 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2146 int FPSI = FI->getFramePointerSaveIndex();
2148 // If the frame pointer save index hasn't been defined yet.
2150 // Find out what the fix offset of the frame pointer save area.
2151 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
2153 // Allocate the frame index for frame pointer save area.
2154 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
2156 FI->setFramePointerSaveIndex(FPSI);
2160 SDOperand Chain = Op.getOperand(0);
2161 SDOperand Size = Op.getOperand(1);
2163 // Get the corect type for pointers.
2164 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2166 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
2167 DAG.getConstant(0, PtrVT), Size);
2168 // Construct a node for the frame pointer save index.
2169 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT);
2170 // Build a DYNALLOC node.
2171 SDOperand Ops[3] = { Chain, NegSize, FPSIdx };
2172 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
2173 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
2177 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
2179 SDOperand PPCTargetLowering::LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
2180 // Not FP? Not a fsel.
2181 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
2182 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
2185 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2187 // Cannot handle SETEQ/SETNE.
2188 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
2190 MVT::ValueType ResVT = Op.getValueType();
2191 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
2192 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2193 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
2195 // If the RHS of the comparison is a 0.0, we don't need to do the
2196 // subtraction at all.
2197 if (isFloatingPointZero(RHS))
2199 default: break; // SETUO etc aren't handled by fsel.
2203 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2207 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2208 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2209 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
2213 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2217 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2218 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2219 return DAG.getNode(PPCISD::FSEL, ResVT,
2220 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
2225 default: break; // SETUO etc aren't handled by fsel.
2229 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2230 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2231 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2232 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2236 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2237 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2238 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2239 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2243 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2244 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2245 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2246 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2250 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2251 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2252 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2253 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2258 // FIXME: Split this code up when LegalizeDAGTypes lands.
2259 SDOperand PPCTargetLowering::LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
2260 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
2261 SDOperand Src = Op.getOperand(0);
2262 if (Src.getValueType() == MVT::f32)
2263 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
2266 switch (Op.getValueType()) {
2267 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
2269 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
2272 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
2276 // Convert the FP value to an int value through memory.
2277 SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64);
2279 // Emit a store to the stack slot.
2280 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0);
2282 // Result is a load from the stack slot. If loading 4 bytes, make sure to
2284 if (Op.getValueType() == MVT::i32)
2285 FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr,
2286 DAG.getConstant(4, FIPtr.getValueType()));
2287 return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0);
2290 SDOperand PPCTargetLowering::LowerFP_ROUND_INREG(SDOperand Op,
2291 SelectionDAG &DAG) {
2292 assert(Op.getValueType() == MVT::ppcf128);
2293 SDNode *Node = Op.Val;
2294 assert(Node->getOperand(0).getValueType() == MVT::ppcf128);
2295 assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR);
2296 SDOperand Lo = Node->getOperand(0).Val->getOperand(0);
2297 SDOperand Hi = Node->getOperand(0).Val->getOperand(1);
2299 // This sequence changes FPSCR to do round-to-zero, adds the two halves
2300 // of the long double, and puts FPSCR back the way it was. We do not
2301 // actually model FPSCR.
2302 std::vector<MVT::ValueType> NodeTys;
2303 SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg;
2305 NodeTys.push_back(MVT::f64); // Return register
2306 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
2307 Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2308 MFFSreg = Result.getValue(0);
2309 InFlag = Result.getValue(1);
2312 NodeTys.push_back(MVT::Flag); // Returns a flag
2313 Ops[0] = DAG.getConstant(31, MVT::i32);
2315 Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2);
2316 InFlag = Result.getValue(0);
2319 NodeTys.push_back(MVT::Flag); // Returns a flag
2320 Ops[0] = DAG.getConstant(30, MVT::i32);
2322 Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2);
2323 InFlag = Result.getValue(0);
2326 NodeTys.push_back(MVT::f64); // result of add
2327 NodeTys.push_back(MVT::Flag); // Returns a flag
2331 Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3);
2332 FPreg = Result.getValue(0);
2333 InFlag = Result.getValue(1);
2336 NodeTys.push_back(MVT::f64);
2337 Ops[0] = DAG.getConstant(1, MVT::i32);
2341 Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4);
2342 FPreg = Result.getValue(0);
2344 // We know the low half is about to be thrown away, so just use something
2346 return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg);
2349 SDOperand PPCTargetLowering::LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
2350 if (Op.getOperand(0).getValueType() == MVT::i64) {
2351 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
2352 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
2353 if (Op.getValueType() == MVT::f32)
2354 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
2358 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
2359 "Unhandled SINT_TO_FP type in custom expander!");
2360 // Since we only generate this in 64-bit mode, we can take advantage of
2361 // 64-bit registers. In particular, sign extend the input value into the
2362 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
2363 // then lfd it and fcfid it.
2364 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2365 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
2366 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2367 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2369 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
2372 // STD the extended value into the stack slot.
2373 MemOperand MO(PseudoSourceValue::getFixedStack(),
2374 MemOperand::MOStore, FrameIdx, 8, 8);
2375 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
2376 DAG.getEntryNode(), Ext64, FIdx,
2377 DAG.getMemOperand(MO));
2378 // Load the value as a double.
2379 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
2381 // FCFID it and return it.
2382 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
2383 if (Op.getValueType() == MVT::f32)
2384 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
2388 SDOperand PPCTargetLowering::LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
2390 The rounding mode is in bits 30:31 of FPSR, and has the following
2397 FLT_ROUNDS, on the other hand, expects the following:
2404 To perform the conversion, we do:
2405 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
2408 MachineFunction &MF = DAG.getMachineFunction();
2409 MVT::ValueType VT = Op.getValueType();
2410 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2411 std::vector<MVT::ValueType> NodeTys;
2412 SDOperand MFFSreg, InFlag;
2414 // Save FP Control Word to register
2415 NodeTys.push_back(MVT::f64); // return register
2416 NodeTys.push_back(MVT::Flag); // unused in this context
2417 SDOperand Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2419 // Save FP register to stack slot
2420 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
2421 SDOperand StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
2422 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Chain,
2423 StackSlot, NULL, 0);
2425 // Load FP Control Word from low 32 bits of stack slot.
2426 SDOperand Four = DAG.getConstant(4, PtrVT);
2427 SDOperand Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four);
2428 SDOperand CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0);
2430 // Transform as necessary
2432 DAG.getNode(ISD::AND, MVT::i32,
2433 CWD, DAG.getConstant(3, MVT::i32));
2435 DAG.getNode(ISD::SRL, MVT::i32,
2436 DAG.getNode(ISD::AND, MVT::i32,
2437 DAG.getNode(ISD::XOR, MVT::i32,
2438 CWD, DAG.getConstant(3, MVT::i32)),
2439 DAG.getConstant(3, MVT::i32)),
2440 DAG.getConstant(1, MVT::i8));
2443 DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2);
2445 return DAG.getNode((MVT::getSizeInBits(VT) < 16 ?
2446 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
2449 SDOperand PPCTargetLowering::LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2450 MVT::ValueType VT = Op.getValueType();
2451 unsigned BitWidth = MVT::getSizeInBits(VT);
2452 assert(Op.getNumOperands() == 3 &&
2453 VT == Op.getOperand(1).getValueType() &&
2456 // Expand into a bunch of logical ops. Note that these ops
2457 // depend on the PPC behavior for oversized shift amounts.
2458 SDOperand Lo = Op.getOperand(0);
2459 SDOperand Hi = Op.getOperand(1);
2460 SDOperand Amt = Op.getOperand(2);
2461 MVT::ValueType AmtVT = Amt.getValueType();
2463 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
2464 DAG.getConstant(BitWidth, AmtVT), Amt);
2465 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, VT, Hi, Amt);
2466 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, VT, Lo, Tmp1);
2467 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
2468 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
2469 DAG.getConstant(-BitWidth, AmtVT));
2470 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, VT, Lo, Tmp5);
2471 SDOperand OutHi = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
2472 SDOperand OutLo = DAG.getNode(PPCISD::SHL, VT, Lo, Amt);
2473 SDOperand OutOps[] = { OutLo, OutHi };
2474 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT),
2478 SDOperand PPCTargetLowering::LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2479 MVT::ValueType VT = Op.getValueType();
2480 unsigned BitWidth = MVT::getSizeInBits(VT);
2481 assert(Op.getNumOperands() == 3 &&
2482 VT == Op.getOperand(1).getValueType() &&
2485 // Expand into a bunch of logical ops. Note that these ops
2486 // depend on the PPC behavior for oversized shift amounts.
2487 SDOperand Lo = Op.getOperand(0);
2488 SDOperand Hi = Op.getOperand(1);
2489 SDOperand Amt = Op.getOperand(2);
2490 MVT::ValueType AmtVT = Amt.getValueType();
2492 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
2493 DAG.getConstant(BitWidth, AmtVT), Amt);
2494 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
2495 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
2496 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
2497 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
2498 DAG.getConstant(-BitWidth, AmtVT));
2499 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, VT, Hi, Tmp5);
2500 SDOperand OutLo = DAG.getNode(ISD::OR, VT, Tmp4, Tmp6);
2501 SDOperand OutHi = DAG.getNode(PPCISD::SRL, VT, Hi, Amt);
2502 SDOperand OutOps[] = { OutLo, OutHi };
2503 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT),
2507 SDOperand PPCTargetLowering::LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
2508 MVT::ValueType VT = Op.getValueType();
2509 unsigned BitWidth = MVT::getSizeInBits(VT);
2510 assert(Op.getNumOperands() == 3 &&
2511 VT == Op.getOperand(1).getValueType() &&
2514 // Expand into a bunch of logical ops, followed by a select_cc.
2515 SDOperand Lo = Op.getOperand(0);
2516 SDOperand Hi = Op.getOperand(1);
2517 SDOperand Amt = Op.getOperand(2);
2518 MVT::ValueType AmtVT = Amt.getValueType();
2520 SDOperand Tmp1 = DAG.getNode(ISD::SUB, AmtVT,
2521 DAG.getConstant(BitWidth, AmtVT), Amt);
2522 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, VT, Lo, Amt);
2523 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, VT, Hi, Tmp1);
2524 SDOperand Tmp4 = DAG.getNode(ISD::OR , VT, Tmp2, Tmp3);
2525 SDOperand Tmp5 = DAG.getNode(ISD::ADD, AmtVT, Amt,
2526 DAG.getConstant(-BitWidth, AmtVT));
2527 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, VT, Hi, Tmp5);
2528 SDOperand OutHi = DAG.getNode(PPCISD::SRA, VT, Hi, Amt);
2529 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, AmtVT),
2530 Tmp4, Tmp6, ISD::SETLE);
2531 SDOperand OutOps[] = { OutLo, OutHi };
2532 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(VT, VT),
2536 //===----------------------------------------------------------------------===//
2537 // Vector related lowering.
2540 // If this is a vector of constants or undefs, get the bits. A bit in
2541 // UndefBits is set if the corresponding element of the vector is an
2542 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2543 // zero. Return true if this is not an array of constants, false if it is.
2545 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
2546 uint64_t UndefBits[2]) {
2547 // Start with zero'd results.
2548 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
2550 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
2551 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2552 SDOperand OpVal = BV->getOperand(i);
2554 unsigned PartNo = i >= e/2; // In the upper 128 bits?
2555 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
2557 uint64_t EltBits = 0;
2558 if (OpVal.getOpcode() == ISD::UNDEF) {
2559 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
2560 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
2562 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2563 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
2564 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2565 assert(CN->getValueType(0) == MVT::f32 &&
2566 "Only one legal FP vector type!");
2567 EltBits = FloatToBits(CN->getValueAPF().convertToFloat());
2569 // Nonconstant element.
2573 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
2576 //printf("%llx %llx %llx %llx\n",
2577 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
2581 // If this is a splat (repetition) of a value across the whole vector, return
2582 // the smallest size that splats it. For example, "0x01010101010101..." is a
2583 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2584 // SplatSize = 1 byte.
2585 static bool isConstantSplat(const uint64_t Bits128[2],
2586 const uint64_t Undef128[2],
2587 unsigned &SplatBits, unsigned &SplatUndef,
2588 unsigned &SplatSize) {
2590 // Don't let undefs prevent splats from matching. See if the top 64-bits are
2591 // the same as the lower 64-bits, ignoring undefs.
2592 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
2593 return false; // Can't be a splat if two pieces don't match.
2595 uint64_t Bits64 = Bits128[0] | Bits128[1];
2596 uint64_t Undef64 = Undef128[0] & Undef128[1];
2598 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
2600 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
2601 return false; // Can't be a splat if two pieces don't match.
2603 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
2604 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
2606 // If the top 16-bits are different than the lower 16-bits, ignoring
2607 // undefs, we have an i32 splat.
2608 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
2610 SplatUndef = Undef32;
2615 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
2616 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
2618 // If the top 8-bits are different than the lower 8-bits, ignoring
2619 // undefs, we have an i16 splat.
2620 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
2622 SplatUndef = Undef16;
2627 // Otherwise, we have an 8-bit splat.
2628 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
2629 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
2634 /// BuildSplatI - Build a canonical splati of Val with an element size of
2635 /// SplatSize. Cast the result to VT.
2636 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
2637 SelectionDAG &DAG) {
2638 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
2640 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
2641 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
2644 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
2646 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
2650 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
2652 // Build a canonical splat for this value.
2653 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT));
2654 SmallVector<SDOperand, 8> Ops;
2655 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
2656 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
2657 &Ops[0], Ops.size());
2658 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
2661 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
2662 /// specified intrinsic ID.
2663 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
2665 MVT::ValueType DestVT = MVT::Other) {
2666 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
2667 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2668 DAG.getConstant(IID, MVT::i32), LHS, RHS);
2671 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
2672 /// specified intrinsic ID.
2673 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
2674 SDOperand Op2, SelectionDAG &DAG,
2675 MVT::ValueType DestVT = MVT::Other) {
2676 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
2677 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2678 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
2682 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
2683 /// amount. The result has the specified value type.
2684 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
2685 MVT::ValueType VT, SelectionDAG &DAG) {
2686 // Force LHS/RHS to be the right type.
2687 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
2688 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
2691 for (unsigned i = 0; i != 16; ++i)
2692 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
2693 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
2694 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
2695 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
2698 // If this is a case we can't handle, return null and let the default
2699 // expansion code take care of it. If we CAN select this case, and if it
2700 // selects to a single instruction, return Op. Otherwise, if we can codegen
2701 // this case more efficiently than a constant pool load, lower it to the
2702 // sequence of ops that should be used.
2703 SDOperand PPCTargetLowering::LowerBUILD_VECTOR(SDOperand Op,
2704 SelectionDAG &DAG) {
2705 // If this is a vector of constants or undefs, get the bits. A bit in
2706 // UndefBits is set if the corresponding element of the vector is an
2707 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2709 uint64_t VectorBits[2];
2710 uint64_t UndefBits[2];
2711 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
2712 return SDOperand(); // Not a constant vector.
2714 // If this is a splat (repetition) of a value across the whole vector, return
2715 // the smallest size that splats it. For example, "0x01010101010101..." is a
2716 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2717 // SplatSize = 1 byte.
2718 unsigned SplatBits, SplatUndef, SplatSize;
2719 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
2720 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
2722 // First, handle single instruction cases.
2725 if (SplatBits == 0) {
2726 // Canonicalize all zero vectors to be v4i32.
2727 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
2728 SDOperand Z = DAG.getConstant(0, MVT::i32);
2729 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
2730 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
2735 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
2736 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
2737 if (SextVal >= -16 && SextVal <= 15)
2738 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
2741 // Two instruction sequences.
2743 // If this value is in the range [-32,30] and is even, use:
2744 // tmp = VSPLTI[bhw], result = add tmp, tmp
2745 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
2746 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
2747 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
2750 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
2751 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
2753 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
2754 // Make -1 and vspltisw -1:
2755 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
2757 // Make the VSLW intrinsic, computing 0x8000_0000.
2758 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
2761 // xor by OnesV to invert it.
2762 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
2763 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2766 // Check to see if this is a wide variety of vsplti*, binop self cases.
2767 unsigned SplatBitSize = SplatSize*8;
2768 static const signed char SplatCsts[] = {
2769 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
2770 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
2773 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
2774 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
2775 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
2776 int i = SplatCsts[idx];
2778 // Figure out what shift amount will be used by altivec if shifted by i in
2780 unsigned TypeShiftAmt = i & (SplatBitSize-1);
2782 // vsplti + shl self.
2783 if (SextVal == (i << (int)TypeShiftAmt)) {
2784 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2785 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2786 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
2787 Intrinsic::ppc_altivec_vslw
2789 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2790 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2793 // vsplti + srl self.
2794 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2795 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2796 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2797 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
2798 Intrinsic::ppc_altivec_vsrw
2800 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2801 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2804 // vsplti + sra self.
2805 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2806 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2807 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2808 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
2809 Intrinsic::ppc_altivec_vsraw
2811 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2812 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2815 // vsplti + rol self.
2816 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
2817 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
2818 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2819 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2820 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
2821 Intrinsic::ppc_altivec_vrlw
2823 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2824 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2827 // t = vsplti c, result = vsldoi t, t, 1
2828 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
2829 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2830 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
2832 // t = vsplti c, result = vsldoi t, t, 2
2833 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
2834 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2835 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
2837 // t = vsplti c, result = vsldoi t, t, 3
2838 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
2839 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2840 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
2844 // Three instruction sequences.
2846 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
2847 if (SextVal >= 0 && SextVal <= 31) {
2848 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
2849 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2850 LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS);
2851 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2853 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
2854 if (SextVal >= -31 && SextVal <= 0) {
2855 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
2856 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2857 LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
2858 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2865 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2866 /// the specified operations to build the shuffle.
2867 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
2868 SDOperand RHS, SelectionDAG &DAG) {
2869 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2870 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2871 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2874 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2886 if (OpNum == OP_COPY) {
2887 if (LHSID == (1*9+2)*9+3) return LHS;
2888 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2892 SDOperand OpLHS, OpRHS;
2893 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
2894 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
2896 unsigned ShufIdxs[16];
2898 default: assert(0 && "Unknown i32 permute!");
2900 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
2901 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
2902 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
2903 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
2906 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
2907 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
2908 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
2909 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
2912 for (unsigned i = 0; i != 16; ++i)
2913 ShufIdxs[i] = (i&3)+0;
2916 for (unsigned i = 0; i != 16; ++i)
2917 ShufIdxs[i] = (i&3)+4;
2920 for (unsigned i = 0; i != 16; ++i)
2921 ShufIdxs[i] = (i&3)+8;
2924 for (unsigned i = 0; i != 16; ++i)
2925 ShufIdxs[i] = (i&3)+12;
2928 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
2930 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
2932 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
2935 for (unsigned i = 0; i != 16; ++i)
2936 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
2938 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
2939 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2942 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
2943 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
2944 /// return the code it can be lowered into. Worst case, it can always be
2945 /// lowered into a vperm.
2946 SDOperand PPCTargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op,
2947 SelectionDAG &DAG) {
2948 SDOperand V1 = Op.getOperand(0);
2949 SDOperand V2 = Op.getOperand(1);
2950 SDOperand PermMask = Op.getOperand(2);
2952 // Cases that are handled by instructions that take permute immediates
2953 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
2954 // selected by the instruction selector.
2955 if (V2.getOpcode() == ISD::UNDEF) {
2956 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
2957 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
2958 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
2959 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
2960 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
2961 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
2962 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
2963 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
2964 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
2965 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
2966 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
2967 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
2972 // Altivec has a variety of "shuffle immediates" that take two vector inputs
2973 // and produce a fixed permutation. If any of these match, do not lower to
2975 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
2976 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
2977 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
2978 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
2979 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
2980 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
2981 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
2982 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
2983 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
2986 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
2987 // perfect shuffle table to emit an optimal matching sequence.
2988 unsigned PFIndexes[4];
2989 bool isFourElementShuffle = true;
2990 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
2991 unsigned EltNo = 8; // Start out undef.
2992 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
2993 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
2994 continue; // Undef, ignore it.
2996 unsigned ByteSource =
2997 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
2998 if ((ByteSource & 3) != j) {
2999 isFourElementShuffle = false;
3004 EltNo = ByteSource/4;
3005 } else if (EltNo != ByteSource/4) {
3006 isFourElementShuffle = false;
3010 PFIndexes[i] = EltNo;
3013 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
3014 // perfect shuffle vector to determine if it is cost effective to do this as
3015 // discrete instructions, or whether we should use a vperm.
3016 if (isFourElementShuffle) {
3017 // Compute the index in the perfect shuffle table.
3018 unsigned PFTableIndex =
3019 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
3021 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
3022 unsigned Cost = (PFEntry >> 30);
3024 // Determining when to avoid vperm is tricky. Many things affect the cost
3025 // of vperm, particularly how many times the perm mask needs to be computed.
3026 // For example, if the perm mask can be hoisted out of a loop or is already
3027 // used (perhaps because there are multiple permutes with the same shuffle
3028 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
3029 // the loop requires an extra register.
3031 // As a compromise, we only emit discrete instructions if the shuffle can be
3032 // generated in 3 or fewer operations. When we have loop information
3033 // available, if this block is within a loop, we should avoid using vperm
3034 // for 3-operation perms and use a constant pool load instead.
3036 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
3039 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
3040 // vector that will get spilled to the constant pool.
3041 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
3043 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
3044 // that it is in input element units, not in bytes. Convert now.
3045 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType());
3046 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
3048 SmallVector<SDOperand, 16> ResultMask;
3049 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
3051 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
3054 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
3056 for (unsigned j = 0; j != BytesPerElement; ++j)
3057 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
3061 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
3062 &ResultMask[0], ResultMask.size());
3063 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
3066 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
3067 /// altivec comparison. If it is, return true and fill in Opc/isDot with
3068 /// information about the intrinsic.
3069 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
3071 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
3074 switch (IntrinsicID) {
3075 default: return false;
3076 // Comparison predicates.
3077 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
3078 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
3079 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
3080 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
3081 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
3082 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
3083 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
3084 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
3085 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
3086 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
3087 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
3088 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
3089 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
3091 // Normal Comparisons.
3092 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
3093 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
3094 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
3095 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
3096 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
3097 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
3098 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
3099 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
3100 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
3101 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
3102 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
3103 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
3104 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
3109 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
3110 /// lower, do it, otherwise return null.
3111 SDOperand PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDOperand Op,
3112 SelectionDAG &DAG) {
3113 // If this is a lowered altivec predicate compare, CompareOpc is set to the
3114 // opcode number of the comparison.
3117 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
3118 return SDOperand(); // Don't custom lower most intrinsics.
3120 // If this is a non-dot comparison, make the VCMP node and we are done.
3122 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
3123 Op.getOperand(1), Op.getOperand(2),
3124 DAG.getConstant(CompareOpc, MVT::i32));
3125 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
3128 // Create the PPCISD altivec 'dot' comparison node.
3130 Op.getOperand(2), // LHS
3131 Op.getOperand(3), // RHS
3132 DAG.getConstant(CompareOpc, MVT::i32)
3134 std::vector<MVT::ValueType> VTs;
3135 VTs.push_back(Op.getOperand(2).getValueType());
3136 VTs.push_back(MVT::Flag);
3137 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
3139 // Now that we have the comparison, emit a copy from the CR to a GPR.
3140 // This is flagged to the above dot comparison.
3141 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
3142 DAG.getRegister(PPC::CR6, MVT::i32),
3143 CompNode.getValue(1));
3145 // Unpack the result based on how the target uses it.
3146 unsigned BitNo; // Bit # of CR6.
3147 bool InvertBit; // Invert result?
3148 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
3149 default: // Can't happen, don't crash on invalid number though.
3150 case 0: // Return the value of the EQ bit of CR6.
3151 BitNo = 0; InvertBit = false;
3153 case 1: // Return the inverted value of the EQ bit of CR6.
3154 BitNo = 0; InvertBit = true;
3156 case 2: // Return the value of the LT bit of CR6.
3157 BitNo = 2; InvertBit = false;
3159 case 3: // Return the inverted value of the LT bit of CR6.
3160 BitNo = 2; InvertBit = true;
3164 // Shift the bit into the low position.
3165 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
3166 DAG.getConstant(8-(3-BitNo), MVT::i32));
3168 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
3169 DAG.getConstant(1, MVT::i32));
3171 // If we are supposed to, toggle the bit.
3173 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
3174 DAG.getConstant(1, MVT::i32));
3178 SDOperand PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDOperand Op,
3179 SelectionDAG &DAG) {
3180 // Create a stack slot that is 16-byte aligned.
3181 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
3182 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
3183 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3184 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3186 // Store the input value into Value#0 of the stack slot.
3187 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
3188 Op.getOperand(0), FIdx, NULL, 0);
3190 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
3193 SDOperand PPCTargetLowering::LowerMUL(SDOperand Op, SelectionDAG &DAG) {
3194 if (Op.getValueType() == MVT::v4i32) {
3195 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3197 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
3198 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
3200 SDOperand RHSSwap = // = vrlw RHS, 16
3201 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
3203 // Shrinkify inputs to v8i16.
3204 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
3205 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
3206 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
3208 // Low parts multiplied together, generating 32-bit results (we ignore the
3210 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
3211 LHS, RHS, DAG, MVT::v4i32);
3213 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
3214 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
3215 // Shift the high parts up 16 bits.
3216 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
3217 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
3218 } else if (Op.getValueType() == MVT::v8i16) {
3219 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3221 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
3223 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
3224 LHS, RHS, Zero, DAG);
3225 } else if (Op.getValueType() == MVT::v16i8) {
3226 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3228 // Multiply the even 8-bit parts, producing 16-bit sums.
3229 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
3230 LHS, RHS, DAG, MVT::v8i16);
3231 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
3233 // Multiply the odd 8-bit parts, producing 16-bit sums.
3234 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
3235 LHS, RHS, DAG, MVT::v8i16);
3236 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
3238 // Merge the results together.
3240 for (unsigned i = 0; i != 8; ++i) {
3241 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
3242 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
3244 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
3245 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
3247 assert(0 && "Unknown mul to lower!");
3252 /// LowerOperation - Provide custom lowering hooks for some operations.
3254 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
3255 switch (Op.getOpcode()) {
3256 default: assert(0 && "Wasn't expecting to be able to lower this!");
3257 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3258 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3259 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3260 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3261 case ISD::SETCC: return LowerSETCC(Op, DAG);
3263 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3264 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3267 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3268 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3270 case ISD::FORMAL_ARGUMENTS:
3271 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
3272 VarArgsStackOffset, VarArgsNumGPR,
3273 VarArgsNumFPR, PPCSubTarget);
3275 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget);
3276 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
3277 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
3278 case ISD::DYNAMIC_STACKALLOC:
3279 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
3281 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3282 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
3283 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
3284 case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG);
3285 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3287 // Lower 64-bit shifts.
3288 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
3289 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
3290 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
3292 // Vector-related lowering.
3293 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3294 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3295 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3296 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
3297 case ISD::MUL: return LowerMUL(Op, DAG);
3299 // Frame & Return address.
3300 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3301 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3306 SDNode *PPCTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
3307 switch (N->getOpcode()) {
3308 default: assert(0 && "Wasn't expecting to be able to lower this!");
3309 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(SDOperand(N, 0), DAG).Val;
3314 //===----------------------------------------------------------------------===//
3315 // Other Lowering Code
3316 //===----------------------------------------------------------------------===//
3319 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3320 MachineBasicBlock *BB) {
3321 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3322 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
3323 MI->getOpcode() == PPC::SELECT_CC_I8 ||
3324 MI->getOpcode() == PPC::SELECT_CC_F4 ||
3325 MI->getOpcode() == PPC::SELECT_CC_F8 ||
3326 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
3327 "Unexpected instr type to insert");
3329 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
3330 // control-flow pattern. The incoming instruction knows the destination vreg
3331 // to set, the condition code register to branch on, the true/false values to
3332 // select between, and a branch opcode to use.
3333 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3334 ilist<MachineBasicBlock>::iterator It = BB;
3340 // cmpTY ccX, r1, r2
3342 // fallthrough --> copy0MBB
3343 MachineBasicBlock *thisMBB = BB;
3344 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
3345 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
3346 unsigned SelectPred = MI->getOperand(4).getImm();
3347 BuildMI(BB, TII->get(PPC::BCC))
3348 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
3349 MachineFunction *F = BB->getParent();
3350 F->getBasicBlockList().insert(It, copy0MBB);
3351 F->getBasicBlockList().insert(It, sinkMBB);
3352 // Update machine-CFG edges by first adding all successors of the current
3353 // block to the new block which will contain the Phi node for the select.
3354 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
3355 e = BB->succ_end(); i != e; ++i)
3356 sinkMBB->addSuccessor(*i);
3357 // Next, remove all successors of the current block, and add the true
3358 // and fallthrough blocks as its successors.
3359 while(!BB->succ_empty())
3360 BB->removeSuccessor(BB->succ_begin());
3361 BB->addSuccessor(copy0MBB);
3362 BB->addSuccessor(sinkMBB);
3365 // %FalseValue = ...
3366 // # fallthrough to sinkMBB
3369 // Update machine-CFG edges
3370 BB->addSuccessor(sinkMBB);
3373 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3376 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
3377 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
3378 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3380 delete MI; // The pseudo instruction is gone now.
3384 //===----------------------------------------------------------------------===//
3385 // Target Optimization Hooks
3386 //===----------------------------------------------------------------------===//
3388 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
3389 DAGCombinerInfo &DCI) const {
3390 TargetMachine &TM = getTargetMachine();
3391 SelectionDAG &DAG = DCI.DAG;
3392 switch (N->getOpcode()) {
3395 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3396 if (C->getValue() == 0) // 0 << V -> 0.
3397 return N->getOperand(0);
3401 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3402 if (C->getValue() == 0) // 0 >>u V -> 0.
3403 return N->getOperand(0);
3407 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3408 if (C->getValue() == 0 || // 0 >>s V -> 0.
3409 C->isAllOnesValue()) // -1 >>s V -> -1.
3410 return N->getOperand(0);
3414 case ISD::SINT_TO_FP:
3415 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
3416 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
3417 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
3418 // We allow the src/dst to be either f32/f64, but the intermediate
3419 // type must be i64.
3420 if (N->getOperand(0).getValueType() == MVT::i64 &&
3421 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
3422 SDOperand Val = N->getOperand(0).getOperand(0);
3423 if (Val.getValueType() == MVT::f32) {
3424 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3425 DCI.AddToWorklist(Val.Val);
3428 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
3429 DCI.AddToWorklist(Val.Val);
3430 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
3431 DCI.AddToWorklist(Val.Val);
3432 if (N->getValueType(0) == MVT::f32) {
3433 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val,
3434 DAG.getIntPtrConstant(0));
3435 DCI.AddToWorklist(Val.Val);
3438 } else if (N->getOperand(0).getValueType() == MVT::i32) {
3439 // If the intermediate type is i32, we can avoid the load/store here
3446 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
3447 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
3448 !cast<StoreSDNode>(N)->isTruncatingStore() &&
3449 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
3450 N->getOperand(1).getValueType() == MVT::i32 &&
3451 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
3452 SDOperand Val = N->getOperand(1).getOperand(0);
3453 if (Val.getValueType() == MVT::f32) {
3454 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3455 DCI.AddToWorklist(Val.Val);
3457 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
3458 DCI.AddToWorklist(Val.Val);
3460 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
3461 N->getOperand(2), N->getOperand(3));
3462 DCI.AddToWorklist(Val.Val);
3466 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
3467 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
3468 N->getOperand(1).Val->hasOneUse() &&
3469 (N->getOperand(1).getValueType() == MVT::i32 ||
3470 N->getOperand(1).getValueType() == MVT::i16)) {
3471 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
3472 // Do an any-extend to 32-bits if this is a half-word input.
3473 if (BSwapOp.getValueType() == MVT::i16)
3474 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
3476 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
3477 N->getOperand(2), N->getOperand(3),
3478 DAG.getValueType(N->getOperand(1).getValueType()));
3482 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
3483 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
3484 N->getOperand(0).hasOneUse() &&
3485 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
3486 SDOperand Load = N->getOperand(0);
3487 LoadSDNode *LD = cast<LoadSDNode>(Load);
3488 // Create the byte-swapping load.
3489 std::vector<MVT::ValueType> VTs;
3490 VTs.push_back(MVT::i32);
3491 VTs.push_back(MVT::Other);
3492 SDOperand MO = DAG.getMemOperand(LD->getMemOperand());
3494 LD->getChain(), // Chain
3495 LD->getBasePtr(), // Ptr
3497 DAG.getValueType(N->getValueType(0)) // VT
3499 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
3501 // If this is an i16 load, insert the truncate.
3502 SDOperand ResVal = BSLoad;
3503 if (N->getValueType(0) == MVT::i16)
3504 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
3506 // First, combine the bswap away. This makes the value produced by the
3508 DCI.CombineTo(N, ResVal);
3510 // Next, combine the load away, we give it a bogus result value but a real
3511 // chain result. The result value is dead because the bswap is dead.
3512 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
3514 // Return N so it doesn't get rechecked!
3515 return SDOperand(N, 0);
3519 case PPCISD::VCMP: {
3520 // If a VCMPo node already exists with exactly the same operands as this
3521 // node, use its result instead of this node (VCMPo computes both a CR6 and
3522 // a normal output).
3524 if (!N->getOperand(0).hasOneUse() &&
3525 !N->getOperand(1).hasOneUse() &&
3526 !N->getOperand(2).hasOneUse()) {
3528 // Scan all of the users of the LHS, looking for VCMPo's that match.
3529 SDNode *VCMPoNode = 0;
3531 SDNode *LHSN = N->getOperand(0).Val;
3532 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
3534 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
3535 (*UI)->getOperand(1) == N->getOperand(1) &&
3536 (*UI)->getOperand(2) == N->getOperand(2) &&
3537 (*UI)->getOperand(0) == N->getOperand(0)) {
3542 // If there is no VCMPo node, or if the flag value has a single use, don't
3544 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
3547 // Look at the (necessarily single) use of the flag value. If it has a
3548 // chain, this transformation is more complex. Note that multiple things
3549 // could use the value result, which we should ignore.
3550 SDNode *FlagUser = 0;
3551 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
3552 FlagUser == 0; ++UI) {
3553 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
3555 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
3556 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
3563 // If the user is a MFCR instruction, we know this is safe. Otherwise we
3564 // give up for right now.
3565 if (FlagUser->getOpcode() == PPCISD::MFCR)
3566 return SDOperand(VCMPoNode, 0);
3571 // If this is a branch on an altivec predicate comparison, lower this so
3572 // that we don't have to do a MFCR: instead, branch directly on CR6. This
3573 // lowering is done pre-legalize, because the legalizer lowers the predicate
3574 // compare down to code that is difficult to reassemble.
3575 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
3576 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
3580 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
3581 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
3582 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
3583 assert(isDot && "Can't compare against a vector result!");
3585 // If this is a comparison against something other than 0/1, then we know
3586 // that the condition is never/always true.
3587 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
3588 if (Val != 0 && Val != 1) {
3589 if (CC == ISD::SETEQ) // Cond never true, remove branch.
3590 return N->getOperand(0);
3591 // Always !=, turn it into an unconditional branch.
3592 return DAG.getNode(ISD::BR, MVT::Other,
3593 N->getOperand(0), N->getOperand(4));
3596 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
3598 // Create the PPCISD altivec 'dot' comparison node.
3599 std::vector<MVT::ValueType> VTs;
3601 LHS.getOperand(2), // LHS of compare
3602 LHS.getOperand(3), // RHS of compare
3603 DAG.getConstant(CompareOpc, MVT::i32)
3605 VTs.push_back(LHS.getOperand(2).getValueType());
3606 VTs.push_back(MVT::Flag);
3607 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
3609 // Unpack the result based on how the target uses it.
3610 PPC::Predicate CompOpc;
3611 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
3612 default: // Can't happen, don't crash on invalid number though.
3613 case 0: // Branch on the value of the EQ bit of CR6.
3614 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
3616 case 1: // Branch on the inverted value of the EQ bit of CR6.
3617 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
3619 case 2: // Branch on the value of the LT bit of CR6.
3620 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
3622 case 3: // Branch on the inverted value of the LT bit of CR6.
3623 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
3627 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
3628 DAG.getConstant(CompOpc, MVT::i32),
3629 DAG.getRegister(PPC::CR6, MVT::i32),
3630 N->getOperand(4), CompNode.getValue(1));
3639 //===----------------------------------------------------------------------===//
3640 // Inline Assembly Support
3641 //===----------------------------------------------------------------------===//
3643 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
3647 const SelectionDAG &DAG,
3648 unsigned Depth) const {
3649 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3650 switch (Op.getOpcode()) {
3652 case PPCISD::LBRX: {
3653 // lhbrx is known to have the top bits cleared out.
3654 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
3655 KnownZero = 0xFFFF0000;
3658 case ISD::INTRINSIC_WO_CHAIN: {
3659 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
3661 case Intrinsic::ppc_altivec_vcmpbfp_p:
3662 case Intrinsic::ppc_altivec_vcmpeqfp_p:
3663 case Intrinsic::ppc_altivec_vcmpequb_p:
3664 case Intrinsic::ppc_altivec_vcmpequh_p:
3665 case Intrinsic::ppc_altivec_vcmpequw_p:
3666 case Intrinsic::ppc_altivec_vcmpgefp_p:
3667 case Intrinsic::ppc_altivec_vcmpgtfp_p:
3668 case Intrinsic::ppc_altivec_vcmpgtsb_p:
3669 case Intrinsic::ppc_altivec_vcmpgtsh_p:
3670 case Intrinsic::ppc_altivec_vcmpgtsw_p:
3671 case Intrinsic::ppc_altivec_vcmpgtub_p:
3672 case Intrinsic::ppc_altivec_vcmpgtuh_p:
3673 case Intrinsic::ppc_altivec_vcmpgtuw_p:
3674 KnownZero = ~1U; // All bits but the low one are known to be zero.
3682 /// getConstraintType - Given a constraint, return the type of
3683 /// constraint it is for this target.
3684 PPCTargetLowering::ConstraintType
3685 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
3686 if (Constraint.size() == 1) {
3687 switch (Constraint[0]) {
3694 return C_RegisterClass;
3697 return TargetLowering::getConstraintType(Constraint);
3700 std::pair<unsigned, const TargetRegisterClass*>
3701 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3702 MVT::ValueType VT) const {
3703 if (Constraint.size() == 1) {
3704 // GCC RS6000 Constraint Letters
3705 switch (Constraint[0]) {
3708 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
3709 return std::make_pair(0U, PPC::G8RCRegisterClass);
3710 return std::make_pair(0U, PPC::GPRCRegisterClass);
3713 return std::make_pair(0U, PPC::F4RCRegisterClass);
3714 else if (VT == MVT::f64)
3715 return std::make_pair(0U, PPC::F8RCRegisterClass);
3718 return std::make_pair(0U, PPC::VRRCRegisterClass);
3720 return std::make_pair(0U, PPC::CRRCRegisterClass);
3724 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3728 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3729 /// vector. If it is invalid, don't add anything to Ops.
3730 void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter,
3731 std::vector<SDOperand>&Ops,
3732 SelectionDAG &DAG) {
3733 SDOperand Result(0,0);
3744 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
3745 if (!CST) return; // Must be an immediate to match.
3746 unsigned Value = CST->getValue();
3748 default: assert(0 && "Unknown constraint letter!");
3749 case 'I': // "I" is a signed 16-bit constant.
3750 if ((short)Value == (int)Value)
3751 Result = DAG.getTargetConstant(Value, Op.getValueType());
3753 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
3754 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
3755 if ((short)Value == 0)
3756 Result = DAG.getTargetConstant(Value, Op.getValueType());
3758 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
3759 if ((Value >> 16) == 0)
3760 Result = DAG.getTargetConstant(Value, Op.getValueType());
3762 case 'M': // "M" is a constant that is greater than 31.
3764 Result = DAG.getTargetConstant(Value, Op.getValueType());
3766 case 'N': // "N" is a positive constant that is an exact power of two.
3767 if ((int)Value > 0 && isPowerOf2_32(Value))
3768 Result = DAG.getTargetConstant(Value, Op.getValueType());
3770 case 'O': // "O" is the constant zero.
3772 Result = DAG.getTargetConstant(Value, Op.getValueType());
3774 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
3775 if ((short)-Value == (int)-Value)
3776 Result = DAG.getTargetConstant(Value, Op.getValueType());
3784 Ops.push_back(Result);
3788 // Handle standard constraint letters.
3789 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
3792 // isLegalAddressingMode - Return true if the addressing mode represented
3793 // by AM is legal for this target, for a load/store of the specified type.
3794 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3795 const Type *Ty) const {
3796 // FIXME: PPC does not allow r+i addressing modes for vectors!
3798 // PPC allows a sign-extended 16-bit immediate field.
3799 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3802 // No global is ever allowed as a base.
3806 // PPC only support r+r,
3808 case 0: // "r+i" or just "i", depending on HasBaseReg.
3811 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3813 // Otherwise we have r+r or r+i.
3816 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3818 // Allow 2*r as r+r.
3821 // No other scales are supported.
3828 /// isLegalAddressImmediate - Return true if the integer value can be used
3829 /// as the offset of the target addressing mode for load / store of the
3831 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
3832 // PPC allows a sign-extended 16-bit immediate field.
3833 return (V > -(1 << 16) && V < (1 << 16)-1);
3836 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
3840 SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
3841 // Depths > 0 not supported yet!
3842 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3845 MachineFunction &MF = DAG.getMachineFunction();
3846 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3847 int RAIdx = FuncInfo->getReturnAddrSaveIndex();
3849 bool isPPC64 = PPCSubTarget.isPPC64();
3851 PPCFrameInfo::getReturnSaveOffset(isPPC64, PPCSubTarget.isMachoABI());
3853 // Set up a frame object for the return address.
3854 RAIdx = MF.getFrameInfo()->CreateFixedObject(isPPC64 ? 8 : 4, Offset);
3856 // Remember it for next time.
3857 FuncInfo->setReturnAddrSaveIndex(RAIdx);
3859 // Make sure the function really does not optimize away the store of the RA
3861 FuncInfo->setLRStoreRequired();
3864 // Just load the return address off the stack.
3865 SDOperand RetAddrFI = DAG.getFrameIndex(RAIdx, getPointerTy());
3866 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
3869 SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
3870 // Depths > 0 not supported yet!
3871 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3874 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3875 bool isPPC64 = PtrVT == MVT::i64;
3877 MachineFunction &MF = DAG.getMachineFunction();
3878 MachineFrameInfo *MFI = MF.getFrameInfo();
3879 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
3880 && MFI->getStackSize();
3883 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
3886 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,