1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "ppc-codegen"
17 #include "PPCPredicates.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCISelLowering.h"
20 #include "PPCHazardRecognizers.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Constants.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/Compiler.h"
36 //===--------------------------------------------------------------------===//
37 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
38 /// instructions for SelectionDAG operations.
40 class VISIBILITY_HIDDEN PPCDAGToDAGISel : public SelectionDAGISel {
42 PPCTargetLowering &PPCLowering;
43 const PPCSubtarget &PPCSubTarget;
44 unsigned GlobalBaseReg;
46 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
47 : SelectionDAGISel(tm), TM(tm),
48 PPCLowering(*TM.getTargetLowering()),
49 PPCSubTarget(*TM.getSubtargetImpl()) {}
51 virtual bool runOnFunction(Function &Fn) {
52 // Make sure we re-emit a set of the global base reg if necessary
54 SelectionDAGISel::runOnFunction(Fn);
60 /// getI32Imm - Return a target constant with the specified value, of type
62 inline SDValue getI32Imm(unsigned Imm) {
63 return CurDAG->getTargetConstant(Imm, MVT::i32);
66 /// getI64Imm - Return a target constant with the specified value, of type
68 inline SDValue getI64Imm(uint64_t Imm) {
69 return CurDAG->getTargetConstant(Imm, MVT::i64);
72 /// getSmallIPtrImm - Return a target constant of pointer type.
73 inline SDValue getSmallIPtrImm(unsigned Imm) {
74 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
77 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
78 /// with any number of 0s on either side. The 1s are allowed to wrap from
79 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
80 /// 0x0F0F0000 is not, since all 1s are not contiguous.
81 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
84 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
85 /// rotate and mask opcode and mask operation.
86 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
87 unsigned &SH, unsigned &MB, unsigned &ME);
89 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
90 /// base register. Return the virtual register that holds this value.
91 SDNode *getGlobalBaseReg();
93 // Select - Convert the specified operand from a target-independent to a
94 // target-specific node if it hasn't already been changed.
95 SDNode *Select(SDValue Op);
97 SDNode *SelectBitfieldInsert(SDNode *N);
99 /// SelectCC - Select a comparison of the specified values with the
100 /// specified condition code, returning the CR# of the expression.
101 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC);
103 /// SelectAddrImm - Returns true if the address N can be represented by
104 /// a base register plus a signed 16-bit displacement [r+imm].
105 bool SelectAddrImm(SDValue Op, SDValue N, SDValue &Disp,
107 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
110 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
111 /// immediate field. Because preinc imms have already been validated, just
113 bool SelectAddrImmOffs(SDValue Op, SDValue N, SDValue &Out) const {
118 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
119 /// represented as an indexed [r+r] operation. Returns false if it can
120 /// be represented by [r+imm], which are preferred.
121 bool SelectAddrIdx(SDValue Op, SDValue N, SDValue &Base,
123 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
126 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
127 /// represented as an indexed [r+r] operation.
128 bool SelectAddrIdxOnly(SDValue Op, SDValue N, SDValue &Base,
130 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
133 /// SelectAddrImmShift - Returns true if the address N can be represented by
134 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
135 /// for use by STD and friends.
136 bool SelectAddrImmShift(SDValue Op, SDValue N, SDValue &Disp,
138 return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
141 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
142 /// inline asm expressions.
143 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
145 std::vector<SDValue> &OutOps) {
147 switch (ConstraintCode) {
148 default: return true;
150 if (!SelectAddrIdx(Op, Op, Op0, Op1))
151 SelectAddrImm(Op, Op, Op0, Op1);
153 case 'o': // offsetable
154 if (!SelectAddrImm(Op, Op, Op0, Op1)) {
156 Op1 = getSmallIPtrImm(0);
159 case 'v': // not offsetable
160 SelectAddrIdxOnly(Op, Op, Op0, Op1);
164 OutOps.push_back(Op0);
165 OutOps.push_back(Op1);
169 SDValue BuildSDIVSequence(SDNode *N);
170 SDValue BuildUDIVSequence(SDNode *N);
172 /// InstructionSelect - This callback is invoked by
173 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
174 virtual void InstructionSelect();
176 void InsertVRSaveCode(Function &Fn);
178 virtual const char *getPassName() const {
179 return "PowerPC DAG->DAG Pattern Instruction Selection";
182 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
183 /// this target when scheduling the DAG.
184 virtual ScheduleHazardRecognizer *CreateTargetHazardRecognizer() {
185 // Should use subtarget info to pick the right hazard recognizer. For
186 // now, always return a PPC970 recognizer.
187 const TargetInstrInfo *II = TM.getInstrInfo();
188 assert(II && "No InstrInfo?");
189 return new PPCHazardRecognizer970(*II);
192 // Include the pieces autogenerated from the target description.
193 #include "PPCGenDAGISel.inc"
196 SDNode *SelectSETCC(SDValue Op);
200 /// InstructionSelect - This callback is invoked by
201 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
202 void PPCDAGToDAGISel::InstructionSelect() {
205 // Select target instructions for the DAG.
207 CurDAG->RemoveDeadNodes();
210 /// InsertVRSaveCode - Once the entire function has been instruction selected,
211 /// all virtual registers are created and all machine instructions are built,
212 /// check to see if we need to save/restore VRSAVE. If so, do it.
213 void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
214 // Check to see if this function uses vector registers, which means we have to
215 // save and restore the VRSAVE register and update it with the regs we use.
217 // In this case, there will be virtual registers of vector type type created
218 // by the scheduler. Detect them now.
219 MachineFunction &Fn = MachineFunction::get(&F);
220 bool HasVectorVReg = false;
221 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
222 e = RegInfo->getLastVirtReg()+1; i != e; ++i)
223 if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) {
224 HasVectorVReg = true;
227 if (!HasVectorVReg) return; // nothing to do.
229 // If we have a vector register, we want to emit code into the entry and exit
230 // blocks to save and restore the VRSAVE register. We do this here (instead
231 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
233 // 1. This (trivially) reduces the load on the register allocator, by not
234 // having to represent the live range of the VRSAVE register.
235 // 2. This (more significantly) allows us to create a temporary virtual
236 // register to hold the saved VRSAVE value, allowing this temporary to be
237 // register allocated, instead of forcing it to be spilled to the stack.
239 // Create two vregs - one to hold the VRSAVE register that is live-in to the
240 // function and one for the value after having bits or'd into it.
241 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
242 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
244 const TargetInstrInfo &TII = *TM.getInstrInfo();
245 MachineBasicBlock &EntryBB = *Fn.begin();
246 // Emit the following code into the entry block:
247 // InVRSAVE = MFVRSAVE
248 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
249 // MTVRSAVE UpdatedVRSAVE
250 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
251 BuildMI(EntryBB, IP, TII.get(PPC::MFVRSAVE), InVRSAVE);
252 BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE),
253 UpdatedVRSAVE).addReg(InVRSAVE);
254 BuildMI(EntryBB, IP, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
256 // Find all return blocks, outputting a restore in each epilog.
257 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
258 if (!BB->empty() && BB->back().getDesc().isReturn()) {
259 IP = BB->end(); --IP;
261 // Skip over all terminator instructions, which are part of the return
263 MachineBasicBlock::iterator I2 = IP;
264 while (I2 != BB->begin() && (--I2)->getDesc().isTerminator())
267 // Emit: MTVRSAVE InVRSave
268 BuildMI(*BB, IP, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
274 /// getGlobalBaseReg - Output the instructions required to put the
275 /// base address to use for accessing globals into a register.
277 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
278 if (!GlobalBaseReg) {
279 const TargetInstrInfo &TII = *TM.getInstrInfo();
280 // Insert the set of GlobalBaseReg into the first MBB of the function
281 MachineBasicBlock &FirstMBB = BB->getParent()->front();
282 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
284 if (PPCLowering.getPointerTy() == MVT::i32) {
285 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
286 BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR), PPC::LR);
287 BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR), GlobalBaseReg);
289 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass);
290 BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR8), PPC::LR8);
291 BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg);
294 return CurDAG->getRegister(GlobalBaseReg,
295 PPCLowering.getPointerTy()).getNode();
298 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
299 /// or 64-bit immediate, and if the value can be accurately represented as a
300 /// sign extension from a 16-bit value. If so, this returns true and the
302 static bool isIntS16Immediate(SDNode *N, short &Imm) {
303 if (N->getOpcode() != ISD::Constant)
306 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
307 if (N->getValueType(0) == MVT::i32)
308 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
310 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
313 static bool isIntS16Immediate(SDValue Op, short &Imm) {
314 return isIntS16Immediate(Op.getNode(), Imm);
318 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
319 /// operand. If so Imm will receive the 32-bit value.
320 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
321 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
322 Imm = cast<ConstantSDNode>(N)->getZExtValue();
328 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
329 /// operand. If so Imm will receive the 64-bit value.
330 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
331 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
332 Imm = cast<ConstantSDNode>(N)->getZExtValue();
338 // isInt32Immediate - This method tests to see if a constant operand.
339 // If so Imm will receive the 32 bit value.
340 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
341 return isInt32Immediate(N.getNode(), Imm);
345 // isOpcWithIntImmediate - This method tests to see if the node is a specific
346 // opcode and that it has a immediate integer right operand.
347 // If so Imm will receive the 32 bit value.
348 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
349 return N->getOpcode() == Opc
350 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
353 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
354 if (isShiftedMask_32(Val)) {
355 // look for the first non-zero bit
356 MB = CountLeadingZeros_32(Val);
357 // look for the first zero bit after the run of ones
358 ME = CountLeadingZeros_32((Val - 1) ^ Val);
361 Val = ~Val; // invert mask
362 if (isShiftedMask_32(Val)) {
363 // effectively look for the first zero bit
364 ME = CountLeadingZeros_32(Val) - 1;
365 // effectively look for the first one bit after the run of zeros
366 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
374 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
375 bool IsShiftMask, unsigned &SH,
376 unsigned &MB, unsigned &ME) {
377 // Don't even go down this path for i64, since different logic will be
378 // necessary for rldicl/rldicr/rldimi.
379 if (N->getValueType(0) != MVT::i32)
383 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
384 unsigned Opcode = N->getOpcode();
385 if (N->getNumOperands() != 2 ||
386 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
389 if (Opcode == ISD::SHL) {
390 // apply shift left to mask if it comes first
391 if (IsShiftMask) Mask = Mask << Shift;
392 // determine which bits are made indeterminant by shift
393 Indeterminant = ~(0xFFFFFFFFu << Shift);
394 } else if (Opcode == ISD::SRL) {
395 // apply shift right to mask if it comes first
396 if (IsShiftMask) Mask = Mask >> Shift;
397 // determine which bits are made indeterminant by shift
398 Indeterminant = ~(0xFFFFFFFFu >> Shift);
399 // adjust for the left rotate
401 } else if (Opcode == ISD::ROTL) {
407 // if the mask doesn't intersect any Indeterminant bits
408 if (Mask && !(Mask & Indeterminant)) {
410 // make sure the mask is still a mask (wrap arounds may not be)
411 return isRunOfOnes(Mask, MB, ME);
416 /// SelectBitfieldInsert - turn an or of two masked values into
417 /// the rotate left word immediate then mask insert (rlwimi) instruction.
418 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
419 SDValue Op0 = N->getOperand(0);
420 SDValue Op1 = N->getOperand(1);
422 APInt LKZ, LKO, RKZ, RKO;
423 CurDAG->ComputeMaskedBits(Op0, APInt::getAllOnesValue(32), LKZ, LKO);
424 CurDAG->ComputeMaskedBits(Op1, APInt::getAllOnesValue(32), RKZ, RKO);
426 unsigned TargetMask = LKZ.getZExtValue();
427 unsigned InsertMask = RKZ.getZExtValue();
429 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
430 unsigned Op0Opc = Op0.getOpcode();
431 unsigned Op1Opc = Op1.getOpcode();
432 unsigned Value, SH = 0;
433 TargetMask = ~TargetMask;
434 InsertMask = ~InsertMask;
436 // If the LHS has a foldable shift and the RHS does not, then swap it to the
437 // RHS so that we can fold the shift into the insert.
438 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
439 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
440 Op0.getOperand(0).getOpcode() == ISD::SRL) {
441 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
442 Op1.getOperand(0).getOpcode() != ISD::SRL) {
444 std::swap(Op0Opc, Op1Opc);
445 std::swap(TargetMask, InsertMask);
448 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
449 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
450 Op1.getOperand(0).getOpcode() != ISD::SRL) {
452 std::swap(Op0Opc, Op1Opc);
453 std::swap(TargetMask, InsertMask);
458 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
459 SDValue Tmp1, Tmp2, Tmp3;
460 bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF;
462 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
463 isInt32Immediate(Op1.getOperand(1), Value)) {
464 Op1 = Op1.getOperand(0);
465 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
467 if (Op1Opc == ISD::AND) {
468 unsigned SHOpc = Op1.getOperand(0).getOpcode();
469 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
470 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
471 Op1 = Op1.getOperand(0).getOperand(0);
472 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
474 Op1 = Op1.getOperand(0);
478 Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0;
480 SDValue Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
482 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
488 /// SelectCC - Select a comparison of the specified values with the specified
489 /// condition code, returning the CR# of the expression.
490 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
492 // Always select the LHS.
495 if (LHS.getValueType() == MVT::i32) {
497 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
498 if (isInt32Immediate(RHS, Imm)) {
499 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
501 return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
502 getI32Imm(Imm & 0xFFFF)), 0);
503 // If this is a 16-bit signed immediate, fold it.
504 if (isInt16((int)Imm))
505 return SDValue(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
506 getI32Imm(Imm & 0xFFFF)), 0);
508 // For non-equality comparisons, the default code would materialize the
509 // constant, then compare against it, like this:
513 // Since we are just comparing for equality, we can emit this instead:
514 // xoris r0,r3,0x1234
515 // cmplwi cr0,r0,0x5678
517 SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, MVT::i32, LHS,
518 getI32Imm(Imm >> 16)), 0);
519 return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, Xor,
520 getI32Imm(Imm & 0xFFFF)), 0);
523 } else if (ISD::isUnsignedIntSetCC(CC)) {
524 if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
525 return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
526 getI32Imm(Imm & 0xFFFF)), 0);
530 if (isIntS16Immediate(RHS, SImm))
531 return SDValue(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
532 getI32Imm((int)SImm & 0xFFFF)),
536 } else if (LHS.getValueType() == MVT::i64) {
538 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
539 if (isInt64Immediate(RHS.getNode(), Imm)) {
540 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
542 return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
543 getI32Imm(Imm & 0xFFFF)), 0);
544 // If this is a 16-bit signed immediate, fold it.
546 return SDValue(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
547 getI32Imm(Imm & 0xFFFF)), 0);
549 // For non-equality comparisons, the default code would materialize the
550 // constant, then compare against it, like this:
554 // Since we are just comparing for equality, we can emit this instead:
555 // xoris r0,r3,0x1234
556 // cmpldi cr0,r0,0x5678
559 SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, MVT::i64, LHS,
560 getI64Imm(Imm >> 16)), 0);
561 return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, Xor,
562 getI64Imm(Imm & 0xFFFF)), 0);
566 } else if (ISD::isUnsignedIntSetCC(CC)) {
567 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt16(Imm))
568 return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
569 getI64Imm(Imm & 0xFFFF)), 0);
573 if (isIntS16Immediate(RHS, SImm))
574 return SDValue(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
575 getI64Imm(SImm & 0xFFFF)),
579 } else if (LHS.getValueType() == MVT::f32) {
582 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
585 return SDValue(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0);
588 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
594 assert(0 && "Should be lowered by legalize!");
595 default: assert(0 && "Unknown condition!"); abort();
597 case ISD::SETEQ: return PPC::PRED_EQ;
599 case ISD::SETNE: return PPC::PRED_NE;
601 case ISD::SETLT: return PPC::PRED_LT;
603 case ISD::SETLE: return PPC::PRED_LE;
605 case ISD::SETGT: return PPC::PRED_GT;
607 case ISD::SETGE: return PPC::PRED_GE;
608 case ISD::SETO: return PPC::PRED_NU;
609 case ISD::SETUO: return PPC::PRED_UN;
610 // These two are invalid for floating point. Assume we have int.
611 case ISD::SETULT: return PPC::PRED_LT;
612 case ISD::SETUGT: return PPC::PRED_GT;
616 /// getCRIdxForSetCC - Return the index of the condition register field
617 /// associated with the SetCC condition, and whether or not the field is
618 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
620 /// If this returns with Other != -1, then the returned comparison is an or of
621 /// two simpler comparisons. In this case, Invert is guaranteed to be false.
622 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) {
626 default: assert(0 && "Unknown condition!"); abort();
628 case ISD::SETLT: return 0; // Bit #0 = SETOLT
630 case ISD::SETGT: return 1; // Bit #1 = SETOGT
632 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
633 case ISD::SETUO: return 3; // Bit #3 = SETUO
635 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
637 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
639 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
640 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
645 assert(0 && "Invalid branch code: should be expanded by legalize");
646 // These are invalid for floating point. Assume integer.
647 case ISD::SETULT: return 0;
648 case ISD::SETUGT: return 1;
653 SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
654 SDNode *N = Op.getNode();
656 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
657 if (isInt32Immediate(N->getOperand(1), Imm)) {
658 // We can codegen setcc op, imm very efficiently compared to a brcond.
659 // Check for those cases here.
662 SDValue Op = N->getOperand(0);
666 Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
667 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
668 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
672 SDValue(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
673 Op, getI32Imm(~0U)), 0);
674 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
678 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
679 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
683 SDValue(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
684 T = SDValue(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
685 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
686 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
689 } else if (Imm == ~0U) { // setcc op, -1
690 SDValue Op = N->getOperand(0);
694 Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
695 Op, getI32Imm(1)), 0);
696 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
697 SDValue(CurDAG->getTargetNode(PPC::LI, MVT::i32,
701 Op = SDValue(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0);
702 SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
704 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
708 SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
710 SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
712 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
713 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
716 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
717 Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
718 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
727 unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx);
728 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
731 // Force the ccreg into CR7.
732 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
734 SDValue InFlag(0, 0); // Null incoming flag value.
735 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg,
738 if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
739 IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg,
742 IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
744 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
745 getI32Imm(31), getI32Imm(31) };
746 if (OtherCondIdx == -1 && !Inv)
747 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
749 // Get the specified bit.
751 SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
753 assert(OtherCondIdx == -1 && "Can't have split plus negation");
754 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
757 // Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT.
758 // We already got the bit for the first part of the comparison (e.g. SETULE).
760 // Get the other bit of the comparison.
761 Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
763 SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
765 return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
769 // Select - Convert the specified operand from a target-independent to a
770 // target-specific node if it hasn't already been changed.
771 SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
772 SDNode *N = Op.getNode();
773 if (N->isMachineOpcode())
774 return NULL; // Already selected.
776 switch (N->getOpcode()) {
779 case ISD::Constant: {
780 if (N->getValueType(0) == MVT::i64) {
782 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
783 // Assume no remaining bits.
784 unsigned Remainder = 0;
785 // Assume no shift required.
788 // If it can't be represented as a 32 bit value.
790 Shift = CountTrailingZeros_64(Imm);
791 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
793 // If the shifted value fits 32 bits.
794 if (isInt32(ImmSh)) {
795 // Go with the shifted value.
798 // Still stuck with a 64 bit value.
805 // Intermediate operand.
808 // Handle first 32 bits.
809 unsigned Lo = Imm & 0xFFFF;
810 unsigned Hi = (Imm >> 16) & 0xFFFF;
815 Result = CurDAG->getTargetNode(PPC::LI8, MVT::i64, getI32Imm(Lo));
817 // Handle the Hi bits.
818 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
819 Result = CurDAG->getTargetNode(OpC, MVT::i64, getI32Imm(Hi));
821 Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64,
822 SDValue(Result, 0), getI32Imm(Lo));
825 Result = CurDAG->getTargetNode(PPC::LIS8, MVT::i64, getI32Imm(Hi));
828 // If no shift, we're done.
829 if (!Shift) return Result;
831 // Shift for next step if the upper 32-bits were not zero.
833 Result = CurDAG->getTargetNode(PPC::RLDICR, MVT::i64,
835 getI32Imm(Shift), getI32Imm(63 - Shift));
838 // Add in the last bits as required.
839 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
840 Result = CurDAG->getTargetNode(PPC::ORIS8, MVT::i64,
841 SDValue(Result, 0), getI32Imm(Hi));
843 if ((Lo = Remainder & 0xFFFF)) {
844 Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64,
845 SDValue(Result, 0), getI32Imm(Lo));
854 return SelectSETCC(Op);
855 case PPCISD::GlobalBaseReg:
856 return getGlobalBaseReg();
858 case ISD::FrameIndex: {
859 int FI = cast<FrameIndexSDNode>(N)->getIndex();
860 SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
861 unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
863 return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
865 return CurDAG->getTargetNode(Opc, Op.getValueType(), TFI,
870 SDValue InFlag = N->getOperand(1);
871 // Use MFOCRF if supported.
872 if (PPCSubTarget.isGigaProcessor())
873 return CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32,
874 N->getOperand(0), InFlag);
876 return CurDAG->getTargetNode(PPC::MFCR, MVT::i32, InFlag);
880 // FIXME: since this depends on the setting of the carry flag from the srawi
881 // we should really be making notes about that for the scheduler.
882 // FIXME: It sure would be nice if we could cheaply recognize the
883 // srl/add/sra pattern the dag combiner will generate for this as
884 // sra/addze rather than having to handle sdiv ourselves. oh well.
886 if (isInt32Immediate(N->getOperand(1), Imm)) {
887 SDValue N0 = N->getOperand(0);
888 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
890 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
891 N0, getI32Imm(Log2_32(Imm)));
892 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
893 SDValue(Op, 0), SDValue(Op, 1));
894 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
896 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
897 N0, getI32Imm(Log2_32(-Imm)));
899 SDValue(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32,
900 SDValue(Op, 0), SDValue(Op, 1)),
902 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
906 // Other cases are autogenerated.
911 // Handle preincrement loads.
912 LoadSDNode *LD = cast<LoadSDNode>(Op);
913 MVT LoadedVT = LD->getMemoryVT();
915 // Normal loads are handled by code generated from the .td file.
916 if (LD->getAddressingMode() != ISD::PRE_INC)
919 SDValue Offset = LD->getOffset();
920 if (isa<ConstantSDNode>(Offset) ||
921 Offset.getOpcode() == ISD::TargetGlobalAddress) {
924 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
925 if (LD->getValueType(0) != MVT::i64) {
926 // Handle PPC32 integer and normal FP loads.
927 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
928 switch (LoadedVT.getSimpleVT()) {
929 default: assert(0 && "Invalid PPC load type!");
930 case MVT::f64: Opcode = PPC::LFDU; break;
931 case MVT::f32: Opcode = PPC::LFSU; break;
932 case MVT::i32: Opcode = PPC::LWZU; break;
933 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
935 case MVT::i8: Opcode = PPC::LBZU; break;
938 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
939 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
940 switch (LoadedVT.getSimpleVT()) {
941 default: assert(0 && "Invalid PPC load type!");
942 case MVT::i64: Opcode = PPC::LDU; break;
943 case MVT::i32: Opcode = PPC::LWZU8; break;
944 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
946 case MVT::i8: Opcode = PPC::LBZU8; break;
950 SDValue Chain = LD->getChain();
951 SDValue Base = LD->getBasePtr();
952 SDValue Ops[] = { Offset, Base, Chain };
954 return CurDAG->getTargetNode(Opcode, LD->getValueType(0),
955 PPCLowering.getPointerTy(),
958 assert(0 && "R+R preindex loads not supported yet!");
963 unsigned Imm, Imm2, SH, MB, ME;
965 // If this is an and of a value rotated between 0 and 31 bits and then and'd
966 // with a mask, emit rlwinm
967 if (isInt32Immediate(N->getOperand(1), Imm) &&
968 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
969 SDValue Val = N->getOperand(0).getOperand(0);
970 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
971 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
973 // If this is just a masked value where the input is not handled above, and
974 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
975 if (isInt32Immediate(N->getOperand(1), Imm) &&
976 isRunOfOnes(Imm, MB, ME) &&
977 N->getOperand(0).getOpcode() != ISD::ROTL) {
978 SDValue Val = N->getOperand(0);
979 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
980 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
982 // AND X, 0 -> 0, not "rlwinm 32".
983 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
984 ReplaceUses(SDValue(N, 0), N->getOperand(1));
987 // ISD::OR doesn't get all the bitfield insertion fun.
988 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
989 if (isInt32Immediate(N->getOperand(1), Imm) &&
990 N->getOperand(0).getOpcode() == ISD::OR &&
991 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
994 if (isRunOfOnes(Imm, MB, ME)) {
995 SDValue Ops[] = { N->getOperand(0).getOperand(0),
996 N->getOperand(0).getOperand(1),
997 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
998 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
1002 // Other cases are autogenerated.
1006 if (N->getValueType(0) == MVT::i32)
1007 if (SDNode *I = SelectBitfieldInsert(N))
1010 // Other cases are autogenerated.
1013 unsigned Imm, SH, MB, ME;
1014 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1015 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1016 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1017 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1018 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1021 // Other cases are autogenerated.
1025 unsigned Imm, SH, MB, ME;
1026 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1027 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1028 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1029 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1030 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1033 // Other cases are autogenerated.
1036 case ISD::SELECT_CC: {
1037 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1039 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1040 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1041 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1042 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1043 if (N1C->isNullValue() && N3C->isNullValue() &&
1044 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
1045 // FIXME: Implement this optzn for PPC64.
1046 N->getValueType(0) == MVT::i32) {
1048 CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1049 N->getOperand(0), getI32Imm(~0U));
1050 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1051 SDValue(Tmp, 0), N->getOperand(0),
1055 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
1056 unsigned BROpc = getPredicateForSetCC(CC);
1058 unsigned SelectCCOp;
1059 if (N->getValueType(0) == MVT::i32)
1060 SelectCCOp = PPC::SELECT_CC_I4;
1061 else if (N->getValueType(0) == MVT::i64)
1062 SelectCCOp = PPC::SELECT_CC_I8;
1063 else if (N->getValueType(0) == MVT::f32)
1064 SelectCCOp = PPC::SELECT_CC_F4;
1065 else if (N->getValueType(0) == MVT::f64)
1066 SelectCCOp = PPC::SELECT_CC_F8;
1068 SelectCCOp = PPC::SELECT_CC_VRRC;
1070 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
1072 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
1074 case PPCISD::COND_BRANCH: {
1075 // Op #0 is the Chain.
1076 // Op #1 is the PPC::PRED_* number.
1078 // Op #3 is the Dest MBB
1079 // Op #4 is the Flag.
1080 // Prevent PPC::PRED_* from being selected into LI.
1082 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
1083 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
1084 N->getOperand(0), N->getOperand(4) };
1085 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
1088 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1089 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
1090 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
1091 N->getOperand(4), N->getOperand(0) };
1092 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
1095 // FIXME: Should custom lower this.
1096 SDValue Chain = N->getOperand(0);
1097 SDValue Target = N->getOperand(1);
1098 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1099 Chain = SDValue(CurDAG->getTargetNode(Opc, MVT::Other, Target,
1101 return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
1103 case ISD::DECLARE: {
1104 SDValue Chain = N->getOperand(0);
1105 SDValue N1 = N->getOperand(1);
1106 SDValue N2 = N->getOperand(2);
1107 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N1);
1110 if (N2.getOpcode() == ISD::ADD &&
1111 N2.getOperand(0).getOpcode() == PPCISD::Hi &&
1112 N2.getOperand(1).getOpcode() == PPCISD::Lo)
1113 N2 = N2.getOperand(0).getOperand(0);
1114 if (!isa<GlobalAddressSDNode>(N2))
1116 int FI = cast<FrameIndexSDNode>(N1)->getIndex();
1117 GlobalValue *GV = cast<GlobalAddressSDNode>(N2)->getGlobal();
1118 SDValue Tmp1 = CurDAG->getTargetFrameIndex(FI, TLI.getPointerTy());
1119 SDValue Tmp2 = CurDAG->getTargetGlobalAddress(GV, TLI.getPointerTy());
1120 return CurDAG->SelectNodeTo(N, TargetInstrInfo::DECLARE,
1121 MVT::Other, Tmp1, Tmp2, Chain);
1125 return SelectCode(Op);
1130 /// createPPCISelDag - This pass converts a legalized DAG into a
1131 /// PowerPC-specific DAG, ready for instruction scheduling.
1133 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1134 return new PPCDAGToDAGISel(TM);