1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalAlias.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/GlobalVariable.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Module.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetOptions.h"
39 #define DEBUG_TYPE "ppc-codegen"
41 // FIXME: Remove this once the bug has been fixed!
42 cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
43 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
45 cl::opt<bool> UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true),
46 cl::desc("use aggressive ppc isel for bit permutations"), cl::Hidden);
47 cl::opt<bool> BPermRewriterNoMasking("ppc-bit-perm-rewriter-stress-rotates",
48 cl::desc("stress rotate selection in aggressive ppc isel for "
49 "bit permutations"), cl::Hidden);
52 void initializePPCDAGToDAGISelPass(PassRegistry&);
56 //===--------------------------------------------------------------------===//
57 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
58 /// instructions for SelectionDAG operations.
60 class PPCDAGToDAGISel : public SelectionDAGISel {
61 const PPCTargetMachine &TM;
62 const PPCTargetLowering *PPCLowering;
63 const PPCSubtarget *PPCSubTarget;
64 unsigned GlobalBaseReg;
66 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
67 : SelectionDAGISel(tm), TM(tm),
68 PPCLowering(TM.getSubtargetImpl()->getTargetLowering()),
69 PPCSubTarget(TM.getSubtargetImpl()) {
70 initializePPCDAGToDAGISelPass(*PassRegistry::getPassRegistry());
73 bool runOnMachineFunction(MachineFunction &MF) override {
74 // Make sure we re-emit a set of the global base reg if necessary
76 PPCLowering = TM.getSubtargetImpl()->getTargetLowering();
77 PPCSubTarget = TM.getSubtargetImpl();
78 SelectionDAGISel::runOnMachineFunction(MF);
80 if (!PPCSubTarget->isSVR4ABI())
86 void PreprocessISelDAG() override;
87 void PostprocessISelDAG() override;
89 /// getI32Imm - Return a target constant with the specified value, of type
91 inline SDValue getI32Imm(unsigned Imm) {
92 return CurDAG->getTargetConstant(Imm, MVT::i32);
95 /// getI64Imm - Return a target constant with the specified value, of type
97 inline SDValue getI64Imm(uint64_t Imm) {
98 return CurDAG->getTargetConstant(Imm, MVT::i64);
101 /// getSmallIPtrImm - Return a target constant of pointer type.
102 inline SDValue getSmallIPtrImm(unsigned Imm) {
103 return CurDAG->getTargetConstant(Imm, PPCLowering->getPointerTy());
106 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
107 /// with any number of 0s on either side. The 1s are allowed to wrap from
108 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
109 /// 0x0F0F0000 is not, since all 1s are not contiguous.
110 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
113 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
114 /// rotate and mask opcode and mask operation.
115 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
116 unsigned &SH, unsigned &MB, unsigned &ME);
118 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
119 /// base register. Return the virtual register that holds this value.
120 SDNode *getGlobalBaseReg();
122 SDNode *getFrameIndex(SDNode *SN, SDNode *N, unsigned Offset = 0);
124 // Select - Convert the specified operand from a target-independent to a
125 // target-specific node if it hasn't already been changed.
126 SDNode *Select(SDNode *N) override;
128 SDNode *SelectBitfieldInsert(SDNode *N);
129 SDNode *SelectBitPermutation(SDNode *N);
131 /// SelectCC - Select a comparison of the specified values with the
132 /// specified condition code, returning the CR# of the expression.
133 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl);
135 /// SelectAddrImm - Returns true if the address N can be represented by
136 /// a base register plus a signed 16-bit displacement [r+imm].
137 bool SelectAddrImm(SDValue N, SDValue &Disp,
139 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, false);
142 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
143 /// immediate field. Note that the operand at this point is already the
144 /// result of a prior SelectAddressRegImm call.
145 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
146 if (N.getOpcode() == ISD::TargetConstant ||
147 N.getOpcode() == ISD::TargetGlobalAddress) {
155 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
156 /// represented as an indexed [r+r] operation. Returns false if it can
157 /// be represented by [r+imm], which are preferred.
158 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
159 return PPCLowering->SelectAddressRegReg(N, Base, Index, *CurDAG);
162 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
163 /// represented as an indexed [r+r] operation.
164 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
165 return PPCLowering->SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
168 /// SelectAddrImmX4 - Returns true if the address N can be represented by
169 /// a base register plus a signed 16-bit displacement that is a multiple of 4.
170 /// Suitable for use by STD and friends.
171 bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) {
172 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, true);
175 // Select an address into a single register.
176 bool SelectAddr(SDValue N, SDValue &Base) {
181 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
182 /// inline asm expressions. It is always correct to compute the value into
183 /// a register. The case of adding a (possibly relocatable) constant to a
184 /// register can be improved, but it is wrong to substitute Reg+Reg for
185 /// Reg in an asm, because the load or store opcode would have to change.
186 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
188 std::vector<SDValue> &OutOps) override {
189 // We need to make sure that this one operand does not end up in r0
190 // (because we might end up lowering this as 0(%op)).
191 const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();
192 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1);
193 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
195 SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
196 SDLoc(Op), Op.getValueType(),
199 OutOps.push_back(NewOp);
203 void InsertVRSaveCode(MachineFunction &MF);
205 const char *getPassName() const override {
206 return "PowerPC DAG->DAG Pattern Instruction Selection";
209 // Include the pieces autogenerated from the target description.
210 #include "PPCGenDAGISel.inc"
213 SDNode *SelectSETCC(SDNode *N);
215 void PeepholePPC64();
216 void PeepholePPC64ZExt();
217 void PeepholeCROps();
219 SDValue combineToCMPB(SDNode *N);
221 bool AllUsersSelectZero(SDNode *N);
222 void SwapAllSelectUsers(SDNode *N);
226 /// InsertVRSaveCode - Once the entire function has been instruction selected,
227 /// all virtual registers are created and all machine instructions are built,
228 /// check to see if we need to save/restore VRSAVE. If so, do it.
229 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
230 // Check to see if this function uses vector registers, which means we have to
231 // save and restore the VRSAVE register and update it with the regs we use.
233 // In this case, there will be virtual registers of vector type created
234 // by the scheduler. Detect them now.
235 bool HasVectorVReg = false;
236 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
237 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
238 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
239 HasVectorVReg = true;
243 if (!HasVectorVReg) return; // nothing to do.
245 // If we have a vector register, we want to emit code into the entry and exit
246 // blocks to save and restore the VRSAVE register. We do this here (instead
247 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
249 // 1. This (trivially) reduces the load on the register allocator, by not
250 // having to represent the live range of the VRSAVE register.
251 // 2. This (more significantly) allows us to create a temporary virtual
252 // register to hold the saved VRSAVE value, allowing this temporary to be
253 // register allocated, instead of forcing it to be spilled to the stack.
255 // Create two vregs - one to hold the VRSAVE register that is live-in to the
256 // function and one for the value after having bits or'd into it.
257 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
258 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
260 const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
261 MachineBasicBlock &EntryBB = *Fn.begin();
263 // Emit the following code into the entry block:
264 // InVRSAVE = MFVRSAVE
265 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
266 // MTVRSAVE UpdatedVRSAVE
267 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
268 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
269 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
270 UpdatedVRSAVE).addReg(InVRSAVE);
271 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
273 // Find all return blocks, outputting a restore in each epilog.
274 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
275 if (!BB->empty() && BB->back().isReturn()) {
276 IP = BB->end(); --IP;
278 // Skip over all terminator instructions, which are part of the return
280 MachineBasicBlock::iterator I2 = IP;
281 while (I2 != BB->begin() && (--I2)->isTerminator())
284 // Emit: MTVRSAVE InVRSave
285 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
291 /// getGlobalBaseReg - Output the instructions required to put the
292 /// base address to use for accessing globals into a register.
294 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
295 if (!GlobalBaseReg) {
296 const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
297 // Insert the set of GlobalBaseReg into the first MBB of the function
298 MachineBasicBlock &FirstMBB = MF->front();
299 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
300 const Module *M = MF->getFunction()->getParent();
303 if (PPCLowering->getPointerTy() == MVT::i32) {
304 if (PPCSubTarget->isTargetELF()) {
305 GlobalBaseReg = PPC::R30;
306 if (M->getPICLevel() == PICLevel::Small) {
307 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR));
308 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
310 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
311 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
312 unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
313 BuildMI(FirstMBB, MBBI, dl,
314 TII.get(PPC::UpdateGBR)).addReg(GlobalBaseReg)
315 .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg);
316 MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
320 RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass);
321 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
322 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
325 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_NOX0RegClass);
326 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
327 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
330 return CurDAG->getRegister(GlobalBaseReg,
331 PPCLowering->getPointerTy()).getNode();
334 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
335 /// or 64-bit immediate, and if the value can be accurately represented as a
336 /// sign extension from a 16-bit value. If so, this returns true and the
338 static bool isIntS16Immediate(SDNode *N, short &Imm) {
339 if (N->getOpcode() != ISD::Constant)
342 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
343 if (N->getValueType(0) == MVT::i32)
344 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
346 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
349 static bool isIntS16Immediate(SDValue Op, short &Imm) {
350 return isIntS16Immediate(Op.getNode(), Imm);
354 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
355 /// operand. If so Imm will receive the 32-bit value.
356 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
357 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
358 Imm = cast<ConstantSDNode>(N)->getZExtValue();
364 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
365 /// operand. If so Imm will receive the 64-bit value.
366 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
367 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
368 Imm = cast<ConstantSDNode>(N)->getZExtValue();
374 // isInt32Immediate - This method tests to see if a constant operand.
375 // If so Imm will receive the 32 bit value.
376 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
377 return isInt32Immediate(N.getNode(), Imm);
381 // isOpcWithIntImmediate - This method tests to see if the node is a specific
382 // opcode and that it has a immediate integer right operand.
383 // If so Imm will receive the 32 bit value.
384 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
385 return N->getOpcode() == Opc
386 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
389 SDNode *PPCDAGToDAGISel::getFrameIndex(SDNode *SN, SDNode *N, unsigned Offset) {
391 int FI = cast<FrameIndexSDNode>(N)->getIndex();
392 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
393 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
395 return CurDAG->SelectNodeTo(SN, Opc, N->getValueType(0), TFI,
396 getSmallIPtrImm(Offset));
397 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
398 getSmallIPtrImm(Offset));
401 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
405 if (isShiftedMask_32(Val)) {
406 // look for the first non-zero bit
407 MB = countLeadingZeros(Val);
408 // look for the first zero bit after the run of ones
409 ME = countLeadingZeros((Val - 1) ^ Val);
412 Val = ~Val; // invert mask
413 if (isShiftedMask_32(Val)) {
414 // effectively look for the first zero bit
415 ME = countLeadingZeros(Val) - 1;
416 // effectively look for the first one bit after the run of zeros
417 MB = countLeadingZeros((Val - 1) ^ Val) + 1;
425 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
426 bool isShiftMask, unsigned &SH,
427 unsigned &MB, unsigned &ME) {
428 // Don't even go down this path for i64, since different logic will be
429 // necessary for rldicl/rldicr/rldimi.
430 if (N->getValueType(0) != MVT::i32)
434 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
435 unsigned Opcode = N->getOpcode();
436 if (N->getNumOperands() != 2 ||
437 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
440 if (Opcode == ISD::SHL) {
441 // apply shift left to mask if it comes first
442 if (isShiftMask) Mask = Mask << Shift;
443 // determine which bits are made indeterminant by shift
444 Indeterminant = ~(0xFFFFFFFFu << Shift);
445 } else if (Opcode == ISD::SRL) {
446 // apply shift right to mask if it comes first
447 if (isShiftMask) Mask = Mask >> Shift;
448 // determine which bits are made indeterminant by shift
449 Indeterminant = ~(0xFFFFFFFFu >> Shift);
450 // adjust for the left rotate
452 } else if (Opcode == ISD::ROTL) {
458 // if the mask doesn't intersect any Indeterminant bits
459 if (Mask && !(Mask & Indeterminant)) {
461 // make sure the mask is still a mask (wrap arounds may not be)
462 return isRunOfOnes(Mask, MB, ME);
467 /// SelectBitfieldInsert - turn an or of two masked values into
468 /// the rotate left word immediate then mask insert (rlwimi) instruction.
469 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
470 SDValue Op0 = N->getOperand(0);
471 SDValue Op1 = N->getOperand(1);
474 APInt LKZ, LKO, RKZ, RKO;
475 CurDAG->computeKnownBits(Op0, LKZ, LKO);
476 CurDAG->computeKnownBits(Op1, RKZ, RKO);
478 unsigned TargetMask = LKZ.getZExtValue();
479 unsigned InsertMask = RKZ.getZExtValue();
481 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
482 unsigned Op0Opc = Op0.getOpcode();
483 unsigned Op1Opc = Op1.getOpcode();
484 unsigned Value, SH = 0;
485 TargetMask = ~TargetMask;
486 InsertMask = ~InsertMask;
488 // If the LHS has a foldable shift and the RHS does not, then swap it to the
489 // RHS so that we can fold the shift into the insert.
490 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
491 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
492 Op0.getOperand(0).getOpcode() == ISD::SRL) {
493 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
494 Op1.getOperand(0).getOpcode() != ISD::SRL) {
496 std::swap(Op0Opc, Op1Opc);
497 std::swap(TargetMask, InsertMask);
500 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
501 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
502 Op1.getOperand(0).getOpcode() != ISD::SRL) {
504 std::swap(Op0Opc, Op1Opc);
505 std::swap(TargetMask, InsertMask);
510 if (isRunOfOnes(InsertMask, MB, ME)) {
513 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
514 isInt32Immediate(Op1.getOperand(1), Value)) {
515 Op1 = Op1.getOperand(0);
516 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
518 if (Op1Opc == ISD::AND) {
519 // The AND mask might not be a constant, and we need to make sure that
520 // if we're going to fold the masking with the insert, all bits not
521 // know to be zero in the mask are known to be one.
523 CurDAG->computeKnownBits(Op1.getOperand(1), MKZ, MKO);
524 bool CanFoldMask = InsertMask == MKO.getZExtValue();
526 unsigned SHOpc = Op1.getOperand(0).getOpcode();
527 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
528 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
529 // Note that Value must be in range here (less than 32) because
530 // otherwise there would not be any bits set in InsertMask.
531 Op1 = Op1.getOperand(0).getOperand(0);
532 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
537 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
539 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
545 // Predict the number of instructions that would be generated by calling
547 static unsigned SelectInt64Count(int64_t Imm) {
548 // Assume no remaining bits.
549 unsigned Remainder = 0;
550 // Assume no shift required.
553 // If it can't be represented as a 32 bit value.
554 if (!isInt<32>(Imm)) {
555 Shift = countTrailingZeros<uint64_t>(Imm);
556 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
558 // If the shifted value fits 32 bits.
559 if (isInt<32>(ImmSh)) {
560 // Go with the shifted value.
563 // Still stuck with a 64 bit value.
570 // Intermediate operand.
573 // Handle first 32 bits.
574 unsigned Lo = Imm & 0xFFFF;
575 unsigned Hi = (Imm >> 16) & 0xFFFF;
578 if (isInt<16>(Imm)) {
582 // Handle the Hi bits and Lo bits.
589 // If no shift, we're done.
590 if (!Shift) return Result;
592 // Shift for next step if the upper 32-bits were not zero.
596 // Add in the last bits as required.
597 if ((Hi = (Remainder >> 16) & 0xFFFF))
599 if ((Lo = Remainder & 0xFFFF))
605 // Select a 64-bit constant. For cost-modeling purposes, SelectInt64Count
606 // (above) needs to be kept in sync with this function.
607 static SDNode *SelectInt64(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
608 // Assume no remaining bits.
609 unsigned Remainder = 0;
610 // Assume no shift required.
613 // If it can't be represented as a 32 bit value.
614 if (!isInt<32>(Imm)) {
615 Shift = countTrailingZeros<uint64_t>(Imm);
616 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
618 // If the shifted value fits 32 bits.
619 if (isInt<32>(ImmSh)) {
620 // Go with the shifted value.
623 // Still stuck with a 64 bit value.
630 // Intermediate operand.
633 // Handle first 32 bits.
634 unsigned Lo = Imm & 0xFFFF;
635 unsigned Hi = (Imm >> 16) & 0xFFFF;
637 auto getI32Imm = [CurDAG](unsigned Imm) {
638 return CurDAG->getTargetConstant(Imm, MVT::i32);
642 if (isInt<16>(Imm)) {
644 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
646 // Handle the Hi bits.
647 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
648 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
650 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
651 SDValue(Result, 0), getI32Imm(Lo));
654 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
657 // If no shift, we're done.
658 if (!Shift) return Result;
660 // Shift for next step if the upper 32-bits were not zero.
662 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
665 getI32Imm(63 - Shift));
668 // Add in the last bits as required.
669 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
670 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
671 SDValue(Result, 0), getI32Imm(Hi));
673 if ((Lo = Remainder & 0xFFFF)) {
674 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
675 SDValue(Result, 0), getI32Imm(Lo));
681 // Select a 64-bit constant.
682 static SDNode *SelectInt64(SelectionDAG *CurDAG, SDNode *N) {
686 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
687 return SelectInt64(CurDAG, dl, Imm);
691 class BitPermutationSelector {
695 // The bit number in the value, using a convention where bit 0 is the
704 ValueBit(SDValue V, unsigned I, Kind K = Variable)
705 : V(V), Idx(I), K(K) {}
706 ValueBit(Kind K = Variable)
707 : V(SDValue(nullptr, 0)), Idx(UINT32_MAX), K(K) {}
709 bool isZero() const {
710 return K == ConstZero;
713 bool hasValue() const {
714 return K == Variable;
717 SDValue getValue() const {
718 assert(hasValue() && "Cannot get the value of a constant bit");
722 unsigned getValueBitIndex() const {
723 assert(hasValue() && "Cannot get the value bit index of a constant bit");
728 // A bit group has the same underlying value and the same rotate factor.
732 unsigned StartIdx, EndIdx;
734 // This rotation amount assumes that the lower 32 bits of the quantity are
735 // replicated in the high 32 bits by the rotation operator (which is done
736 // by rlwinm and friends in 64-bit mode).
738 // Did converting to Repl32 == true change the rotation factor? If it did,
739 // it decreased it by 32.
741 // Was this group coalesced after setting Repl32 to true?
742 bool Repl32Coalesced;
744 BitGroup(SDValue V, unsigned R, unsigned S, unsigned E)
745 : V(V), RLAmt(R), StartIdx(S), EndIdx(E), Repl32(false), Repl32CR(false),
746 Repl32Coalesced(false) {
747 DEBUG(dbgs() << "\tbit group for " << V.getNode() << " RLAmt = " << R <<
748 " [" << S << ", " << E << "]\n");
752 // Information on each (Value, RLAmt) pair (like the number of groups
753 // associated with each) used to choose the lowering method.
754 struct ValueRotInfo {
758 unsigned FirstGroupStartIdx;
762 : RLAmt(UINT32_MAX), NumGroups(0), FirstGroupStartIdx(UINT32_MAX),
765 // For sorting (in reverse order) by NumGroups, and then by
766 // FirstGroupStartIdx.
767 bool operator < (const ValueRotInfo &Other) const {
768 // We need to sort so that the non-Repl32 come first because, when we're
769 // doing masking, the Repl32 bit groups might be subsumed into the 64-bit
770 // masking operation.
771 if (Repl32 < Other.Repl32)
773 else if (Repl32 > Other.Repl32)
775 else if (NumGroups > Other.NumGroups)
777 else if (NumGroups < Other.NumGroups)
779 else if (FirstGroupStartIdx < Other.FirstGroupStartIdx)
785 // Return true if something interesting was deduced, return false if we're
786 // providing only a generic representation of V (or something else likewise
787 // uninteresting for instruction selection).
788 bool getValueBits(SDValue V, SmallVector<ValueBit, 64> &Bits) {
789 switch (V.getOpcode()) {
792 if (isa<ConstantSDNode>(V.getOperand(1))) {
793 unsigned RotAmt = V.getConstantOperandVal(1);
795 SmallVector<ValueBit, 64> LHSBits(Bits.size());
796 getValueBits(V.getOperand(0), LHSBits);
798 for (unsigned i = 0; i < Bits.size(); ++i)
799 Bits[i] = LHSBits[i < RotAmt ? i + (Bits.size() - RotAmt) : i - RotAmt];
805 if (isa<ConstantSDNode>(V.getOperand(1))) {
806 unsigned ShiftAmt = V.getConstantOperandVal(1);
808 SmallVector<ValueBit, 64> LHSBits(Bits.size());
809 getValueBits(V.getOperand(0), LHSBits);
811 for (unsigned i = ShiftAmt; i < Bits.size(); ++i)
812 Bits[i] = LHSBits[i - ShiftAmt];
814 for (unsigned i = 0; i < ShiftAmt; ++i)
815 Bits[i] = ValueBit(ValueBit::ConstZero);
821 if (isa<ConstantSDNode>(V.getOperand(1))) {
822 unsigned ShiftAmt = V.getConstantOperandVal(1);
824 SmallVector<ValueBit, 64> LHSBits(Bits.size());
825 getValueBits(V.getOperand(0), LHSBits);
827 for (unsigned i = 0; i < Bits.size() - ShiftAmt; ++i)
828 Bits[i] = LHSBits[i + ShiftAmt];
830 for (unsigned i = Bits.size() - ShiftAmt; i < Bits.size(); ++i)
831 Bits[i] = ValueBit(ValueBit::ConstZero);
837 if (isa<ConstantSDNode>(V.getOperand(1))) {
838 uint64_t Mask = V.getConstantOperandVal(1);
840 SmallVector<ValueBit, 64> LHSBits(Bits.size());
841 bool LHSTrivial = getValueBits(V.getOperand(0), LHSBits);
843 for (unsigned i = 0; i < Bits.size(); ++i)
844 if (((Mask >> i) & 1) == 1)
845 Bits[i] = LHSBits[i];
847 Bits[i] = ValueBit(ValueBit::ConstZero);
849 // Mark this as interesting, only if the LHS was also interesting. This
850 // prevents the overall procedure from matching a single immediate 'and'
851 // (which is non-optimal because such an and might be folded with other
852 // things if we don't select it here).
857 SmallVector<ValueBit, 64> LHSBits(Bits.size()), RHSBits(Bits.size());
858 getValueBits(V.getOperand(0), LHSBits);
859 getValueBits(V.getOperand(1), RHSBits);
861 bool AllDisjoint = true;
862 for (unsigned i = 0; i < Bits.size(); ++i)
863 if (LHSBits[i].isZero())
864 Bits[i] = RHSBits[i];
865 else if (RHSBits[i].isZero())
866 Bits[i] = LHSBits[i];
879 for (unsigned i = 0; i < Bits.size(); ++i)
880 Bits[i] = ValueBit(V, i);
885 // For each value (except the constant ones), compute the left-rotate amount
886 // to get it from its original to final position.
887 void computeRotationAmounts() {
889 RLAmt.resize(Bits.size());
890 for (unsigned i = 0; i < Bits.size(); ++i)
891 if (Bits[i].hasValue()) {
892 unsigned VBI = Bits[i].getValueBitIndex();
896 RLAmt[i] = Bits.size() - (VBI - i);
897 } else if (Bits[i].isZero()) {
899 RLAmt[i] = UINT32_MAX;
901 llvm_unreachable("Unknown value bit type");
905 // Collect groups of consecutive bits with the same underlying value and
906 // rotation factor. If we're doing late masking, we ignore zeros, otherwise
907 // they break up groups.
908 void collectBitGroups(bool LateMask) {
911 unsigned LastRLAmt = RLAmt[0];
912 SDValue LastValue = Bits[0].hasValue() ? Bits[0].getValue() : SDValue();
913 unsigned LastGroupStartIdx = 0;
914 for (unsigned i = 1; i < Bits.size(); ++i) {
915 unsigned ThisRLAmt = RLAmt[i];
916 SDValue ThisValue = Bits[i].hasValue() ? Bits[i].getValue() : SDValue();
917 if (LateMask && !ThisValue) {
918 ThisValue = LastValue;
919 ThisRLAmt = LastRLAmt;
920 // If we're doing late masking, then the first bit group always starts
921 // at zero (even if the first bits were zero).
922 if (BitGroups.empty())
923 LastGroupStartIdx = 0;
926 // If this bit has the same underlying value and the same rotate factor as
927 // the last one, then they're part of the same group.
928 if (ThisRLAmt == LastRLAmt && ThisValue == LastValue)
931 if (LastValue.getNode())
932 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
934 LastRLAmt = ThisRLAmt;
935 LastValue = ThisValue;
936 LastGroupStartIdx = i;
938 if (LastValue.getNode())
939 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
942 if (BitGroups.empty())
945 // We might be able to combine the first and last groups.
946 if (BitGroups.size() > 1) {
947 // If the first and last groups are the same, then remove the first group
948 // in favor of the last group, making the ending index of the last group
949 // equal to the ending index of the to-be-removed first group.
950 if (BitGroups[0].StartIdx == 0 &&
951 BitGroups[BitGroups.size()-1].EndIdx == Bits.size()-1 &&
952 BitGroups[0].V == BitGroups[BitGroups.size()-1].V &&
953 BitGroups[0].RLAmt == BitGroups[BitGroups.size()-1].RLAmt) {
954 DEBUG(dbgs() << "\tcombining final bit group with inital one\n");
955 BitGroups[BitGroups.size()-1].EndIdx = BitGroups[0].EndIdx;
956 BitGroups.erase(BitGroups.begin());
961 // Take all (SDValue, RLAmt) pairs and sort them by the number of groups
962 // associated with each. If there is a degeneracy, pick the one that occurs
963 // first (in the final value).
964 void collectValueRotInfo() {
967 for (auto &BG : BitGroups) {
968 unsigned RLAmtKey = BG.RLAmt + (BG.Repl32 ? 64 : 0);
969 ValueRotInfo &VRI = ValueRots[std::make_pair(BG.V, RLAmtKey)];
971 VRI.RLAmt = BG.RLAmt;
972 VRI.Repl32 = BG.Repl32;
974 VRI.FirstGroupStartIdx = std::min(VRI.FirstGroupStartIdx, BG.StartIdx);
977 // Now that we've collected the various ValueRotInfo instances, we need to
979 ValueRotsVec.clear();
980 for (auto &I : ValueRots) {
981 ValueRotsVec.push_back(I.second);
983 std::sort(ValueRotsVec.begin(), ValueRotsVec.end());
986 // In 64-bit mode, rlwinm and friends have a rotation operator that
987 // replicates the low-order 32 bits into the high-order 32-bits. The mask
988 // indices of these instructions can only be in the lower 32 bits, so they
989 // can only represent some 64-bit bit groups. However, when they can be used,
990 // the 32-bit replication can be used to represent, as a single bit group,
991 // otherwise separate bit groups. We'll convert to replicated-32-bit bit
992 // groups when possible. Returns true if any of the bit groups were
994 void assignRepl32BitGroups() {
995 // If we have bits like this:
997 // Indices: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
998 // V bits: ... 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24
999 // Groups: | RLAmt = 8 | RLAmt = 40 |
1001 // But, making use of a 32-bit operation that replicates the low-order 32
1002 // bits into the high-order 32 bits, this can be one bit group with a RLAmt
1005 auto IsAllLow32 = [this](BitGroup & BG) {
1006 if (BG.StartIdx <= BG.EndIdx) {
1007 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i) {
1008 if (!Bits[i].hasValue())
1010 if (Bits[i].getValueBitIndex() >= 32)
1014 for (unsigned i = BG.StartIdx; i < Bits.size(); ++i) {
1015 if (!Bits[i].hasValue())
1017 if (Bits[i].getValueBitIndex() >= 32)
1020 for (unsigned i = 0; i <= BG.EndIdx; ++i) {
1021 if (!Bits[i].hasValue())
1023 if (Bits[i].getValueBitIndex() >= 32)
1031 for (auto &BG : BitGroups) {
1032 if (BG.StartIdx < 32 && BG.EndIdx < 32) {
1033 if (IsAllLow32(BG)) {
1034 if (BG.RLAmt >= 32) {
1041 DEBUG(dbgs() << "\t32-bit replicated bit group for " <<
1042 BG.V.getNode() << " RLAmt = " << BG.RLAmt <<
1043 " [" << BG.StartIdx << ", " << BG.EndIdx << "]\n");
1048 // Now walk through the bit groups, consolidating where possible.
1049 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1050 // We might want to remove this bit group by merging it with the previous
1051 // group (which might be the ending group).
1052 auto IP = (I == BitGroups.begin()) ?
1053 std::prev(BitGroups.end()) : std::prev(I);
1054 if (I->Repl32 && IP->Repl32 && I->V == IP->V && I->RLAmt == IP->RLAmt &&
1055 I->StartIdx == (IP->EndIdx + 1) % 64 && I != IP) {
1057 DEBUG(dbgs() << "\tcombining 32-bit replicated bit group for " <<
1058 I->V.getNode() << " RLAmt = " << I->RLAmt <<
1059 " [" << I->StartIdx << ", " << I->EndIdx <<
1060 "] with group with range [" <<
1061 IP->StartIdx << ", " << IP->EndIdx << "]\n");
1063 IP->EndIdx = I->EndIdx;
1064 IP->Repl32CR = IP->Repl32CR || I->Repl32CR;
1065 IP->Repl32Coalesced = true;
1066 I = BitGroups.erase(I);
1069 // There is a special case worth handling: If there is a single group
1070 // covering the entire upper 32 bits, and it can be merged with both
1071 // the next and previous groups (which might be the same group), then
1072 // do so. If it is the same group (so there will be only one group in
1073 // total), then we need to reverse the order of the range so that it
1074 // covers the entire 64 bits.
1075 if (I->StartIdx == 32 && I->EndIdx == 63) {
1076 assert(std::next(I) == BitGroups.end() &&
1077 "bit group ends at index 63 but there is another?");
1078 auto IN = BitGroups.begin();
1080 if (IP->Repl32 && IN->Repl32 && I->V == IP->V && I->V == IN->V &&
1081 (I->RLAmt % 32) == IP->RLAmt && (I->RLAmt % 32) == IN->RLAmt &&
1082 IP->EndIdx == 31 && IN->StartIdx == 0 && I != IP &&
1085 DEBUG(dbgs() << "\tcombining bit group for " <<
1086 I->V.getNode() << " RLAmt = " << I->RLAmt <<
1087 " [" << I->StartIdx << ", " << I->EndIdx <<
1088 "] with 32-bit replicated groups with ranges [" <<
1089 IP->StartIdx << ", " << IP->EndIdx << "] and [" <<
1090 IN->StartIdx << ", " << IN->EndIdx << "]\n");
1093 // There is only one other group; change it to cover the whole
1094 // range (backward, so that it can still be Repl32 but cover the
1095 // whole 64-bit range).
1098 IP->Repl32CR = IP->Repl32CR || I->RLAmt >= 32;
1099 IP->Repl32Coalesced = true;
1100 I = BitGroups.erase(I);
1102 // There are two separate groups, one before this group and one
1103 // after us (at the beginning). We're going to remove this group,
1104 // but also the group at the very beginning.
1105 IP->EndIdx = IN->EndIdx;
1106 IP->Repl32CR = IP->Repl32CR || IN->Repl32CR || I->RLAmt >= 32;
1107 IP->Repl32Coalesced = true;
1108 I = BitGroups.erase(I);
1109 BitGroups.erase(BitGroups.begin());
1112 // This must be the last group in the vector (and we might have
1113 // just invalidated the iterator above), so break here.
1123 SDValue getI32Imm(unsigned Imm) {
1124 return CurDAG->getTargetConstant(Imm, MVT::i32);
1127 uint64_t getZerosMask() {
1129 for (unsigned i = 0; i < Bits.size(); ++i) {
1130 if (Bits[i].hasValue())
1132 Mask |= (UINT64_C(1) << i);
1138 // Depending on the number of groups for a particular value, it might be
1139 // better to rotate, mask explicitly (using andi/andis), and then or the
1140 // result. Select this part of the result first.
1141 void SelectAndParts32(SDLoc dl, SDValue &Res, unsigned *InstCnt) {
1142 if (BPermRewriterNoMasking)
1145 for (ValueRotInfo &VRI : ValueRotsVec) {
1147 for (unsigned i = 0; i < Bits.size(); ++i) {
1148 if (!Bits[i].hasValue() || Bits[i].getValue() != VRI.V)
1150 if (RLAmt[i] != VRI.RLAmt)
1155 // Compute the masks for andi/andis that would be necessary.
1156 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1157 assert((ANDIMask != 0 || ANDISMask != 0) &&
1158 "No set bits in mask for value bit groups");
1159 bool NeedsRotate = VRI.RLAmt != 0;
1161 // We're trying to minimize the number of instructions. If we have one
1162 // group, using one of andi/andis can break even. If we have three
1163 // groups, we can use both andi and andis and break even (to use both
1164 // andi and andis we also need to or the results together). We need four
1165 // groups if we also need to rotate. To use andi/andis we need to do more
1166 // than break even because rotate-and-mask instructions tend to be easier
1169 // FIXME: We've biased here against using andi/andis, which is right for
1170 // POWER cores, but not optimal everywhere. For example, on the A2,
1171 // andi/andis have single-cycle latency whereas the rotate-and-mask
1172 // instructions take two cycles, and it would be better to bias toward
1173 // andi/andis in break-even cases.
1175 unsigned NumAndInsts = (unsigned) NeedsRotate +
1176 (unsigned) (ANDIMask != 0) +
1177 (unsigned) (ANDISMask != 0) +
1178 (unsigned) (ANDIMask != 0 && ANDISMask != 0) +
1179 (unsigned) (bool) Res;
1181 DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode() <<
1182 " RL: " << VRI.RLAmt << ":" <<
1183 "\n\t\t\tisel using masking: " << NumAndInsts <<
1184 " using rotates: " << VRI.NumGroups << "\n");
1186 if (NumAndInsts >= VRI.NumGroups)
1189 DEBUG(dbgs() << "\t\t\t\tusing masking\n");
1191 if (InstCnt) *InstCnt += NumAndInsts;
1196 { VRI.V, getI32Imm(VRI.RLAmt), getI32Imm(0), getI32Imm(31) };
1197 VRot = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
1203 SDValue ANDIVal, ANDISVal;
1205 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1206 VRot, getI32Imm(ANDIMask)), 0);
1208 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1209 VRot, getI32Imm(ANDISMask)), 0);
1213 TotalVal = ANDISVal;
1217 TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1218 ANDIVal, ANDISVal), 0);
1223 Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1226 // Now, remove all groups with this underlying value and rotation
1228 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1229 if (I->V == VRI.V && I->RLAmt == VRI.RLAmt)
1230 I = BitGroups.erase(I);
1237 // Instruction selection for the 32-bit case.
1238 SDNode *Select32(SDNode *N, bool LateMask, unsigned *InstCnt) {
1242 if (InstCnt) *InstCnt = 0;
1244 // Take care of cases that should use andi/andis first.
1245 SelectAndParts32(dl, Res, InstCnt);
1247 // If we've not yet selected a 'starting' instruction, and we have no zeros
1248 // to fill in, select the (Value, RLAmt) with the highest priority (largest
1249 // number of groups), and start with this rotated value.
1250 if ((!HasZeros || LateMask) && !Res) {
1251 ValueRotInfo &VRI = ValueRotsVec[0];
1253 if (InstCnt) *InstCnt += 1;
1255 { VRI.V, getI32Imm(VRI.RLAmt), getI32Imm(0), getI32Imm(31) };
1256 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
1261 // Now, remove all groups with this underlying value and rotation factor.
1262 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1263 if (I->V == VRI.V && I->RLAmt == VRI.RLAmt)
1264 I = BitGroups.erase(I);
1270 if (InstCnt) *InstCnt += BitGroups.size();
1272 // Insert the other groups (one at a time).
1273 for (auto &BG : BitGroups) {
1276 { BG.V, getI32Imm(BG.RLAmt), getI32Imm(Bits.size() - BG.EndIdx - 1),
1277 getI32Imm(Bits.size() - BG.StartIdx - 1) };
1278 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
1281 { Res, BG.V, getI32Imm(BG.RLAmt), getI32Imm(Bits.size() - BG.EndIdx - 1),
1282 getI32Imm(Bits.size() - BG.StartIdx - 1) };
1283 Res = SDValue(CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops), 0);
1288 unsigned Mask = (unsigned) getZerosMask();
1290 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1291 assert((ANDIMask != 0 || ANDISMask != 0) &&
1292 "No set bits in zeros mask?");
1294 if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
1295 (unsigned) (ANDISMask != 0) +
1296 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1298 SDValue ANDIVal, ANDISVal;
1300 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1301 Res, getI32Imm(ANDIMask)), 0);
1303 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1304 Res, getI32Imm(ANDISMask)), 0);
1311 Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1312 ANDIVal, ANDISVal), 0);
1315 return Res.getNode();
1318 unsigned SelectRotMask64Count(unsigned RLAmt, bool Repl32,
1319 unsigned MaskStart, unsigned MaskEnd,
1321 // In the notation used by the instructions, 'start' and 'end' are reversed
1322 // because bits are counted from high to low order.
1323 unsigned InstMaskStart = 64 - MaskEnd - 1,
1324 InstMaskEnd = 64 - MaskStart - 1;
1329 if ((!IsIns && (InstMaskEnd == 63 || InstMaskStart == 0)) ||
1330 InstMaskEnd == 63 - RLAmt)
1336 // For 64-bit values, not all combinations of rotates and masks are
1337 // available. Produce one if it is available.
1338 SDValue SelectRotMask64(SDValue V, SDLoc dl, unsigned RLAmt, bool Repl32,
1339 unsigned MaskStart, unsigned MaskEnd,
1340 unsigned *InstCnt = nullptr) {
1341 // In the notation used by the instructions, 'start' and 'end' are reversed
1342 // because bits are counted from high to low order.
1343 unsigned InstMaskStart = 64 - MaskEnd - 1,
1344 InstMaskEnd = 64 - MaskStart - 1;
1346 if (InstCnt) *InstCnt += 1;
1349 // This rotation amount assumes that the lower 32 bits of the quantity
1350 // are replicated in the high 32 bits by the rotation operator (which is
1351 // done by rlwinm and friends).
1352 assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1353 assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1355 { V, getI32Imm(RLAmt), getI32Imm(InstMaskStart - 32),
1356 getI32Imm(InstMaskEnd - 32) };
1357 return SDValue(CurDAG->getMachineNode(PPC::RLWINM8, dl, MVT::i64,
1361 if (InstMaskEnd == 63) {
1363 { V, getI32Imm(RLAmt), getI32Imm(InstMaskStart) };
1364 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops), 0);
1367 if (InstMaskStart == 0) {
1369 { V, getI32Imm(RLAmt), getI32Imm(InstMaskEnd) };
1370 return SDValue(CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Ops), 0);
1373 if (InstMaskEnd == 63 - RLAmt) {
1375 { V, getI32Imm(RLAmt), getI32Imm(InstMaskStart) };
1376 return SDValue(CurDAG->getMachineNode(PPC::RLDIC, dl, MVT::i64, Ops), 0);
1379 // We cannot do this with a single instruction, so we'll use two. The
1380 // problem is that we're not free to choose both a rotation amount and mask
1381 // start and end independently. We can choose an arbitrary mask start and
1382 // end, but then the rotation amount is fixed. Rotation, however, can be
1383 // inverted, and so by applying an "inverse" rotation first, we can get the
1385 if (InstCnt) *InstCnt += 1;
1387 // The rotation mask for the second instruction must be MaskStart.
1388 unsigned RLAmt2 = MaskStart;
1389 // The first instruction must rotate V so that the overall rotation amount
1391 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1393 V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
1394 return SelectRotMask64(V, dl, RLAmt2, false, MaskStart, MaskEnd);
1397 // For 64-bit values, not all combinations of rotates and masks are
1398 // available. Produce a rotate-mask-and-insert if one is available.
1399 SDValue SelectRotMaskIns64(SDValue Base, SDValue V, SDLoc dl, unsigned RLAmt,
1400 bool Repl32, unsigned MaskStart,
1401 unsigned MaskEnd, unsigned *InstCnt = nullptr) {
1402 // In the notation used by the instructions, 'start' and 'end' are reversed
1403 // because bits are counted from high to low order.
1404 unsigned InstMaskStart = 64 - MaskEnd - 1,
1405 InstMaskEnd = 64 - MaskStart - 1;
1407 if (InstCnt) *InstCnt += 1;
1410 // This rotation amount assumes that the lower 32 bits of the quantity
1411 // are replicated in the high 32 bits by the rotation operator (which is
1412 // done by rlwinm and friends).
1413 assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1414 assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1416 { Base, V, getI32Imm(RLAmt), getI32Imm(InstMaskStart - 32),
1417 getI32Imm(InstMaskEnd - 32) };
1418 return SDValue(CurDAG->getMachineNode(PPC::RLWIMI8, dl, MVT::i64,
1422 if (InstMaskEnd == 63 - RLAmt) {
1424 { Base, V, getI32Imm(RLAmt), getI32Imm(InstMaskStart) };
1425 return SDValue(CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops), 0);
1428 // We cannot do this with a single instruction, so we'll use two. The
1429 // problem is that we're not free to choose both a rotation amount and mask
1430 // start and end independently. We can choose an arbitrary mask start and
1431 // end, but then the rotation amount is fixed. Rotation, however, can be
1432 // inverted, and so by applying an "inverse" rotation first, we can get the
1434 if (InstCnt) *InstCnt += 1;
1436 // The rotation mask for the second instruction must be MaskStart.
1437 unsigned RLAmt2 = MaskStart;
1438 // The first instruction must rotate V so that the overall rotation amount
1440 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1442 V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
1443 return SelectRotMaskIns64(Base, V, dl, RLAmt2, false, MaskStart, MaskEnd);
1446 void SelectAndParts64(SDLoc dl, SDValue &Res, unsigned *InstCnt) {
1447 if (BPermRewriterNoMasking)
1450 // The idea here is the same as in the 32-bit version, but with additional
1451 // complications from the fact that Repl32 might be true. Because we
1452 // aggressively convert bit groups to Repl32 form (which, for small
1453 // rotation factors, involves no other change), and then coalesce, it might
1454 // be the case that a single 64-bit masking operation could handle both
1455 // some Repl32 groups and some non-Repl32 groups. If converting to Repl32
1456 // form allowed coalescing, then we must use a 32-bit rotaton in order to
1457 // completely capture the new combined bit group.
1459 for (ValueRotInfo &VRI : ValueRotsVec) {
1462 // We need to add to the mask all bits from the associated bit groups.
1463 // If Repl32 is false, we need to add bits from bit groups that have
1464 // Repl32 true, but are trivially convertable to Repl32 false. Such a
1465 // group is trivially convertable if it overlaps only with the lower 32
1466 // bits, and the group has not been coalesced.
1467 auto MatchingBG = [VRI](BitGroup &BG) {
1471 unsigned EffRLAmt = BG.RLAmt;
1472 if (!VRI.Repl32 && BG.Repl32) {
1473 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx <= BG.EndIdx &&
1474 !BG.Repl32Coalesced) {
1480 } else if (VRI.Repl32 != BG.Repl32) {
1484 if (VRI.RLAmt != EffRLAmt)
1490 for (auto &BG : BitGroups) {
1491 if (!MatchingBG(BG))
1494 if (BG.StartIdx <= BG.EndIdx) {
1495 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i)
1496 Mask |= (UINT64_C(1) << i);
1498 for (unsigned i = BG.StartIdx; i < Bits.size(); ++i)
1499 Mask |= (UINT64_C(1) << i);
1500 for (unsigned i = 0; i <= BG.EndIdx; ++i)
1501 Mask |= (UINT64_C(1) << i);
1505 // We can use the 32-bit andi/andis technique if the mask does not
1506 // require any higher-order bits. This can save an instruction compared
1507 // to always using the general 64-bit technique.
1508 bool Use32BitInsts = isUInt<32>(Mask);
1509 // Compute the masks for andi/andis that would be necessary.
1510 unsigned ANDIMask = (Mask & UINT16_MAX),
1511 ANDISMask = (Mask >> 16) & UINT16_MAX;
1513 bool NeedsRotate = VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask));
1515 unsigned NumAndInsts = (unsigned) NeedsRotate +
1516 (unsigned) (bool) Res;
1518 NumAndInsts += (unsigned) (ANDIMask != 0) + (unsigned) (ANDISMask != 0) +
1519 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1521 NumAndInsts += SelectInt64Count(Mask) + /* and */ 1;
1523 unsigned NumRLInsts = 0;
1524 bool FirstBG = true;
1525 for (auto &BG : BitGroups) {
1526 if (!MatchingBG(BG))
1529 SelectRotMask64Count(BG.RLAmt, BG.Repl32, BG.StartIdx, BG.EndIdx,
1534 DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode() <<
1535 " RL: " << VRI.RLAmt << (VRI.Repl32 ? " (32):" : ":") <<
1536 "\n\t\t\tisel using masking: " << NumAndInsts <<
1537 " using rotates: " << NumRLInsts << "\n");
1539 // When we'd use andi/andis, we bias toward using the rotates (andi only
1540 // has a record form, and is cracked on POWER cores). However, when using
1541 // general 64-bit constant formation, bias toward the constant form,
1542 // because that exposes more opportunities for CSE.
1543 if (NumAndInsts > NumRLInsts)
1545 if (Use32BitInsts && NumAndInsts == NumRLInsts)
1548 DEBUG(dbgs() << "\t\t\t\tusing masking\n");
1550 if (InstCnt) *InstCnt += NumAndInsts;
1553 // We actually need to generate a rotation if we have a non-zero rotation
1554 // factor or, in the Repl32 case, if we care about any of the
1555 // higher-order replicated bits. In the latter case, we generate a mask
1556 // backward so that it actually includes the entire 64 bits.
1557 if (VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask)))
1558 VRot = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
1559 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63);
1564 if (Use32BitInsts) {
1565 assert((ANDIMask != 0 || ANDISMask != 0) &&
1566 "No set bits in mask when using 32-bit ands for 64-bit value");
1568 SDValue ANDIVal, ANDISVal;
1570 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
1571 VRot, getI32Imm(ANDIMask)), 0);
1573 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
1574 VRot, getI32Imm(ANDISMask)), 0);
1577 TotalVal = ANDISVal;
1581 TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1582 ANDIVal, ANDISVal), 0);
1584 TotalVal = SDValue(SelectInt64(CurDAG, dl, Mask), 0);
1586 SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
1587 VRot, TotalVal), 0);
1593 Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1596 // Now, remove all groups with this underlying value and rotation
1598 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1600 I = BitGroups.erase(I);
1607 // Instruction selection for the 64-bit case.
1608 SDNode *Select64(SDNode *N, bool LateMask, unsigned *InstCnt) {
1612 if (InstCnt) *InstCnt = 0;
1614 // Take care of cases that should use andi/andis first.
1615 SelectAndParts64(dl, Res, InstCnt);
1617 // If we've not yet selected a 'starting' instruction, and we have no zeros
1618 // to fill in, select the (Value, RLAmt) with the highest priority (largest
1619 // number of groups), and start with this rotated value.
1620 if ((!HasZeros || LateMask) && !Res) {
1621 // If we have both Repl32 groups and non-Repl32 groups, the non-Repl32
1622 // groups will come first, and so the VRI representing the largest number
1623 // of groups might not be first (it might be the first Repl32 groups).
1624 unsigned MaxGroupsIdx = 0;
1625 if (!ValueRotsVec[0].Repl32) {
1626 for (unsigned i = 0, ie = ValueRotsVec.size(); i < ie; ++i)
1627 if (ValueRotsVec[i].Repl32) {
1628 if (ValueRotsVec[i].NumGroups > ValueRotsVec[0].NumGroups)
1634 ValueRotInfo &VRI = ValueRotsVec[MaxGroupsIdx];
1635 bool NeedsRotate = false;
1638 } else if (VRI.Repl32) {
1639 for (auto &BG : BitGroups) {
1640 if (BG.V != VRI.V || BG.RLAmt != VRI.RLAmt ||
1641 BG.Repl32 != VRI.Repl32)
1644 // We don't need a rotate if the bit group is confined to the lower
1646 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx < BG.EndIdx)
1655 Res = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
1656 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63,
1661 // Now, remove all groups with this underlying value and rotation factor.
1663 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1664 if (I->V == VRI.V && I->RLAmt == VRI.RLAmt && I->Repl32 == VRI.Repl32)
1665 I = BitGroups.erase(I);
1671 // Because 64-bit rotates are more flexible than inserts, we might have a
1672 // preference regarding which one we do first (to save one instruction).
1674 for (auto I = BitGroups.begin(), IE = BitGroups.end(); I != IE; ++I) {
1675 if (SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
1677 SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
1679 if (I != BitGroups.begin()) {
1682 BitGroups.insert(BitGroups.begin(), BG);
1689 // Insert the other groups (one at a time).
1690 for (auto &BG : BitGroups) {
1692 Res = SelectRotMask64(BG.V, dl, BG.RLAmt, BG.Repl32, BG.StartIdx,
1693 BG.EndIdx, InstCnt);
1695 Res = SelectRotMaskIns64(Res, BG.V, dl, BG.RLAmt, BG.Repl32,
1696 BG.StartIdx, BG.EndIdx, InstCnt);
1700 uint64_t Mask = getZerosMask();
1702 // We can use the 32-bit andi/andis technique if the mask does not
1703 // require any higher-order bits. This can save an instruction compared
1704 // to always using the general 64-bit technique.
1705 bool Use32BitInsts = isUInt<32>(Mask);
1706 // Compute the masks for andi/andis that would be necessary.
1707 unsigned ANDIMask = (Mask & UINT16_MAX),
1708 ANDISMask = (Mask >> 16) & UINT16_MAX;
1710 if (Use32BitInsts) {
1711 assert((ANDIMask != 0 || ANDISMask != 0) &&
1712 "No set bits in mask when using 32-bit ands for 64-bit value");
1714 if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
1715 (unsigned) (ANDISMask != 0) +
1716 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1718 SDValue ANDIVal, ANDISVal;
1720 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
1721 Res, getI32Imm(ANDIMask)), 0);
1723 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
1724 Res, getI32Imm(ANDISMask)), 0);
1731 Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1732 ANDIVal, ANDISVal), 0);
1734 if (InstCnt) *InstCnt += SelectInt64Count(Mask) + /* and */ 1;
1736 SDValue MaskVal = SDValue(SelectInt64(CurDAG, dl, Mask), 0);
1738 SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
1743 return Res.getNode();
1746 SDNode *Select(SDNode *N, bool LateMask, unsigned *InstCnt = nullptr) {
1747 // Fill in BitGroups.
1748 collectBitGroups(LateMask);
1749 if (BitGroups.empty())
1752 // For 64-bit values, figure out when we can use 32-bit instructions.
1753 if (Bits.size() == 64)
1754 assignRepl32BitGroups();
1756 // Fill in ValueRotsVec.
1757 collectValueRotInfo();
1759 if (Bits.size() == 32) {
1760 return Select32(N, LateMask, InstCnt);
1762 assert(Bits.size() == 64 && "Not 64 bits here?");
1763 return Select64(N, LateMask, InstCnt);
1769 SmallVector<ValueBit, 64> Bits;
1772 SmallVector<unsigned, 64> RLAmt;
1774 SmallVector<BitGroup, 16> BitGroups;
1776 DenseMap<std::pair<SDValue, unsigned>, ValueRotInfo> ValueRots;
1777 SmallVector<ValueRotInfo, 16> ValueRotsVec;
1779 SelectionDAG *CurDAG;
1782 BitPermutationSelector(SelectionDAG *DAG)
1785 // Here we try to match complex bit permutations into a set of
1786 // rotate-and-shift/shift/and/or instructions, using a set of heuristics
1787 // known to produce optimial code for common cases (like i32 byte swapping).
1788 SDNode *Select(SDNode *N) {
1789 Bits.resize(N->getValueType(0).getSizeInBits());
1790 if (!getValueBits(SDValue(N, 0), Bits))
1793 DEBUG(dbgs() << "Considering bit-permutation-based instruction"
1794 " selection for: ");
1795 DEBUG(N->dump(CurDAG));
1797 // Fill it RLAmt and set HasZeros.
1798 computeRotationAmounts();
1801 return Select(N, false);
1803 // We currently have two techniques for handling results with zeros: early
1804 // masking (the default) and late masking. Late masking is sometimes more
1805 // efficient, but because the structure of the bit groups is different, it
1806 // is hard to tell without generating both and comparing the results. With
1807 // late masking, we ignore zeros in the resulting value when inserting each
1808 // set of bit groups, and then mask in the zeros at the end. With early
1809 // masking, we only insert the non-zero parts of the result at every step.
1811 unsigned InstCnt, InstCntLateMask;
1812 DEBUG(dbgs() << "\tEarly masking:\n");
1813 SDNode *RN = Select(N, false, &InstCnt);
1814 DEBUG(dbgs() << "\t\tisel would use " << InstCnt << " instructions\n");
1816 DEBUG(dbgs() << "\tLate masking:\n");
1817 SDNode *RNLM = Select(N, true, &InstCntLateMask);
1818 DEBUG(dbgs() << "\t\tisel would use " << InstCntLateMask <<
1821 if (InstCnt <= InstCntLateMask) {
1822 DEBUG(dbgs() << "\tUsing early-masking for isel\n");
1826 DEBUG(dbgs() << "\tUsing late-masking for isel\n");
1830 } // anonymous namespace
1832 SDNode *PPCDAGToDAGISel::SelectBitPermutation(SDNode *N) {
1833 if (N->getValueType(0) != MVT::i32 &&
1834 N->getValueType(0) != MVT::i64)
1837 if (!UseBitPermRewriter)
1840 switch (N->getOpcode()) {
1847 BitPermutationSelector BPS(CurDAG);
1848 return BPS.Select(N);
1855 /// SelectCC - Select a comparison of the specified values with the specified
1856 /// condition code, returning the CR# of the expression.
1857 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
1858 ISD::CondCode CC, SDLoc dl) {
1859 // Always select the LHS.
1862 if (LHS.getValueType() == MVT::i32) {
1864 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1865 if (isInt32Immediate(RHS, Imm)) {
1866 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
1867 if (isUInt<16>(Imm))
1868 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
1869 getI32Imm(Imm & 0xFFFF)), 0);
1870 // If this is a 16-bit signed immediate, fold it.
1871 if (isInt<16>((int)Imm))
1872 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
1873 getI32Imm(Imm & 0xFFFF)), 0);
1875 // For non-equality comparisons, the default code would materialize the
1876 // constant, then compare against it, like this:
1878 // ori r2, r2, 22136
1880 // Since we are just comparing for equality, we can emit this instead:
1881 // xoris r0,r3,0x1234
1882 // cmplwi cr0,r0,0x5678
1884 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
1885 getI32Imm(Imm >> 16)), 0);
1886 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
1887 getI32Imm(Imm & 0xFFFF)), 0);
1890 } else if (ISD::isUnsignedIntSetCC(CC)) {
1891 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
1892 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
1893 getI32Imm(Imm & 0xFFFF)), 0);
1897 if (isIntS16Immediate(RHS, SImm))
1898 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
1899 getI32Imm((int)SImm & 0xFFFF)),
1903 } else if (LHS.getValueType() == MVT::i64) {
1905 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1906 if (isInt64Immediate(RHS.getNode(), Imm)) {
1907 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
1908 if (isUInt<16>(Imm))
1909 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
1910 getI32Imm(Imm & 0xFFFF)), 0);
1911 // If this is a 16-bit signed immediate, fold it.
1913 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
1914 getI32Imm(Imm & 0xFFFF)), 0);
1916 // For non-equality comparisons, the default code would materialize the
1917 // constant, then compare against it, like this:
1919 // ori r2, r2, 22136
1921 // Since we are just comparing for equality, we can emit this instead:
1922 // xoris r0,r3,0x1234
1923 // cmpldi cr0,r0,0x5678
1925 if (isUInt<32>(Imm)) {
1926 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
1927 getI64Imm(Imm >> 16)), 0);
1928 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
1929 getI64Imm(Imm & 0xFFFF)), 0);
1933 } else if (ISD::isUnsignedIntSetCC(CC)) {
1934 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
1935 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
1936 getI64Imm(Imm & 0xFFFF)), 0);
1940 if (isIntS16Immediate(RHS, SImm))
1941 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
1942 getI64Imm(SImm & 0xFFFF)),
1946 } else if (LHS.getValueType() == MVT::f32) {
1949 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
1950 Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
1952 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
1955 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
1961 llvm_unreachable("Should be lowered by legalize!");
1962 default: llvm_unreachable("Unknown condition!");
1964 case ISD::SETEQ: return PPC::PRED_EQ;
1966 case ISD::SETNE: return PPC::PRED_NE;
1968 case ISD::SETLT: return PPC::PRED_LT;
1970 case ISD::SETLE: return PPC::PRED_LE;
1972 case ISD::SETGT: return PPC::PRED_GT;
1974 case ISD::SETGE: return PPC::PRED_GE;
1975 case ISD::SETO: return PPC::PRED_NU;
1976 case ISD::SETUO: return PPC::PRED_UN;
1977 // These two are invalid for floating point. Assume we have int.
1978 case ISD::SETULT: return PPC::PRED_LT;
1979 case ISD::SETUGT: return PPC::PRED_GT;
1983 /// getCRIdxForSetCC - Return the index of the condition register field
1984 /// associated with the SetCC condition, and whether or not the field is
1985 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
1986 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
1989 default: llvm_unreachable("Unknown condition!");
1991 case ISD::SETLT: return 0; // Bit #0 = SETOLT
1993 case ISD::SETGT: return 1; // Bit #1 = SETOGT
1995 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
1996 case ISD::SETUO: return 3; // Bit #3 = SETUO
1998 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
2000 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
2002 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
2003 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
2008 llvm_unreachable("Invalid branch code: should be expanded by legalize");
2009 // These are invalid for floating point. Assume integer.
2010 case ISD::SETULT: return 0;
2011 case ISD::SETUGT: return 1;
2015 // getVCmpInst: return the vector compare instruction for the specified
2016 // vector type and condition code. Since this is for altivec specific code,
2017 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
2018 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC,
2019 bool HasVSX, bool &Swap, bool &Negate) {
2023 if (VecVT.isFloatingPoint()) {
2024 /* Handle some cases by swapping input operands. */
2026 case ISD::SETLE: CC = ISD::SETGE; Swap = true; break;
2027 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
2028 case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break;
2029 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break;
2030 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
2031 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break;
2034 /* Handle some cases by negating the result. */
2036 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
2037 case ISD::SETUNE: CC = ISD::SETOEQ; Negate = true; break;
2038 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break;
2039 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break;
2042 /* We have instructions implementing the remaining cases. */
2046 if (VecVT == MVT::v4f32)
2047 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
2048 else if (VecVT == MVT::v2f64)
2049 return PPC::XVCMPEQDP;
2053 if (VecVT == MVT::v4f32)
2054 return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
2055 else if (VecVT == MVT::v2f64)
2056 return PPC::XVCMPGTDP;
2060 if (VecVT == MVT::v4f32)
2061 return HasVSX ? PPC::XVCMPGESP : PPC::VCMPGEFP;
2062 else if (VecVT == MVT::v2f64)
2063 return PPC::XVCMPGEDP;
2068 llvm_unreachable("Invalid floating-point vector compare condition");
2070 /* Handle some cases by swapping input operands. */
2072 case ISD::SETGE: CC = ISD::SETLE; Swap = true; break;
2073 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
2074 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
2075 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break;
2078 /* Handle some cases by negating the result. */
2080 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
2081 case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break;
2082 case ISD::SETLE: CC = ISD::SETGT; Negate = true; break;
2083 case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break;
2086 /* We have instructions implementing the remaining cases. */
2090 if (VecVT == MVT::v16i8)
2091 return PPC::VCMPEQUB;
2092 else if (VecVT == MVT::v8i16)
2093 return PPC::VCMPEQUH;
2094 else if (VecVT == MVT::v4i32)
2095 return PPC::VCMPEQUW;
2098 if (VecVT == MVT::v16i8)
2099 return PPC::VCMPGTSB;
2100 else if (VecVT == MVT::v8i16)
2101 return PPC::VCMPGTSH;
2102 else if (VecVT == MVT::v4i32)
2103 return PPC::VCMPGTSW;
2106 if (VecVT == MVT::v16i8)
2107 return PPC::VCMPGTUB;
2108 else if (VecVT == MVT::v8i16)
2109 return PPC::VCMPGTUH;
2110 else if (VecVT == MVT::v4i32)
2111 return PPC::VCMPGTUW;
2116 llvm_unreachable("Invalid integer vector compare condition");
2120 SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
2123 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
2124 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
2125 bool isPPC64 = (PtrVT == MVT::i64);
2127 if (!PPCSubTarget->useCRBits() &&
2128 isInt32Immediate(N->getOperand(1), Imm)) {
2129 // We can codegen setcc op, imm very efficiently compared to a brcond.
2130 // Check for those cases here.
2133 SDValue Op = N->getOperand(0);
2137 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
2138 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
2139 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2144 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2145 Op, getI32Imm(~0U)), 0);
2146 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
2150 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2151 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2155 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
2156 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
2157 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2158 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2161 } else if (Imm == ~0U) { // setcc op, -1
2162 SDValue Op = N->getOperand(0);
2167 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2168 Op, getI32Imm(1)), 0);
2169 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
2170 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
2176 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
2177 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2178 Op, getI32Imm(~0U));
2179 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
2180 Op, SDValue(AD, 1));
2183 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
2185 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
2187 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2188 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2191 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2192 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops),
2194 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
2201 SDValue LHS = N->getOperand(0);
2202 SDValue RHS = N->getOperand(1);
2204 // Altivec Vector compare instructions do not set any CR register by default and
2205 // vector compare operations return the same type as the operands.
2206 if (LHS.getValueType().isVector()) {
2207 EVT VecVT = LHS.getValueType();
2209 unsigned int VCmpInst = getVCmpInst(VecVT.getSimpleVT(), CC,
2210 PPCSubTarget->hasVSX(), Swap, Negate);
2212 std::swap(LHS, RHS);
2215 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
2216 return CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR :
2221 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
2224 if (PPCSubTarget->useCRBits())
2228 unsigned Idx = getCRIdxForSetCC(CC, Inv);
2229 SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
2232 // Force the ccreg into CR7.
2233 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
2235 SDValue InFlag(nullptr, 0); // Null incoming flag value.
2236 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
2237 InFlag).getValue(1);
2239 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
2242 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
2243 getI32Imm(31), getI32Imm(31) };
2245 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2247 // Get the specified bit.
2249 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
2250 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
2254 // Select - Convert the specified operand from a target-independent to a
2255 // target-specific node if it hasn't already been changed.
2256 SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
2258 if (N->isMachineOpcode()) {
2260 return nullptr; // Already selected.
2263 // In case any misguided DAG-level optimizations form an ADD with a
2264 // TargetConstant operand, crash here instead of miscompiling (by selecting
2265 // an r+r add instead of some kind of r+i add).
2266 if (N->getOpcode() == ISD::ADD &&
2267 N->getOperand(1).getOpcode() == ISD::TargetConstant)
2268 llvm_unreachable("Invalid ADD with TargetConstant operand");
2270 // Try matching complex bit permutations before doing anything else.
2271 if (SDNode *NN = SelectBitPermutation(N))
2274 switch (N->getOpcode()) {
2277 case ISD::Constant: {
2278 if (N->getValueType(0) == MVT::i64)
2279 return SelectInt64(CurDAG, N);
2284 SDNode *SN = SelectSETCC(N);
2289 case PPCISD::GlobalBaseReg:
2290 return getGlobalBaseReg();
2292 case ISD::FrameIndex:
2293 return getFrameIndex(N, N);
2295 case PPCISD::MFOCRF: {
2296 SDValue InFlag = N->getOperand(1);
2297 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
2298 N->getOperand(0), InFlag);
2301 case PPCISD::READ_TIME_BASE: {
2302 return CurDAG->getMachineNode(PPC::ReadTB, dl, MVT::i32, MVT::i32,
2303 MVT::Other, N->getOperand(0));
2306 case PPCISD::SRA_ADDZE: {
2307 SDValue N0 = N->getOperand(0);
2309 CurDAG->getTargetConstant(*cast<ConstantSDNode>(N->getOperand(1))->
2310 getConstantIntValue(), N->getValueType(0));
2311 if (N->getValueType(0) == MVT::i64) {
2313 CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, MVT::Glue,
2315 return CurDAG->SelectNodeTo(N, PPC::ADDZE8, MVT::i64,
2316 SDValue(Op, 0), SDValue(Op, 1));
2318 assert(N->getValueType(0) == MVT::i32 &&
2319 "Expecting i64 or i32 in PPCISD::SRA_ADDZE");
2321 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
2323 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
2324 SDValue(Op, 0), SDValue(Op, 1));
2329 // Handle preincrement loads.
2330 LoadSDNode *LD = cast<LoadSDNode>(N);
2331 EVT LoadedVT = LD->getMemoryVT();
2333 // Normal loads are handled by code generated from the .td file.
2334 if (LD->getAddressingMode() != ISD::PRE_INC)
2337 SDValue Offset = LD->getOffset();
2338 if (Offset.getOpcode() == ISD::TargetConstant ||
2339 Offset.getOpcode() == ISD::TargetGlobalAddress) {
2342 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
2343 if (LD->getValueType(0) != MVT::i64) {
2344 // Handle PPC32 integer and normal FP loads.
2345 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
2346 switch (LoadedVT.getSimpleVT().SimpleTy) {
2347 default: llvm_unreachable("Invalid PPC load type!");
2348 case MVT::f64: Opcode = PPC::LFDU; break;
2349 case MVT::f32: Opcode = PPC::LFSU; break;
2350 case MVT::i32: Opcode = PPC::LWZU; break;
2351 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
2353 case MVT::i8: Opcode = PPC::LBZU; break;
2356 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
2357 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
2358 switch (LoadedVT.getSimpleVT().SimpleTy) {
2359 default: llvm_unreachable("Invalid PPC load type!");
2360 case MVT::i64: Opcode = PPC::LDU; break;
2361 case MVT::i32: Opcode = PPC::LWZU8; break;
2362 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
2364 case MVT::i8: Opcode = PPC::LBZU8; break;
2368 SDValue Chain = LD->getChain();
2369 SDValue Base = LD->getBasePtr();
2370 SDValue Ops[] = { Offset, Base, Chain };
2371 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
2372 PPCLowering->getPointerTy(),
2376 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
2377 if (LD->getValueType(0) != MVT::i64) {
2378 // Handle PPC32 integer and normal FP loads.
2379 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
2380 switch (LoadedVT.getSimpleVT().SimpleTy) {
2381 default: llvm_unreachable("Invalid PPC load type!");
2382 case MVT::f64: Opcode = PPC::LFDUX; break;
2383 case MVT::f32: Opcode = PPC::LFSUX; break;
2384 case MVT::i32: Opcode = PPC::LWZUX; break;
2385 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
2387 case MVT::i8: Opcode = PPC::LBZUX; break;
2390 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
2391 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) &&
2392 "Invalid sext update load");
2393 switch (LoadedVT.getSimpleVT().SimpleTy) {
2394 default: llvm_unreachable("Invalid PPC load type!");
2395 case MVT::i64: Opcode = PPC::LDUX; break;
2396 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
2397 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
2399 case MVT::i8: Opcode = PPC::LBZUX8; break;
2403 SDValue Chain = LD->getChain();
2404 SDValue Base = LD->getBasePtr();
2405 SDValue Ops[] = { Base, Offset, Chain };
2406 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
2407 PPCLowering->getPointerTy(),
2413 unsigned Imm, Imm2, SH, MB, ME;
2416 // If this is an and of a value rotated between 0 and 31 bits and then and'd
2417 // with a mask, emit rlwinm
2418 if (isInt32Immediate(N->getOperand(1), Imm) &&
2419 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
2420 SDValue Val = N->getOperand(0).getOperand(0);
2421 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
2422 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2424 // If this is just a masked value where the input is not handled above, and
2425 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
2426 if (isInt32Immediate(N->getOperand(1), Imm) &&
2427 isRunOfOnes(Imm, MB, ME) &&
2428 N->getOperand(0).getOpcode() != ISD::ROTL) {
2429 SDValue Val = N->getOperand(0);
2430 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
2431 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2433 // If this is a 64-bit zero-extension mask, emit rldicl.
2434 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
2436 SDValue Val = N->getOperand(0);
2437 MB = 64 - CountTrailingOnes_64(Imm64);
2440 // If the operand is a logical right shift, we can fold it into this
2441 // instruction: rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb)
2442 // for n <= mb. The right shift is really a left rotate followed by a
2443 // mask, and this mask is a more-restrictive sub-mask of the mask implied
2445 if (Val.getOpcode() == ISD::SRL &&
2446 isInt32Immediate(Val.getOperand(1).getNode(), Imm) && Imm <= MB) {
2447 assert(Imm < 64 && "Illegal shift amount");
2448 Val = Val.getOperand(0);
2452 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB) };
2453 return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
2455 // AND X, 0 -> 0, not "rlwinm 32".
2456 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
2457 ReplaceUses(SDValue(N, 0), N->getOperand(1));
2460 // ISD::OR doesn't get all the bitfield insertion fun.
2461 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
2462 if (isInt32Immediate(N->getOperand(1), Imm) &&
2463 N->getOperand(0).getOpcode() == ISD::OR &&
2464 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
2467 if (isRunOfOnes(Imm, MB, ME)) {
2468 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2469 N->getOperand(0).getOperand(1),
2470 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
2471 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
2475 // Other cases are autogenerated.
2479 if (N->getValueType(0) == MVT::i32)
2480 if (SDNode *I = SelectBitfieldInsert(N))
2484 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
2485 isIntS16Immediate(N->getOperand(1), Imm)) {
2486 APInt LHSKnownZero, LHSKnownOne;
2487 CurDAG->computeKnownBits(N->getOperand(0), LHSKnownZero, LHSKnownOne);
2489 // If this is equivalent to an add, then we can fold it with the
2490 // FrameIndex calculation.
2491 if ((LHSKnownZero.getZExtValue()|~(uint64_t)Imm) == ~0ULL)
2492 return getFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
2495 // Other cases are autogenerated.
2500 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
2501 isIntS16Immediate(N->getOperand(1), Imm))
2502 return getFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
2507 unsigned Imm, SH, MB, ME;
2508 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
2509 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
2510 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2511 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
2512 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2515 // Other cases are autogenerated.
2519 unsigned Imm, SH, MB, ME;
2520 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
2521 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
2522 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2523 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
2524 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2527 // Other cases are autogenerated.
2530 // FIXME: Remove this once the ANDI glue bug is fixed:
2531 case PPCISD::ANDIo_1_EQ_BIT:
2532 case PPCISD::ANDIo_1_GT_BIT: {
2536 EVT InVT = N->getOperand(0).getValueType();
2537 assert((InVT == MVT::i64 || InVT == MVT::i32) &&
2538 "Invalid input type for ANDIo_1_EQ_BIT");
2540 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
2541 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
2543 CurDAG->getTargetConstant(1, InVT)), 0);
2544 SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
2546 CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
2547 PPC::sub_eq : PPC::sub_gt, MVT::i32);
2549 return CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1,
2551 SDValue(AndI.getNode(), 1) /* glue */);
2553 case ISD::SELECT_CC: {
2554 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
2555 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
2556 bool isPPC64 = (PtrVT == MVT::i64);
2558 // If this is a select of i1 operands, we'll pattern match it.
2559 if (PPCSubTarget->useCRBits() &&
2560 N->getOperand(0).getValueType() == MVT::i1)
2563 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
2565 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2566 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
2567 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
2568 if (N1C->isNullValue() && N3C->isNullValue() &&
2569 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
2570 // FIXME: Implement this optzn for PPC64.
2571 N->getValueType(0) == MVT::i32) {
2573 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2574 N->getOperand(0), getI32Imm(~0U));
2575 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
2576 SDValue(Tmp, 0), N->getOperand(0),
2580 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
2582 if (N->getValueType(0) == MVT::i1) {
2583 // An i1 select is: (c & t) | (!c & f).
2585 unsigned Idx = getCRIdxForSetCC(CC, Inv);
2589 default: llvm_unreachable("Invalid CC index");
2590 case 0: SRI = PPC::sub_lt; break;
2591 case 1: SRI = PPC::sub_gt; break;
2592 case 2: SRI = PPC::sub_eq; break;
2593 case 3: SRI = PPC::sub_un; break;
2596 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg);
2598 SDValue NotCCBit(CurDAG->getMachineNode(PPC::CRNOR, dl, MVT::i1,
2600 SDValue C = Inv ? NotCCBit : CCBit,
2601 NotC = Inv ? CCBit : NotCCBit;
2603 SDValue CAndT(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
2604 C, N->getOperand(2)), 0);
2605 SDValue NotCAndF(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
2606 NotC, N->getOperand(3)), 0);
2608 return CurDAG->SelectNodeTo(N, PPC::CROR, MVT::i1, CAndT, NotCAndF);
2611 unsigned BROpc = getPredicateForSetCC(CC);
2613 unsigned SelectCCOp;
2614 if (N->getValueType(0) == MVT::i32)
2615 SelectCCOp = PPC::SELECT_CC_I4;
2616 else if (N->getValueType(0) == MVT::i64)
2617 SelectCCOp = PPC::SELECT_CC_I8;
2618 else if (N->getValueType(0) == MVT::f32)
2619 SelectCCOp = PPC::SELECT_CC_F4;
2620 else if (N->getValueType(0) == MVT::f64)
2621 if (PPCSubTarget->hasVSX())
2622 SelectCCOp = PPC::SELECT_CC_VSFRC;
2624 SelectCCOp = PPC::SELECT_CC_F8;
2625 else if (N->getValueType(0) == MVT::v2f64 ||
2626 N->getValueType(0) == MVT::v2i64)
2627 SelectCCOp = PPC::SELECT_CC_VSRC;
2629 SelectCCOp = PPC::SELECT_CC_VRRC;
2631 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
2633 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
2636 if (PPCSubTarget->hasVSX()) {
2637 SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) };
2638 return CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops);
2642 case ISD::VECTOR_SHUFFLE:
2643 if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
2644 N->getValueType(0) == MVT::v2i64)) {
2645 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
2647 SDValue Op1 = N->getOperand(SVN->getMaskElt(0) < 2 ? 0 : 1),
2648 Op2 = N->getOperand(SVN->getMaskElt(1) < 2 ? 0 : 1);
2651 for (int i = 0; i < 2; ++i)
2652 if (SVN->getMaskElt(i) <= 0 || SVN->getMaskElt(i) == 2)
2657 // For little endian, we must swap the input operands and adjust
2658 // the mask elements (reverse and invert them).
2659 if (PPCSubTarget->isLittleEndian()) {
2660 std::swap(Op1, Op2);
2661 unsigned tmp = DM[0];
2666 SDValue DMV = CurDAG->getTargetConstant(DM[1] | (DM[0] << 1), MVT::i32);
2668 if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 &&
2669 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
2670 isa<LoadSDNode>(Op1.getOperand(0))) {
2671 LoadSDNode *LD = cast<LoadSDNode>(Op1.getOperand(0));
2672 SDValue Base, Offset;
2674 if (LD->isUnindexed() &&
2675 SelectAddrIdxOnly(LD->getBasePtr(), Base, Offset)) {
2676 SDValue Chain = LD->getChain();
2677 SDValue Ops[] = { Base, Offset, Chain };
2678 return CurDAG->SelectNodeTo(N, PPC::LXVDSX,
2679 N->getValueType(0), Ops);
2683 SDValue Ops[] = { Op1, Op2, DMV };
2684 return CurDAG->SelectNodeTo(N, PPC::XXPERMDI, N->getValueType(0), Ops);
2690 bool IsPPC64 = PPCSubTarget->isPPC64();
2691 SDValue Ops[] = { N->getOperand(1), N->getOperand(0) };
2692 return CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ ?
2693 (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
2694 (IsPPC64 ? PPC::BDZ8 : PPC::BDZ),
2697 case PPCISD::COND_BRANCH: {
2698 // Op #0 is the Chain.
2699 // Op #1 is the PPC::PRED_* number.
2701 // Op #3 is the Dest MBB
2702 // Op #4 is the Flag.
2703 // Prevent PPC::PRED_* from being selected into LI.
2705 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
2706 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
2707 N->getOperand(0), N->getOperand(4) };
2708 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
2711 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
2712 unsigned PCC = getPredicateForSetCC(CC);
2714 if (N->getOperand(2).getValueType() == MVT::i1) {
2718 default: llvm_unreachable("Unexpected Boolean-operand predicate");
2719 case PPC::PRED_LT: Opc = PPC::CRANDC; Swap = true; break;
2720 case PPC::PRED_LE: Opc = PPC::CRORC; Swap = true; break;
2721 case PPC::PRED_EQ: Opc = PPC::CREQV; Swap = false; break;
2722 case PPC::PRED_GE: Opc = PPC::CRORC; Swap = false; break;
2723 case PPC::PRED_GT: Opc = PPC::CRANDC; Swap = false; break;
2724 case PPC::PRED_NE: Opc = PPC::CRXOR; Swap = false; break;
2727 SDValue BitComp(CurDAG->getMachineNode(Opc, dl, MVT::i1,
2728 N->getOperand(Swap ? 3 : 2),
2729 N->getOperand(Swap ? 2 : 3)), 0);
2730 return CurDAG->SelectNodeTo(N, PPC::BC, MVT::Other,
2731 BitComp, N->getOperand(4), N->getOperand(0));
2734 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
2735 SDValue Ops[] = { getI32Imm(PCC), CondCode,
2736 N->getOperand(4), N->getOperand(0) };
2737 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
2740 // FIXME: Should custom lower this.
2741 SDValue Chain = N->getOperand(0);
2742 SDValue Target = N->getOperand(1);
2743 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
2744 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
2745 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
2747 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
2749 case PPCISD::TOC_ENTRY: {
2750 assert ((PPCSubTarget->isPPC64() || PPCSubTarget->isSVR4ABI()) &&
2751 "Only supported for 64-bit ABI and 32-bit SVR4");
2752 if (PPCSubTarget->isSVR4ABI() && !PPCSubTarget->isPPC64()) {
2753 SDValue GA = N->getOperand(0);
2754 return CurDAG->getMachineNode(PPC::LWZtoc, dl, MVT::i32, GA,
2758 // For medium and large code model, we generate two instructions as
2759 // described below. Otherwise we allow SelectCodeCommon to handle this,
2760 // selecting one of LDtoc, LDtocJTI, LDtocCPT, and LDtocBA.
2761 CodeModel::Model CModel = TM.getCodeModel();
2762 if (CModel != CodeModel::Medium && CModel != CodeModel::Large)
2765 // The first source operand is a TargetGlobalAddress or a TargetJumpTable.
2766 // If it is an externally defined symbol, a symbol with common linkage,
2767 // a non-local function address, or a jump table address, or if we are
2768 // generating code for large code model, we generate:
2769 // LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>))
2770 // Otherwise we generate:
2771 // ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>)
2772 SDValue GA = N->getOperand(0);
2773 SDValue TOCbase = N->getOperand(1);
2774 SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
2777 if (isa<JumpTableSDNode>(GA) || isa<BlockAddressSDNode>(GA) ||
2778 CModel == CodeModel::Large)
2779 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
2782 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) {
2783 const GlobalValue *GValue = G->getGlobal();
2784 if ((GValue->getType()->getElementType()->isFunctionTy() &&
2785 (GValue->isDeclaration() || GValue->isWeakForLinker())) ||
2786 GValue->isDeclaration() || GValue->hasCommonLinkage() ||
2787 GValue->hasAvailableExternallyLinkage())
2788 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
2792 return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
2793 SDValue(Tmp, 0), GA);
2795 case PPCISD::PPC32_PICGOT: {
2796 // Generate a PIC-safe GOT reference.
2797 assert(!PPCSubTarget->isPPC64() && PPCSubTarget->isSVR4ABI() &&
2798 "PPCISD::PPC32_PICGOT is only supported for 32-bit SVR4");
2799 return CurDAG->SelectNodeTo(N, PPC::PPC32PICGOT, PPCLowering->getPointerTy(), MVT::i32);
2801 case PPCISD::VADD_SPLAT: {
2802 // This expands into one of three sequences, depending on whether
2803 // the first operand is odd or even, positive or negative.
2804 assert(isa<ConstantSDNode>(N->getOperand(0)) &&
2805 isa<ConstantSDNode>(N->getOperand(1)) &&
2806 "Invalid operand on VADD_SPLAT!");
2808 int Elt = N->getConstantOperandVal(0);
2809 int EltSize = N->getConstantOperandVal(1);
2810 unsigned Opc1, Opc2, Opc3;
2814 Opc1 = PPC::VSPLTISB;
2815 Opc2 = PPC::VADDUBM;
2816 Opc3 = PPC::VSUBUBM;
2818 } else if (EltSize == 2) {
2819 Opc1 = PPC::VSPLTISH;
2820 Opc2 = PPC::VADDUHM;
2821 Opc3 = PPC::VSUBUHM;
2824 assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!");
2825 Opc1 = PPC::VSPLTISW;
2826 Opc2 = PPC::VADDUWM;
2827 Opc3 = PPC::VSUBUWM;
2831 if ((Elt & 1) == 0) {
2832 // Elt is even, in the range [-32,-18] + [16,30].
2834 // Convert: VADD_SPLAT elt, size
2835 // Into: tmp = VSPLTIS[BHW] elt
2836 // VADDU[BHW]M tmp, tmp
2837 // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4
2838 SDValue EltVal = getI32Imm(Elt >> 1);
2839 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2840 SDValue TmpVal = SDValue(Tmp, 0);
2841 return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal);
2843 } else if (Elt > 0) {
2844 // Elt is odd and positive, in the range [17,31].
2846 // Convert: VADD_SPLAT elt, size
2847 // Into: tmp1 = VSPLTIS[BHW] elt-16
2848 // tmp2 = VSPLTIS[BHW] -16
2849 // VSUBU[BHW]M tmp1, tmp2
2850 SDValue EltVal = getI32Imm(Elt - 16);
2851 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2852 EltVal = getI32Imm(-16);
2853 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2854 return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
2858 // Elt is odd and negative, in the range [-31,-17].
2860 // Convert: VADD_SPLAT elt, size
2861 // Into: tmp1 = VSPLTIS[BHW] elt+16
2862 // tmp2 = VSPLTIS[BHW] -16
2863 // VADDU[BHW]M tmp1, tmp2
2864 SDValue EltVal = getI32Imm(Elt + 16);
2865 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2866 EltVal = getI32Imm(-16);
2867 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2868 return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
2874 return SelectCode(N);
2877 // If the target supports the cmpb instruction, do the idiom recognition here.
2878 // We don't do this as a DAG combine because we don't want to do it as nodes
2879 // are being combined (because we might miss part of the eventual idiom). We
2880 // don't want to do it during instruction selection because we want to reuse
2881 // the logic for lowering the masking operations already part of the
2882 // instruction selector.
2883 SDValue PPCDAGToDAGISel::combineToCMPB(SDNode *N) {
2886 assert(N->getOpcode() == ISD::OR &&
2887 "Only OR nodes are supported for CMPB");
2890 if (!PPCSubTarget->hasCMPB())
2893 if (N->getValueType(0) != MVT::i32 &&
2894 N->getValueType(0) != MVT::i64)
2897 EVT VT = N->getValueType(0);
2900 bool BytesFound[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
2901 uint64_t Mask = 0, Alt = 0;
2903 auto IsByteSelectCC = [this](SDValue O, unsigned &b,
2904 uint64_t &Mask, uint64_t &Alt,
2905 SDValue &LHS, SDValue &RHS) {
2906 if (O.getOpcode() != ISD::SELECT_CC)
2908 ISD::CondCode CC = cast<CondCodeSDNode>(O.getOperand(4))->get();
2910 if (!isa<ConstantSDNode>(O.getOperand(2)) ||
2911 !isa<ConstantSDNode>(O.getOperand(3)))
2914 uint64_t PM = O.getConstantOperandVal(2);
2915 uint64_t PAlt = O.getConstantOperandVal(3);
2916 for (b = 0; b < 8; ++b) {
2917 uint64_t Mask = UINT64_C(0xFF) << (8*b);
2918 if (PM && (PM & Mask) == PM && (PAlt & Mask) == PAlt)
2927 if (!isa<ConstantSDNode>(O.getOperand(1)) ||
2928 O.getConstantOperandVal(1) != 0) {
2929 SDValue Op0 = O.getOperand(0), Op1 = O.getOperand(1);
2930 if (Op0.getOpcode() == ISD::TRUNCATE)
2931 Op0 = Op0.getOperand(0);
2932 if (Op1.getOpcode() == ISD::TRUNCATE)
2933 Op1 = Op1.getOperand(0);
2935 if (Op0.getOpcode() == ISD::SRL && Op1.getOpcode() == ISD::SRL &&
2936 Op0.getOperand(1) == Op1.getOperand(1) && CC == ISD::SETEQ &&
2937 isa<ConstantSDNode>(Op0.getOperand(1))) {
2939 unsigned Bits = Op0.getValueType().getSizeInBits();
2942 if (Op0.getConstantOperandVal(1) != Bits-8)
2945 LHS = Op0.getOperand(0);
2946 RHS = Op1.getOperand(0);
2950 // When we have small integers (i16 to be specific), the form present
2951 // post-legalization uses SETULT in the SELECT_CC for the
2952 // higher-order byte, depending on the fact that the
2953 // even-higher-order bytes are known to all be zero, for example:
2954 // select_cc (xor $lhs, $rhs), 256, 65280, 0, setult
2955 // (so when the second byte is the same, because all higher-order
2956 // bits from bytes 3 and 4 are known to be zero, the result of the
2957 // xor can be at most 255)
2958 if (Op0.getOpcode() == ISD::XOR && CC == ISD::SETULT &&
2959 isa<ConstantSDNode>(O.getOperand(1))) {
2961 uint64_t ULim = O.getConstantOperandVal(1);
2962 if (ULim != (UINT64_C(1) << b*8))
2965 // Now we need to make sure that the upper bytes are known to be
2967 unsigned Bits = Op0.getValueType().getSizeInBits();
2968 if (!CurDAG->MaskedValueIsZero(Op0,
2969 APInt::getHighBitsSet(Bits, Bits - (b+1)*8)))
2972 LHS = Op0.getOperand(0);
2973 RHS = Op0.getOperand(1);
2980 if (CC != ISD::SETEQ)
2983 SDValue Op = O.getOperand(0);
2984 if (Op.getOpcode() == ISD::AND) {
2985 if (!isa<ConstantSDNode>(Op.getOperand(1)))
2987 if (Op.getConstantOperandVal(1) != (UINT64_C(0xFF) << (8*b)))
2990 SDValue XOR = Op.getOperand(0);
2991 if (XOR.getOpcode() == ISD::TRUNCATE)
2992 XOR = XOR.getOperand(0);
2993 if (XOR.getOpcode() != ISD::XOR)
2996 LHS = XOR.getOperand(0);
2997 RHS = XOR.getOperand(1);
2999 } else if (Op.getOpcode() == ISD::SRL) {
3000 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3002 unsigned Bits = Op.getValueType().getSizeInBits();
3005 if (Op.getConstantOperandVal(1) != Bits-8)
3008 SDValue XOR = Op.getOperand(0);
3009 if (XOR.getOpcode() == ISD::TRUNCATE)
3010 XOR = XOR.getOperand(0);
3011 if (XOR.getOpcode() != ISD::XOR)
3014 LHS = XOR.getOperand(0);
3015 RHS = XOR.getOperand(1);
3022 SmallVector<SDValue, 8> Queue(1, SDValue(N, 0));
3023 while (!Queue.empty()) {
3024 SDValue V = Queue.pop_back_val();
3026 for (const SDValue &O : V.getNode()->ops()) {
3028 uint64_t M = 0, A = 0;
3030 if (O.getOpcode() == ISD::OR) {
3032 } else if (IsByteSelectCC(O, b, M, A, OLHS, ORHS)) {
3036 BytesFound[b] = true;
3039 } else if ((LHS == ORHS && RHS == OLHS) ||
3040 (RHS == ORHS && LHS == OLHS)) {
3041 BytesFound[b] = true;
3053 unsigned LastB = 0, BCnt = 0;
3054 for (unsigned i = 0; i < 8; ++i)
3055 if (BytesFound[LastB]) {
3060 if (!LastB || BCnt < 2)
3063 // Because we'll be zero-extending the output anyway if don't have a specific
3064 // value for each input byte (via the Mask), we can 'anyext' the inputs.
3065 if (LHS.getValueType() != VT) {
3066 LHS = CurDAG->getAnyExtOrTrunc(LHS, dl, VT);
3067 RHS = CurDAG->getAnyExtOrTrunc(RHS, dl, VT);
3070 Res = CurDAG->getNode(PPCISD::CMPB, dl, VT, LHS, RHS);
3072 bool NonTrivialMask = ((int64_t) Mask) != INT64_C(-1);
3073 if (NonTrivialMask && !Alt) {
3074 // Res = Mask & CMPB
3075 Res = CurDAG->getNode(ISD::AND, dl, VT, Res, CurDAG->getConstant(Mask, VT));
3077 // Res = (CMPB & Mask) | (~CMPB & Alt)
3078 // Which, as suggested here:
3079 // https://graphics.stanford.edu/~seander/bithacks.html#MaskedMerge
3080 // can be written as:
3081 // Res = Alt ^ ((Alt ^ Mask) & CMPB)
3082 // useful because the (Alt ^ Mask) can be pre-computed.
3083 Res = CurDAG->getNode(ISD::AND, dl, VT, Res,
3084 CurDAG->getConstant(Mask ^ Alt, VT));
3085 Res = CurDAG->getNode(ISD::XOR, dl, VT, Res, CurDAG->getConstant(Alt, VT));
3091 void PPCDAGToDAGISel::PreprocessISelDAG() {
3092 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
3095 bool MadeChange = false;
3096 while (Position != CurDAG->allnodes_begin()) {
3097 SDNode *N = --Position;
3102 switch (N->getOpcode()) {
3105 Res = combineToCMPB(N);
3110 DEBUG(dbgs() << "PPC DAG preprocessing replacing:\nOld: ");
3111 DEBUG(N->dump(CurDAG));
3112 DEBUG(dbgs() << "\nNew: ");
3113 DEBUG(Res.getNode()->dump(CurDAG));
3114 DEBUG(dbgs() << "\n");
3116 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Res);
3122 CurDAG->RemoveDeadNodes();
3125 /// PostprocessISelDAG - Perform some late peephole optimizations
3126 /// on the DAG representation.
3127 void PPCDAGToDAGISel::PostprocessISelDAG() {
3129 // Skip peepholes at -O0.
3130 if (TM.getOptLevel() == CodeGenOpt::None)
3135 PeepholePPC64ZExt();
3138 // Check if all users of this node will become isel where the second operand
3139 // is the constant zero. If this is so, and if we can negate the condition,
3140 // then we can flip the true and false operands. This will allow the zero to
3141 // be folded with the isel so that we don't need to materialize a register
3143 bool PPCDAGToDAGISel::AllUsersSelectZero(SDNode *N) {
3144 // If we're not using isel, then this does not matter.
3145 if (!PPCSubTarget->hasISEL())
3148 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3151 if (!User->isMachineOpcode())
3153 if (User->getMachineOpcode() != PPC::SELECT_I4 &&
3154 User->getMachineOpcode() != PPC::SELECT_I8)
3157 SDNode *Op2 = User->getOperand(2).getNode();
3158 if (!Op2->isMachineOpcode())
3161 if (Op2->getMachineOpcode() != PPC::LI &&
3162 Op2->getMachineOpcode() != PPC::LI8)
3165 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2->getOperand(0));
3169 if (!C->isNullValue())
3176 void PPCDAGToDAGISel::SwapAllSelectUsers(SDNode *N) {
3177 SmallVector<SDNode *, 4> ToReplace;
3178 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3181 assert((User->getMachineOpcode() == PPC::SELECT_I4 ||
3182 User->getMachineOpcode() == PPC::SELECT_I8) &&
3183 "Must have all select users");
3184 ToReplace.push_back(User);
3187 for (SmallVector<SDNode *, 4>::iterator UI = ToReplace.begin(),
3188 UE = ToReplace.end(); UI != UE; ++UI) {
3191 CurDAG->getMachineNode(User->getMachineOpcode(), SDLoc(User),
3192 User->getValueType(0), User->getOperand(0),
3193 User->getOperand(2),
3194 User->getOperand(1));
3196 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
3197 DEBUG(User->dump(CurDAG));
3198 DEBUG(dbgs() << "\nNew: ");
3199 DEBUG(ResNode->dump(CurDAG));
3200 DEBUG(dbgs() << "\n");
3202 ReplaceUses(User, ResNode);
3206 void PPCDAGToDAGISel::PeepholeCROps() {
3210 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
3211 E = CurDAG->allnodes_end(); I != E; ++I) {
3212 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
3213 if (!MachineNode || MachineNode->use_empty())
3215 SDNode *ResNode = MachineNode;
3217 bool Op1Set = false, Op1Unset = false,
3219 Op2Set = false, Op2Unset = false,
3222 unsigned Opcode = MachineNode->getMachineOpcode();
3233 SDValue Op = MachineNode->getOperand(1);
3234 if (Op.isMachineOpcode()) {
3235 if (Op.getMachineOpcode() == PPC::CRSET)
3237 else if (Op.getMachineOpcode() == PPC::CRUNSET)
3239 else if (Op.getMachineOpcode() == PPC::CRNOR &&
3240 Op.getOperand(0) == Op.getOperand(1))
3246 case PPC::SELECT_I4:
3247 case PPC::SELECT_I8:
3248 case PPC::SELECT_F4:
3249 case PPC::SELECT_F8:
3250 case PPC::SELECT_VRRC:
3251 case PPC::SELECT_VSFRC:
3252 case PPC::SELECT_VSRC: {
3253 SDValue Op = MachineNode->getOperand(0);
3254 if (Op.isMachineOpcode()) {
3255 if (Op.getMachineOpcode() == PPC::CRSET)
3257 else if (Op.getMachineOpcode() == PPC::CRUNSET)
3259 else if (Op.getMachineOpcode() == PPC::CRNOR &&
3260 Op.getOperand(0) == Op.getOperand(1))
3267 bool SelectSwap = false;
3271 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3273 ResNode = MachineNode->getOperand(0).getNode();
3276 ResNode = MachineNode->getOperand(1).getNode();
3279 ResNode = MachineNode->getOperand(0).getNode();
3280 else if (Op1Unset || Op2Unset)
3281 // x & 0 = 0 & y = 0
3282 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3285 // ~x & y = andc(y, x)
3286 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3287 MVT::i1, MachineNode->getOperand(1),
3288 MachineNode->getOperand(0).
3291 // x & ~y = andc(x, y)
3292 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3293 MVT::i1, MachineNode->getOperand(0),
3294 MachineNode->getOperand(1).
3296 else if (AllUsersSelectZero(MachineNode))
3297 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
3298 MVT::i1, MachineNode->getOperand(0),
3299 MachineNode->getOperand(1)),
3303 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3304 // nand(x, x) -> nor(x, x)
3305 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3306 MVT::i1, MachineNode->getOperand(0),
3307 MachineNode->getOperand(0));
3309 // nand(1, y) -> nor(y, y)
3310 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3311 MVT::i1, MachineNode->getOperand(1),
3312 MachineNode->getOperand(1));
3314 // nand(x, 1) -> nor(x, x)
3315 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3316 MVT::i1, MachineNode->getOperand(0),
3317 MachineNode->getOperand(0));
3318 else if (Op1Unset || Op2Unset)
3319 // nand(x, 0) = nand(0, y) = 1
3320 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3323 // nand(~x, y) = ~(~x & y) = x | ~y = orc(x, y)
3324 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3325 MVT::i1, MachineNode->getOperand(0).
3327 MachineNode->getOperand(1));
3329 // nand(x, ~y) = ~x | y = orc(y, x)
3330 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3331 MVT::i1, MachineNode->getOperand(1).
3333 MachineNode->getOperand(0));
3334 else if (AllUsersSelectZero(MachineNode))
3335 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
3336 MVT::i1, MachineNode->getOperand(0),
3337 MachineNode->getOperand(1)),
3341 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3343 ResNode = MachineNode->getOperand(0).getNode();
3344 else if (Op1Set || Op2Set)
3345 // x | 1 = 1 | y = 1
3346 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3350 ResNode = MachineNode->getOperand(1).getNode();
3353 ResNode = MachineNode->getOperand(0).getNode();
3355 // ~x | y = orc(y, x)
3356 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3357 MVT::i1, MachineNode->getOperand(1),
3358 MachineNode->getOperand(0).
3361 // x | ~y = orc(x, y)
3362 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3363 MVT::i1, MachineNode->getOperand(0),
3364 MachineNode->getOperand(1).
3366 else if (AllUsersSelectZero(MachineNode))
3367 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3368 MVT::i1, MachineNode->getOperand(0),
3369 MachineNode->getOperand(1)),
3373 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3375 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3378 // xor(1, y) -> nor(y, y)
3379 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3380 MVT::i1, MachineNode->getOperand(1),
3381 MachineNode->getOperand(1));
3383 // xor(x, 1) -> nor(x, x)
3384 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3385 MVT::i1, MachineNode->getOperand(0),
3386 MachineNode->getOperand(0));
3389 ResNode = MachineNode->getOperand(1).getNode();
3392 ResNode = MachineNode->getOperand(0).getNode();
3394 // xor(~x, y) = eqv(x, y)
3395 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
3396 MVT::i1, MachineNode->getOperand(0).
3398 MachineNode->getOperand(1));
3400 // xor(x, ~y) = eqv(x, y)
3401 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
3402 MVT::i1, MachineNode->getOperand(0),
3403 MachineNode->getOperand(1).
3405 else if (AllUsersSelectZero(MachineNode))
3406 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
3407 MVT::i1, MachineNode->getOperand(0),
3408 MachineNode->getOperand(1)),
3412 if (Op1Set || Op2Set)
3414 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3417 // nor(0, y) = ~y -> nor(y, y)
3418 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3419 MVT::i1, MachineNode->getOperand(1),
3420 MachineNode->getOperand(1));
3423 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3424 MVT::i1, MachineNode->getOperand(0),
3425 MachineNode->getOperand(0));
3427 // nor(~x, y) = andc(x, y)
3428 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3429 MVT::i1, MachineNode->getOperand(0).
3431 MachineNode->getOperand(1));
3433 // nor(x, ~y) = andc(y, x)
3434 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3435 MVT::i1, MachineNode->getOperand(1).
3437 MachineNode->getOperand(0));
3438 else if (AllUsersSelectZero(MachineNode))
3439 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
3440 MVT::i1, MachineNode->getOperand(0),
3441 MachineNode->getOperand(1)),
3445 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3447 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3451 ResNode = MachineNode->getOperand(1).getNode();
3454 ResNode = MachineNode->getOperand(0).getNode();
3456 // eqv(0, y) = ~y -> nor(y, y)
3457 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3458 MVT::i1, MachineNode->getOperand(1),
3459 MachineNode->getOperand(1));
3462 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3463 MVT::i1, MachineNode->getOperand(0),
3464 MachineNode->getOperand(0));
3466 // eqv(~x, y) = xor(x, y)
3467 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
3468 MVT::i1, MachineNode->getOperand(0).
3470 MachineNode->getOperand(1));
3472 // eqv(x, ~y) = xor(x, y)
3473 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
3474 MVT::i1, MachineNode->getOperand(0),
3475 MachineNode->getOperand(1).
3477 else if (AllUsersSelectZero(MachineNode))
3478 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
3479 MVT::i1, MachineNode->getOperand(0),
3480 MachineNode->getOperand(1)),
3484 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3486 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3490 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3491 MVT::i1, MachineNode->getOperand(1),
3492 MachineNode->getOperand(1));
3493 else if (Op1Unset || Op2Set)
3494 // andc(0, y) = andc(x, 1) = 0
3495 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3499 ResNode = MachineNode->getOperand(0).getNode();
3501 // andc(~x, y) = ~(x | y) = nor(x, y)
3502 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3503 MVT::i1, MachineNode->getOperand(0).
3505 MachineNode->getOperand(1));
3507 // andc(x, ~y) = x & y
3508 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
3509 MVT::i1, MachineNode->getOperand(0),
3510 MachineNode->getOperand(1).
3512 else if (AllUsersSelectZero(MachineNode))
3513 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3514 MVT::i1, MachineNode->getOperand(1),
3515 MachineNode->getOperand(0)),
3519 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3521 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3523 else if (Op1Set || Op2Unset)
3524 // orc(1, y) = orc(x, 0) = 1
3525 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3529 ResNode = MachineNode->getOperand(0).getNode();
3532 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3533 MVT::i1, MachineNode->getOperand(1),
3534 MachineNode->getOperand(1));
3536 // orc(~x, y) = ~(x & y) = nand(x, y)
3537 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
3538 MVT::i1, MachineNode->getOperand(0).
3540 MachineNode->getOperand(1));
3542 // orc(x, ~y) = x | y
3543 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
3544 MVT::i1, MachineNode->getOperand(0),
3545 MachineNode->getOperand(1).
3547 else if (AllUsersSelectZero(MachineNode))
3548 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3549 MVT::i1, MachineNode->getOperand(1),
3550 MachineNode->getOperand(0)),
3553 case PPC::SELECT_I4:
3554 case PPC::SELECT_I8:
3555 case PPC::SELECT_F4:
3556 case PPC::SELECT_F8:
3557 case PPC::SELECT_VRRC:
3558 case PPC::SELECT_VSFRC:
3559 case PPC::SELECT_VSRC:
3561 ResNode = MachineNode->getOperand(1).getNode();
3563 ResNode = MachineNode->getOperand(2).getNode();
3565 ResNode = CurDAG->getMachineNode(MachineNode->getMachineOpcode(),
3567 MachineNode->getValueType(0),
3568 MachineNode->getOperand(0).
3570 MachineNode->getOperand(2),
3571 MachineNode->getOperand(1));
3576 ResNode = CurDAG->getMachineNode(Opcode == PPC::BC ? PPC::BCn :
3580 MachineNode->getOperand(0).
3582 MachineNode->getOperand(1),
3583 MachineNode->getOperand(2));
3584 // FIXME: Handle Op1Set, Op1Unset here too.
3588 // If we're inverting this node because it is used only by selects that
3589 // we'd like to swap, then swap the selects before the node replacement.
3591 SwapAllSelectUsers(MachineNode);
3593 if (ResNode != MachineNode) {
3594 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
3595 DEBUG(MachineNode->dump(CurDAG));
3596 DEBUG(dbgs() << "\nNew: ");
3597 DEBUG(ResNode->dump(CurDAG));
3598 DEBUG(dbgs() << "\n");
3600 ReplaceUses(MachineNode, ResNode);
3605 CurDAG->RemoveDeadNodes();
3606 } while (IsModified);
3609 // Gather the set of 32-bit operations that are known to have their
3610 // higher-order 32 bits zero, where ToPromote contains all such operations.
3611 static bool PeepholePPC64ZExtGather(SDValue Op32,
3612 SmallPtrSetImpl<SDNode *> &ToPromote) {
3613 if (!Op32.isMachineOpcode())
3616 // First, check for the "frontier" instructions (those that will clear the
3617 // higher-order 32 bits.
3619 // For RLWINM and RLWNM, we need to make sure that the mask does not wrap
3620 // around. If it does not, then these instructions will clear the
3621 // higher-order bits.
3622 if ((Op32.getMachineOpcode() == PPC::RLWINM ||
3623 Op32.getMachineOpcode() == PPC::RLWNM) &&
3624 Op32.getConstantOperandVal(2) <= Op32.getConstantOperandVal(3)) {
3625 ToPromote.insert(Op32.getNode());
3629 // SLW and SRW always clear the higher-order bits.
3630 if (Op32.getMachineOpcode() == PPC::SLW ||
3631 Op32.getMachineOpcode() == PPC::SRW) {
3632 ToPromote.insert(Op32.getNode());
3636 // For LI and LIS, we need the immediate to be positive (so that it is not
3638 if (Op32.getMachineOpcode() == PPC::LI ||
3639 Op32.getMachineOpcode() == PPC::LIS) {
3640 if (!isUInt<15>(Op32.getConstantOperandVal(0)))
3643 ToPromote.insert(Op32.getNode());
3647 // Next, check for those instructions we can look through.
3649 // Assuming the mask does not wrap around, then the higher-order bits are
3650 // taken directly from the first operand.
3651 if (Op32.getMachineOpcode() == PPC::RLWIMI &&
3652 Op32.getConstantOperandVal(3) <= Op32.getConstantOperandVal(4)) {
3653 SmallPtrSet<SDNode *, 16> ToPromote1;
3654 if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
3657 ToPromote.insert(Op32.getNode());
3658 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3662 // For OR, the higher-order bits are zero if that is true for both operands.
3663 // For SELECT_I4, the same is true (but the relevant operand numbers are
3665 if (Op32.getMachineOpcode() == PPC::OR ||
3666 Op32.getMachineOpcode() == PPC::SELECT_I4) {
3667 unsigned B = Op32.getMachineOpcode() == PPC::SELECT_I4 ? 1 : 0;
3668 SmallPtrSet<SDNode *, 16> ToPromote1;
3669 if (!PeepholePPC64ZExtGather(Op32.getOperand(B+0), ToPromote1))
3671 if (!PeepholePPC64ZExtGather(Op32.getOperand(B+1), ToPromote1))
3674 ToPromote.insert(Op32.getNode());
3675 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3679 // For ORI and ORIS, we need the higher-order bits of the first operand to be
3680 // zero, and also for the constant to be positive (so that it is not sign
3682 if (Op32.getMachineOpcode() == PPC::ORI ||
3683 Op32.getMachineOpcode() == PPC::ORIS) {
3684 SmallPtrSet<SDNode *, 16> ToPromote1;
3685 if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
3687 if (!isUInt<15>(Op32.getConstantOperandVal(1)))
3690 ToPromote.insert(Op32.getNode());
3691 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3695 // The higher-order bits of AND are zero if that is true for at least one of
3697 if (Op32.getMachineOpcode() == PPC::AND) {
3698 SmallPtrSet<SDNode *, 16> ToPromote1, ToPromote2;
3700 PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
3702 PeepholePPC64ZExtGather(Op32.getOperand(1), ToPromote2);
3703 if (!Op0OK && !Op1OK)
3706 ToPromote.insert(Op32.getNode());
3709 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3712 ToPromote.insert(ToPromote2.begin(), ToPromote2.end());
3717 // For ANDI and ANDIS, the higher-order bits are zero if either that is true
3718 // of the first operand, or if the second operand is positive (so that it is
3719 // not sign extended).
3720 if (Op32.getMachineOpcode() == PPC::ANDIo ||
3721 Op32.getMachineOpcode() == PPC::ANDISo) {
3722 SmallPtrSet<SDNode *, 16> ToPromote1;
3724 PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
3725 bool Op1OK = isUInt<15>(Op32.getConstantOperandVal(1));
3726 if (!Op0OK && !Op1OK)
3729 ToPromote.insert(Op32.getNode());
3732 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3740 void PPCDAGToDAGISel::PeepholePPC64ZExt() {
3741 if (!PPCSubTarget->isPPC64())
3744 // When we zero-extend from i32 to i64, we use a pattern like this:
3745 // def : Pat<(i64 (zext i32:$in)),
3746 // (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
3748 // There are several 32-bit shift/rotate instructions, however, that will
3749 // clear the higher-order bits of their output, rendering the RLDICL
3750 // unnecessary. When that happens, we remove it here, and redefine the
3751 // relevant 32-bit operation to be a 64-bit operation.
3753 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
3756 bool MadeChange = false;
3757 while (Position != CurDAG->allnodes_begin()) {
3758 SDNode *N = --Position;
3759 // Skip dead nodes and any non-machine opcodes.
3760 if (N->use_empty() || !N->isMachineOpcode())
3763 if (N->getMachineOpcode() != PPC::RLDICL)
3766 if (N->getConstantOperandVal(1) != 0 ||
3767 N->getConstantOperandVal(2) != 32)
3770 SDValue ISR = N->getOperand(0);
3771 if (!ISR.isMachineOpcode() ||
3772 ISR.getMachineOpcode() != TargetOpcode::INSERT_SUBREG)
3775 if (!ISR.hasOneUse())
3778 if (ISR.getConstantOperandVal(2) != PPC::sub_32)
3781 SDValue IDef = ISR.getOperand(0);
3782 if (!IDef.isMachineOpcode() ||
3783 IDef.getMachineOpcode() != TargetOpcode::IMPLICIT_DEF)
3786 // We now know that we're looking at a canonical i32 -> i64 zext. See if we
3787 // can get rid of it.
3789 SDValue Op32 = ISR->getOperand(1);
3790 if (!Op32.isMachineOpcode())
3793 // There are some 32-bit instructions that always clear the high-order 32
3794 // bits, there are also some instructions (like AND) that we can look
3796 SmallPtrSet<SDNode *, 16> ToPromote;
3797 if (!PeepholePPC64ZExtGather(Op32, ToPromote))
3800 // If the ToPromote set contains nodes that have uses outside of the set
3801 // (except for the original INSERT_SUBREG), then abort the transformation.
3802 bool OutsideUse = false;
3803 for (SDNode *PN : ToPromote) {
3804 for (SDNode *UN : PN->uses()) {
3805 if (!ToPromote.count(UN) && UN != ISR.getNode()) {
3819 // We now know that this zero extension can be removed by promoting to
3820 // nodes in ToPromote to 64-bit operations, where for operations in the
3821 // frontier of the set, we need to insert INSERT_SUBREGs for their
3823 for (SDNode *PN : ToPromote) {
3825 switch (PN->getMachineOpcode()) {
3827 llvm_unreachable("Don't know the 64-bit variant of this instruction");
3828 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break;
3829 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break;
3830 case PPC::SLW: NewOpcode = PPC::SLW8; break;
3831 case PPC::SRW: NewOpcode = PPC::SRW8; break;
3832 case PPC::LI: NewOpcode = PPC::LI8; break;
3833 case PPC::LIS: NewOpcode = PPC::LIS8; break;
3834 case PPC::RLWIMI: NewOpcode = PPC::RLWIMI8; break;
3835 case PPC::OR: NewOpcode = PPC::OR8; break;
3836 case PPC::SELECT_I4: NewOpcode = PPC::SELECT_I8; break;
3837 case PPC::ORI: NewOpcode = PPC::ORI8; break;
3838 case PPC::ORIS: NewOpcode = PPC::ORIS8; break;
3839 case PPC::AND: NewOpcode = PPC::AND8; break;
3840 case PPC::ANDIo: NewOpcode = PPC::ANDIo8; break;
3841 case PPC::ANDISo: NewOpcode = PPC::ANDISo8; break;
3844 // Note: During the replacement process, the nodes will be in an
3845 // inconsistent state (some instructions will have operands with values
3846 // of the wrong type). Once done, however, everything should be right
3849 SmallVector<SDValue, 4> Ops;
3850 for (const SDValue &V : PN->ops()) {
3851 if (!ToPromote.count(V.getNode()) && V.getValueType() == MVT::i32 &&
3852 !isa<ConstantSDNode>(V)) {
3853 SDValue ReplOpOps[] = { ISR.getOperand(0), V, ISR.getOperand(2) };
3855 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, SDLoc(V),
3856 ISR.getNode()->getVTList(), ReplOpOps);
3857 Ops.push_back(SDValue(ReplOp, 0));
3863 // Because all to-be-promoted nodes only have users that are other
3864 // promoted nodes (or the original INSERT_SUBREG), we can safely replace
3865 // the i32 result value type with i64.
3867 SmallVector<EVT, 2> NewVTs;
3868 SDVTList VTs = PN->getVTList();
3869 for (unsigned i = 0, ie = VTs.NumVTs; i != ie; ++i)
3870 if (VTs.VTs[i] == MVT::i32)
3871 NewVTs.push_back(MVT::i64);
3873 NewVTs.push_back(VTs.VTs[i]);
3875 DEBUG(dbgs() << "PPC64 ZExt Peephole morphing:\nOld: ");
3876 DEBUG(PN->dump(CurDAG));
3878 CurDAG->SelectNodeTo(PN, NewOpcode, CurDAG->getVTList(NewVTs), Ops);
3880 DEBUG(dbgs() << "\nNew: ");
3881 DEBUG(PN->dump(CurDAG));
3882 DEBUG(dbgs() << "\n");
3885 // Now we replace the original zero extend and its associated INSERT_SUBREG
3886 // with the value feeding the INSERT_SUBREG (which has now been promoted to
3889 DEBUG(dbgs() << "PPC64 ZExt Peephole replacing:\nOld: ");
3890 DEBUG(N->dump(CurDAG));
3891 DEBUG(dbgs() << "\nNew: ");
3892 DEBUG(Op32.getNode()->dump(CurDAG));
3893 DEBUG(dbgs() << "\n");
3895 ReplaceUses(N, Op32.getNode());
3899 CurDAG->RemoveDeadNodes();
3902 void PPCDAGToDAGISel::PeepholePPC64() {
3903 // These optimizations are currently supported only for 64-bit SVR4.
3904 if (PPCSubTarget->isDarwin() || !PPCSubTarget->isPPC64())
3907 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
3910 while (Position != CurDAG->allnodes_begin()) {
3911 SDNode *N = --Position;
3912 // Skip dead nodes and any non-machine opcodes.
3913 if (N->use_empty() || !N->isMachineOpcode())
3917 unsigned StorageOpcode = N->getMachineOpcode();
3919 switch (StorageOpcode) {
3950 // If this is a load or store with a zero offset, we may be able to
3951 // fold an add-immediate into the memory operation.
3952 if (!isa<ConstantSDNode>(N->getOperand(FirstOp)) ||
3953 N->getConstantOperandVal(FirstOp) != 0)
3956 SDValue Base = N->getOperand(FirstOp + 1);
3957 if (!Base.isMachineOpcode())
3961 bool ReplaceFlags = true;
3963 // When the feeding operation is an add-immediate of some sort,
3964 // determine whether we need to add relocation information to the
3965 // target flags on the immediate operand when we fold it into the
3966 // load instruction.
3968 // For something like ADDItocL, the relocation information is
3969 // inferred from the opcode; when we process it in the AsmPrinter,
3970 // we add the necessary relocation there. A load, though, can receive
3971 // relocation from various flavors of ADDIxxx, so we need to carry
3972 // the relocation information in the target flags.
3973 switch (Base.getMachineOpcode()) {
3978 // In some cases (such as TLS) the relocation information
3979 // is already in place on the operand, so copying the operand
3981 ReplaceFlags = false;
3982 // For these cases, the immediate may not be divisible by 4, in
3983 // which case the fold is illegal for DS-form instructions. (The
3984 // other cases provide aligned addresses and are always safe.)
3985 if ((StorageOpcode == PPC::LWA ||
3986 StorageOpcode == PPC::LD ||
3987 StorageOpcode == PPC::STD) &&
3988 (!isa<ConstantSDNode>(Base.getOperand(1)) ||
3989 Base.getConstantOperandVal(1) % 4 != 0))
3992 case PPC::ADDIdtprelL:
3993 Flags = PPCII::MO_DTPREL_LO;
3995 case PPC::ADDItlsldL:
3996 Flags = PPCII::MO_TLSLD_LO;
3999 Flags = PPCII::MO_TOC_LO;
4003 // We found an opportunity. Reverse the operands from the add
4004 // immediate and substitute them into the load or store. If
4005 // needed, update the target flags for the immediate operand to
4006 // reflect the necessary relocation information.
4007 DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: ");
4008 DEBUG(Base->dump(CurDAG));
4009 DEBUG(dbgs() << "\nN: ");
4010 DEBUG(N->dump(CurDAG));
4011 DEBUG(dbgs() << "\n");
4013 SDValue ImmOpnd = Base.getOperand(1);
4015 // If the relocation information isn't already present on the
4016 // immediate operand, add it now.
4018 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
4020 const GlobalValue *GV = GA->getGlobal();
4021 // We can't perform this optimization for data whose alignment
4022 // is insufficient for the instruction encoding.
4023 if (GV->getAlignment() < 4 &&
4024 (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD ||
4025 StorageOpcode == PPC::LWA)) {
4026 DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
4029 ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);
4030 } else if (ConstantPoolSDNode *CP =
4031 dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
4032 const Constant *C = CP->getConstVal();
4033 ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64,
4039 if (FirstOp == 1) // Store
4040 (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd,
4041 Base.getOperand(0), N->getOperand(3));
4043 (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0),
4046 // The add-immediate may now be dead, in which case remove it.
4047 if (Base.getNode()->use_empty())
4048 CurDAG->RemoveDeadNode(Base.getNode());
4053 /// createPPCISelDag - This pass converts a legalized DAG into a
4054 /// PowerPC-specific DAG, ready for instruction scheduling.
4056 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
4057 return new PPCDAGToDAGISel(TM);
4060 static void initializePassOnce(PassRegistry &Registry) {
4061 const char *Name = "PowerPC DAG->DAG Pattern Instruction Selection";
4062 PassInfo *PI = new PassInfo(Name, "ppc-codegen", &SelectionDAGISel::ID,
4063 nullptr, false, false);
4064 Registry.registerPass(*PI, true);
4067 void llvm::initializePPCDAGToDAGISelPass(PassRegistry &Registry) {
4068 CALL_ONCE_INITIALIZATION(initializePassOnce);