1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalAlias.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/GlobalVariable.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Module.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetOptions.h"
39 #define DEBUG_TYPE "ppc-codegen"
41 // FIXME: Remove this once the bug has been fixed!
42 cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
43 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
45 cl::opt<bool> UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true),
46 cl::desc("use aggressive ppc isel for bit permutations"), cl::Hidden);
47 cl::opt<bool> BPermRewriterNoMasking("ppc-bit-perm-rewriter-stress-rotates",
48 cl::desc("stress rotate selection in aggressive ppc isel for "
49 "bit permutations"), cl::Hidden);
52 void initializePPCDAGToDAGISelPass(PassRegistry&);
56 //===--------------------------------------------------------------------===//
57 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
58 /// instructions for SelectionDAG operations.
60 class PPCDAGToDAGISel : public SelectionDAGISel {
61 const PPCTargetMachine &TM;
62 const PPCTargetLowering *PPCLowering;
63 const PPCSubtarget *PPCSubTarget;
64 unsigned GlobalBaseReg;
66 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
67 : SelectionDAGISel(tm), TM(tm),
68 PPCLowering(TM.getSubtargetImpl()->getTargetLowering()),
69 PPCSubTarget(TM.getSubtargetImpl()) {
70 initializePPCDAGToDAGISelPass(*PassRegistry::getPassRegistry());
73 bool runOnMachineFunction(MachineFunction &MF) override {
74 // Make sure we re-emit a set of the global base reg if necessary
76 PPCLowering = TM.getSubtargetImpl()->getTargetLowering();
77 PPCSubTarget = TM.getSubtargetImpl();
78 SelectionDAGISel::runOnMachineFunction(MF);
80 if (!PPCSubTarget->isSVR4ABI())
86 void PreprocessISelDAG() override;
87 void PostprocessISelDAG() override;
89 /// getI32Imm - Return a target constant with the specified value, of type
91 inline SDValue getI32Imm(unsigned Imm) {
92 return CurDAG->getTargetConstant(Imm, MVT::i32);
95 /// getI64Imm - Return a target constant with the specified value, of type
97 inline SDValue getI64Imm(uint64_t Imm) {
98 return CurDAG->getTargetConstant(Imm, MVT::i64);
101 /// getSmallIPtrImm - Return a target constant of pointer type.
102 inline SDValue getSmallIPtrImm(unsigned Imm) {
103 return CurDAG->getTargetConstant(Imm, PPCLowering->getPointerTy());
106 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
107 /// with any number of 0s on either side. The 1s are allowed to wrap from
108 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
109 /// 0x0F0F0000 is not, since all 1s are not contiguous.
110 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
113 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
114 /// rotate and mask opcode and mask operation.
115 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
116 unsigned &SH, unsigned &MB, unsigned &ME);
118 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
119 /// base register. Return the virtual register that holds this value.
120 SDNode *getGlobalBaseReg();
122 SDNode *getFrameIndex(SDNode *SN, SDNode *N, unsigned Offset = 0);
124 // Select - Convert the specified operand from a target-independent to a
125 // target-specific node if it hasn't already been changed.
126 SDNode *Select(SDNode *N) override;
128 SDNode *SelectBitfieldInsert(SDNode *N);
129 SDNode *SelectBitPermutation(SDNode *N);
131 /// SelectCC - Select a comparison of the specified values with the
132 /// specified condition code, returning the CR# of the expression.
133 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl);
135 /// SelectAddrImm - Returns true if the address N can be represented by
136 /// a base register plus a signed 16-bit displacement [r+imm].
137 bool SelectAddrImm(SDValue N, SDValue &Disp,
139 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, false);
142 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
143 /// immediate field. Note that the operand at this point is already the
144 /// result of a prior SelectAddressRegImm call.
145 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
146 if (N.getOpcode() == ISD::TargetConstant ||
147 N.getOpcode() == ISD::TargetGlobalAddress) {
155 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
156 /// represented as an indexed [r+r] operation. Returns false if it can
157 /// be represented by [r+imm], which are preferred.
158 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
159 return PPCLowering->SelectAddressRegReg(N, Base, Index, *CurDAG);
162 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
163 /// represented as an indexed [r+r] operation.
164 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
165 return PPCLowering->SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
168 /// SelectAddrImmX4 - Returns true if the address N can be represented by
169 /// a base register plus a signed 16-bit displacement that is a multiple of 4.
170 /// Suitable for use by STD and friends.
171 bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) {
172 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, true);
175 // Select an address into a single register.
176 bool SelectAddr(SDValue N, SDValue &Base) {
181 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
182 /// inline asm expressions. It is always correct to compute the value into
183 /// a register. The case of adding a (possibly relocatable) constant to a
184 /// register can be improved, but it is wrong to substitute Reg+Reg for
185 /// Reg in an asm, because the load or store opcode would have to change.
186 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
188 std::vector<SDValue> &OutOps) override {
189 // We need to make sure that this one operand does not end up in r0
190 // (because we might end up lowering this as 0(%op)).
191 const TargetRegisterInfo *TRI = TM.getSubtargetImpl()->getRegisterInfo();
192 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1);
193 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
195 SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
196 SDLoc(Op), Op.getValueType(),
199 OutOps.push_back(NewOp);
203 void InsertVRSaveCode(MachineFunction &MF);
205 const char *getPassName() const override {
206 return "PowerPC DAG->DAG Pattern Instruction Selection";
209 // Include the pieces autogenerated from the target description.
210 #include "PPCGenDAGISel.inc"
213 SDNode *SelectSETCC(SDNode *N);
215 void PeepholePPC64();
216 void PeepholePPC64ZExt();
217 void PeepholeCROps();
219 SDValue combineToCMPB(SDNode *N);
220 void foldBoolExts(SDValue &Res, SDNode *&N);
222 bool AllUsersSelectZero(SDNode *N);
223 void SwapAllSelectUsers(SDNode *N);
227 /// InsertVRSaveCode - Once the entire function has been instruction selected,
228 /// all virtual registers are created and all machine instructions are built,
229 /// check to see if we need to save/restore VRSAVE. If so, do it.
230 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
231 // Check to see if this function uses vector registers, which means we have to
232 // save and restore the VRSAVE register and update it with the regs we use.
234 // In this case, there will be virtual registers of vector type created
235 // by the scheduler. Detect them now.
236 bool HasVectorVReg = false;
237 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
238 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
239 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
240 HasVectorVReg = true;
244 if (!HasVectorVReg) return; // nothing to do.
246 // If we have a vector register, we want to emit code into the entry and exit
247 // blocks to save and restore the VRSAVE register. We do this here (instead
248 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
250 // 1. This (trivially) reduces the load on the register allocator, by not
251 // having to represent the live range of the VRSAVE register.
252 // 2. This (more significantly) allows us to create a temporary virtual
253 // register to hold the saved VRSAVE value, allowing this temporary to be
254 // register allocated, instead of forcing it to be spilled to the stack.
256 // Create two vregs - one to hold the VRSAVE register that is live-in to the
257 // function and one for the value after having bits or'd into it.
258 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
259 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
261 const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
262 MachineBasicBlock &EntryBB = *Fn.begin();
264 // Emit the following code into the entry block:
265 // InVRSAVE = MFVRSAVE
266 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
267 // MTVRSAVE UpdatedVRSAVE
268 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
269 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
270 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
271 UpdatedVRSAVE).addReg(InVRSAVE);
272 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
274 // Find all return blocks, outputting a restore in each epilog.
275 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
276 if (!BB->empty() && BB->back().isReturn()) {
277 IP = BB->end(); --IP;
279 // Skip over all terminator instructions, which are part of the return
281 MachineBasicBlock::iterator I2 = IP;
282 while (I2 != BB->begin() && (--I2)->isTerminator())
285 // Emit: MTVRSAVE InVRSave
286 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
292 /// getGlobalBaseReg - Output the instructions required to put the
293 /// base address to use for accessing globals into a register.
295 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
296 if (!GlobalBaseReg) {
297 const TargetInstrInfo &TII = *TM.getSubtargetImpl()->getInstrInfo();
298 // Insert the set of GlobalBaseReg into the first MBB of the function
299 MachineBasicBlock &FirstMBB = MF->front();
300 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
301 const Module *M = MF->getFunction()->getParent();
304 if (PPCLowering->getPointerTy() == MVT::i32) {
305 if (PPCSubTarget->isTargetELF()) {
306 GlobalBaseReg = PPC::R30;
307 if (M->getPICLevel() == PICLevel::Small) {
308 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR));
309 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
310 MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
312 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
313 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
314 unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
315 BuildMI(FirstMBB, MBBI, dl,
316 TII.get(PPC::UpdateGBR)).addReg(GlobalBaseReg)
317 .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg);
318 MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
322 RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass);
323 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
324 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
327 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_NOX0RegClass);
328 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
329 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
332 return CurDAG->getRegister(GlobalBaseReg,
333 PPCLowering->getPointerTy()).getNode();
336 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
337 /// or 64-bit immediate, and if the value can be accurately represented as a
338 /// sign extension from a 16-bit value. If so, this returns true and the
340 static bool isIntS16Immediate(SDNode *N, short &Imm) {
341 if (N->getOpcode() != ISD::Constant)
344 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
345 if (N->getValueType(0) == MVT::i32)
346 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
348 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
351 static bool isIntS16Immediate(SDValue Op, short &Imm) {
352 return isIntS16Immediate(Op.getNode(), Imm);
356 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
357 /// operand. If so Imm will receive the 32-bit value.
358 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
359 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
360 Imm = cast<ConstantSDNode>(N)->getZExtValue();
366 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
367 /// operand. If so Imm will receive the 64-bit value.
368 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
369 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
370 Imm = cast<ConstantSDNode>(N)->getZExtValue();
376 // isInt32Immediate - This method tests to see if a constant operand.
377 // If so Imm will receive the 32 bit value.
378 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
379 return isInt32Immediate(N.getNode(), Imm);
383 // isOpcWithIntImmediate - This method tests to see if the node is a specific
384 // opcode and that it has a immediate integer right operand.
385 // If so Imm will receive the 32 bit value.
386 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
387 return N->getOpcode() == Opc
388 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
391 SDNode *PPCDAGToDAGISel::getFrameIndex(SDNode *SN, SDNode *N, unsigned Offset) {
393 int FI = cast<FrameIndexSDNode>(N)->getIndex();
394 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
395 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
397 return CurDAG->SelectNodeTo(SN, Opc, N->getValueType(0), TFI,
398 getSmallIPtrImm(Offset));
399 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
400 getSmallIPtrImm(Offset));
403 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
407 if (isShiftedMask_32(Val)) {
408 // look for the first non-zero bit
409 MB = countLeadingZeros(Val);
410 // look for the first zero bit after the run of ones
411 ME = countLeadingZeros((Val - 1) ^ Val);
414 Val = ~Val; // invert mask
415 if (isShiftedMask_32(Val)) {
416 // effectively look for the first zero bit
417 ME = countLeadingZeros(Val) - 1;
418 // effectively look for the first one bit after the run of zeros
419 MB = countLeadingZeros((Val - 1) ^ Val) + 1;
427 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
428 bool isShiftMask, unsigned &SH,
429 unsigned &MB, unsigned &ME) {
430 // Don't even go down this path for i64, since different logic will be
431 // necessary for rldicl/rldicr/rldimi.
432 if (N->getValueType(0) != MVT::i32)
436 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
437 unsigned Opcode = N->getOpcode();
438 if (N->getNumOperands() != 2 ||
439 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
442 if (Opcode == ISD::SHL) {
443 // apply shift left to mask if it comes first
444 if (isShiftMask) Mask = Mask << Shift;
445 // determine which bits are made indeterminant by shift
446 Indeterminant = ~(0xFFFFFFFFu << Shift);
447 } else if (Opcode == ISD::SRL) {
448 // apply shift right to mask if it comes first
449 if (isShiftMask) Mask = Mask >> Shift;
450 // determine which bits are made indeterminant by shift
451 Indeterminant = ~(0xFFFFFFFFu >> Shift);
452 // adjust for the left rotate
454 } else if (Opcode == ISD::ROTL) {
460 // if the mask doesn't intersect any Indeterminant bits
461 if (Mask && !(Mask & Indeterminant)) {
463 // make sure the mask is still a mask (wrap arounds may not be)
464 return isRunOfOnes(Mask, MB, ME);
469 /// SelectBitfieldInsert - turn an or of two masked values into
470 /// the rotate left word immediate then mask insert (rlwimi) instruction.
471 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
472 SDValue Op0 = N->getOperand(0);
473 SDValue Op1 = N->getOperand(1);
476 APInt LKZ, LKO, RKZ, RKO;
477 CurDAG->computeKnownBits(Op0, LKZ, LKO);
478 CurDAG->computeKnownBits(Op1, RKZ, RKO);
480 unsigned TargetMask = LKZ.getZExtValue();
481 unsigned InsertMask = RKZ.getZExtValue();
483 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
484 unsigned Op0Opc = Op0.getOpcode();
485 unsigned Op1Opc = Op1.getOpcode();
486 unsigned Value, SH = 0;
487 TargetMask = ~TargetMask;
488 InsertMask = ~InsertMask;
490 // If the LHS has a foldable shift and the RHS does not, then swap it to the
491 // RHS so that we can fold the shift into the insert.
492 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
493 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
494 Op0.getOperand(0).getOpcode() == ISD::SRL) {
495 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
496 Op1.getOperand(0).getOpcode() != ISD::SRL) {
498 std::swap(Op0Opc, Op1Opc);
499 std::swap(TargetMask, InsertMask);
502 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
503 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
504 Op1.getOperand(0).getOpcode() != ISD::SRL) {
506 std::swap(Op0Opc, Op1Opc);
507 std::swap(TargetMask, InsertMask);
512 if (isRunOfOnes(InsertMask, MB, ME)) {
515 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
516 isInt32Immediate(Op1.getOperand(1), Value)) {
517 Op1 = Op1.getOperand(0);
518 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
520 if (Op1Opc == ISD::AND) {
521 // The AND mask might not be a constant, and we need to make sure that
522 // if we're going to fold the masking with the insert, all bits not
523 // know to be zero in the mask are known to be one.
525 CurDAG->computeKnownBits(Op1.getOperand(1), MKZ, MKO);
526 bool CanFoldMask = InsertMask == MKO.getZExtValue();
528 unsigned SHOpc = Op1.getOperand(0).getOpcode();
529 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
530 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
531 // Note that Value must be in range here (less than 32) because
532 // otherwise there would not be any bits set in InsertMask.
533 Op1 = Op1.getOperand(0).getOperand(0);
534 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
539 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
541 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
547 // Predict the number of instructions that would be generated by calling
549 static unsigned SelectInt64CountDirect(int64_t Imm) {
550 // Assume no remaining bits.
551 unsigned Remainder = 0;
552 // Assume no shift required.
555 // If it can't be represented as a 32 bit value.
556 if (!isInt<32>(Imm)) {
557 Shift = countTrailingZeros<uint64_t>(Imm);
558 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
560 // If the shifted value fits 32 bits.
561 if (isInt<32>(ImmSh)) {
562 // Go with the shifted value.
565 // Still stuck with a 64 bit value.
572 // Intermediate operand.
575 // Handle first 32 bits.
576 unsigned Lo = Imm & 0xFFFF;
577 unsigned Hi = (Imm >> 16) & 0xFFFF;
580 if (isInt<16>(Imm)) {
584 // Handle the Hi bits and Lo bits.
591 // If no shift, we're done.
592 if (!Shift) return Result;
594 // Shift for next step if the upper 32-bits were not zero.
598 // Add in the last bits as required.
599 if ((Hi = (Remainder >> 16) & 0xFFFF))
601 if ((Lo = Remainder & 0xFFFF))
607 static uint64_t Rot64(uint64_t Imm, unsigned R) {
608 return (Imm << R) | (Imm >> (64 - R));
611 static unsigned SelectInt64Count(int64_t Imm) {
612 unsigned Count = SelectInt64CountDirect(Imm);
616 for (unsigned r = 1; r < 63; ++r) {
617 uint64_t RImm = Rot64(Imm, r);
618 unsigned RCount = SelectInt64CountDirect(RImm) + 1;
619 Count = std::min(Count, RCount);
621 // See comments in SelectInt64 for an explanation of the logic below.
622 unsigned LS = findLastSet(RImm);
626 uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
627 uint64_t RImmWithOnes = RImm | OnesMask;
629 RCount = SelectInt64CountDirect(RImmWithOnes) + 1;
630 Count = std::min(Count, RCount);
636 // Select a 64-bit constant. For cost-modeling purposes, SelectInt64Count
637 // (above) needs to be kept in sync with this function.
638 static SDNode *SelectInt64Direct(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
639 // Assume no remaining bits.
640 unsigned Remainder = 0;
641 // Assume no shift required.
644 // If it can't be represented as a 32 bit value.
645 if (!isInt<32>(Imm)) {
646 Shift = countTrailingZeros<uint64_t>(Imm);
647 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
649 // If the shifted value fits 32 bits.
650 if (isInt<32>(ImmSh)) {
651 // Go with the shifted value.
654 // Still stuck with a 64 bit value.
661 // Intermediate operand.
664 // Handle first 32 bits.
665 unsigned Lo = Imm & 0xFFFF;
666 unsigned Hi = (Imm >> 16) & 0xFFFF;
668 auto getI32Imm = [CurDAG](unsigned Imm) {
669 return CurDAG->getTargetConstant(Imm, MVT::i32);
673 if (isInt<16>(Imm)) {
675 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
677 // Handle the Hi bits.
678 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
679 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
681 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
682 SDValue(Result, 0), getI32Imm(Lo));
685 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
688 // If no shift, we're done.
689 if (!Shift) return Result;
691 // Shift for next step if the upper 32-bits were not zero.
693 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
696 getI32Imm(63 - Shift));
699 // Add in the last bits as required.
700 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
701 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
702 SDValue(Result, 0), getI32Imm(Hi));
704 if ((Lo = Remainder & 0xFFFF)) {
705 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
706 SDValue(Result, 0), getI32Imm(Lo));
712 static SDNode *SelectInt64(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
713 unsigned Count = SelectInt64CountDirect(Imm);
715 return SelectInt64Direct(CurDAG, dl, Imm);
722 for (unsigned r = 1; r < 63; ++r) {
723 uint64_t RImm = Rot64(Imm, r);
724 unsigned RCount = SelectInt64CountDirect(RImm) + 1;
725 if (RCount < Count) {
732 // If the immediate to generate has many trailing zeros, it might be
733 // worthwhile to generate a rotated value with too many leading ones
734 // (because that's free with li/lis's sign-extension semantics), and then
735 // mask them off after rotation.
737 unsigned LS = findLastSet(RImm);
738 // We're adding (63-LS) higher-order ones, and we expect to mask them off
739 // after performing the inverse rotation by (64-r). So we need that:
740 // 63-LS == 64-r => LS == r-1
744 uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
745 uint64_t RImmWithOnes = RImm | OnesMask;
747 RCount = SelectInt64CountDirect(RImmWithOnes) + 1;
748 if (RCount < Count) {
751 MatImm = RImmWithOnes;
757 return SelectInt64Direct(CurDAG, dl, Imm);
759 auto getI32Imm = [CurDAG](unsigned Imm) {
760 return CurDAG->getTargetConstant(Imm, MVT::i32);
763 SDValue Val = SDValue(SelectInt64Direct(CurDAG, dl, MatImm), 0);
764 return CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Val,
765 getI32Imm(64 - RMin), getI32Imm(MaskEnd));
768 // Select a 64-bit constant.
769 static SDNode *SelectInt64(SelectionDAG *CurDAG, SDNode *N) {
773 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
774 return SelectInt64(CurDAG, dl, Imm);
778 class BitPermutationSelector {
782 // The bit number in the value, using a convention where bit 0 is the
791 ValueBit(SDValue V, unsigned I, Kind K = Variable)
792 : V(V), Idx(I), K(K) {}
793 ValueBit(Kind K = Variable)
794 : V(SDValue(nullptr, 0)), Idx(UINT32_MAX), K(K) {}
796 bool isZero() const {
797 return K == ConstZero;
800 bool hasValue() const {
801 return K == Variable;
804 SDValue getValue() const {
805 assert(hasValue() && "Cannot get the value of a constant bit");
809 unsigned getValueBitIndex() const {
810 assert(hasValue() && "Cannot get the value bit index of a constant bit");
815 // A bit group has the same underlying value and the same rotate factor.
819 unsigned StartIdx, EndIdx;
821 // This rotation amount assumes that the lower 32 bits of the quantity are
822 // replicated in the high 32 bits by the rotation operator (which is done
823 // by rlwinm and friends in 64-bit mode).
825 // Did converting to Repl32 == true change the rotation factor? If it did,
826 // it decreased it by 32.
828 // Was this group coalesced after setting Repl32 to true?
829 bool Repl32Coalesced;
831 BitGroup(SDValue V, unsigned R, unsigned S, unsigned E)
832 : V(V), RLAmt(R), StartIdx(S), EndIdx(E), Repl32(false), Repl32CR(false),
833 Repl32Coalesced(false) {
834 DEBUG(dbgs() << "\tbit group for " << V.getNode() << " RLAmt = " << R <<
835 " [" << S << ", " << E << "]\n");
839 // Information on each (Value, RLAmt) pair (like the number of groups
840 // associated with each) used to choose the lowering method.
841 struct ValueRotInfo {
845 unsigned FirstGroupStartIdx;
849 : RLAmt(UINT32_MAX), NumGroups(0), FirstGroupStartIdx(UINT32_MAX),
852 // For sorting (in reverse order) by NumGroups, and then by
853 // FirstGroupStartIdx.
854 bool operator < (const ValueRotInfo &Other) const {
855 // We need to sort so that the non-Repl32 come first because, when we're
856 // doing masking, the Repl32 bit groups might be subsumed into the 64-bit
857 // masking operation.
858 if (Repl32 < Other.Repl32)
860 else if (Repl32 > Other.Repl32)
862 else if (NumGroups > Other.NumGroups)
864 else if (NumGroups < Other.NumGroups)
866 else if (FirstGroupStartIdx < Other.FirstGroupStartIdx)
872 // Return true if something interesting was deduced, return false if we're
873 // providing only a generic representation of V (or something else likewise
874 // uninteresting for instruction selection).
875 bool getValueBits(SDValue V, SmallVector<ValueBit, 64> &Bits) {
876 switch (V.getOpcode()) {
879 if (isa<ConstantSDNode>(V.getOperand(1))) {
880 unsigned RotAmt = V.getConstantOperandVal(1);
882 SmallVector<ValueBit, 64> LHSBits(Bits.size());
883 getValueBits(V.getOperand(0), LHSBits);
885 for (unsigned i = 0; i < Bits.size(); ++i)
886 Bits[i] = LHSBits[i < RotAmt ? i + (Bits.size() - RotAmt) : i - RotAmt];
892 if (isa<ConstantSDNode>(V.getOperand(1))) {
893 unsigned ShiftAmt = V.getConstantOperandVal(1);
895 SmallVector<ValueBit, 64> LHSBits(Bits.size());
896 getValueBits(V.getOperand(0), LHSBits);
898 for (unsigned i = ShiftAmt; i < Bits.size(); ++i)
899 Bits[i] = LHSBits[i - ShiftAmt];
901 for (unsigned i = 0; i < ShiftAmt; ++i)
902 Bits[i] = ValueBit(ValueBit::ConstZero);
908 if (isa<ConstantSDNode>(V.getOperand(1))) {
909 unsigned ShiftAmt = V.getConstantOperandVal(1);
911 SmallVector<ValueBit, 64> LHSBits(Bits.size());
912 getValueBits(V.getOperand(0), LHSBits);
914 for (unsigned i = 0; i < Bits.size() - ShiftAmt; ++i)
915 Bits[i] = LHSBits[i + ShiftAmt];
917 for (unsigned i = Bits.size() - ShiftAmt; i < Bits.size(); ++i)
918 Bits[i] = ValueBit(ValueBit::ConstZero);
924 if (isa<ConstantSDNode>(V.getOperand(1))) {
925 uint64_t Mask = V.getConstantOperandVal(1);
927 SmallVector<ValueBit, 64> LHSBits(Bits.size());
928 bool LHSTrivial = getValueBits(V.getOperand(0), LHSBits);
930 for (unsigned i = 0; i < Bits.size(); ++i)
931 if (((Mask >> i) & 1) == 1)
932 Bits[i] = LHSBits[i];
934 Bits[i] = ValueBit(ValueBit::ConstZero);
936 // Mark this as interesting, only if the LHS was also interesting. This
937 // prevents the overall procedure from matching a single immediate 'and'
938 // (which is non-optimal because such an and might be folded with other
939 // things if we don't select it here).
944 SmallVector<ValueBit, 64> LHSBits(Bits.size()), RHSBits(Bits.size());
945 getValueBits(V.getOperand(0), LHSBits);
946 getValueBits(V.getOperand(1), RHSBits);
948 bool AllDisjoint = true;
949 for (unsigned i = 0; i < Bits.size(); ++i)
950 if (LHSBits[i].isZero())
951 Bits[i] = RHSBits[i];
952 else if (RHSBits[i].isZero())
953 Bits[i] = LHSBits[i];
966 for (unsigned i = 0; i < Bits.size(); ++i)
967 Bits[i] = ValueBit(V, i);
972 // For each value (except the constant ones), compute the left-rotate amount
973 // to get it from its original to final position.
974 void computeRotationAmounts() {
976 RLAmt.resize(Bits.size());
977 for (unsigned i = 0; i < Bits.size(); ++i)
978 if (Bits[i].hasValue()) {
979 unsigned VBI = Bits[i].getValueBitIndex();
983 RLAmt[i] = Bits.size() - (VBI - i);
984 } else if (Bits[i].isZero()) {
986 RLAmt[i] = UINT32_MAX;
988 llvm_unreachable("Unknown value bit type");
992 // Collect groups of consecutive bits with the same underlying value and
993 // rotation factor. If we're doing late masking, we ignore zeros, otherwise
994 // they break up groups.
995 void collectBitGroups(bool LateMask) {
998 unsigned LastRLAmt = RLAmt[0];
999 SDValue LastValue = Bits[0].hasValue() ? Bits[0].getValue() : SDValue();
1000 unsigned LastGroupStartIdx = 0;
1001 for (unsigned i = 1; i < Bits.size(); ++i) {
1002 unsigned ThisRLAmt = RLAmt[i];
1003 SDValue ThisValue = Bits[i].hasValue() ? Bits[i].getValue() : SDValue();
1004 if (LateMask && !ThisValue) {
1005 ThisValue = LastValue;
1006 ThisRLAmt = LastRLAmt;
1007 // If we're doing late masking, then the first bit group always starts
1008 // at zero (even if the first bits were zero).
1009 if (BitGroups.empty())
1010 LastGroupStartIdx = 0;
1013 // If this bit has the same underlying value and the same rotate factor as
1014 // the last one, then they're part of the same group.
1015 if (ThisRLAmt == LastRLAmt && ThisValue == LastValue)
1018 if (LastValue.getNode())
1019 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1021 LastRLAmt = ThisRLAmt;
1022 LastValue = ThisValue;
1023 LastGroupStartIdx = i;
1025 if (LastValue.getNode())
1026 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1029 if (BitGroups.empty())
1032 // We might be able to combine the first and last groups.
1033 if (BitGroups.size() > 1) {
1034 // If the first and last groups are the same, then remove the first group
1035 // in favor of the last group, making the ending index of the last group
1036 // equal to the ending index of the to-be-removed first group.
1037 if (BitGroups[0].StartIdx == 0 &&
1038 BitGroups[BitGroups.size()-1].EndIdx == Bits.size()-1 &&
1039 BitGroups[0].V == BitGroups[BitGroups.size()-1].V &&
1040 BitGroups[0].RLAmt == BitGroups[BitGroups.size()-1].RLAmt) {
1041 DEBUG(dbgs() << "\tcombining final bit group with inital one\n");
1042 BitGroups[BitGroups.size()-1].EndIdx = BitGroups[0].EndIdx;
1043 BitGroups.erase(BitGroups.begin());
1048 // Take all (SDValue, RLAmt) pairs and sort them by the number of groups
1049 // associated with each. If there is a degeneracy, pick the one that occurs
1050 // first (in the final value).
1051 void collectValueRotInfo() {
1054 for (auto &BG : BitGroups) {
1055 unsigned RLAmtKey = BG.RLAmt + (BG.Repl32 ? 64 : 0);
1056 ValueRotInfo &VRI = ValueRots[std::make_pair(BG.V, RLAmtKey)];
1058 VRI.RLAmt = BG.RLAmt;
1059 VRI.Repl32 = BG.Repl32;
1061 VRI.FirstGroupStartIdx = std::min(VRI.FirstGroupStartIdx, BG.StartIdx);
1064 // Now that we've collected the various ValueRotInfo instances, we need to
1066 ValueRotsVec.clear();
1067 for (auto &I : ValueRots) {
1068 ValueRotsVec.push_back(I.second);
1070 std::sort(ValueRotsVec.begin(), ValueRotsVec.end());
1073 // In 64-bit mode, rlwinm and friends have a rotation operator that
1074 // replicates the low-order 32 bits into the high-order 32-bits. The mask
1075 // indices of these instructions can only be in the lower 32 bits, so they
1076 // can only represent some 64-bit bit groups. However, when they can be used,
1077 // the 32-bit replication can be used to represent, as a single bit group,
1078 // otherwise separate bit groups. We'll convert to replicated-32-bit bit
1079 // groups when possible. Returns true if any of the bit groups were
1081 void assignRepl32BitGroups() {
1082 // If we have bits like this:
1084 // Indices: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1085 // V bits: ... 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24
1086 // Groups: | RLAmt = 8 | RLAmt = 40 |
1088 // But, making use of a 32-bit operation that replicates the low-order 32
1089 // bits into the high-order 32 bits, this can be one bit group with a RLAmt
1092 auto IsAllLow32 = [this](BitGroup & BG) {
1093 if (BG.StartIdx <= BG.EndIdx) {
1094 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i) {
1095 if (!Bits[i].hasValue())
1097 if (Bits[i].getValueBitIndex() >= 32)
1101 for (unsigned i = BG.StartIdx; i < Bits.size(); ++i) {
1102 if (!Bits[i].hasValue())
1104 if (Bits[i].getValueBitIndex() >= 32)
1107 for (unsigned i = 0; i <= BG.EndIdx; ++i) {
1108 if (!Bits[i].hasValue())
1110 if (Bits[i].getValueBitIndex() >= 32)
1118 for (auto &BG : BitGroups) {
1119 if (BG.StartIdx < 32 && BG.EndIdx < 32) {
1120 if (IsAllLow32(BG)) {
1121 if (BG.RLAmt >= 32) {
1128 DEBUG(dbgs() << "\t32-bit replicated bit group for " <<
1129 BG.V.getNode() << " RLAmt = " << BG.RLAmt <<
1130 " [" << BG.StartIdx << ", " << BG.EndIdx << "]\n");
1135 // Now walk through the bit groups, consolidating where possible.
1136 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1137 // We might want to remove this bit group by merging it with the previous
1138 // group (which might be the ending group).
1139 auto IP = (I == BitGroups.begin()) ?
1140 std::prev(BitGroups.end()) : std::prev(I);
1141 if (I->Repl32 && IP->Repl32 && I->V == IP->V && I->RLAmt == IP->RLAmt &&
1142 I->StartIdx == (IP->EndIdx + 1) % 64 && I != IP) {
1144 DEBUG(dbgs() << "\tcombining 32-bit replicated bit group for " <<
1145 I->V.getNode() << " RLAmt = " << I->RLAmt <<
1146 " [" << I->StartIdx << ", " << I->EndIdx <<
1147 "] with group with range [" <<
1148 IP->StartIdx << ", " << IP->EndIdx << "]\n");
1150 IP->EndIdx = I->EndIdx;
1151 IP->Repl32CR = IP->Repl32CR || I->Repl32CR;
1152 IP->Repl32Coalesced = true;
1153 I = BitGroups.erase(I);
1156 // There is a special case worth handling: If there is a single group
1157 // covering the entire upper 32 bits, and it can be merged with both
1158 // the next and previous groups (which might be the same group), then
1159 // do so. If it is the same group (so there will be only one group in
1160 // total), then we need to reverse the order of the range so that it
1161 // covers the entire 64 bits.
1162 if (I->StartIdx == 32 && I->EndIdx == 63) {
1163 assert(std::next(I) == BitGroups.end() &&
1164 "bit group ends at index 63 but there is another?");
1165 auto IN = BitGroups.begin();
1167 if (IP->Repl32 && IN->Repl32 && I->V == IP->V && I->V == IN->V &&
1168 (I->RLAmt % 32) == IP->RLAmt && (I->RLAmt % 32) == IN->RLAmt &&
1169 IP->EndIdx == 31 && IN->StartIdx == 0 && I != IP &&
1172 DEBUG(dbgs() << "\tcombining bit group for " <<
1173 I->V.getNode() << " RLAmt = " << I->RLAmt <<
1174 " [" << I->StartIdx << ", " << I->EndIdx <<
1175 "] with 32-bit replicated groups with ranges [" <<
1176 IP->StartIdx << ", " << IP->EndIdx << "] and [" <<
1177 IN->StartIdx << ", " << IN->EndIdx << "]\n");
1180 // There is only one other group; change it to cover the whole
1181 // range (backward, so that it can still be Repl32 but cover the
1182 // whole 64-bit range).
1185 IP->Repl32CR = IP->Repl32CR || I->RLAmt >= 32;
1186 IP->Repl32Coalesced = true;
1187 I = BitGroups.erase(I);
1189 // There are two separate groups, one before this group and one
1190 // after us (at the beginning). We're going to remove this group,
1191 // but also the group at the very beginning.
1192 IP->EndIdx = IN->EndIdx;
1193 IP->Repl32CR = IP->Repl32CR || IN->Repl32CR || I->RLAmt >= 32;
1194 IP->Repl32Coalesced = true;
1195 I = BitGroups.erase(I);
1196 BitGroups.erase(BitGroups.begin());
1199 // This must be the last group in the vector (and we might have
1200 // just invalidated the iterator above), so break here.
1210 SDValue getI32Imm(unsigned Imm) {
1211 return CurDAG->getTargetConstant(Imm, MVT::i32);
1214 uint64_t getZerosMask() {
1216 for (unsigned i = 0; i < Bits.size(); ++i) {
1217 if (Bits[i].hasValue())
1219 Mask |= (UINT64_C(1) << i);
1225 // Depending on the number of groups for a particular value, it might be
1226 // better to rotate, mask explicitly (using andi/andis), and then or the
1227 // result. Select this part of the result first.
1228 void SelectAndParts32(SDLoc dl, SDValue &Res, unsigned *InstCnt) {
1229 if (BPermRewriterNoMasking)
1232 for (ValueRotInfo &VRI : ValueRotsVec) {
1234 for (unsigned i = 0; i < Bits.size(); ++i) {
1235 if (!Bits[i].hasValue() || Bits[i].getValue() != VRI.V)
1237 if (RLAmt[i] != VRI.RLAmt)
1242 // Compute the masks for andi/andis that would be necessary.
1243 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1244 assert((ANDIMask != 0 || ANDISMask != 0) &&
1245 "No set bits in mask for value bit groups");
1246 bool NeedsRotate = VRI.RLAmt != 0;
1248 // We're trying to minimize the number of instructions. If we have one
1249 // group, using one of andi/andis can break even. If we have three
1250 // groups, we can use both andi and andis and break even (to use both
1251 // andi and andis we also need to or the results together). We need four
1252 // groups if we also need to rotate. To use andi/andis we need to do more
1253 // than break even because rotate-and-mask instructions tend to be easier
1256 // FIXME: We've biased here against using andi/andis, which is right for
1257 // POWER cores, but not optimal everywhere. For example, on the A2,
1258 // andi/andis have single-cycle latency whereas the rotate-and-mask
1259 // instructions take two cycles, and it would be better to bias toward
1260 // andi/andis in break-even cases.
1262 unsigned NumAndInsts = (unsigned) NeedsRotate +
1263 (unsigned) (ANDIMask != 0) +
1264 (unsigned) (ANDISMask != 0) +
1265 (unsigned) (ANDIMask != 0 && ANDISMask != 0) +
1266 (unsigned) (bool) Res;
1268 DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode() <<
1269 " RL: " << VRI.RLAmt << ":" <<
1270 "\n\t\t\tisel using masking: " << NumAndInsts <<
1271 " using rotates: " << VRI.NumGroups << "\n");
1273 if (NumAndInsts >= VRI.NumGroups)
1276 DEBUG(dbgs() << "\t\t\t\tusing masking\n");
1278 if (InstCnt) *InstCnt += NumAndInsts;
1283 { VRI.V, getI32Imm(VRI.RLAmt), getI32Imm(0), getI32Imm(31) };
1284 VRot = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
1290 SDValue ANDIVal, ANDISVal;
1292 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1293 VRot, getI32Imm(ANDIMask)), 0);
1295 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1296 VRot, getI32Imm(ANDISMask)), 0);
1300 TotalVal = ANDISVal;
1304 TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1305 ANDIVal, ANDISVal), 0);
1310 Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1313 // Now, remove all groups with this underlying value and rotation
1315 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1316 if (I->V == VRI.V && I->RLAmt == VRI.RLAmt)
1317 I = BitGroups.erase(I);
1324 // Instruction selection for the 32-bit case.
1325 SDNode *Select32(SDNode *N, bool LateMask, unsigned *InstCnt) {
1329 if (InstCnt) *InstCnt = 0;
1331 // Take care of cases that should use andi/andis first.
1332 SelectAndParts32(dl, Res, InstCnt);
1334 // If we've not yet selected a 'starting' instruction, and we have no zeros
1335 // to fill in, select the (Value, RLAmt) with the highest priority (largest
1336 // number of groups), and start with this rotated value.
1337 if ((!HasZeros || LateMask) && !Res) {
1338 ValueRotInfo &VRI = ValueRotsVec[0];
1340 if (InstCnt) *InstCnt += 1;
1342 { VRI.V, getI32Imm(VRI.RLAmt), getI32Imm(0), getI32Imm(31) };
1343 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
1348 // Now, remove all groups with this underlying value and rotation factor.
1349 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1350 if (I->V == VRI.V && I->RLAmt == VRI.RLAmt)
1351 I = BitGroups.erase(I);
1357 if (InstCnt) *InstCnt += BitGroups.size();
1359 // Insert the other groups (one at a time).
1360 for (auto &BG : BitGroups) {
1363 { BG.V, getI32Imm(BG.RLAmt), getI32Imm(Bits.size() - BG.EndIdx - 1),
1364 getI32Imm(Bits.size() - BG.StartIdx - 1) };
1365 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
1368 { Res, BG.V, getI32Imm(BG.RLAmt), getI32Imm(Bits.size() - BG.EndIdx - 1),
1369 getI32Imm(Bits.size() - BG.StartIdx - 1) };
1370 Res = SDValue(CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops), 0);
1375 unsigned Mask = (unsigned) getZerosMask();
1377 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1378 assert((ANDIMask != 0 || ANDISMask != 0) &&
1379 "No set bits in zeros mask?");
1381 if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
1382 (unsigned) (ANDISMask != 0) +
1383 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1385 SDValue ANDIVal, ANDISVal;
1387 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1388 Res, getI32Imm(ANDIMask)), 0);
1390 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1391 Res, getI32Imm(ANDISMask)), 0);
1398 Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1399 ANDIVal, ANDISVal), 0);
1402 return Res.getNode();
1405 unsigned SelectRotMask64Count(unsigned RLAmt, bool Repl32,
1406 unsigned MaskStart, unsigned MaskEnd,
1408 // In the notation used by the instructions, 'start' and 'end' are reversed
1409 // because bits are counted from high to low order.
1410 unsigned InstMaskStart = 64 - MaskEnd - 1,
1411 InstMaskEnd = 64 - MaskStart - 1;
1416 if ((!IsIns && (InstMaskEnd == 63 || InstMaskStart == 0)) ||
1417 InstMaskEnd == 63 - RLAmt)
1423 // For 64-bit values, not all combinations of rotates and masks are
1424 // available. Produce one if it is available.
1425 SDValue SelectRotMask64(SDValue V, SDLoc dl, unsigned RLAmt, bool Repl32,
1426 unsigned MaskStart, unsigned MaskEnd,
1427 unsigned *InstCnt = nullptr) {
1428 // In the notation used by the instructions, 'start' and 'end' are reversed
1429 // because bits are counted from high to low order.
1430 unsigned InstMaskStart = 64 - MaskEnd - 1,
1431 InstMaskEnd = 64 - MaskStart - 1;
1433 if (InstCnt) *InstCnt += 1;
1436 // This rotation amount assumes that the lower 32 bits of the quantity
1437 // are replicated in the high 32 bits by the rotation operator (which is
1438 // done by rlwinm and friends).
1439 assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1440 assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1442 { V, getI32Imm(RLAmt), getI32Imm(InstMaskStart - 32),
1443 getI32Imm(InstMaskEnd - 32) };
1444 return SDValue(CurDAG->getMachineNode(PPC::RLWINM8, dl, MVT::i64,
1448 if (InstMaskEnd == 63) {
1450 { V, getI32Imm(RLAmt), getI32Imm(InstMaskStart) };
1451 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops), 0);
1454 if (InstMaskStart == 0) {
1456 { V, getI32Imm(RLAmt), getI32Imm(InstMaskEnd) };
1457 return SDValue(CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Ops), 0);
1460 if (InstMaskEnd == 63 - RLAmt) {
1462 { V, getI32Imm(RLAmt), getI32Imm(InstMaskStart) };
1463 return SDValue(CurDAG->getMachineNode(PPC::RLDIC, dl, MVT::i64, Ops), 0);
1466 // We cannot do this with a single instruction, so we'll use two. The
1467 // problem is that we're not free to choose both a rotation amount and mask
1468 // start and end independently. We can choose an arbitrary mask start and
1469 // end, but then the rotation amount is fixed. Rotation, however, can be
1470 // inverted, and so by applying an "inverse" rotation first, we can get the
1472 if (InstCnt) *InstCnt += 1;
1474 // The rotation mask for the second instruction must be MaskStart.
1475 unsigned RLAmt2 = MaskStart;
1476 // The first instruction must rotate V so that the overall rotation amount
1478 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1480 V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
1481 return SelectRotMask64(V, dl, RLAmt2, false, MaskStart, MaskEnd);
1484 // For 64-bit values, not all combinations of rotates and masks are
1485 // available. Produce a rotate-mask-and-insert if one is available.
1486 SDValue SelectRotMaskIns64(SDValue Base, SDValue V, SDLoc dl, unsigned RLAmt,
1487 bool Repl32, unsigned MaskStart,
1488 unsigned MaskEnd, unsigned *InstCnt = nullptr) {
1489 // In the notation used by the instructions, 'start' and 'end' are reversed
1490 // because bits are counted from high to low order.
1491 unsigned InstMaskStart = 64 - MaskEnd - 1,
1492 InstMaskEnd = 64 - MaskStart - 1;
1494 if (InstCnt) *InstCnt += 1;
1497 // This rotation amount assumes that the lower 32 bits of the quantity
1498 // are replicated in the high 32 bits by the rotation operator (which is
1499 // done by rlwinm and friends).
1500 assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1501 assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1503 { Base, V, getI32Imm(RLAmt), getI32Imm(InstMaskStart - 32),
1504 getI32Imm(InstMaskEnd - 32) };
1505 return SDValue(CurDAG->getMachineNode(PPC::RLWIMI8, dl, MVT::i64,
1509 if (InstMaskEnd == 63 - RLAmt) {
1511 { Base, V, getI32Imm(RLAmt), getI32Imm(InstMaskStart) };
1512 return SDValue(CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops), 0);
1515 // We cannot do this with a single instruction, so we'll use two. The
1516 // problem is that we're not free to choose both a rotation amount and mask
1517 // start and end independently. We can choose an arbitrary mask start and
1518 // end, but then the rotation amount is fixed. Rotation, however, can be
1519 // inverted, and so by applying an "inverse" rotation first, we can get the
1521 if (InstCnt) *InstCnt += 1;
1523 // The rotation mask for the second instruction must be MaskStart.
1524 unsigned RLAmt2 = MaskStart;
1525 // The first instruction must rotate V so that the overall rotation amount
1527 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1529 V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
1530 return SelectRotMaskIns64(Base, V, dl, RLAmt2, false, MaskStart, MaskEnd);
1533 void SelectAndParts64(SDLoc dl, SDValue &Res, unsigned *InstCnt) {
1534 if (BPermRewriterNoMasking)
1537 // The idea here is the same as in the 32-bit version, but with additional
1538 // complications from the fact that Repl32 might be true. Because we
1539 // aggressively convert bit groups to Repl32 form (which, for small
1540 // rotation factors, involves no other change), and then coalesce, it might
1541 // be the case that a single 64-bit masking operation could handle both
1542 // some Repl32 groups and some non-Repl32 groups. If converting to Repl32
1543 // form allowed coalescing, then we must use a 32-bit rotaton in order to
1544 // completely capture the new combined bit group.
1546 for (ValueRotInfo &VRI : ValueRotsVec) {
1549 // We need to add to the mask all bits from the associated bit groups.
1550 // If Repl32 is false, we need to add bits from bit groups that have
1551 // Repl32 true, but are trivially convertable to Repl32 false. Such a
1552 // group is trivially convertable if it overlaps only with the lower 32
1553 // bits, and the group has not been coalesced.
1554 auto MatchingBG = [VRI](BitGroup &BG) {
1558 unsigned EffRLAmt = BG.RLAmt;
1559 if (!VRI.Repl32 && BG.Repl32) {
1560 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx <= BG.EndIdx &&
1561 !BG.Repl32Coalesced) {
1567 } else if (VRI.Repl32 != BG.Repl32) {
1571 if (VRI.RLAmt != EffRLAmt)
1577 for (auto &BG : BitGroups) {
1578 if (!MatchingBG(BG))
1581 if (BG.StartIdx <= BG.EndIdx) {
1582 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i)
1583 Mask |= (UINT64_C(1) << i);
1585 for (unsigned i = BG.StartIdx; i < Bits.size(); ++i)
1586 Mask |= (UINT64_C(1) << i);
1587 for (unsigned i = 0; i <= BG.EndIdx; ++i)
1588 Mask |= (UINT64_C(1) << i);
1592 // We can use the 32-bit andi/andis technique if the mask does not
1593 // require any higher-order bits. This can save an instruction compared
1594 // to always using the general 64-bit technique.
1595 bool Use32BitInsts = isUInt<32>(Mask);
1596 // Compute the masks for andi/andis that would be necessary.
1597 unsigned ANDIMask = (Mask & UINT16_MAX),
1598 ANDISMask = (Mask >> 16) & UINT16_MAX;
1600 bool NeedsRotate = VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask));
1602 unsigned NumAndInsts = (unsigned) NeedsRotate +
1603 (unsigned) (bool) Res;
1605 NumAndInsts += (unsigned) (ANDIMask != 0) + (unsigned) (ANDISMask != 0) +
1606 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1608 NumAndInsts += SelectInt64Count(Mask) + /* and */ 1;
1610 unsigned NumRLInsts = 0;
1611 bool FirstBG = true;
1612 for (auto &BG : BitGroups) {
1613 if (!MatchingBG(BG))
1616 SelectRotMask64Count(BG.RLAmt, BG.Repl32, BG.StartIdx, BG.EndIdx,
1621 DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode() <<
1622 " RL: " << VRI.RLAmt << (VRI.Repl32 ? " (32):" : ":") <<
1623 "\n\t\t\tisel using masking: " << NumAndInsts <<
1624 " using rotates: " << NumRLInsts << "\n");
1626 // When we'd use andi/andis, we bias toward using the rotates (andi only
1627 // has a record form, and is cracked on POWER cores). However, when using
1628 // general 64-bit constant formation, bias toward the constant form,
1629 // because that exposes more opportunities for CSE.
1630 if (NumAndInsts > NumRLInsts)
1632 if (Use32BitInsts && NumAndInsts == NumRLInsts)
1635 DEBUG(dbgs() << "\t\t\t\tusing masking\n");
1637 if (InstCnt) *InstCnt += NumAndInsts;
1640 // We actually need to generate a rotation if we have a non-zero rotation
1641 // factor or, in the Repl32 case, if we care about any of the
1642 // higher-order replicated bits. In the latter case, we generate a mask
1643 // backward so that it actually includes the entire 64 bits.
1644 if (VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask)))
1645 VRot = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
1646 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63);
1651 if (Use32BitInsts) {
1652 assert((ANDIMask != 0 || ANDISMask != 0) &&
1653 "No set bits in mask when using 32-bit ands for 64-bit value");
1655 SDValue ANDIVal, ANDISVal;
1657 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
1658 VRot, getI32Imm(ANDIMask)), 0);
1660 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
1661 VRot, getI32Imm(ANDISMask)), 0);
1664 TotalVal = ANDISVal;
1668 TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1669 ANDIVal, ANDISVal), 0);
1671 TotalVal = SDValue(SelectInt64(CurDAG, dl, Mask), 0);
1673 SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
1674 VRot, TotalVal), 0);
1680 Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1683 // Now, remove all groups with this underlying value and rotation
1685 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1687 I = BitGroups.erase(I);
1694 // Instruction selection for the 64-bit case.
1695 SDNode *Select64(SDNode *N, bool LateMask, unsigned *InstCnt) {
1699 if (InstCnt) *InstCnt = 0;
1701 // Take care of cases that should use andi/andis first.
1702 SelectAndParts64(dl, Res, InstCnt);
1704 // If we've not yet selected a 'starting' instruction, and we have no zeros
1705 // to fill in, select the (Value, RLAmt) with the highest priority (largest
1706 // number of groups), and start with this rotated value.
1707 if ((!HasZeros || LateMask) && !Res) {
1708 // If we have both Repl32 groups and non-Repl32 groups, the non-Repl32
1709 // groups will come first, and so the VRI representing the largest number
1710 // of groups might not be first (it might be the first Repl32 groups).
1711 unsigned MaxGroupsIdx = 0;
1712 if (!ValueRotsVec[0].Repl32) {
1713 for (unsigned i = 0, ie = ValueRotsVec.size(); i < ie; ++i)
1714 if (ValueRotsVec[i].Repl32) {
1715 if (ValueRotsVec[i].NumGroups > ValueRotsVec[0].NumGroups)
1721 ValueRotInfo &VRI = ValueRotsVec[MaxGroupsIdx];
1722 bool NeedsRotate = false;
1725 } else if (VRI.Repl32) {
1726 for (auto &BG : BitGroups) {
1727 if (BG.V != VRI.V || BG.RLAmt != VRI.RLAmt ||
1728 BG.Repl32 != VRI.Repl32)
1731 // We don't need a rotate if the bit group is confined to the lower
1733 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx < BG.EndIdx)
1742 Res = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
1743 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63,
1748 // Now, remove all groups with this underlying value and rotation factor.
1750 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1751 if (I->V == VRI.V && I->RLAmt == VRI.RLAmt && I->Repl32 == VRI.Repl32)
1752 I = BitGroups.erase(I);
1758 // Because 64-bit rotates are more flexible than inserts, we might have a
1759 // preference regarding which one we do first (to save one instruction).
1761 for (auto I = BitGroups.begin(), IE = BitGroups.end(); I != IE; ++I) {
1762 if (SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
1764 SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
1766 if (I != BitGroups.begin()) {
1769 BitGroups.insert(BitGroups.begin(), BG);
1776 // Insert the other groups (one at a time).
1777 for (auto &BG : BitGroups) {
1779 Res = SelectRotMask64(BG.V, dl, BG.RLAmt, BG.Repl32, BG.StartIdx,
1780 BG.EndIdx, InstCnt);
1782 Res = SelectRotMaskIns64(Res, BG.V, dl, BG.RLAmt, BG.Repl32,
1783 BG.StartIdx, BG.EndIdx, InstCnt);
1787 uint64_t Mask = getZerosMask();
1789 // We can use the 32-bit andi/andis technique if the mask does not
1790 // require any higher-order bits. This can save an instruction compared
1791 // to always using the general 64-bit technique.
1792 bool Use32BitInsts = isUInt<32>(Mask);
1793 // Compute the masks for andi/andis that would be necessary.
1794 unsigned ANDIMask = (Mask & UINT16_MAX),
1795 ANDISMask = (Mask >> 16) & UINT16_MAX;
1797 if (Use32BitInsts) {
1798 assert((ANDIMask != 0 || ANDISMask != 0) &&
1799 "No set bits in mask when using 32-bit ands for 64-bit value");
1801 if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
1802 (unsigned) (ANDISMask != 0) +
1803 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1805 SDValue ANDIVal, ANDISVal;
1807 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
1808 Res, getI32Imm(ANDIMask)), 0);
1810 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
1811 Res, getI32Imm(ANDISMask)), 0);
1818 Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1819 ANDIVal, ANDISVal), 0);
1821 if (InstCnt) *InstCnt += SelectInt64Count(Mask) + /* and */ 1;
1823 SDValue MaskVal = SDValue(SelectInt64(CurDAG, dl, Mask), 0);
1825 SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
1830 return Res.getNode();
1833 SDNode *Select(SDNode *N, bool LateMask, unsigned *InstCnt = nullptr) {
1834 // Fill in BitGroups.
1835 collectBitGroups(LateMask);
1836 if (BitGroups.empty())
1839 // For 64-bit values, figure out when we can use 32-bit instructions.
1840 if (Bits.size() == 64)
1841 assignRepl32BitGroups();
1843 // Fill in ValueRotsVec.
1844 collectValueRotInfo();
1846 if (Bits.size() == 32) {
1847 return Select32(N, LateMask, InstCnt);
1849 assert(Bits.size() == 64 && "Not 64 bits here?");
1850 return Select64(N, LateMask, InstCnt);
1856 SmallVector<ValueBit, 64> Bits;
1859 SmallVector<unsigned, 64> RLAmt;
1861 SmallVector<BitGroup, 16> BitGroups;
1863 DenseMap<std::pair<SDValue, unsigned>, ValueRotInfo> ValueRots;
1864 SmallVector<ValueRotInfo, 16> ValueRotsVec;
1866 SelectionDAG *CurDAG;
1869 BitPermutationSelector(SelectionDAG *DAG)
1872 // Here we try to match complex bit permutations into a set of
1873 // rotate-and-shift/shift/and/or instructions, using a set of heuristics
1874 // known to produce optimial code for common cases (like i32 byte swapping).
1875 SDNode *Select(SDNode *N) {
1876 Bits.resize(N->getValueType(0).getSizeInBits());
1877 if (!getValueBits(SDValue(N, 0), Bits))
1880 DEBUG(dbgs() << "Considering bit-permutation-based instruction"
1881 " selection for: ");
1882 DEBUG(N->dump(CurDAG));
1884 // Fill it RLAmt and set HasZeros.
1885 computeRotationAmounts();
1888 return Select(N, false);
1890 // We currently have two techniques for handling results with zeros: early
1891 // masking (the default) and late masking. Late masking is sometimes more
1892 // efficient, but because the structure of the bit groups is different, it
1893 // is hard to tell without generating both and comparing the results. With
1894 // late masking, we ignore zeros in the resulting value when inserting each
1895 // set of bit groups, and then mask in the zeros at the end. With early
1896 // masking, we only insert the non-zero parts of the result at every step.
1898 unsigned InstCnt, InstCntLateMask;
1899 DEBUG(dbgs() << "\tEarly masking:\n");
1900 SDNode *RN = Select(N, false, &InstCnt);
1901 DEBUG(dbgs() << "\t\tisel would use " << InstCnt << " instructions\n");
1903 DEBUG(dbgs() << "\tLate masking:\n");
1904 SDNode *RNLM = Select(N, true, &InstCntLateMask);
1905 DEBUG(dbgs() << "\t\tisel would use " << InstCntLateMask <<
1908 if (InstCnt <= InstCntLateMask) {
1909 DEBUG(dbgs() << "\tUsing early-masking for isel\n");
1913 DEBUG(dbgs() << "\tUsing late-masking for isel\n");
1917 } // anonymous namespace
1919 SDNode *PPCDAGToDAGISel::SelectBitPermutation(SDNode *N) {
1920 if (N->getValueType(0) != MVT::i32 &&
1921 N->getValueType(0) != MVT::i64)
1924 if (!UseBitPermRewriter)
1927 switch (N->getOpcode()) {
1934 BitPermutationSelector BPS(CurDAG);
1935 return BPS.Select(N);
1942 /// SelectCC - Select a comparison of the specified values with the specified
1943 /// condition code, returning the CR# of the expression.
1944 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
1945 ISD::CondCode CC, SDLoc dl) {
1946 // Always select the LHS.
1949 if (LHS.getValueType() == MVT::i32) {
1951 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1952 if (isInt32Immediate(RHS, Imm)) {
1953 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
1954 if (isUInt<16>(Imm))
1955 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
1956 getI32Imm(Imm & 0xFFFF)), 0);
1957 // If this is a 16-bit signed immediate, fold it.
1958 if (isInt<16>((int)Imm))
1959 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
1960 getI32Imm(Imm & 0xFFFF)), 0);
1962 // For non-equality comparisons, the default code would materialize the
1963 // constant, then compare against it, like this:
1965 // ori r2, r2, 22136
1967 // Since we are just comparing for equality, we can emit this instead:
1968 // xoris r0,r3,0x1234
1969 // cmplwi cr0,r0,0x5678
1971 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
1972 getI32Imm(Imm >> 16)), 0);
1973 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
1974 getI32Imm(Imm & 0xFFFF)), 0);
1977 } else if (ISD::isUnsignedIntSetCC(CC)) {
1978 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
1979 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
1980 getI32Imm(Imm & 0xFFFF)), 0);
1984 if (isIntS16Immediate(RHS, SImm))
1985 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
1986 getI32Imm((int)SImm & 0xFFFF)),
1990 } else if (LHS.getValueType() == MVT::i64) {
1992 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1993 if (isInt64Immediate(RHS.getNode(), Imm)) {
1994 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
1995 if (isUInt<16>(Imm))
1996 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
1997 getI32Imm(Imm & 0xFFFF)), 0);
1998 // If this is a 16-bit signed immediate, fold it.
2000 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
2001 getI32Imm(Imm & 0xFFFF)), 0);
2003 // For non-equality comparisons, the default code would materialize the
2004 // constant, then compare against it, like this:
2006 // ori r2, r2, 22136
2008 // Since we are just comparing for equality, we can emit this instead:
2009 // xoris r0,r3,0x1234
2010 // cmpldi cr0,r0,0x5678
2012 if (isUInt<32>(Imm)) {
2013 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
2014 getI64Imm(Imm >> 16)), 0);
2015 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
2016 getI64Imm(Imm & 0xFFFF)), 0);
2020 } else if (ISD::isUnsignedIntSetCC(CC)) {
2021 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
2022 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
2023 getI64Imm(Imm & 0xFFFF)), 0);
2027 if (isIntS16Immediate(RHS, SImm))
2028 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
2029 getI64Imm(SImm & 0xFFFF)),
2033 } else if (LHS.getValueType() == MVT::f32) {
2036 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
2037 Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
2039 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
2042 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
2048 llvm_unreachable("Should be lowered by legalize!");
2049 default: llvm_unreachable("Unknown condition!");
2051 case ISD::SETEQ: return PPC::PRED_EQ;
2053 case ISD::SETNE: return PPC::PRED_NE;
2055 case ISD::SETLT: return PPC::PRED_LT;
2057 case ISD::SETLE: return PPC::PRED_LE;
2059 case ISD::SETGT: return PPC::PRED_GT;
2061 case ISD::SETGE: return PPC::PRED_GE;
2062 case ISD::SETO: return PPC::PRED_NU;
2063 case ISD::SETUO: return PPC::PRED_UN;
2064 // These two are invalid for floating point. Assume we have int.
2065 case ISD::SETULT: return PPC::PRED_LT;
2066 case ISD::SETUGT: return PPC::PRED_GT;
2070 /// getCRIdxForSetCC - Return the index of the condition register field
2071 /// associated with the SetCC condition, and whether or not the field is
2072 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
2073 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
2076 default: llvm_unreachable("Unknown condition!");
2078 case ISD::SETLT: return 0; // Bit #0 = SETOLT
2080 case ISD::SETGT: return 1; // Bit #1 = SETOGT
2082 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
2083 case ISD::SETUO: return 3; // Bit #3 = SETUO
2085 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
2087 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
2089 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
2090 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
2095 llvm_unreachable("Invalid branch code: should be expanded by legalize");
2096 // These are invalid for floating point. Assume integer.
2097 case ISD::SETULT: return 0;
2098 case ISD::SETUGT: return 1;
2102 // getVCmpInst: return the vector compare instruction for the specified
2103 // vector type and condition code. Since this is for altivec specific code,
2104 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
2105 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC,
2106 bool HasVSX, bool &Swap, bool &Negate) {
2110 if (VecVT.isFloatingPoint()) {
2111 /* Handle some cases by swapping input operands. */
2113 case ISD::SETLE: CC = ISD::SETGE; Swap = true; break;
2114 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
2115 case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break;
2116 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break;
2117 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
2118 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break;
2121 /* Handle some cases by negating the result. */
2123 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
2124 case ISD::SETUNE: CC = ISD::SETOEQ; Negate = true; break;
2125 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break;
2126 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break;
2129 /* We have instructions implementing the remaining cases. */
2133 if (VecVT == MVT::v4f32)
2134 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
2135 else if (VecVT == MVT::v2f64)
2136 return PPC::XVCMPEQDP;
2140 if (VecVT == MVT::v4f32)
2141 return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
2142 else if (VecVT == MVT::v2f64)
2143 return PPC::XVCMPGTDP;
2147 if (VecVT == MVT::v4f32)
2148 return HasVSX ? PPC::XVCMPGESP : PPC::VCMPGEFP;
2149 else if (VecVT == MVT::v2f64)
2150 return PPC::XVCMPGEDP;
2155 llvm_unreachable("Invalid floating-point vector compare condition");
2157 /* Handle some cases by swapping input operands. */
2159 case ISD::SETGE: CC = ISD::SETLE; Swap = true; break;
2160 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
2161 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
2162 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break;
2165 /* Handle some cases by negating the result. */
2167 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
2168 case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break;
2169 case ISD::SETLE: CC = ISD::SETGT; Negate = true; break;
2170 case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break;
2173 /* We have instructions implementing the remaining cases. */
2177 if (VecVT == MVT::v16i8)
2178 return PPC::VCMPEQUB;
2179 else if (VecVT == MVT::v8i16)
2180 return PPC::VCMPEQUH;
2181 else if (VecVT == MVT::v4i32)
2182 return PPC::VCMPEQUW;
2185 if (VecVT == MVT::v16i8)
2186 return PPC::VCMPGTSB;
2187 else if (VecVT == MVT::v8i16)
2188 return PPC::VCMPGTSH;
2189 else if (VecVT == MVT::v4i32)
2190 return PPC::VCMPGTSW;
2193 if (VecVT == MVT::v16i8)
2194 return PPC::VCMPGTUB;
2195 else if (VecVT == MVT::v8i16)
2196 return PPC::VCMPGTUH;
2197 else if (VecVT == MVT::v4i32)
2198 return PPC::VCMPGTUW;
2203 llvm_unreachable("Invalid integer vector compare condition");
2207 SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
2210 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
2211 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
2212 bool isPPC64 = (PtrVT == MVT::i64);
2214 if (!PPCSubTarget->useCRBits() &&
2215 isInt32Immediate(N->getOperand(1), Imm)) {
2216 // We can codegen setcc op, imm very efficiently compared to a brcond.
2217 // Check for those cases here.
2220 SDValue Op = N->getOperand(0);
2224 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
2225 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
2226 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2231 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2232 Op, getI32Imm(~0U)), 0);
2233 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
2237 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2238 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2242 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
2243 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
2244 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2245 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2248 } else if (Imm == ~0U) { // setcc op, -1
2249 SDValue Op = N->getOperand(0);
2254 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2255 Op, getI32Imm(1)), 0);
2256 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
2257 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
2263 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
2264 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2265 Op, getI32Imm(~0U));
2266 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
2267 Op, SDValue(AD, 1));
2270 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
2272 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
2274 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2275 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2278 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2279 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops),
2281 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
2288 SDValue LHS = N->getOperand(0);
2289 SDValue RHS = N->getOperand(1);
2291 // Altivec Vector compare instructions do not set any CR register by default and
2292 // vector compare operations return the same type as the operands.
2293 if (LHS.getValueType().isVector()) {
2294 EVT VecVT = LHS.getValueType();
2296 unsigned int VCmpInst = getVCmpInst(VecVT.getSimpleVT(), CC,
2297 PPCSubTarget->hasVSX(), Swap, Negate);
2299 std::swap(LHS, RHS);
2302 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
2303 return CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR :
2308 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
2311 if (PPCSubTarget->useCRBits())
2315 unsigned Idx = getCRIdxForSetCC(CC, Inv);
2316 SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
2319 // Force the ccreg into CR7.
2320 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
2322 SDValue InFlag(nullptr, 0); // Null incoming flag value.
2323 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
2324 InFlag).getValue(1);
2326 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
2329 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
2330 getI32Imm(31), getI32Imm(31) };
2332 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2334 // Get the specified bit.
2336 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
2337 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
2341 // Select - Convert the specified operand from a target-independent to a
2342 // target-specific node if it hasn't already been changed.
2343 SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
2345 if (N->isMachineOpcode()) {
2347 return nullptr; // Already selected.
2350 // In case any misguided DAG-level optimizations form an ADD with a
2351 // TargetConstant operand, crash here instead of miscompiling (by selecting
2352 // an r+r add instead of some kind of r+i add).
2353 if (N->getOpcode() == ISD::ADD &&
2354 N->getOperand(1).getOpcode() == ISD::TargetConstant)
2355 llvm_unreachable("Invalid ADD with TargetConstant operand");
2357 // Try matching complex bit permutations before doing anything else.
2358 if (SDNode *NN = SelectBitPermutation(N))
2361 switch (N->getOpcode()) {
2364 case ISD::Constant: {
2365 if (N->getValueType(0) == MVT::i64)
2366 return SelectInt64(CurDAG, N);
2371 SDNode *SN = SelectSETCC(N);
2376 case PPCISD::GlobalBaseReg:
2377 return getGlobalBaseReg();
2379 case ISD::FrameIndex:
2380 return getFrameIndex(N, N);
2382 case PPCISD::MFOCRF: {
2383 SDValue InFlag = N->getOperand(1);
2384 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
2385 N->getOperand(0), InFlag);
2388 case PPCISD::READ_TIME_BASE: {
2389 return CurDAG->getMachineNode(PPC::ReadTB, dl, MVT::i32, MVT::i32,
2390 MVT::Other, N->getOperand(0));
2393 case PPCISD::SRA_ADDZE: {
2394 SDValue N0 = N->getOperand(0);
2396 CurDAG->getTargetConstant(*cast<ConstantSDNode>(N->getOperand(1))->
2397 getConstantIntValue(), N->getValueType(0));
2398 if (N->getValueType(0) == MVT::i64) {
2400 CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, MVT::Glue,
2402 return CurDAG->SelectNodeTo(N, PPC::ADDZE8, MVT::i64,
2403 SDValue(Op, 0), SDValue(Op, 1));
2405 assert(N->getValueType(0) == MVT::i32 &&
2406 "Expecting i64 or i32 in PPCISD::SRA_ADDZE");
2408 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
2410 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
2411 SDValue(Op, 0), SDValue(Op, 1));
2416 // Handle preincrement loads.
2417 LoadSDNode *LD = cast<LoadSDNode>(N);
2418 EVT LoadedVT = LD->getMemoryVT();
2420 // Normal loads are handled by code generated from the .td file.
2421 if (LD->getAddressingMode() != ISD::PRE_INC)
2424 SDValue Offset = LD->getOffset();
2425 if (Offset.getOpcode() == ISD::TargetConstant ||
2426 Offset.getOpcode() == ISD::TargetGlobalAddress) {
2429 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
2430 if (LD->getValueType(0) != MVT::i64) {
2431 // Handle PPC32 integer and normal FP loads.
2432 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
2433 switch (LoadedVT.getSimpleVT().SimpleTy) {
2434 default: llvm_unreachable("Invalid PPC load type!");
2435 case MVT::f64: Opcode = PPC::LFDU; break;
2436 case MVT::f32: Opcode = PPC::LFSU; break;
2437 case MVT::i32: Opcode = PPC::LWZU; break;
2438 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
2440 case MVT::i8: Opcode = PPC::LBZU; break;
2443 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
2444 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
2445 switch (LoadedVT.getSimpleVT().SimpleTy) {
2446 default: llvm_unreachable("Invalid PPC load type!");
2447 case MVT::i64: Opcode = PPC::LDU; break;
2448 case MVT::i32: Opcode = PPC::LWZU8; break;
2449 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
2451 case MVT::i8: Opcode = PPC::LBZU8; break;
2455 SDValue Chain = LD->getChain();
2456 SDValue Base = LD->getBasePtr();
2457 SDValue Ops[] = { Offset, Base, Chain };
2458 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
2459 PPCLowering->getPointerTy(),
2463 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
2464 if (LD->getValueType(0) != MVT::i64) {
2465 // Handle PPC32 integer and normal FP loads.
2466 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
2467 switch (LoadedVT.getSimpleVT().SimpleTy) {
2468 default: llvm_unreachable("Invalid PPC load type!");
2469 case MVT::f64: Opcode = PPC::LFDUX; break;
2470 case MVT::f32: Opcode = PPC::LFSUX; break;
2471 case MVT::i32: Opcode = PPC::LWZUX; break;
2472 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
2474 case MVT::i8: Opcode = PPC::LBZUX; break;
2477 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
2478 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) &&
2479 "Invalid sext update load");
2480 switch (LoadedVT.getSimpleVT().SimpleTy) {
2481 default: llvm_unreachable("Invalid PPC load type!");
2482 case MVT::i64: Opcode = PPC::LDUX; break;
2483 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
2484 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
2486 case MVT::i8: Opcode = PPC::LBZUX8; break;
2490 SDValue Chain = LD->getChain();
2491 SDValue Base = LD->getBasePtr();
2492 SDValue Ops[] = { Base, Offset, Chain };
2493 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
2494 PPCLowering->getPointerTy(),
2500 unsigned Imm, Imm2, SH, MB, ME;
2503 // If this is an and of a value rotated between 0 and 31 bits and then and'd
2504 // with a mask, emit rlwinm
2505 if (isInt32Immediate(N->getOperand(1), Imm) &&
2506 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
2507 SDValue Val = N->getOperand(0).getOperand(0);
2508 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
2509 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2511 // If this is just a masked value where the input is not handled above, and
2512 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
2513 if (isInt32Immediate(N->getOperand(1), Imm) &&
2514 isRunOfOnes(Imm, MB, ME) &&
2515 N->getOperand(0).getOpcode() != ISD::ROTL) {
2516 SDValue Val = N->getOperand(0);
2517 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
2518 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2520 // If this is a 64-bit zero-extension mask, emit rldicl.
2521 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
2523 SDValue Val = N->getOperand(0);
2524 MB = 64 - CountTrailingOnes_64(Imm64);
2527 // If the operand is a logical right shift, we can fold it into this
2528 // instruction: rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb)
2529 // for n <= mb. The right shift is really a left rotate followed by a
2530 // mask, and this mask is a more-restrictive sub-mask of the mask implied
2532 if (Val.getOpcode() == ISD::SRL &&
2533 isInt32Immediate(Val.getOperand(1).getNode(), Imm) && Imm <= MB) {
2534 assert(Imm < 64 && "Illegal shift amount");
2535 Val = Val.getOperand(0);
2539 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB) };
2540 return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
2542 // AND X, 0 -> 0, not "rlwinm 32".
2543 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
2544 ReplaceUses(SDValue(N, 0), N->getOperand(1));
2547 // ISD::OR doesn't get all the bitfield insertion fun.
2548 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
2549 if (isInt32Immediate(N->getOperand(1), Imm) &&
2550 N->getOperand(0).getOpcode() == ISD::OR &&
2551 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
2554 if (isRunOfOnes(Imm, MB, ME)) {
2555 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2556 N->getOperand(0).getOperand(1),
2557 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
2558 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
2562 // Other cases are autogenerated.
2566 if (N->getValueType(0) == MVT::i32)
2567 if (SDNode *I = SelectBitfieldInsert(N))
2571 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
2572 isIntS16Immediate(N->getOperand(1), Imm)) {
2573 APInt LHSKnownZero, LHSKnownOne;
2574 CurDAG->computeKnownBits(N->getOperand(0), LHSKnownZero, LHSKnownOne);
2576 // If this is equivalent to an add, then we can fold it with the
2577 // FrameIndex calculation.
2578 if ((LHSKnownZero.getZExtValue()|~(uint64_t)Imm) == ~0ULL)
2579 return getFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
2582 // Other cases are autogenerated.
2587 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
2588 isIntS16Immediate(N->getOperand(1), Imm))
2589 return getFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
2594 unsigned Imm, SH, MB, ME;
2595 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
2596 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
2597 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2598 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
2599 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2602 // Other cases are autogenerated.
2606 unsigned Imm, SH, MB, ME;
2607 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
2608 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
2609 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2610 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
2611 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2614 // Other cases are autogenerated.
2617 // FIXME: Remove this once the ANDI glue bug is fixed:
2618 case PPCISD::ANDIo_1_EQ_BIT:
2619 case PPCISD::ANDIo_1_GT_BIT: {
2623 EVT InVT = N->getOperand(0).getValueType();
2624 assert((InVT == MVT::i64 || InVT == MVT::i32) &&
2625 "Invalid input type for ANDIo_1_EQ_BIT");
2627 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
2628 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
2630 CurDAG->getTargetConstant(1, InVT)), 0);
2631 SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
2633 CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
2634 PPC::sub_eq : PPC::sub_gt, MVT::i32);
2636 return CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1,
2638 SDValue(AndI.getNode(), 1) /* glue */);
2640 case ISD::SELECT_CC: {
2641 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
2642 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
2643 bool isPPC64 = (PtrVT == MVT::i64);
2645 // If this is a select of i1 operands, we'll pattern match it.
2646 if (PPCSubTarget->useCRBits() &&
2647 N->getOperand(0).getValueType() == MVT::i1)
2650 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
2652 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2653 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
2654 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
2655 if (N1C->isNullValue() && N3C->isNullValue() &&
2656 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
2657 // FIXME: Implement this optzn for PPC64.
2658 N->getValueType(0) == MVT::i32) {
2660 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2661 N->getOperand(0), getI32Imm(~0U));
2662 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
2663 SDValue(Tmp, 0), N->getOperand(0),
2667 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
2669 if (N->getValueType(0) == MVT::i1) {
2670 // An i1 select is: (c & t) | (!c & f).
2672 unsigned Idx = getCRIdxForSetCC(CC, Inv);
2676 default: llvm_unreachable("Invalid CC index");
2677 case 0: SRI = PPC::sub_lt; break;
2678 case 1: SRI = PPC::sub_gt; break;
2679 case 2: SRI = PPC::sub_eq; break;
2680 case 3: SRI = PPC::sub_un; break;
2683 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg);
2685 SDValue NotCCBit(CurDAG->getMachineNode(PPC::CRNOR, dl, MVT::i1,
2687 SDValue C = Inv ? NotCCBit : CCBit,
2688 NotC = Inv ? CCBit : NotCCBit;
2690 SDValue CAndT(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
2691 C, N->getOperand(2)), 0);
2692 SDValue NotCAndF(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
2693 NotC, N->getOperand(3)), 0);
2695 return CurDAG->SelectNodeTo(N, PPC::CROR, MVT::i1, CAndT, NotCAndF);
2698 unsigned BROpc = getPredicateForSetCC(CC);
2700 unsigned SelectCCOp;
2701 if (N->getValueType(0) == MVT::i32)
2702 SelectCCOp = PPC::SELECT_CC_I4;
2703 else if (N->getValueType(0) == MVT::i64)
2704 SelectCCOp = PPC::SELECT_CC_I8;
2705 else if (N->getValueType(0) == MVT::f32)
2706 SelectCCOp = PPC::SELECT_CC_F4;
2707 else if (N->getValueType(0) == MVT::f64)
2708 if (PPCSubTarget->hasVSX())
2709 SelectCCOp = PPC::SELECT_CC_VSFRC;
2711 SelectCCOp = PPC::SELECT_CC_F8;
2712 else if (N->getValueType(0) == MVT::v2f64 ||
2713 N->getValueType(0) == MVT::v2i64)
2714 SelectCCOp = PPC::SELECT_CC_VSRC;
2716 SelectCCOp = PPC::SELECT_CC_VRRC;
2718 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
2720 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
2723 if (PPCSubTarget->hasVSX()) {
2724 SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) };
2725 return CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops);
2729 case ISD::VECTOR_SHUFFLE:
2730 if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
2731 N->getValueType(0) == MVT::v2i64)) {
2732 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
2734 SDValue Op1 = N->getOperand(SVN->getMaskElt(0) < 2 ? 0 : 1),
2735 Op2 = N->getOperand(SVN->getMaskElt(1) < 2 ? 0 : 1);
2738 for (int i = 0; i < 2; ++i)
2739 if (SVN->getMaskElt(i) <= 0 || SVN->getMaskElt(i) == 2)
2744 // For little endian, we must swap the input operands and adjust
2745 // the mask elements (reverse and invert them).
2746 if (PPCSubTarget->isLittleEndian()) {
2747 std::swap(Op1, Op2);
2748 unsigned tmp = DM[0];
2753 SDValue DMV = CurDAG->getTargetConstant(DM[1] | (DM[0] << 1), MVT::i32);
2755 if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 &&
2756 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
2757 isa<LoadSDNode>(Op1.getOperand(0))) {
2758 LoadSDNode *LD = cast<LoadSDNode>(Op1.getOperand(0));
2759 SDValue Base, Offset;
2761 if (LD->isUnindexed() &&
2762 SelectAddrIdxOnly(LD->getBasePtr(), Base, Offset)) {
2763 SDValue Chain = LD->getChain();
2764 SDValue Ops[] = { Base, Offset, Chain };
2765 return CurDAG->SelectNodeTo(N, PPC::LXVDSX,
2766 N->getValueType(0), Ops);
2770 SDValue Ops[] = { Op1, Op2, DMV };
2771 return CurDAG->SelectNodeTo(N, PPC::XXPERMDI, N->getValueType(0), Ops);
2777 bool IsPPC64 = PPCSubTarget->isPPC64();
2778 SDValue Ops[] = { N->getOperand(1), N->getOperand(0) };
2779 return CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ ?
2780 (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
2781 (IsPPC64 ? PPC::BDZ8 : PPC::BDZ),
2784 case PPCISD::COND_BRANCH: {
2785 // Op #0 is the Chain.
2786 // Op #1 is the PPC::PRED_* number.
2788 // Op #3 is the Dest MBB
2789 // Op #4 is the Flag.
2790 // Prevent PPC::PRED_* from being selected into LI.
2792 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
2793 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
2794 N->getOperand(0), N->getOperand(4) };
2795 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
2798 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
2799 unsigned PCC = getPredicateForSetCC(CC);
2801 if (N->getOperand(2).getValueType() == MVT::i1) {
2805 default: llvm_unreachable("Unexpected Boolean-operand predicate");
2806 case PPC::PRED_LT: Opc = PPC::CRANDC; Swap = true; break;
2807 case PPC::PRED_LE: Opc = PPC::CRORC; Swap = true; break;
2808 case PPC::PRED_EQ: Opc = PPC::CREQV; Swap = false; break;
2809 case PPC::PRED_GE: Opc = PPC::CRORC; Swap = false; break;
2810 case PPC::PRED_GT: Opc = PPC::CRANDC; Swap = false; break;
2811 case PPC::PRED_NE: Opc = PPC::CRXOR; Swap = false; break;
2814 SDValue BitComp(CurDAG->getMachineNode(Opc, dl, MVT::i1,
2815 N->getOperand(Swap ? 3 : 2),
2816 N->getOperand(Swap ? 2 : 3)), 0);
2817 return CurDAG->SelectNodeTo(N, PPC::BC, MVT::Other,
2818 BitComp, N->getOperand(4), N->getOperand(0));
2821 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
2822 SDValue Ops[] = { getI32Imm(PCC), CondCode,
2823 N->getOperand(4), N->getOperand(0) };
2824 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
2827 // FIXME: Should custom lower this.
2828 SDValue Chain = N->getOperand(0);
2829 SDValue Target = N->getOperand(1);
2830 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
2831 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
2832 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
2834 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
2836 case PPCISD::TOC_ENTRY: {
2837 assert ((PPCSubTarget->isPPC64() || PPCSubTarget->isSVR4ABI()) &&
2838 "Only supported for 64-bit ABI and 32-bit SVR4");
2839 if (PPCSubTarget->isSVR4ABI() && !PPCSubTarget->isPPC64()) {
2840 SDValue GA = N->getOperand(0);
2841 return CurDAG->getMachineNode(PPC::LWZtoc, dl, MVT::i32, GA,
2845 // For medium and large code model, we generate two instructions as
2846 // described below. Otherwise we allow SelectCodeCommon to handle this,
2847 // selecting one of LDtoc, LDtocJTI, LDtocCPT, and LDtocBA.
2848 CodeModel::Model CModel = TM.getCodeModel();
2849 if (CModel != CodeModel::Medium && CModel != CodeModel::Large)
2852 // The first source operand is a TargetGlobalAddress or a TargetJumpTable.
2853 // If it is an externally defined symbol, a symbol with common linkage,
2854 // a non-local function address, or a jump table address, or if we are
2855 // generating code for large code model, we generate:
2856 // LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>))
2857 // Otherwise we generate:
2858 // ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>)
2859 SDValue GA = N->getOperand(0);
2860 SDValue TOCbase = N->getOperand(1);
2861 SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
2864 if (isa<JumpTableSDNode>(GA) || isa<BlockAddressSDNode>(GA) ||
2865 CModel == CodeModel::Large)
2866 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
2869 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) {
2870 const GlobalValue *GValue = G->getGlobal();
2871 if ((GValue->getType()->getElementType()->isFunctionTy() &&
2872 (GValue->isDeclaration() || GValue->isWeakForLinker())) ||
2873 GValue->isDeclaration() || GValue->hasCommonLinkage() ||
2874 GValue->hasAvailableExternallyLinkage())
2875 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
2879 return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
2880 SDValue(Tmp, 0), GA);
2882 case PPCISD::PPC32_PICGOT: {
2883 // Generate a PIC-safe GOT reference.
2884 assert(!PPCSubTarget->isPPC64() && PPCSubTarget->isSVR4ABI() &&
2885 "PPCISD::PPC32_PICGOT is only supported for 32-bit SVR4");
2886 return CurDAG->SelectNodeTo(N, PPC::PPC32PICGOT, PPCLowering->getPointerTy(), MVT::i32);
2888 case PPCISD::VADD_SPLAT: {
2889 // This expands into one of three sequences, depending on whether
2890 // the first operand is odd or even, positive or negative.
2891 assert(isa<ConstantSDNode>(N->getOperand(0)) &&
2892 isa<ConstantSDNode>(N->getOperand(1)) &&
2893 "Invalid operand on VADD_SPLAT!");
2895 int Elt = N->getConstantOperandVal(0);
2896 int EltSize = N->getConstantOperandVal(1);
2897 unsigned Opc1, Opc2, Opc3;
2901 Opc1 = PPC::VSPLTISB;
2902 Opc2 = PPC::VADDUBM;
2903 Opc3 = PPC::VSUBUBM;
2905 } else if (EltSize == 2) {
2906 Opc1 = PPC::VSPLTISH;
2907 Opc2 = PPC::VADDUHM;
2908 Opc3 = PPC::VSUBUHM;
2911 assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!");
2912 Opc1 = PPC::VSPLTISW;
2913 Opc2 = PPC::VADDUWM;
2914 Opc3 = PPC::VSUBUWM;
2918 if ((Elt & 1) == 0) {
2919 // Elt is even, in the range [-32,-18] + [16,30].
2921 // Convert: VADD_SPLAT elt, size
2922 // Into: tmp = VSPLTIS[BHW] elt
2923 // VADDU[BHW]M tmp, tmp
2924 // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4
2925 SDValue EltVal = getI32Imm(Elt >> 1);
2926 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2927 SDValue TmpVal = SDValue(Tmp, 0);
2928 return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal);
2930 } else if (Elt > 0) {
2931 // Elt is odd and positive, in the range [17,31].
2933 // Convert: VADD_SPLAT elt, size
2934 // Into: tmp1 = VSPLTIS[BHW] elt-16
2935 // tmp2 = VSPLTIS[BHW] -16
2936 // VSUBU[BHW]M tmp1, tmp2
2937 SDValue EltVal = getI32Imm(Elt - 16);
2938 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2939 EltVal = getI32Imm(-16);
2940 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2941 return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
2945 // Elt is odd and negative, in the range [-31,-17].
2947 // Convert: VADD_SPLAT elt, size
2948 // Into: tmp1 = VSPLTIS[BHW] elt+16
2949 // tmp2 = VSPLTIS[BHW] -16
2950 // VADDU[BHW]M tmp1, tmp2
2951 SDValue EltVal = getI32Imm(Elt + 16);
2952 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2953 EltVal = getI32Imm(-16);
2954 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2955 return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
2961 return SelectCode(N);
2964 // If the target supports the cmpb instruction, do the idiom recognition here.
2965 // We don't do this as a DAG combine because we don't want to do it as nodes
2966 // are being combined (because we might miss part of the eventual idiom). We
2967 // don't want to do it during instruction selection because we want to reuse
2968 // the logic for lowering the masking operations already part of the
2969 // instruction selector.
2970 SDValue PPCDAGToDAGISel::combineToCMPB(SDNode *N) {
2973 assert(N->getOpcode() == ISD::OR &&
2974 "Only OR nodes are supported for CMPB");
2977 if (!PPCSubTarget->hasCMPB())
2980 if (N->getValueType(0) != MVT::i32 &&
2981 N->getValueType(0) != MVT::i64)
2984 EVT VT = N->getValueType(0);
2987 bool BytesFound[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
2988 uint64_t Mask = 0, Alt = 0;
2990 auto IsByteSelectCC = [this](SDValue O, unsigned &b,
2991 uint64_t &Mask, uint64_t &Alt,
2992 SDValue &LHS, SDValue &RHS) {
2993 if (O.getOpcode() != ISD::SELECT_CC)
2995 ISD::CondCode CC = cast<CondCodeSDNode>(O.getOperand(4))->get();
2997 if (!isa<ConstantSDNode>(O.getOperand(2)) ||
2998 !isa<ConstantSDNode>(O.getOperand(3)))
3001 uint64_t PM = O.getConstantOperandVal(2);
3002 uint64_t PAlt = O.getConstantOperandVal(3);
3003 for (b = 0; b < 8; ++b) {
3004 uint64_t Mask = UINT64_C(0xFF) << (8*b);
3005 if (PM && (PM & Mask) == PM && (PAlt & Mask) == PAlt)
3014 if (!isa<ConstantSDNode>(O.getOperand(1)) ||
3015 O.getConstantOperandVal(1) != 0) {
3016 SDValue Op0 = O.getOperand(0), Op1 = O.getOperand(1);
3017 if (Op0.getOpcode() == ISD::TRUNCATE)
3018 Op0 = Op0.getOperand(0);
3019 if (Op1.getOpcode() == ISD::TRUNCATE)
3020 Op1 = Op1.getOperand(0);
3022 if (Op0.getOpcode() == ISD::SRL && Op1.getOpcode() == ISD::SRL &&
3023 Op0.getOperand(1) == Op1.getOperand(1) && CC == ISD::SETEQ &&
3024 isa<ConstantSDNode>(Op0.getOperand(1))) {
3026 unsigned Bits = Op0.getValueType().getSizeInBits();
3029 if (Op0.getConstantOperandVal(1) != Bits-8)
3032 LHS = Op0.getOperand(0);
3033 RHS = Op1.getOperand(0);
3037 // When we have small integers (i16 to be specific), the form present
3038 // post-legalization uses SETULT in the SELECT_CC for the
3039 // higher-order byte, depending on the fact that the
3040 // even-higher-order bytes are known to all be zero, for example:
3041 // select_cc (xor $lhs, $rhs), 256, 65280, 0, setult
3042 // (so when the second byte is the same, because all higher-order
3043 // bits from bytes 3 and 4 are known to be zero, the result of the
3044 // xor can be at most 255)
3045 if (Op0.getOpcode() == ISD::XOR && CC == ISD::SETULT &&
3046 isa<ConstantSDNode>(O.getOperand(1))) {
3048 uint64_t ULim = O.getConstantOperandVal(1);
3049 if (ULim != (UINT64_C(1) << b*8))
3052 // Now we need to make sure that the upper bytes are known to be
3054 unsigned Bits = Op0.getValueType().getSizeInBits();
3055 if (!CurDAG->MaskedValueIsZero(Op0,
3056 APInt::getHighBitsSet(Bits, Bits - (b+1)*8)))
3059 LHS = Op0.getOperand(0);
3060 RHS = Op0.getOperand(1);
3067 if (CC != ISD::SETEQ)
3070 SDValue Op = O.getOperand(0);
3071 if (Op.getOpcode() == ISD::AND) {
3072 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3074 if (Op.getConstantOperandVal(1) != (UINT64_C(0xFF) << (8*b)))
3077 SDValue XOR = Op.getOperand(0);
3078 if (XOR.getOpcode() == ISD::TRUNCATE)
3079 XOR = XOR.getOperand(0);
3080 if (XOR.getOpcode() != ISD::XOR)
3083 LHS = XOR.getOperand(0);
3084 RHS = XOR.getOperand(1);
3086 } else if (Op.getOpcode() == ISD::SRL) {
3087 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3089 unsigned Bits = Op.getValueType().getSizeInBits();
3092 if (Op.getConstantOperandVal(1) != Bits-8)
3095 SDValue XOR = Op.getOperand(0);
3096 if (XOR.getOpcode() == ISD::TRUNCATE)
3097 XOR = XOR.getOperand(0);
3098 if (XOR.getOpcode() != ISD::XOR)
3101 LHS = XOR.getOperand(0);
3102 RHS = XOR.getOperand(1);
3109 SmallVector<SDValue, 8> Queue(1, SDValue(N, 0));
3110 while (!Queue.empty()) {
3111 SDValue V = Queue.pop_back_val();
3113 for (const SDValue &O : V.getNode()->ops()) {
3115 uint64_t M = 0, A = 0;
3117 if (O.getOpcode() == ISD::OR) {
3119 } else if (IsByteSelectCC(O, b, M, A, OLHS, ORHS)) {
3123 BytesFound[b] = true;
3126 } else if ((LHS == ORHS && RHS == OLHS) ||
3127 (RHS == ORHS && LHS == OLHS)) {
3128 BytesFound[b] = true;
3140 unsigned LastB = 0, BCnt = 0;
3141 for (unsigned i = 0; i < 8; ++i)
3142 if (BytesFound[LastB]) {
3147 if (!LastB || BCnt < 2)
3150 // Because we'll be zero-extending the output anyway if don't have a specific
3151 // value for each input byte (via the Mask), we can 'anyext' the inputs.
3152 if (LHS.getValueType() != VT) {
3153 LHS = CurDAG->getAnyExtOrTrunc(LHS, dl, VT);
3154 RHS = CurDAG->getAnyExtOrTrunc(RHS, dl, VT);
3157 Res = CurDAG->getNode(PPCISD::CMPB, dl, VT, LHS, RHS);
3159 bool NonTrivialMask = ((int64_t) Mask) != INT64_C(-1);
3160 if (NonTrivialMask && !Alt) {
3161 // Res = Mask & CMPB
3162 Res = CurDAG->getNode(ISD::AND, dl, VT, Res, CurDAG->getConstant(Mask, VT));
3164 // Res = (CMPB & Mask) | (~CMPB & Alt)
3165 // Which, as suggested here:
3166 // https://graphics.stanford.edu/~seander/bithacks.html#MaskedMerge
3167 // can be written as:
3168 // Res = Alt ^ ((Alt ^ Mask) & CMPB)
3169 // useful because the (Alt ^ Mask) can be pre-computed.
3170 Res = CurDAG->getNode(ISD::AND, dl, VT, Res,
3171 CurDAG->getConstant(Mask ^ Alt, VT));
3172 Res = CurDAG->getNode(ISD::XOR, dl, VT, Res, CurDAG->getConstant(Alt, VT));
3178 // When CR bit registers are enabled, an extension of an i1 variable to a i32
3179 // or i64 value is lowered in terms of a SELECT_I[48] operation, and thus
3180 // involves constant materialization of a 0 or a 1 or both. If the result of
3181 // the extension is then operated upon by some operator that can be constant
3182 // folded with a constant 0 or 1, and that constant can be materialized using
3183 // only one instruction (like a zero or one), then we should fold in those
3184 // operations with the select.
3185 void PPCDAGToDAGISel::foldBoolExts(SDValue &Res, SDNode *&N) {
3186 if (!PPCSubTarget->useCRBits())
3189 if (N->getOpcode() != ISD::ZERO_EXTEND &&
3190 N->getOpcode() != ISD::SIGN_EXTEND &&
3191 N->getOpcode() != ISD::ANY_EXTEND)
3194 if (N->getOperand(0).getValueType() != MVT::i1)
3197 if (!N->hasOneUse())
3201 EVT VT = N->getValueType(0);
3202 SDValue Cond = N->getOperand(0);
3204 CurDAG->getConstant(N->getOpcode() == ISD::SIGN_EXTEND ? -1 : 1, VT);
3205 SDValue ConstFalse = CurDAG->getConstant(0, VT);
3208 SDNode *User = *N->use_begin();
3209 if (User->getNumOperands() != 2)
3212 auto TryFold = [this, N, User](SDValue Val) {
3213 SDValue UserO0 = User->getOperand(0), UserO1 = User->getOperand(1);
3214 SDValue O0 = UserO0.getNode() == N ? Val : UserO0;
3215 SDValue O1 = UserO1.getNode() == N ? Val : UserO1;
3217 return CurDAG->FoldConstantArithmetic(User->getOpcode(),
3218 User->getValueType(0),
3219 O0.getNode(), O1.getNode());
3222 SDValue TrueRes = TryFold(ConstTrue);
3225 SDValue FalseRes = TryFold(ConstFalse);
3229 // For us to materialize these using one instruction, we must be able to
3230 // represent them as signed 16-bit integers.
3231 uint64_t True = cast<ConstantSDNode>(TrueRes)->getZExtValue(),
3232 False = cast<ConstantSDNode>(FalseRes)->getZExtValue();
3233 if (!isInt<16>(True) || !isInt<16>(False))
3236 // We can replace User with a new SELECT node, and try again to see if we
3237 // can fold the select with its user.
3238 Res = CurDAG->getSelect(dl, User->getValueType(0), Cond, TrueRes, FalseRes);
3240 ConstTrue = TrueRes;
3241 ConstFalse = FalseRes;
3242 } while (N->hasOneUse());
3245 void PPCDAGToDAGISel::PreprocessISelDAG() {
3246 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
3249 bool MadeChange = false;
3250 while (Position != CurDAG->allnodes_begin()) {
3251 SDNode *N = --Position;
3256 switch (N->getOpcode()) {
3259 Res = combineToCMPB(N);
3264 foldBoolExts(Res, N);
3267 DEBUG(dbgs() << "PPC DAG preprocessing replacing:\nOld: ");
3268 DEBUG(N->dump(CurDAG));
3269 DEBUG(dbgs() << "\nNew: ");
3270 DEBUG(Res.getNode()->dump(CurDAG));
3271 DEBUG(dbgs() << "\n");
3273 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Res);
3279 CurDAG->RemoveDeadNodes();
3282 /// PostprocessISelDAG - Perform some late peephole optimizations
3283 /// on the DAG representation.
3284 void PPCDAGToDAGISel::PostprocessISelDAG() {
3286 // Skip peepholes at -O0.
3287 if (TM.getOptLevel() == CodeGenOpt::None)
3292 PeepholePPC64ZExt();
3295 // Check if all users of this node will become isel where the second operand
3296 // is the constant zero. If this is so, and if we can negate the condition,
3297 // then we can flip the true and false operands. This will allow the zero to
3298 // be folded with the isel so that we don't need to materialize a register
3300 bool PPCDAGToDAGISel::AllUsersSelectZero(SDNode *N) {
3301 // If we're not using isel, then this does not matter.
3302 if (!PPCSubTarget->hasISEL())
3305 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3308 if (!User->isMachineOpcode())
3310 if (User->getMachineOpcode() != PPC::SELECT_I4 &&
3311 User->getMachineOpcode() != PPC::SELECT_I8)
3314 SDNode *Op2 = User->getOperand(2).getNode();
3315 if (!Op2->isMachineOpcode())
3318 if (Op2->getMachineOpcode() != PPC::LI &&
3319 Op2->getMachineOpcode() != PPC::LI8)
3322 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2->getOperand(0));
3326 if (!C->isNullValue())
3333 void PPCDAGToDAGISel::SwapAllSelectUsers(SDNode *N) {
3334 SmallVector<SDNode *, 4> ToReplace;
3335 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3338 assert((User->getMachineOpcode() == PPC::SELECT_I4 ||
3339 User->getMachineOpcode() == PPC::SELECT_I8) &&
3340 "Must have all select users");
3341 ToReplace.push_back(User);
3344 for (SmallVector<SDNode *, 4>::iterator UI = ToReplace.begin(),
3345 UE = ToReplace.end(); UI != UE; ++UI) {
3348 CurDAG->getMachineNode(User->getMachineOpcode(), SDLoc(User),
3349 User->getValueType(0), User->getOperand(0),
3350 User->getOperand(2),
3351 User->getOperand(1));
3353 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
3354 DEBUG(User->dump(CurDAG));
3355 DEBUG(dbgs() << "\nNew: ");
3356 DEBUG(ResNode->dump(CurDAG));
3357 DEBUG(dbgs() << "\n");
3359 ReplaceUses(User, ResNode);
3363 void PPCDAGToDAGISel::PeepholeCROps() {
3367 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
3368 E = CurDAG->allnodes_end(); I != E; ++I) {
3369 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
3370 if (!MachineNode || MachineNode->use_empty())
3372 SDNode *ResNode = MachineNode;
3374 bool Op1Set = false, Op1Unset = false,
3376 Op2Set = false, Op2Unset = false,
3379 unsigned Opcode = MachineNode->getMachineOpcode();
3390 SDValue Op = MachineNode->getOperand(1);
3391 if (Op.isMachineOpcode()) {
3392 if (Op.getMachineOpcode() == PPC::CRSET)
3394 else if (Op.getMachineOpcode() == PPC::CRUNSET)
3396 else if (Op.getMachineOpcode() == PPC::CRNOR &&
3397 Op.getOperand(0) == Op.getOperand(1))
3403 case PPC::SELECT_I4:
3404 case PPC::SELECT_I8:
3405 case PPC::SELECT_F4:
3406 case PPC::SELECT_F8:
3407 case PPC::SELECT_VRRC:
3408 case PPC::SELECT_VSFRC:
3409 case PPC::SELECT_VSRC: {
3410 SDValue Op = MachineNode->getOperand(0);
3411 if (Op.isMachineOpcode()) {
3412 if (Op.getMachineOpcode() == PPC::CRSET)
3414 else if (Op.getMachineOpcode() == PPC::CRUNSET)
3416 else if (Op.getMachineOpcode() == PPC::CRNOR &&
3417 Op.getOperand(0) == Op.getOperand(1))
3424 bool SelectSwap = false;
3428 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3430 ResNode = MachineNode->getOperand(0).getNode();
3433 ResNode = MachineNode->getOperand(1).getNode();
3436 ResNode = MachineNode->getOperand(0).getNode();
3437 else if (Op1Unset || Op2Unset)
3438 // x & 0 = 0 & y = 0
3439 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3442 // ~x & y = andc(y, x)
3443 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3444 MVT::i1, MachineNode->getOperand(1),
3445 MachineNode->getOperand(0).
3448 // x & ~y = andc(x, y)
3449 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3450 MVT::i1, MachineNode->getOperand(0),
3451 MachineNode->getOperand(1).
3453 else if (AllUsersSelectZero(MachineNode))
3454 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
3455 MVT::i1, MachineNode->getOperand(0),
3456 MachineNode->getOperand(1)),
3460 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3461 // nand(x, x) -> nor(x, x)
3462 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3463 MVT::i1, MachineNode->getOperand(0),
3464 MachineNode->getOperand(0));
3466 // nand(1, y) -> nor(y, y)
3467 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3468 MVT::i1, MachineNode->getOperand(1),
3469 MachineNode->getOperand(1));
3471 // nand(x, 1) -> nor(x, x)
3472 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3473 MVT::i1, MachineNode->getOperand(0),
3474 MachineNode->getOperand(0));
3475 else if (Op1Unset || Op2Unset)
3476 // nand(x, 0) = nand(0, y) = 1
3477 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3480 // nand(~x, y) = ~(~x & y) = x | ~y = orc(x, y)
3481 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3482 MVT::i1, MachineNode->getOperand(0).
3484 MachineNode->getOperand(1));
3486 // nand(x, ~y) = ~x | y = orc(y, x)
3487 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3488 MVT::i1, MachineNode->getOperand(1).
3490 MachineNode->getOperand(0));
3491 else if (AllUsersSelectZero(MachineNode))
3492 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
3493 MVT::i1, MachineNode->getOperand(0),
3494 MachineNode->getOperand(1)),
3498 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3500 ResNode = MachineNode->getOperand(0).getNode();
3501 else if (Op1Set || Op2Set)
3502 // x | 1 = 1 | y = 1
3503 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3507 ResNode = MachineNode->getOperand(1).getNode();
3510 ResNode = MachineNode->getOperand(0).getNode();
3512 // ~x | y = orc(y, x)
3513 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3514 MVT::i1, MachineNode->getOperand(1),
3515 MachineNode->getOperand(0).
3518 // x | ~y = orc(x, y)
3519 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3520 MVT::i1, MachineNode->getOperand(0),
3521 MachineNode->getOperand(1).
3523 else if (AllUsersSelectZero(MachineNode))
3524 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3525 MVT::i1, MachineNode->getOperand(0),
3526 MachineNode->getOperand(1)),
3530 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3532 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3535 // xor(1, y) -> nor(y, y)
3536 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3537 MVT::i1, MachineNode->getOperand(1),
3538 MachineNode->getOperand(1));
3540 // xor(x, 1) -> nor(x, x)
3541 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3542 MVT::i1, MachineNode->getOperand(0),
3543 MachineNode->getOperand(0));
3546 ResNode = MachineNode->getOperand(1).getNode();
3549 ResNode = MachineNode->getOperand(0).getNode();
3551 // xor(~x, y) = eqv(x, y)
3552 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
3553 MVT::i1, MachineNode->getOperand(0).
3555 MachineNode->getOperand(1));
3557 // xor(x, ~y) = eqv(x, y)
3558 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
3559 MVT::i1, MachineNode->getOperand(0),
3560 MachineNode->getOperand(1).
3562 else if (AllUsersSelectZero(MachineNode))
3563 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
3564 MVT::i1, MachineNode->getOperand(0),
3565 MachineNode->getOperand(1)),
3569 if (Op1Set || Op2Set)
3571 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3574 // nor(0, y) = ~y -> nor(y, y)
3575 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3576 MVT::i1, MachineNode->getOperand(1),
3577 MachineNode->getOperand(1));
3580 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3581 MVT::i1, MachineNode->getOperand(0),
3582 MachineNode->getOperand(0));
3584 // nor(~x, y) = andc(x, y)
3585 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3586 MVT::i1, MachineNode->getOperand(0).
3588 MachineNode->getOperand(1));
3590 // nor(x, ~y) = andc(y, x)
3591 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3592 MVT::i1, MachineNode->getOperand(1).
3594 MachineNode->getOperand(0));
3595 else if (AllUsersSelectZero(MachineNode))
3596 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
3597 MVT::i1, MachineNode->getOperand(0),
3598 MachineNode->getOperand(1)),
3602 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3604 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3608 ResNode = MachineNode->getOperand(1).getNode();
3611 ResNode = MachineNode->getOperand(0).getNode();
3613 // eqv(0, y) = ~y -> nor(y, y)
3614 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3615 MVT::i1, MachineNode->getOperand(1),
3616 MachineNode->getOperand(1));
3619 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3620 MVT::i1, MachineNode->getOperand(0),
3621 MachineNode->getOperand(0));
3623 // eqv(~x, y) = xor(x, y)
3624 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
3625 MVT::i1, MachineNode->getOperand(0).
3627 MachineNode->getOperand(1));
3629 // eqv(x, ~y) = xor(x, y)
3630 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
3631 MVT::i1, MachineNode->getOperand(0),
3632 MachineNode->getOperand(1).
3634 else if (AllUsersSelectZero(MachineNode))
3635 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
3636 MVT::i1, MachineNode->getOperand(0),
3637 MachineNode->getOperand(1)),
3641 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3643 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3647 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3648 MVT::i1, MachineNode->getOperand(1),
3649 MachineNode->getOperand(1));
3650 else if (Op1Unset || Op2Set)
3651 // andc(0, y) = andc(x, 1) = 0
3652 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3656 ResNode = MachineNode->getOperand(0).getNode();
3658 // andc(~x, y) = ~(x | y) = nor(x, y)
3659 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3660 MVT::i1, MachineNode->getOperand(0).
3662 MachineNode->getOperand(1));
3664 // andc(x, ~y) = x & y
3665 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
3666 MVT::i1, MachineNode->getOperand(0),
3667 MachineNode->getOperand(1).
3669 else if (AllUsersSelectZero(MachineNode))
3670 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3671 MVT::i1, MachineNode->getOperand(1),
3672 MachineNode->getOperand(0)),
3676 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3678 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3680 else if (Op1Set || Op2Unset)
3681 // orc(1, y) = orc(x, 0) = 1
3682 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3686 ResNode = MachineNode->getOperand(0).getNode();
3689 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3690 MVT::i1, MachineNode->getOperand(1),
3691 MachineNode->getOperand(1));
3693 // orc(~x, y) = ~(x & y) = nand(x, y)
3694 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
3695 MVT::i1, MachineNode->getOperand(0).
3697 MachineNode->getOperand(1));
3699 // orc(x, ~y) = x | y
3700 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
3701 MVT::i1, MachineNode->getOperand(0),
3702 MachineNode->getOperand(1).
3704 else if (AllUsersSelectZero(MachineNode))
3705 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3706 MVT::i1, MachineNode->getOperand(1),
3707 MachineNode->getOperand(0)),
3710 case PPC::SELECT_I4:
3711 case PPC::SELECT_I8:
3712 case PPC::SELECT_F4:
3713 case PPC::SELECT_F8:
3714 case PPC::SELECT_VRRC:
3715 case PPC::SELECT_VSFRC:
3716 case PPC::SELECT_VSRC:
3718 ResNode = MachineNode->getOperand(1).getNode();
3720 ResNode = MachineNode->getOperand(2).getNode();
3722 ResNode = CurDAG->getMachineNode(MachineNode->getMachineOpcode(),
3724 MachineNode->getValueType(0),
3725 MachineNode->getOperand(0).
3727 MachineNode->getOperand(2),
3728 MachineNode->getOperand(1));
3733 ResNode = CurDAG->getMachineNode(Opcode == PPC::BC ? PPC::BCn :
3737 MachineNode->getOperand(0).
3739 MachineNode->getOperand(1),
3740 MachineNode->getOperand(2));
3741 // FIXME: Handle Op1Set, Op1Unset here too.
3745 // If we're inverting this node because it is used only by selects that
3746 // we'd like to swap, then swap the selects before the node replacement.
3748 SwapAllSelectUsers(MachineNode);
3750 if (ResNode != MachineNode) {
3751 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
3752 DEBUG(MachineNode->dump(CurDAG));
3753 DEBUG(dbgs() << "\nNew: ");
3754 DEBUG(ResNode->dump(CurDAG));
3755 DEBUG(dbgs() << "\n");
3757 ReplaceUses(MachineNode, ResNode);
3762 CurDAG->RemoveDeadNodes();
3763 } while (IsModified);
3766 // Gather the set of 32-bit operations that are known to have their
3767 // higher-order 32 bits zero, where ToPromote contains all such operations.
3768 static bool PeepholePPC64ZExtGather(SDValue Op32,
3769 SmallPtrSetImpl<SDNode *> &ToPromote) {
3770 if (!Op32.isMachineOpcode())
3773 // First, check for the "frontier" instructions (those that will clear the
3774 // higher-order 32 bits.
3776 // For RLWINM and RLWNM, we need to make sure that the mask does not wrap
3777 // around. If it does not, then these instructions will clear the
3778 // higher-order bits.
3779 if ((Op32.getMachineOpcode() == PPC::RLWINM ||
3780 Op32.getMachineOpcode() == PPC::RLWNM) &&
3781 Op32.getConstantOperandVal(2) <= Op32.getConstantOperandVal(3)) {
3782 ToPromote.insert(Op32.getNode());
3786 // SLW and SRW always clear the higher-order bits.
3787 if (Op32.getMachineOpcode() == PPC::SLW ||
3788 Op32.getMachineOpcode() == PPC::SRW) {
3789 ToPromote.insert(Op32.getNode());
3793 // For LI and LIS, we need the immediate to be positive (so that it is not
3795 if (Op32.getMachineOpcode() == PPC::LI ||
3796 Op32.getMachineOpcode() == PPC::LIS) {
3797 if (!isUInt<15>(Op32.getConstantOperandVal(0)))
3800 ToPromote.insert(Op32.getNode());
3804 // LHBRX and LWBRX always clear the higher-order bits.
3805 if (Op32.getMachineOpcode() == PPC::LHBRX ||
3806 Op32.getMachineOpcode() == PPC::LWBRX) {
3807 ToPromote.insert(Op32.getNode());
3811 // CNTLZW always produces a 64-bit value in [0,32], and so is zero extended.
3812 if (Op32.getMachineOpcode() == PPC::CNTLZW) {
3813 ToPromote.insert(Op32.getNode());
3817 // Next, check for those instructions we can look through.
3819 // Assuming the mask does not wrap around, then the higher-order bits are
3820 // taken directly from the first operand.
3821 if (Op32.getMachineOpcode() == PPC::RLWIMI &&
3822 Op32.getConstantOperandVal(3) <= Op32.getConstantOperandVal(4)) {
3823 SmallPtrSet<SDNode *, 16> ToPromote1;
3824 if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
3827 ToPromote.insert(Op32.getNode());
3828 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3832 // For OR, the higher-order bits are zero if that is true for both operands.
3833 // For SELECT_I4, the same is true (but the relevant operand numbers are
3835 if (Op32.getMachineOpcode() == PPC::OR ||
3836 Op32.getMachineOpcode() == PPC::SELECT_I4) {
3837 unsigned B = Op32.getMachineOpcode() == PPC::SELECT_I4 ? 1 : 0;
3838 SmallPtrSet<SDNode *, 16> ToPromote1;
3839 if (!PeepholePPC64ZExtGather(Op32.getOperand(B+0), ToPromote1))
3841 if (!PeepholePPC64ZExtGather(Op32.getOperand(B+1), ToPromote1))
3844 ToPromote.insert(Op32.getNode());
3845 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3849 // For ORI and ORIS, we need the higher-order bits of the first operand to be
3850 // zero, and also for the constant to be positive (so that it is not sign
3852 if (Op32.getMachineOpcode() == PPC::ORI ||
3853 Op32.getMachineOpcode() == PPC::ORIS) {
3854 SmallPtrSet<SDNode *, 16> ToPromote1;
3855 if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
3857 if (!isUInt<15>(Op32.getConstantOperandVal(1)))
3860 ToPromote.insert(Op32.getNode());
3861 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3865 // The higher-order bits of AND are zero if that is true for at least one of
3867 if (Op32.getMachineOpcode() == PPC::AND) {
3868 SmallPtrSet<SDNode *, 16> ToPromote1, ToPromote2;
3870 PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
3872 PeepholePPC64ZExtGather(Op32.getOperand(1), ToPromote2);
3873 if (!Op0OK && !Op1OK)
3876 ToPromote.insert(Op32.getNode());
3879 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3882 ToPromote.insert(ToPromote2.begin(), ToPromote2.end());
3887 // For ANDI and ANDIS, the higher-order bits are zero if either that is true
3888 // of the first operand, or if the second operand is positive (so that it is
3889 // not sign extended).
3890 if (Op32.getMachineOpcode() == PPC::ANDIo ||
3891 Op32.getMachineOpcode() == PPC::ANDISo) {
3892 SmallPtrSet<SDNode *, 16> ToPromote1;
3894 PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
3895 bool Op1OK = isUInt<15>(Op32.getConstantOperandVal(1));
3896 if (!Op0OK && !Op1OK)
3899 ToPromote.insert(Op32.getNode());
3902 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3910 void PPCDAGToDAGISel::PeepholePPC64ZExt() {
3911 if (!PPCSubTarget->isPPC64())
3914 // When we zero-extend from i32 to i64, we use a pattern like this:
3915 // def : Pat<(i64 (zext i32:$in)),
3916 // (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
3918 // There are several 32-bit shift/rotate instructions, however, that will
3919 // clear the higher-order bits of their output, rendering the RLDICL
3920 // unnecessary. When that happens, we remove it here, and redefine the
3921 // relevant 32-bit operation to be a 64-bit operation.
3923 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
3926 bool MadeChange = false;
3927 while (Position != CurDAG->allnodes_begin()) {
3928 SDNode *N = --Position;
3929 // Skip dead nodes and any non-machine opcodes.
3930 if (N->use_empty() || !N->isMachineOpcode())
3933 if (N->getMachineOpcode() != PPC::RLDICL)
3936 if (N->getConstantOperandVal(1) != 0 ||
3937 N->getConstantOperandVal(2) != 32)
3940 SDValue ISR = N->getOperand(0);
3941 if (!ISR.isMachineOpcode() ||
3942 ISR.getMachineOpcode() != TargetOpcode::INSERT_SUBREG)
3945 if (!ISR.hasOneUse())
3948 if (ISR.getConstantOperandVal(2) != PPC::sub_32)
3951 SDValue IDef = ISR.getOperand(0);
3952 if (!IDef.isMachineOpcode() ||
3953 IDef.getMachineOpcode() != TargetOpcode::IMPLICIT_DEF)
3956 // We now know that we're looking at a canonical i32 -> i64 zext. See if we
3957 // can get rid of it.
3959 SDValue Op32 = ISR->getOperand(1);
3960 if (!Op32.isMachineOpcode())
3963 // There are some 32-bit instructions that always clear the high-order 32
3964 // bits, there are also some instructions (like AND) that we can look
3966 SmallPtrSet<SDNode *, 16> ToPromote;
3967 if (!PeepholePPC64ZExtGather(Op32, ToPromote))
3970 // If the ToPromote set contains nodes that have uses outside of the set
3971 // (except for the original INSERT_SUBREG), then abort the transformation.
3972 bool OutsideUse = false;
3973 for (SDNode *PN : ToPromote) {
3974 for (SDNode *UN : PN->uses()) {
3975 if (!ToPromote.count(UN) && UN != ISR.getNode()) {
3989 // We now know that this zero extension can be removed by promoting to
3990 // nodes in ToPromote to 64-bit operations, where for operations in the
3991 // frontier of the set, we need to insert INSERT_SUBREGs for their
3993 for (SDNode *PN : ToPromote) {
3995 switch (PN->getMachineOpcode()) {
3997 llvm_unreachable("Don't know the 64-bit variant of this instruction");
3998 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break;
3999 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break;
4000 case PPC::SLW: NewOpcode = PPC::SLW8; break;
4001 case PPC::SRW: NewOpcode = PPC::SRW8; break;
4002 case PPC::LI: NewOpcode = PPC::LI8; break;
4003 case PPC::LIS: NewOpcode = PPC::LIS8; break;
4004 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break;
4005 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break;
4006 case PPC::CNTLZW: NewOpcode = PPC::CNTLZW8; break;
4007 case PPC::RLWIMI: NewOpcode = PPC::RLWIMI8; break;
4008 case PPC::OR: NewOpcode = PPC::OR8; break;
4009 case PPC::SELECT_I4: NewOpcode = PPC::SELECT_I8; break;
4010 case PPC::ORI: NewOpcode = PPC::ORI8; break;
4011 case PPC::ORIS: NewOpcode = PPC::ORIS8; break;
4012 case PPC::AND: NewOpcode = PPC::AND8; break;
4013 case PPC::ANDIo: NewOpcode = PPC::ANDIo8; break;
4014 case PPC::ANDISo: NewOpcode = PPC::ANDISo8; break;
4017 // Note: During the replacement process, the nodes will be in an
4018 // inconsistent state (some instructions will have operands with values
4019 // of the wrong type). Once done, however, everything should be right
4022 SmallVector<SDValue, 4> Ops;
4023 for (const SDValue &V : PN->ops()) {
4024 if (!ToPromote.count(V.getNode()) && V.getValueType() == MVT::i32 &&
4025 !isa<ConstantSDNode>(V)) {
4026 SDValue ReplOpOps[] = { ISR.getOperand(0), V, ISR.getOperand(2) };
4028 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, SDLoc(V),
4029 ISR.getNode()->getVTList(), ReplOpOps);
4030 Ops.push_back(SDValue(ReplOp, 0));
4036 // Because all to-be-promoted nodes only have users that are other
4037 // promoted nodes (or the original INSERT_SUBREG), we can safely replace
4038 // the i32 result value type with i64.
4040 SmallVector<EVT, 2> NewVTs;
4041 SDVTList VTs = PN->getVTList();
4042 for (unsigned i = 0, ie = VTs.NumVTs; i != ie; ++i)
4043 if (VTs.VTs[i] == MVT::i32)
4044 NewVTs.push_back(MVT::i64);
4046 NewVTs.push_back(VTs.VTs[i]);
4048 DEBUG(dbgs() << "PPC64 ZExt Peephole morphing:\nOld: ");
4049 DEBUG(PN->dump(CurDAG));
4051 CurDAG->SelectNodeTo(PN, NewOpcode, CurDAG->getVTList(NewVTs), Ops);
4053 DEBUG(dbgs() << "\nNew: ");
4054 DEBUG(PN->dump(CurDAG));
4055 DEBUG(dbgs() << "\n");
4058 // Now we replace the original zero extend and its associated INSERT_SUBREG
4059 // with the value feeding the INSERT_SUBREG (which has now been promoted to
4062 DEBUG(dbgs() << "PPC64 ZExt Peephole replacing:\nOld: ");
4063 DEBUG(N->dump(CurDAG));
4064 DEBUG(dbgs() << "\nNew: ");
4065 DEBUG(Op32.getNode()->dump(CurDAG));
4066 DEBUG(dbgs() << "\n");
4068 ReplaceUses(N, Op32.getNode());
4072 CurDAG->RemoveDeadNodes();
4075 void PPCDAGToDAGISel::PeepholePPC64() {
4076 // These optimizations are currently supported only for 64-bit SVR4.
4077 if (PPCSubTarget->isDarwin() || !PPCSubTarget->isPPC64())
4080 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
4083 while (Position != CurDAG->allnodes_begin()) {
4084 SDNode *N = --Position;
4085 // Skip dead nodes and any non-machine opcodes.
4086 if (N->use_empty() || !N->isMachineOpcode())
4090 unsigned StorageOpcode = N->getMachineOpcode();
4092 switch (StorageOpcode) {
4123 // If this is a load or store with a zero offset, we may be able to
4124 // fold an add-immediate into the memory operation.
4125 if (!isa<ConstantSDNode>(N->getOperand(FirstOp)) ||
4126 N->getConstantOperandVal(FirstOp) != 0)
4129 SDValue Base = N->getOperand(FirstOp + 1);
4130 if (!Base.isMachineOpcode())
4134 bool ReplaceFlags = true;
4136 // When the feeding operation is an add-immediate of some sort,
4137 // determine whether we need to add relocation information to the
4138 // target flags on the immediate operand when we fold it into the
4139 // load instruction.
4141 // For something like ADDItocL, the relocation information is
4142 // inferred from the opcode; when we process it in the AsmPrinter,
4143 // we add the necessary relocation there. A load, though, can receive
4144 // relocation from various flavors of ADDIxxx, so we need to carry
4145 // the relocation information in the target flags.
4146 switch (Base.getMachineOpcode()) {
4151 // In some cases (such as TLS) the relocation information
4152 // is already in place on the operand, so copying the operand
4154 ReplaceFlags = false;
4155 // For these cases, the immediate may not be divisible by 4, in
4156 // which case the fold is illegal for DS-form instructions. (The
4157 // other cases provide aligned addresses and are always safe.)
4158 if ((StorageOpcode == PPC::LWA ||
4159 StorageOpcode == PPC::LD ||
4160 StorageOpcode == PPC::STD) &&
4161 (!isa<ConstantSDNode>(Base.getOperand(1)) ||
4162 Base.getConstantOperandVal(1) % 4 != 0))
4165 case PPC::ADDIdtprelL:
4166 Flags = PPCII::MO_DTPREL_LO;
4168 case PPC::ADDItlsldL:
4169 Flags = PPCII::MO_TLSLD_LO;
4172 Flags = PPCII::MO_TOC_LO;
4176 // We found an opportunity. Reverse the operands from the add
4177 // immediate and substitute them into the load or store. If
4178 // needed, update the target flags for the immediate operand to
4179 // reflect the necessary relocation information.
4180 DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: ");
4181 DEBUG(Base->dump(CurDAG));
4182 DEBUG(dbgs() << "\nN: ");
4183 DEBUG(N->dump(CurDAG));
4184 DEBUG(dbgs() << "\n");
4186 SDValue ImmOpnd = Base.getOperand(1);
4188 // If the relocation information isn't already present on the
4189 // immediate operand, add it now.
4191 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
4193 const GlobalValue *GV = GA->getGlobal();
4194 // We can't perform this optimization for data whose alignment
4195 // is insufficient for the instruction encoding.
4196 if (GV->getAlignment() < 4 &&
4197 (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD ||
4198 StorageOpcode == PPC::LWA)) {
4199 DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
4202 ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);
4203 } else if (ConstantPoolSDNode *CP =
4204 dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
4205 const Constant *C = CP->getConstVal();
4206 ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64,
4212 if (FirstOp == 1) // Store
4213 (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd,
4214 Base.getOperand(0), N->getOperand(3));
4216 (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0),
4219 // The add-immediate may now be dead, in which case remove it.
4220 if (Base.getNode()->use_empty())
4221 CurDAG->RemoveDeadNode(Base.getNode());
4226 /// createPPCISelDag - This pass converts a legalized DAG into a
4227 /// PowerPC-specific DAG, ready for instruction scheduling.
4229 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
4230 return new PPCDAGToDAGISel(TM);
4233 static void initializePassOnce(PassRegistry &Registry) {
4234 const char *Name = "PowerPC DAG->DAG Pattern Instruction Selection";
4235 PassInfo *PI = new PassInfo(Name, "ppc-codegen", &SelectionDAGISel::ID,
4236 nullptr, false, false);
4237 Registry.registerPass(*PI, true);
4240 void llvm::initializePPCDAGToDAGISelPass(PassRegistry &Registry) {
4241 CALL_ONCE_INITIALIZATION(initializePassOnce);