1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "ppc-codegen"
17 #include "PPCPredicates.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCISelLowering.h"
20 #include "PPCHazardRecognizers.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Constants.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/Compiler.h"
38 //===--------------------------------------------------------------------===//
39 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
40 /// instructions for SelectionDAG operations.
42 class VISIBILITY_HIDDEN PPCDAGToDAGISel : public SelectionDAGISel {
44 PPCTargetLowering PPCLowering;
45 const PPCSubtarget &PPCSubTarget;
46 unsigned GlobalBaseReg;
48 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
49 : SelectionDAGISel(PPCLowering), TM(tm),
50 PPCLowering(*TM.getTargetLowering()),
51 PPCSubTarget(*TM.getSubtargetImpl()) {}
53 virtual bool runOnFunction(Function &Fn) {
54 // Make sure we re-emit a set of the global base reg if necessary
56 SelectionDAGISel::runOnFunction(Fn);
62 /// getI32Imm - Return a target constant with the specified value, of type
64 inline SDValue getI32Imm(unsigned Imm) {
65 return CurDAG->getTargetConstant(Imm, MVT::i32);
68 /// getI64Imm - Return a target constant with the specified value, of type
70 inline SDValue getI64Imm(uint64_t Imm) {
71 return CurDAG->getTargetConstant(Imm, MVT::i64);
74 /// getSmallIPtrImm - Return a target constant of pointer type.
75 inline SDValue getSmallIPtrImm(unsigned Imm) {
76 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
79 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
80 /// with any number of 0s on either side. The 1s are allowed to wrap from
81 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
82 /// 0x0F0F0000 is not, since all 1s are not contiguous.
83 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
86 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
87 /// rotate and mask opcode and mask operation.
88 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
89 unsigned &SH, unsigned &MB, unsigned &ME);
91 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
92 /// base register. Return the virtual register that holds this value.
93 SDNode *getGlobalBaseReg();
95 // Select - Convert the specified operand from a target-independent to a
96 // target-specific node if it hasn't already been changed.
97 SDNode *Select(SDValue Op);
99 SDNode *SelectBitfieldInsert(SDNode *N);
101 /// SelectCC - Select a comparison of the specified values with the
102 /// specified condition code, returning the CR# of the expression.
103 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC);
105 /// SelectAddrImm - Returns true if the address N can be represented by
106 /// a base register plus a signed 16-bit displacement [r+imm].
107 bool SelectAddrImm(SDValue Op, SDValue N, SDValue &Disp,
109 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
112 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
113 /// immediate field. Because preinc imms have already been validated, just
115 bool SelectAddrImmOffs(SDValue Op, SDValue N, SDValue &Out) const {
120 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
121 /// represented as an indexed [r+r] operation. Returns false if it can
122 /// be represented by [r+imm], which are preferred.
123 bool SelectAddrIdx(SDValue Op, SDValue N, SDValue &Base,
125 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
128 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
129 /// represented as an indexed [r+r] operation.
130 bool SelectAddrIdxOnly(SDValue Op, SDValue N, SDValue &Base,
132 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
135 /// SelectAddrImmShift - Returns true if the address N can be represented by
136 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
137 /// for use by STD and friends.
138 bool SelectAddrImmShift(SDValue Op, SDValue N, SDValue &Disp,
140 return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
143 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
144 /// inline asm expressions.
145 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
147 std::vector<SDValue> &OutOps) {
149 switch (ConstraintCode) {
150 default: return true;
152 if (!SelectAddrIdx(Op, Op, Op0, Op1))
153 SelectAddrImm(Op, Op, Op0, Op1);
155 case 'o': // offsetable
156 if (!SelectAddrImm(Op, Op, Op0, Op1)) {
158 AddToISelQueue(Op0); // r+0.
159 Op1 = getSmallIPtrImm(0);
162 case 'v': // not offsetable
163 SelectAddrIdxOnly(Op, Op, Op0, Op1);
167 OutOps.push_back(Op0);
168 OutOps.push_back(Op1);
172 SDValue BuildSDIVSequence(SDNode *N);
173 SDValue BuildUDIVSequence(SDNode *N);
175 /// InstructionSelect - This callback is invoked by
176 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
177 virtual void InstructionSelect();
179 void InsertVRSaveCode(Function &Fn);
181 virtual const char *getPassName() const {
182 return "PowerPC DAG->DAG Pattern Instruction Selection";
185 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
186 /// this target when scheduling the DAG.
187 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
188 // Should use subtarget info to pick the right hazard recognizer. For
189 // now, always return a PPC970 recognizer.
190 const TargetInstrInfo *II = TM.getInstrInfo();
191 assert(II && "No InstrInfo?");
192 return new PPCHazardRecognizer970(*II);
195 // Include the pieces autogenerated from the target description.
196 #include "PPCGenDAGISel.inc"
199 SDNode *SelectSETCC(SDValue Op);
203 /// InstructionSelect - This callback is invoked by
204 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
205 void PPCDAGToDAGISel::InstructionSelect() {
208 // Select target instructions for the DAG.
210 CurDAG->RemoveDeadNodes();
213 /// InsertVRSaveCode - Once the entire function has been instruction selected,
214 /// all virtual registers are created and all machine instructions are built,
215 /// check to see if we need to save/restore VRSAVE. If so, do it.
216 void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
217 // Check to see if this function uses vector registers, which means we have to
218 // save and restore the VRSAVE register and update it with the regs we use.
220 // In this case, there will be virtual registers of vector type type created
221 // by the scheduler. Detect them now.
222 MachineFunction &Fn = MachineFunction::get(&F);
223 bool HasVectorVReg = false;
224 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
225 e = RegInfo->getLastVirtReg()+1; i != e; ++i)
226 if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) {
227 HasVectorVReg = true;
230 if (!HasVectorVReg) return; // nothing to do.
232 // If we have a vector register, we want to emit code into the entry and exit
233 // blocks to save and restore the VRSAVE register. We do this here (instead
234 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
236 // 1. This (trivially) reduces the load on the register allocator, by not
237 // having to represent the live range of the VRSAVE register.
238 // 2. This (more significantly) allows us to create a temporary virtual
239 // register to hold the saved VRSAVE value, allowing this temporary to be
240 // register allocated, instead of forcing it to be spilled to the stack.
242 // Create two vregs - one to hold the VRSAVE register that is live-in to the
243 // function and one for the value after having bits or'd into it.
244 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
245 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
247 const TargetInstrInfo &TII = *TM.getInstrInfo();
248 MachineBasicBlock &EntryBB = *Fn.begin();
249 // Emit the following code into the entry block:
250 // InVRSAVE = MFVRSAVE
251 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
252 // MTVRSAVE UpdatedVRSAVE
253 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
254 BuildMI(EntryBB, IP, TII.get(PPC::MFVRSAVE), InVRSAVE);
255 BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE),
256 UpdatedVRSAVE).addReg(InVRSAVE);
257 BuildMI(EntryBB, IP, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
259 // Find all return blocks, outputting a restore in each epilog.
260 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
261 if (!BB->empty() && BB->back().getDesc().isReturn()) {
262 IP = BB->end(); --IP;
264 // Skip over all terminator instructions, which are part of the return
266 MachineBasicBlock::iterator I2 = IP;
267 while (I2 != BB->begin() && (--I2)->getDesc().isTerminator())
270 // Emit: MTVRSAVE InVRSave
271 BuildMI(*BB, IP, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
277 /// getGlobalBaseReg - Output the instructions required to put the
278 /// base address to use for accessing globals into a register.
280 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
281 if (!GlobalBaseReg) {
282 const TargetInstrInfo &TII = *TM.getInstrInfo();
283 // Insert the set of GlobalBaseReg into the first MBB of the function
284 MachineBasicBlock &FirstMBB = BB->getParent()->front();
285 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
287 if (PPCLowering.getPointerTy() == MVT::i32) {
288 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
289 BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR), PPC::LR);
290 BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR), GlobalBaseReg);
292 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass);
293 BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR8), PPC::LR8);
294 BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg);
297 return CurDAG->getRegister(GlobalBaseReg,
298 PPCLowering.getPointerTy()).getNode();
301 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
302 /// or 64-bit immediate, and if the value can be accurately represented as a
303 /// sign extension from a 16-bit value. If so, this returns true and the
305 static bool isIntS16Immediate(SDNode *N, short &Imm) {
306 if (N->getOpcode() != ISD::Constant)
309 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
310 if (N->getValueType(0) == MVT::i32)
311 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
313 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
316 static bool isIntS16Immediate(SDValue Op, short &Imm) {
317 return isIntS16Immediate(Op.getNode(), Imm);
321 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
322 /// operand. If so Imm will receive the 32-bit value.
323 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
324 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
325 Imm = cast<ConstantSDNode>(N)->getZExtValue();
331 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
332 /// operand. If so Imm will receive the 64-bit value.
333 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
334 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
335 Imm = cast<ConstantSDNode>(N)->getZExtValue();
341 // isInt32Immediate - This method tests to see if a constant operand.
342 // If so Imm will receive the 32 bit value.
343 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
344 return isInt32Immediate(N.getNode(), Imm);
348 // isOpcWithIntImmediate - This method tests to see if the node is a specific
349 // opcode and that it has a immediate integer right operand.
350 // If so Imm will receive the 32 bit value.
351 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
352 return N->getOpcode() == Opc
353 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
356 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
357 if (isShiftedMask_32(Val)) {
358 // look for the first non-zero bit
359 MB = CountLeadingZeros_32(Val);
360 // look for the first zero bit after the run of ones
361 ME = CountLeadingZeros_32((Val - 1) ^ Val);
364 Val = ~Val; // invert mask
365 if (isShiftedMask_32(Val)) {
366 // effectively look for the first zero bit
367 ME = CountLeadingZeros_32(Val) - 1;
368 // effectively look for the first one bit after the run of zeros
369 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
377 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
378 bool IsShiftMask, unsigned &SH,
379 unsigned &MB, unsigned &ME) {
380 // Don't even go down this path for i64, since different logic will be
381 // necessary for rldicl/rldicr/rldimi.
382 if (N->getValueType(0) != MVT::i32)
386 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
387 unsigned Opcode = N->getOpcode();
388 if (N->getNumOperands() != 2 ||
389 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
392 if (Opcode == ISD::SHL) {
393 // apply shift left to mask if it comes first
394 if (IsShiftMask) Mask = Mask << Shift;
395 // determine which bits are made indeterminant by shift
396 Indeterminant = ~(0xFFFFFFFFu << Shift);
397 } else if (Opcode == ISD::SRL) {
398 // apply shift right to mask if it comes first
399 if (IsShiftMask) Mask = Mask >> Shift;
400 // determine which bits are made indeterminant by shift
401 Indeterminant = ~(0xFFFFFFFFu >> Shift);
402 // adjust for the left rotate
404 } else if (Opcode == ISD::ROTL) {
410 // if the mask doesn't intersect any Indeterminant bits
411 if (Mask && !(Mask & Indeterminant)) {
413 // make sure the mask is still a mask (wrap arounds may not be)
414 return isRunOfOnes(Mask, MB, ME);
419 /// SelectBitfieldInsert - turn an or of two masked values into
420 /// the rotate left word immediate then mask insert (rlwimi) instruction.
421 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
422 SDValue Op0 = N->getOperand(0);
423 SDValue Op1 = N->getOperand(1);
425 APInt LKZ, LKO, RKZ, RKO;
426 CurDAG->ComputeMaskedBits(Op0, APInt::getAllOnesValue(32), LKZ, LKO);
427 CurDAG->ComputeMaskedBits(Op1, APInt::getAllOnesValue(32), RKZ, RKO);
429 unsigned TargetMask = LKZ.getZExtValue();
430 unsigned InsertMask = RKZ.getZExtValue();
432 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
433 unsigned Op0Opc = Op0.getOpcode();
434 unsigned Op1Opc = Op1.getOpcode();
435 unsigned Value, SH = 0;
436 TargetMask = ~TargetMask;
437 InsertMask = ~InsertMask;
439 // If the LHS has a foldable shift and the RHS does not, then swap it to the
440 // RHS so that we can fold the shift into the insert.
441 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
442 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
443 Op0.getOperand(0).getOpcode() == ISD::SRL) {
444 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
445 Op1.getOperand(0).getOpcode() != ISD::SRL) {
447 std::swap(Op0Opc, Op1Opc);
448 std::swap(TargetMask, InsertMask);
451 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
452 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
453 Op1.getOperand(0).getOpcode() != ISD::SRL) {
455 std::swap(Op0Opc, Op1Opc);
456 std::swap(TargetMask, InsertMask);
461 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
462 SDValue Tmp1, Tmp2, Tmp3;
463 bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF;
465 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
466 isInt32Immediate(Op1.getOperand(1), Value)) {
467 Op1 = Op1.getOperand(0);
468 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
470 if (Op1Opc == ISD::AND) {
471 unsigned SHOpc = Op1.getOperand(0).getOpcode();
472 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
473 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
474 Op1 = Op1.getOperand(0).getOperand(0);
475 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
477 Op1 = Op1.getOperand(0);
481 Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0;
482 AddToISelQueue(Tmp3);
485 SDValue Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
487 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
493 /// SelectCC - Select a comparison of the specified values with the specified
494 /// condition code, returning the CR# of the expression.
495 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
497 // Always select the LHS.
501 if (LHS.getValueType() == MVT::i32) {
503 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
504 if (isInt32Immediate(RHS, Imm)) {
505 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
507 return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
508 getI32Imm(Imm & 0xFFFF)), 0);
509 // If this is a 16-bit signed immediate, fold it.
510 if (isInt16((int)Imm))
511 return SDValue(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
512 getI32Imm(Imm & 0xFFFF)), 0);
514 // For non-equality comparisons, the default code would materialize the
515 // constant, then compare against it, like this:
519 // Since we are just comparing for equality, we can emit this instead:
520 // xoris r0,r3,0x1234
521 // cmplwi cr0,r0,0x5678
523 SDValue Xor(CurDAG->getTargetNode(PPC::XORIS, MVT::i32, LHS,
524 getI32Imm(Imm >> 16)), 0);
525 return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, Xor,
526 getI32Imm(Imm & 0xFFFF)), 0);
529 } else if (ISD::isUnsignedIntSetCC(CC)) {
530 if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
531 return SDValue(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
532 getI32Imm(Imm & 0xFFFF)), 0);
536 if (isIntS16Immediate(RHS, SImm))
537 return SDValue(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
538 getI32Imm((int)SImm & 0xFFFF)),
542 } else if (LHS.getValueType() == MVT::i64) {
544 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
545 if (isInt64Immediate(RHS.getNode(), Imm)) {
546 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
548 return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
549 getI32Imm(Imm & 0xFFFF)), 0);
550 // If this is a 16-bit signed immediate, fold it.
552 return SDValue(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
553 getI32Imm(Imm & 0xFFFF)), 0);
555 // For non-equality comparisons, the default code would materialize the
556 // constant, then compare against it, like this:
560 // Since we are just comparing for equality, we can emit this instead:
561 // xoris r0,r3,0x1234
562 // cmpldi cr0,r0,0x5678
565 SDValue Xor(CurDAG->getTargetNode(PPC::XORIS8, MVT::i64, LHS,
566 getI64Imm(Imm >> 16)), 0);
567 return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, Xor,
568 getI64Imm(Imm & 0xFFFF)), 0);
572 } else if (ISD::isUnsignedIntSetCC(CC)) {
573 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt16(Imm))
574 return SDValue(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
575 getI64Imm(Imm & 0xFFFF)), 0);
579 if (isIntS16Immediate(RHS, SImm))
580 return SDValue(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
581 getI64Imm(SImm & 0xFFFF)),
585 } else if (LHS.getValueType() == MVT::f32) {
588 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
592 return SDValue(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0);
595 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
597 default: assert(0 && "Unknown condition!"); abort();
598 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
600 case ISD::SETEQ: return PPC::PRED_EQ;
601 case ISD::SETONE: // FIXME: This is incorrect see PR642.
603 case ISD::SETNE: return PPC::PRED_NE;
604 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
606 case ISD::SETLT: return PPC::PRED_LT;
607 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
609 case ISD::SETLE: return PPC::PRED_LE;
610 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
612 case ISD::SETGT: return PPC::PRED_GT;
613 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
615 case ISD::SETGE: return PPC::PRED_GE;
617 case ISD::SETO: return PPC::PRED_NU;
618 case ISD::SETUO: return PPC::PRED_UN;
622 /// getCRIdxForSetCC - Return the index of the condition register field
623 /// associated with the SetCC condition, and whether or not the field is
624 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
626 /// If this returns with Other != -1, then the returned comparison is an or of
627 /// two simpler comparisons. In this case, Invert is guaranteed to be false.
628 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) {
632 default: assert(0 && "Unknown condition!"); abort();
634 case ISD::SETLT: return 0; // Bit #0 = SETOLT
636 case ISD::SETGT: return 1; // Bit #1 = SETOGT
638 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
639 case ISD::SETUO: return 3; // Bit #3 = SETUO
641 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
643 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
645 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
646 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
647 case ISD::SETULT: Other = 0; return 3; // SETOLT | SETUO
648 case ISD::SETUGT: Other = 1; return 3; // SETOGT | SETUO
649 case ISD::SETUEQ: Other = 2; return 3; // SETOEQ | SETUO
650 case ISD::SETOGE: Other = 1; return 2; // SETOGT | SETOEQ
651 case ISD::SETOLE: Other = 0; return 2; // SETOLT | SETOEQ
652 case ISD::SETONE: Other = 0; return 1; // SETOLT | SETOGT
657 SDNode *PPCDAGToDAGISel::SelectSETCC(SDValue Op) {
658 SDNode *N = Op.getNode();
660 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
661 if (isInt32Immediate(N->getOperand(1), Imm)) {
662 // We can codegen setcc op, imm very efficiently compared to a brcond.
663 // Check for those cases here.
666 SDValue Op = N->getOperand(0);
671 Op = SDValue(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
672 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
673 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
677 SDValue(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
678 Op, getI32Imm(~0U)), 0);
679 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
683 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
684 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
688 SDValue(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
689 T = SDValue(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
690 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
691 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
694 } else if (Imm == ~0U) { // setcc op, -1
695 SDValue Op = N->getOperand(0);
700 Op = SDValue(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
701 Op, getI32Imm(1)), 0);
702 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
703 SDValue(CurDAG->getTargetNode(PPC::LI, MVT::i32,
707 Op = SDValue(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0);
708 SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
710 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
714 SDValue AD = SDValue(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
716 SDValue AN = SDValue(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
718 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
719 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
722 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
723 Op = SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
724 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
733 unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx);
734 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
737 // Force the ccreg into CR7.
738 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
740 SDValue InFlag(0, 0); // Null incoming flag value.
741 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg,
744 if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
745 IntCR = SDValue(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg,
748 IntCR = SDValue(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
750 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
751 getI32Imm(31), getI32Imm(31) };
752 if (OtherCondIdx == -1 && !Inv)
753 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
755 // Get the specified bit.
757 SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
759 assert(OtherCondIdx == -1 && "Can't have split plus negation");
760 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
763 // Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT.
764 // We already got the bit for the first part of the comparison (e.g. SETULE).
766 // Get the other bit of the comparison.
767 Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
769 SDValue(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
771 return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
775 // Select - Convert the specified operand from a target-independent to a
776 // target-specific node if it hasn't already been changed.
777 SDNode *PPCDAGToDAGISel::Select(SDValue Op) {
778 SDNode *N = Op.getNode();
779 if (N->isMachineOpcode())
780 return NULL; // Already selected.
782 switch (N->getOpcode()) {
785 case ISD::Constant: {
786 if (N->getValueType(0) == MVT::i64) {
788 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
789 // Assume no remaining bits.
790 unsigned Remainder = 0;
791 // Assume no shift required.
794 // If it can't be represented as a 32 bit value.
796 Shift = CountTrailingZeros_64(Imm);
797 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
799 // If the shifted value fits 32 bits.
800 if (isInt32(ImmSh)) {
801 // Go with the shifted value.
804 // Still stuck with a 64 bit value.
811 // Intermediate operand.
814 // Handle first 32 bits.
815 unsigned Lo = Imm & 0xFFFF;
816 unsigned Hi = (Imm >> 16) & 0xFFFF;
821 Result = CurDAG->getTargetNode(PPC::LI8, MVT::i64, getI32Imm(Lo));
823 // Handle the Hi bits.
824 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
825 Result = CurDAG->getTargetNode(OpC, MVT::i64, getI32Imm(Hi));
827 Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64,
828 SDValue(Result, 0), getI32Imm(Lo));
831 Result = CurDAG->getTargetNode(PPC::LIS8, MVT::i64, getI32Imm(Hi));
834 // If no shift, we're done.
835 if (!Shift) return Result;
837 // Shift for next step if the upper 32-bits were not zero.
839 Result = CurDAG->getTargetNode(PPC::RLDICR, MVT::i64,
841 getI32Imm(Shift), getI32Imm(63 - Shift));
844 // Add in the last bits as required.
845 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
846 Result = CurDAG->getTargetNode(PPC::ORIS8, MVT::i64,
847 SDValue(Result, 0), getI32Imm(Hi));
849 if ((Lo = Remainder & 0xFFFF)) {
850 Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64,
851 SDValue(Result, 0), getI32Imm(Lo));
860 return SelectSETCC(Op);
861 case PPCISD::GlobalBaseReg:
862 return getGlobalBaseReg();
864 case ISD::FrameIndex: {
865 int FI = cast<FrameIndexSDNode>(N)->getIndex();
866 SDValue TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
867 unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
869 return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
871 return CurDAG->getTargetNode(Opc, Op.getValueType(), TFI,
876 SDValue InFlag = N->getOperand(1);
877 AddToISelQueue(InFlag);
878 // Use MFOCRF if supported.
879 if (PPCSubTarget.isGigaProcessor())
880 return CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32,
881 N->getOperand(0), InFlag);
883 return CurDAG->getTargetNode(PPC::MFCR, MVT::i32, InFlag);
887 // FIXME: since this depends on the setting of the carry flag from the srawi
888 // we should really be making notes about that for the scheduler.
889 // FIXME: It sure would be nice if we could cheaply recognize the
890 // srl/add/sra pattern the dag combiner will generate for this as
891 // sra/addze rather than having to handle sdiv ourselves. oh well.
893 if (isInt32Immediate(N->getOperand(1), Imm)) {
894 SDValue N0 = N->getOperand(0);
896 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
898 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
899 N0, getI32Imm(Log2_32(Imm)));
900 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
901 SDValue(Op, 0), SDValue(Op, 1));
902 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
904 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
905 N0, getI32Imm(Log2_32(-Imm)));
907 SDValue(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32,
908 SDValue(Op, 0), SDValue(Op, 1)),
910 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
914 // Other cases are autogenerated.
919 // Handle preincrement loads.
920 LoadSDNode *LD = cast<LoadSDNode>(Op);
921 MVT LoadedVT = LD->getMemoryVT();
923 // Normal loads are handled by code generated from the .td file.
924 if (LD->getAddressingMode() != ISD::PRE_INC)
927 SDValue Offset = LD->getOffset();
928 if (isa<ConstantSDNode>(Offset) ||
929 Offset.getOpcode() == ISD::TargetGlobalAddress) {
932 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
933 if (LD->getValueType(0) != MVT::i64) {
934 // Handle PPC32 integer and normal FP loads.
935 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
936 switch (LoadedVT.getSimpleVT()) {
937 default: assert(0 && "Invalid PPC load type!");
938 case MVT::f64: Opcode = PPC::LFDU; break;
939 case MVT::f32: Opcode = PPC::LFSU; break;
940 case MVT::i32: Opcode = PPC::LWZU; break;
941 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
943 case MVT::i8: Opcode = PPC::LBZU; break;
946 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
947 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
948 switch (LoadedVT.getSimpleVT()) {
949 default: assert(0 && "Invalid PPC load type!");
950 case MVT::i64: Opcode = PPC::LDU; break;
951 case MVT::i32: Opcode = PPC::LWZU8; break;
952 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
954 case MVT::i8: Opcode = PPC::LBZU8; break;
958 SDValue Chain = LD->getChain();
959 SDValue Base = LD->getBasePtr();
960 AddToISelQueue(Chain);
961 AddToISelQueue(Base);
962 AddToISelQueue(Offset);
963 SDValue Ops[] = { Offset, Base, Chain };
965 return CurDAG->getTargetNode(Opcode, LD->getValueType(0),
966 PPCLowering.getPointerTy(),
969 assert(0 && "R+R preindex loads not supported yet!");
974 unsigned Imm, Imm2, SH, MB, ME;
976 // If this is an and of a value rotated between 0 and 31 bits and then and'd
977 // with a mask, emit rlwinm
978 if (isInt32Immediate(N->getOperand(1), Imm) &&
979 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
980 SDValue Val = N->getOperand(0).getOperand(0);
982 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
983 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
985 // If this is just a masked value where the input is not handled above, and
986 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
987 if (isInt32Immediate(N->getOperand(1), Imm) &&
988 isRunOfOnes(Imm, MB, ME) &&
989 N->getOperand(0).getOpcode() != ISD::ROTL) {
990 SDValue Val = N->getOperand(0);
992 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
993 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
995 // AND X, 0 -> 0, not "rlwinm 32".
996 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
997 AddToISelQueue(N->getOperand(1));
998 ReplaceUses(SDValue(N, 0), N->getOperand(1));
1001 // ISD::OR doesn't get all the bitfield insertion fun.
1002 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
1003 if (isInt32Immediate(N->getOperand(1), Imm) &&
1004 N->getOperand(0).getOpcode() == ISD::OR &&
1005 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
1008 if (isRunOfOnes(Imm, MB, ME)) {
1009 AddToISelQueue(N->getOperand(0).getOperand(0));
1010 AddToISelQueue(N->getOperand(0).getOperand(1));
1011 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1012 N->getOperand(0).getOperand(1),
1013 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
1014 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
1018 // Other cases are autogenerated.
1022 if (N->getValueType(0) == MVT::i32)
1023 if (SDNode *I = SelectBitfieldInsert(N))
1026 // Other cases are autogenerated.
1029 unsigned Imm, SH, MB, ME;
1030 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1031 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1032 AddToISelQueue(N->getOperand(0).getOperand(0));
1033 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1034 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1035 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1038 // Other cases are autogenerated.
1042 unsigned Imm, SH, MB, ME;
1043 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
1044 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1045 AddToISelQueue(N->getOperand(0).getOperand(0));
1046 SDValue Ops[] = { N->getOperand(0).getOperand(0),
1047 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1048 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1051 // Other cases are autogenerated.
1054 case ISD::SELECT_CC: {
1055 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1057 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1058 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1059 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1060 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1061 if (N1C->isNullValue() && N3C->isNullValue() &&
1062 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
1063 // FIXME: Implement this optzn for PPC64.
1064 N->getValueType(0) == MVT::i32) {
1065 AddToISelQueue(N->getOperand(0));
1067 CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1068 N->getOperand(0), getI32Imm(~0U));
1069 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1070 SDValue(Tmp, 0), N->getOperand(0),
1074 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
1075 unsigned BROpc = getPredicateForSetCC(CC);
1077 unsigned SelectCCOp;
1078 if (N->getValueType(0) == MVT::i32)
1079 SelectCCOp = PPC::SELECT_CC_I4;
1080 else if (N->getValueType(0) == MVT::i64)
1081 SelectCCOp = PPC::SELECT_CC_I8;
1082 else if (N->getValueType(0) == MVT::f32)
1083 SelectCCOp = PPC::SELECT_CC_F4;
1084 else if (N->getValueType(0) == MVT::f64)
1085 SelectCCOp = PPC::SELECT_CC_F8;
1087 SelectCCOp = PPC::SELECT_CC_VRRC;
1089 AddToISelQueue(N->getOperand(2));
1090 AddToISelQueue(N->getOperand(3));
1091 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
1093 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
1095 case PPCISD::COND_BRANCH: {
1096 AddToISelQueue(N->getOperand(0)); // Op #0 is the Chain.
1097 // Op #1 is the PPC::PRED_* number.
1099 // Op #3 is the Dest MBB
1100 AddToISelQueue(N->getOperand(4)); // Op #4 is the Flag.
1101 // Prevent PPC::PRED_* from being selected into LI.
1103 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
1104 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
1105 N->getOperand(0), N->getOperand(4) };
1106 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
1109 AddToISelQueue(N->getOperand(0));
1110 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1111 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
1112 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
1113 N->getOperand(4), N->getOperand(0) };
1114 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
1117 // FIXME: Should custom lower this.
1118 SDValue Chain = N->getOperand(0);
1119 SDValue Target = N->getOperand(1);
1120 AddToISelQueue(Chain);
1121 AddToISelQueue(Target);
1122 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1123 Chain = SDValue(CurDAG->getTargetNode(Opc, MVT::Other, Target,
1125 return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
1129 return SelectCode(Op);
1134 /// createPPCISelDag - This pass converts a legalized DAG into a
1135 /// PowerPC-specific DAG, ready for instruction scheduling.
1137 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1138 return new PPCDAGToDAGISel(TM);