1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "PPCTargetMachine.h"
17 #include "PPCISelLowering.h"
18 #include "PPCHazardRecognizers.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
31 #include "llvm/Support/Compiler.h"
38 Statistic<> FrameOff("ppc-codegen", "Number of frame idx offsets collapsed");
40 //===--------------------------------------------------------------------===//
41 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
42 /// instructions for SelectionDAG operations.
44 class VISIBILITY_HIDDEN PPCDAGToDAGISel : public SelectionDAGISel {
46 PPCTargetLowering PPCLowering;
47 unsigned GlobalBaseReg;
49 PPCDAGToDAGISel(PPCTargetMachine &tm)
50 : SelectionDAGISel(PPCLowering), TM(tm),
51 PPCLowering(*TM.getTargetLowering()) {}
53 virtual bool runOnFunction(Function &Fn) {
54 // Make sure we re-emit a set of the global base reg if necessary
56 SelectionDAGISel::runOnFunction(Fn);
62 /// getI32Imm - Return a target constant with the specified value, of type
64 inline SDOperand getI32Imm(unsigned Imm) {
65 return CurDAG->getTargetConstant(Imm, MVT::i32);
68 /// getI64Imm - Return a target constant with the specified value, of type
70 inline SDOperand getI64Imm(uint64_t Imm) {
71 return CurDAG->getTargetConstant(Imm, MVT::i64);
74 /// getSmallIPtrImm - Return a target constant of pointer type.
75 inline SDOperand getSmallIPtrImm(unsigned Imm) {
76 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
79 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
80 /// with any number of 0s on either side. The 1s are allowed to wrap from
81 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
82 /// 0x0F0F0000 is not, since all 1s are not contiguous.
83 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
86 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
87 /// rotate and mask opcode and mask operation.
88 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
89 unsigned &SH, unsigned &MB, unsigned &ME);
91 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
92 /// base register. Return the virtual register that holds this value.
93 SDNode *getGlobalBaseReg();
95 // Select - Convert the specified operand from a target-independent to a
96 // target-specific node if it hasn't already been changed.
97 SDNode *Select(SDOperand Op);
99 SDNode *SelectBitfieldInsert(SDNode *N);
101 /// SelectCC - Select a comparison of the specified values with the
102 /// specified condition code, returning the CR# of the expression.
103 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
105 /// SelectAddrImm - Returns true if the address N can be represented by
106 /// a base register plus a signed 16-bit displacement [r+imm].
107 bool SelectAddrImm(SDOperand Op, SDOperand N, SDOperand &Disp,
109 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
112 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
113 /// represented as an indexed [r+r] operation. Returns false if it can
114 /// be represented by [r+imm], which are preferred.
115 bool SelectAddrIdx(SDOperand Op, SDOperand N, SDOperand &Base,
117 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
120 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
121 /// represented as an indexed [r+r] operation.
122 bool SelectAddrIdxOnly(SDOperand Op, SDOperand N, SDOperand &Base,
124 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
127 /// SelectAddrImmShift - Returns true if the address N can be represented by
128 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
129 /// for use by STD and friends.
130 bool SelectAddrImmShift(SDOperand Op, SDOperand N, SDOperand &Disp,
132 return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
135 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
136 /// inline asm expressions.
137 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
139 std::vector<SDOperand> &OutOps,
142 switch (ConstraintCode) {
143 default: return true;
145 if (!SelectAddrIdx(Op, Op, Op0, Op1))
146 SelectAddrImm(Op, Op, Op0, Op1);
148 case 'o': // offsetable
149 if (!SelectAddrImm(Op, Op, Op0, Op1)) {
151 AddToISelQueue(Op0); // r+0.
152 Op1 = getSmallIPtrImm(0);
155 case 'v': // not offsetable
156 SelectAddrIdxOnly(Op, Op, Op0, Op1);
160 OutOps.push_back(Op0);
161 OutOps.push_back(Op1);
165 SDOperand BuildSDIVSequence(SDNode *N);
166 SDOperand BuildUDIVSequence(SDNode *N);
168 /// InstructionSelectBasicBlock - This callback is invoked by
169 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
170 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
172 void InsertVRSaveCode(Function &Fn);
174 virtual const char *getPassName() const {
175 return "PowerPC DAG->DAG Pattern Instruction Selection";
178 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
179 /// this target when scheduling the DAG.
180 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
181 // Should use subtarget info to pick the right hazard recognizer. For
182 // now, always return a PPC970 recognizer.
183 const TargetInstrInfo *II = PPCLowering.getTargetMachine().getInstrInfo();
184 assert(II && "No InstrInfo?");
185 return new PPCHazardRecognizer970(*II);
188 // Include the pieces autogenerated from the target description.
189 #include "PPCGenDAGISel.inc"
192 SDNode *SelectSETCC(SDOperand Op);
196 /// InstructionSelectBasicBlock - This callback is invoked by
197 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
198 void PPCDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
201 // Select target instructions for the DAG.
202 DAG.setRoot(SelectRoot(DAG.getRoot()));
203 DAG.RemoveDeadNodes();
205 // Emit machine code to BB.
206 ScheduleAndEmitDAG(DAG);
209 /// InsertVRSaveCode - Once the entire function has been instruction selected,
210 /// all virtual registers are created and all machine instructions are built,
211 /// check to see if we need to save/restore VRSAVE. If so, do it.
212 void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
213 // Check to see if this function uses vector registers, which means we have to
214 // save and restore the VRSAVE register and update it with the regs we use.
216 // In this case, there will be virtual registers of vector type type created
217 // by the scheduler. Detect them now.
218 MachineFunction &Fn = MachineFunction::get(&F);
219 SSARegMap *RegMap = Fn.getSSARegMap();
220 bool HasVectorVReg = false;
221 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
222 e = RegMap->getLastVirtReg()+1; i != e; ++i)
223 if (RegMap->getRegClass(i) == &PPC::VRRCRegClass) {
224 HasVectorVReg = true;
227 if (!HasVectorVReg) return; // nothing to do.
229 // If we have a vector register, we want to emit code into the entry and exit
230 // blocks to save and restore the VRSAVE register. We do this here (instead
231 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
233 // 1. This (trivially) reduces the load on the register allocator, by not
234 // having to represent the live range of the VRSAVE register.
235 // 2. This (more significantly) allows us to create a temporary virtual
236 // register to hold the saved VRSAVE value, allowing this temporary to be
237 // register allocated, instead of forcing it to be spilled to the stack.
239 // Create two vregs - one to hold the VRSAVE register that is live-in to the
240 // function and one for the value after having bits or'd into it.
241 unsigned InVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
242 unsigned UpdatedVRSAVE = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
244 MachineBasicBlock &EntryBB = *Fn.begin();
245 // Emit the following code into the entry block:
246 // InVRSAVE = MFVRSAVE
247 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
248 // MTVRSAVE UpdatedVRSAVE
249 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
250 BuildMI(EntryBB, IP, PPC::MFVRSAVE, 0, InVRSAVE);
251 BuildMI(EntryBB, IP, PPC::UPDATE_VRSAVE, 1, UpdatedVRSAVE).addReg(InVRSAVE);
252 BuildMI(EntryBB, IP, PPC::MTVRSAVE, 1).addReg(UpdatedVRSAVE);
254 // Find all return blocks, outputting a restore in each epilog.
255 const TargetInstrInfo &TII = *TM.getInstrInfo();
256 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
257 if (!BB->empty() && TII.isReturn(BB->back().getOpcode())) {
258 IP = BB->end(); --IP;
260 // Skip over all terminator instructions, which are part of the return
262 MachineBasicBlock::iterator I2 = IP;
263 while (I2 != BB->begin() && TII.isTerminatorInstr((--I2)->getOpcode()))
266 // Emit: MTVRSAVE InVRSave
267 BuildMI(*BB, IP, PPC::MTVRSAVE, 1).addReg(InVRSAVE);
273 /// getGlobalBaseReg - Output the instructions required to put the
274 /// base address to use for accessing globals into a register.
276 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
277 if (!GlobalBaseReg) {
278 // Insert the set of GlobalBaseReg into the first MBB of the function
279 MachineBasicBlock &FirstMBB = BB->getParent()->front();
280 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
281 SSARegMap *RegMap = BB->getParent()->getSSARegMap();
283 if (PPCLowering.getPointerTy() == MVT::i32) {
284 GlobalBaseReg = RegMap->createVirtualRegister(PPC::GPRCRegisterClass);
285 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
286 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg);
288 GlobalBaseReg = RegMap->createVirtualRegister(PPC::G8RCRegisterClass);
289 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR8, 0, PPC::LR8);
290 BuildMI(FirstMBB, MBBI, PPC::MFLR8, 1, GlobalBaseReg);
293 return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy()).Val;
296 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
297 /// or 64-bit immediate, and if the value can be accurately represented as a
298 /// sign extension from a 16-bit value. If so, this returns true and the
300 static bool isIntS16Immediate(SDNode *N, short &Imm) {
301 if (N->getOpcode() != ISD::Constant)
304 Imm = (short)cast<ConstantSDNode>(N)->getValue();
305 if (N->getValueType(0) == MVT::i32)
306 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
308 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
311 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
312 return isIntS16Immediate(Op.Val, Imm);
316 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
317 /// operand. If so Imm will receive the 32-bit value.
318 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
319 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
320 Imm = cast<ConstantSDNode>(N)->getValue();
326 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
327 /// operand. If so Imm will receive the 64-bit value.
328 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
329 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
330 Imm = cast<ConstantSDNode>(N)->getValue();
336 // isInt32Immediate - This method tests to see if a constant operand.
337 // If so Imm will receive the 32 bit value.
338 static bool isInt32Immediate(SDOperand N, unsigned &Imm) {
339 return isInt32Immediate(N.Val, Imm);
343 // isOpcWithIntImmediate - This method tests to see if the node is a specific
344 // opcode and that it has a immediate integer right operand.
345 // If so Imm will receive the 32 bit value.
346 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
347 return N->getOpcode() == Opc && isInt32Immediate(N->getOperand(1).Val, Imm);
350 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
351 if (isShiftedMask_32(Val)) {
352 // look for the first non-zero bit
353 MB = CountLeadingZeros_32(Val);
354 // look for the first zero bit after the run of ones
355 ME = CountLeadingZeros_32((Val - 1) ^ Val);
358 Val = ~Val; // invert mask
359 if (isShiftedMask_32(Val)) {
360 // effectively look for the first zero bit
361 ME = CountLeadingZeros_32(Val) - 1;
362 // effectively look for the first one bit after the run of zeros
363 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
371 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
372 bool IsShiftMask, unsigned &SH,
373 unsigned &MB, unsigned &ME) {
374 // Don't even go down this path for i64, since different logic will be
375 // necessary for rldicl/rldicr/rldimi.
376 if (N->getValueType(0) != MVT::i32)
380 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
381 unsigned Opcode = N->getOpcode();
382 if (N->getNumOperands() != 2 ||
383 !isInt32Immediate(N->getOperand(1).Val, Shift) || (Shift > 31))
386 if (Opcode == ISD::SHL) {
387 // apply shift left to mask if it comes first
388 if (IsShiftMask) Mask = Mask << Shift;
389 // determine which bits are made indeterminant by shift
390 Indeterminant = ~(0xFFFFFFFFu << Shift);
391 } else if (Opcode == ISD::SRL) {
392 // apply shift right to mask if it comes first
393 if (IsShiftMask) Mask = Mask >> Shift;
394 // determine which bits are made indeterminant by shift
395 Indeterminant = ~(0xFFFFFFFFu >> Shift);
396 // adjust for the left rotate
398 } else if (Opcode == ISD::ROTL) {
404 // if the mask doesn't intersect any Indeterminant bits
405 if (Mask && !(Mask & Indeterminant)) {
407 // make sure the mask is still a mask (wrap arounds may not be)
408 return isRunOfOnes(Mask, MB, ME);
413 /// SelectBitfieldInsert - turn an or of two masked values into
414 /// the rotate left word immediate then mask insert (rlwimi) instruction.
415 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
416 SDOperand Op0 = N->getOperand(0);
417 SDOperand Op1 = N->getOperand(1);
419 uint64_t LKZ, LKO, RKZ, RKO;
420 TLI.ComputeMaskedBits(Op0, 0xFFFFFFFFULL, LKZ, LKO);
421 TLI.ComputeMaskedBits(Op1, 0xFFFFFFFFULL, RKZ, RKO);
423 unsigned TargetMask = LKZ;
424 unsigned InsertMask = RKZ;
426 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
427 unsigned Op0Opc = Op0.getOpcode();
428 unsigned Op1Opc = Op1.getOpcode();
429 unsigned Value, SH = 0;
430 TargetMask = ~TargetMask;
431 InsertMask = ~InsertMask;
433 // If the LHS has a foldable shift and the RHS does not, then swap it to the
434 // RHS so that we can fold the shift into the insert.
435 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
436 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
437 Op0.getOperand(0).getOpcode() == ISD::SRL) {
438 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
439 Op1.getOperand(0).getOpcode() != ISD::SRL) {
441 std::swap(Op0Opc, Op1Opc);
442 std::swap(TargetMask, InsertMask);
445 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
446 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
447 Op1.getOperand(0).getOpcode() != ISD::SRL) {
449 std::swap(Op0Opc, Op1Opc);
450 std::swap(TargetMask, InsertMask);
455 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
456 SDOperand Tmp1, Tmp2, Tmp3;
457 bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF;
459 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
460 isInt32Immediate(Op1.getOperand(1), Value)) {
461 Op1 = Op1.getOperand(0);
462 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
464 if (Op1Opc == ISD::AND) {
465 unsigned SHOpc = Op1.getOperand(0).getOpcode();
466 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
467 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
468 Op1 = Op1.getOperand(0).getOperand(0);
469 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
471 Op1 = Op1.getOperand(0);
475 Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0;
476 AddToISelQueue(Tmp3);
479 SDOperand Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
481 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
487 /// SelectCC - Select a comparison of the specified values with the specified
488 /// condition code, returning the CR# of the expression.
489 SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
491 // Always select the LHS.
495 if (LHS.getValueType() == MVT::i32) {
497 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
498 if (isInt32Immediate(RHS, Imm)) {
499 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
501 return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
502 getI32Imm(Imm & 0xFFFF)), 0);
503 // If this is a 16-bit signed immediate, fold it.
505 return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
506 getI32Imm(Imm & 0xFFFF)), 0);
508 // For non-equality comparisons, the default code would materialize the
509 // constant, then compare against it, like this:
513 // Since we are just comparing for equality, we can emit this instead:
514 // xoris r0,r3,0x1234
515 // cmplwi cr0,r0,0x5678
517 SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS, MVT::i32, LHS,
518 getI32Imm(Imm >> 16)), 0);
519 return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, Xor,
520 getI32Imm(Imm & 0xFFFF)), 0);
523 } else if (ISD::isUnsignedIntSetCC(CC)) {
524 if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
525 return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
526 getI32Imm(Imm & 0xFFFF)), 0);
530 if (isIntS16Immediate(RHS, SImm))
531 return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
532 getI32Imm((int)SImm & 0xFFFF)),
536 } else if (LHS.getValueType() == MVT::i64) {
538 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
539 if (isInt64Immediate(RHS.Val, Imm)) {
540 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
542 return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
543 getI32Imm(Imm & 0xFFFF)), 0);
544 // If this is a 16-bit signed immediate, fold it.
546 return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
547 getI32Imm(Imm & 0xFFFF)), 0);
549 // For non-equality comparisons, the default code would materialize the
550 // constant, then compare against it, like this:
554 // Since we are just comparing for equality, we can emit this instead:
555 // xoris r0,r3,0x1234
556 // cmpldi cr0,r0,0x5678
559 SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS8, MVT::i64, LHS,
560 getI64Imm(Imm >> 16)), 0);
561 return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, Xor,
562 getI64Imm(Imm & 0xFFFF)), 0);
566 } else if (ISD::isUnsignedIntSetCC(CC)) {
567 if (isInt64Immediate(RHS.Val, Imm) && isUInt16(Imm))
568 return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
569 getI64Imm(Imm & 0xFFFF)), 0);
573 if (isIntS16Immediate(RHS, SImm))
574 return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
575 getI64Imm(SImm & 0xFFFF)),
579 } else if (LHS.getValueType() == MVT::f32) {
582 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
586 return SDOperand(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0);
589 /// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
591 static unsigned getBCCForSetCC(ISD::CondCode CC) {
593 default: assert(0 && "Unknown condition!"); abort();
594 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
596 case ISD::SETEQ: return PPC::BEQ;
597 case ISD::SETONE: // FIXME: This is incorrect see PR642.
599 case ISD::SETNE: return PPC::BNE;
600 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
602 case ISD::SETLT: return PPC::BLT;
603 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
605 case ISD::SETLE: return PPC::BLE;
606 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
608 case ISD::SETGT: return PPC::BGT;
609 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
611 case ISD::SETGE: return PPC::BGE;
613 case ISD::SETO: return PPC::BNU;
614 case ISD::SETUO: return PPC::BUN;
619 /// getCRIdxForSetCC - Return the index of the condition register field
620 /// associated with the SetCC condition, and whether or not the field is
621 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
622 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
624 default: assert(0 && "Unknown condition!"); abort();
625 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
627 case ISD::SETLT: Inv = false; return 0;
628 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
630 case ISD::SETGE: Inv = true; return 0;
631 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
633 case ISD::SETGT: Inv = false; return 1;
634 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
636 case ISD::SETLE: Inv = true; return 1;
637 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
639 case ISD::SETEQ: Inv = false; return 2;
640 case ISD::SETONE: // FIXME: This is incorrect see PR642.
642 case ISD::SETNE: Inv = true; return 2;
643 case ISD::SETO: Inv = true; return 3;
644 case ISD::SETUO: Inv = false; return 3;
649 SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
652 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
653 if (isInt32Immediate(N->getOperand(1), Imm)) {
654 // We can codegen setcc op, imm very efficiently compared to a brcond.
655 // Check for those cases here.
658 SDOperand Op = N->getOperand(0);
663 Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
664 SDOperand Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
665 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
669 SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
670 Op, getI32Imm(~0U)), 0);
671 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
675 SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
676 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
680 SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
681 T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
682 SDOperand Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
683 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
686 } else if (Imm == ~0U) { // setcc op, -1
687 SDOperand Op = N->getOperand(0);
692 Op = SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
693 Op, getI32Imm(1)), 0);
694 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
695 SDOperand(CurDAG->getTargetNode(PPC::LI, MVT::i32,
699 Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0);
700 SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
702 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0),
703 Op, SDOperand(AD, 1));
706 SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
708 SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
710 SDOperand Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
711 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
714 SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
715 Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
716 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
724 unsigned Idx = getCRIdxForSetCC(CC, Inv);
725 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
728 // Force the ccreg into CR7.
729 SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
731 SDOperand InFlag(0, 0); // Null incoming flag value.
732 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg,
735 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
736 IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg,
739 IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
741 SDOperand Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
742 getI32Imm(31), getI32Imm(31) };
744 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
747 SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
748 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
753 // Select - Convert the specified operand from a target-independent to a
754 // target-specific node if it hasn't already been changed.
755 SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
757 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
758 N->getOpcode() < PPCISD::FIRST_NUMBER)
759 return NULL; // Already selected.
761 switch (N->getOpcode()) {
764 return SelectSETCC(Op);
765 case PPCISD::GlobalBaseReg:
766 return getGlobalBaseReg();
768 case ISD::FrameIndex: {
769 int FI = cast<FrameIndexSDNode>(N)->getIndex();
770 SDOperand TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
771 unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
773 return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
775 return CurDAG->getTargetNode(Opc, Op.getValueType(), TFI,
780 SDOperand InFlag = N->getOperand(1);
781 AddToISelQueue(InFlag);
782 // Use MFOCRF if supported.
783 if (TLI.getTargetMachine().getSubtarget<PPCSubtarget>().isGigaProcessor())
784 return CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32,
785 N->getOperand(0), InFlag);
787 return CurDAG->getTargetNode(PPC::MFCR, MVT::i32, InFlag);
791 // FIXME: since this depends on the setting of the carry flag from the srawi
792 // we should really be making notes about that for the scheduler.
793 // FIXME: It sure would be nice if we could cheaply recognize the
794 // srl/add/sra pattern the dag combiner will generate for this as
795 // sra/addze rather than having to handle sdiv ourselves. oh well.
797 if (isInt32Immediate(N->getOperand(1), Imm)) {
798 SDOperand N0 = N->getOperand(0);
800 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
802 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
803 N0, getI32Imm(Log2_32(Imm)));
804 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
805 SDOperand(Op, 0), SDOperand(Op, 1));
806 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
808 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
809 N0, getI32Imm(Log2_32(-Imm)));
811 SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32,
812 SDOperand(Op, 0), SDOperand(Op, 1)),
814 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
818 // Other cases are autogenerated.
823 // Handle preincrement loads.
824 LoadSDNode *LD = cast<LoadSDNode>(Op);
825 MVT::ValueType LoadedVT = LD->getLoadedVT();
827 // Normal loads are handled by code generated from the .td file.
828 if (LD->getAddressingMode() != ISD::PRE_INC)
831 SDOperand Offset = LD->getOffset();
832 if (isa<ConstantSDNode>(Offset) ||
833 Offset.getOpcode() == ISD::TargetGlobalAddress) {
836 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
837 if (LD->getValueType(0) != MVT::i64) {
838 // Handle PPC32 integer and normal FP loads.
839 assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
841 default: assert(0 && "Invalid PPC load type!");
842 case MVT::f64: Opcode = PPC::LFDU; break;
843 case MVT::f32: Opcode = PPC::LFSU; break;
844 case MVT::i32: Opcode = PPC::LWZU; break;
845 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
847 case MVT::i8: Opcode = PPC::LBZU; break;
850 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
851 assert(!isSExt || LoadedVT == MVT::i16 && "Invalid sext update load");
853 default: assert(0 && "Invalid PPC load type!");
854 case MVT::i64: Opcode = PPC::LDU; break;
855 case MVT::i32: Opcode = PPC::LWZU8; break;
856 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
858 case MVT::i8: Opcode = PPC::LBZU8; break;
862 SDOperand Chain = LD->getChain();
863 SDOperand Base = LD->getBasePtr();
864 AddToISelQueue(Chain);
865 AddToISelQueue(Base);
866 AddToISelQueue(Offset);
867 SDOperand Ops[] = { Offset, Base, Chain };
869 return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32,
872 assert(0 && "R+R preindex loads not supported yet!");
877 unsigned Imm, Imm2, SH, MB, ME;
879 // If this is an and of a value rotated between 0 and 31 bits and then and'd
880 // with a mask, emit rlwinm
881 if (isInt32Immediate(N->getOperand(1), Imm) &&
882 isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
883 SDOperand Val = N->getOperand(0).getOperand(0);
885 SDOperand Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
886 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
888 // If this is just a masked value where the input is not handled above, and
889 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
890 if (isInt32Immediate(N->getOperand(1), Imm) &&
891 isRunOfOnes(Imm, MB, ME) &&
892 N->getOperand(0).getOpcode() != ISD::ROTL) {
893 SDOperand Val = N->getOperand(0);
895 SDOperand Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
896 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
898 // AND X, 0 -> 0, not "rlwinm 32".
899 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
900 AddToISelQueue(N->getOperand(1));
901 ReplaceUses(SDOperand(N, 0), N->getOperand(1));
904 // ISD::OR doesn't get all the bitfield insertion fun.
905 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
906 if (isInt32Immediate(N->getOperand(1), Imm) &&
907 N->getOperand(0).getOpcode() == ISD::OR &&
908 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
911 if (isRunOfOnes(Imm, MB, ME)) {
912 AddToISelQueue(N->getOperand(0).getOperand(0));
913 AddToISelQueue(N->getOperand(0).getOperand(1));
914 SDOperand Ops[] = { N->getOperand(0).getOperand(0),
915 N->getOperand(0).getOperand(1),
916 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
917 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
921 // Other cases are autogenerated.
925 if (N->getValueType(0) == MVT::i32)
926 if (SDNode *I = SelectBitfieldInsert(N))
929 // Other cases are autogenerated.
932 unsigned Imm, SH, MB, ME;
933 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
934 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
935 AddToISelQueue(N->getOperand(0).getOperand(0));
936 SDOperand Ops[] = { N->getOperand(0).getOperand(0),
937 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
938 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
941 // Other cases are autogenerated.
945 unsigned Imm, SH, MB, ME;
946 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
947 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
948 AddToISelQueue(N->getOperand(0).getOperand(0));
949 SDOperand Ops[] = { N->getOperand(0).getOperand(0),
950 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
951 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
954 // Other cases are autogenerated.
957 case ISD::SELECT_CC: {
958 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
960 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
961 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
962 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
963 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
964 if (N1C->isNullValue() && N3C->isNullValue() &&
965 N2C->getValue() == 1ULL && CC == ISD::SETNE &&
966 // FIXME: Implement this optzn for PPC64.
967 N->getValueType(0) == MVT::i32) {
968 AddToISelQueue(N->getOperand(0));
970 CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
971 N->getOperand(0), getI32Imm(~0U));
972 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
973 SDOperand(Tmp, 0), N->getOperand(0),
977 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
978 unsigned BROpc = getBCCForSetCC(CC);
981 if (N->getValueType(0) == MVT::i32)
982 SelectCCOp = PPC::SELECT_CC_I4;
983 else if (N->getValueType(0) == MVT::i64)
984 SelectCCOp = PPC::SELECT_CC_I8;
985 else if (N->getValueType(0) == MVT::f32)
986 SelectCCOp = PPC::SELECT_CC_F4;
987 else if (N->getValueType(0) == MVT::f64)
988 SelectCCOp = PPC::SELECT_CC_F8;
990 SelectCCOp = PPC::SELECT_CC_VRRC;
992 AddToISelQueue(N->getOperand(2));
993 AddToISelQueue(N->getOperand(3));
994 SDOperand Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
996 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
999 AddToISelQueue(N->getOperand(0));
1000 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1001 SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
1002 SDOperand Ops[] = { CondCode, getI32Imm(getBCCForSetCC(CC)),
1003 N->getOperand(4), N->getOperand(0) };
1004 return CurDAG->SelectNodeTo(N, PPC::COND_BRANCH, MVT::Other, Ops, 4);
1007 // FIXME: Should custom lower this.
1008 SDOperand Chain = N->getOperand(0);
1009 SDOperand Target = N->getOperand(1);
1010 AddToISelQueue(Chain);
1011 AddToISelQueue(Target);
1012 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1013 Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Target,
1015 return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
1019 return SelectCode(Op);
1024 /// createPPCISelDag - This pass converts a legalized DAG into a
1025 /// PowerPC-specific DAG, ready for instruction scheduling.
1027 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1028 return new PPCDAGToDAGISel(TM);