1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
16 #include "MCTargetDesc/PPCPredicates.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/IR/Constants.h"
25 #include "llvm/IR/Function.h"
26 #include "llvm/IR/GlobalAlias.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/GlobalVariable.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Module.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetOptions.h"
39 #define DEBUG_TYPE "ppc-codegen"
41 // FIXME: Remove this once the bug has been fixed!
42 cl::opt<bool> ANDIGlueBug("expose-ppc-andi-glue-bug",
43 cl::desc("expose the ANDI glue bug on PPC"), cl::Hidden);
46 UseBitPermRewriter("ppc-use-bit-perm-rewriter", cl::init(true),
47 cl::desc("use aggressive ppc isel for bit permutations"),
49 static cl::opt<bool> BPermRewriterNoMasking(
50 "ppc-bit-perm-rewriter-stress-rotates",
51 cl::desc("stress rotate selection in aggressive ppc isel for "
56 void initializePPCDAGToDAGISelPass(PassRegistry&);
60 //===--------------------------------------------------------------------===//
61 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
62 /// instructions for SelectionDAG operations.
64 class PPCDAGToDAGISel : public SelectionDAGISel {
65 const PPCTargetMachine &TM;
66 const PPCSubtarget *PPCSubTarget;
67 const PPCTargetLowering *PPCLowering;
68 unsigned GlobalBaseReg;
70 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
71 : SelectionDAGISel(tm), TM(tm) {
72 initializePPCDAGToDAGISelPass(*PassRegistry::getPassRegistry());
75 bool runOnMachineFunction(MachineFunction &MF) override {
76 // Make sure we re-emit a set of the global base reg if necessary
78 PPCSubTarget = &MF.getSubtarget<PPCSubtarget>();
79 PPCLowering = PPCSubTarget->getTargetLowering();
80 SelectionDAGISel::runOnMachineFunction(MF);
82 if (!PPCSubTarget->isSVR4ABI())
88 void PreprocessISelDAG() override;
89 void PostprocessISelDAG() override;
91 /// getI32Imm - Return a target constant with the specified value, of type
93 inline SDValue getI32Imm(unsigned Imm) {
94 return CurDAG->getTargetConstant(Imm, MVT::i32);
97 /// getI64Imm - Return a target constant with the specified value, of type
99 inline SDValue getI64Imm(uint64_t Imm) {
100 return CurDAG->getTargetConstant(Imm, MVT::i64);
103 /// getSmallIPtrImm - Return a target constant of pointer type.
104 inline SDValue getSmallIPtrImm(unsigned Imm) {
105 return CurDAG->getTargetConstant(Imm, PPCLowering->getPointerTy());
108 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
109 /// with any number of 0s on either side. The 1s are allowed to wrap from
110 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
111 /// 0x0F0F0000 is not, since all 1s are not contiguous.
112 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
115 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
116 /// rotate and mask opcode and mask operation.
117 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool isShiftMask,
118 unsigned &SH, unsigned &MB, unsigned &ME);
120 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
121 /// base register. Return the virtual register that holds this value.
122 SDNode *getGlobalBaseReg();
124 SDNode *getFrameIndex(SDNode *SN, SDNode *N, unsigned Offset = 0);
126 // Select - Convert the specified operand from a target-independent to a
127 // target-specific node if it hasn't already been changed.
128 SDNode *Select(SDNode *N) override;
130 SDNode *SelectBitfieldInsert(SDNode *N);
131 SDNode *SelectBitPermutation(SDNode *N);
133 /// SelectCC - Select a comparison of the specified values with the
134 /// specified condition code, returning the CR# of the expression.
135 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, SDLoc dl);
137 /// SelectAddrImm - Returns true if the address N can be represented by
138 /// a base register plus a signed 16-bit displacement [r+imm].
139 bool SelectAddrImm(SDValue N, SDValue &Disp,
141 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, false);
144 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
145 /// immediate field. Note that the operand at this point is already the
146 /// result of a prior SelectAddressRegImm call.
147 bool SelectAddrImmOffs(SDValue N, SDValue &Out) const {
148 if (N.getOpcode() == ISD::TargetConstant ||
149 N.getOpcode() == ISD::TargetGlobalAddress) {
157 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
158 /// represented as an indexed [r+r] operation. Returns false if it can
159 /// be represented by [r+imm], which are preferred.
160 bool SelectAddrIdx(SDValue N, SDValue &Base, SDValue &Index) {
161 return PPCLowering->SelectAddressRegReg(N, Base, Index, *CurDAG);
164 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
165 /// represented as an indexed [r+r] operation.
166 bool SelectAddrIdxOnly(SDValue N, SDValue &Base, SDValue &Index) {
167 return PPCLowering->SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
170 /// SelectAddrImmX4 - Returns true if the address N can be represented by
171 /// a base register plus a signed 16-bit displacement that is a multiple of 4.
172 /// Suitable for use by STD and friends.
173 bool SelectAddrImmX4(SDValue N, SDValue &Disp, SDValue &Base) {
174 return PPCLowering->SelectAddressRegImm(N, Disp, Base, *CurDAG, true);
177 // Select an address into a single register.
178 bool SelectAddr(SDValue N, SDValue &Base) {
183 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
184 /// inline asm expressions. It is always correct to compute the value into
185 /// a register. The case of adding a (possibly relocatable) constant to a
186 /// register can be improved, but it is wrong to substitute Reg+Reg for
187 /// Reg in an asm, because the load or store opcode would have to change.
188 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
190 std::vector<SDValue> &OutOps) override {
191 // We need to make sure that this one operand does not end up in r0
192 // (because we might end up lowering this as 0(%op)).
193 const TargetRegisterInfo *TRI = PPCSubTarget->getRegisterInfo();
194 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1);
195 SDValue RC = CurDAG->getTargetConstant(TRC->getID(), MVT::i32);
197 SDValue(CurDAG->getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
198 SDLoc(Op), Op.getValueType(),
201 OutOps.push_back(NewOp);
205 void InsertVRSaveCode(MachineFunction &MF);
207 const char *getPassName() const override {
208 return "PowerPC DAG->DAG Pattern Instruction Selection";
211 // Include the pieces autogenerated from the target description.
212 #include "PPCGenDAGISel.inc"
215 SDNode *SelectSETCC(SDNode *N);
217 void PeepholePPC64();
218 void PeepholePPC64ZExt();
219 void PeepholeCROps();
221 SDValue combineToCMPB(SDNode *N);
222 void foldBoolExts(SDValue &Res, SDNode *&N);
224 bool AllUsersSelectZero(SDNode *N);
225 void SwapAllSelectUsers(SDNode *N);
229 /// InsertVRSaveCode - Once the entire function has been instruction selected,
230 /// all virtual registers are created and all machine instructions are built,
231 /// check to see if we need to save/restore VRSAVE. If so, do it.
232 void PPCDAGToDAGISel::InsertVRSaveCode(MachineFunction &Fn) {
233 // Check to see if this function uses vector registers, which means we have to
234 // save and restore the VRSAVE register and update it with the regs we use.
236 // In this case, there will be virtual registers of vector type created
237 // by the scheduler. Detect them now.
238 bool HasVectorVReg = false;
239 for (unsigned i = 0, e = RegInfo->getNumVirtRegs(); i != e; ++i) {
240 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
241 if (RegInfo->getRegClass(Reg) == &PPC::VRRCRegClass) {
242 HasVectorVReg = true;
246 if (!HasVectorVReg) return; // nothing to do.
248 // If we have a vector register, we want to emit code into the entry and exit
249 // blocks to save and restore the VRSAVE register. We do this here (instead
250 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
252 // 1. This (trivially) reduces the load on the register allocator, by not
253 // having to represent the live range of the VRSAVE register.
254 // 2. This (more significantly) allows us to create a temporary virtual
255 // register to hold the saved VRSAVE value, allowing this temporary to be
256 // register allocated, instead of forcing it to be spilled to the stack.
258 // Create two vregs - one to hold the VRSAVE register that is live-in to the
259 // function and one for the value after having bits or'd into it.
260 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
261 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
263 const TargetInstrInfo &TII = *PPCSubTarget->getInstrInfo();
264 MachineBasicBlock &EntryBB = *Fn.begin();
266 // Emit the following code into the entry block:
267 // InVRSAVE = MFVRSAVE
268 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
269 // MTVRSAVE UpdatedVRSAVE
270 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
271 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
272 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
273 UpdatedVRSAVE).addReg(InVRSAVE);
274 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
276 // Find all return blocks, outputting a restore in each epilog.
277 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
278 if (!BB->empty() && BB->back().isReturn()) {
279 IP = BB->end(); --IP;
281 // Skip over all terminator instructions, which are part of the return
283 MachineBasicBlock::iterator I2 = IP;
284 while (I2 != BB->begin() && (--I2)->isTerminator())
287 // Emit: MTVRSAVE InVRSave
288 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
294 /// getGlobalBaseReg - Output the instructions required to put the
295 /// base address to use for accessing globals into a register.
297 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
298 if (!GlobalBaseReg) {
299 const TargetInstrInfo &TII = *PPCSubTarget->getInstrInfo();
300 // Insert the set of GlobalBaseReg into the first MBB of the function
301 MachineBasicBlock &FirstMBB = MF->front();
302 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
303 const Module *M = MF->getFunction()->getParent();
306 if (PPCLowering->getPointerTy() == MVT::i32) {
307 if (PPCSubTarget->isTargetELF()) {
308 GlobalBaseReg = PPC::R30;
309 if (M->getPICLevel() == PICLevel::Small) {
310 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MoveGOTtoLR));
311 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
312 MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
314 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
315 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
316 unsigned TempReg = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
317 BuildMI(FirstMBB, MBBI, dl,
318 TII.get(PPC::UpdateGBR)).addReg(GlobalBaseReg)
319 .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg);
320 MF->getInfo<PPCFunctionInfo>()->setUsesPICBase(true);
324 RegInfo->createVirtualRegister(&PPC::GPRC_NOR0RegClass);
325 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR));
326 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
329 GlobalBaseReg = RegInfo->createVirtualRegister(&PPC::G8RC_NOX0RegClass);
330 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MovePCtoLR8));
331 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
334 return CurDAG->getRegister(GlobalBaseReg,
335 PPCLowering->getPointerTy()).getNode();
338 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
339 /// or 64-bit immediate, and if the value can be accurately represented as a
340 /// sign extension from a 16-bit value. If so, this returns true and the
342 static bool isIntS16Immediate(SDNode *N, short &Imm) {
343 if (N->getOpcode() != ISD::Constant)
346 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
347 if (N->getValueType(0) == MVT::i32)
348 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
350 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
353 static bool isIntS16Immediate(SDValue Op, short &Imm) {
354 return isIntS16Immediate(Op.getNode(), Imm);
358 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
359 /// operand. If so Imm will receive the 32-bit value.
360 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
361 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
362 Imm = cast<ConstantSDNode>(N)->getZExtValue();
368 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
369 /// operand. If so Imm will receive the 64-bit value.
370 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
371 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
372 Imm = cast<ConstantSDNode>(N)->getZExtValue();
378 // isInt32Immediate - This method tests to see if a constant operand.
379 // If so Imm will receive the 32 bit value.
380 static bool isInt32Immediate(SDValue N, unsigned &Imm) {
381 return isInt32Immediate(N.getNode(), Imm);
385 // isOpcWithIntImmediate - This method tests to see if the node is a specific
386 // opcode and that it has a immediate integer right operand.
387 // If so Imm will receive the 32 bit value.
388 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
389 return N->getOpcode() == Opc
390 && isInt32Immediate(N->getOperand(1).getNode(), Imm);
393 SDNode *PPCDAGToDAGISel::getFrameIndex(SDNode *SN, SDNode *N, unsigned Offset) {
395 int FI = cast<FrameIndexSDNode>(N)->getIndex();
396 SDValue TFI = CurDAG->getTargetFrameIndex(FI, N->getValueType(0));
397 unsigned Opc = N->getValueType(0) == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
399 return CurDAG->SelectNodeTo(SN, Opc, N->getValueType(0), TFI,
400 getSmallIPtrImm(Offset));
401 return CurDAG->getMachineNode(Opc, dl, N->getValueType(0), TFI,
402 getSmallIPtrImm(Offset));
405 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
409 if (isShiftedMask_32(Val)) {
410 // look for the first non-zero bit
411 MB = countLeadingZeros(Val);
412 // look for the first zero bit after the run of ones
413 ME = countLeadingZeros((Val - 1) ^ Val);
416 Val = ~Val; // invert mask
417 if (isShiftedMask_32(Val)) {
418 // effectively look for the first zero bit
419 ME = countLeadingZeros(Val) - 1;
420 // effectively look for the first one bit after the run of zeros
421 MB = countLeadingZeros((Val - 1) ^ Val) + 1;
429 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
430 bool isShiftMask, unsigned &SH,
431 unsigned &MB, unsigned &ME) {
432 // Don't even go down this path for i64, since different logic will be
433 // necessary for rldicl/rldicr/rldimi.
434 if (N->getValueType(0) != MVT::i32)
438 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
439 unsigned Opcode = N->getOpcode();
440 if (N->getNumOperands() != 2 ||
441 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31))
444 if (Opcode == ISD::SHL) {
445 // apply shift left to mask if it comes first
446 if (isShiftMask) Mask = Mask << Shift;
447 // determine which bits are made indeterminant by shift
448 Indeterminant = ~(0xFFFFFFFFu << Shift);
449 } else if (Opcode == ISD::SRL) {
450 // apply shift right to mask if it comes first
451 if (isShiftMask) Mask = Mask >> Shift;
452 // determine which bits are made indeterminant by shift
453 Indeterminant = ~(0xFFFFFFFFu >> Shift);
454 // adjust for the left rotate
456 } else if (Opcode == ISD::ROTL) {
462 // if the mask doesn't intersect any Indeterminant bits
463 if (Mask && !(Mask & Indeterminant)) {
465 // make sure the mask is still a mask (wrap arounds may not be)
466 return isRunOfOnes(Mask, MB, ME);
471 /// SelectBitfieldInsert - turn an or of two masked values into
472 /// the rotate left word immediate then mask insert (rlwimi) instruction.
473 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
474 SDValue Op0 = N->getOperand(0);
475 SDValue Op1 = N->getOperand(1);
478 APInt LKZ, LKO, RKZ, RKO;
479 CurDAG->computeKnownBits(Op0, LKZ, LKO);
480 CurDAG->computeKnownBits(Op1, RKZ, RKO);
482 unsigned TargetMask = LKZ.getZExtValue();
483 unsigned InsertMask = RKZ.getZExtValue();
485 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
486 unsigned Op0Opc = Op0.getOpcode();
487 unsigned Op1Opc = Op1.getOpcode();
488 unsigned Value, SH = 0;
489 TargetMask = ~TargetMask;
490 InsertMask = ~InsertMask;
492 // If the LHS has a foldable shift and the RHS does not, then swap it to the
493 // RHS so that we can fold the shift into the insert.
494 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
495 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
496 Op0.getOperand(0).getOpcode() == ISD::SRL) {
497 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
498 Op1.getOperand(0).getOpcode() != ISD::SRL) {
500 std::swap(Op0Opc, Op1Opc);
501 std::swap(TargetMask, InsertMask);
504 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
505 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
506 Op1.getOperand(0).getOpcode() != ISD::SRL) {
508 std::swap(Op0Opc, Op1Opc);
509 std::swap(TargetMask, InsertMask);
514 if (isRunOfOnes(InsertMask, MB, ME)) {
517 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
518 isInt32Immediate(Op1.getOperand(1), Value)) {
519 Op1 = Op1.getOperand(0);
520 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
522 if (Op1Opc == ISD::AND) {
523 // The AND mask might not be a constant, and we need to make sure that
524 // if we're going to fold the masking with the insert, all bits not
525 // know to be zero in the mask are known to be one.
527 CurDAG->computeKnownBits(Op1.getOperand(1), MKZ, MKO);
528 bool CanFoldMask = InsertMask == MKO.getZExtValue();
530 unsigned SHOpc = Op1.getOperand(0).getOpcode();
531 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) && CanFoldMask &&
532 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
533 // Note that Value must be in range here (less than 32) because
534 // otherwise there would not be any bits set in InsertMask.
535 Op1 = Op1.getOperand(0).getOperand(0);
536 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
541 SDValue Ops[] = { Op0, Op1, getI32Imm(SH), getI32Imm(MB),
543 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
549 // Predict the number of instructions that would be generated by calling
551 static unsigned SelectInt64CountDirect(int64_t Imm) {
552 // Assume no remaining bits.
553 unsigned Remainder = 0;
554 // Assume no shift required.
557 // If it can't be represented as a 32 bit value.
558 if (!isInt<32>(Imm)) {
559 Shift = countTrailingZeros<uint64_t>(Imm);
560 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
562 // If the shifted value fits 32 bits.
563 if (isInt<32>(ImmSh)) {
564 // Go with the shifted value.
567 // Still stuck with a 64 bit value.
574 // Intermediate operand.
577 // Handle first 32 bits.
578 unsigned Lo = Imm & 0xFFFF;
579 unsigned Hi = (Imm >> 16) & 0xFFFF;
582 if (isInt<16>(Imm)) {
586 // Handle the Hi bits and Lo bits.
593 // If no shift, we're done.
594 if (!Shift) return Result;
596 // Shift for next step if the upper 32-bits were not zero.
600 // Add in the last bits as required.
601 if ((Hi = (Remainder >> 16) & 0xFFFF))
603 if ((Lo = Remainder & 0xFFFF))
609 static uint64_t Rot64(uint64_t Imm, unsigned R) {
610 return (Imm << R) | (Imm >> (64 - R));
613 static unsigned SelectInt64Count(int64_t Imm) {
614 unsigned Count = SelectInt64CountDirect(Imm);
618 for (unsigned r = 1; r < 63; ++r) {
619 uint64_t RImm = Rot64(Imm, r);
620 unsigned RCount = SelectInt64CountDirect(RImm) + 1;
621 Count = std::min(Count, RCount);
623 // See comments in SelectInt64 for an explanation of the logic below.
624 unsigned LS = findLastSet(RImm);
628 uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
629 uint64_t RImmWithOnes = RImm | OnesMask;
631 RCount = SelectInt64CountDirect(RImmWithOnes) + 1;
632 Count = std::min(Count, RCount);
638 // Select a 64-bit constant. For cost-modeling purposes, SelectInt64Count
639 // (above) needs to be kept in sync with this function.
640 static SDNode *SelectInt64Direct(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
641 // Assume no remaining bits.
642 unsigned Remainder = 0;
643 // Assume no shift required.
646 // If it can't be represented as a 32 bit value.
647 if (!isInt<32>(Imm)) {
648 Shift = countTrailingZeros<uint64_t>(Imm);
649 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
651 // If the shifted value fits 32 bits.
652 if (isInt<32>(ImmSh)) {
653 // Go with the shifted value.
656 // Still stuck with a 64 bit value.
663 // Intermediate operand.
666 // Handle first 32 bits.
667 unsigned Lo = Imm & 0xFFFF;
668 unsigned Hi = (Imm >> 16) & 0xFFFF;
670 auto getI32Imm = [CurDAG](unsigned Imm) {
671 return CurDAG->getTargetConstant(Imm, MVT::i32);
675 if (isInt<16>(Imm)) {
677 Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
679 // Handle the Hi bits.
680 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
681 Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
683 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
684 SDValue(Result, 0), getI32Imm(Lo));
687 Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
690 // If no shift, we're done.
691 if (!Shift) return Result;
693 // Shift for next step if the upper 32-bits were not zero.
695 Result = CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64,
698 getI32Imm(63 - Shift));
701 // Add in the last bits as required.
702 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
703 Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
704 SDValue(Result, 0), getI32Imm(Hi));
706 if ((Lo = Remainder & 0xFFFF)) {
707 Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
708 SDValue(Result, 0), getI32Imm(Lo));
714 static SDNode *SelectInt64(SelectionDAG *CurDAG, SDLoc dl, int64_t Imm) {
715 unsigned Count = SelectInt64CountDirect(Imm);
717 return SelectInt64Direct(CurDAG, dl, Imm);
724 for (unsigned r = 1; r < 63; ++r) {
725 uint64_t RImm = Rot64(Imm, r);
726 unsigned RCount = SelectInt64CountDirect(RImm) + 1;
727 if (RCount < Count) {
734 // If the immediate to generate has many trailing zeros, it might be
735 // worthwhile to generate a rotated value with too many leading ones
736 // (because that's free with li/lis's sign-extension semantics), and then
737 // mask them off after rotation.
739 unsigned LS = findLastSet(RImm);
740 // We're adding (63-LS) higher-order ones, and we expect to mask them off
741 // after performing the inverse rotation by (64-r). So we need that:
742 // 63-LS == 64-r => LS == r-1
746 uint64_t OnesMask = -(int64_t) (UINT64_C(1) << (LS+1));
747 uint64_t RImmWithOnes = RImm | OnesMask;
749 RCount = SelectInt64CountDirect(RImmWithOnes) + 1;
750 if (RCount < Count) {
753 MatImm = RImmWithOnes;
759 return SelectInt64Direct(CurDAG, dl, Imm);
761 auto getI32Imm = [CurDAG](unsigned Imm) {
762 return CurDAG->getTargetConstant(Imm, MVT::i32);
765 SDValue Val = SDValue(SelectInt64Direct(CurDAG, dl, MatImm), 0);
766 return CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Val,
767 getI32Imm(64 - RMin), getI32Imm(MaskEnd));
770 // Select a 64-bit constant.
771 static SDNode *SelectInt64(SelectionDAG *CurDAG, SDNode *N) {
775 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue();
776 return SelectInt64(CurDAG, dl, Imm);
780 class BitPermutationSelector {
784 // The bit number in the value, using a convention where bit 0 is the
793 ValueBit(SDValue V, unsigned I, Kind K = Variable)
794 : V(V), Idx(I), K(K) {}
795 ValueBit(Kind K = Variable)
796 : V(SDValue(nullptr, 0)), Idx(UINT32_MAX), K(K) {}
798 bool isZero() const {
799 return K == ConstZero;
802 bool hasValue() const {
803 return K == Variable;
806 SDValue getValue() const {
807 assert(hasValue() && "Cannot get the value of a constant bit");
811 unsigned getValueBitIndex() const {
812 assert(hasValue() && "Cannot get the value bit index of a constant bit");
817 // A bit group has the same underlying value and the same rotate factor.
821 unsigned StartIdx, EndIdx;
823 // This rotation amount assumes that the lower 32 bits of the quantity are
824 // replicated in the high 32 bits by the rotation operator (which is done
825 // by rlwinm and friends in 64-bit mode).
827 // Did converting to Repl32 == true change the rotation factor? If it did,
828 // it decreased it by 32.
830 // Was this group coalesced after setting Repl32 to true?
831 bool Repl32Coalesced;
833 BitGroup(SDValue V, unsigned R, unsigned S, unsigned E)
834 : V(V), RLAmt(R), StartIdx(S), EndIdx(E), Repl32(false), Repl32CR(false),
835 Repl32Coalesced(false) {
836 DEBUG(dbgs() << "\tbit group for " << V.getNode() << " RLAmt = " << R <<
837 " [" << S << ", " << E << "]\n");
841 // Information on each (Value, RLAmt) pair (like the number of groups
842 // associated with each) used to choose the lowering method.
843 struct ValueRotInfo {
847 unsigned FirstGroupStartIdx;
851 : RLAmt(UINT32_MAX), NumGroups(0), FirstGroupStartIdx(UINT32_MAX),
854 // For sorting (in reverse order) by NumGroups, and then by
855 // FirstGroupStartIdx.
856 bool operator < (const ValueRotInfo &Other) const {
857 // We need to sort so that the non-Repl32 come first because, when we're
858 // doing masking, the Repl32 bit groups might be subsumed into the 64-bit
859 // masking operation.
860 if (Repl32 < Other.Repl32)
862 else if (Repl32 > Other.Repl32)
864 else if (NumGroups > Other.NumGroups)
866 else if (NumGroups < Other.NumGroups)
868 else if (FirstGroupStartIdx < Other.FirstGroupStartIdx)
874 // Return true if something interesting was deduced, return false if we're
875 // providing only a generic representation of V (or something else likewise
876 // uninteresting for instruction selection).
877 bool getValueBits(SDValue V, SmallVector<ValueBit, 64> &Bits) {
878 switch (V.getOpcode()) {
881 if (isa<ConstantSDNode>(V.getOperand(1))) {
882 unsigned RotAmt = V.getConstantOperandVal(1);
884 SmallVector<ValueBit, 64> LHSBits(Bits.size());
885 getValueBits(V.getOperand(0), LHSBits);
887 for (unsigned i = 0; i < Bits.size(); ++i)
888 Bits[i] = LHSBits[i < RotAmt ? i + (Bits.size() - RotAmt) : i - RotAmt];
894 if (isa<ConstantSDNode>(V.getOperand(1))) {
895 unsigned ShiftAmt = V.getConstantOperandVal(1);
897 SmallVector<ValueBit, 64> LHSBits(Bits.size());
898 getValueBits(V.getOperand(0), LHSBits);
900 for (unsigned i = ShiftAmt; i < Bits.size(); ++i)
901 Bits[i] = LHSBits[i - ShiftAmt];
903 for (unsigned i = 0; i < ShiftAmt; ++i)
904 Bits[i] = ValueBit(ValueBit::ConstZero);
910 if (isa<ConstantSDNode>(V.getOperand(1))) {
911 unsigned ShiftAmt = V.getConstantOperandVal(1);
913 SmallVector<ValueBit, 64> LHSBits(Bits.size());
914 getValueBits(V.getOperand(0), LHSBits);
916 for (unsigned i = 0; i < Bits.size() - ShiftAmt; ++i)
917 Bits[i] = LHSBits[i + ShiftAmt];
919 for (unsigned i = Bits.size() - ShiftAmt; i < Bits.size(); ++i)
920 Bits[i] = ValueBit(ValueBit::ConstZero);
926 if (isa<ConstantSDNode>(V.getOperand(1))) {
927 uint64_t Mask = V.getConstantOperandVal(1);
929 SmallVector<ValueBit, 64> LHSBits(Bits.size());
930 bool LHSTrivial = getValueBits(V.getOperand(0), LHSBits);
932 for (unsigned i = 0; i < Bits.size(); ++i)
933 if (((Mask >> i) & 1) == 1)
934 Bits[i] = LHSBits[i];
936 Bits[i] = ValueBit(ValueBit::ConstZero);
938 // Mark this as interesting, only if the LHS was also interesting. This
939 // prevents the overall procedure from matching a single immediate 'and'
940 // (which is non-optimal because such an and might be folded with other
941 // things if we don't select it here).
946 SmallVector<ValueBit, 64> LHSBits(Bits.size()), RHSBits(Bits.size());
947 getValueBits(V.getOperand(0), LHSBits);
948 getValueBits(V.getOperand(1), RHSBits);
950 bool AllDisjoint = true;
951 for (unsigned i = 0; i < Bits.size(); ++i)
952 if (LHSBits[i].isZero())
953 Bits[i] = RHSBits[i];
954 else if (RHSBits[i].isZero())
955 Bits[i] = LHSBits[i];
968 for (unsigned i = 0; i < Bits.size(); ++i)
969 Bits[i] = ValueBit(V, i);
974 // For each value (except the constant ones), compute the left-rotate amount
975 // to get it from its original to final position.
976 void computeRotationAmounts() {
978 RLAmt.resize(Bits.size());
979 for (unsigned i = 0; i < Bits.size(); ++i)
980 if (Bits[i].hasValue()) {
981 unsigned VBI = Bits[i].getValueBitIndex();
985 RLAmt[i] = Bits.size() - (VBI - i);
986 } else if (Bits[i].isZero()) {
988 RLAmt[i] = UINT32_MAX;
990 llvm_unreachable("Unknown value bit type");
994 // Collect groups of consecutive bits with the same underlying value and
995 // rotation factor. If we're doing late masking, we ignore zeros, otherwise
996 // they break up groups.
997 void collectBitGroups(bool LateMask) {
1000 unsigned LastRLAmt = RLAmt[0];
1001 SDValue LastValue = Bits[0].hasValue() ? Bits[0].getValue() : SDValue();
1002 unsigned LastGroupStartIdx = 0;
1003 for (unsigned i = 1; i < Bits.size(); ++i) {
1004 unsigned ThisRLAmt = RLAmt[i];
1005 SDValue ThisValue = Bits[i].hasValue() ? Bits[i].getValue() : SDValue();
1006 if (LateMask && !ThisValue) {
1007 ThisValue = LastValue;
1008 ThisRLAmt = LastRLAmt;
1009 // If we're doing late masking, then the first bit group always starts
1010 // at zero (even if the first bits were zero).
1011 if (BitGroups.empty())
1012 LastGroupStartIdx = 0;
1015 // If this bit has the same underlying value and the same rotate factor as
1016 // the last one, then they're part of the same group.
1017 if (ThisRLAmt == LastRLAmt && ThisValue == LastValue)
1020 if (LastValue.getNode())
1021 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1023 LastRLAmt = ThisRLAmt;
1024 LastValue = ThisValue;
1025 LastGroupStartIdx = i;
1027 if (LastValue.getNode())
1028 BitGroups.push_back(BitGroup(LastValue, LastRLAmt, LastGroupStartIdx,
1031 if (BitGroups.empty())
1034 // We might be able to combine the first and last groups.
1035 if (BitGroups.size() > 1) {
1036 // If the first and last groups are the same, then remove the first group
1037 // in favor of the last group, making the ending index of the last group
1038 // equal to the ending index of the to-be-removed first group.
1039 if (BitGroups[0].StartIdx == 0 &&
1040 BitGroups[BitGroups.size()-1].EndIdx == Bits.size()-1 &&
1041 BitGroups[0].V == BitGroups[BitGroups.size()-1].V &&
1042 BitGroups[0].RLAmt == BitGroups[BitGroups.size()-1].RLAmt) {
1043 DEBUG(dbgs() << "\tcombining final bit group with inital one\n");
1044 BitGroups[BitGroups.size()-1].EndIdx = BitGroups[0].EndIdx;
1045 BitGroups.erase(BitGroups.begin());
1050 // Take all (SDValue, RLAmt) pairs and sort them by the number of groups
1051 // associated with each. If there is a degeneracy, pick the one that occurs
1052 // first (in the final value).
1053 void collectValueRotInfo() {
1056 for (auto &BG : BitGroups) {
1057 unsigned RLAmtKey = BG.RLAmt + (BG.Repl32 ? 64 : 0);
1058 ValueRotInfo &VRI = ValueRots[std::make_pair(BG.V, RLAmtKey)];
1060 VRI.RLAmt = BG.RLAmt;
1061 VRI.Repl32 = BG.Repl32;
1063 VRI.FirstGroupStartIdx = std::min(VRI.FirstGroupStartIdx, BG.StartIdx);
1066 // Now that we've collected the various ValueRotInfo instances, we need to
1068 ValueRotsVec.clear();
1069 for (auto &I : ValueRots) {
1070 ValueRotsVec.push_back(I.second);
1072 std::sort(ValueRotsVec.begin(), ValueRotsVec.end());
1075 // In 64-bit mode, rlwinm and friends have a rotation operator that
1076 // replicates the low-order 32 bits into the high-order 32-bits. The mask
1077 // indices of these instructions can only be in the lower 32 bits, so they
1078 // can only represent some 64-bit bit groups. However, when they can be used,
1079 // the 32-bit replication can be used to represent, as a single bit group,
1080 // otherwise separate bit groups. We'll convert to replicated-32-bit bit
1081 // groups when possible. Returns true if any of the bit groups were
1083 void assignRepl32BitGroups() {
1084 // If we have bits like this:
1086 // Indices: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1087 // V bits: ... 7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24
1088 // Groups: | RLAmt = 8 | RLAmt = 40 |
1090 // But, making use of a 32-bit operation that replicates the low-order 32
1091 // bits into the high-order 32 bits, this can be one bit group with a RLAmt
1094 auto IsAllLow32 = [this](BitGroup & BG) {
1095 if (BG.StartIdx <= BG.EndIdx) {
1096 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i) {
1097 if (!Bits[i].hasValue())
1099 if (Bits[i].getValueBitIndex() >= 32)
1103 for (unsigned i = BG.StartIdx; i < Bits.size(); ++i) {
1104 if (!Bits[i].hasValue())
1106 if (Bits[i].getValueBitIndex() >= 32)
1109 for (unsigned i = 0; i <= BG.EndIdx; ++i) {
1110 if (!Bits[i].hasValue())
1112 if (Bits[i].getValueBitIndex() >= 32)
1120 for (auto &BG : BitGroups) {
1121 if (BG.StartIdx < 32 && BG.EndIdx < 32) {
1122 if (IsAllLow32(BG)) {
1123 if (BG.RLAmt >= 32) {
1130 DEBUG(dbgs() << "\t32-bit replicated bit group for " <<
1131 BG.V.getNode() << " RLAmt = " << BG.RLAmt <<
1132 " [" << BG.StartIdx << ", " << BG.EndIdx << "]\n");
1137 // Now walk through the bit groups, consolidating where possible.
1138 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1139 // We might want to remove this bit group by merging it with the previous
1140 // group (which might be the ending group).
1141 auto IP = (I == BitGroups.begin()) ?
1142 std::prev(BitGroups.end()) : std::prev(I);
1143 if (I->Repl32 && IP->Repl32 && I->V == IP->V && I->RLAmt == IP->RLAmt &&
1144 I->StartIdx == (IP->EndIdx + 1) % 64 && I != IP) {
1146 DEBUG(dbgs() << "\tcombining 32-bit replicated bit group for " <<
1147 I->V.getNode() << " RLAmt = " << I->RLAmt <<
1148 " [" << I->StartIdx << ", " << I->EndIdx <<
1149 "] with group with range [" <<
1150 IP->StartIdx << ", " << IP->EndIdx << "]\n");
1152 IP->EndIdx = I->EndIdx;
1153 IP->Repl32CR = IP->Repl32CR || I->Repl32CR;
1154 IP->Repl32Coalesced = true;
1155 I = BitGroups.erase(I);
1158 // There is a special case worth handling: If there is a single group
1159 // covering the entire upper 32 bits, and it can be merged with both
1160 // the next and previous groups (which might be the same group), then
1161 // do so. If it is the same group (so there will be only one group in
1162 // total), then we need to reverse the order of the range so that it
1163 // covers the entire 64 bits.
1164 if (I->StartIdx == 32 && I->EndIdx == 63) {
1165 assert(std::next(I) == BitGroups.end() &&
1166 "bit group ends at index 63 but there is another?");
1167 auto IN = BitGroups.begin();
1169 if (IP->Repl32 && IN->Repl32 && I->V == IP->V && I->V == IN->V &&
1170 (I->RLAmt % 32) == IP->RLAmt && (I->RLAmt % 32) == IN->RLAmt &&
1171 IP->EndIdx == 31 && IN->StartIdx == 0 && I != IP &&
1174 DEBUG(dbgs() << "\tcombining bit group for " <<
1175 I->V.getNode() << " RLAmt = " << I->RLAmt <<
1176 " [" << I->StartIdx << ", " << I->EndIdx <<
1177 "] with 32-bit replicated groups with ranges [" <<
1178 IP->StartIdx << ", " << IP->EndIdx << "] and [" <<
1179 IN->StartIdx << ", " << IN->EndIdx << "]\n");
1182 // There is only one other group; change it to cover the whole
1183 // range (backward, so that it can still be Repl32 but cover the
1184 // whole 64-bit range).
1187 IP->Repl32CR = IP->Repl32CR || I->RLAmt >= 32;
1188 IP->Repl32Coalesced = true;
1189 I = BitGroups.erase(I);
1191 // There are two separate groups, one before this group and one
1192 // after us (at the beginning). We're going to remove this group,
1193 // but also the group at the very beginning.
1194 IP->EndIdx = IN->EndIdx;
1195 IP->Repl32CR = IP->Repl32CR || IN->Repl32CR || I->RLAmt >= 32;
1196 IP->Repl32Coalesced = true;
1197 I = BitGroups.erase(I);
1198 BitGroups.erase(BitGroups.begin());
1201 // This must be the last group in the vector (and we might have
1202 // just invalidated the iterator above), so break here.
1212 SDValue getI32Imm(unsigned Imm) {
1213 return CurDAG->getTargetConstant(Imm, MVT::i32);
1216 uint64_t getZerosMask() {
1218 for (unsigned i = 0; i < Bits.size(); ++i) {
1219 if (Bits[i].hasValue())
1221 Mask |= (UINT64_C(1) << i);
1227 // Depending on the number of groups for a particular value, it might be
1228 // better to rotate, mask explicitly (using andi/andis), and then or the
1229 // result. Select this part of the result first.
1230 void SelectAndParts32(SDLoc dl, SDValue &Res, unsigned *InstCnt) {
1231 if (BPermRewriterNoMasking)
1234 for (ValueRotInfo &VRI : ValueRotsVec) {
1236 for (unsigned i = 0; i < Bits.size(); ++i) {
1237 if (!Bits[i].hasValue() || Bits[i].getValue() != VRI.V)
1239 if (RLAmt[i] != VRI.RLAmt)
1244 // Compute the masks for andi/andis that would be necessary.
1245 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1246 assert((ANDIMask != 0 || ANDISMask != 0) &&
1247 "No set bits in mask for value bit groups");
1248 bool NeedsRotate = VRI.RLAmt != 0;
1250 // We're trying to minimize the number of instructions. If we have one
1251 // group, using one of andi/andis can break even. If we have three
1252 // groups, we can use both andi and andis and break even (to use both
1253 // andi and andis we also need to or the results together). We need four
1254 // groups if we also need to rotate. To use andi/andis we need to do more
1255 // than break even because rotate-and-mask instructions tend to be easier
1258 // FIXME: We've biased here against using andi/andis, which is right for
1259 // POWER cores, but not optimal everywhere. For example, on the A2,
1260 // andi/andis have single-cycle latency whereas the rotate-and-mask
1261 // instructions take two cycles, and it would be better to bias toward
1262 // andi/andis in break-even cases.
1264 unsigned NumAndInsts = (unsigned) NeedsRotate +
1265 (unsigned) (ANDIMask != 0) +
1266 (unsigned) (ANDISMask != 0) +
1267 (unsigned) (ANDIMask != 0 && ANDISMask != 0) +
1268 (unsigned) (bool) Res;
1270 DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode() <<
1271 " RL: " << VRI.RLAmt << ":" <<
1272 "\n\t\t\tisel using masking: " << NumAndInsts <<
1273 " using rotates: " << VRI.NumGroups << "\n");
1275 if (NumAndInsts >= VRI.NumGroups)
1278 DEBUG(dbgs() << "\t\t\t\tusing masking\n");
1280 if (InstCnt) *InstCnt += NumAndInsts;
1285 { VRI.V, getI32Imm(VRI.RLAmt), getI32Imm(0), getI32Imm(31) };
1286 VRot = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32,
1292 SDValue ANDIVal, ANDISVal;
1294 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1295 VRot, getI32Imm(ANDIMask)), 0);
1297 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1298 VRot, getI32Imm(ANDISMask)), 0);
1302 TotalVal = ANDISVal;
1306 TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1307 ANDIVal, ANDISVal), 0);
1312 Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1315 // Now, remove all groups with this underlying value and rotation
1317 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1318 if (I->V == VRI.V && I->RLAmt == VRI.RLAmt)
1319 I = BitGroups.erase(I);
1326 // Instruction selection for the 32-bit case.
1327 SDNode *Select32(SDNode *N, bool LateMask, unsigned *InstCnt) {
1331 if (InstCnt) *InstCnt = 0;
1333 // Take care of cases that should use andi/andis first.
1334 SelectAndParts32(dl, Res, InstCnt);
1336 // If we've not yet selected a 'starting' instruction, and we have no zeros
1337 // to fill in, select the (Value, RLAmt) with the highest priority (largest
1338 // number of groups), and start with this rotated value.
1339 if ((!HasZeros || LateMask) && !Res) {
1340 ValueRotInfo &VRI = ValueRotsVec[0];
1342 if (InstCnt) *InstCnt += 1;
1344 { VRI.V, getI32Imm(VRI.RLAmt), getI32Imm(0), getI32Imm(31) };
1345 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
1350 // Now, remove all groups with this underlying value and rotation factor.
1351 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1352 if (I->V == VRI.V && I->RLAmt == VRI.RLAmt)
1353 I = BitGroups.erase(I);
1359 if (InstCnt) *InstCnt += BitGroups.size();
1361 // Insert the other groups (one at a time).
1362 for (auto &BG : BitGroups) {
1365 { BG.V, getI32Imm(BG.RLAmt), getI32Imm(Bits.size() - BG.EndIdx - 1),
1366 getI32Imm(Bits.size() - BG.StartIdx - 1) };
1367 Res = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
1370 { Res, BG.V, getI32Imm(BG.RLAmt), getI32Imm(Bits.size() - BG.EndIdx - 1),
1371 getI32Imm(Bits.size() - BG.StartIdx - 1) };
1372 Res = SDValue(CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops), 0);
1377 unsigned Mask = (unsigned) getZerosMask();
1379 unsigned ANDIMask = (Mask & UINT16_MAX), ANDISMask = Mask >> 16;
1380 assert((ANDIMask != 0 || ANDISMask != 0) &&
1381 "No set bits in zeros mask?");
1383 if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
1384 (unsigned) (ANDISMask != 0) +
1385 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1387 SDValue ANDIVal, ANDISVal;
1389 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo, dl, MVT::i32,
1390 Res, getI32Imm(ANDIMask)), 0);
1392 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo, dl, MVT::i32,
1393 Res, getI32Imm(ANDISMask)), 0);
1400 Res = SDValue(CurDAG->getMachineNode(PPC::OR, dl, MVT::i32,
1401 ANDIVal, ANDISVal), 0);
1404 return Res.getNode();
1407 unsigned SelectRotMask64Count(unsigned RLAmt, bool Repl32,
1408 unsigned MaskStart, unsigned MaskEnd,
1410 // In the notation used by the instructions, 'start' and 'end' are reversed
1411 // because bits are counted from high to low order.
1412 unsigned InstMaskStart = 64 - MaskEnd - 1,
1413 InstMaskEnd = 64 - MaskStart - 1;
1418 if ((!IsIns && (InstMaskEnd == 63 || InstMaskStart == 0)) ||
1419 InstMaskEnd == 63 - RLAmt)
1425 // For 64-bit values, not all combinations of rotates and masks are
1426 // available. Produce one if it is available.
1427 SDValue SelectRotMask64(SDValue V, SDLoc dl, unsigned RLAmt, bool Repl32,
1428 unsigned MaskStart, unsigned MaskEnd,
1429 unsigned *InstCnt = nullptr) {
1430 // In the notation used by the instructions, 'start' and 'end' are reversed
1431 // because bits are counted from high to low order.
1432 unsigned InstMaskStart = 64 - MaskEnd - 1,
1433 InstMaskEnd = 64 - MaskStart - 1;
1435 if (InstCnt) *InstCnt += 1;
1438 // This rotation amount assumes that the lower 32 bits of the quantity
1439 // are replicated in the high 32 bits by the rotation operator (which is
1440 // done by rlwinm and friends).
1441 assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1442 assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1444 { V, getI32Imm(RLAmt), getI32Imm(InstMaskStart - 32),
1445 getI32Imm(InstMaskEnd - 32) };
1446 return SDValue(CurDAG->getMachineNode(PPC::RLWINM8, dl, MVT::i64,
1450 if (InstMaskEnd == 63) {
1452 { V, getI32Imm(RLAmt), getI32Imm(InstMaskStart) };
1453 return SDValue(CurDAG->getMachineNode(PPC::RLDICL, dl, MVT::i64, Ops), 0);
1456 if (InstMaskStart == 0) {
1458 { V, getI32Imm(RLAmt), getI32Imm(InstMaskEnd) };
1459 return SDValue(CurDAG->getMachineNode(PPC::RLDICR, dl, MVT::i64, Ops), 0);
1462 if (InstMaskEnd == 63 - RLAmt) {
1464 { V, getI32Imm(RLAmt), getI32Imm(InstMaskStart) };
1465 return SDValue(CurDAG->getMachineNode(PPC::RLDIC, dl, MVT::i64, Ops), 0);
1468 // We cannot do this with a single instruction, so we'll use two. The
1469 // problem is that we're not free to choose both a rotation amount and mask
1470 // start and end independently. We can choose an arbitrary mask start and
1471 // end, but then the rotation amount is fixed. Rotation, however, can be
1472 // inverted, and so by applying an "inverse" rotation first, we can get the
1474 if (InstCnt) *InstCnt += 1;
1476 // The rotation mask for the second instruction must be MaskStart.
1477 unsigned RLAmt2 = MaskStart;
1478 // The first instruction must rotate V so that the overall rotation amount
1480 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1482 V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
1483 return SelectRotMask64(V, dl, RLAmt2, false, MaskStart, MaskEnd);
1486 // For 64-bit values, not all combinations of rotates and masks are
1487 // available. Produce a rotate-mask-and-insert if one is available.
1488 SDValue SelectRotMaskIns64(SDValue Base, SDValue V, SDLoc dl, unsigned RLAmt,
1489 bool Repl32, unsigned MaskStart,
1490 unsigned MaskEnd, unsigned *InstCnt = nullptr) {
1491 // In the notation used by the instructions, 'start' and 'end' are reversed
1492 // because bits are counted from high to low order.
1493 unsigned InstMaskStart = 64 - MaskEnd - 1,
1494 InstMaskEnd = 64 - MaskStart - 1;
1496 if (InstCnt) *InstCnt += 1;
1499 // This rotation amount assumes that the lower 32 bits of the quantity
1500 // are replicated in the high 32 bits by the rotation operator (which is
1501 // done by rlwinm and friends).
1502 assert(InstMaskStart >= 32 && "Mask cannot start out of range");
1503 assert(InstMaskEnd >= 32 && "Mask cannot end out of range");
1505 { Base, V, getI32Imm(RLAmt), getI32Imm(InstMaskStart - 32),
1506 getI32Imm(InstMaskEnd - 32) };
1507 return SDValue(CurDAG->getMachineNode(PPC::RLWIMI8, dl, MVT::i64,
1511 if (InstMaskEnd == 63 - RLAmt) {
1513 { Base, V, getI32Imm(RLAmt), getI32Imm(InstMaskStart) };
1514 return SDValue(CurDAG->getMachineNode(PPC::RLDIMI, dl, MVT::i64, Ops), 0);
1517 // We cannot do this with a single instruction, so we'll use two. The
1518 // problem is that we're not free to choose both a rotation amount and mask
1519 // start and end independently. We can choose an arbitrary mask start and
1520 // end, but then the rotation amount is fixed. Rotation, however, can be
1521 // inverted, and so by applying an "inverse" rotation first, we can get the
1523 if (InstCnt) *InstCnt += 1;
1525 // The rotation mask for the second instruction must be MaskStart.
1526 unsigned RLAmt2 = MaskStart;
1527 // The first instruction must rotate V so that the overall rotation amount
1529 unsigned RLAmt1 = (64 + RLAmt - RLAmt2) % 64;
1531 V = SelectRotMask64(V, dl, RLAmt1, false, 0, 63);
1532 return SelectRotMaskIns64(Base, V, dl, RLAmt2, false, MaskStart, MaskEnd);
1535 void SelectAndParts64(SDLoc dl, SDValue &Res, unsigned *InstCnt) {
1536 if (BPermRewriterNoMasking)
1539 // The idea here is the same as in the 32-bit version, but with additional
1540 // complications from the fact that Repl32 might be true. Because we
1541 // aggressively convert bit groups to Repl32 form (which, for small
1542 // rotation factors, involves no other change), and then coalesce, it might
1543 // be the case that a single 64-bit masking operation could handle both
1544 // some Repl32 groups and some non-Repl32 groups. If converting to Repl32
1545 // form allowed coalescing, then we must use a 32-bit rotaton in order to
1546 // completely capture the new combined bit group.
1548 for (ValueRotInfo &VRI : ValueRotsVec) {
1551 // We need to add to the mask all bits from the associated bit groups.
1552 // If Repl32 is false, we need to add bits from bit groups that have
1553 // Repl32 true, but are trivially convertable to Repl32 false. Such a
1554 // group is trivially convertable if it overlaps only with the lower 32
1555 // bits, and the group has not been coalesced.
1556 auto MatchingBG = [VRI](BitGroup &BG) {
1560 unsigned EffRLAmt = BG.RLAmt;
1561 if (!VRI.Repl32 && BG.Repl32) {
1562 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx <= BG.EndIdx &&
1563 !BG.Repl32Coalesced) {
1569 } else if (VRI.Repl32 != BG.Repl32) {
1573 if (VRI.RLAmt != EffRLAmt)
1579 for (auto &BG : BitGroups) {
1580 if (!MatchingBG(BG))
1583 if (BG.StartIdx <= BG.EndIdx) {
1584 for (unsigned i = BG.StartIdx; i <= BG.EndIdx; ++i)
1585 Mask |= (UINT64_C(1) << i);
1587 for (unsigned i = BG.StartIdx; i < Bits.size(); ++i)
1588 Mask |= (UINT64_C(1) << i);
1589 for (unsigned i = 0; i <= BG.EndIdx; ++i)
1590 Mask |= (UINT64_C(1) << i);
1594 // We can use the 32-bit andi/andis technique if the mask does not
1595 // require any higher-order bits. This can save an instruction compared
1596 // to always using the general 64-bit technique.
1597 bool Use32BitInsts = isUInt<32>(Mask);
1598 // Compute the masks for andi/andis that would be necessary.
1599 unsigned ANDIMask = (Mask & UINT16_MAX),
1600 ANDISMask = (Mask >> 16) & UINT16_MAX;
1602 bool NeedsRotate = VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask));
1604 unsigned NumAndInsts = (unsigned) NeedsRotate +
1605 (unsigned) (bool) Res;
1607 NumAndInsts += (unsigned) (ANDIMask != 0) + (unsigned) (ANDISMask != 0) +
1608 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1610 NumAndInsts += SelectInt64Count(Mask) + /* and */ 1;
1612 unsigned NumRLInsts = 0;
1613 bool FirstBG = true;
1614 for (auto &BG : BitGroups) {
1615 if (!MatchingBG(BG))
1618 SelectRotMask64Count(BG.RLAmt, BG.Repl32, BG.StartIdx, BG.EndIdx,
1623 DEBUG(dbgs() << "\t\trotation groups for " << VRI.V.getNode() <<
1624 " RL: " << VRI.RLAmt << (VRI.Repl32 ? " (32):" : ":") <<
1625 "\n\t\t\tisel using masking: " << NumAndInsts <<
1626 " using rotates: " << NumRLInsts << "\n");
1628 // When we'd use andi/andis, we bias toward using the rotates (andi only
1629 // has a record form, and is cracked on POWER cores). However, when using
1630 // general 64-bit constant formation, bias toward the constant form,
1631 // because that exposes more opportunities for CSE.
1632 if (NumAndInsts > NumRLInsts)
1634 if (Use32BitInsts && NumAndInsts == NumRLInsts)
1637 DEBUG(dbgs() << "\t\t\t\tusing masking\n");
1639 if (InstCnt) *InstCnt += NumAndInsts;
1642 // We actually need to generate a rotation if we have a non-zero rotation
1643 // factor or, in the Repl32 case, if we care about any of the
1644 // higher-order replicated bits. In the latter case, we generate a mask
1645 // backward so that it actually includes the entire 64 bits.
1646 if (VRI.RLAmt || (VRI.Repl32 && !isUInt<32>(Mask)))
1647 VRot = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
1648 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63);
1653 if (Use32BitInsts) {
1654 assert((ANDIMask != 0 || ANDISMask != 0) &&
1655 "No set bits in mask when using 32-bit ands for 64-bit value");
1657 SDValue ANDIVal, ANDISVal;
1659 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
1660 VRot, getI32Imm(ANDIMask)), 0);
1662 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
1663 VRot, getI32Imm(ANDISMask)), 0);
1666 TotalVal = ANDISVal;
1670 TotalVal = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1671 ANDIVal, ANDISVal), 0);
1673 TotalVal = SDValue(SelectInt64(CurDAG, dl, Mask), 0);
1675 SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
1676 VRot, TotalVal), 0);
1682 Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1685 // Now, remove all groups with this underlying value and rotation
1687 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1689 I = BitGroups.erase(I);
1696 // Instruction selection for the 64-bit case.
1697 SDNode *Select64(SDNode *N, bool LateMask, unsigned *InstCnt) {
1701 if (InstCnt) *InstCnt = 0;
1703 // Take care of cases that should use andi/andis first.
1704 SelectAndParts64(dl, Res, InstCnt);
1706 // If we've not yet selected a 'starting' instruction, and we have no zeros
1707 // to fill in, select the (Value, RLAmt) with the highest priority (largest
1708 // number of groups), and start with this rotated value.
1709 if ((!HasZeros || LateMask) && !Res) {
1710 // If we have both Repl32 groups and non-Repl32 groups, the non-Repl32
1711 // groups will come first, and so the VRI representing the largest number
1712 // of groups might not be first (it might be the first Repl32 groups).
1713 unsigned MaxGroupsIdx = 0;
1714 if (!ValueRotsVec[0].Repl32) {
1715 for (unsigned i = 0, ie = ValueRotsVec.size(); i < ie; ++i)
1716 if (ValueRotsVec[i].Repl32) {
1717 if (ValueRotsVec[i].NumGroups > ValueRotsVec[0].NumGroups)
1723 ValueRotInfo &VRI = ValueRotsVec[MaxGroupsIdx];
1724 bool NeedsRotate = false;
1727 } else if (VRI.Repl32) {
1728 for (auto &BG : BitGroups) {
1729 if (BG.V != VRI.V || BG.RLAmt != VRI.RLAmt ||
1730 BG.Repl32 != VRI.Repl32)
1733 // We don't need a rotate if the bit group is confined to the lower
1735 if (BG.StartIdx < 32 && BG.EndIdx < 32 && BG.StartIdx < BG.EndIdx)
1744 Res = SelectRotMask64(VRI.V, dl, VRI.RLAmt, VRI.Repl32,
1745 VRI.Repl32 ? 31 : 0, VRI.Repl32 ? 30 : 63,
1750 // Now, remove all groups with this underlying value and rotation factor.
1752 for (auto I = BitGroups.begin(); I != BitGroups.end();) {
1753 if (I->V == VRI.V && I->RLAmt == VRI.RLAmt && I->Repl32 == VRI.Repl32)
1754 I = BitGroups.erase(I);
1760 // Because 64-bit rotates are more flexible than inserts, we might have a
1761 // preference regarding which one we do first (to save one instruction).
1763 for (auto I = BitGroups.begin(), IE = BitGroups.end(); I != IE; ++I) {
1764 if (SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
1766 SelectRotMask64Count(I->RLAmt, I->Repl32, I->StartIdx, I->EndIdx,
1768 if (I != BitGroups.begin()) {
1771 BitGroups.insert(BitGroups.begin(), BG);
1778 // Insert the other groups (one at a time).
1779 for (auto &BG : BitGroups) {
1781 Res = SelectRotMask64(BG.V, dl, BG.RLAmt, BG.Repl32, BG.StartIdx,
1782 BG.EndIdx, InstCnt);
1784 Res = SelectRotMaskIns64(Res, BG.V, dl, BG.RLAmt, BG.Repl32,
1785 BG.StartIdx, BG.EndIdx, InstCnt);
1789 uint64_t Mask = getZerosMask();
1791 // We can use the 32-bit andi/andis technique if the mask does not
1792 // require any higher-order bits. This can save an instruction compared
1793 // to always using the general 64-bit technique.
1794 bool Use32BitInsts = isUInt<32>(Mask);
1795 // Compute the masks for andi/andis that would be necessary.
1796 unsigned ANDIMask = (Mask & UINT16_MAX),
1797 ANDISMask = (Mask >> 16) & UINT16_MAX;
1799 if (Use32BitInsts) {
1800 assert((ANDIMask != 0 || ANDISMask != 0) &&
1801 "No set bits in mask when using 32-bit ands for 64-bit value");
1803 if (InstCnt) *InstCnt += (unsigned) (ANDIMask != 0) +
1804 (unsigned) (ANDISMask != 0) +
1805 (unsigned) (ANDIMask != 0 && ANDISMask != 0);
1807 SDValue ANDIVal, ANDISVal;
1809 ANDIVal = SDValue(CurDAG->getMachineNode(PPC::ANDIo8, dl, MVT::i64,
1810 Res, getI32Imm(ANDIMask)), 0);
1812 ANDISVal = SDValue(CurDAG->getMachineNode(PPC::ANDISo8, dl, MVT::i64,
1813 Res, getI32Imm(ANDISMask)), 0);
1820 Res = SDValue(CurDAG->getMachineNode(PPC::OR8, dl, MVT::i64,
1821 ANDIVal, ANDISVal), 0);
1823 if (InstCnt) *InstCnt += SelectInt64Count(Mask) + /* and */ 1;
1825 SDValue MaskVal = SDValue(SelectInt64(CurDAG, dl, Mask), 0);
1827 SDValue(CurDAG->getMachineNode(PPC::AND8, dl, MVT::i64,
1832 return Res.getNode();
1835 SDNode *Select(SDNode *N, bool LateMask, unsigned *InstCnt = nullptr) {
1836 // Fill in BitGroups.
1837 collectBitGroups(LateMask);
1838 if (BitGroups.empty())
1841 // For 64-bit values, figure out when we can use 32-bit instructions.
1842 if (Bits.size() == 64)
1843 assignRepl32BitGroups();
1845 // Fill in ValueRotsVec.
1846 collectValueRotInfo();
1848 if (Bits.size() == 32) {
1849 return Select32(N, LateMask, InstCnt);
1851 assert(Bits.size() == 64 && "Not 64 bits here?");
1852 return Select64(N, LateMask, InstCnt);
1858 SmallVector<ValueBit, 64> Bits;
1861 SmallVector<unsigned, 64> RLAmt;
1863 SmallVector<BitGroup, 16> BitGroups;
1865 DenseMap<std::pair<SDValue, unsigned>, ValueRotInfo> ValueRots;
1866 SmallVector<ValueRotInfo, 16> ValueRotsVec;
1868 SelectionDAG *CurDAG;
1871 BitPermutationSelector(SelectionDAG *DAG)
1874 // Here we try to match complex bit permutations into a set of
1875 // rotate-and-shift/shift/and/or instructions, using a set of heuristics
1876 // known to produce optimial code for common cases (like i32 byte swapping).
1877 SDNode *Select(SDNode *N) {
1878 Bits.resize(N->getValueType(0).getSizeInBits());
1879 if (!getValueBits(SDValue(N, 0), Bits))
1882 DEBUG(dbgs() << "Considering bit-permutation-based instruction"
1883 " selection for: ");
1884 DEBUG(N->dump(CurDAG));
1886 // Fill it RLAmt and set HasZeros.
1887 computeRotationAmounts();
1890 return Select(N, false);
1892 // We currently have two techniques for handling results with zeros: early
1893 // masking (the default) and late masking. Late masking is sometimes more
1894 // efficient, but because the structure of the bit groups is different, it
1895 // is hard to tell without generating both and comparing the results. With
1896 // late masking, we ignore zeros in the resulting value when inserting each
1897 // set of bit groups, and then mask in the zeros at the end. With early
1898 // masking, we only insert the non-zero parts of the result at every step.
1900 unsigned InstCnt, InstCntLateMask;
1901 DEBUG(dbgs() << "\tEarly masking:\n");
1902 SDNode *RN = Select(N, false, &InstCnt);
1903 DEBUG(dbgs() << "\t\tisel would use " << InstCnt << " instructions\n");
1905 DEBUG(dbgs() << "\tLate masking:\n");
1906 SDNode *RNLM = Select(N, true, &InstCntLateMask);
1907 DEBUG(dbgs() << "\t\tisel would use " << InstCntLateMask <<
1910 if (InstCnt <= InstCntLateMask) {
1911 DEBUG(dbgs() << "\tUsing early-masking for isel\n");
1915 DEBUG(dbgs() << "\tUsing late-masking for isel\n");
1919 } // anonymous namespace
1921 SDNode *PPCDAGToDAGISel::SelectBitPermutation(SDNode *N) {
1922 if (N->getValueType(0) != MVT::i32 &&
1923 N->getValueType(0) != MVT::i64)
1926 if (!UseBitPermRewriter)
1929 switch (N->getOpcode()) {
1936 BitPermutationSelector BPS(CurDAG);
1937 return BPS.Select(N);
1944 /// SelectCC - Select a comparison of the specified values with the specified
1945 /// condition code, returning the CR# of the expression.
1946 SDValue PPCDAGToDAGISel::SelectCC(SDValue LHS, SDValue RHS,
1947 ISD::CondCode CC, SDLoc dl) {
1948 // Always select the LHS.
1951 if (LHS.getValueType() == MVT::i32) {
1953 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1954 if (isInt32Immediate(RHS, Imm)) {
1955 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
1956 if (isUInt<16>(Imm))
1957 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
1958 getI32Imm(Imm & 0xFFFF)), 0);
1959 // If this is a 16-bit signed immediate, fold it.
1960 if (isInt<16>((int)Imm))
1961 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
1962 getI32Imm(Imm & 0xFFFF)), 0);
1964 // For non-equality comparisons, the default code would materialize the
1965 // constant, then compare against it, like this:
1967 // ori r2, r2, 22136
1969 // Since we are just comparing for equality, we can emit this instead:
1970 // xoris r0,r3,0x1234
1971 // cmplwi cr0,r0,0x5678
1973 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS, dl, MVT::i32, LHS,
1974 getI32Imm(Imm >> 16)), 0);
1975 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, Xor,
1976 getI32Imm(Imm & 0xFFFF)), 0);
1979 } else if (ISD::isUnsignedIntSetCC(CC)) {
1980 if (isInt32Immediate(RHS, Imm) && isUInt<16>(Imm))
1981 return SDValue(CurDAG->getMachineNode(PPC::CMPLWI, dl, MVT::i32, LHS,
1982 getI32Imm(Imm & 0xFFFF)), 0);
1986 if (isIntS16Immediate(RHS, SImm))
1987 return SDValue(CurDAG->getMachineNode(PPC::CMPWI, dl, MVT::i32, LHS,
1988 getI32Imm((int)SImm & 0xFFFF)),
1992 } else if (LHS.getValueType() == MVT::i64) {
1994 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1995 if (isInt64Immediate(RHS.getNode(), Imm)) {
1996 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
1997 if (isUInt<16>(Imm))
1998 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
1999 getI32Imm(Imm & 0xFFFF)), 0);
2000 // If this is a 16-bit signed immediate, fold it.
2002 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
2003 getI32Imm(Imm & 0xFFFF)), 0);
2005 // For non-equality comparisons, the default code would materialize the
2006 // constant, then compare against it, like this:
2008 // ori r2, r2, 22136
2010 // Since we are just comparing for equality, we can emit this instead:
2011 // xoris r0,r3,0x1234
2012 // cmpldi cr0,r0,0x5678
2014 if (isUInt<32>(Imm)) {
2015 SDValue Xor(CurDAG->getMachineNode(PPC::XORIS8, dl, MVT::i64, LHS,
2016 getI64Imm(Imm >> 16)), 0);
2017 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, Xor,
2018 getI64Imm(Imm & 0xFFFF)), 0);
2022 } else if (ISD::isUnsignedIntSetCC(CC)) {
2023 if (isInt64Immediate(RHS.getNode(), Imm) && isUInt<16>(Imm))
2024 return SDValue(CurDAG->getMachineNode(PPC::CMPLDI, dl, MVT::i64, LHS,
2025 getI64Imm(Imm & 0xFFFF)), 0);
2029 if (isIntS16Immediate(RHS, SImm))
2030 return SDValue(CurDAG->getMachineNode(PPC::CMPDI, dl, MVT::i64, LHS,
2031 getI64Imm(SImm & 0xFFFF)),
2035 } else if (LHS.getValueType() == MVT::f32) {
2038 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
2039 Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD;
2041 return SDValue(CurDAG->getMachineNode(Opc, dl, MVT::i32, LHS, RHS), 0);
2044 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
2050 llvm_unreachable("Should be lowered by legalize!");
2051 default: llvm_unreachable("Unknown condition!");
2053 case ISD::SETEQ: return PPC::PRED_EQ;
2055 case ISD::SETNE: return PPC::PRED_NE;
2057 case ISD::SETLT: return PPC::PRED_LT;
2059 case ISD::SETLE: return PPC::PRED_LE;
2061 case ISD::SETGT: return PPC::PRED_GT;
2063 case ISD::SETGE: return PPC::PRED_GE;
2064 case ISD::SETO: return PPC::PRED_NU;
2065 case ISD::SETUO: return PPC::PRED_UN;
2066 // These two are invalid for floating point. Assume we have int.
2067 case ISD::SETULT: return PPC::PRED_LT;
2068 case ISD::SETUGT: return PPC::PRED_GT;
2072 /// getCRIdxForSetCC - Return the index of the condition register field
2073 /// associated with the SetCC condition, and whether or not the field is
2074 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
2075 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert) {
2078 default: llvm_unreachable("Unknown condition!");
2080 case ISD::SETLT: return 0; // Bit #0 = SETOLT
2082 case ISD::SETGT: return 1; // Bit #1 = SETOGT
2084 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
2085 case ISD::SETUO: return 3; // Bit #3 = SETUO
2087 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
2089 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
2091 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
2092 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
2097 llvm_unreachable("Invalid branch code: should be expanded by legalize");
2098 // These are invalid for floating point. Assume integer.
2099 case ISD::SETULT: return 0;
2100 case ISD::SETUGT: return 1;
2104 // getVCmpInst: return the vector compare instruction for the specified
2105 // vector type and condition code. Since this is for altivec specific code,
2106 // only support the altivec types (v16i8, v8i16, v4i32, and v4f32).
2107 static unsigned int getVCmpInst(MVT VecVT, ISD::CondCode CC,
2108 bool HasVSX, bool &Swap, bool &Negate) {
2112 if (VecVT.isFloatingPoint()) {
2113 /* Handle some cases by swapping input operands. */
2115 case ISD::SETLE: CC = ISD::SETGE; Swap = true; break;
2116 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
2117 case ISD::SETOLE: CC = ISD::SETOGE; Swap = true; break;
2118 case ISD::SETOLT: CC = ISD::SETOGT; Swap = true; break;
2119 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
2120 case ISD::SETUGT: CC = ISD::SETULT; Swap = true; break;
2123 /* Handle some cases by negating the result. */
2125 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
2126 case ISD::SETUNE: CC = ISD::SETOEQ; Negate = true; break;
2127 case ISD::SETULE: CC = ISD::SETOGT; Negate = true; break;
2128 case ISD::SETULT: CC = ISD::SETOGE; Negate = true; break;
2131 /* We have instructions implementing the remaining cases. */
2135 if (VecVT == MVT::v4f32)
2136 return HasVSX ? PPC::XVCMPEQSP : PPC::VCMPEQFP;
2137 else if (VecVT == MVT::v2f64)
2138 return PPC::XVCMPEQDP;
2142 if (VecVT == MVT::v4f32)
2143 return HasVSX ? PPC::XVCMPGTSP : PPC::VCMPGTFP;
2144 else if (VecVT == MVT::v2f64)
2145 return PPC::XVCMPGTDP;
2149 if (VecVT == MVT::v4f32)
2150 return HasVSX ? PPC::XVCMPGESP : PPC::VCMPGEFP;
2151 else if (VecVT == MVT::v2f64)
2152 return PPC::XVCMPGEDP;
2157 llvm_unreachable("Invalid floating-point vector compare condition");
2159 /* Handle some cases by swapping input operands. */
2161 case ISD::SETGE: CC = ISD::SETLE; Swap = true; break;
2162 case ISD::SETLT: CC = ISD::SETGT; Swap = true; break;
2163 case ISD::SETUGE: CC = ISD::SETULE; Swap = true; break;
2164 case ISD::SETULT: CC = ISD::SETUGT; Swap = true; break;
2167 /* Handle some cases by negating the result. */
2169 case ISD::SETNE: CC = ISD::SETEQ; Negate = true; break;
2170 case ISD::SETUNE: CC = ISD::SETUEQ; Negate = true; break;
2171 case ISD::SETLE: CC = ISD::SETGT; Negate = true; break;
2172 case ISD::SETULE: CC = ISD::SETUGT; Negate = true; break;
2175 /* We have instructions implementing the remaining cases. */
2179 if (VecVT == MVT::v16i8)
2180 return PPC::VCMPEQUB;
2181 else if (VecVT == MVT::v8i16)
2182 return PPC::VCMPEQUH;
2183 else if (VecVT == MVT::v4i32)
2184 return PPC::VCMPEQUW;
2187 if (VecVT == MVT::v16i8)
2188 return PPC::VCMPGTSB;
2189 else if (VecVT == MVT::v8i16)
2190 return PPC::VCMPGTSH;
2191 else if (VecVT == MVT::v4i32)
2192 return PPC::VCMPGTSW;
2195 if (VecVT == MVT::v16i8)
2196 return PPC::VCMPGTUB;
2197 else if (VecVT == MVT::v8i16)
2198 return PPC::VCMPGTUH;
2199 else if (VecVT == MVT::v4i32)
2200 return PPC::VCMPGTUW;
2205 llvm_unreachable("Invalid integer vector compare condition");
2209 SDNode *PPCDAGToDAGISel::SelectSETCC(SDNode *N) {
2212 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
2213 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
2214 bool isPPC64 = (PtrVT == MVT::i64);
2216 if (!PPCSubTarget->useCRBits() &&
2217 isInt32Immediate(N->getOperand(1), Imm)) {
2218 // We can codegen setcc op, imm very efficiently compared to a brcond.
2219 // Check for those cases here.
2222 SDValue Op = N->getOperand(0);
2226 Op = SDValue(CurDAG->getMachineNode(PPC::CNTLZW, dl, MVT::i32, Op), 0);
2227 SDValue Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
2228 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2233 SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2234 Op, getI32Imm(~0U)), 0);
2235 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
2239 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2240 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2244 SDValue(CurDAG->getMachineNode(PPC::NEG, dl, MVT::i32, Op), 0);
2245 T = SDValue(CurDAG->getMachineNode(PPC::ANDC, dl, MVT::i32, T, Op), 0);
2246 SDValue Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2247 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2250 } else if (Imm == ~0U) { // setcc op, -1
2251 SDValue Op = N->getOperand(0);
2256 Op = SDValue(CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2257 Op, getI32Imm(1)), 0);
2258 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
2259 SDValue(CurDAG->getMachineNode(PPC::LI, dl,
2265 Op = SDValue(CurDAG->getMachineNode(PPC::NOR, dl, MVT::i32, Op, Op), 0);
2266 SDNode *AD = CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2267 Op, getI32Imm(~0U));
2268 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDValue(AD, 0),
2269 Op, SDValue(AD, 1));
2272 SDValue AD = SDValue(CurDAG->getMachineNode(PPC::ADDI, dl, MVT::i32, Op,
2274 SDValue AN = SDValue(CurDAG->getMachineNode(PPC::AND, dl, MVT::i32, AD,
2276 SDValue Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2277 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2280 SDValue Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
2281 Op = SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops),
2283 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
2290 SDValue LHS = N->getOperand(0);
2291 SDValue RHS = N->getOperand(1);
2293 // Altivec Vector compare instructions do not set any CR register by default and
2294 // vector compare operations return the same type as the operands.
2295 if (LHS.getValueType().isVector()) {
2296 if (PPCSubTarget->hasQPX())
2299 EVT VecVT = LHS.getValueType();
2301 unsigned int VCmpInst = getVCmpInst(VecVT.getSimpleVT(), CC,
2302 PPCSubTarget->hasVSX(), Swap, Negate);
2304 std::swap(LHS, RHS);
2307 SDValue VCmp(CurDAG->getMachineNode(VCmpInst, dl, VecVT, LHS, RHS), 0);
2308 return CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR :
2313 return CurDAG->SelectNodeTo(N, VCmpInst, VecVT, LHS, RHS);
2316 if (PPCSubTarget->useCRBits())
2320 unsigned Idx = getCRIdxForSetCC(CC, Inv);
2321 SDValue CCReg = SelectCC(LHS, RHS, CC, dl);
2324 // Force the ccreg into CR7.
2325 SDValue CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
2327 SDValue InFlag(nullptr, 0); // Null incoming flag value.
2328 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), dl, CR7Reg, CCReg,
2329 InFlag).getValue(1);
2331 IntCR = SDValue(CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32, CR7Reg,
2334 SDValue Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
2335 getI32Imm(31), getI32Imm(31) };
2337 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2339 // Get the specified bit.
2341 SDValue(CurDAG->getMachineNode(PPC::RLWINM, dl, MVT::i32, Ops), 0);
2342 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
2346 // Select - Convert the specified operand from a target-independent to a
2347 // target-specific node if it hasn't already been changed.
2348 SDNode *PPCDAGToDAGISel::Select(SDNode *N) {
2350 if (N->isMachineOpcode()) {
2352 return nullptr; // Already selected.
2355 // In case any misguided DAG-level optimizations form an ADD with a
2356 // TargetConstant operand, crash here instead of miscompiling (by selecting
2357 // an r+r add instead of some kind of r+i add).
2358 if (N->getOpcode() == ISD::ADD &&
2359 N->getOperand(1).getOpcode() == ISD::TargetConstant)
2360 llvm_unreachable("Invalid ADD with TargetConstant operand");
2362 // Try matching complex bit permutations before doing anything else.
2363 if (SDNode *NN = SelectBitPermutation(N))
2366 switch (N->getOpcode()) {
2369 case ISD::Constant: {
2370 if (N->getValueType(0) == MVT::i64)
2371 return SelectInt64(CurDAG, N);
2376 SDNode *SN = SelectSETCC(N);
2381 case PPCISD::GlobalBaseReg:
2382 return getGlobalBaseReg();
2384 case ISD::FrameIndex:
2385 return getFrameIndex(N, N);
2387 case PPCISD::MFOCRF: {
2388 SDValue InFlag = N->getOperand(1);
2389 return CurDAG->getMachineNode(PPC::MFOCRF, dl, MVT::i32,
2390 N->getOperand(0), InFlag);
2393 case PPCISD::READ_TIME_BASE: {
2394 return CurDAG->getMachineNode(PPC::ReadTB, dl, MVT::i32, MVT::i32,
2395 MVT::Other, N->getOperand(0));
2398 case PPCISD::SRA_ADDZE: {
2399 SDValue N0 = N->getOperand(0);
2401 CurDAG->getTargetConstant(*cast<ConstantSDNode>(N->getOperand(1))->
2402 getConstantIntValue(), N->getValueType(0));
2403 if (N->getValueType(0) == MVT::i64) {
2405 CurDAG->getMachineNode(PPC::SRADI, dl, MVT::i64, MVT::Glue,
2407 return CurDAG->SelectNodeTo(N, PPC::ADDZE8, MVT::i64,
2408 SDValue(Op, 0), SDValue(Op, 1));
2410 assert(N->getValueType(0) == MVT::i32 &&
2411 "Expecting i64 or i32 in PPCISD::SRA_ADDZE");
2413 CurDAG->getMachineNode(PPC::SRAWI, dl, MVT::i32, MVT::Glue,
2415 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
2416 SDValue(Op, 0), SDValue(Op, 1));
2421 // Handle preincrement loads.
2422 LoadSDNode *LD = cast<LoadSDNode>(N);
2423 EVT LoadedVT = LD->getMemoryVT();
2425 // Normal loads are handled by code generated from the .td file.
2426 if (LD->getAddressingMode() != ISD::PRE_INC)
2429 SDValue Offset = LD->getOffset();
2430 if (Offset.getOpcode() == ISD::TargetConstant ||
2431 Offset.getOpcode() == ISD::TargetGlobalAddress) {
2434 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
2435 if (LD->getValueType(0) != MVT::i64) {
2436 // Handle PPC32 integer and normal FP loads.
2437 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
2438 switch (LoadedVT.getSimpleVT().SimpleTy) {
2439 default: llvm_unreachable("Invalid PPC load type!");
2440 case MVT::f64: Opcode = PPC::LFDU; break;
2441 case MVT::f32: Opcode = PPC::LFSU; break;
2442 case MVT::i32: Opcode = PPC::LWZU; break;
2443 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
2445 case MVT::i8: Opcode = PPC::LBZU; break;
2448 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
2449 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
2450 switch (LoadedVT.getSimpleVT().SimpleTy) {
2451 default: llvm_unreachable("Invalid PPC load type!");
2452 case MVT::i64: Opcode = PPC::LDU; break;
2453 case MVT::i32: Opcode = PPC::LWZU8; break;
2454 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
2456 case MVT::i8: Opcode = PPC::LBZU8; break;
2460 SDValue Chain = LD->getChain();
2461 SDValue Base = LD->getBasePtr();
2462 SDValue Ops[] = { Offset, Base, Chain };
2463 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
2464 PPCLowering->getPointerTy(),
2468 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
2469 if (LD->getValueType(0) != MVT::i64) {
2470 // Handle PPC32 integer and normal FP loads.
2471 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
2472 switch (LoadedVT.getSimpleVT().SimpleTy) {
2473 default: llvm_unreachable("Invalid PPC load type!");
2474 case MVT::v4f64: Opcode = PPC::QVLFDUX; break; // QPX
2475 case MVT::v4f32: Opcode = PPC::QVLFSUX; break; // QPX
2476 case MVT::f64: Opcode = PPC::LFDUX; break;
2477 case MVT::f32: Opcode = PPC::LFSUX; break;
2478 case MVT::i32: Opcode = PPC::LWZUX; break;
2479 case MVT::i16: Opcode = isSExt ? PPC::LHAUX : PPC::LHZUX; break;
2481 case MVT::i8: Opcode = PPC::LBZUX; break;
2484 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
2485 assert((!isSExt || LoadedVT == MVT::i16 || LoadedVT == MVT::i32) &&
2486 "Invalid sext update load");
2487 switch (LoadedVT.getSimpleVT().SimpleTy) {
2488 default: llvm_unreachable("Invalid PPC load type!");
2489 case MVT::i64: Opcode = PPC::LDUX; break;
2490 case MVT::i32: Opcode = isSExt ? PPC::LWAUX : PPC::LWZUX8; break;
2491 case MVT::i16: Opcode = isSExt ? PPC::LHAUX8 : PPC::LHZUX8; break;
2493 case MVT::i8: Opcode = PPC::LBZUX8; break;
2497 SDValue Chain = LD->getChain();
2498 SDValue Base = LD->getBasePtr();
2499 SDValue Ops[] = { Base, Offset, Chain };
2500 return CurDAG->getMachineNode(Opcode, dl, LD->getValueType(0),
2501 PPCLowering->getPointerTy(),
2507 unsigned Imm, Imm2, SH, MB, ME;
2510 // If this is an and of a value rotated between 0 and 31 bits and then and'd
2511 // with a mask, emit rlwinm
2512 if (isInt32Immediate(N->getOperand(1), Imm) &&
2513 isRotateAndMask(N->getOperand(0).getNode(), Imm, false, SH, MB, ME)) {
2514 SDValue Val = N->getOperand(0).getOperand(0);
2515 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
2516 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2518 // If this is just a masked value where the input is not handled above, and
2519 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
2520 if (isInt32Immediate(N->getOperand(1), Imm) &&
2521 isRunOfOnes(Imm, MB, ME) &&
2522 N->getOperand(0).getOpcode() != ISD::ROTL) {
2523 SDValue Val = N->getOperand(0);
2524 SDValue Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
2525 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2527 // If this is a 64-bit zero-extension mask, emit rldicl.
2528 if (isInt64Immediate(N->getOperand(1).getNode(), Imm64) &&
2530 SDValue Val = N->getOperand(0);
2531 MB = 64 - countTrailingOnes(Imm64);
2534 // If the operand is a logical right shift, we can fold it into this
2535 // instruction: rldicl(rldicl(x, 64-n, n), 0, mb) -> rldicl(x, 64-n, mb)
2536 // for n <= mb. The right shift is really a left rotate followed by a
2537 // mask, and this mask is a more-restrictive sub-mask of the mask implied
2539 if (Val.getOpcode() == ISD::SRL &&
2540 isInt32Immediate(Val.getOperand(1).getNode(), Imm) && Imm <= MB) {
2541 assert(Imm < 64 && "Illegal shift amount");
2542 Val = Val.getOperand(0);
2546 SDValue Ops[] = { Val, getI32Imm(SH), getI32Imm(MB) };
2547 return CurDAG->SelectNodeTo(N, PPC::RLDICL, MVT::i64, Ops);
2549 // AND X, 0 -> 0, not "rlwinm 32".
2550 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
2551 ReplaceUses(SDValue(N, 0), N->getOperand(1));
2554 // ISD::OR doesn't get all the bitfield insertion fun.
2555 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
2556 if (isInt32Immediate(N->getOperand(1), Imm) &&
2557 N->getOperand(0).getOpcode() == ISD::OR &&
2558 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
2561 if (isRunOfOnes(Imm, MB, ME)) {
2562 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2563 N->getOperand(0).getOperand(1),
2564 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
2565 return CurDAG->getMachineNode(PPC::RLWIMI, dl, MVT::i32, Ops);
2569 // Other cases are autogenerated.
2573 if (N->getValueType(0) == MVT::i32)
2574 if (SDNode *I = SelectBitfieldInsert(N))
2578 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
2579 isIntS16Immediate(N->getOperand(1), Imm)) {
2580 APInt LHSKnownZero, LHSKnownOne;
2581 CurDAG->computeKnownBits(N->getOperand(0), LHSKnownZero, LHSKnownOne);
2583 // If this is equivalent to an add, then we can fold it with the
2584 // FrameIndex calculation.
2585 if ((LHSKnownZero.getZExtValue()|~(uint64_t)Imm) == ~0ULL)
2586 return getFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
2589 // Other cases are autogenerated.
2594 if (N->getOperand(0)->getOpcode() == ISD::FrameIndex &&
2595 isIntS16Immediate(N->getOperand(1), Imm))
2596 return getFrameIndex(N, N->getOperand(0).getNode(), (int)Imm);
2601 unsigned Imm, SH, MB, ME;
2602 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
2603 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
2604 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2605 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
2606 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2609 // Other cases are autogenerated.
2613 unsigned Imm, SH, MB, ME;
2614 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, Imm) &&
2615 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
2616 SDValue Ops[] = { N->getOperand(0).getOperand(0),
2617 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
2618 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops);
2621 // Other cases are autogenerated.
2624 // FIXME: Remove this once the ANDI glue bug is fixed:
2625 case PPCISD::ANDIo_1_EQ_BIT:
2626 case PPCISD::ANDIo_1_GT_BIT: {
2630 EVT InVT = N->getOperand(0).getValueType();
2631 assert((InVT == MVT::i64 || InVT == MVT::i32) &&
2632 "Invalid input type for ANDIo_1_EQ_BIT");
2634 unsigned Opcode = (InVT == MVT::i64) ? PPC::ANDIo8 : PPC::ANDIo;
2635 SDValue AndI(CurDAG->getMachineNode(Opcode, dl, InVT, MVT::Glue,
2637 CurDAG->getTargetConstant(1, InVT)), 0);
2638 SDValue CR0Reg = CurDAG->getRegister(PPC::CR0, MVT::i32);
2640 CurDAG->getTargetConstant(N->getOpcode() == PPCISD::ANDIo_1_EQ_BIT ?
2641 PPC::sub_eq : PPC::sub_gt, MVT::i32);
2643 return CurDAG->SelectNodeTo(N, TargetOpcode::EXTRACT_SUBREG, MVT::i1,
2645 SDValue(AndI.getNode(), 1) /* glue */);
2647 case ISD::SELECT_CC: {
2648 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
2649 EVT PtrVT = CurDAG->getTargetLoweringInfo().getPointerTy();
2650 bool isPPC64 = (PtrVT == MVT::i64);
2652 // If this is a select of i1 operands, we'll pattern match it.
2653 if (PPCSubTarget->useCRBits() &&
2654 N->getOperand(0).getValueType() == MVT::i1)
2657 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
2659 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
2660 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
2661 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
2662 if (N1C->isNullValue() && N3C->isNullValue() &&
2663 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE &&
2664 // FIXME: Implement this optzn for PPC64.
2665 N->getValueType(0) == MVT::i32) {
2667 CurDAG->getMachineNode(PPC::ADDIC, dl, MVT::i32, MVT::Glue,
2668 N->getOperand(0), getI32Imm(~0U));
2669 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
2670 SDValue(Tmp, 0), N->getOperand(0),
2674 SDValue CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC, dl);
2676 if (N->getValueType(0) == MVT::i1) {
2677 // An i1 select is: (c & t) | (!c & f).
2679 unsigned Idx = getCRIdxForSetCC(CC, Inv);
2683 default: llvm_unreachable("Invalid CC index");
2684 case 0: SRI = PPC::sub_lt; break;
2685 case 1: SRI = PPC::sub_gt; break;
2686 case 2: SRI = PPC::sub_eq; break;
2687 case 3: SRI = PPC::sub_un; break;
2690 SDValue CCBit = CurDAG->getTargetExtractSubreg(SRI, dl, MVT::i1, CCReg);
2692 SDValue NotCCBit(CurDAG->getMachineNode(PPC::CRNOR, dl, MVT::i1,
2694 SDValue C = Inv ? NotCCBit : CCBit,
2695 NotC = Inv ? CCBit : NotCCBit;
2697 SDValue CAndT(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
2698 C, N->getOperand(2)), 0);
2699 SDValue NotCAndF(CurDAG->getMachineNode(PPC::CRAND, dl, MVT::i1,
2700 NotC, N->getOperand(3)), 0);
2702 return CurDAG->SelectNodeTo(N, PPC::CROR, MVT::i1, CAndT, NotCAndF);
2705 unsigned BROpc = getPredicateForSetCC(CC);
2707 unsigned SelectCCOp;
2708 if (N->getValueType(0) == MVT::i32)
2709 SelectCCOp = PPC::SELECT_CC_I4;
2710 else if (N->getValueType(0) == MVT::i64)
2711 SelectCCOp = PPC::SELECT_CC_I8;
2712 else if (N->getValueType(0) == MVT::f32)
2713 SelectCCOp = PPC::SELECT_CC_F4;
2714 else if (N->getValueType(0) == MVT::f64)
2715 if (PPCSubTarget->hasVSX())
2716 SelectCCOp = PPC::SELECT_CC_VSFRC;
2718 SelectCCOp = PPC::SELECT_CC_F8;
2719 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f64)
2720 SelectCCOp = PPC::SELECT_CC_QFRC;
2721 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f32)
2722 SelectCCOp = PPC::SELECT_CC_QSRC;
2723 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4i1)
2724 SelectCCOp = PPC::SELECT_CC_QBRC;
2725 else if (N->getValueType(0) == MVT::v2f64 ||
2726 N->getValueType(0) == MVT::v2i64)
2727 SelectCCOp = PPC::SELECT_CC_VSRC;
2729 SelectCCOp = PPC::SELECT_CC_VRRC;
2731 SDValue Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
2733 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops);
2736 if (PPCSubTarget->hasVSX()) {
2737 SDValue Ops[] = { N->getOperand(2), N->getOperand(1), N->getOperand(0) };
2738 return CurDAG->SelectNodeTo(N, PPC::XXSEL, N->getValueType(0), Ops);
2742 case ISD::VECTOR_SHUFFLE:
2743 if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 ||
2744 N->getValueType(0) == MVT::v2i64)) {
2745 ShuffleVectorSDNode *SVN = cast<ShuffleVectorSDNode>(N);
2747 SDValue Op1 = N->getOperand(SVN->getMaskElt(0) < 2 ? 0 : 1),
2748 Op2 = N->getOperand(SVN->getMaskElt(1) < 2 ? 0 : 1);
2751 for (int i = 0; i < 2; ++i)
2752 if (SVN->getMaskElt(i) <= 0 || SVN->getMaskElt(i) == 2)
2757 // For little endian, we must swap the input operands and adjust
2758 // the mask elements (reverse and invert them).
2759 if (PPCSubTarget->isLittleEndian()) {
2760 std::swap(Op1, Op2);
2761 unsigned tmp = DM[0];
2766 SDValue DMV = CurDAG->getTargetConstant(DM[1] | (DM[0] << 1), MVT::i32);
2768 if (Op1 == Op2 && DM[0] == 0 && DM[1] == 0 &&
2769 Op1.getOpcode() == ISD::SCALAR_TO_VECTOR &&
2770 isa<LoadSDNode>(Op1.getOperand(0))) {
2771 LoadSDNode *LD = cast<LoadSDNode>(Op1.getOperand(0));
2772 SDValue Base, Offset;
2774 if (LD->isUnindexed() &&
2775 SelectAddrIdxOnly(LD->getBasePtr(), Base, Offset)) {
2776 SDValue Chain = LD->getChain();
2777 SDValue Ops[] = { Base, Offset, Chain };
2778 return CurDAG->SelectNodeTo(N, PPC::LXVDSX,
2779 N->getValueType(0), Ops);
2783 SDValue Ops[] = { Op1, Op2, DMV };
2784 return CurDAG->SelectNodeTo(N, PPC::XXPERMDI, N->getValueType(0), Ops);
2790 bool IsPPC64 = PPCSubTarget->isPPC64();
2791 SDValue Ops[] = { N->getOperand(1), N->getOperand(0) };
2792 return CurDAG->SelectNodeTo(N, N->getOpcode() == PPCISD::BDNZ ?
2793 (IsPPC64 ? PPC::BDNZ8 : PPC::BDNZ) :
2794 (IsPPC64 ? PPC::BDZ8 : PPC::BDZ),
2797 case PPCISD::COND_BRANCH: {
2798 // Op #0 is the Chain.
2799 // Op #1 is the PPC::PRED_* number.
2801 // Op #3 is the Dest MBB
2802 // Op #4 is the Flag.
2803 // Prevent PPC::PRED_* from being selected into LI.
2805 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getZExtValue());
2806 SDValue Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
2807 N->getOperand(0), N->getOperand(4) };
2808 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
2811 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
2812 unsigned PCC = getPredicateForSetCC(CC);
2814 if (N->getOperand(2).getValueType() == MVT::i1) {
2818 default: llvm_unreachable("Unexpected Boolean-operand predicate");
2819 case PPC::PRED_LT: Opc = PPC::CRANDC; Swap = true; break;
2820 case PPC::PRED_LE: Opc = PPC::CRORC; Swap = true; break;
2821 case PPC::PRED_EQ: Opc = PPC::CREQV; Swap = false; break;
2822 case PPC::PRED_GE: Opc = PPC::CRORC; Swap = false; break;
2823 case PPC::PRED_GT: Opc = PPC::CRANDC; Swap = false; break;
2824 case PPC::PRED_NE: Opc = PPC::CRXOR; Swap = false; break;
2827 SDValue BitComp(CurDAG->getMachineNode(Opc, dl, MVT::i1,
2828 N->getOperand(Swap ? 3 : 2),
2829 N->getOperand(Swap ? 2 : 3)), 0);
2830 return CurDAG->SelectNodeTo(N, PPC::BC, MVT::Other,
2831 BitComp, N->getOperand(4), N->getOperand(0));
2834 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl);
2835 SDValue Ops[] = { getI32Imm(PCC), CondCode,
2836 N->getOperand(4), N->getOperand(0) };
2837 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops);
2840 // FIXME: Should custom lower this.
2841 SDValue Chain = N->getOperand(0);
2842 SDValue Target = N->getOperand(1);
2843 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
2844 unsigned Reg = Target.getValueType() == MVT::i32 ? PPC::BCTR : PPC::BCTR8;
2845 Chain = SDValue(CurDAG->getMachineNode(Opc, dl, MVT::Glue, Target,
2847 return CurDAG->SelectNodeTo(N, Reg, MVT::Other, Chain);
2849 case PPCISD::TOC_ENTRY: {
2850 assert ((PPCSubTarget->isPPC64() || PPCSubTarget->isSVR4ABI()) &&
2851 "Only supported for 64-bit ABI and 32-bit SVR4");
2852 if (PPCSubTarget->isSVR4ABI() && !PPCSubTarget->isPPC64()) {
2853 SDValue GA = N->getOperand(0);
2854 return CurDAG->getMachineNode(PPC::LWZtoc, dl, MVT::i32, GA,
2858 // For medium and large code model, we generate two instructions as
2859 // described below. Otherwise we allow SelectCodeCommon to handle this,
2860 // selecting one of LDtoc, LDtocJTI, LDtocCPT, and LDtocBA.
2861 CodeModel::Model CModel = TM.getCodeModel();
2862 if (CModel != CodeModel::Medium && CModel != CodeModel::Large)
2865 // The first source operand is a TargetGlobalAddress or a TargetJumpTable.
2866 // If it is an externally defined symbol, a symbol with common linkage,
2867 // a non-local function address, or a jump table address, or if we are
2868 // generating code for large code model, we generate:
2869 // LDtocL(<ga:@sym>, ADDIStocHA(%X2, <ga:@sym>))
2870 // Otherwise we generate:
2871 // ADDItocL(ADDIStocHA(%X2, <ga:@sym>), <ga:@sym>)
2872 SDValue GA = N->getOperand(0);
2873 SDValue TOCbase = N->getOperand(1);
2874 SDNode *Tmp = CurDAG->getMachineNode(PPC::ADDIStocHA, dl, MVT::i64,
2877 if (isa<JumpTableSDNode>(GA) || isa<BlockAddressSDNode>(GA) ||
2878 CModel == CodeModel::Large)
2879 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
2882 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(GA)) {
2883 const GlobalValue *GValue = G->getGlobal();
2884 if ((GValue->getType()->getElementType()->isFunctionTy() &&
2885 (GValue->isDeclaration() || GValue->isWeakForLinker())) ||
2886 GValue->isDeclaration() || GValue->hasCommonLinkage() ||
2887 GValue->hasAvailableExternallyLinkage())
2888 return CurDAG->getMachineNode(PPC::LDtocL, dl, MVT::i64, GA,
2892 return CurDAG->getMachineNode(PPC::ADDItocL, dl, MVT::i64,
2893 SDValue(Tmp, 0), GA);
2895 case PPCISD::PPC32_PICGOT: {
2896 // Generate a PIC-safe GOT reference.
2897 assert(!PPCSubTarget->isPPC64() && PPCSubTarget->isSVR4ABI() &&
2898 "PPCISD::PPC32_PICGOT is only supported for 32-bit SVR4");
2899 return CurDAG->SelectNodeTo(N, PPC::PPC32PICGOT, PPCLowering->getPointerTy(), MVT::i32);
2901 case PPCISD::VADD_SPLAT: {
2902 // This expands into one of three sequences, depending on whether
2903 // the first operand is odd or even, positive or negative.
2904 assert(isa<ConstantSDNode>(N->getOperand(0)) &&
2905 isa<ConstantSDNode>(N->getOperand(1)) &&
2906 "Invalid operand on VADD_SPLAT!");
2908 int Elt = N->getConstantOperandVal(0);
2909 int EltSize = N->getConstantOperandVal(1);
2910 unsigned Opc1, Opc2, Opc3;
2914 Opc1 = PPC::VSPLTISB;
2915 Opc2 = PPC::VADDUBM;
2916 Opc3 = PPC::VSUBUBM;
2918 } else if (EltSize == 2) {
2919 Opc1 = PPC::VSPLTISH;
2920 Opc2 = PPC::VADDUHM;
2921 Opc3 = PPC::VSUBUHM;
2924 assert(EltSize == 4 && "Invalid element size on VADD_SPLAT!");
2925 Opc1 = PPC::VSPLTISW;
2926 Opc2 = PPC::VADDUWM;
2927 Opc3 = PPC::VSUBUWM;
2931 if ((Elt & 1) == 0) {
2932 // Elt is even, in the range [-32,-18] + [16,30].
2934 // Convert: VADD_SPLAT elt, size
2935 // Into: tmp = VSPLTIS[BHW] elt
2936 // VADDU[BHW]M tmp, tmp
2937 // Where: [BHW] = B for size = 1, H for size = 2, W for size = 4
2938 SDValue EltVal = getI32Imm(Elt >> 1);
2939 SDNode *Tmp = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2940 SDValue TmpVal = SDValue(Tmp, 0);
2941 return CurDAG->getMachineNode(Opc2, dl, VT, TmpVal, TmpVal);
2943 } else if (Elt > 0) {
2944 // Elt is odd and positive, in the range [17,31].
2946 // Convert: VADD_SPLAT elt, size
2947 // Into: tmp1 = VSPLTIS[BHW] elt-16
2948 // tmp2 = VSPLTIS[BHW] -16
2949 // VSUBU[BHW]M tmp1, tmp2
2950 SDValue EltVal = getI32Imm(Elt - 16);
2951 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2952 EltVal = getI32Imm(-16);
2953 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2954 return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
2958 // Elt is odd and negative, in the range [-31,-17].
2960 // Convert: VADD_SPLAT elt, size
2961 // Into: tmp1 = VSPLTIS[BHW] elt+16
2962 // tmp2 = VSPLTIS[BHW] -16
2963 // VADDU[BHW]M tmp1, tmp2
2964 SDValue EltVal = getI32Imm(Elt + 16);
2965 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2966 EltVal = getI32Imm(-16);
2967 SDNode *Tmp2 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal);
2968 return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
2974 return SelectCode(N);
2977 // If the target supports the cmpb instruction, do the idiom recognition here.
2978 // We don't do this as a DAG combine because we don't want to do it as nodes
2979 // are being combined (because we might miss part of the eventual idiom). We
2980 // don't want to do it during instruction selection because we want to reuse
2981 // the logic for lowering the masking operations already part of the
2982 // instruction selector.
2983 SDValue PPCDAGToDAGISel::combineToCMPB(SDNode *N) {
2986 assert(N->getOpcode() == ISD::OR &&
2987 "Only OR nodes are supported for CMPB");
2990 if (!PPCSubTarget->hasCMPB())
2993 if (N->getValueType(0) != MVT::i32 &&
2994 N->getValueType(0) != MVT::i64)
2997 EVT VT = N->getValueType(0);
3000 bool BytesFound[8] = { 0, 0, 0, 0, 0, 0, 0, 0 };
3001 uint64_t Mask = 0, Alt = 0;
3003 auto IsByteSelectCC = [this](SDValue O, unsigned &b,
3004 uint64_t &Mask, uint64_t &Alt,
3005 SDValue &LHS, SDValue &RHS) {
3006 if (O.getOpcode() != ISD::SELECT_CC)
3008 ISD::CondCode CC = cast<CondCodeSDNode>(O.getOperand(4))->get();
3010 if (!isa<ConstantSDNode>(O.getOperand(2)) ||
3011 !isa<ConstantSDNode>(O.getOperand(3)))
3014 uint64_t PM = O.getConstantOperandVal(2);
3015 uint64_t PAlt = O.getConstantOperandVal(3);
3016 for (b = 0; b < 8; ++b) {
3017 uint64_t Mask = UINT64_C(0xFF) << (8*b);
3018 if (PM && (PM & Mask) == PM && (PAlt & Mask) == PAlt)
3027 if (!isa<ConstantSDNode>(O.getOperand(1)) ||
3028 O.getConstantOperandVal(1) != 0) {
3029 SDValue Op0 = O.getOperand(0), Op1 = O.getOperand(1);
3030 if (Op0.getOpcode() == ISD::TRUNCATE)
3031 Op0 = Op0.getOperand(0);
3032 if (Op1.getOpcode() == ISD::TRUNCATE)
3033 Op1 = Op1.getOperand(0);
3035 if (Op0.getOpcode() == ISD::SRL && Op1.getOpcode() == ISD::SRL &&
3036 Op0.getOperand(1) == Op1.getOperand(1) && CC == ISD::SETEQ &&
3037 isa<ConstantSDNode>(Op0.getOperand(1))) {
3039 unsigned Bits = Op0.getValueType().getSizeInBits();
3042 if (Op0.getConstantOperandVal(1) != Bits-8)
3045 LHS = Op0.getOperand(0);
3046 RHS = Op1.getOperand(0);
3050 // When we have small integers (i16 to be specific), the form present
3051 // post-legalization uses SETULT in the SELECT_CC for the
3052 // higher-order byte, depending on the fact that the
3053 // even-higher-order bytes are known to all be zero, for example:
3054 // select_cc (xor $lhs, $rhs), 256, 65280, 0, setult
3055 // (so when the second byte is the same, because all higher-order
3056 // bits from bytes 3 and 4 are known to be zero, the result of the
3057 // xor can be at most 255)
3058 if (Op0.getOpcode() == ISD::XOR && CC == ISD::SETULT &&
3059 isa<ConstantSDNode>(O.getOperand(1))) {
3061 uint64_t ULim = O.getConstantOperandVal(1);
3062 if (ULim != (UINT64_C(1) << b*8))
3065 // Now we need to make sure that the upper bytes are known to be
3067 unsigned Bits = Op0.getValueType().getSizeInBits();
3068 if (!CurDAG->MaskedValueIsZero(Op0,
3069 APInt::getHighBitsSet(Bits, Bits - (b+1)*8)))
3072 LHS = Op0.getOperand(0);
3073 RHS = Op0.getOperand(1);
3080 if (CC != ISD::SETEQ)
3083 SDValue Op = O.getOperand(0);
3084 if (Op.getOpcode() == ISD::AND) {
3085 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3087 if (Op.getConstantOperandVal(1) != (UINT64_C(0xFF) << (8*b)))
3090 SDValue XOR = Op.getOperand(0);
3091 if (XOR.getOpcode() == ISD::TRUNCATE)
3092 XOR = XOR.getOperand(0);
3093 if (XOR.getOpcode() != ISD::XOR)
3096 LHS = XOR.getOperand(0);
3097 RHS = XOR.getOperand(1);
3099 } else if (Op.getOpcode() == ISD::SRL) {
3100 if (!isa<ConstantSDNode>(Op.getOperand(1)))
3102 unsigned Bits = Op.getValueType().getSizeInBits();
3105 if (Op.getConstantOperandVal(1) != Bits-8)
3108 SDValue XOR = Op.getOperand(0);
3109 if (XOR.getOpcode() == ISD::TRUNCATE)
3110 XOR = XOR.getOperand(0);
3111 if (XOR.getOpcode() != ISD::XOR)
3114 LHS = XOR.getOperand(0);
3115 RHS = XOR.getOperand(1);
3122 SmallVector<SDValue, 8> Queue(1, SDValue(N, 0));
3123 while (!Queue.empty()) {
3124 SDValue V = Queue.pop_back_val();
3126 for (const SDValue &O : V.getNode()->ops()) {
3128 uint64_t M = 0, A = 0;
3130 if (O.getOpcode() == ISD::OR) {
3132 } else if (IsByteSelectCC(O, b, M, A, OLHS, ORHS)) {
3136 BytesFound[b] = true;
3139 } else if ((LHS == ORHS && RHS == OLHS) ||
3140 (RHS == ORHS && LHS == OLHS)) {
3141 BytesFound[b] = true;
3153 unsigned LastB = 0, BCnt = 0;
3154 for (unsigned i = 0; i < 8; ++i)
3155 if (BytesFound[LastB]) {
3160 if (!LastB || BCnt < 2)
3163 // Because we'll be zero-extending the output anyway if don't have a specific
3164 // value for each input byte (via the Mask), we can 'anyext' the inputs.
3165 if (LHS.getValueType() != VT) {
3166 LHS = CurDAG->getAnyExtOrTrunc(LHS, dl, VT);
3167 RHS = CurDAG->getAnyExtOrTrunc(RHS, dl, VT);
3170 Res = CurDAG->getNode(PPCISD::CMPB, dl, VT, LHS, RHS);
3172 bool NonTrivialMask = ((int64_t) Mask) != INT64_C(-1);
3173 if (NonTrivialMask && !Alt) {
3174 // Res = Mask & CMPB
3175 Res = CurDAG->getNode(ISD::AND, dl, VT, Res, CurDAG->getConstant(Mask, VT));
3177 // Res = (CMPB & Mask) | (~CMPB & Alt)
3178 // Which, as suggested here:
3179 // https://graphics.stanford.edu/~seander/bithacks.html#MaskedMerge
3180 // can be written as:
3181 // Res = Alt ^ ((Alt ^ Mask) & CMPB)
3182 // useful because the (Alt ^ Mask) can be pre-computed.
3183 Res = CurDAG->getNode(ISD::AND, dl, VT, Res,
3184 CurDAG->getConstant(Mask ^ Alt, VT));
3185 Res = CurDAG->getNode(ISD::XOR, dl, VT, Res, CurDAG->getConstant(Alt, VT));
3191 // When CR bit registers are enabled, an extension of an i1 variable to a i32
3192 // or i64 value is lowered in terms of a SELECT_I[48] operation, and thus
3193 // involves constant materialization of a 0 or a 1 or both. If the result of
3194 // the extension is then operated upon by some operator that can be constant
3195 // folded with a constant 0 or 1, and that constant can be materialized using
3196 // only one instruction (like a zero or one), then we should fold in those
3197 // operations with the select.
3198 void PPCDAGToDAGISel::foldBoolExts(SDValue &Res, SDNode *&N) {
3199 if (!PPCSubTarget->useCRBits())
3202 if (N->getOpcode() != ISD::ZERO_EXTEND &&
3203 N->getOpcode() != ISD::SIGN_EXTEND &&
3204 N->getOpcode() != ISD::ANY_EXTEND)
3207 if (N->getOperand(0).getValueType() != MVT::i1)
3210 if (!N->hasOneUse())
3214 EVT VT = N->getValueType(0);
3215 SDValue Cond = N->getOperand(0);
3217 CurDAG->getConstant(N->getOpcode() == ISD::SIGN_EXTEND ? -1 : 1, VT);
3218 SDValue ConstFalse = CurDAG->getConstant(0, VT);
3221 SDNode *User = *N->use_begin();
3222 if (User->getNumOperands() != 2)
3225 auto TryFold = [this, N, User](SDValue Val) {
3226 SDValue UserO0 = User->getOperand(0), UserO1 = User->getOperand(1);
3227 SDValue O0 = UserO0.getNode() == N ? Val : UserO0;
3228 SDValue O1 = UserO1.getNode() == N ? Val : UserO1;
3230 return CurDAG->FoldConstantArithmetic(User->getOpcode(),
3231 User->getValueType(0),
3232 O0.getNode(), O1.getNode());
3235 SDValue TrueRes = TryFold(ConstTrue);
3238 SDValue FalseRes = TryFold(ConstFalse);
3242 // For us to materialize these using one instruction, we must be able to
3243 // represent them as signed 16-bit integers.
3244 uint64_t True = cast<ConstantSDNode>(TrueRes)->getZExtValue(),
3245 False = cast<ConstantSDNode>(FalseRes)->getZExtValue();
3246 if (!isInt<16>(True) || !isInt<16>(False))
3249 // We can replace User with a new SELECT node, and try again to see if we
3250 // can fold the select with its user.
3251 Res = CurDAG->getSelect(dl, User->getValueType(0), Cond, TrueRes, FalseRes);
3253 ConstTrue = TrueRes;
3254 ConstFalse = FalseRes;
3255 } while (N->hasOneUse());
3258 void PPCDAGToDAGISel::PreprocessISelDAG() {
3259 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
3262 bool MadeChange = false;
3263 while (Position != CurDAG->allnodes_begin()) {
3264 SDNode *N = --Position;
3269 switch (N->getOpcode()) {
3272 Res = combineToCMPB(N);
3277 foldBoolExts(Res, N);
3280 DEBUG(dbgs() << "PPC DAG preprocessing replacing:\nOld: ");
3281 DEBUG(N->dump(CurDAG));
3282 DEBUG(dbgs() << "\nNew: ");
3283 DEBUG(Res.getNode()->dump(CurDAG));
3284 DEBUG(dbgs() << "\n");
3286 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Res);
3292 CurDAG->RemoveDeadNodes();
3295 /// PostprocessISelDAG - Perform some late peephole optimizations
3296 /// on the DAG representation.
3297 void PPCDAGToDAGISel::PostprocessISelDAG() {
3299 // Skip peepholes at -O0.
3300 if (TM.getOptLevel() == CodeGenOpt::None)
3305 PeepholePPC64ZExt();
3308 // Check if all users of this node will become isel where the second operand
3309 // is the constant zero. If this is so, and if we can negate the condition,
3310 // then we can flip the true and false operands. This will allow the zero to
3311 // be folded with the isel so that we don't need to materialize a register
3313 bool PPCDAGToDAGISel::AllUsersSelectZero(SDNode *N) {
3314 // If we're not using isel, then this does not matter.
3315 if (!PPCSubTarget->hasISEL())
3318 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3321 if (!User->isMachineOpcode())
3323 if (User->getMachineOpcode() != PPC::SELECT_I4 &&
3324 User->getMachineOpcode() != PPC::SELECT_I8)
3327 SDNode *Op2 = User->getOperand(2).getNode();
3328 if (!Op2->isMachineOpcode())
3331 if (Op2->getMachineOpcode() != PPC::LI &&
3332 Op2->getMachineOpcode() != PPC::LI8)
3335 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op2->getOperand(0));
3339 if (!C->isNullValue())
3346 void PPCDAGToDAGISel::SwapAllSelectUsers(SDNode *N) {
3347 SmallVector<SDNode *, 4> ToReplace;
3348 for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
3351 assert((User->getMachineOpcode() == PPC::SELECT_I4 ||
3352 User->getMachineOpcode() == PPC::SELECT_I8) &&
3353 "Must have all select users");
3354 ToReplace.push_back(User);
3357 for (SmallVector<SDNode *, 4>::iterator UI = ToReplace.begin(),
3358 UE = ToReplace.end(); UI != UE; ++UI) {
3361 CurDAG->getMachineNode(User->getMachineOpcode(), SDLoc(User),
3362 User->getValueType(0), User->getOperand(0),
3363 User->getOperand(2),
3364 User->getOperand(1));
3366 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
3367 DEBUG(User->dump(CurDAG));
3368 DEBUG(dbgs() << "\nNew: ");
3369 DEBUG(ResNode->dump(CurDAG));
3370 DEBUG(dbgs() << "\n");
3372 ReplaceUses(User, ResNode);
3376 void PPCDAGToDAGISel::PeepholeCROps() {
3380 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
3381 E = CurDAG->allnodes_end(); I != E; ++I) {
3382 MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(I);
3383 if (!MachineNode || MachineNode->use_empty())
3385 SDNode *ResNode = MachineNode;
3387 bool Op1Set = false, Op1Unset = false,
3389 Op2Set = false, Op2Unset = false,
3392 unsigned Opcode = MachineNode->getMachineOpcode();
3403 SDValue Op = MachineNode->getOperand(1);
3404 if (Op.isMachineOpcode()) {
3405 if (Op.getMachineOpcode() == PPC::CRSET)
3407 else if (Op.getMachineOpcode() == PPC::CRUNSET)
3409 else if (Op.getMachineOpcode() == PPC::CRNOR &&
3410 Op.getOperand(0) == Op.getOperand(1))
3416 case PPC::SELECT_I4:
3417 case PPC::SELECT_I8:
3418 case PPC::SELECT_F4:
3419 case PPC::SELECT_F8:
3420 case PPC::SELECT_QFRC:
3421 case PPC::SELECT_QSRC:
3422 case PPC::SELECT_QBRC:
3423 case PPC::SELECT_VRRC:
3424 case PPC::SELECT_VSFRC:
3425 case PPC::SELECT_VSRC: {
3426 SDValue Op = MachineNode->getOperand(0);
3427 if (Op.isMachineOpcode()) {
3428 if (Op.getMachineOpcode() == PPC::CRSET)
3430 else if (Op.getMachineOpcode() == PPC::CRUNSET)
3432 else if (Op.getMachineOpcode() == PPC::CRNOR &&
3433 Op.getOperand(0) == Op.getOperand(1))
3440 bool SelectSwap = false;
3444 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3446 ResNode = MachineNode->getOperand(0).getNode();
3449 ResNode = MachineNode->getOperand(1).getNode();
3452 ResNode = MachineNode->getOperand(0).getNode();
3453 else if (Op1Unset || Op2Unset)
3454 // x & 0 = 0 & y = 0
3455 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3458 // ~x & y = andc(y, x)
3459 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3460 MVT::i1, MachineNode->getOperand(1),
3461 MachineNode->getOperand(0).
3464 // x & ~y = andc(x, y)
3465 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3466 MVT::i1, MachineNode->getOperand(0),
3467 MachineNode->getOperand(1).
3469 else if (AllUsersSelectZero(MachineNode))
3470 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
3471 MVT::i1, MachineNode->getOperand(0),
3472 MachineNode->getOperand(1)),
3476 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3477 // nand(x, x) -> nor(x, x)
3478 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3479 MVT::i1, MachineNode->getOperand(0),
3480 MachineNode->getOperand(0));
3482 // nand(1, y) -> nor(y, y)
3483 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3484 MVT::i1, MachineNode->getOperand(1),
3485 MachineNode->getOperand(1));
3487 // nand(x, 1) -> nor(x, x)
3488 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3489 MVT::i1, MachineNode->getOperand(0),
3490 MachineNode->getOperand(0));
3491 else if (Op1Unset || Op2Unset)
3492 // nand(x, 0) = nand(0, y) = 1
3493 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3496 // nand(~x, y) = ~(~x & y) = x | ~y = orc(x, y)
3497 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3498 MVT::i1, MachineNode->getOperand(0).
3500 MachineNode->getOperand(1));
3502 // nand(x, ~y) = ~x | y = orc(y, x)
3503 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3504 MVT::i1, MachineNode->getOperand(1).
3506 MachineNode->getOperand(0));
3507 else if (AllUsersSelectZero(MachineNode))
3508 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
3509 MVT::i1, MachineNode->getOperand(0),
3510 MachineNode->getOperand(1)),
3514 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3516 ResNode = MachineNode->getOperand(0).getNode();
3517 else if (Op1Set || Op2Set)
3518 // x | 1 = 1 | y = 1
3519 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3523 ResNode = MachineNode->getOperand(1).getNode();
3526 ResNode = MachineNode->getOperand(0).getNode();
3528 // ~x | y = orc(y, x)
3529 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3530 MVT::i1, MachineNode->getOperand(1),
3531 MachineNode->getOperand(0).
3534 // x | ~y = orc(x, y)
3535 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3536 MVT::i1, MachineNode->getOperand(0),
3537 MachineNode->getOperand(1).
3539 else if (AllUsersSelectZero(MachineNode))
3540 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3541 MVT::i1, MachineNode->getOperand(0),
3542 MachineNode->getOperand(1)),
3546 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3548 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3551 // xor(1, y) -> nor(y, y)
3552 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3553 MVT::i1, MachineNode->getOperand(1),
3554 MachineNode->getOperand(1));
3556 // xor(x, 1) -> nor(x, x)
3557 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3558 MVT::i1, MachineNode->getOperand(0),
3559 MachineNode->getOperand(0));
3562 ResNode = MachineNode->getOperand(1).getNode();
3565 ResNode = MachineNode->getOperand(0).getNode();
3567 // xor(~x, y) = eqv(x, y)
3568 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
3569 MVT::i1, MachineNode->getOperand(0).
3571 MachineNode->getOperand(1));
3573 // xor(x, ~y) = eqv(x, y)
3574 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
3575 MVT::i1, MachineNode->getOperand(0),
3576 MachineNode->getOperand(1).
3578 else if (AllUsersSelectZero(MachineNode))
3579 ResNode = CurDAG->getMachineNode(PPC::CREQV, SDLoc(MachineNode),
3580 MVT::i1, MachineNode->getOperand(0),
3581 MachineNode->getOperand(1)),
3585 if (Op1Set || Op2Set)
3587 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3590 // nor(0, y) = ~y -> nor(y, y)
3591 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3592 MVT::i1, MachineNode->getOperand(1),
3593 MachineNode->getOperand(1));
3596 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3597 MVT::i1, MachineNode->getOperand(0),
3598 MachineNode->getOperand(0));
3600 // nor(~x, y) = andc(x, y)
3601 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3602 MVT::i1, MachineNode->getOperand(0).
3604 MachineNode->getOperand(1));
3606 // nor(x, ~y) = andc(y, x)
3607 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3608 MVT::i1, MachineNode->getOperand(1).
3610 MachineNode->getOperand(0));
3611 else if (AllUsersSelectZero(MachineNode))
3612 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
3613 MVT::i1, MachineNode->getOperand(0),
3614 MachineNode->getOperand(1)),
3618 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3620 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3624 ResNode = MachineNode->getOperand(1).getNode();
3627 ResNode = MachineNode->getOperand(0).getNode();
3629 // eqv(0, y) = ~y -> nor(y, y)
3630 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3631 MVT::i1, MachineNode->getOperand(1),
3632 MachineNode->getOperand(1));
3635 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3636 MVT::i1, MachineNode->getOperand(0),
3637 MachineNode->getOperand(0));
3639 // eqv(~x, y) = xor(x, y)
3640 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
3641 MVT::i1, MachineNode->getOperand(0).
3643 MachineNode->getOperand(1));
3645 // eqv(x, ~y) = xor(x, y)
3646 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
3647 MVT::i1, MachineNode->getOperand(0),
3648 MachineNode->getOperand(1).
3650 else if (AllUsersSelectZero(MachineNode))
3651 ResNode = CurDAG->getMachineNode(PPC::CRXOR, SDLoc(MachineNode),
3652 MVT::i1, MachineNode->getOperand(0),
3653 MachineNode->getOperand(1)),
3657 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3659 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3663 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3664 MVT::i1, MachineNode->getOperand(1),
3665 MachineNode->getOperand(1));
3666 else if (Op1Unset || Op2Set)
3667 // andc(0, y) = andc(x, 1) = 0
3668 ResNode = CurDAG->getMachineNode(PPC::CRUNSET, SDLoc(MachineNode),
3672 ResNode = MachineNode->getOperand(0).getNode();
3674 // andc(~x, y) = ~(x | y) = nor(x, y)
3675 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3676 MVT::i1, MachineNode->getOperand(0).
3678 MachineNode->getOperand(1));
3680 // andc(x, ~y) = x & y
3681 ResNode = CurDAG->getMachineNode(PPC::CRAND, SDLoc(MachineNode),
3682 MVT::i1, MachineNode->getOperand(0),
3683 MachineNode->getOperand(1).
3685 else if (AllUsersSelectZero(MachineNode))
3686 ResNode = CurDAG->getMachineNode(PPC::CRORC, SDLoc(MachineNode),
3687 MVT::i1, MachineNode->getOperand(1),
3688 MachineNode->getOperand(0)),
3692 if (MachineNode->getOperand(0) == MachineNode->getOperand(1))
3694 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3696 else if (Op1Set || Op2Unset)
3697 // orc(1, y) = orc(x, 0) = 1
3698 ResNode = CurDAG->getMachineNode(PPC::CRSET, SDLoc(MachineNode),
3702 ResNode = MachineNode->getOperand(0).getNode();
3705 ResNode = CurDAG->getMachineNode(PPC::CRNOR, SDLoc(MachineNode),
3706 MVT::i1, MachineNode->getOperand(1),
3707 MachineNode->getOperand(1));
3709 // orc(~x, y) = ~(x & y) = nand(x, y)
3710 ResNode = CurDAG->getMachineNode(PPC::CRNAND, SDLoc(MachineNode),
3711 MVT::i1, MachineNode->getOperand(0).
3713 MachineNode->getOperand(1));
3715 // orc(x, ~y) = x | y
3716 ResNode = CurDAG->getMachineNode(PPC::CROR, SDLoc(MachineNode),
3717 MVT::i1, MachineNode->getOperand(0),
3718 MachineNode->getOperand(1).
3720 else if (AllUsersSelectZero(MachineNode))
3721 ResNode = CurDAG->getMachineNode(PPC::CRANDC, SDLoc(MachineNode),
3722 MVT::i1, MachineNode->getOperand(1),
3723 MachineNode->getOperand(0)),
3726 case PPC::SELECT_I4:
3727 case PPC::SELECT_I8:
3728 case PPC::SELECT_F4:
3729 case PPC::SELECT_F8:
3730 case PPC::SELECT_QFRC:
3731 case PPC::SELECT_QSRC:
3732 case PPC::SELECT_QBRC:
3733 case PPC::SELECT_VRRC:
3734 case PPC::SELECT_VSFRC:
3735 case PPC::SELECT_VSRC:
3737 ResNode = MachineNode->getOperand(1).getNode();
3739 ResNode = MachineNode->getOperand(2).getNode();
3741 ResNode = CurDAG->getMachineNode(MachineNode->getMachineOpcode(),
3743 MachineNode->getValueType(0),
3744 MachineNode->getOperand(0).
3746 MachineNode->getOperand(2),
3747 MachineNode->getOperand(1));
3752 ResNode = CurDAG->getMachineNode(Opcode == PPC::BC ? PPC::BCn :
3756 MachineNode->getOperand(0).
3758 MachineNode->getOperand(1),
3759 MachineNode->getOperand(2));
3760 // FIXME: Handle Op1Set, Op1Unset here too.
3764 // If we're inverting this node because it is used only by selects that
3765 // we'd like to swap, then swap the selects before the node replacement.
3767 SwapAllSelectUsers(MachineNode);
3769 if (ResNode != MachineNode) {
3770 DEBUG(dbgs() << "CR Peephole replacing:\nOld: ");
3771 DEBUG(MachineNode->dump(CurDAG));
3772 DEBUG(dbgs() << "\nNew: ");
3773 DEBUG(ResNode->dump(CurDAG));
3774 DEBUG(dbgs() << "\n");
3776 ReplaceUses(MachineNode, ResNode);
3781 CurDAG->RemoveDeadNodes();
3782 } while (IsModified);
3785 // Gather the set of 32-bit operations that are known to have their
3786 // higher-order 32 bits zero, where ToPromote contains all such operations.
3787 static bool PeepholePPC64ZExtGather(SDValue Op32,
3788 SmallPtrSetImpl<SDNode *> &ToPromote) {
3789 if (!Op32.isMachineOpcode())
3792 // First, check for the "frontier" instructions (those that will clear the
3793 // higher-order 32 bits.
3795 // For RLWINM and RLWNM, we need to make sure that the mask does not wrap
3796 // around. If it does not, then these instructions will clear the
3797 // higher-order bits.
3798 if ((Op32.getMachineOpcode() == PPC::RLWINM ||
3799 Op32.getMachineOpcode() == PPC::RLWNM) &&
3800 Op32.getConstantOperandVal(2) <= Op32.getConstantOperandVal(3)) {
3801 ToPromote.insert(Op32.getNode());
3805 // SLW and SRW always clear the higher-order bits.
3806 if (Op32.getMachineOpcode() == PPC::SLW ||
3807 Op32.getMachineOpcode() == PPC::SRW) {
3808 ToPromote.insert(Op32.getNode());
3812 // For LI and LIS, we need the immediate to be positive (so that it is not
3814 if (Op32.getMachineOpcode() == PPC::LI ||
3815 Op32.getMachineOpcode() == PPC::LIS) {
3816 if (!isUInt<15>(Op32.getConstantOperandVal(0)))
3819 ToPromote.insert(Op32.getNode());
3823 // LHBRX and LWBRX always clear the higher-order bits.
3824 if (Op32.getMachineOpcode() == PPC::LHBRX ||
3825 Op32.getMachineOpcode() == PPC::LWBRX) {
3826 ToPromote.insert(Op32.getNode());
3830 // CNTLZW always produces a 64-bit value in [0,32], and so is zero extended.
3831 if (Op32.getMachineOpcode() == PPC::CNTLZW) {
3832 ToPromote.insert(Op32.getNode());
3836 // Next, check for those instructions we can look through.
3838 // Assuming the mask does not wrap around, then the higher-order bits are
3839 // taken directly from the first operand.
3840 if (Op32.getMachineOpcode() == PPC::RLWIMI &&
3841 Op32.getConstantOperandVal(3) <= Op32.getConstantOperandVal(4)) {
3842 SmallPtrSet<SDNode *, 16> ToPromote1;
3843 if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
3846 ToPromote.insert(Op32.getNode());
3847 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3851 // For OR, the higher-order bits are zero if that is true for both operands.
3852 // For SELECT_I4, the same is true (but the relevant operand numbers are
3854 if (Op32.getMachineOpcode() == PPC::OR ||
3855 Op32.getMachineOpcode() == PPC::SELECT_I4) {
3856 unsigned B = Op32.getMachineOpcode() == PPC::SELECT_I4 ? 1 : 0;
3857 SmallPtrSet<SDNode *, 16> ToPromote1;
3858 if (!PeepholePPC64ZExtGather(Op32.getOperand(B+0), ToPromote1))
3860 if (!PeepholePPC64ZExtGather(Op32.getOperand(B+1), ToPromote1))
3863 ToPromote.insert(Op32.getNode());
3864 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3868 // For ORI and ORIS, we need the higher-order bits of the first operand to be
3869 // zero, and also for the constant to be positive (so that it is not sign
3871 if (Op32.getMachineOpcode() == PPC::ORI ||
3872 Op32.getMachineOpcode() == PPC::ORIS) {
3873 SmallPtrSet<SDNode *, 16> ToPromote1;
3874 if (!PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1))
3876 if (!isUInt<15>(Op32.getConstantOperandVal(1)))
3879 ToPromote.insert(Op32.getNode());
3880 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3884 // The higher-order bits of AND are zero if that is true for at least one of
3886 if (Op32.getMachineOpcode() == PPC::AND) {
3887 SmallPtrSet<SDNode *, 16> ToPromote1, ToPromote2;
3889 PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
3891 PeepholePPC64ZExtGather(Op32.getOperand(1), ToPromote2);
3892 if (!Op0OK && !Op1OK)
3895 ToPromote.insert(Op32.getNode());
3898 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3901 ToPromote.insert(ToPromote2.begin(), ToPromote2.end());
3906 // For ANDI and ANDIS, the higher-order bits are zero if either that is true
3907 // of the first operand, or if the second operand is positive (so that it is
3908 // not sign extended).
3909 if (Op32.getMachineOpcode() == PPC::ANDIo ||
3910 Op32.getMachineOpcode() == PPC::ANDISo) {
3911 SmallPtrSet<SDNode *, 16> ToPromote1;
3913 PeepholePPC64ZExtGather(Op32.getOperand(0), ToPromote1);
3914 bool Op1OK = isUInt<15>(Op32.getConstantOperandVal(1));
3915 if (!Op0OK && !Op1OK)
3918 ToPromote.insert(Op32.getNode());
3921 ToPromote.insert(ToPromote1.begin(), ToPromote1.end());
3929 void PPCDAGToDAGISel::PeepholePPC64ZExt() {
3930 if (!PPCSubTarget->isPPC64())
3933 // When we zero-extend from i32 to i64, we use a pattern like this:
3934 // def : Pat<(i64 (zext i32:$in)),
3935 // (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
3937 // There are several 32-bit shift/rotate instructions, however, that will
3938 // clear the higher-order bits of their output, rendering the RLDICL
3939 // unnecessary. When that happens, we remove it here, and redefine the
3940 // relevant 32-bit operation to be a 64-bit operation.
3942 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
3945 bool MadeChange = false;
3946 while (Position != CurDAG->allnodes_begin()) {
3947 SDNode *N = --Position;
3948 // Skip dead nodes and any non-machine opcodes.
3949 if (N->use_empty() || !N->isMachineOpcode())
3952 if (N->getMachineOpcode() != PPC::RLDICL)
3955 if (N->getConstantOperandVal(1) != 0 ||
3956 N->getConstantOperandVal(2) != 32)
3959 SDValue ISR = N->getOperand(0);
3960 if (!ISR.isMachineOpcode() ||
3961 ISR.getMachineOpcode() != TargetOpcode::INSERT_SUBREG)
3964 if (!ISR.hasOneUse())
3967 if (ISR.getConstantOperandVal(2) != PPC::sub_32)
3970 SDValue IDef = ISR.getOperand(0);
3971 if (!IDef.isMachineOpcode() ||
3972 IDef.getMachineOpcode() != TargetOpcode::IMPLICIT_DEF)
3975 // We now know that we're looking at a canonical i32 -> i64 zext. See if we
3976 // can get rid of it.
3978 SDValue Op32 = ISR->getOperand(1);
3979 if (!Op32.isMachineOpcode())
3982 // There are some 32-bit instructions that always clear the high-order 32
3983 // bits, there are also some instructions (like AND) that we can look
3985 SmallPtrSet<SDNode *, 16> ToPromote;
3986 if (!PeepholePPC64ZExtGather(Op32, ToPromote))
3989 // If the ToPromote set contains nodes that have uses outside of the set
3990 // (except for the original INSERT_SUBREG), then abort the transformation.
3991 bool OutsideUse = false;
3992 for (SDNode *PN : ToPromote) {
3993 for (SDNode *UN : PN->uses()) {
3994 if (!ToPromote.count(UN) && UN != ISR.getNode()) {
4008 // We now know that this zero extension can be removed by promoting to
4009 // nodes in ToPromote to 64-bit operations, where for operations in the
4010 // frontier of the set, we need to insert INSERT_SUBREGs for their
4012 for (SDNode *PN : ToPromote) {
4014 switch (PN->getMachineOpcode()) {
4016 llvm_unreachable("Don't know the 64-bit variant of this instruction");
4017 case PPC::RLWINM: NewOpcode = PPC::RLWINM8; break;
4018 case PPC::RLWNM: NewOpcode = PPC::RLWNM8; break;
4019 case PPC::SLW: NewOpcode = PPC::SLW8; break;
4020 case PPC::SRW: NewOpcode = PPC::SRW8; break;
4021 case PPC::LI: NewOpcode = PPC::LI8; break;
4022 case PPC::LIS: NewOpcode = PPC::LIS8; break;
4023 case PPC::LHBRX: NewOpcode = PPC::LHBRX8; break;
4024 case PPC::LWBRX: NewOpcode = PPC::LWBRX8; break;
4025 case PPC::CNTLZW: NewOpcode = PPC::CNTLZW8; break;
4026 case PPC::RLWIMI: NewOpcode = PPC::RLWIMI8; break;
4027 case PPC::OR: NewOpcode = PPC::OR8; break;
4028 case PPC::SELECT_I4: NewOpcode = PPC::SELECT_I8; break;
4029 case PPC::ORI: NewOpcode = PPC::ORI8; break;
4030 case PPC::ORIS: NewOpcode = PPC::ORIS8; break;
4031 case PPC::AND: NewOpcode = PPC::AND8; break;
4032 case PPC::ANDIo: NewOpcode = PPC::ANDIo8; break;
4033 case PPC::ANDISo: NewOpcode = PPC::ANDISo8; break;
4036 // Note: During the replacement process, the nodes will be in an
4037 // inconsistent state (some instructions will have operands with values
4038 // of the wrong type). Once done, however, everything should be right
4041 SmallVector<SDValue, 4> Ops;
4042 for (const SDValue &V : PN->ops()) {
4043 if (!ToPromote.count(V.getNode()) && V.getValueType() == MVT::i32 &&
4044 !isa<ConstantSDNode>(V)) {
4045 SDValue ReplOpOps[] = { ISR.getOperand(0), V, ISR.getOperand(2) };
4047 CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG, SDLoc(V),
4048 ISR.getNode()->getVTList(), ReplOpOps);
4049 Ops.push_back(SDValue(ReplOp, 0));
4055 // Because all to-be-promoted nodes only have users that are other
4056 // promoted nodes (or the original INSERT_SUBREG), we can safely replace
4057 // the i32 result value type with i64.
4059 SmallVector<EVT, 2> NewVTs;
4060 SDVTList VTs = PN->getVTList();
4061 for (unsigned i = 0, ie = VTs.NumVTs; i != ie; ++i)
4062 if (VTs.VTs[i] == MVT::i32)
4063 NewVTs.push_back(MVT::i64);
4065 NewVTs.push_back(VTs.VTs[i]);
4067 DEBUG(dbgs() << "PPC64 ZExt Peephole morphing:\nOld: ");
4068 DEBUG(PN->dump(CurDAG));
4070 CurDAG->SelectNodeTo(PN, NewOpcode, CurDAG->getVTList(NewVTs), Ops);
4072 DEBUG(dbgs() << "\nNew: ");
4073 DEBUG(PN->dump(CurDAG));
4074 DEBUG(dbgs() << "\n");
4077 // Now we replace the original zero extend and its associated INSERT_SUBREG
4078 // with the value feeding the INSERT_SUBREG (which has now been promoted to
4081 DEBUG(dbgs() << "PPC64 ZExt Peephole replacing:\nOld: ");
4082 DEBUG(N->dump(CurDAG));
4083 DEBUG(dbgs() << "\nNew: ");
4084 DEBUG(Op32.getNode()->dump(CurDAG));
4085 DEBUG(dbgs() << "\n");
4087 ReplaceUses(N, Op32.getNode());
4091 CurDAG->RemoveDeadNodes();
4094 void PPCDAGToDAGISel::PeepholePPC64() {
4095 // These optimizations are currently supported only for 64-bit SVR4.
4096 if (PPCSubTarget->isDarwin() || !PPCSubTarget->isPPC64())
4099 SelectionDAG::allnodes_iterator Position(CurDAG->getRoot().getNode());
4102 while (Position != CurDAG->allnodes_begin()) {
4103 SDNode *N = --Position;
4104 // Skip dead nodes and any non-machine opcodes.
4105 if (N->use_empty() || !N->isMachineOpcode())
4109 unsigned StorageOpcode = N->getMachineOpcode();
4111 switch (StorageOpcode) {
4142 // If this is a load or store with a zero offset, we may be able to
4143 // fold an add-immediate into the memory operation.
4144 if (!isa<ConstantSDNode>(N->getOperand(FirstOp)) ||
4145 N->getConstantOperandVal(FirstOp) != 0)
4148 SDValue Base = N->getOperand(FirstOp + 1);
4149 if (!Base.isMachineOpcode())
4153 bool ReplaceFlags = true;
4155 // When the feeding operation is an add-immediate of some sort,
4156 // determine whether we need to add relocation information to the
4157 // target flags on the immediate operand when we fold it into the
4158 // load instruction.
4160 // For something like ADDItocL, the relocation information is
4161 // inferred from the opcode; when we process it in the AsmPrinter,
4162 // we add the necessary relocation there. A load, though, can receive
4163 // relocation from various flavors of ADDIxxx, so we need to carry
4164 // the relocation information in the target flags.
4165 switch (Base.getMachineOpcode()) {
4170 // In some cases (such as TLS) the relocation information
4171 // is already in place on the operand, so copying the operand
4173 ReplaceFlags = false;
4174 // For these cases, the immediate may not be divisible by 4, in
4175 // which case the fold is illegal for DS-form instructions. (The
4176 // other cases provide aligned addresses and are always safe.)
4177 if ((StorageOpcode == PPC::LWA ||
4178 StorageOpcode == PPC::LD ||
4179 StorageOpcode == PPC::STD) &&
4180 (!isa<ConstantSDNode>(Base.getOperand(1)) ||
4181 Base.getConstantOperandVal(1) % 4 != 0))
4184 case PPC::ADDIdtprelL:
4185 Flags = PPCII::MO_DTPREL_LO;
4187 case PPC::ADDItlsldL:
4188 Flags = PPCII::MO_TLSLD_LO;
4191 Flags = PPCII::MO_TOC_LO;
4195 // We found an opportunity. Reverse the operands from the add
4196 // immediate and substitute them into the load or store. If
4197 // needed, update the target flags for the immediate operand to
4198 // reflect the necessary relocation information.
4199 DEBUG(dbgs() << "Folding add-immediate into mem-op:\nBase: ");
4200 DEBUG(Base->dump(CurDAG));
4201 DEBUG(dbgs() << "\nN: ");
4202 DEBUG(N->dump(CurDAG));
4203 DEBUG(dbgs() << "\n");
4205 SDValue ImmOpnd = Base.getOperand(1);
4207 // If the relocation information isn't already present on the
4208 // immediate operand, add it now.
4210 if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
4212 const GlobalValue *GV = GA->getGlobal();
4213 // We can't perform this optimization for data whose alignment
4214 // is insufficient for the instruction encoding.
4215 if (GV->getAlignment() < 4 &&
4216 (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD ||
4217 StorageOpcode == PPC::LWA)) {
4218 DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
4221 ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);
4222 } else if (ConstantPoolSDNode *CP =
4223 dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {
4224 const Constant *C = CP->getConstVal();
4225 ImmOpnd = CurDAG->getTargetConstantPool(C, MVT::i64,
4231 if (FirstOp == 1) // Store
4232 (void)CurDAG->UpdateNodeOperands(N, N->getOperand(0), ImmOpnd,
4233 Base.getOperand(0), N->getOperand(3));
4235 (void)CurDAG->UpdateNodeOperands(N, ImmOpnd, Base.getOperand(0),
4238 // The add-immediate may now be dead, in which case remove it.
4239 if (Base.getNode()->use_empty())
4240 CurDAG->RemoveDeadNode(Base.getNode());
4245 /// createPPCISelDag - This pass converts a legalized DAG into a
4246 /// PowerPC-specific DAG, ready for instruction scheduling.
4248 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
4249 return new PPCDAGToDAGISel(TM);
4252 static void initializePassOnce(PassRegistry &Registry) {
4253 const char *Name = "PowerPC DAG->DAG Pattern Instruction Selection";
4254 PassInfo *PI = new PassInfo(Name, "ppc-codegen", &SelectionDAGISel::ID,
4255 nullptr, false, false);
4256 Registry.registerPass(*PI, true);
4259 void llvm::initializePPCDAGToDAGISelPass(PassRegistry &Registry) {
4260 CALL_ONCE_INITIALIZATION(initializePassOnce);