1 //===-- PPCISelDAGToDAG.cpp - PPC --pattern matching inst selector --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for PowerPC,
11 // converting from a legalized dag to a PPC dag.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "ppc-codegen"
17 #include "PPCPredicates.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCISelLowering.h"
20 #include "PPCHazardRecognizers.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/SelectionDAG.h"
25 #include "llvm/CodeGen/SelectionDAGISel.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Constants.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/Compiler.h"
38 //===--------------------------------------------------------------------===//
39 /// PPCDAGToDAGISel - PPC specific code to select PPC machine
40 /// instructions for SelectionDAG operations.
42 class VISIBILITY_HIDDEN PPCDAGToDAGISel : public SelectionDAGISel {
44 PPCTargetLowering PPCLowering;
45 const PPCSubtarget &PPCSubTarget;
46 unsigned GlobalBaseReg;
48 explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
49 : SelectionDAGISel(PPCLowering), TM(tm),
50 PPCLowering(*TM.getTargetLowering()),
51 PPCSubTarget(*TM.getSubtargetImpl()) {}
53 virtual bool runOnFunction(Function &Fn) {
54 // Make sure we re-emit a set of the global base reg if necessary
56 SelectionDAGISel::runOnFunction(Fn);
62 /// getI32Imm - Return a target constant with the specified value, of type
64 inline SDOperand getI32Imm(unsigned Imm) {
65 return CurDAG->getTargetConstant(Imm, MVT::i32);
68 /// getI64Imm - Return a target constant with the specified value, of type
70 inline SDOperand getI64Imm(uint64_t Imm) {
71 return CurDAG->getTargetConstant(Imm, MVT::i64);
74 /// getSmallIPtrImm - Return a target constant of pointer type.
75 inline SDOperand getSmallIPtrImm(unsigned Imm) {
76 return CurDAG->getTargetConstant(Imm, PPCLowering.getPointerTy());
79 /// isRunOfOnes - Returns true iff Val consists of one contiguous run of 1s
80 /// with any number of 0s on either side. The 1s are allowed to wrap from
81 /// LSB to MSB, so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs.
82 /// 0x0F0F0000 is not, since all 1s are not contiguous.
83 static bool isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME);
86 /// isRotateAndMask - Returns true if Mask and Shift can be folded into a
87 /// rotate and mask opcode and mask operation.
88 static bool isRotateAndMask(SDNode *N, unsigned Mask, bool IsShiftMask,
89 unsigned &SH, unsigned &MB, unsigned &ME);
91 /// getGlobalBaseReg - insert code into the entry mbb to materialize the PIC
92 /// base register. Return the virtual register that holds this value.
93 SDNode *getGlobalBaseReg();
95 // Select - Convert the specified operand from a target-independent to a
96 // target-specific node if it hasn't already been changed.
97 SDNode *Select(SDOperand Op);
99 SDNode *SelectBitfieldInsert(SDNode *N);
101 /// SelectCC - Select a comparison of the specified values with the
102 /// specified condition code, returning the CR# of the expression.
103 SDOperand SelectCC(SDOperand LHS, SDOperand RHS, ISD::CondCode CC);
105 /// SelectAddrImm - Returns true if the address N can be represented by
106 /// a base register plus a signed 16-bit displacement [r+imm].
107 bool SelectAddrImm(SDOperand Op, SDOperand N, SDOperand &Disp,
109 return PPCLowering.SelectAddressRegImm(N, Disp, Base, *CurDAG);
112 /// SelectAddrImmOffs - Return true if the operand is valid for a preinc
113 /// immediate field. Because preinc imms have already been validated, just
115 bool SelectAddrImmOffs(SDOperand Op, SDOperand N, SDOperand &Out) const {
120 /// SelectAddrIdx - Given the specified addressed, check to see if it can be
121 /// represented as an indexed [r+r] operation. Returns false if it can
122 /// be represented by [r+imm], which are preferred.
123 bool SelectAddrIdx(SDOperand Op, SDOperand N, SDOperand &Base,
125 return PPCLowering.SelectAddressRegReg(N, Base, Index, *CurDAG);
128 /// SelectAddrIdxOnly - Given the specified addressed, force it to be
129 /// represented as an indexed [r+r] operation.
130 bool SelectAddrIdxOnly(SDOperand Op, SDOperand N, SDOperand &Base,
132 return PPCLowering.SelectAddressRegRegOnly(N, Base, Index, *CurDAG);
135 /// SelectAddrImmShift - Returns true if the address N can be represented by
136 /// a base register plus a signed 14-bit displacement [r+imm*4]. Suitable
137 /// for use by STD and friends.
138 bool SelectAddrImmShift(SDOperand Op, SDOperand N, SDOperand &Disp,
140 return PPCLowering.SelectAddressRegImmShift(N, Disp, Base, *CurDAG);
143 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
144 /// inline asm expressions.
145 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
147 std::vector<SDOperand> &OutOps,
150 switch (ConstraintCode) {
151 default: return true;
153 if (!SelectAddrIdx(Op, Op, Op0, Op1))
154 SelectAddrImm(Op, Op, Op0, Op1);
156 case 'o': // offsetable
157 if (!SelectAddrImm(Op, Op, Op0, Op1)) {
159 AddToISelQueue(Op0); // r+0.
160 Op1 = getSmallIPtrImm(0);
163 case 'v': // not offsetable
164 SelectAddrIdxOnly(Op, Op, Op0, Op1);
168 OutOps.push_back(Op0);
169 OutOps.push_back(Op1);
173 SDOperand BuildSDIVSequence(SDNode *N);
174 SDOperand BuildUDIVSequence(SDNode *N);
176 /// InstructionSelect - This callback is invoked by
177 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
178 virtual void InstructionSelect(SelectionDAG &DAG);
180 void InsertVRSaveCode(Function &Fn);
182 virtual const char *getPassName() const {
183 return "PowerPC DAG->DAG Pattern Instruction Selection";
186 /// CreateTargetHazardRecognizer - Return the hazard recognizer to use for
187 /// this target when scheduling the DAG.
188 virtual HazardRecognizer *CreateTargetHazardRecognizer() {
189 // Should use subtarget info to pick the right hazard recognizer. For
190 // now, always return a PPC970 recognizer.
191 const TargetInstrInfo *II = PPCLowering.getTargetMachine().getInstrInfo();
192 assert(II && "No InstrInfo?");
193 return new PPCHazardRecognizer970(*II);
196 // Include the pieces autogenerated from the target description.
197 #include "PPCGenDAGISel.inc"
200 SDNode *SelectSETCC(SDOperand Op);
204 /// InstructionSelect - This callback is invoked by
205 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
206 void PPCDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
209 // Select target instructions for the DAG.
210 DAG.setRoot(SelectRoot(DAG.getRoot()));
211 DAG.RemoveDeadNodes();
214 /// InsertVRSaveCode - Once the entire function has been instruction selected,
215 /// all virtual registers are created and all machine instructions are built,
216 /// check to see if we need to save/restore VRSAVE. If so, do it.
217 void PPCDAGToDAGISel::InsertVRSaveCode(Function &F) {
218 // Check to see if this function uses vector registers, which means we have to
219 // save and restore the VRSAVE register and update it with the regs we use.
221 // In this case, there will be virtual registers of vector type type created
222 // by the scheduler. Detect them now.
223 MachineFunction &Fn = MachineFunction::get(&F);
224 bool HasVectorVReg = false;
225 for (unsigned i = TargetRegisterInfo::FirstVirtualRegister,
226 e = RegInfo->getLastVirtReg()+1; i != e; ++i)
227 if (RegInfo->getRegClass(i) == &PPC::VRRCRegClass) {
228 HasVectorVReg = true;
231 if (!HasVectorVReg) return; // nothing to do.
233 // If we have a vector register, we want to emit code into the entry and exit
234 // blocks to save and restore the VRSAVE register. We do this here (instead
235 // of marking all vector instructions as clobbering VRSAVE) for two reasons:
237 // 1. This (trivially) reduces the load on the register allocator, by not
238 // having to represent the live range of the VRSAVE register.
239 // 2. This (more significantly) allows us to create a temporary virtual
240 // register to hold the saved VRSAVE value, allowing this temporary to be
241 // register allocated, instead of forcing it to be spilled to the stack.
243 // Create two vregs - one to hold the VRSAVE register that is live-in to the
244 // function and one for the value after having bits or'd into it.
245 unsigned InVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
246 unsigned UpdatedVRSAVE = RegInfo->createVirtualRegister(&PPC::GPRCRegClass);
248 const TargetInstrInfo &TII = *TM.getInstrInfo();
249 MachineBasicBlock &EntryBB = *Fn.begin();
250 // Emit the following code into the entry block:
251 // InVRSAVE = MFVRSAVE
252 // UpdatedVRSAVE = UPDATE_VRSAVE InVRSAVE
253 // MTVRSAVE UpdatedVRSAVE
254 MachineBasicBlock::iterator IP = EntryBB.begin(); // Insert Point
255 BuildMI(EntryBB, IP, TII.get(PPC::MFVRSAVE), InVRSAVE);
256 BuildMI(EntryBB, IP, TII.get(PPC::UPDATE_VRSAVE),
257 UpdatedVRSAVE).addReg(InVRSAVE);
258 BuildMI(EntryBB, IP, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
260 // Find all return blocks, outputting a restore in each epilog.
261 for (MachineFunction::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) {
262 if (!BB->empty() && BB->back().getDesc().isReturn()) {
263 IP = BB->end(); --IP;
265 // Skip over all terminator instructions, which are part of the return
267 MachineBasicBlock::iterator I2 = IP;
268 while (I2 != BB->begin() && (--I2)->getDesc().isTerminator())
271 // Emit: MTVRSAVE InVRSave
272 BuildMI(*BB, IP, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
278 /// getGlobalBaseReg - Output the instructions required to put the
279 /// base address to use for accessing globals into a register.
281 SDNode *PPCDAGToDAGISel::getGlobalBaseReg() {
282 if (!GlobalBaseReg) {
283 const TargetInstrInfo &TII = *TM.getInstrInfo();
284 // Insert the set of GlobalBaseReg into the first MBB of the function
285 MachineBasicBlock &FirstMBB = BB->getParent()->front();
286 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
288 if (PPCLowering.getPointerTy() == MVT::i32) {
289 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::GPRCRegisterClass);
290 BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR), PPC::LR);
291 BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR), GlobalBaseReg);
293 GlobalBaseReg = RegInfo->createVirtualRegister(PPC::G8RCRegisterClass);
294 BuildMI(FirstMBB, MBBI, TII.get(PPC::MovePCtoLR8), PPC::LR8);
295 BuildMI(FirstMBB, MBBI, TII.get(PPC::MFLR8), GlobalBaseReg);
298 return CurDAG->getRegister(GlobalBaseReg, PPCLowering.getPointerTy()).Val;
301 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
302 /// or 64-bit immediate, and if the value can be accurately represented as a
303 /// sign extension from a 16-bit value. If so, this returns true and the
305 static bool isIntS16Immediate(SDNode *N, short &Imm) {
306 if (N->getOpcode() != ISD::Constant)
309 Imm = (short)cast<ConstantSDNode>(N)->getValue();
310 if (N->getValueType(0) == MVT::i32)
311 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
313 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
316 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
317 return isIntS16Immediate(Op.Val, Imm);
321 /// isInt32Immediate - This method tests to see if the node is a 32-bit constant
322 /// operand. If so Imm will receive the 32-bit value.
323 static bool isInt32Immediate(SDNode *N, unsigned &Imm) {
324 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) {
325 Imm = cast<ConstantSDNode>(N)->getValue();
331 /// isInt64Immediate - This method tests to see if the node is a 64-bit constant
332 /// operand. If so Imm will receive the 64-bit value.
333 static bool isInt64Immediate(SDNode *N, uint64_t &Imm) {
334 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) {
335 Imm = cast<ConstantSDNode>(N)->getValue();
341 // isInt32Immediate - This method tests to see if a constant operand.
342 // If so Imm will receive the 32 bit value.
343 static bool isInt32Immediate(SDOperand N, unsigned &Imm) {
344 return isInt32Immediate(N.Val, Imm);
348 // isOpcWithIntImmediate - This method tests to see if the node is a specific
349 // opcode and that it has a immediate integer right operand.
350 // If so Imm will receive the 32 bit value.
351 static bool isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) {
352 return N->getOpcode() == Opc && isInt32Immediate(N->getOperand(1).Val, Imm);
355 bool PPCDAGToDAGISel::isRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
356 if (isShiftedMask_32(Val)) {
357 // look for the first non-zero bit
358 MB = CountLeadingZeros_32(Val);
359 // look for the first zero bit after the run of ones
360 ME = CountLeadingZeros_32((Val - 1) ^ Val);
363 Val = ~Val; // invert mask
364 if (isShiftedMask_32(Val)) {
365 // effectively look for the first zero bit
366 ME = CountLeadingZeros_32(Val) - 1;
367 // effectively look for the first one bit after the run of zeros
368 MB = CountLeadingZeros_32((Val - 1) ^ Val) + 1;
376 bool PPCDAGToDAGISel::isRotateAndMask(SDNode *N, unsigned Mask,
377 bool IsShiftMask, unsigned &SH,
378 unsigned &MB, unsigned &ME) {
379 // Don't even go down this path for i64, since different logic will be
380 // necessary for rldicl/rldicr/rldimi.
381 if (N->getValueType(0) != MVT::i32)
385 unsigned Indeterminant = ~0; // bit mask marking indeterminant results
386 unsigned Opcode = N->getOpcode();
387 if (N->getNumOperands() != 2 ||
388 !isInt32Immediate(N->getOperand(1).Val, Shift) || (Shift > 31))
391 if (Opcode == ISD::SHL) {
392 // apply shift left to mask if it comes first
393 if (IsShiftMask) Mask = Mask << Shift;
394 // determine which bits are made indeterminant by shift
395 Indeterminant = ~(0xFFFFFFFFu << Shift);
396 } else if (Opcode == ISD::SRL) {
397 // apply shift right to mask if it comes first
398 if (IsShiftMask) Mask = Mask >> Shift;
399 // determine which bits are made indeterminant by shift
400 Indeterminant = ~(0xFFFFFFFFu >> Shift);
401 // adjust for the left rotate
403 } else if (Opcode == ISD::ROTL) {
409 // if the mask doesn't intersect any Indeterminant bits
410 if (Mask && !(Mask & Indeterminant)) {
412 // make sure the mask is still a mask (wrap arounds may not be)
413 return isRunOfOnes(Mask, MB, ME);
418 /// SelectBitfieldInsert - turn an or of two masked values into
419 /// the rotate left word immediate then mask insert (rlwimi) instruction.
420 SDNode *PPCDAGToDAGISel::SelectBitfieldInsert(SDNode *N) {
421 SDOperand Op0 = N->getOperand(0);
422 SDOperand Op1 = N->getOperand(1);
424 APInt LKZ, LKO, RKZ, RKO;
425 CurDAG->ComputeMaskedBits(Op0, APInt::getAllOnesValue(32), LKZ, LKO);
426 CurDAG->ComputeMaskedBits(Op1, APInt::getAllOnesValue(32), RKZ, RKO);
428 unsigned TargetMask = LKZ.getZExtValue();
429 unsigned InsertMask = RKZ.getZExtValue();
431 if ((TargetMask | InsertMask) == 0xFFFFFFFF) {
432 unsigned Op0Opc = Op0.getOpcode();
433 unsigned Op1Opc = Op1.getOpcode();
434 unsigned Value, SH = 0;
435 TargetMask = ~TargetMask;
436 InsertMask = ~InsertMask;
438 // If the LHS has a foldable shift and the RHS does not, then swap it to the
439 // RHS so that we can fold the shift into the insert.
440 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
441 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
442 Op0.getOperand(0).getOpcode() == ISD::SRL) {
443 if (Op1.getOperand(0).getOpcode() != ISD::SHL &&
444 Op1.getOperand(0).getOpcode() != ISD::SRL) {
446 std::swap(Op0Opc, Op1Opc);
447 std::swap(TargetMask, InsertMask);
450 } else if (Op0Opc == ISD::SHL || Op0Opc == ISD::SRL) {
451 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL &&
452 Op1.getOperand(0).getOpcode() != ISD::SRL) {
454 std::swap(Op0Opc, Op1Opc);
455 std::swap(TargetMask, InsertMask);
460 if (InsertMask && isRunOfOnes(InsertMask, MB, ME)) {
461 SDOperand Tmp1, Tmp2, Tmp3;
462 bool DisjointMask = (TargetMask ^ InsertMask) == 0xFFFFFFFF;
464 if ((Op1Opc == ISD::SHL || Op1Opc == ISD::SRL) &&
465 isInt32Immediate(Op1.getOperand(1), Value)) {
466 Op1 = Op1.getOperand(0);
467 SH = (Op1Opc == ISD::SHL) ? Value : 32 - Value;
469 if (Op1Opc == ISD::AND) {
470 unsigned SHOpc = Op1.getOperand(0).getOpcode();
471 if ((SHOpc == ISD::SHL || SHOpc == ISD::SRL) &&
472 isInt32Immediate(Op1.getOperand(0).getOperand(1), Value)) {
473 Op1 = Op1.getOperand(0).getOperand(0);
474 SH = (SHOpc == ISD::SHL) ? Value : 32 - Value;
476 Op1 = Op1.getOperand(0);
480 Tmp3 = (Op0Opc == ISD::AND && DisjointMask) ? Op0.getOperand(0) : Op0;
481 AddToISelQueue(Tmp3);
484 SDOperand Ops[] = { Tmp3, Op1, getI32Imm(SH), getI32Imm(MB),
486 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
492 /// SelectCC - Select a comparison of the specified values with the specified
493 /// condition code, returning the CR# of the expression.
494 SDOperand PPCDAGToDAGISel::SelectCC(SDOperand LHS, SDOperand RHS,
496 // Always select the LHS.
500 if (LHS.getValueType() == MVT::i32) {
502 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
503 if (isInt32Immediate(RHS, Imm)) {
504 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
506 return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
507 getI32Imm(Imm & 0xFFFF)), 0);
508 // If this is a 16-bit signed immediate, fold it.
509 if (isInt16((int)Imm))
510 return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
511 getI32Imm(Imm & 0xFFFF)), 0);
513 // For non-equality comparisons, the default code would materialize the
514 // constant, then compare against it, like this:
518 // Since we are just comparing for equality, we can emit this instead:
519 // xoris r0,r3,0x1234
520 // cmplwi cr0,r0,0x5678
522 SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS, MVT::i32, LHS,
523 getI32Imm(Imm >> 16)), 0);
524 return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, Xor,
525 getI32Imm(Imm & 0xFFFF)), 0);
528 } else if (ISD::isUnsignedIntSetCC(CC)) {
529 if (isInt32Immediate(RHS, Imm) && isUInt16(Imm))
530 return SDOperand(CurDAG->getTargetNode(PPC::CMPLWI, MVT::i32, LHS,
531 getI32Imm(Imm & 0xFFFF)), 0);
535 if (isIntS16Immediate(RHS, SImm))
536 return SDOperand(CurDAG->getTargetNode(PPC::CMPWI, MVT::i32, LHS,
537 getI32Imm((int)SImm & 0xFFFF)),
541 } else if (LHS.getValueType() == MVT::i64) {
543 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
544 if (isInt64Immediate(RHS.Val, Imm)) {
545 // SETEQ/SETNE comparison with 16-bit immediate, fold it.
547 return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
548 getI32Imm(Imm & 0xFFFF)), 0);
549 // If this is a 16-bit signed immediate, fold it.
551 return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
552 getI32Imm(Imm & 0xFFFF)), 0);
554 // For non-equality comparisons, the default code would materialize the
555 // constant, then compare against it, like this:
559 // Since we are just comparing for equality, we can emit this instead:
560 // xoris r0,r3,0x1234
561 // cmpldi cr0,r0,0x5678
564 SDOperand Xor(CurDAG->getTargetNode(PPC::XORIS8, MVT::i64, LHS,
565 getI64Imm(Imm >> 16)), 0);
566 return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, Xor,
567 getI64Imm(Imm & 0xFFFF)), 0);
571 } else if (ISD::isUnsignedIntSetCC(CC)) {
572 if (isInt64Immediate(RHS.Val, Imm) && isUInt16(Imm))
573 return SDOperand(CurDAG->getTargetNode(PPC::CMPLDI, MVT::i64, LHS,
574 getI64Imm(Imm & 0xFFFF)), 0);
578 if (isIntS16Immediate(RHS, SImm))
579 return SDOperand(CurDAG->getTargetNode(PPC::CMPDI, MVT::i64, LHS,
580 getI64Imm(SImm & 0xFFFF)),
584 } else if (LHS.getValueType() == MVT::f32) {
587 assert(LHS.getValueType() == MVT::f64 && "Unknown vt!");
591 return SDOperand(CurDAG->getTargetNode(Opc, MVT::i32, LHS, RHS), 0);
594 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
596 default: assert(0 && "Unknown condition!"); abort();
597 case ISD::SETOEQ: // FIXME: This is incorrect see PR642.
599 case ISD::SETEQ: return PPC::PRED_EQ;
600 case ISD::SETONE: // FIXME: This is incorrect see PR642.
602 case ISD::SETNE: return PPC::PRED_NE;
603 case ISD::SETOLT: // FIXME: This is incorrect see PR642.
605 case ISD::SETLT: return PPC::PRED_LT;
606 case ISD::SETOLE: // FIXME: This is incorrect see PR642.
608 case ISD::SETLE: return PPC::PRED_LE;
609 case ISD::SETOGT: // FIXME: This is incorrect see PR642.
611 case ISD::SETGT: return PPC::PRED_GT;
612 case ISD::SETOGE: // FIXME: This is incorrect see PR642.
614 case ISD::SETGE: return PPC::PRED_GE;
616 case ISD::SETO: return PPC::PRED_NU;
617 case ISD::SETUO: return PPC::PRED_UN;
621 /// getCRIdxForSetCC - Return the index of the condition register field
622 /// associated with the SetCC condition, and whether or not the field is
623 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
625 /// If this returns with Other != -1, then the returned comparison is an or of
626 /// two simpler comparisons. In this case, Invert is guaranteed to be false.
627 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) {
631 default: assert(0 && "Unknown condition!"); abort();
633 case ISD::SETLT: return 0; // Bit #0 = SETOLT
635 case ISD::SETGT: return 1; // Bit #1 = SETOGT
637 case ISD::SETEQ: return 2; // Bit #2 = SETOEQ
638 case ISD::SETUO: return 3; // Bit #3 = SETUO
640 case ISD::SETGE: Invert = true; return 0; // !Bit #0 = SETUGE
642 case ISD::SETLE: Invert = true; return 1; // !Bit #1 = SETULE
644 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE
645 case ISD::SETO: Invert = true; return 3; // !Bit #3 = SETO
646 case ISD::SETULT: Other = 0; return 3; // SETOLT | SETUO
647 case ISD::SETUGT: Other = 1; return 3; // SETOGT | SETUO
648 case ISD::SETUEQ: Other = 2; return 3; // SETOEQ | SETUO
649 case ISD::SETOGE: Other = 1; return 2; // SETOGT | SETOEQ
650 case ISD::SETOLE: Other = 0; return 2; // SETOLT | SETOEQ
651 case ISD::SETONE: Other = 0; return 1; // SETOLT | SETOGT
656 SDNode *PPCDAGToDAGISel::SelectSETCC(SDOperand Op) {
659 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
660 if (isInt32Immediate(N->getOperand(1), Imm)) {
661 // We can codegen setcc op, imm very efficiently compared to a brcond.
662 // Check for those cases here.
665 SDOperand Op = N->getOperand(0);
670 Op = SDOperand(CurDAG->getTargetNode(PPC::CNTLZW, MVT::i32, Op), 0);
671 SDOperand Ops[] = { Op, getI32Imm(27), getI32Imm(5), getI32Imm(31) };
672 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
676 SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
677 Op, getI32Imm(~0U)), 0);
678 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, AD, Op,
682 SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
683 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
687 SDOperand(CurDAG->getTargetNode(PPC::NEG, MVT::i32, Op), 0);
688 T = SDOperand(CurDAG->getTargetNode(PPC::ANDC, MVT::i32, T, Op), 0);
689 SDOperand Ops[] = { T, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
690 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
693 } else if (Imm == ~0U) { // setcc op, -1
694 SDOperand Op = N->getOperand(0);
699 Op = SDOperand(CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
700 Op, getI32Imm(1)), 0);
701 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
702 SDOperand(CurDAG->getTargetNode(PPC::LI, MVT::i32,
706 Op = SDOperand(CurDAG->getTargetNode(PPC::NOR, MVT::i32, Op, Op), 0);
707 SDNode *AD = CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
709 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32, SDOperand(AD, 0),
710 Op, SDOperand(AD, 1));
713 SDOperand AD = SDOperand(CurDAG->getTargetNode(PPC::ADDI, MVT::i32, Op,
715 SDOperand AN = SDOperand(CurDAG->getTargetNode(PPC::AND, MVT::i32, AD,
717 SDOperand Ops[] = { AN, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
718 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
721 SDOperand Ops[] = { Op, getI32Imm(1), getI32Imm(31), getI32Imm(31) };
722 Op = SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
723 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Op,
732 unsigned Idx = getCRIdxForSetCC(CC, Inv, OtherCondIdx);
733 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
736 // Force the ccreg into CR7.
737 SDOperand CR7Reg = CurDAG->getRegister(PPC::CR7, MVT::i32);
739 SDOperand InFlag(0, 0); // Null incoming flag value.
740 CCReg = CurDAG->getCopyToReg(CurDAG->getEntryNode(), CR7Reg, CCReg,
743 if (PPCSubTarget.isGigaProcessor() && OtherCondIdx == -1)
744 IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32, CR7Reg,
747 IntCR = SDOperand(CurDAG->getTargetNode(PPC::MFCR, MVT::i32, CCReg), 0);
749 SDOperand Ops[] = { IntCR, getI32Imm((32-(3-Idx)) & 31),
750 getI32Imm(31), getI32Imm(31) };
751 if (OtherCondIdx == -1 && !Inv)
752 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
754 // Get the specified bit.
756 SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
758 assert(OtherCondIdx == -1 && "Can't have split plus negation");
759 return CurDAG->SelectNodeTo(N, PPC::XORI, MVT::i32, Tmp, getI32Imm(1));
762 // Otherwise, we have to turn an operation like SETONE -> SETOLT | SETOGT.
763 // We already got the bit for the first part of the comparison (e.g. SETULE).
765 // Get the other bit of the comparison.
766 Ops[1] = getI32Imm((32-(3-OtherCondIdx)) & 31);
767 SDOperand OtherCond =
768 SDOperand(CurDAG->getTargetNode(PPC::RLWINM, MVT::i32, Ops, 4), 0);
770 return CurDAG->SelectNodeTo(N, PPC::OR, MVT::i32, Tmp, OtherCond);
774 // Select - Convert the specified operand from a target-independent to a
775 // target-specific node if it hasn't already been changed.
776 SDNode *PPCDAGToDAGISel::Select(SDOperand Op) {
778 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
779 N->getOpcode() < PPCISD::FIRST_NUMBER)
780 return NULL; // Already selected.
782 switch (N->getOpcode()) {
785 case ISD::Constant: {
786 if (N->getValueType(0) == MVT::i64) {
788 int64_t Imm = cast<ConstantSDNode>(N)->getValue();
789 // Assume no remaining bits.
790 unsigned Remainder = 0;
791 // Assume no shift required.
794 // If it can't be represented as a 32 bit value.
796 Shift = CountTrailingZeros_64(Imm);
797 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
799 // If the shifted value fits 32 bits.
800 if (isInt32(ImmSh)) {
801 // Go with the shifted value.
804 // Still stuck with a 64 bit value.
811 // Intermediate operand.
814 // Handle first 32 bits.
815 unsigned Lo = Imm & 0xFFFF;
816 unsigned Hi = (Imm >> 16) & 0xFFFF;
821 Result = CurDAG->getTargetNode(PPC::LI8, MVT::i64, getI32Imm(Lo));
823 // Handle the Hi bits.
824 unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
825 Result = CurDAG->getTargetNode(OpC, MVT::i64, getI32Imm(Hi));
827 Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64,
828 SDOperand(Result, 0), getI32Imm(Lo));
831 Result = CurDAG->getTargetNode(PPC::LIS8, MVT::i64, getI32Imm(Hi));
834 // If no shift, we're done.
835 if (!Shift) return Result;
837 // Shift for next step if the upper 32-bits were not zero.
839 Result = CurDAG->getTargetNode(PPC::RLDICR, MVT::i64,
840 SDOperand(Result, 0),
841 getI32Imm(Shift), getI32Imm(63 - Shift));
844 // Add in the last bits as required.
845 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
846 Result = CurDAG->getTargetNode(PPC::ORIS8, MVT::i64,
847 SDOperand(Result, 0), getI32Imm(Hi));
849 if ((Lo = Remainder & 0xFFFF)) {
850 Result = CurDAG->getTargetNode(PPC::ORI8, MVT::i64,
851 SDOperand(Result, 0), getI32Imm(Lo));
860 return SelectSETCC(Op);
861 case PPCISD::GlobalBaseReg:
862 return getGlobalBaseReg();
864 case ISD::FrameIndex: {
865 int FI = cast<FrameIndexSDNode>(N)->getIndex();
866 SDOperand TFI = CurDAG->getTargetFrameIndex(FI, Op.getValueType());
867 unsigned Opc = Op.getValueType() == MVT::i32 ? PPC::ADDI : PPC::ADDI8;
869 return CurDAG->SelectNodeTo(N, Opc, Op.getValueType(), TFI,
871 return CurDAG->getTargetNode(Opc, Op.getValueType(), TFI,
876 SDOperand InFlag = N->getOperand(1);
877 AddToISelQueue(InFlag);
878 // Use MFOCRF if supported.
879 if (PPCSubTarget.isGigaProcessor())
880 return CurDAG->getTargetNode(PPC::MFOCRF, MVT::i32,
881 N->getOperand(0), InFlag);
883 return CurDAG->getTargetNode(PPC::MFCR, MVT::i32, InFlag);
887 // FIXME: since this depends on the setting of the carry flag from the srawi
888 // we should really be making notes about that for the scheduler.
889 // FIXME: It sure would be nice if we could cheaply recognize the
890 // srl/add/sra pattern the dag combiner will generate for this as
891 // sra/addze rather than having to handle sdiv ourselves. oh well.
893 if (isInt32Immediate(N->getOperand(1), Imm)) {
894 SDOperand N0 = N->getOperand(0);
896 if ((signed)Imm > 0 && isPowerOf2_32(Imm)) {
898 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
899 N0, getI32Imm(Log2_32(Imm)));
900 return CurDAG->SelectNodeTo(N, PPC::ADDZE, MVT::i32,
901 SDOperand(Op, 0), SDOperand(Op, 1));
902 } else if ((signed)Imm < 0 && isPowerOf2_32(-Imm)) {
904 CurDAG->getTargetNode(PPC::SRAWI, MVT::i32, MVT::Flag,
905 N0, getI32Imm(Log2_32(-Imm)));
907 SDOperand(CurDAG->getTargetNode(PPC::ADDZE, MVT::i32,
908 SDOperand(Op, 0), SDOperand(Op, 1)),
910 return CurDAG->SelectNodeTo(N, PPC::NEG, MVT::i32, PT);
914 // Other cases are autogenerated.
919 // Handle preincrement loads.
920 LoadSDNode *LD = cast<LoadSDNode>(Op);
921 MVT LoadedVT = LD->getMemoryVT();
923 // Normal loads are handled by code generated from the .td file.
924 if (LD->getAddressingMode() != ISD::PRE_INC)
927 SDOperand Offset = LD->getOffset();
928 if (isa<ConstantSDNode>(Offset) ||
929 Offset.getOpcode() == ISD::TargetGlobalAddress) {
932 bool isSExt = LD->getExtensionType() == ISD::SEXTLOAD;
933 if (LD->getValueType(0) != MVT::i64) {
934 // Handle PPC32 integer and normal FP loads.
935 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
936 switch (LoadedVT.getSimpleVT()) {
937 default: assert(0 && "Invalid PPC load type!");
938 case MVT::f64: Opcode = PPC::LFDU; break;
939 case MVT::f32: Opcode = PPC::LFSU; break;
940 case MVT::i32: Opcode = PPC::LWZU; break;
941 case MVT::i16: Opcode = isSExt ? PPC::LHAU : PPC::LHZU; break;
943 case MVT::i8: Opcode = PPC::LBZU; break;
946 assert(LD->getValueType(0) == MVT::i64 && "Unknown load result type!");
947 assert((!isSExt || LoadedVT == MVT::i16) && "Invalid sext update load");
948 switch (LoadedVT.getSimpleVT()) {
949 default: assert(0 && "Invalid PPC load type!");
950 case MVT::i64: Opcode = PPC::LDU; break;
951 case MVT::i32: Opcode = PPC::LWZU8; break;
952 case MVT::i16: Opcode = isSExt ? PPC::LHAU8 : PPC::LHZU8; break;
954 case MVT::i8: Opcode = PPC::LBZU8; break;
958 SDOperand Chain = LD->getChain();
959 SDOperand Base = LD->getBasePtr();
960 AddToISelQueue(Chain);
961 AddToISelQueue(Base);
962 AddToISelQueue(Offset);
963 SDOperand Ops[] = { Offset, Base, Chain };
965 return CurDAG->getTargetNode(Opcode, MVT::i32, MVT::i32,
968 assert(0 && "R+R preindex loads not supported yet!");
973 unsigned Imm, Imm2, SH, MB, ME;
975 // If this is an and of a value rotated between 0 and 31 bits and then and'd
976 // with a mask, emit rlwinm
977 if (isInt32Immediate(N->getOperand(1), Imm) &&
978 isRotateAndMask(N->getOperand(0).Val, Imm, false, SH, MB, ME)) {
979 SDOperand Val = N->getOperand(0).getOperand(0);
981 SDOperand Ops[] = { Val, getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
982 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
984 // If this is just a masked value where the input is not handled above, and
985 // is not a rotate-left (handled by a pattern in the .td file), emit rlwinm
986 if (isInt32Immediate(N->getOperand(1), Imm) &&
987 isRunOfOnes(Imm, MB, ME) &&
988 N->getOperand(0).getOpcode() != ISD::ROTL) {
989 SDOperand Val = N->getOperand(0);
991 SDOperand Ops[] = { Val, getI32Imm(0), getI32Imm(MB), getI32Imm(ME) };
992 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
994 // AND X, 0 -> 0, not "rlwinm 32".
995 if (isInt32Immediate(N->getOperand(1), Imm) && (Imm == 0)) {
996 AddToISelQueue(N->getOperand(1));
997 ReplaceUses(SDOperand(N, 0), N->getOperand(1));
1000 // ISD::OR doesn't get all the bitfield insertion fun.
1001 // (and (or x, c1), c2) where isRunOfOnes(~(c1^c2)) is a bitfield insert
1002 if (isInt32Immediate(N->getOperand(1), Imm) &&
1003 N->getOperand(0).getOpcode() == ISD::OR &&
1004 isInt32Immediate(N->getOperand(0).getOperand(1), Imm2)) {
1007 if (isRunOfOnes(Imm, MB, ME)) {
1008 AddToISelQueue(N->getOperand(0).getOperand(0));
1009 AddToISelQueue(N->getOperand(0).getOperand(1));
1010 SDOperand Ops[] = { N->getOperand(0).getOperand(0),
1011 N->getOperand(0).getOperand(1),
1012 getI32Imm(0), getI32Imm(MB),getI32Imm(ME) };
1013 return CurDAG->getTargetNode(PPC::RLWIMI, MVT::i32, Ops, 5);
1017 // Other cases are autogenerated.
1021 if (N->getValueType(0) == MVT::i32)
1022 if (SDNode *I = SelectBitfieldInsert(N))
1025 // Other cases are autogenerated.
1028 unsigned Imm, SH, MB, ME;
1029 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1030 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1031 AddToISelQueue(N->getOperand(0).getOperand(0));
1032 SDOperand Ops[] = { N->getOperand(0).getOperand(0),
1033 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1034 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1037 // Other cases are autogenerated.
1041 unsigned Imm, SH, MB, ME;
1042 if (isOpcWithIntImmediate(N->getOperand(0).Val, ISD::AND, Imm) &&
1043 isRotateAndMask(N, Imm, true, SH, MB, ME)) {
1044 AddToISelQueue(N->getOperand(0).getOperand(0));
1045 SDOperand Ops[] = { N->getOperand(0).getOperand(0),
1046 getI32Imm(SH), getI32Imm(MB), getI32Imm(ME) };
1047 return CurDAG->SelectNodeTo(N, PPC::RLWINM, MVT::i32, Ops, 4);
1050 // Other cases are autogenerated.
1053 case ISD::SELECT_CC: {
1054 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get();
1056 // Handle the setcc cases here. select_cc lhs, 0, 1, 0, cc
1057 if (ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
1058 if (ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N->getOperand(2)))
1059 if (ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N->getOperand(3)))
1060 if (N1C->isNullValue() && N3C->isNullValue() &&
1061 N2C->getValue() == 1ULL && CC == ISD::SETNE &&
1062 // FIXME: Implement this optzn for PPC64.
1063 N->getValueType(0) == MVT::i32) {
1064 AddToISelQueue(N->getOperand(0));
1066 CurDAG->getTargetNode(PPC::ADDIC, MVT::i32, MVT::Flag,
1067 N->getOperand(0), getI32Imm(~0U));
1068 return CurDAG->SelectNodeTo(N, PPC::SUBFE, MVT::i32,
1069 SDOperand(Tmp, 0), N->getOperand(0),
1073 SDOperand CCReg = SelectCC(N->getOperand(0), N->getOperand(1), CC);
1074 unsigned BROpc = getPredicateForSetCC(CC);
1076 unsigned SelectCCOp;
1077 if (N->getValueType(0) == MVT::i32)
1078 SelectCCOp = PPC::SELECT_CC_I4;
1079 else if (N->getValueType(0) == MVT::i64)
1080 SelectCCOp = PPC::SELECT_CC_I8;
1081 else if (N->getValueType(0) == MVT::f32)
1082 SelectCCOp = PPC::SELECT_CC_F4;
1083 else if (N->getValueType(0) == MVT::f64)
1084 SelectCCOp = PPC::SELECT_CC_F8;
1086 SelectCCOp = PPC::SELECT_CC_VRRC;
1088 AddToISelQueue(N->getOperand(2));
1089 AddToISelQueue(N->getOperand(3));
1090 SDOperand Ops[] = { CCReg, N->getOperand(2), N->getOperand(3),
1092 return CurDAG->SelectNodeTo(N, SelectCCOp, N->getValueType(0), Ops, 4);
1094 case PPCISD::COND_BRANCH: {
1095 AddToISelQueue(N->getOperand(0)); // Op #0 is the Chain.
1096 // Op #1 is the PPC::PRED_* number.
1098 // Op #3 is the Dest MBB
1099 AddToISelQueue(N->getOperand(4)); // Op #4 is the Flag.
1100 // Prevent PPC::PRED_* from being selected into LI.
1102 getI32Imm(cast<ConstantSDNode>(N->getOperand(1))->getValue());
1103 SDOperand Ops[] = { Pred, N->getOperand(2), N->getOperand(3),
1104 N->getOperand(0), N->getOperand(4) };
1105 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 5);
1108 AddToISelQueue(N->getOperand(0));
1109 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
1110 SDOperand CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC);
1111 SDOperand Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode,
1112 N->getOperand(4), N->getOperand(0) };
1113 return CurDAG->SelectNodeTo(N, PPC::BCC, MVT::Other, Ops, 4);
1116 // FIXME: Should custom lower this.
1117 SDOperand Chain = N->getOperand(0);
1118 SDOperand Target = N->getOperand(1);
1119 AddToISelQueue(Chain);
1120 AddToISelQueue(Target);
1121 unsigned Opc = Target.getValueType() == MVT::i32 ? PPC::MTCTR : PPC::MTCTR8;
1122 Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Target,
1124 return CurDAG->SelectNodeTo(N, PPC::BCTR, MVT::Other, Chain);
1128 return SelectCode(Op);
1133 /// createPPCISelDag - This pass converts a legalized DAG into a
1134 /// PowerPC-specific DAG, ready for instruction scheduling.
1136 FunctionPass *llvm::createPPCISelDag(PPCTargetMachine &TM) {
1137 return new PPCDAGToDAGISel(TM);