1 //===-- PPCHazardRecognizers.cpp - PowerPC Hazard Recognizer Impls --------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements hazard recognizers for scheduling on PowerPC processors.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "sched"
15 #include "PPCHazardRecognizers.h"
17 #include "PPCInstrInfo.h"
18 #include "llvm/Support/Debug.h"
23 //===----------------------------------------------------------------------===//
24 // PowerPC 970 Hazard Recognizer
26 // This models the dispatch group formation of the PPC970 processor. Dispatch
27 // groups are bundles of up to five instructions that can contain various mixes
28 // of instructions. The PPC970 can dispatch a peak of 4 non-branch and one
29 // branch instruction per-cycle.
31 // There are a number of restrictions to dispatch group formation: some
32 // instructions can only be issued in the first slot of a dispatch group, & some
33 // instructions fill an entire dispatch group. Additionally, only branches can
34 // issue in the 5th (last) slot.
36 // Finally, there are a number of "structural" hazards on the PPC970. These
37 // conditions cause large performance penalties due to misprediction, recovery,
38 // and replay logic that has to happen. These cases include setting a CTR and
39 // branching through it in the same dispatch group, and storing to an address,
40 // then loading from the same address within a dispatch group. To avoid these
41 // conditions, we insert no-op instructions when appropriate.
43 // FIXME: This is missing some significant cases:
44 // 1. Modeling of microcoded instructions.
45 // 2. Handling of cracked instructions.
46 // 3. Handling of serialized operations.
47 // 4. Handling of the esoteric cases in "Resource-based Instruction Grouping",
48 // e.g. integer divides that only execute in the second slot.
51 PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii)
56 void PPCHazardRecognizer970::EndDispatchGroup() {
57 DEBUG(std::cerr << "=== Start of dispatch group\n");
60 // Structural hazard info.
67 PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
68 bool &isFirst, bool &isSingle,
69 bool &isLoad, bool &isStore){
70 if (Opcode < ISD::BUILTIN_OP_END) {
71 isFirst = isSingle = isLoad = isStore = false;
72 return PPCII::PPC970_Pseudo;
74 Opcode -= ISD::BUILTIN_OP_END;
76 const TargetInstrDescriptor &TID = TII.get(Opcode);
78 isLoad = TID.Flags & M_LOAD_FLAG;
79 isStore = TID.Flags & M_STORE_FLAG;
81 unsigned TSFlags = TID.TSFlags;
83 isFirst = TSFlags & PPCII::PPC970_First;
84 isSingle = TSFlags & PPCII::PPC970_Single;
85 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
88 /// isLoadOfStoredAddress - If we have a load from the previously stored pointer
89 /// as indicated by StorePtr1/StorePtr2/StoreSize, return true.
90 bool PPCHazardRecognizer970::
91 isLoadOfStoredAddress(unsigned LoadSize, SDOperand Ptr1, SDOperand Ptr2) const {
92 for (unsigned i = 0, e = NumStores; i != e; ++i) {
93 // Handle exact and commuted addresses.
94 if (Ptr1 == StorePtr1[i] && Ptr2 == StorePtr2[i])
96 if (Ptr2 == StorePtr1[i] && Ptr1 == StorePtr2[i])
99 // Okay, we don't have an exact match, if this is an indexed offset, see if
100 // we have overlap (which happens during fp->int conversion for example).
101 if (StorePtr2[i] == Ptr2) {
102 if (ConstantSDNode *StoreOffset = dyn_cast<ConstantSDNode>(StorePtr1[i]))
103 if (ConstantSDNode *LoadOffset = dyn_cast<ConstantSDNode>(Ptr1)) {
104 // Okay the base pointers match, so we have [c1+r] vs [c2+r]. Check
105 // to see if the load and store actually overlap.
106 int StoreOffs = StoreOffset->getValue();
107 int LoadOffs = LoadOffset->getValue();
108 if (StoreOffs < LoadOffs) {
109 if (int(StoreOffs+StoreSize) > LoadOffs) return true;
111 if (int(LoadOffs+LoadSize) > StoreOffs) return true;
119 /// getHazardType - We return hazard for any non-branch instruction that would
120 /// terminate terminate the dispatch group. We turn NoopHazard for any
121 /// instructions that wouldn't terminate the dispatch group that would cause a
123 HazardRecognizer::HazardType PPCHazardRecognizer970::
124 getHazardType(SDNode *Node) {
125 bool isFirst, isSingle, isLoad, isStore;
126 PPCII::PPC970_Unit InstrType =
127 GetInstrType(Node->getOpcode(), isFirst, isSingle, isLoad, isStore);
128 if (InstrType == PPCII::PPC970_Pseudo) return NoHazard;
129 unsigned Opcode = Node->getOpcode()-ISD::BUILTIN_OP_END;
131 // We can only issue a PPC970_First/PPC970_Single instruction (such as
132 // crand/mtspr/etc) if this is the first cycle of the dispatch group.
133 if (NumIssued != 0 && (isFirst || isSingle) )
137 default: assert(0 && "Unknown instruction type!");
138 case PPCII::PPC970_FXU:
139 case PPCII::PPC970_LSU:
140 case PPCII::PPC970_FPU:
141 case PPCII::PPC970_VALU:
142 case PPCII::PPC970_VPERM:
143 // We can only issue a branch as the last instruction in a group.
144 if (NumIssued == 4) return Hazard;
146 case PPCII::PPC970_CRU:
147 // We can only issue a CR instruction in the first two slots.
148 if (NumIssued >= 2) return Hazard;
150 case PPCII::PPC970_BRU:
154 // Do not allow MTCTR and BCTRL to be in the same dispatch group.
155 if (HasCTRSet && Opcode == PPC::BCTRL)
158 // If this is a load following a store, make sure it's not to the same or
159 // overlapping address.
160 if (isLoad && StoreSize) {
163 default: assert(0 && "Unknown load!");
197 if (isLoadOfStoredAddress(LoadSize,
198 Node->getOperand(0), Node->getOperand(1)))
205 void PPCHazardRecognizer970::EmitInstruction(SDNode *Node) {
206 bool isFirst, isSingle, isLoad, isStore;
207 PPCII::PPC970_Unit InstrType =
208 GetInstrType(Node->getOpcode(), isFirst, isSingle, isLoad, isStore);
209 if (InstrType == PPCII::PPC970_Pseudo) return;
210 unsigned Opcode = Node->getOpcode()-ISD::BUILTIN_OP_END;
212 // Update structural hazard information.
213 if (Opcode == PPC::MTCTR) HasCTRSet = true;
215 // Track the address stored to.
217 unsigned ThisStoreSize;
219 default: assert(0 && "Unknown store instruction!");
253 StoreSize[NumStores] = ThisStoreSize;
254 StorePtr1[NumStores] = Node->getOperand(1);
255 StorePtr2[NumStores] = Node->getOperand(2);
259 if (InstrType == PPCII::PPC970_BRU || isSingle)
260 NumIssued = 4; // Terminate a d-group.
267 void PPCHazardRecognizer970::AdvanceCycle() {
268 assert(NumIssued < 5 && "Illegal dispatch group!");
274 void PPCHazardRecognizer970::EmitNoop() {