1 //===-- PPCHazardRecognizers.cpp - PowerPC Hazard Recognizer Impls --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements hazard recognizers for scheduling on PowerPC processors.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "pre-RA-sched"
15 #include "PPCHazardRecognizers.h"
17 #include "PPCInstrInfo.h"
18 #include "llvm/CodeGen/ScheduleDAG.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/raw_ostream.h"
24 //===----------------------------------------------------------------------===//
25 // PowerPC 440 Hazard Recognizer
26 void PPCHazardRecognizer440::EmitInstruction(SUnit *SU) {
27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
29 // This is a PPC pseudo-instruction.
33 ScoreboardHazardRecognizer::EmitInstruction(SU);
36 //===----------------------------------------------------------------------===//
37 // PowerPC 970 Hazard Recognizer
39 // This models the dispatch group formation of the PPC970 processor. Dispatch
40 // groups are bundles of up to five instructions that can contain various mixes
41 // of instructions. The PPC970 can dispatch a peak of 4 non-branch and one
42 // branch instruction per-cycle.
44 // There are a number of restrictions to dispatch group formation: some
45 // instructions can only be issued in the first slot of a dispatch group, & some
46 // instructions fill an entire dispatch group. Additionally, only branches can
47 // issue in the 5th (last) slot.
49 // Finally, there are a number of "structural" hazards on the PPC970. These
50 // conditions cause large performance penalties due to misprediction, recovery,
51 // and replay logic that has to happen. These cases include setting a CTR and
52 // branching through it in the same dispatch group, and storing to an address,
53 // then loading from the same address within a dispatch group. To avoid these
54 // conditions, we insert no-op instructions when appropriate.
56 // FIXME: This is missing some significant cases:
57 // 1. Modeling of microcoded instructions.
58 // 2. Handling of serialized operations.
59 // 3. Handling of the esoteric cases in "Resource-based Instruction Grouping".
62 PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetInstrInfo &tii)
64 LastWasBL8_ELF = false;
68 void PPCHazardRecognizer970::EndDispatchGroup() {
69 DEBUG(errs() << "=== Start of dispatch group\n");
72 // Structural hazard info.
79 PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
80 bool &isFirst, bool &isSingle,
82 bool &isLoad, bool &isStore) {
83 const MCInstrDesc &MCID = TII.get(Opcode);
85 isLoad = MCID.mayLoad();
86 isStore = MCID.mayStore();
88 uint64_t TSFlags = MCID.TSFlags;
90 isFirst = TSFlags & PPCII::PPC970_First;
91 isSingle = TSFlags & PPCII::PPC970_Single;
92 isCracked = TSFlags & PPCII::PPC970_Cracked;
93 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
96 /// isLoadOfStoredAddress - If we have a load from the previously stored pointer
97 /// as indicated by StorePtr1/StorePtr2/StoreSize, return true.
98 bool PPCHazardRecognizer970::
99 isLoadOfStoredAddress(uint64_t LoadSize, int64_t LoadOffset,
100 const Value *LoadValue) const {
101 for (unsigned i = 0, e = NumStores; i != e; ++i) {
102 // Handle exact and commuted addresses.
103 if (LoadValue == StoreValue[i] && LoadOffset == StoreOffset[i])
106 // Okay, we don't have an exact match, if this is an indexed offset, see if
107 // we have overlap (which happens during fp->int conversion for example).
108 if (StoreValue[i] == LoadValue) {
109 // Okay the base pointers match, so we have [c1+r] vs [c2+r]. Check
110 // to see if the load and store actually overlap.
111 if (StoreOffset[i] < LoadOffset) {
112 if (int64_t(StoreOffset[i]+StoreSize[i]) > LoadOffset) return true;
114 if (int64_t(LoadOffset+LoadSize) > StoreOffset[i]) return true;
121 /// getHazardType - We return hazard for any non-branch instruction that would
122 /// terminate the dispatch group. We turn NoopHazard for any
123 /// instructions that wouldn't terminate the dispatch group that would cause a
125 ScheduleHazardRecognizer::HazardType PPCHazardRecognizer970::
126 getHazardType(SUnit *SU, int Stalls) {
127 assert(Stalls == 0 && "PPC hazards don't support scoreboard lookahead");
129 MachineInstr *MI = SU->getInstr();
131 if (MI->isDebugValue())
134 unsigned Opcode = MI->getOpcode();
136 // If the last instruction was a BL8_ELF, then the NOP must follow it
137 // directly (this is strong requirement from the linker due to the ELF ABI).
138 // We return only Hazard (and not NoopHazard) because if the NOP is necessary
139 // then it will already be in the instruction stream (it is not always
140 // necessary; tail calls, for example, do not need it).
141 if (LastWasBL8_ELF && Opcode != PPC::NOP)
144 bool isFirst, isSingle, isCracked, isLoad, isStore;
145 PPCII::PPC970_Unit InstrType =
146 GetInstrType(Opcode, isFirst, isSingle, isCracked,
148 if (InstrType == PPCII::PPC970_Pseudo) return NoHazard;
150 // We can only issue a PPC970_First/PPC970_Single instruction (such as
151 // crand/mtspr/etc) if this is the first cycle of the dispatch group.
152 if (NumIssued != 0 && (isFirst || isSingle))
155 // If this instruction is cracked into two ops by the decoder, we know that
156 // it is not a branch and that it cannot issue if 3 other instructions are
157 // already in the dispatch group.
158 if (isCracked && NumIssued > 2)
162 default: llvm_unreachable("Unknown instruction type!");
163 case PPCII::PPC970_FXU:
164 case PPCII::PPC970_LSU:
165 case PPCII::PPC970_FPU:
166 case PPCII::PPC970_VALU:
167 case PPCII::PPC970_VPERM:
168 // We can only issue a branch as the last instruction in a group.
169 if (NumIssued == 4) return Hazard;
171 case PPCII::PPC970_CRU:
172 // We can only issue a CR instruction in the first two slots.
173 if (NumIssued >= 2) return Hazard;
175 case PPCII::PPC970_BRU:
179 // Do not allow MTCTR and BCTRL to be in the same dispatch group.
180 if (HasCTRSet && (Opcode == PPC::BCTRL_Darwin || Opcode == PPC::BCTRL_SVR4))
183 // If this is a load following a store, make sure it's not to the same or
184 // overlapping address.
185 if (isLoad && NumStores && !MI->memoperands_empty()) {
186 MachineMemOperand *MO = *MI->memoperands_begin();
187 if (isLoadOfStoredAddress(MO->getSize(),
188 MO->getOffset(), MO->getValue()))
195 void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) {
196 MachineInstr *MI = SU->getInstr();
198 if (MI->isDebugValue())
201 unsigned Opcode = MI->getOpcode();
202 LastWasBL8_ELF = (Opcode == PPC::BL8_ELF);
204 bool isFirst, isSingle, isCracked, isLoad, isStore;
205 PPCII::PPC970_Unit InstrType =
206 GetInstrType(Opcode, isFirst, isSingle, isCracked,
208 if (InstrType == PPCII::PPC970_Pseudo) return;
210 // Update structural hazard information.
211 if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true;
213 // Track the address stored to.
214 if (isStore && NumStores < 4 && !MI->memoperands_empty()) {
215 MachineMemOperand *MO = *MI->memoperands_begin();
216 StoreSize[NumStores] = MO->getSize();
217 StoreOffset[NumStores] = MO->getOffset();
218 StoreValue[NumStores] = MO->getValue();
222 if (InstrType == PPCII::PPC970_BRU || isSingle)
223 NumIssued = 4; // Terminate a d-group.
226 // If this instruction is cracked into two ops by the decoder, remember that
227 // we issued two pieces.
235 void PPCHazardRecognizer970::AdvanceCycle() {
236 assert(NumIssued < 5 && "Illegal dispatch group!");
242 void PPCHazardRecognizer970::Reset() {
243 LastWasBL8_ELF = false;