1 //===-- PPCHazardRecognizers.cpp - PowerPC Hazard Recognizer Impls --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements hazard recognizers for scheduling on PowerPC processors.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "pre-RA-sched"
15 #include "PPCHazardRecognizers.h"
17 #include "PPCInstrInfo.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/CodeGen/ScheduleDAG.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/raw_ostream.h"
25 bool PPCDispatchGroupSBHazardRecognizer::isLoadAfterStore(SUnit *SU) {
27 if (isBCTRAfterSet(SU))
30 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
37 // SU is a load; for any predecessors in this dispatch group, that are stores,
38 // and with which we have an ordering dependency, return true.
39 for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) {
40 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
41 if (!PredMCID || !PredMCID->mayStore())
44 if (!SU->Preds[i].isNormalMemory() && !SU->Preds[i].isBarrier())
47 for (unsigned j = 0, je = CurGroup.size(); j != je; ++j)
48 if (SU->Preds[i].getSUnit() == CurGroup[j])
55 bool PPCDispatchGroupSBHazardRecognizer::isBCTRAfterSet(SUnit *SU) {
56 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
60 if (!MCID->isBranch())
63 // SU is a branch; for any predecessors in this dispatch group, with which we
64 // have a data dependence and set the counter register, return true.
65 for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) {
66 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
67 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR)
70 if (SU->Preds[i].isCtrl())
73 for (unsigned j = 0, je = CurGroup.size(); j != je; ++j)
74 if (SU->Preds[i].getSUnit() == CurGroup[j])
81 // FIXME: Remove this when we don't need this:
82 namespace llvm { namespace PPC { extern int getNonRecordFormOpcode(uint16_t); } }
84 // FIXME: A lot of code in PPCDispatchGroupSBHazardRecognizer is P7 specific.
86 bool PPCDispatchGroupSBHazardRecognizer::mustComeFirst(const MCInstrDesc *MCID,
88 // FIXME: Indirectly, this information is contained in the itinerary, and
89 // we should derive it from there instead of separately specifying it
91 unsigned IIC = MCID->getSchedClass();
96 case PPC::Sched::IIC_IntDivW:
97 case PPC::Sched::IIC_IntDivD:
98 case PPC::Sched::IIC_LdStLoadUpd:
99 case PPC::Sched::IIC_LdStLDU:
100 case PPC::Sched::IIC_LdStLFDU:
101 case PPC::Sched::IIC_LdStLFDUX:
102 case PPC::Sched::IIC_LdStLHA:
103 case PPC::Sched::IIC_LdStLHAU:
104 case PPC::Sched::IIC_LdStLWA:
105 case PPC::Sched::IIC_LdStSTDU:
106 case PPC::Sched::IIC_LdStSTFDU:
109 case PPC::Sched::IIC_LdStLoadUpdX:
110 case PPC::Sched::IIC_LdStLDUX:
111 case PPC::Sched::IIC_LdStLHAUX:
112 case PPC::Sched::IIC_LdStLWARX:
113 case PPC::Sched::IIC_LdStLDARX:
114 case PPC::Sched::IIC_LdStSTDUX:
115 case PPC::Sched::IIC_LdStSTDCX:
116 case PPC::Sched::IIC_LdStSTWCX:
117 case PPC::Sched::IIC_BrMCRX: // mtcr
118 // FIXME: Add sync/isync (here and in the itinerary).
123 // FIXME: record-form instructions need a different itinerary class.
124 if (NSlots == 1 && PPC::getNonRecordFormOpcode(MCID->getOpcode()) != -1)
129 // All multi-slot instructions must come first.
131 case PPC::Sched::IIC_BrCR: // cr logicals
132 case PPC::Sched::IIC_SprMFCR:
133 case PPC::Sched::IIC_SprMFCRF:
134 case PPC::Sched::IIC_SprMTSPR:
139 ScheduleHazardRecognizer::HazardType
140 PPCDispatchGroupSBHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
141 if (Stalls == 0 && isLoadAfterStore(SU))
144 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
147 bool PPCDispatchGroupSBHazardRecognizer::ShouldPreferAnother(SUnit *SU) {
148 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
150 if (MCID && mustComeFirst(MCID, NSlots) && CurSlots)
153 return ScoreboardHazardRecognizer::ShouldPreferAnother(SU);
156 unsigned PPCDispatchGroupSBHazardRecognizer::PreEmitNoops(SUnit *SU) {
157 // We only need to fill out a maximum of 5 slots here: The 6th slot could
158 // only be a second branch, and otherwise the next instruction will start a
160 if (isLoadAfterStore(SU) && CurSlots < 6) {
162 DAG->TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
163 // If we're using a special group-terminating nop, then we need only one.
164 if (Directive == PPC::DIR_PWR6 || Directive == PPC::DIR_PWR7)
170 return ScoreboardHazardRecognizer::PreEmitNoops(SU);
173 void PPCDispatchGroupSBHazardRecognizer::EmitInstruction(SUnit *SU) {
174 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
176 if (CurSlots == 5 || (MCID->isBranch() && CurBranches == 1)) {
178 CurSlots = CurBranches = 0;
180 DEBUG(dbgs() << "**** Adding to dispatch group: SU(" <<
181 SU->NodeNum << "): ");
182 DEBUG(DAG->dumpNode(SU));
185 bool MustBeFirst = mustComeFirst(MCID, NSlots);
187 // If this instruction must come first, but does not, then it starts a
189 if (MustBeFirst && CurSlots) {
190 CurSlots = CurBranches = 0;
195 CurGroup.push_back(SU);
197 if (MCID->isBranch())
202 return ScoreboardHazardRecognizer::EmitInstruction(SU);
205 void PPCDispatchGroupSBHazardRecognizer::AdvanceCycle() {
206 return ScoreboardHazardRecognizer::AdvanceCycle();
209 void PPCDispatchGroupSBHazardRecognizer::RecedeCycle() {
210 llvm_unreachable("Bottom-up scheduling not supported");
213 void PPCDispatchGroupSBHazardRecognizer::Reset() {
215 CurSlots = CurBranches = 0;
216 return ScoreboardHazardRecognizer::Reset();
219 void PPCDispatchGroupSBHazardRecognizer::EmitNoop() {
221 DAG->TM.getSubtarget<PPCSubtarget>().getDarwinDirective();
222 // If the group has now filled all of its slots, or if we're using a special
223 // group-terminating nop, the group is complete.
224 if (Directive == PPC::DIR_PWR6 || Directive == PPC::DIR_PWR7 ||
227 CurSlots = CurBranches = 0;
229 CurGroup.push_back(0);
234 //===----------------------------------------------------------------------===//
235 // PowerPC 970 Hazard Recognizer
237 // This models the dispatch group formation of the PPC970 processor. Dispatch
238 // groups are bundles of up to five instructions that can contain various mixes
239 // of instructions. The PPC970 can dispatch a peak of 4 non-branch and one
240 // branch instruction per-cycle.
242 // There are a number of restrictions to dispatch group formation: some
243 // instructions can only be issued in the first slot of a dispatch group, & some
244 // instructions fill an entire dispatch group. Additionally, only branches can
245 // issue in the 5th (last) slot.
247 // Finally, there are a number of "structural" hazards on the PPC970. These
248 // conditions cause large performance penalties due to misprediction, recovery,
249 // and replay logic that has to happen. These cases include setting a CTR and
250 // branching through it in the same dispatch group, and storing to an address,
251 // then loading from the same address within a dispatch group. To avoid these
252 // conditions, we insert no-op instructions when appropriate.
254 // FIXME: This is missing some significant cases:
255 // 1. Modeling of microcoded instructions.
256 // 2. Handling of serialized operations.
257 // 3. Handling of the esoteric cases in "Resource-based Instruction Grouping".
260 PPCHazardRecognizer970::PPCHazardRecognizer970(const TargetMachine &TM)
265 void PPCHazardRecognizer970::EndDispatchGroup() {
266 DEBUG(errs() << "=== Start of dispatch group\n");
269 // Structural hazard info.
276 PPCHazardRecognizer970::GetInstrType(unsigned Opcode,
277 bool &isFirst, bool &isSingle,
279 bool &isLoad, bool &isStore) {
280 const MCInstrDesc &MCID = TM.getInstrInfo()->get(Opcode);
282 isLoad = MCID.mayLoad();
283 isStore = MCID.mayStore();
285 uint64_t TSFlags = MCID.TSFlags;
287 isFirst = TSFlags & PPCII::PPC970_First;
288 isSingle = TSFlags & PPCII::PPC970_Single;
289 isCracked = TSFlags & PPCII::PPC970_Cracked;
290 return (PPCII::PPC970_Unit)(TSFlags & PPCII::PPC970_Mask);
293 /// isLoadOfStoredAddress - If we have a load from the previously stored pointer
294 /// as indicated by StorePtr1/StorePtr2/StoreSize, return true.
295 bool PPCHazardRecognizer970::
296 isLoadOfStoredAddress(uint64_t LoadSize, int64_t LoadOffset,
297 const Value *LoadValue) const {
298 for (unsigned i = 0, e = NumStores; i != e; ++i) {
299 // Handle exact and commuted addresses.
300 if (LoadValue == StoreValue[i] && LoadOffset == StoreOffset[i])
303 // Okay, we don't have an exact match, if this is an indexed offset, see if
304 // we have overlap (which happens during fp->int conversion for example).
305 if (StoreValue[i] == LoadValue) {
306 // Okay the base pointers match, so we have [c1+r] vs [c2+r]. Check
307 // to see if the load and store actually overlap.
308 if (StoreOffset[i] < LoadOffset) {
309 if (int64_t(StoreOffset[i]+StoreSize[i]) > LoadOffset) return true;
311 if (int64_t(LoadOffset+LoadSize) > StoreOffset[i]) return true;
318 /// getHazardType - We return hazard for any non-branch instruction that would
319 /// terminate the dispatch group. We turn NoopHazard for any
320 /// instructions that wouldn't terminate the dispatch group that would cause a
322 ScheduleHazardRecognizer::HazardType PPCHazardRecognizer970::
323 getHazardType(SUnit *SU, int Stalls) {
324 assert(Stalls == 0 && "PPC hazards don't support scoreboard lookahead");
326 MachineInstr *MI = SU->getInstr();
328 if (MI->isDebugValue())
331 unsigned Opcode = MI->getOpcode();
332 bool isFirst, isSingle, isCracked, isLoad, isStore;
333 PPCII::PPC970_Unit InstrType =
334 GetInstrType(Opcode, isFirst, isSingle, isCracked,
336 if (InstrType == PPCII::PPC970_Pseudo) return NoHazard;
338 // We can only issue a PPC970_First/PPC970_Single instruction (such as
339 // crand/mtspr/etc) if this is the first cycle of the dispatch group.
340 if (NumIssued != 0 && (isFirst || isSingle))
343 // If this instruction is cracked into two ops by the decoder, we know that
344 // it is not a branch and that it cannot issue if 3 other instructions are
345 // already in the dispatch group.
346 if (isCracked && NumIssued > 2)
350 default: llvm_unreachable("Unknown instruction type!");
351 case PPCII::PPC970_FXU:
352 case PPCII::PPC970_LSU:
353 case PPCII::PPC970_FPU:
354 case PPCII::PPC970_VALU:
355 case PPCII::PPC970_VPERM:
356 // We can only issue a branch as the last instruction in a group.
357 if (NumIssued == 4) return Hazard;
359 case PPCII::PPC970_CRU:
360 // We can only issue a CR instruction in the first two slots.
361 if (NumIssued >= 2) return Hazard;
363 case PPCII::PPC970_BRU:
367 // Do not allow MTCTR and BCTRL to be in the same dispatch group.
368 if (HasCTRSet && Opcode == PPC::BCTRL)
371 // If this is a load following a store, make sure it's not to the same or
372 // overlapping address.
373 if (isLoad && NumStores && !MI->memoperands_empty()) {
374 MachineMemOperand *MO = *MI->memoperands_begin();
375 if (isLoadOfStoredAddress(MO->getSize(),
376 MO->getOffset(), MO->getValue()))
383 void PPCHazardRecognizer970::EmitInstruction(SUnit *SU) {
384 MachineInstr *MI = SU->getInstr();
386 if (MI->isDebugValue())
389 unsigned Opcode = MI->getOpcode();
390 bool isFirst, isSingle, isCracked, isLoad, isStore;
391 PPCII::PPC970_Unit InstrType =
392 GetInstrType(Opcode, isFirst, isSingle, isCracked,
394 if (InstrType == PPCII::PPC970_Pseudo) return;
396 // Update structural hazard information.
397 if (Opcode == PPC::MTCTR || Opcode == PPC::MTCTR8) HasCTRSet = true;
399 // Track the address stored to.
400 if (isStore && NumStores < 4 && !MI->memoperands_empty()) {
401 MachineMemOperand *MO = *MI->memoperands_begin();
402 StoreSize[NumStores] = MO->getSize();
403 StoreOffset[NumStores] = MO->getOffset();
404 StoreValue[NumStores] = MO->getValue();
408 if (InstrType == PPCII::PPC970_BRU || isSingle)
409 NumIssued = 4; // Terminate a d-group.
412 // If this instruction is cracked into two ops by the decoder, remember that
413 // we issued two pieces.
421 void PPCHazardRecognizer970::AdvanceCycle() {
422 assert(NumIssued < 5 && "Illegal dispatch group!");
428 void PPCHazardRecognizer970::Reset() {