1 //===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the PPC implementation of TargetFrameLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCFrameLowering.h"
15 #include "PPCInstrBuilder.h"
16 #include "PPCInstrInfo.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Target/TargetOptions.h"
29 // FIXME This disables some code that aligns the stack to a boundary bigger than
30 // the default (16 bytes on Darwin) when there is a stack local of greater
31 // alignment. This does not currently work, because the delta between old and
32 // new stack pointers is added to offsets that reference incoming parameters
33 // after the prolog is generated, and the code that does that doesn't handle a
34 // variable delta. You don't want to do that anyway; a better approach is to
35 // reserve another register that retains to the incoming stack pointer, and
36 // reference parameters relative to that.
40 /// VRRegNo - Map from a numbered VR register to its enum value.
42 static const uint16_t VRRegNo[] = {
43 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
44 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
45 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
46 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
49 /// RemoveVRSaveCode - We have found that this function does not need any code
50 /// to manipulate the VRSAVE register, even though it uses vector registers.
51 /// This can happen when the only registers used are known to be live in or out
52 /// of the function. Remove all of the VRSAVE related code from the function.
53 /// FIXME: The removal of the code results in a compile failure at -O0 when the
54 /// function contains a function call, as the GPR containing original VRSAVE
55 /// contents is spilled and reloaded around the call. Without the prolog code,
56 /// the spill instruction refers to an undefined register. This code needs
57 /// to account for all uses of that GPR.
58 static void RemoveVRSaveCode(MachineInstr *MI) {
59 MachineBasicBlock *Entry = MI->getParent();
60 MachineFunction *MF = Entry->getParent();
62 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
63 MachineBasicBlock::iterator MBBI = MI;
65 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
66 MBBI->eraseFromParent();
68 bool RemovedAllMTVRSAVEs = true;
69 // See if we can find and remove the MTVRSAVE instruction from all of the
71 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
72 // If last instruction is a return instruction, add an epilogue
73 if (!I->empty() && I->back().isReturn()) {
75 for (MBBI = I->end(); MBBI != I->begin(); ) {
77 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
78 MBBI->eraseFromParent(); // remove it.
83 RemovedAllMTVRSAVEs &= FoundIt;
87 // If we found and removed all MTVRSAVE instructions, remove the read of
89 if (RemovedAllMTVRSAVEs) {
91 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
93 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
94 MBBI->eraseFromParent();
97 // Finally, nuke the UPDATE_VRSAVE.
98 MI->eraseFromParent();
101 // HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
102 // instruction selector. Based on the vector registers that have been used,
103 // transform this into the appropriate ORI instruction.
104 static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
105 MachineFunction *MF = MI->getParent()->getParent();
106 DebugLoc dl = MI->getDebugLoc();
108 unsigned UsedRegMask = 0;
109 for (unsigned i = 0; i != 32; ++i)
110 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
111 UsedRegMask |= 1 << (31-i);
113 // Live in and live out values already must be in the mask, so don't bother
115 for (MachineRegisterInfo::livein_iterator
116 I = MF->getRegInfo().livein_begin(),
117 E = MF->getRegInfo().livein_end(); I != E; ++I) {
118 unsigned RegNo = getPPCRegisterNumbering(I->first);
119 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
120 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
123 // Live out registers appear as use operands on return instructions.
124 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
125 UsedRegMask != 0 && BI != BE; ++BI) {
126 const MachineBasicBlock &MBB = *BI;
127 if (MBB.empty() || !MBB.back().isReturn())
129 const MachineInstr &Ret = MBB.back();
130 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
131 const MachineOperand &MO = Ret.getOperand(I);
132 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
134 unsigned RegNo = getPPCRegisterNumbering(MO.getReg());
135 UsedRegMask &= ~(1 << (31-RegNo));
139 // If no registers are used, turn this into a copy.
140 if (UsedRegMask == 0) {
141 // Remove all VRSAVE code.
142 RemoveVRSaveCode(MI);
146 unsigned SrcReg = MI->getOperand(1).getReg();
147 unsigned DstReg = MI->getOperand(0).getReg();
149 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
150 if (DstReg != SrcReg)
151 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
153 .addImm(UsedRegMask);
155 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
156 .addReg(SrcReg, RegState::Kill)
157 .addImm(UsedRegMask);
158 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
159 if (DstReg != SrcReg)
160 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
162 .addImm(UsedRegMask >> 16);
164 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
165 .addReg(SrcReg, RegState::Kill)
166 .addImm(UsedRegMask >> 16);
168 if (DstReg != SrcReg)
169 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
171 .addImm(UsedRegMask >> 16);
173 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
174 .addReg(SrcReg, RegState::Kill)
175 .addImm(UsedRegMask >> 16);
177 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
178 .addReg(DstReg, RegState::Kill)
179 .addImm(UsedRegMask & 0xFFFF);
182 // Remove the old UPDATE_VRSAVE instruction.
183 MI->eraseFromParent();
186 static bool spillsCR(const MachineFunction &MF) {
187 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
188 return FuncInfo->isCRSpilled();
191 static bool hasSpills(const MachineFunction &MF) {
192 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
193 return FuncInfo->hasSpills();
196 /// determineFrameLayout - Determine the size of the frame and maximum call
198 unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
200 bool UseEstimate) const {
201 MachineFrameInfo *MFI = MF.getFrameInfo();
203 // Get the number of bytes to allocate from the FrameInfo
205 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
207 // Get the alignments provided by the target, and the maximum alignment
208 // (if any) of the fixed frame objects.
209 unsigned MaxAlign = MFI->getMaxAlignment();
210 unsigned TargetAlign = getStackAlignment();
211 unsigned AlignMask = TargetAlign - 1; //
213 // If we are a leaf function, and use up to 224 bytes of stack space,
214 // don't have a frame pointer, calls, or dynamic alloca then we do not need
215 // to adjust the stack pointer (we fit in the Red Zone). For 64-bit
216 // SVR4, we also require a stack frame if we need to spill the CR,
217 // since this spill area is addressed relative to the stack pointer.
218 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
219 // stackless code if all local vars are reg-allocated.
220 bool DisableRedZone = MF.getFunction()->getAttributes().
221 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone);
222 if (!DisableRedZone &&
223 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
224 !Subtarget.isSVR4ABI() || // allocated locals.
226 FrameSize <= 224 && // Fits in red zone.
227 !MFI->hasVarSizedObjects() && // No dynamic alloca.
228 !MFI->adjustsStack() && // No calls.
229 !(Subtarget.isPPC64() && // No 64-bit SVR4 CRsave.
230 Subtarget.isSVR4ABI()
232 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment.
235 MFI->setStackSize(0);
239 // Get the maximum call frame size of all the calls.
240 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
242 // Maximum call frame needs to be at least big enough for linkage and 8 args.
243 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(),
244 Subtarget.isDarwinABI());
245 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
247 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
248 // that allocations will be aligned.
249 if (MFI->hasVarSizedObjects())
250 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
252 // Update maximum call frame size.
254 MFI->setMaxCallFrameSize(maxCallFrameSize);
256 // Include call frame size in total.
257 FrameSize += maxCallFrameSize;
259 // Make sure the frame is aligned.
260 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
262 // Update frame info.
264 MFI->setStackSize(FrameSize);
269 // hasFP - Return true if the specified function actually has a dedicated frame
271 bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
272 const MachineFrameInfo *MFI = MF.getFrameInfo();
273 // FIXME: This is pretty much broken by design: hasFP() might be called really
274 // early, before the stack layout was calculated and thus hasFP() might return
275 // true or false here depending on the time of call.
276 return (MFI->getStackSize()) && needsFP(MF);
279 // needsFP - Return true if the specified function should have a dedicated frame
280 // pointer register. This is true if the function has variable sized allocas or
281 // if frame pointer elimination is disabled.
282 bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
283 const MachineFrameInfo *MFI = MF.getFrameInfo();
285 // Naked functions have no stack frame pushed, so we don't have a frame
287 if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex,
291 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
292 MFI->hasVarSizedObjects() ||
293 (MF.getTarget().Options.GuaranteedTailCallOpt &&
294 MF.getInfo<PPCFunctionInfo>()->hasFastCall());
298 void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
299 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
300 MachineBasicBlock::iterator MBBI = MBB.begin();
301 MachineFrameInfo *MFI = MF.getFrameInfo();
302 const PPCInstrInfo &TII =
303 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
305 MachineModuleInfo &MMI = MF.getMMI();
307 bool needsFrameMoves = MMI.hasDebugInfo() ||
308 MF.getFunction()->needsUnwindTableEntry();
310 // Prepare for frame info.
311 MCSymbol *FrameLabel = 0;
313 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
315 if (!Subtarget.isSVR4ABI())
316 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
317 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
318 HandleVRSaveUpdate(MBBI, TII);
323 // Move MBBI back to the beginning of the function.
326 // Work out frame sizes.
327 unsigned FrameSize = determineFrameLayout(MF);
328 int NegFrameSize = -FrameSize;
330 // Get processor type.
331 bool isPPC64 = Subtarget.isPPC64();
332 // Get operating system
333 bool isDarwinABI = Subtarget.isDarwinABI();
334 // Check if the link register (LR) must be saved.
335 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
336 bool MustSaveLR = FI->mustSaveLR();
337 // Do we have a frame pointer for this function?
338 bool HasFP = hasFP(MF);
340 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
344 if (Subtarget.isSVR4ABI()) {
345 MachineFrameInfo *FFI = MF.getFrameInfo();
346 int FPIndex = FI->getFramePointerSaveIndex();
347 assert(FPIndex && "No Frame Pointer Save Slot!");
348 FPOffset = FFI->getObjectOffset(FPIndex);
350 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
356 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0);
359 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
365 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD))
367 .addImm(LROffset / 4)
371 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0);
374 // FIXME: On PPC32 SVR4, FPOffset is negative and access to negative
375 // offsets of R1 is not allowed.
376 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
382 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW))
388 // Skip if a leaf routine.
389 if (!FrameSize) return;
391 // Get stack alignments.
392 unsigned TargetAlign = getStackAlignment();
393 unsigned MaxAlign = MFI->getMaxAlignment();
395 // Adjust stack pointer: r1 += NegFrameSize.
396 // If there is a preferred stack alignment, align R1 now
399 if (ALIGN_STACK && MaxAlign > TargetAlign) {
400 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
401 "Invalid alignment!");
402 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
404 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0)
407 .addImm(32 - Log2_32(MaxAlign))
409 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0)
410 .addReg(PPC::R0, RegState::Kill)
411 .addImm(NegFrameSize);
412 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1)
413 .addReg(PPC::R1, RegState::Kill)
416 } else if (isInt<16>(NegFrameSize)) {
417 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1)
419 .addImm(NegFrameSize)
422 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
423 .addImm(NegFrameSize >> 16);
424 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
425 .addReg(PPC::R0, RegState::Kill)
426 .addImm(NegFrameSize & 0xFFFF);
427 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1)
428 .addReg(PPC::R1, RegState::Kill)
433 if (ALIGN_STACK && MaxAlign > TargetAlign) {
434 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
435 "Invalid alignment!");
436 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!");
438 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0)
441 .addImm(64 - Log2_32(MaxAlign));
442 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0)
444 .addImm(NegFrameSize);
445 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1)
446 .addReg(PPC::X1, RegState::Kill)
449 } else if (isInt<16>(NegFrameSize)) {
450 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1)
452 .addImm(NegFrameSize / 4)
455 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
456 .addImm(NegFrameSize >> 16);
457 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
458 .addReg(PPC::X0, RegState::Kill)
459 .addImm(NegFrameSize & 0xFFFF);
460 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1)
461 .addReg(PPC::X1, RegState::Kill)
467 std::vector<MachineMove> &Moves = MMI.getFrameMoves();
469 // Add the "machine moves" for the instructions we generated above, but in
471 if (needsFrameMoves) {
472 // Mark effective beginning of when frame pointer becomes valid.
473 FrameLabel = MMI.getContext().CreateTempSymbol();
474 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel);
476 // Show update of SP.
478 MachineLocation SPDst(MachineLocation::VirtualFP);
479 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize);
480 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
482 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31);
483 Moves.push_back(MachineMove(FrameLabel, SP, SP));
487 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset);
488 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31);
489 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc));
493 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset);
494 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR);
495 Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc));
499 MCSymbol *ReadyLabel = 0;
501 // If there is a frame pointer, copy R1 into R31
504 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31)
508 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31)
513 if (needsFrameMoves) {
514 ReadyLabel = MMI.getContext().CreateTempSymbol();
516 // Mark effective beginning of when frame pointer is ready.
517 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel);
519 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) :
520 (isPPC64 ? PPC::X1 : PPC::R1));
521 MachineLocation FPSrc(MachineLocation::VirtualFP);
522 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc));
526 if (needsFrameMoves) {
527 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel;
529 // Add callee saved registers to move list.
530 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
531 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
532 unsigned Reg = CSI[I].getReg();
533 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
535 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
536 // subregisters of CR2. We just need to emit a move of CR2.
537 if (PPC::CRBITRCRegClass.contains(Reg))
540 // For SVR4, don't emit a move for the CR spill slot if we haven't
542 if (Subtarget.isSVR4ABI()
543 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
547 // For 64-bit SVR4 when we have spilled CRs, the spill location
548 // is SP+8, not a frame-relative slot.
549 if (Subtarget.isSVR4ABI()
550 && Subtarget.isPPC64()
551 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
552 MachineLocation CSDst(PPC::X1, 8);
553 MachineLocation CSSrc(PPC::CR2);
554 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
558 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
559 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
560 MachineLocation CSSrc(Reg);
561 Moves.push_back(MachineMove(Label, CSDst, CSSrc));
566 void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
567 MachineBasicBlock &MBB) const {
568 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
569 assert(MBBI != MBB.end() && "Returning block has no terminator");
570 const PPCInstrInfo &TII =
571 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
573 unsigned RetOpcode = MBBI->getOpcode();
576 assert((RetOpcode == PPC::BLR ||
577 RetOpcode == PPC::TCRETURNri ||
578 RetOpcode == PPC::TCRETURNdi ||
579 RetOpcode == PPC::TCRETURNai ||
580 RetOpcode == PPC::TCRETURNri8 ||
581 RetOpcode == PPC::TCRETURNdi8 ||
582 RetOpcode == PPC::TCRETURNai8) &&
583 "Can only insert epilog into returning blocks");
585 // Get alignment info so we know how to restore r1
586 const MachineFrameInfo *MFI = MF.getFrameInfo();
587 unsigned TargetAlign = getStackAlignment();
588 unsigned MaxAlign = MFI->getMaxAlignment();
590 // Get the number of bytes allocated from the FrameInfo.
591 int FrameSize = MFI->getStackSize();
593 // Get processor type.
594 bool isPPC64 = Subtarget.isPPC64();
595 // Get operating system
596 bool isDarwinABI = Subtarget.isDarwinABI();
597 // Check if the link register (LR) has been saved.
598 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
599 bool MustSaveLR = FI->mustSaveLR();
600 // Do we have a frame pointer for this function?
601 bool HasFP = hasFP(MF);
603 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
607 if (Subtarget.isSVR4ABI()) {
608 MachineFrameInfo *FFI = MF.getFrameInfo();
609 int FPIndex = FI->getFramePointerSaveIndex();
610 assert(FPIndex && "No Frame Pointer Save Slot!");
611 FPOffset = FFI->getObjectOffset(FPIndex);
613 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
617 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
618 RetOpcode == PPC::TCRETURNdi ||
619 RetOpcode == PPC::TCRETURNai ||
620 RetOpcode == PPC::TCRETURNri8 ||
621 RetOpcode == PPC::TCRETURNdi8 ||
622 RetOpcode == PPC::TCRETURNai8;
625 int MaxTCRetDelta = FI->getTailCallSPDelta();
626 MachineOperand &StackAdjust = MBBI->getOperand(1);
627 assert(StackAdjust.isImm() && "Expecting immediate value.");
628 // Adjust stack pointer.
629 int StackAdj = StackAdjust.getImm();
630 int Delta = StackAdj - MaxTCRetDelta;
631 assert((Delta >= 0) && "Delta must be positive");
633 FrameSize += (StackAdj +Delta);
635 FrameSize += StackAdj;
639 // The loaded (or persistent) stack pointer value is offset by the 'stwu'
640 // on entry to the function. Add this offset back now.
642 // If this function contained a fastcc call and GuaranteedTailCallOpt is
643 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
644 // call which invalidates the stack pointer value in SP(0). So we use the
645 // value of R31 in this case.
646 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
647 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
648 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
649 .addReg(PPC::R31).addImm(FrameSize);
650 } else if(FI->hasFastCall()) {
651 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0)
652 .addImm(FrameSize >> 16);
653 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0)
654 .addReg(PPC::R0, RegState::Kill)
655 .addImm(FrameSize & 0xFFFF);
656 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4))
660 } else if (isInt<16>(FrameSize) &&
661 (!ALIGN_STACK || TargetAlign >= MaxAlign) &&
662 !MFI->hasVarSizedObjects()) {
663 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1)
664 .addReg(PPC::R1).addImm(FrameSize);
666 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1)
667 .addImm(0).addReg(PPC::R1);
670 if (FI->hasFastCall() && isInt<16>(FrameSize)) {
671 assert(hasFP(MF) && "Expecting a valid the frame pointer.");
672 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
673 .addReg(PPC::X31).addImm(FrameSize);
674 } else if(FI->hasFastCall()) {
675 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0)
676 .addImm(FrameSize >> 16);
677 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0)
678 .addReg(PPC::X0, RegState::Kill)
679 .addImm(FrameSize & 0xFFFF);
680 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8))
684 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign &&
685 !MFI->hasVarSizedObjects()) {
686 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1)
687 .addReg(PPC::X1).addImm(FrameSize);
689 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1)
690 .addImm(0).addReg(PPC::X1);
697 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0)
698 .addImm(LROffset/4).addReg(PPC::X1);
701 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31)
702 .addImm(FPOffset/4).addReg(PPC::X1);
705 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0);
708 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0)
709 .addImm(LROffset).addReg(PPC::R1);
712 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31)
713 .addImm(FPOffset).addReg(PPC::R1);
716 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0);
719 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
721 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
722 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
723 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
724 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
725 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1;
726 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
727 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0;
728 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI;
729 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4;
730 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS;
731 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI;
733 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
734 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg)
735 .addReg(StackReg).addImm(CallerAllocatedAmt);
737 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
738 .addImm(CallerAllocatedAmt >> 16);
739 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
740 .addReg(TmpReg, RegState::Kill)
741 .addImm(CallerAllocatedAmt & 0xFFFF);
742 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr))
747 } else if (RetOpcode == PPC::TCRETURNdi) {
748 MBBI = MBB.getLastNonDebugInstr();
749 MachineOperand &JumpTarget = MBBI->getOperand(0);
750 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
751 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
752 } else if (RetOpcode == PPC::TCRETURNri) {
753 MBBI = MBB.getLastNonDebugInstr();
754 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
755 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
756 } else if (RetOpcode == PPC::TCRETURNai) {
757 MBBI = MBB.getLastNonDebugInstr();
758 MachineOperand &JumpTarget = MBBI->getOperand(0);
759 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
760 } else if (RetOpcode == PPC::TCRETURNdi8) {
761 MBBI = MBB.getLastNonDebugInstr();
762 MachineOperand &JumpTarget = MBBI->getOperand(0);
763 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
764 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
765 } else if (RetOpcode == PPC::TCRETURNri8) {
766 MBBI = MBB.getLastNonDebugInstr();
767 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
768 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
769 } else if (RetOpcode == PPC::TCRETURNai8) {
770 MBBI = MBB.getLastNonDebugInstr();
771 MachineOperand &JumpTarget = MBBI->getOperand(0);
772 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
776 /// MustSaveLR - Return true if this function requires that we save the LR
777 /// register onto the stack in the prolog and restore it in the epilog of the
779 static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
780 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
782 // We need a save/restore of LR if there is any def of LR (which is
783 // defined by calls, including the PIC setup sequence), or if there is
784 // some use of the LR stack slot (e.g. for builtin_return_address).
785 // (LR comes in 32 and 64 bit versions.)
786 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
787 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
791 PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
792 RegScavenger *) const {
793 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
795 // Save and clear the LR state.
796 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
797 unsigned LR = RegInfo->getRARegister();
798 FI->setMustSaveLR(MustSaveLR(MF, LR));
799 MachineRegisterInfo &MRI = MF.getRegInfo();
800 MRI.setPhysRegUnused(LR);
802 // Save R31 if necessary
803 int FPSI = FI->getFramePointerSaveIndex();
804 bool isPPC64 = Subtarget.isPPC64();
805 bool isDarwinABI = Subtarget.isDarwinABI();
806 MachineFrameInfo *MFI = MF.getFrameInfo();
808 // If the frame pointer save index hasn't been defined yet.
809 if (!FPSI && needsFP(MF)) {
810 // Find out what the fix offset of the frame pointer save area.
811 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
812 // Allocate the frame index for frame pointer save area.
813 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
815 FI->setFramePointerSaveIndex(FPSI);
818 // Reserve stack space to move the linkage area to in case of a tail call.
820 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
821 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
822 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
825 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
826 // function uses CR 2, 3, or 4.
827 if (!isPPC64 && !isDarwinABI &&
828 (MRI.isPhysRegUsed(PPC::CR2) ||
829 MRI.isPhysRegUsed(PPC::CR3) ||
830 MRI.isPhysRegUsed(PPC::CR4))) {
831 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
832 FI->setCRSpillFrameIndex(FrameIdx);
836 void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
837 RegScavenger *RS) const {
838 // Early exit if not using the SVR4 ABI.
839 if (!Subtarget.isSVR4ABI()) {
840 addScavengingSpillSlot(MF, RS);
844 // Get callee saved register information.
845 MachineFrameInfo *FFI = MF.getFrameInfo();
846 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
848 // Early exit if no callee saved registers are modified!
849 if (CSI.empty() && !needsFP(MF)) {
850 addScavengingSpillSlot(MF, RS);
854 unsigned MinGPR = PPC::R31;
855 unsigned MinG8R = PPC::X31;
856 unsigned MinFPR = PPC::F31;
857 unsigned MinVR = PPC::V31;
859 bool HasGPSaveArea = false;
860 bool HasG8SaveArea = false;
861 bool HasFPSaveArea = false;
862 bool HasVRSAVESaveArea = false;
863 bool HasVRSaveArea = false;
865 SmallVector<CalleeSavedInfo, 18> GPRegs;
866 SmallVector<CalleeSavedInfo, 18> G8Regs;
867 SmallVector<CalleeSavedInfo, 18> FPRegs;
868 SmallVector<CalleeSavedInfo, 18> VRegs;
870 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
871 unsigned Reg = CSI[i].getReg();
872 if (PPC::GPRCRegClass.contains(Reg)) {
873 HasGPSaveArea = true;
875 GPRegs.push_back(CSI[i]);
880 } else if (PPC::G8RCRegClass.contains(Reg)) {
881 HasG8SaveArea = true;
883 G8Regs.push_back(CSI[i]);
888 } else if (PPC::F8RCRegClass.contains(Reg)) {
889 HasFPSaveArea = true;
891 FPRegs.push_back(CSI[i]);
896 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
897 PPC::CRRCRegClass.contains(Reg)) {
898 ; // do nothing, as we already know whether CRs are spilled
899 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
900 HasVRSAVESaveArea = true;
901 } else if (PPC::VRRCRegClass.contains(Reg)) {
902 HasVRSaveArea = true;
904 VRegs.push_back(CSI[i]);
910 llvm_unreachable("Unknown RegisterClass!");
914 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
916 int64_t LowerBound = 0;
918 // Take into account stack space reserved for tail calls.
920 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
921 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
922 LowerBound = TCSPDelta;
925 // The Floating-point register save area is right below the back chain word
926 // of the previous stack frame.
928 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
929 int FI = FPRegs[i].getFrameIdx();
931 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
934 LowerBound -= (31 - getPPCRegisterNumbering(MinFPR) + 1) * 8;
937 // Check whether the frame pointer register is allocated. If so, make sure it
938 // is spilled to the correct offset.
940 HasGPSaveArea = true;
942 int FI = PFI->getFramePointerSaveIndex();
943 assert(FI && "No Frame Pointer Save Slot!");
945 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
948 // General register save area starts right below the Floating-point
949 // register save area.
950 if (HasGPSaveArea || HasG8SaveArea) {
951 // Move general register save area spill slots down, taking into account
952 // the size of the Floating-point register save area.
953 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
954 int FI = GPRegs[i].getFrameIdx();
956 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
959 // Move general register save area spill slots down, taking into account
960 // the size of the Floating-point register save area.
961 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
962 int FI = G8Regs[i].getFrameIdx();
964 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
968 std::min<unsigned>(getPPCRegisterNumbering(MinGPR),
969 getPPCRegisterNumbering(MinG8R));
971 if (Subtarget.isPPC64()) {
972 LowerBound -= (31 - MinReg + 1) * 8;
974 LowerBound -= (31 - MinReg + 1) * 4;
978 // For 32-bit only, the CR save area is below the general register
979 // save area. For 64-bit SVR4, the CR save area is addressed relative
980 // to the stack pointer and hence does not need an adjustment here.
981 // Only CR2 (the first nonvolatile spilled) has an associated frame
982 // index so that we have a single uniform save area.
983 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
984 // Adjust the frame index of the CR spill slot.
985 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
986 unsigned Reg = CSI[i].getReg();
988 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
989 // Leave Darwin logic as-is.
990 || (!Subtarget.isSVR4ABI() &&
991 (PPC::CRBITRCRegClass.contains(Reg) ||
992 PPC::CRRCRegClass.contains(Reg)))) {
993 int FI = CSI[i].getFrameIdx();
995 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
999 LowerBound -= 4; // The CR save area is always 4 bytes long.
1002 if (HasVRSAVESaveArea) {
1003 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1004 // which have the VRSAVE register class?
1005 // Adjust the frame index of the VRSAVE spill slot.
1006 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1007 unsigned Reg = CSI[i].getReg();
1009 if (PPC::VRSAVERCRegClass.contains(Reg)) {
1010 int FI = CSI[i].getFrameIdx();
1012 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1016 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1019 if (HasVRSaveArea) {
1020 // Insert alignment padding, we need 16-byte alignment.
1021 LowerBound = (LowerBound - 15) & ~(15);
1023 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1024 int FI = VRegs[i].getFrameIdx();
1026 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1030 addScavengingSpillSlot(MF, RS);
1034 PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
1035 RegScavenger *RS) const {
1036 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1037 // a large stack, which will require scavenging a register to materialize a
1040 // We need to have a scavenger spill slot for spills if the frame size is
1041 // large. In case there is no free register for large-offset addressing,
1042 // this slot is used for the necessary emergency spill. Also, we need the
1043 // slot for dynamic stack allocations.
1045 // The scavenger might be invoked if the frame offset does not fit into
1046 // the 16-bit immediate. We don't know the complete frame size here
1047 // because we've not yet computed callee-saved register spills or the
1048 // needed alignment padding.
1049 unsigned StackSize = determineFrameLayout(MF, false, true);
1050 MachineFrameInfo *MFI = MF.getFrameInfo();
1051 if (MFI->hasVarSizedObjects() || spillsCR(MF) ||
1052 (hasSpills(MF) && !isInt<16>(StackSize))) {
1053 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1054 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1055 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
1056 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1063 PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
1064 MachineBasicBlock::iterator MI,
1065 const std::vector<CalleeSavedInfo> &CSI,
1066 const TargetRegisterInfo *TRI) const {
1068 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1069 // Return false otherwise to maintain pre-existing behavior.
1070 if (!Subtarget.isSVR4ABI())
1073 MachineFunction *MF = MBB.getParent();
1074 const PPCInstrInfo &TII =
1075 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1077 bool CRSpilled = false;
1079 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1080 unsigned Reg = CSI[i].getReg();
1081 // CR2 through CR4 are the nonvolatile CR fields.
1082 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1084 if (CRSpilled && IsCRField)
1087 // Add the callee-saved register as live-in; it's killed at the spill.
1090 // Insert the spill to the stack frame.
1093 // The first time we see a CR field, store the whole CR into the
1094 // save slot via GPR12 (available in the prolog for 32- and 64-bit).
1095 if (Subtarget.isPPC64()) {
1097 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::X12));
1098 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::STW))
1100 getKillRegState(true))
1104 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1105 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1106 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12));
1107 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1109 getKillRegState(true)),
1110 CSI[i].getFrameIdx()));
1113 // Record that we spill the CR in this function.
1114 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
1115 FuncInfo->setSpillsCR();
1117 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1118 TII.storeRegToStackSlot(MBB, MI, Reg, true,
1119 CSI[i].getFrameIdx(), RC, TRI);
1126 restoreCRs(bool isPPC64, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
1127 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1128 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
1130 MachineFunction *MF = MBB.getParent();
1131 const PPCInstrInfo &TII =
1132 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1134 unsigned RestoreOp, MoveReg;
1138 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::LWZ), PPC::X12)
1141 RestoreOp = PPC::MTCRF8;
1144 // 32-bit: FP-relative
1145 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
1147 CSI[CSIIndex].getFrameIdx()));
1148 RestoreOp = PPC::MTCRF;
1153 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
1157 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
1161 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
1165 void PPCFrameLowering::
1166 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1167 MachineBasicBlock::iterator I) const {
1168 const PPCInstrInfo &TII =
1169 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
1170 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1171 I->getOpcode() == PPC::ADJCALLSTACKUP) {
1172 // Add (actually subtract) back the amount the callee popped on return.
1173 if (int CalleeAmt = I->getOperand(1).getImm()) {
1174 bool is64Bit = Subtarget.isPPC64();
1176 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1177 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1178 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1179 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1180 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1181 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1182 MachineInstr *MI = I;
1183 DebugLoc dl = MI->getDebugLoc();
1185 if (isInt<16>(CalleeAmt)) {
1186 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1187 .addReg(StackReg, RegState::Kill)
1190 MachineBasicBlock::iterator MBBI = I;
1191 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1192 .addImm(CalleeAmt >> 16);
1193 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1194 .addReg(TmpReg, RegState::Kill)
1195 .addImm(CalleeAmt & 0xFFFF);
1196 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1197 .addReg(StackReg, RegState::Kill)
1202 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1207 PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
1208 MachineBasicBlock::iterator MI,
1209 const std::vector<CalleeSavedInfo> &CSI,
1210 const TargetRegisterInfo *TRI) const {
1212 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1213 // Return false otherwise to maintain pre-existing behavior.
1214 if (!Subtarget.isSVR4ABI())
1217 MachineFunction *MF = MBB.getParent();
1218 const PPCInstrInfo &TII =
1219 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1220 bool CR2Spilled = false;
1221 bool CR3Spilled = false;
1222 bool CR4Spilled = false;
1223 unsigned CSIIndex = 0;
1225 // Initialize insertion-point logic; we will be restoring in reverse
1227 MachineBasicBlock::iterator I = MI, BeforeI = I;
1228 bool AtStart = I == MBB.begin();
1233 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1234 unsigned Reg = CSI[i].getReg();
1236 if (Reg == PPC::CR2) {
1238 // The spill slot is associated only with CR2, which is the
1239 // first nonvolatile spilled. Save it here.
1242 } else if (Reg == PPC::CR3) {
1245 } else if (Reg == PPC::CR4) {
1249 // When we first encounter a non-CR register after seeing at
1250 // least one CR register, restore all spilled CRs together.
1251 if ((CR2Spilled || CR3Spilled || CR4Spilled)
1252 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
1253 restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled,
1254 MBB, I, CSI, CSIIndex);
1255 CR2Spilled = CR3Spilled = CR4Spilled = false;
1258 // Default behavior for non-CR saves.
1259 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1260 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
1262 assert(I != MBB.begin() &&
1263 "loadRegFromStackSlot didn't insert any code!");
1266 // Insert in reverse order.
1275 // If we haven't yet spilled the CRs, do so now.
1276 if (CR2Spilled || CR3Spilled || CR4Spilled)
1277 restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled,
1278 MBB, I, CSI, CSIIndex);