1 //===-- PPCFastISel.cpp - PowerPC FastISel implementation -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the PowerPC-specific support for the FastISel class. Some
11 // of the target-specific code is generated by tablegen in the file
12 // PPCGenFastISel.inc, which is #included here.
14 //===----------------------------------------------------------------------===//
17 #include "MCTargetDesc/PPCPredicates.h"
18 #include "PPCCallingConv.h"
19 #include "PPCISelLowering.h"
20 #include "PPCMachineFunctionInfo.h"
21 #include "PPCSubtarget.h"
22 #include "PPCTargetMachine.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/FastISel.h"
26 #include "llvm/CodeGen/FunctionLoweringInfo.h"
27 #include "llvm/CodeGen/MachineConstantPool.h"
28 #include "llvm/CodeGen/MachineFrameInfo.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/GetElementPtrTypeIterator.h"
33 #include "llvm/IR/GlobalAlias.h"
34 #include "llvm/IR/GlobalVariable.h"
35 #include "llvm/IR/IntrinsicInst.h"
36 #include "llvm/IR/Operator.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Target/TargetLowering.h"
39 #include "llvm/Target/TargetMachine.h"
41 //===----------------------------------------------------------------------===//
44 // fastLowerArguments: Handle simple cases.
45 // PPCMaterializeGV: Handle TLS.
46 // SelectCall: Handle function pointers.
47 // SelectCall: Handle multi-register return values.
48 // SelectCall: Optimize away nops for local calls.
49 // processCallArgs: Handle bit-converted arguments.
50 // finishCall: Handle multi-register return values.
51 // PPCComputeAddress: Handle parameter references as FrameIndex's.
52 // PPCEmitCmp: Handle immediate as operand 1.
53 // SelectCall: Handle small byval arguments.
54 // SelectIntrinsicCall: Implement.
55 // SelectSelect: Implement.
56 // Consider factoring isTypeLegal into the base class.
57 // Implement switches and jump tables.
59 //===----------------------------------------------------------------------===//
62 #define DEBUG_TYPE "ppcfastisel"
66 typedef struct Address {
79 // Innocuous defaults for our address.
81 : BaseType(RegBase), Offset(0) {
86 class PPCFastISel final : public FastISel {
88 const TargetMachine &TM;
89 const PPCSubtarget *PPCSubTarget;
90 PPCFunctionInfo *PPCFuncInfo;
91 const TargetInstrInfo &TII;
92 const TargetLowering &TLI;
96 explicit PPCFastISel(FunctionLoweringInfo &FuncInfo,
97 const TargetLibraryInfo *LibInfo)
98 : FastISel(FuncInfo, LibInfo), TM(FuncInfo.MF->getTarget()),
99 PPCSubTarget(&FuncInfo.MF->getSubtarget<PPCSubtarget>()),
100 PPCFuncInfo(FuncInfo.MF->getInfo<PPCFunctionInfo>()),
101 TII(*PPCSubTarget->getInstrInfo()),
102 TLI(*PPCSubTarget->getTargetLowering()),
103 Context(&FuncInfo.Fn->getContext()) {}
105 // Backend specific FastISel code.
107 bool fastSelectInstruction(const Instruction *I) override;
108 unsigned fastMaterializeConstant(const Constant *C) override;
109 unsigned fastMaterializeAlloca(const AllocaInst *AI) override;
110 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
111 const LoadInst *LI) override;
112 bool fastLowerArguments() override;
113 unsigned fastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
114 unsigned fastEmitInst_ri(unsigned MachineInstOpcode,
115 const TargetRegisterClass *RC,
116 unsigned Op0, bool Op0IsKill,
118 unsigned fastEmitInst_r(unsigned MachineInstOpcode,
119 const TargetRegisterClass *RC,
120 unsigned Op0, bool Op0IsKill);
121 unsigned fastEmitInst_rr(unsigned MachineInstOpcode,
122 const TargetRegisterClass *RC,
123 unsigned Op0, bool Op0IsKill,
124 unsigned Op1, bool Op1IsKill);
126 bool fastLowerCall(CallLoweringInfo &CLI) override;
128 // Instruction selection routines.
130 bool SelectLoad(const Instruction *I);
131 bool SelectStore(const Instruction *I);
132 bool SelectBranch(const Instruction *I);
133 bool SelectIndirectBr(const Instruction *I);
134 bool SelectFPExt(const Instruction *I);
135 bool SelectFPTrunc(const Instruction *I);
136 bool SelectIToFP(const Instruction *I, bool IsSigned);
137 bool SelectFPToI(const Instruction *I, bool IsSigned);
138 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode);
139 bool SelectRet(const Instruction *I);
140 bool SelectTrunc(const Instruction *I);
141 bool SelectIntExt(const Instruction *I);
145 bool isTypeLegal(Type *Ty, MVT &VT);
146 bool isLoadTypeLegal(Type *Ty, MVT &VT);
147 bool isValueAvailable(const Value *V) const;
148 bool isVSFRCRegister(unsigned Register) const {
149 return MRI.getRegClass(Register)->getID() == PPC::VSFRCRegClassID;
151 bool isVSSRCRegister(unsigned Register) const {
152 return MRI.getRegClass(Register)->getID() == PPC::VSSRCRegClassID;
154 bool PPCEmitCmp(const Value *Src1Value, const Value *Src2Value,
155 bool isZExt, unsigned DestReg);
156 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
157 const TargetRegisterClass *RC, bool IsZExt = true,
158 unsigned FP64LoadOpc = PPC::LFD);
159 bool PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr);
160 bool PPCComputeAddress(const Value *Obj, Address &Addr);
161 void PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
163 bool PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
164 unsigned DestReg, bool IsZExt);
165 unsigned PPCMaterializeFP(const ConstantFP *CFP, MVT VT);
166 unsigned PPCMaterializeGV(const GlobalValue *GV, MVT VT);
167 unsigned PPCMaterializeInt(const Constant *C, MVT VT, bool UseSExt = true);
168 unsigned PPCMaterialize32BitInt(int64_t Imm,
169 const TargetRegisterClass *RC);
170 unsigned PPCMaterialize64BitInt(int64_t Imm,
171 const TargetRegisterClass *RC);
172 unsigned PPCMoveToIntReg(const Instruction *I, MVT VT,
173 unsigned SrcReg, bool IsSigned);
174 unsigned PPCMoveToFPReg(MVT VT, unsigned SrcReg, bool IsSigned);
176 // Call handling routines.
178 bool processCallArgs(SmallVectorImpl<Value*> &Args,
179 SmallVectorImpl<unsigned> &ArgRegs,
180 SmallVectorImpl<MVT> &ArgVTs,
181 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
182 SmallVectorImpl<unsigned> &RegArgs,
186 bool finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes);
187 CCAssignFn *usePPC32CCs(unsigned Flag);
190 #include "PPCGenFastISel.inc"
194 } // end anonymous namespace
196 #include "PPCGenCallingConv.inc"
198 // Function whose sole purpose is to kill compiler warnings
199 // stemming from unused functions included from PPCGenCallingConv.inc.
200 CCAssignFn *PPCFastISel::usePPC32CCs(unsigned Flag) {
202 return CC_PPC32_SVR4;
204 return CC_PPC32_SVR4_ByVal;
206 return CC_PPC32_SVR4_VarArg;
211 static Optional<PPC::Predicate> getComparePred(CmpInst::Predicate Pred) {
213 // These are not representable with any single compare.
214 case CmpInst::FCMP_FALSE:
215 case CmpInst::FCMP_UEQ:
216 case CmpInst::FCMP_UGT:
217 case CmpInst::FCMP_UGE:
218 case CmpInst::FCMP_ULT:
219 case CmpInst::FCMP_ULE:
220 case CmpInst::FCMP_UNE:
221 case CmpInst::FCMP_TRUE:
223 return Optional<PPC::Predicate>();
225 case CmpInst::FCMP_OEQ:
226 case CmpInst::ICMP_EQ:
229 case CmpInst::FCMP_OGT:
230 case CmpInst::ICMP_UGT:
231 case CmpInst::ICMP_SGT:
234 case CmpInst::FCMP_OGE:
235 case CmpInst::ICMP_UGE:
236 case CmpInst::ICMP_SGE:
239 case CmpInst::FCMP_OLT:
240 case CmpInst::ICMP_ULT:
241 case CmpInst::ICMP_SLT:
244 case CmpInst::FCMP_OLE:
245 case CmpInst::ICMP_ULE:
246 case CmpInst::ICMP_SLE:
249 case CmpInst::FCMP_ONE:
250 case CmpInst::ICMP_NE:
253 case CmpInst::FCMP_ORD:
256 case CmpInst::FCMP_UNO:
261 // Determine whether the type Ty is simple enough to be handled by
262 // fast-isel, and return its equivalent machine type in VT.
263 // FIXME: Copied directly from ARM -- factor into base class?
264 bool PPCFastISel::isTypeLegal(Type *Ty, MVT &VT) {
265 EVT Evt = TLI.getValueType(DL, Ty, true);
267 // Only handle simple types.
268 if (Evt == MVT::Other || !Evt.isSimple()) return false;
269 VT = Evt.getSimpleVT();
271 // Handle all legal types, i.e. a register that will directly hold this
273 return TLI.isTypeLegal(VT);
276 // Determine whether the type Ty is simple enough to be handled by
277 // fast-isel as a load target, and return its equivalent machine type in VT.
278 bool PPCFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) {
279 if (isTypeLegal(Ty, VT)) return true;
281 // If this is a type than can be sign or zero-extended to a basic operation
282 // go ahead and accept it now.
283 if (VT == MVT::i8 || VT == MVT::i16 || VT == MVT::i32) {
290 bool PPCFastISel::isValueAvailable(const Value *V) const {
291 if (!isa<Instruction>(V))
294 const auto *I = cast<Instruction>(V);
295 if (FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB)
301 // Given a value Obj, create an Address object Addr that represents its
302 // address. Return false if we can't handle it.
303 bool PPCFastISel::PPCComputeAddress(const Value *Obj, Address &Addr) {
304 const User *U = nullptr;
305 unsigned Opcode = Instruction::UserOp1;
306 if (const Instruction *I = dyn_cast<Instruction>(Obj)) {
307 // Don't walk into other basic blocks unless the object is an alloca from
308 // another block, otherwise it may not have a virtual register assigned.
309 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) ||
310 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) {
311 Opcode = I->getOpcode();
314 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) {
315 Opcode = C->getOpcode();
322 case Instruction::BitCast:
323 // Look through bitcasts.
324 return PPCComputeAddress(U->getOperand(0), Addr);
325 case Instruction::IntToPtr:
326 // Look past no-op inttoptrs.
327 if (TLI.getValueType(DL, U->getOperand(0)->getType()) ==
328 TLI.getPointerTy(DL))
329 return PPCComputeAddress(U->getOperand(0), Addr);
331 case Instruction::PtrToInt:
332 // Look past no-op ptrtoints.
333 if (TLI.getValueType(DL, U->getType()) == TLI.getPointerTy(DL))
334 return PPCComputeAddress(U->getOperand(0), Addr);
336 case Instruction::GetElementPtr: {
337 Address SavedAddr = Addr;
338 long TmpOffset = Addr.Offset;
340 // Iterate through the GEP folding the constants into offsets where
342 gep_type_iterator GTI = gep_type_begin(U);
343 for (User::const_op_iterator II = U->op_begin() + 1, IE = U->op_end();
344 II != IE; ++II, ++GTI) {
345 const Value *Op = *II;
346 if (StructType *STy = dyn_cast<StructType>(*GTI)) {
347 const StructLayout *SL = DL.getStructLayout(STy);
348 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue();
349 TmpOffset += SL->getElementOffset(Idx);
351 uint64_t S = DL.getTypeAllocSize(GTI.getIndexedType());
353 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) {
354 // Constant-offset addressing.
355 TmpOffset += CI->getSExtValue() * S;
358 if (canFoldAddIntoGEP(U, Op)) {
359 // A compatible add with a constant operand. Fold the constant.
361 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1));
362 TmpOffset += CI->getSExtValue() * S;
363 // Iterate on the other operand.
364 Op = cast<AddOperator>(Op)->getOperand(0);
368 goto unsupported_gep;
373 // Try to grab the base operand now.
374 Addr.Offset = TmpOffset;
375 if (PPCComputeAddress(U->getOperand(0), Addr)) return true;
377 // We failed, restore everything and try the other options.
383 case Instruction::Alloca: {
384 const AllocaInst *AI = cast<AllocaInst>(Obj);
385 DenseMap<const AllocaInst*, int>::iterator SI =
386 FuncInfo.StaticAllocaMap.find(AI);
387 if (SI != FuncInfo.StaticAllocaMap.end()) {
388 Addr.BaseType = Address::FrameIndexBase;
389 Addr.Base.FI = SI->second;
396 // FIXME: References to parameters fall through to the behavior
397 // below. They should be able to reference a frame index since
398 // they are stored to the stack, so we can get "ld rx, offset(r1)"
399 // instead of "addi ry, r1, offset / ld rx, 0(ry)". Obj will
400 // just contain the parameter. Try to handle this with a FI.
402 // Try to get this in a register if nothing else has worked.
403 if (Addr.Base.Reg == 0)
404 Addr.Base.Reg = getRegForValue(Obj);
406 // Prevent assignment of base register to X0, which is inappropriate
407 // for loads and stores alike.
408 if (Addr.Base.Reg != 0)
409 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass);
411 return Addr.Base.Reg != 0;
414 // Fix up some addresses that can't be used directly. For example, if
415 // an offset won't fit in an instruction field, we may need to move it
416 // into an index register.
417 void PPCFastISel::PPCSimplifyAddress(Address &Addr, MVT VT, bool &UseOffset,
418 unsigned &IndexReg) {
420 // Check whether the offset fits in the instruction field.
421 if (!isInt<16>(Addr.Offset))
424 // If this is a stack pointer and the offset needs to be simplified then
425 // put the alloca address into a register, set the base type back to
426 // register and continue. This should almost never happen.
427 if (!UseOffset && Addr.BaseType == Address::FrameIndexBase) {
428 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
429 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
430 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0);
431 Addr.Base.Reg = ResultReg;
432 Addr.BaseType = Address::RegBase;
436 IntegerType *OffsetTy = ((VT == MVT::i32) ? Type::getInt32Ty(*Context)
437 : Type::getInt64Ty(*Context));
438 const ConstantInt *Offset =
439 ConstantInt::getSigned(OffsetTy, (int64_t)(Addr.Offset));
440 IndexReg = PPCMaterializeInt(Offset, MVT::i64);
441 assert(IndexReg && "Unexpected error in PPCMaterializeInt!");
445 // Emit a load instruction if possible, returning true if we succeeded,
446 // otherwise false. See commentary below for how the register class of
447 // the load is determined.
448 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
449 const TargetRegisterClass *RC,
450 bool IsZExt, unsigned FP64LoadOpc) {
452 bool UseOffset = true;
454 // If ResultReg is given, it determines the register class of the load.
455 // Otherwise, RC is the register class to use. If the result of the
456 // load isn't anticipated in this block, both may be zero, in which
457 // case we must make a conservative guess. In particular, don't assign
458 // R0 or X0 to the result register, as the result may be used in a load,
459 // store, add-immediate, or isel that won't permit this. (Though
460 // perhaps the spill and reload of live-exit values would handle this?)
461 const TargetRegisterClass *UseRC =
462 (ResultReg ? MRI.getRegClass(ResultReg) :
464 (VT == MVT::f64 ? &PPC::F8RCRegClass :
465 (VT == MVT::f32 ? &PPC::F4RCRegClass :
466 (VT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
467 &PPC::GPRC_and_GPRC_NOR0RegClass)))));
469 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass);
471 switch (VT.SimpleTy) {
472 default: // e.g., vector types not handled
475 Opc = Is32BitInt ? PPC::LBZ : PPC::LBZ8;
479 (Is32BitInt ? PPC::LHZ : PPC::LHZ8) :
480 (Is32BitInt ? PPC::LHA : PPC::LHA8));
484 (Is32BitInt ? PPC::LWZ : PPC::LWZ8) :
485 (Is32BitInt ? PPC::LWA_32 : PPC::LWA));
486 if ((Opc == PPC::LWA || Opc == PPC::LWA_32) && ((Addr.Offset & 3) != 0))
491 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) &&
492 "64-bit load with 32-bit target??");
493 UseOffset = ((Addr.Offset & 3) == 0);
503 // If necessary, materialize the offset into a register and use
504 // the indexed form. Also handle stack pointers with special needs.
505 unsigned IndexReg = 0;
506 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
508 // If this is a potential VSX load with an offset of 0, a VSX indexed load can
510 bool IsVSSRC = (ResultReg != 0) && isVSSRCRegister(ResultReg);
511 bool IsVSFRC = (ResultReg != 0) && isVSFRCRegister(ResultReg);
512 bool Is32VSXLoad = IsVSSRC && Opc == PPC::LFS;
513 bool Is64VSXLoad = IsVSSRC && Opc == PPC::LFD;
514 if ((Is32VSXLoad || Is64VSXLoad) &&
515 (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
516 (Addr.Offset == 0)) {
521 ResultReg = createResultReg(UseRC);
523 // Note: If we still have a frame index here, we know the offset is
524 // in range, as otherwise PPCSimplifyAddress would have converted it
526 if (Addr.BaseType == Address::FrameIndexBase) {
527 // VSX only provides an indexed load.
528 if (Is32VSXLoad || Is64VSXLoad) return false;
530 MachineMemOperand *MMO =
531 FuncInfo.MF->getMachineMemOperand(
532 MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset),
533 MachineMemOperand::MOLoad, MFI.getObjectSize(Addr.Base.FI),
534 MFI.getObjectAlignment(Addr.Base.FI));
536 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
537 .addImm(Addr.Offset).addFrameIndex(Addr.Base.FI).addMemOperand(MMO);
539 // Base reg with offset in range.
540 } else if (UseOffset) {
541 // VSX only provides an indexed load.
542 if (Is32VSXLoad || Is64VSXLoad) return false;
544 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
545 .addImm(Addr.Offset).addReg(Addr.Base.Reg);
549 // Get the RR opcode corresponding to the RI one. FIXME: It would be
550 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
551 // is hard to get at.
553 default: llvm_unreachable("Unexpected opcode!");
554 case PPC::LBZ: Opc = PPC::LBZX; break;
555 case PPC::LBZ8: Opc = PPC::LBZX8; break;
556 case PPC::LHZ: Opc = PPC::LHZX; break;
557 case PPC::LHZ8: Opc = PPC::LHZX8; break;
558 case PPC::LHA: Opc = PPC::LHAX; break;
559 case PPC::LHA8: Opc = PPC::LHAX8; break;
560 case PPC::LWZ: Opc = PPC::LWZX; break;
561 case PPC::LWZ8: Opc = PPC::LWZX8; break;
562 case PPC::LWA: Opc = PPC::LWAX; break;
563 case PPC::LWA_32: Opc = PPC::LWAX_32; break;
564 case PPC::LD: Opc = PPC::LDX; break;
565 case PPC::LFS: Opc = IsVSSRC ? PPC::LXSSPX : PPC::LFSX; break;
566 case PPC::LFD: Opc = IsVSFRC ? PPC::LXSDX : PPC::LFDX; break;
568 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
569 .addReg(Addr.Base.Reg).addReg(IndexReg);
575 // Attempt to fast-select a load instruction.
576 bool PPCFastISel::SelectLoad(const Instruction *I) {
577 // FIXME: No atomic loads are supported.
578 if (cast<LoadInst>(I)->isAtomic())
581 // Verify we have a legal type before going any further.
583 if (!isLoadTypeLegal(I->getType(), VT))
586 // See if we can handle this address.
588 if (!PPCComputeAddress(I->getOperand(0), Addr))
591 // Look at the currently assigned register for this instruction
592 // to determine the required register class. This is necessary
593 // to constrain RA from using R0/X0 when this is not legal.
594 unsigned AssignedReg = FuncInfo.ValueMap[I];
595 const TargetRegisterClass *RC =
596 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
598 unsigned ResultReg = 0;
599 if (!PPCEmitLoad(VT, ResultReg, Addr, RC))
601 updateValueMap(I, ResultReg);
605 // Emit a store instruction to store SrcReg at Addr.
606 bool PPCFastISel::PPCEmitStore(MVT VT, unsigned SrcReg, Address &Addr) {
607 assert(SrcReg && "Nothing to store!");
609 bool UseOffset = true;
611 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
612 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass);
614 switch (VT.SimpleTy) {
615 default: // e.g., vector types not handled
618 Opc = Is32BitInt ? PPC::STB : PPC::STB8;
621 Opc = Is32BitInt ? PPC::STH : PPC::STH8;
624 assert(Is32BitInt && "Not GPRC for i32??");
629 UseOffset = ((Addr.Offset & 3) == 0);
639 // If necessary, materialize the offset into a register and use
640 // the indexed form. Also handle stack pointers with special needs.
641 unsigned IndexReg = 0;
642 PPCSimplifyAddress(Addr, VT, UseOffset, IndexReg);
644 // If this is a potential VSX store with an offset of 0, a VSX indexed store
646 bool IsVSSRC = isVSSRCRegister(SrcReg);
647 bool IsVSFRC = isVSFRCRegister(SrcReg);
648 bool Is32VSXStore = IsVSSRC && Opc == PPC::STFS;
649 bool Is64VSXStore = IsVSFRC && Opc == PPC::STFD;
650 if ((Is32VSXStore || Is64VSXStore) &&
651 (Addr.BaseType != Address::FrameIndexBase) && UseOffset &&
652 (Addr.Offset == 0)) {
656 // Note: If we still have a frame index here, we know the offset is
657 // in range, as otherwise PPCSimplifyAddress would have converted it
659 if (Addr.BaseType == Address::FrameIndexBase) {
660 // VSX only provides an indexed store.
661 if (Is32VSXStore || Is64VSXStore) return false;
663 MachineMemOperand *MMO =
664 FuncInfo.MF->getMachineMemOperand(
665 MachinePointerInfo::getFixedStack(Addr.Base.FI, Addr.Offset),
666 MachineMemOperand::MOStore, MFI.getObjectSize(Addr.Base.FI),
667 MFI.getObjectAlignment(Addr.Base.FI));
669 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
672 .addFrameIndex(Addr.Base.FI)
675 // Base reg with offset in range.
676 } else if (UseOffset) {
677 // VSX only provides an indexed store.
678 if (Is32VSXStore || Is64VSXStore) return false;
680 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
681 .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
685 // Get the RR opcode corresponding to the RI one. FIXME: It would be
686 // preferable to use the ImmToIdxMap from PPCRegisterInfo.cpp, but it
687 // is hard to get at.
689 default: llvm_unreachable("Unexpected opcode!");
690 case PPC::STB: Opc = PPC::STBX; break;
691 case PPC::STH : Opc = PPC::STHX; break;
692 case PPC::STW : Opc = PPC::STWX; break;
693 case PPC::STB8: Opc = PPC::STBX8; break;
694 case PPC::STH8: Opc = PPC::STHX8; break;
695 case PPC::STW8: Opc = PPC::STWX8; break;
696 case PPC::STD: Opc = PPC::STDX; break;
697 case PPC::STFS: Opc = IsVSSRC ? PPC::STXSSPX : PPC::STFSX; break;
698 case PPC::STFD: Opc = IsVSFRC ? PPC::STXSDX : PPC::STFDX; break;
701 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
704 // If we have an index register defined we use it in the store inst,
705 // otherwise we use X0 as base as it makes the vector instructions to
706 // use zero in the computation of the effective address regardless the
707 // content of the register.
709 MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
711 MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
717 // Attempt to fast-select a store instruction.
718 bool PPCFastISel::SelectStore(const Instruction *I) {
719 Value *Op0 = I->getOperand(0);
722 // FIXME: No atomics loads are supported.
723 if (cast<StoreInst>(I)->isAtomic())
726 // Verify we have a legal type before going any further.
728 if (!isLoadTypeLegal(Op0->getType(), VT))
731 // Get the value to be stored into a register.
732 SrcReg = getRegForValue(Op0);
736 // See if we can handle this address.
738 if (!PPCComputeAddress(I->getOperand(1), Addr))
741 if (!PPCEmitStore(VT, SrcReg, Addr))
747 // Attempt to fast-select a branch instruction.
748 bool PPCFastISel::SelectBranch(const Instruction *I) {
749 const BranchInst *BI = cast<BranchInst>(I);
750 MachineBasicBlock *BrBB = FuncInfo.MBB;
751 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)];
752 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)];
754 // For now, just try the simplest case where it's fed by a compare.
755 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) {
756 if (isValueAvailable(CI)) {
757 Optional<PPC::Predicate> OptPPCPred = getComparePred(CI->getPredicate());
761 PPC::Predicate PPCPred = OptPPCPred.getValue();
763 // Take advantage of fall-through opportunities.
764 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) {
766 PPCPred = PPC::InvertPredicate(PPCPred);
769 unsigned CondReg = createResultReg(&PPC::CRRCRegClass);
771 if (!PPCEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned(),
775 BuildMI(*BrBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCC))
776 .addImm(PPCPred).addReg(CondReg).addMBB(TBB);
777 fastEmitBranch(FBB, DbgLoc);
778 FuncInfo.MBB->addSuccessor(TBB);
781 } else if (const ConstantInt *CI =
782 dyn_cast<ConstantInt>(BI->getCondition())) {
783 uint64_t Imm = CI->getZExtValue();
784 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
785 fastEmitBranch(Target, DbgLoc);
789 // FIXME: ARM looks for a case where the block containing the compare
790 // has been split from the block containing the branch. If this happens,
791 // there is a vreg available containing the result of the compare. I'm
792 // not sure we can do much, as we've lost the predicate information with
793 // the compare instruction -- we have a 4-bit CR but don't know which bit
798 // Attempt to emit a compare of the two source values. Signed and unsigned
799 // comparisons are supported. Return false if we can't handle it.
800 bool PPCFastISel::PPCEmitCmp(const Value *SrcValue1, const Value *SrcValue2,
801 bool IsZExt, unsigned DestReg) {
802 Type *Ty = SrcValue1->getType();
803 EVT SrcEVT = TLI.getValueType(DL, Ty, true);
804 if (!SrcEVT.isSimple())
806 MVT SrcVT = SrcEVT.getSimpleVT();
808 if (SrcVT == MVT::i1 && PPCSubTarget->useCRBits())
811 // See if operand 2 is an immediate encodeable in the compare.
812 // FIXME: Operands are not in canonical order at -O0, so an immediate
813 // operand in position 1 is a lost opportunity for now. We are
814 // similar to ARM in this regard.
818 // Only 16-bit integer constants can be represented in compares for
819 // PowerPC. Others will be materialized into a register.
820 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(SrcValue2)) {
821 if (SrcVT == MVT::i64 || SrcVT == MVT::i32 || SrcVT == MVT::i16 ||
822 SrcVT == MVT::i8 || SrcVT == MVT::i1) {
823 const APInt &CIVal = ConstInt->getValue();
824 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue();
825 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
831 bool NeedsExt = false;
832 switch (SrcVT.SimpleTy) {
833 default: return false;
835 CmpOpc = PPC::FCMPUS;
838 CmpOpc = PPC::FCMPUD;
844 // Intentional fall-through.
847 CmpOpc = IsZExt ? PPC::CMPLW : PPC::CMPW;
849 CmpOpc = IsZExt ? PPC::CMPLWI : PPC::CMPWI;
853 CmpOpc = IsZExt ? PPC::CMPLD : PPC::CMPD;
855 CmpOpc = IsZExt ? PPC::CMPLDI : PPC::CMPDI;
859 unsigned SrcReg1 = getRegForValue(SrcValue1);
863 unsigned SrcReg2 = 0;
865 SrcReg2 = getRegForValue(SrcValue2);
871 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
872 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
877 unsigned ExtReg = createResultReg(&PPC::GPRCRegClass);
878 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
885 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
886 .addReg(SrcReg1).addReg(SrcReg2);
888 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
889 .addReg(SrcReg1).addImm(Imm);
894 // Attempt to fast-select a floating-point extend instruction.
895 bool PPCFastISel::SelectFPExt(const Instruction *I) {
896 Value *Src = I->getOperand(0);
897 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
898 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
900 if (SrcVT != MVT::f32 || DestVT != MVT::f64)
903 unsigned SrcReg = getRegForValue(Src);
907 // No code is generated for a FP extend.
908 updateValueMap(I, SrcReg);
912 // Attempt to fast-select a floating-point truncate instruction.
913 bool PPCFastISel::SelectFPTrunc(const Instruction *I) {
914 Value *Src = I->getOperand(0);
915 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
916 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
918 if (SrcVT != MVT::f64 || DestVT != MVT::f32)
921 unsigned SrcReg = getRegForValue(Src);
925 // Round the result to single precision.
926 unsigned DestReg = createResultReg(&PPC::F4RCRegClass);
927 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP), DestReg)
930 updateValueMap(I, DestReg);
934 // Move an i32 or i64 value in a GPR to an f64 value in an FPR.
935 // FIXME: When direct register moves are implemented (see PowerISA 2.07),
936 // those should be used instead of moving via a stack slot when the
937 // subtarget permits.
938 // FIXME: The code here is sloppy for the 4-byte case. Can use a 4-byte
939 // stack slot and 4-byte store/load sequence. Or just sext the 4-byte
940 // case to 8 bytes which produces tighter code but wastes stack space.
941 unsigned PPCFastISel::PPCMoveToFPReg(MVT SrcVT, unsigned SrcReg,
944 // If necessary, extend 32-bit int to 64-bit.
945 if (SrcVT == MVT::i32) {
946 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
947 if (!PPCEmitIntExt(MVT::i32, SrcReg, MVT::i64, TmpReg, !IsSigned))
952 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
954 Addr.BaseType = Address::FrameIndexBase;
955 Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
957 // Store the value from the GPR.
958 if (!PPCEmitStore(MVT::i64, SrcReg, Addr))
961 // Load the integer value into an FPR. The kind of load used depends
962 // on a number of conditions.
963 unsigned LoadOpc = PPC::LFD;
965 if (SrcVT == MVT::i32) {
967 LoadOpc = PPC::LFIWZX;
968 Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
969 } else if (PPCSubTarget->hasLFIWAX()) {
970 LoadOpc = PPC::LFIWAX;
971 Addr.Offset = (PPCSubTarget->isLittleEndian()) ? 0 : 4;
975 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
976 unsigned ResultReg = 0;
977 if (!PPCEmitLoad(MVT::f64, ResultReg, Addr, RC, !IsSigned, LoadOpc))
983 // Attempt to fast-select an integer-to-floating-point conversion.
984 // FIXME: Once fast-isel has better support for VSX, conversions using
985 // direct moves should be implemented.
986 bool PPCFastISel::SelectIToFP(const Instruction *I, bool IsSigned) {
988 Type *DstTy = I->getType();
989 if (!isTypeLegal(DstTy, DstVT))
992 if (DstVT != MVT::f32 && DstVT != MVT::f64)
995 Value *Src = I->getOperand(0);
996 EVT SrcEVT = TLI.getValueType(DL, Src->getType(), true);
997 if (!SrcEVT.isSimple())
1000 MVT SrcVT = SrcEVT.getSimpleVT();
1002 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 &&
1003 SrcVT != MVT::i32 && SrcVT != MVT::i64)
1006 unsigned SrcReg = getRegForValue(Src);
1010 // We can only lower an unsigned convert if we have the newer
1011 // floating-point conversion operations.
1012 if (!IsSigned && !PPCSubTarget->hasFPCVT())
1015 // FIXME: For now we require the newer floating-point conversion operations
1016 // (which are present only on P7 and A2 server models) when converting
1017 // to single-precision float. Otherwise we have to generate a lot of
1018 // fiddly code to avoid double rounding. If necessary, the fiddly code
1019 // can be found in PPCTargetLowering::LowerINT_TO_FP().
1020 if (DstVT == MVT::f32 && !PPCSubTarget->hasFPCVT())
1023 // Extend the input if necessary.
1024 if (SrcVT == MVT::i8 || SrcVT == MVT::i16) {
1025 unsigned TmpReg = createResultReg(&PPC::G8RCRegClass);
1026 if (!PPCEmitIntExt(SrcVT, SrcReg, MVT::i64, TmpReg, !IsSigned))
1032 // Move the integer value to an FPR.
1033 unsigned FPReg = PPCMoveToFPReg(SrcVT, SrcReg, IsSigned);
1037 // Determine the opcode for the conversion.
1038 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1039 unsigned DestReg = createResultReg(RC);
1042 if (DstVT == MVT::f32)
1043 Opc = IsSigned ? PPC::FCFIDS : PPC::FCFIDUS;
1045 Opc = IsSigned ? PPC::FCFID : PPC::FCFIDU;
1047 // Generate the convert.
1048 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1051 updateValueMap(I, DestReg);
1055 // Move the floating-point value in SrcReg into an integer destination
1056 // register, and return the register (or zero if we can't handle it).
1057 // FIXME: When direct register moves are implemented (see PowerISA 2.07),
1058 // those should be used instead of moving via a stack slot when the
1059 // subtarget permits.
1060 unsigned PPCFastISel::PPCMoveToIntReg(const Instruction *I, MVT VT,
1061 unsigned SrcReg, bool IsSigned) {
1062 // Get a stack slot 8 bytes wide, aligned on an 8-byte boundary.
1063 // Note that if have STFIWX available, we could use a 4-byte stack
1064 // slot for i32, but this being fast-isel we'll just go with the
1065 // easiest code gen possible.
1067 Addr.BaseType = Address::FrameIndexBase;
1068 Addr.Base.FI = MFI.CreateStackObject(8, 8, false);
1070 // Store the value from the FPR.
1071 if (!PPCEmitStore(MVT::f64, SrcReg, Addr))
1074 // Reload it into a GPR. If we want an i32, modify the address
1075 // to have a 4-byte offset so we load from the right place.
1079 // Look at the currently assigned register for this instruction
1080 // to determine the required register class.
1081 unsigned AssignedReg = FuncInfo.ValueMap[I];
1082 const TargetRegisterClass *RC =
1083 AssignedReg ? MRI.getRegClass(AssignedReg) : nullptr;
1085 unsigned ResultReg = 0;
1086 if (!PPCEmitLoad(VT, ResultReg, Addr, RC, !IsSigned))
1092 // Attempt to fast-select a floating-point-to-integer conversion.
1093 // FIXME: Once fast-isel has better support for VSX, conversions using
1094 // direct moves should be implemented.
1095 bool PPCFastISel::SelectFPToI(const Instruction *I, bool IsSigned) {
1097 Type *DstTy = I->getType();
1098 if (!isTypeLegal(DstTy, DstVT))
1101 if (DstVT != MVT::i32 && DstVT != MVT::i64)
1104 // If we don't have FCTIDUZ and we need it, punt to SelectionDAG.
1105 if (DstVT == MVT::i64 && !IsSigned && !PPCSubTarget->hasFPCVT())
1108 Value *Src = I->getOperand(0);
1109 Type *SrcTy = Src->getType();
1110 if (!isTypeLegal(SrcTy, SrcVT))
1113 if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
1116 unsigned SrcReg = getRegForValue(Src);
1120 // Convert f32 to f64 if necessary. This is just a meaningless copy
1121 // to get the register class right. COPY_TO_REGCLASS is needed since
1122 // a COPY from F4RC to F8RC is converted to a F4RC-F4RC copy downstream.
1123 const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
1124 if (InRC == &PPC::F4RCRegClass) {
1125 unsigned TmpReg = createResultReg(&PPC::F8RCRegClass);
1126 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1127 TII.get(TargetOpcode::COPY_TO_REGCLASS), TmpReg)
1128 .addReg(SrcReg).addImm(PPC::F8RCRegClassID);
1132 // Determine the opcode for the conversion, which takes place
1133 // entirely within FPRs.
1134 unsigned DestReg = createResultReg(&PPC::F8RCRegClass);
1137 if (DstVT == MVT::i32)
1141 Opc = PPCSubTarget->hasFPCVT() ? PPC::FCTIWUZ : PPC::FCTIDZ;
1143 Opc = IsSigned ? PPC::FCTIDZ : PPC::FCTIDUZ;
1145 // Generate the convert.
1146 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1149 // Now move the integer value from a float register to an integer register.
1150 unsigned IntReg = PPCMoveToIntReg(I, DstVT, DestReg, IsSigned);
1154 updateValueMap(I, IntReg);
1158 // Attempt to fast-select a binary integer operation that isn't already
1159 // handled automatically.
1160 bool PPCFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) {
1161 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1163 // We can get here in the case when we have a binary operation on a non-legal
1164 // type and the target independent selector doesn't know how to handle it.
1165 if (DestVT != MVT::i16 && DestVT != MVT::i8)
1168 // Look at the currently assigned register for this instruction
1169 // to determine the required register class. If there is no register,
1170 // make a conservative choice (don't assign R0).
1171 unsigned AssignedReg = FuncInfo.ValueMap[I];
1172 const TargetRegisterClass *RC =
1173 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1174 &PPC::GPRC_and_GPRC_NOR0RegClass);
1175 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
1178 switch (ISDOpcode) {
1179 default: return false;
1181 Opc = IsGPRC ? PPC::ADD4 : PPC::ADD8;
1184 Opc = IsGPRC ? PPC::OR : PPC::OR8;
1187 Opc = IsGPRC ? PPC::SUBF : PPC::SUBF8;
1191 unsigned ResultReg = createResultReg(RC ? RC : &PPC::G8RCRegClass);
1192 unsigned SrcReg1 = getRegForValue(I->getOperand(0));
1193 if (SrcReg1 == 0) return false;
1195 // Handle case of small immediate operand.
1196 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(1))) {
1197 const APInt &CIVal = ConstInt->getValue();
1198 int Imm = (int)CIVal.getSExtValue();
1200 if (isInt<16>(Imm)) {
1203 llvm_unreachable("Missing case!");
1206 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1210 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1223 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass);
1232 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass);
1239 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1243 updateValueMap(I, ResultReg);
1250 unsigned SrcReg2 = getRegForValue(I->getOperand(1));
1251 if (SrcReg2 == 0) return false;
1253 // Reverse operands for subtract-from.
1254 if (ISDOpcode == ISD::SUB)
1255 std::swap(SrcReg1, SrcReg2);
1257 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1258 .addReg(SrcReg1).addReg(SrcReg2);
1259 updateValueMap(I, ResultReg);
1263 // Handle arguments to a call that we're attempting to fast-select.
1264 // Return false if the arguments are too complex for us at the moment.
1265 bool PPCFastISel::processCallArgs(SmallVectorImpl<Value*> &Args,
1266 SmallVectorImpl<unsigned> &ArgRegs,
1267 SmallVectorImpl<MVT> &ArgVTs,
1268 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags,
1269 SmallVectorImpl<unsigned> &RegArgs,
1273 SmallVector<CCValAssign, 16> ArgLocs;
1274 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, ArgLocs, *Context);
1276 // Reserve space for the linkage area on the stack.
1277 unsigned LinkageSize = PPCSubTarget->getFrameLowering()->getLinkageSize();
1278 CCInfo.AllocateStack(LinkageSize, 8);
1280 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, CC_PPC64_ELF_FIS);
1282 // Bail out if we can't handle any of the arguments.
1283 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1284 CCValAssign &VA = ArgLocs[I];
1285 MVT ArgVT = ArgVTs[VA.getValNo()];
1287 // Skip vector arguments for now, as well as long double and
1288 // uint128_t, and anything that isn't passed in a register.
1289 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64 || ArgVT == MVT::i1 ||
1290 !VA.isRegLoc() || VA.needsCustom())
1293 // Skip bit-converted arguments for now.
1294 if (VA.getLocInfo() == CCValAssign::BCvt)
1298 // Get a count of how many bytes are to be pushed onto the stack.
1299 NumBytes = CCInfo.getNextStackOffset();
1301 // The prolog code of the callee may store up to 8 GPR argument registers to
1302 // the stack, allowing va_start to index over them in memory if its varargs.
1303 // Because we cannot tell if this is needed on the caller side, we have to
1304 // conservatively assume that it is needed. As such, make sure we have at
1305 // least enough stack space for the caller to store the 8 GPRs.
1306 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
1307 NumBytes = std::max(NumBytes, LinkageSize + 64);
1309 // Issue CALLSEQ_START.
1310 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1311 TII.get(TII.getCallFrameSetupOpcode()))
1314 // Prepare to assign register arguments. Every argument uses up a
1315 // GPR protocol register even if it's passed in a floating-point
1316 // register (unless we're using the fast calling convention).
1317 unsigned NextGPR = PPC::X3;
1318 unsigned NextFPR = PPC::F1;
1320 // Process arguments.
1321 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1322 CCValAssign &VA = ArgLocs[I];
1323 unsigned Arg = ArgRegs[VA.getValNo()];
1324 MVT ArgVT = ArgVTs[VA.getValNo()];
1326 // Handle argument promotion and bitcasts.
1327 switch (VA.getLocInfo()) {
1329 llvm_unreachable("Unknown loc info!");
1330 case CCValAssign::Full:
1332 case CCValAssign::SExt: {
1333 MVT DestVT = VA.getLocVT();
1334 const TargetRegisterClass *RC =
1335 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1336 unsigned TmpReg = createResultReg(RC);
1337 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/false))
1338 llvm_unreachable("Failed to emit a sext!");
1343 case CCValAssign::AExt:
1344 case CCValAssign::ZExt: {
1345 MVT DestVT = VA.getLocVT();
1346 const TargetRegisterClass *RC =
1347 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1348 unsigned TmpReg = createResultReg(RC);
1349 if (!PPCEmitIntExt(ArgVT, Arg, DestVT, TmpReg, /*IsZExt*/true))
1350 llvm_unreachable("Failed to emit a zext!");
1355 case CCValAssign::BCvt: {
1356 // FIXME: Not yet handled.
1357 llvm_unreachable("Should have bailed before getting here!");
1362 // Copy this argument to the appropriate register.
1364 if (ArgVT == MVT::f32 || ArgVT == MVT::f64) {
1366 if (CC != CallingConv::Fast)
1371 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1372 TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg);
1373 RegArgs.push_back(ArgReg);
1379 // For a call that we've determined we can fast-select, finish the
1380 // call sequence and generate a copy to obtain the return value (if any).
1381 bool PPCFastISel::finishCall(MVT RetVT, CallLoweringInfo &CLI, unsigned &NumBytes) {
1382 CallingConv::ID CC = CLI.CallConv;
1384 // Issue CallSEQ_END.
1385 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1386 TII.get(TII.getCallFrameDestroyOpcode()))
1387 .addImm(NumBytes).addImm(0);
1389 // Next, generate a copy to obtain the return value.
1390 // FIXME: No multi-register return values yet, though I don't foresee
1391 // any real difficulties there.
1392 if (RetVT != MVT::isVoid) {
1393 SmallVector<CCValAssign, 16> RVLocs;
1394 CCState CCInfo(CC, false, *FuncInfo.MF, RVLocs, *Context);
1395 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1396 CCValAssign &VA = RVLocs[0];
1397 assert(RVLocs.size() == 1 && "No support for multi-reg return values!");
1398 assert(VA.isRegLoc() && "Can only return in registers!");
1400 MVT DestVT = VA.getValVT();
1401 MVT CopyVT = DestVT;
1403 // Ints smaller than a register still arrive in a full 64-bit
1404 // register, so make sure we recognize this.
1405 if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32)
1408 unsigned SourcePhysReg = VA.getLocReg();
1409 unsigned ResultReg = 0;
1411 if (RetVT == CopyVT) {
1412 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
1413 ResultReg = createResultReg(CpyRC);
1415 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1416 TII.get(TargetOpcode::COPY), ResultReg)
1417 .addReg(SourcePhysReg);
1419 // If necessary, round the floating result to single precision.
1420 } else if (CopyVT == MVT::f64) {
1421 ResultReg = createResultReg(TLI.getRegClassFor(RetVT));
1422 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP),
1423 ResultReg).addReg(SourcePhysReg);
1425 // If only the low half of a general register is needed, generate
1426 // a GPRC copy instead of a G8RC copy. (EXTRACT_SUBREG can't be
1427 // used along the fast-isel path (not lowered), and downstream logic
1428 // also doesn't like a direct subreg copy on a physical reg.)
1429 } else if (RetVT == MVT::i8 || RetVT == MVT::i16 || RetVT == MVT::i32) {
1430 ResultReg = createResultReg(&PPC::GPRCRegClass);
1431 // Convert physical register from G8RC to GPRC.
1432 SourcePhysReg -= PPC::X0 - PPC::R0;
1433 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1434 TII.get(TargetOpcode::COPY), ResultReg)
1435 .addReg(SourcePhysReg);
1438 assert(ResultReg && "ResultReg unset!");
1439 CLI.InRegs.push_back(SourcePhysReg);
1440 CLI.ResultReg = ResultReg;
1441 CLI.NumResultRegs = 1;
1447 bool PPCFastISel::fastLowerCall(CallLoweringInfo &CLI) {
1448 CallingConv::ID CC = CLI.CallConv;
1449 bool IsTailCall = CLI.IsTailCall;
1450 bool IsVarArg = CLI.IsVarArg;
1451 const Value *Callee = CLI.Callee;
1452 const MCSymbol *Symbol = CLI.Symbol;
1454 if (!Callee && !Symbol)
1457 // Allow SelectionDAG isel to handle tail calls.
1461 // Let SDISel handle vararg functions.
1465 // Handle simple calls for now, with legal return types and
1466 // those that can be extended.
1467 Type *RetTy = CLI.RetTy;
1469 if (RetTy->isVoidTy())
1470 RetVT = MVT::isVoid;
1471 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 &&
1474 else if (RetVT == MVT::i1 && PPCSubTarget->useCRBits())
1475 // We can't handle boolean returns when CR bits are in use.
1478 // FIXME: No multi-register return values yet.
1479 if (RetVT != MVT::isVoid && RetVT != MVT::i8 && RetVT != MVT::i16 &&
1480 RetVT != MVT::i32 && RetVT != MVT::i64 && RetVT != MVT::f32 &&
1481 RetVT != MVT::f64) {
1482 SmallVector<CCValAssign, 16> RVLocs;
1483 CCState CCInfo(CC, IsVarArg, *FuncInfo.MF, RVLocs, *Context);
1484 CCInfo.AnalyzeCallResult(RetVT, RetCC_PPC64_ELF_FIS);
1485 if (RVLocs.size() > 1)
1489 // Bail early if more than 8 arguments, as we only currently
1490 // handle arguments passed in registers.
1491 unsigned NumArgs = CLI.OutVals.size();
1495 // Set up the argument vectors.
1496 SmallVector<Value*, 8> Args;
1497 SmallVector<unsigned, 8> ArgRegs;
1498 SmallVector<MVT, 8> ArgVTs;
1499 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags;
1501 Args.reserve(NumArgs);
1502 ArgRegs.reserve(NumArgs);
1503 ArgVTs.reserve(NumArgs);
1504 ArgFlags.reserve(NumArgs);
1506 for (unsigned i = 0, ie = NumArgs; i != ie; ++i) {
1507 // Only handle easy calls for now. It would be reasonably easy
1508 // to handle <= 8-byte structures passed ByVal in registers, but we
1509 // have to ensure they are right-justified in the register.
1510 ISD::ArgFlagsTy Flags = CLI.OutFlags[i];
1511 if (Flags.isInReg() || Flags.isSRet() || Flags.isNest() || Flags.isByVal())
1514 Value *ArgValue = CLI.OutVals[i];
1515 Type *ArgTy = ArgValue->getType();
1517 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8)
1520 if (ArgVT.isVector())
1523 unsigned Arg = getRegForValue(ArgValue);
1527 Args.push_back(ArgValue);
1528 ArgRegs.push_back(Arg);
1529 ArgVTs.push_back(ArgVT);
1530 ArgFlags.push_back(Flags);
1533 // Process the arguments.
1534 SmallVector<unsigned, 8> RegArgs;
1537 if (!processCallArgs(Args, ArgRegs, ArgVTs, ArgFlags,
1538 RegArgs, CC, NumBytes, IsVarArg))
1541 MachineInstrBuilder MIB;
1542 // FIXME: No handling for function pointers yet. This requires
1543 // implementing the function descriptor (OPD) setup.
1544 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee);
1546 // patchpoints are a special case; they always dispatch to a pointer value.
1547 // However, we don't actually want to generate the indirect call sequence
1548 // here (that will be generated, as necessary, during asm printing), and
1549 // the call we generate here will be erased by FastISel::selectPatchpoint,
1550 // so don't try very hard...
1551 if (CLI.IsPatchPoint)
1552 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::NOP));
1556 // Build direct call with NOP for TOC restore.
1557 // FIXME: We can and should optimize away the NOP for local calls.
1558 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1559 TII.get(PPC::BL8_NOP));
1561 MIB.addGlobalAddress(GV);
1564 // Add implicit physical register uses to the call.
1565 for (unsigned II = 0, IE = RegArgs.size(); II != IE; ++II)
1566 MIB.addReg(RegArgs[II], RegState::Implicit);
1568 // Direct calls, in both the ELF V1 and V2 ABIs, need the TOC register live
1570 PPCFuncInfo->setUsesTOCBasePtr();
1571 MIB.addReg(PPC::X2, RegState::Implicit);
1573 // Add a register mask with the call-preserved registers. Proper
1574 // defs for return values will be added by setPhysRegsDeadExcept().
1575 MIB.addRegMask(TRI.getCallPreservedMask(*FuncInfo.MF, CC));
1579 // Finish off the call including any return values.
1580 return finishCall(RetVT, CLI, NumBytes);
1583 // Attempt to fast-select a return instruction.
1584 bool PPCFastISel::SelectRet(const Instruction *I) {
1586 if (!FuncInfo.CanLowerReturn)
1589 const ReturnInst *Ret = cast<ReturnInst>(I);
1590 const Function &F = *I->getParent()->getParent();
1592 // Build a list of return value registers.
1593 SmallVector<unsigned, 4> RetRegs;
1594 CallingConv::ID CC = F.getCallingConv();
1596 if (Ret->getNumOperands() > 0) {
1597 SmallVector<ISD::OutputArg, 4> Outs;
1598 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI, DL);
1600 // Analyze operands of the call, assigning locations to each operand.
1601 SmallVector<CCValAssign, 16> ValLocs;
1602 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, ValLocs, *Context);
1603 CCInfo.AnalyzeReturn(Outs, RetCC_PPC64_ELF_FIS);
1604 const Value *RV = Ret->getOperand(0);
1606 // FIXME: Only one output register for now.
1607 if (ValLocs.size() > 1)
1610 // Special case for returning a constant integer of any size.
1611 // Materialize the constant as an i64 and copy it to the return
1612 // register. We still need to worry about properly extending the sign. E.g:
1613 // If the constant has only one bit, it means it is a boolean. Therefore
1614 // we can't use PPCMaterializeInt because it extends the sign which will
1615 // cause negations of the returned value to be incorrect as they are
1616 // implemented as the flip of the least significant bit.
1617 if (isa<ConstantInt>(*RV)) {
1618 const Constant *C = cast<Constant>(RV);
1620 CCValAssign &VA = ValLocs[0];
1622 unsigned RetReg = VA.getLocReg();
1623 unsigned SrcReg = PPCMaterializeInt(C, MVT::i64,
1624 VA.getLocInfo() == CCValAssign::SExt);
1626 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1627 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
1629 RetRegs.push_back(RetReg);
1632 unsigned Reg = getRegForValue(RV);
1637 // Copy the result values into the output registers.
1638 for (unsigned i = 0; i < ValLocs.size(); ++i) {
1640 CCValAssign &VA = ValLocs[i];
1641 assert(VA.isRegLoc() && "Can only return in registers!");
1642 RetRegs.push_back(VA.getLocReg());
1643 unsigned SrcReg = Reg + VA.getValNo();
1645 EVT RVEVT = TLI.getValueType(DL, RV->getType());
1646 if (!RVEVT.isSimple())
1648 MVT RVVT = RVEVT.getSimpleVT();
1649 MVT DestVT = VA.getLocVT();
1651 if (RVVT != DestVT && RVVT != MVT::i8 &&
1652 RVVT != MVT::i16 && RVVT != MVT::i32)
1655 if (RVVT != DestVT) {
1656 switch (VA.getLocInfo()) {
1658 llvm_unreachable("Unknown loc info!");
1659 case CCValAssign::Full:
1660 llvm_unreachable("Full value assign but types don't match?");
1661 case CCValAssign::AExt:
1662 case CCValAssign::ZExt: {
1663 const TargetRegisterClass *RC =
1664 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1665 unsigned TmpReg = createResultReg(RC);
1666 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, true))
1671 case CCValAssign::SExt: {
1672 const TargetRegisterClass *RC =
1673 (DestVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
1674 unsigned TmpReg = createResultReg(RC);
1675 if (!PPCEmitIntExt(RVVT, SrcReg, DestVT, TmpReg, false))
1683 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1684 TII.get(TargetOpcode::COPY), RetRegs[i])
1690 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1691 TII.get(PPC::BLR8));
1693 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i)
1694 MIB.addReg(RetRegs[i], RegState::Implicit);
1699 // Attempt to emit an integer extend of SrcReg into DestReg. Both
1700 // signed and zero extensions are supported. Return false if we
1702 bool PPCFastISel::PPCEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT,
1703 unsigned DestReg, bool IsZExt) {
1704 if (DestVT != MVT::i32 && DestVT != MVT::i64)
1706 if (SrcVT != MVT::i8 && SrcVT != MVT::i16 && SrcVT != MVT::i32)
1709 // Signed extensions use EXTSB, EXTSH, EXTSW.
1712 if (SrcVT == MVT::i8)
1713 Opc = (DestVT == MVT::i32) ? PPC::EXTSB : PPC::EXTSB8_32_64;
1714 else if (SrcVT == MVT::i16)
1715 Opc = (DestVT == MVT::i32) ? PPC::EXTSH : PPC::EXTSH8_32_64;
1717 assert(DestVT == MVT::i64 && "Signed extend from i32 to i32??");
1718 Opc = PPC::EXTSW_32_64;
1720 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1723 // Unsigned 32-bit extensions use RLWINM.
1724 } else if (DestVT == MVT::i32) {
1726 if (SrcVT == MVT::i8)
1729 assert(SrcVT == MVT::i16 && "Unsigned extend from i32 to i32??");
1732 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLWINM),
1734 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
1736 // Unsigned 64-bit extensions use RLDICL (with a 32-bit source).
1739 if (SrcVT == MVT::i8)
1741 else if (SrcVT == MVT::i16)
1745 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1746 TII.get(PPC::RLDICL_32_64), DestReg)
1747 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB);
1753 // Attempt to fast-select an indirect branch instruction.
1754 bool PPCFastISel::SelectIndirectBr(const Instruction *I) {
1755 unsigned AddrReg = getRegForValue(I->getOperand(0));
1759 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::MTCTR8))
1761 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::BCTR8));
1763 const IndirectBrInst *IB = cast<IndirectBrInst>(I);
1764 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i)
1765 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]);
1770 // Attempt to fast-select an integer truncate instruction.
1771 bool PPCFastISel::SelectTrunc(const Instruction *I) {
1772 Value *Src = I->getOperand(0);
1773 EVT SrcVT = TLI.getValueType(DL, Src->getType(), true);
1774 EVT DestVT = TLI.getValueType(DL, I->getType(), true);
1776 if (SrcVT != MVT::i64 && SrcVT != MVT::i32 && SrcVT != MVT::i16)
1779 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8)
1782 unsigned SrcReg = getRegForValue(Src);
1786 // The only interesting case is when we need to switch register classes.
1787 if (SrcVT == MVT::i64) {
1788 unsigned ResultReg = createResultReg(&PPC::GPRCRegClass);
1789 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1790 TII.get(TargetOpcode::COPY),
1791 ResultReg).addReg(SrcReg, 0, PPC::sub_32);
1795 updateValueMap(I, SrcReg);
1799 // Attempt to fast-select an integer extend instruction.
1800 bool PPCFastISel::SelectIntExt(const Instruction *I) {
1801 Type *DestTy = I->getType();
1802 Value *Src = I->getOperand(0);
1803 Type *SrcTy = Src->getType();
1805 bool IsZExt = isa<ZExtInst>(I);
1806 unsigned SrcReg = getRegForValue(Src);
1807 if (!SrcReg) return false;
1809 EVT SrcEVT, DestEVT;
1810 SrcEVT = TLI.getValueType(DL, SrcTy, true);
1811 DestEVT = TLI.getValueType(DL, DestTy, true);
1812 if (!SrcEVT.isSimple())
1814 if (!DestEVT.isSimple())
1817 MVT SrcVT = SrcEVT.getSimpleVT();
1818 MVT DestVT = DestEVT.getSimpleVT();
1820 // If we know the register class needed for the result of this
1821 // instruction, use it. Otherwise pick the register class of the
1822 // correct size that does not contain X0/R0, since we don't know
1823 // whether downstream uses permit that assignment.
1824 unsigned AssignedReg = FuncInfo.ValueMap[I];
1825 const TargetRegisterClass *RC =
1826 (AssignedReg ? MRI.getRegClass(AssignedReg) :
1827 (DestVT == MVT::i64 ? &PPC::G8RC_and_G8RC_NOX0RegClass :
1828 &PPC::GPRC_and_GPRC_NOR0RegClass));
1829 unsigned ResultReg = createResultReg(RC);
1831 if (!PPCEmitIntExt(SrcVT, SrcReg, DestVT, ResultReg, IsZExt))
1834 updateValueMap(I, ResultReg);
1838 // Attempt to fast-select an instruction that wasn't handled by
1839 // the table-generated machinery.
1840 bool PPCFastISel::fastSelectInstruction(const Instruction *I) {
1842 switch (I->getOpcode()) {
1843 case Instruction::Load:
1844 return SelectLoad(I);
1845 case Instruction::Store:
1846 return SelectStore(I);
1847 case Instruction::Br:
1848 return SelectBranch(I);
1849 case Instruction::IndirectBr:
1850 return SelectIndirectBr(I);
1851 case Instruction::FPExt:
1852 return SelectFPExt(I);
1853 case Instruction::FPTrunc:
1854 return SelectFPTrunc(I);
1855 case Instruction::SIToFP:
1856 return SelectIToFP(I, /*IsSigned*/ true);
1857 case Instruction::UIToFP:
1858 return SelectIToFP(I, /*IsSigned*/ false);
1859 case Instruction::FPToSI:
1860 return SelectFPToI(I, /*IsSigned*/ true);
1861 case Instruction::FPToUI:
1862 return SelectFPToI(I, /*IsSigned*/ false);
1863 case Instruction::Add:
1864 return SelectBinaryIntOp(I, ISD::ADD);
1865 case Instruction::Or:
1866 return SelectBinaryIntOp(I, ISD::OR);
1867 case Instruction::Sub:
1868 return SelectBinaryIntOp(I, ISD::SUB);
1869 case Instruction::Call:
1870 return selectCall(I);
1871 case Instruction::Ret:
1872 return SelectRet(I);
1873 case Instruction::Trunc:
1874 return SelectTrunc(I);
1875 case Instruction::ZExt:
1876 case Instruction::SExt:
1877 return SelectIntExt(I);
1878 // Here add other flavors of Instruction::XXX that automated
1879 // cases don't catch. For example, switches are terminators
1880 // that aren't yet handled.
1887 // Materialize a floating-point constant into a register, and return
1888 // the register number (or zero if we failed to handle it).
1889 unsigned PPCFastISel::PPCMaterializeFP(const ConstantFP *CFP, MVT VT) {
1890 // No plans to handle long double here.
1891 if (VT != MVT::f32 && VT != MVT::f64)
1894 // All FP constants are loaded from the constant pool.
1895 unsigned Align = DL.getPrefTypeAlignment(CFP->getType());
1896 assert(Align > 0 && "Unexpectedly missing alignment information!");
1897 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align);
1898 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT));
1899 CodeModel::Model CModel = TM.getCodeModel();
1901 MachineMemOperand *MMO =
1902 FuncInfo.MF->getMachineMemOperand(
1903 MachinePointerInfo::getConstantPool(), MachineMemOperand::MOLoad,
1904 (VT == MVT::f32) ? 4 : 8, Align);
1906 unsigned Opc = (VT == MVT::f32) ? PPC::LFS : PPC::LFD;
1907 unsigned TmpReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
1909 PPCFuncInfo->setUsesTOCBasePtr();
1910 // For small code model, generate a LF[SD](0, LDtocCPT(Idx, X2)).
1911 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault) {
1912 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT),
1914 .addConstantPoolIndex(Idx).addReg(PPC::X2);
1915 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1916 .addImm(0).addReg(TmpReg).addMemOperand(MMO);
1918 // Otherwise we generate LF[SD](Idx[lo], ADDIStocHA(X2, Idx)).
1919 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
1920 TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
1921 // But for large code model, we must generate a LDtocL followed
1923 if (CModel == CodeModel::Large) {
1924 unsigned TmpReg2 = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
1925 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
1926 TmpReg2).addConstantPoolIndex(Idx).addReg(TmpReg);
1927 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1928 .addImm(0).addReg(TmpReg2);
1930 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1931 .addConstantPoolIndex(Idx, 0, PPCII::MO_TOC_LO)
1933 .addMemOperand(MMO);
1939 // Materialize the address of a global value into a register, and return
1940 // the register number (or zero if we failed to handle it).
1941 unsigned PPCFastISel::PPCMaterializeGV(const GlobalValue *GV, MVT VT) {
1942 assert(VT == MVT::i64 && "Non-address!");
1943 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass;
1944 unsigned DestReg = createResultReg(RC);
1946 // Global values may be plain old object addresses, TLS object
1947 // addresses, constant pool entries, or jump tables. How we generate
1948 // code for these may depend on small, medium, or large code model.
1949 CodeModel::Model CModel = TM.getCodeModel();
1951 // FIXME: Jump tables are not yet required because fast-isel doesn't
1952 // handle switches; if that changes, we need them as well. For now,
1953 // what follows assumes everything's a generic (or TLS) global address.
1955 // FIXME: We don't yet handle the complexity of TLS.
1956 if (GV->isThreadLocal())
1959 PPCFuncInfo->setUsesTOCBasePtr();
1960 // For small code model, generate a simple TOC load.
1961 if (CModel == CodeModel::Small || CModel == CodeModel::JITDefault)
1962 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtoc),
1964 .addGlobalAddress(GV)
1967 // If the address is an externally defined symbol, a symbol with common
1968 // or externally available linkage, a non-local function address, or a
1969 // jump table address (not yet needed), or if we are generating code
1970 // for large code model, we generate:
1971 // LDtocL(GV, ADDIStocHA(%X2, GV))
1972 // Otherwise we generate:
1973 // ADDItocL(ADDIStocHA(%X2, GV), GV)
1974 // Either way, start with the ADDIStocHA:
1975 unsigned HighPartReg = createResultReg(RC);
1976 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA),
1977 HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
1979 // If/when switches are implemented, jump tables should be handled
1980 // on the "if" path here.
1981 if (CModel == CodeModel::Large ||
1982 (GV->getType()->getElementType()->isFunctionTy() &&
1983 !GV->isStrongDefinitionForLinker()) ||
1984 GV->isDeclaration() || GV->hasCommonLinkage() ||
1985 GV->hasAvailableExternallyLinkage())
1986 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
1987 DestReg).addGlobalAddress(GV).addReg(HighPartReg);
1989 // Otherwise generate the ADDItocL.
1990 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDItocL),
1991 DestReg).addReg(HighPartReg).addGlobalAddress(GV);
1997 // Materialize a 32-bit integer constant into a register, and return
1998 // the register number (or zero if we failed to handle it).
1999 unsigned PPCFastISel::PPCMaterialize32BitInt(int64_t Imm,
2000 const TargetRegisterClass *RC) {
2001 unsigned Lo = Imm & 0xFFFF;
2002 unsigned Hi = (Imm >> 16) & 0xFFFF;
2004 unsigned ResultReg = createResultReg(RC);
2005 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);
2008 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2009 TII.get(IsGPRC ? PPC::LI : PPC::LI8), ResultReg)
2012 // Both Lo and Hi have nonzero bits.
2013 unsigned TmpReg = createResultReg(RC);
2014 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2015 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), TmpReg)
2017 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2018 TII.get(IsGPRC ? PPC::ORI : PPC::ORI8), ResultReg)
2019 .addReg(TmpReg).addImm(Lo);
2022 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2023 TII.get(IsGPRC ? PPC::LIS : PPC::LIS8), ResultReg)
2029 // Materialize a 64-bit integer constant into a register, and return
2030 // the register number (or zero if we failed to handle it).
2031 unsigned PPCFastISel::PPCMaterialize64BitInt(int64_t Imm,
2032 const TargetRegisterClass *RC) {
2033 unsigned Remainder = 0;
2036 // If the value doesn't fit in 32 bits, see if we can shift it
2037 // so that it fits in 32 bits.
2038 if (!isInt<32>(Imm)) {
2039 Shift = countTrailingZeros<uint64_t>(Imm);
2040 int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
2042 if (isInt<32>(ImmSh))
2051 // Handle the high-order 32 bits (if shifted) or the whole 32 bits
2052 // (if not shifted).
2053 unsigned TmpReg1 = PPCMaterialize32BitInt(Imm, RC);
2057 // If upper 32 bits were not zero, we've built them and need to shift
2061 TmpReg2 = createResultReg(RC);
2062 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLDICR),
2063 TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
2067 unsigned TmpReg3, Hi, Lo;
2068 if ((Hi = (Remainder >> 16) & 0xFFFF)) {
2069 TmpReg3 = createResultReg(RC);
2070 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORIS8),
2071 TmpReg3).addReg(TmpReg2).addImm(Hi);
2075 if ((Lo = Remainder & 0xFFFF)) {
2076 unsigned ResultReg = createResultReg(RC);
2077 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORI8),
2078 ResultReg).addReg(TmpReg3).addImm(Lo);
2086 // Materialize an integer constant into a register, and return
2087 // the register number (or zero if we failed to handle it).
2088 unsigned PPCFastISel::PPCMaterializeInt(const Constant *C, MVT VT,
2090 // If we're using CR bit registers for i1 values, handle that as a special
2092 if (VT == MVT::i1 && PPCSubTarget->useCRBits()) {
2093 const ConstantInt *CI = cast<ConstantInt>(C);
2094 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2095 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2096 TII.get(CI->isZero() ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2100 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
2101 VT != MVT::i8 && VT != MVT::i1)
2104 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2105 &PPC::GPRCRegClass);
2107 // If the constant is in range, use a load-immediate.
2108 const ConstantInt *CI = cast<ConstantInt>(C);
2109 if (isInt<16>(CI->getSExtValue())) {
2110 unsigned Opc = (VT == MVT::i64) ? PPC::LI8 : PPC::LI;
2111 unsigned ImmReg = createResultReg(RC);
2112 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
2113 .addImm( (UseSExt) ? CI->getSExtValue() : CI->getZExtValue() );
2117 // Construct the constant piecewise.
2118 int64_t Imm = CI->getZExtValue();
2121 return PPCMaterialize64BitInt(Imm, RC);
2122 else if (VT == MVT::i32)
2123 return PPCMaterialize32BitInt(Imm, RC);
2128 // Materialize a constant into a register, and return the register
2129 // number (or zero if we failed to handle it).
2130 unsigned PPCFastISel::fastMaterializeConstant(const Constant *C) {
2131 EVT CEVT = TLI.getValueType(DL, C->getType(), true);
2133 // Only handle simple types.
2134 if (!CEVT.isSimple()) return 0;
2135 MVT VT = CEVT.getSimpleVT();
2137 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C))
2138 return PPCMaterializeFP(CFP, VT);
2139 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C))
2140 return PPCMaterializeGV(GV, VT);
2141 else if (isa<ConstantInt>(C))
2142 return PPCMaterializeInt(C, VT, VT != MVT::i1);
2147 // Materialize the address created by an alloca into a register, and
2148 // return the register number (or zero if we failed to handle it).
2149 unsigned PPCFastISel::fastMaterializeAlloca(const AllocaInst *AI) {
2150 // Don't handle dynamic allocas.
2151 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0;
2154 if (!isLoadTypeLegal(AI->getType(), VT)) return 0;
2156 DenseMap<const AllocaInst*, int>::iterator SI =
2157 FuncInfo.StaticAllocaMap.find(AI);
2159 if (SI != FuncInfo.StaticAllocaMap.end()) {
2160 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass);
2161 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
2162 ResultReg).addFrameIndex(SI->second).addImm(0);
2169 // Fold loads into extends when possible.
2170 // FIXME: We can have multiple redundant extend/trunc instructions
2171 // following a load. The folding only picks up one. Extend this
2172 // to check subsequent instructions for the same pattern and remove
2173 // them. Thus ResultReg should be the def reg for the last redundant
2174 // instruction in a chain, and all intervening instructions can be
2175 // removed from parent. Change test/CodeGen/PowerPC/fast-isel-fold.ll
2176 // to add ELF64-NOT: rldicl to the appropriate tests when this works.
2177 bool PPCFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
2178 const LoadInst *LI) {
2179 // Verify we have a legal type before going any further.
2181 if (!isLoadTypeLegal(LI->getType(), VT))
2184 // Combine load followed by zero- or sign-extend.
2185 bool IsZExt = false;
2186 switch(MI->getOpcode()) {
2191 case PPC::RLDICL_32_64: {
2193 unsigned MB = MI->getOperand(3).getImm();
2194 if ((VT == MVT::i8 && MB <= 56) ||
2195 (VT == MVT::i16 && MB <= 48) ||
2196 (VT == MVT::i32 && MB <= 32))
2202 case PPC::RLWINM8: {
2204 unsigned MB = MI->getOperand(3).getImm();
2205 if ((VT == MVT::i8 && MB <= 24) ||
2206 (VT == MVT::i16 && MB <= 16))
2213 case PPC::EXTSB8_32_64:
2214 /* There is no sign-extending load-byte instruction. */
2219 case PPC::EXTSH8_32_64: {
2220 if (VT != MVT::i16 && VT != MVT::i8)
2226 case PPC::EXTSW_32_64: {
2227 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8)
2233 // See if we can handle this address.
2235 if (!PPCComputeAddress(LI->getOperand(0), Addr))
2238 unsigned ResultReg = MI->getOperand(0).getReg();
2240 if (!PPCEmitLoad(VT, ResultReg, Addr, nullptr, IsZExt))
2243 MI->eraseFromParent();
2247 // Attempt to lower call arguments in a faster way than done by
2248 // the selection DAG code.
2249 bool PPCFastISel::fastLowerArguments() {
2250 // Defer to normal argument lowering for now. It's reasonably
2251 // efficient. Consider doing something like ARM to handle the
2252 // case where all args fit in registers, no varargs, no float
2257 // Handle materializing integer constants into a register. This is not
2258 // automatically generated for PowerPC, so must be explicitly created here.
2259 unsigned PPCFastISel::fastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) {
2261 if (Opc != ISD::Constant)
2264 // If we're using CR bit registers for i1 values, handle that as a special
2266 if (VT == MVT::i1 && PPCSubTarget->useCRBits()) {
2267 unsigned ImmReg = createResultReg(&PPC::CRBITRCRegClass);
2268 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2269 TII.get(Imm == 0 ? PPC::CRUNSET : PPC::CRSET), ImmReg);
2273 if (VT != MVT::i64 && VT != MVT::i32 && VT != MVT::i16 &&
2274 VT != MVT::i8 && VT != MVT::i1)
2277 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2278 &PPC::GPRCRegClass);
2280 return PPCMaterialize64BitInt(Imm, RC);
2282 return PPCMaterialize32BitInt(Imm, RC);
2285 // Override for ADDI and ADDI8 to set the correct register class
2286 // on RHS operand 0. The automatic infrastructure naively assumes
2287 // GPRC for i32 and G8RC for i64; the concept of "no R0" is lost
2288 // for these cases. At the moment, none of the other automatically
2289 // generated RI instructions require special treatment. However, once
2290 // SelectSelect is implemented, "isel" requires similar handling.
2292 // Also be conservative about the output register class. Avoid
2293 // assigning R0 or X0 to the output register for GPRC and G8RC
2294 // register classes, as any such result could be used in ADDI, etc.,
2295 // where those regs have another meaning.
2296 unsigned PPCFastISel::fastEmitInst_ri(unsigned MachineInstOpcode,
2297 const TargetRegisterClass *RC,
2298 unsigned Op0, bool Op0IsKill,
2300 if (MachineInstOpcode == PPC::ADDI)
2301 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass);
2302 else if (MachineInstOpcode == PPC::ADDI8)
2303 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass);
2305 const TargetRegisterClass *UseRC =
2306 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2307 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2309 return FastISel::fastEmitInst_ri(MachineInstOpcode, UseRC,
2310 Op0, Op0IsKill, Imm);
2313 // Override for instructions with one register operand to avoid use of
2314 // R0/X0. The automatic infrastructure isn't aware of the context so
2315 // we must be conservative.
2316 unsigned PPCFastISel::fastEmitInst_r(unsigned MachineInstOpcode,
2317 const TargetRegisterClass* RC,
2318 unsigned Op0, bool Op0IsKill) {
2319 const TargetRegisterClass *UseRC =
2320 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2321 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2323 return FastISel::fastEmitInst_r(MachineInstOpcode, UseRC, Op0, Op0IsKill);
2326 // Override for instructions with two register operands to avoid use
2327 // of R0/X0. The automatic infrastructure isn't aware of the context
2328 // so we must be conservative.
2329 unsigned PPCFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
2330 const TargetRegisterClass* RC,
2331 unsigned Op0, bool Op0IsKill,
2332 unsigned Op1, bool Op1IsKill) {
2333 const TargetRegisterClass *UseRC =
2334 (RC == &PPC::GPRCRegClass ? &PPC::GPRC_and_GPRC_NOR0RegClass :
2335 (RC == &PPC::G8RCRegClass ? &PPC::G8RC_and_G8RC_NOX0RegClass : RC));
2337 return FastISel::fastEmitInst_rr(MachineInstOpcode, UseRC, Op0, Op0IsKill,
2342 // Create the fast instruction selector for PowerPC64 ELF.
2343 FastISel *PPC::createFastISel(FunctionLoweringInfo &FuncInfo,
2344 const TargetLibraryInfo *LibInfo) {
2345 // Only available on 64-bit ELF for now.
2346 const PPCSubtarget &Subtarget = FuncInfo.MF->getSubtarget<PPCSubtarget>();
2347 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI())
2348 return new PPCFastISel(FuncInfo, LibInfo);