1 //===-- PPCCodeEmitter.cpp - JIT Code Emitter for PowerPC -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the PowerPC 32-bit CodeEmitter and associated machinery to
11 // JIT-compile bitcode to native PowerPC.
13 //===----------------------------------------------------------------------===//
16 #include "PPCRelocations.h"
17 #include "PPCTargetMachine.h"
18 #include "llvm/CodeGen/JITCodeEmitter.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/PassManager.h"
24 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/raw_ostream.h"
26 #include "llvm/Target/TargetOptions.h"
30 class PPCCodeEmitter : public MachineFunctionPass {
33 MachineModuleInfo *MMI;
35 void getAnalysisUsage(AnalysisUsage &AU) const override {
36 AU.addRequired<MachineModuleInfo>();
37 MachineFunctionPass::getAnalysisUsage(AU);
42 /// MovePCtoLROffset - When/if we see a MovePCtoLR instruction, we record
43 /// its address in the function into this pointer.
44 void *MovePCtoLROffset;
47 PPCCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
48 : MachineFunctionPass(ID), TM(tm), MCE(mce) {}
50 /// getBinaryCodeForInstr - This function, generated by the
51 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
52 /// machine instructions.
53 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
56 MachineRelocation GetRelocation(const MachineOperand &MO,
57 unsigned RelocID) const;
59 /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
60 unsigned getMachineOpValue(const MachineInstr &MI,
61 const MachineOperand &MO) const;
63 unsigned get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const;
64 unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
65 unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
66 unsigned getAbsDirectBrEncoding(const MachineInstr &MI,
68 unsigned getAbsCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
70 unsigned getImm16Encoding(const MachineInstr &MI, unsigned OpNo) const;
71 unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const;
72 unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const;
73 unsigned getSPE8DisEncoding(const MachineInstr &MI, unsigned OpNo) const;
74 unsigned getSPE4DisEncoding(const MachineInstr &MI, unsigned OpNo) const;
75 unsigned getSPE2DisEncoding(const MachineInstr &MI, unsigned OpNo) const;
76 unsigned getTLSRegEncoding(const MachineInstr &MI, unsigned OpNo) const;
77 unsigned getTLSCallEncoding(const MachineInstr &MI, unsigned OpNo) const;
79 const char *getPassName() const override {
80 return "PowerPC Machine Code Emitter";
83 /// runOnMachineFunction - emits the given MachineFunction to memory
85 bool runOnMachineFunction(MachineFunction &MF) override;
87 /// emitBasicBlock - emits the given MachineBasicBlock to memory
89 void emitBasicBlock(MachineBasicBlock &MBB);
93 char PPCCodeEmitter::ID = 0;
95 /// createPPCCodeEmitterPass - Return a pass that emits the collected PPC code
96 /// to the specified MCE object.
97 FunctionPass *llvm::createPPCJITCodeEmitterPass(PPCTargetMachine &TM,
98 JITCodeEmitter &JCE) {
99 return new PPCCodeEmitter(TM, JCE);
102 bool PPCCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
103 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
104 MF.getTarget().getRelocationModel() != Reloc::Static) &&
105 "JIT relocation model must be set to static or default!");
107 MMI = &getAnalysis<MachineModuleInfo>();
108 MCE.setModuleInfo(MMI);
110 MovePCtoLROffset = nullptr;
111 MCE.startFunction(MF);
112 for (MachineFunction::iterator BB = MF.begin(), E = MF.end(); BB != E; ++BB)
114 } while (MCE.finishFunction(MF));
119 void PPCCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
120 MCE.StartMachineBasicBlock(&MBB);
122 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I){
123 const MachineInstr &MI = *I;
124 MCE.processDebugLoc(MI.getDebugLoc(), true);
125 switch (MI.getOpcode()) {
127 MCE.emitWordBE(getBinaryCodeForInstr(MI));
129 case TargetOpcode::CFI_INSTRUCTION:
131 case TargetOpcode::EH_LABEL:
132 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
134 case TargetOpcode::IMPLICIT_DEF:
135 case TargetOpcode::KILL:
136 break; // pseudo opcode, no side effects
137 case PPC::MovePCtoLR:
138 case PPC::MovePCtoLR8:
139 assert(TM.getRelocationModel() == Reloc::PIC_);
140 MovePCtoLROffset = (void*)MCE.getCurrentPCValue();
141 MCE.emitWordBE(0x48000005); // bl 1
144 MCE.processDebugLoc(MI.getDebugLoc(), false);
148 unsigned PPCCodeEmitter::get_crbitm_encoding(const MachineInstr &MI,
149 unsigned OpNo) const {
150 const MachineOperand &MO = MI.getOperand(OpNo);
151 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
152 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
153 (MO.getReg() >= PPC::CR0 && MO.getReg() <= PPC::CR7));
154 return 0x80 >> TM.getSubtargetImpl()->getRegisterInfo()->getEncodingValue(
158 MachineRelocation PPCCodeEmitter::GetRelocation(const MachineOperand &MO,
159 unsigned RelocID) const {
160 // If in PIC mode, we need to encode the negated address of the
161 // 'movepctolr' into the unrelocated field. After relocation, we'll have
162 // &gv-&movepctolr-4 in the imm field. Once &movepctolr is added to the imm
163 // field, we get &gv. This doesn't happen for branch relocations, which are
164 // always implicitly pc relative.
166 if (TM.getRelocationModel() == Reloc::PIC_) {
167 assert(MovePCtoLROffset && "MovePCtoLR not seen yet?");
168 Cst = -(intptr_t)MovePCtoLROffset - 4;
172 return MachineRelocation::getGV(MCE.getCurrentPCOffset(), RelocID,
173 const_cast<GlobalValue *>(MO.getGlobal()),
174 Cst, isa<Function>(MO.getGlobal()));
176 return MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
177 RelocID, MO.getSymbolName(), Cst);
179 return MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
180 RelocID, MO.getIndex(), Cst);
183 return MachineRelocation::getBB(MCE.getCurrentPCOffset(),
184 RelocID, MO.getMBB());
187 return MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
188 RelocID, MO.getIndex(), Cst);
191 unsigned PPCCodeEmitter::getDirectBrEncoding(const MachineInstr &MI,
192 unsigned OpNo) const {
193 const MachineOperand &MO = MI.getOperand(OpNo);
194 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
196 MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bx));
200 unsigned PPCCodeEmitter::getCondBrEncoding(const MachineInstr &MI,
201 unsigned OpNo) const {
202 const MachineOperand &MO = MI.getOperand(OpNo);
203 MCE.addRelocation(GetRelocation(MO, PPC::reloc_pcrel_bcx));
207 unsigned PPCCodeEmitter::getAbsDirectBrEncoding(const MachineInstr &MI,
208 unsigned OpNo) const {
209 const MachineOperand &MO = MI.getOperand(OpNo);
210 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
212 llvm_unreachable("Absolute branch relocations unsupported on the old JIT.");
215 unsigned PPCCodeEmitter::getAbsCondBrEncoding(const MachineInstr &MI,
216 unsigned OpNo) const {
217 llvm_unreachable("Absolute branch relocations unsupported on the old JIT.");
220 unsigned PPCCodeEmitter::getImm16Encoding(const MachineInstr &MI,
221 unsigned OpNo) const {
222 const MachineOperand &MO = MI.getOperand(OpNo);
223 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO);
226 switch (MO.getTargetFlags() & PPCII::MO_ACCESS_MASK) {
227 default: llvm_unreachable("Unsupported target operand flags!");
228 case PPCII::MO_LO: RelocID = PPC::reloc_absolute_low; break;
229 case PPCII::MO_HA: RelocID = PPC::reloc_absolute_high; break;
232 MCE.addRelocation(GetRelocation(MO, RelocID));
236 unsigned PPCCodeEmitter::getMemRIEncoding(const MachineInstr &MI,
237 unsigned OpNo) const {
238 // Encode (imm, reg) as a memri, which has the low 16-bits as the
239 // displacement and the next 5 bits as the register #.
240 assert(MI.getOperand(OpNo+1).isReg());
241 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 16;
243 const MachineOperand &MO = MI.getOperand(OpNo);
245 return (getMachineOpValue(MI, MO) & 0xFFFF) | RegBits;
247 // Add a fixup for the displacement field.
248 MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low));
252 unsigned PPCCodeEmitter::getMemRIXEncoding(const MachineInstr &MI,
253 unsigned OpNo) const {
254 // Encode (imm, reg) as a memrix, which has the low 14-bits as the
255 // displacement and the next 5 bits as the register #.
256 assert(MI.getOperand(OpNo+1).isReg());
257 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 14;
259 const MachineOperand &MO = MI.getOperand(OpNo);
261 return ((getMachineOpValue(MI, MO) >> 2) & 0x3FFF) | RegBits;
263 MCE.addRelocation(GetRelocation(MO, PPC::reloc_absolute_low_ix));
267 unsigned PPCCodeEmitter::getSPE8DisEncoding(const MachineInstr &MI, unsigned OpNo) const {
268 // Encode (imm, reg) as a spe8dis, which has the low 5-bits of (imm / 8)
269 // as the displacement and the next 5 bits as the register #.
270 assert(MI.getOperand(OpNo+1).isReg());
271 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 5;
273 const MachineOperand &MO = MI.getOperand(OpNo);
275 uint32_t Imm = getMachineOpValue(MI, MO) >> 3;
276 return reverseBits(Imm | RegBits) >> 22;
280 unsigned PPCCodeEmitter::getSPE4DisEncoding(const MachineInstr &MI, unsigned OpNo) const {
281 // Encode (imm, reg) as a spe4dis, which has the low 5-bits of (imm / 4)
282 // as the displacement and the next 5 bits as the register #.
283 assert(MI.getOperand(OpNo+1).isReg());
284 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 5;
286 const MachineOperand &MO = MI.getOperand(OpNo);
288 uint32_t Imm = getMachineOpValue(MI, MO) >> 2;
289 return reverseBits(Imm | RegBits) >> 22;
293 unsigned PPCCodeEmitter::getSPE2DisEncoding(const MachineInstr &MI, unsigned OpNo) const {
294 // Encode (imm, reg) as a spe2dis, which has the low 5-bits of (imm / 2)
295 // as the displacement and the next 5 bits as the register #.
296 assert(MI.getOperand(OpNo+1).isReg());
297 uint32_t RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 5;
299 const MachineOperand &MO = MI.getOperand(OpNo);
301 uint32_t Imm = getMachineOpValue(MI, MO) >> 1;
302 return reverseBits(Imm | RegBits) >> 22;
305 unsigned PPCCodeEmitter::getTLSRegEncoding(const MachineInstr &MI,
306 unsigned OpNo) const {
307 llvm_unreachable("TLS not supported on the old JIT.");
311 unsigned PPCCodeEmitter::getTLSCallEncoding(const MachineInstr &MI,
312 unsigned OpNo) const {
313 llvm_unreachable("TLS not supported on the old JIT.");
317 unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI,
318 const MachineOperand &MO) const {
321 // MTOCRF/MFOCRF should go through get_crbitm_encoding for the CR operand.
322 // The GPR operand should come through here though.
323 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
324 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
325 MO.getReg() < PPC::CR0 || MO.getReg() > PPC::CR7);
326 return TM.getSubtargetImpl()->getRegisterInfo()->getEncodingValue(
331 "Relocation required in an instruction that we cannot encode!");
335 #include "PPCGenCodeEmitter.inc"