lib/Target/PowerPC/PPC.td

   1 //===- PPC.td - Describe the PowerPC Target Machine --------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by the LLVM research group and is distributed under
   6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This is the top level entry point for the PowerPC target.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 // Get the target-independent interfaces which we are implementing.
  15 //
  16 include "../Target.td"
  17
  18 //===----------------------------------------------------------------------===//
  19 // Register File Description
  20 //===----------------------------------------------------------------------===//
  21
  22 include "PPCRegisterInfo.td"
  23 include "PPCSchedule.td"
  24 include "PPCInstrInfo.td"
  25
  26
  27
  28 //===----------------------------------------------------------------------===//
  29 // PowerPC Subtarget features (sorted by name).
  30 //
  31
  32 def Feature64Bit     : SubtargetFeature<"64bit",
  33                                 "Should 64 bit instructions be used">;
  34 def Feature64BitRegs : SubtargetFeature<"64bitregs",
  35                                 "Should 64 bit registers be used">;
  36 def FeatureAltivec   : SubtargetFeature<"altivec",
  37                                 "Should Altivec instructions be used">;
  38 def FeatureFSqrt     : SubtargetFeature<"fsqrt",
  39                                 "Should the fsqrt instruction be used">;
  40 def FeatureGPUL      : SubtargetFeature<"gpul",
  41                                 "Should GPUL instructions be used">;
  42
  43 //===----------------------------------------------------------------------===//
  44 // PowerPC chips sets supported (sorted by name)
  45 //
  46
  47 def : Processor<"601", G3Itineraries, []>;
  48 def : Processor<"602", G3Itineraries, []>;
  49 def : Processor<"603", G3Itineraries, []>;
  50 def : Processor<"603e", G3Itineraries, []>;
  51 def : Processor<"603ev", G3Itineraries, []>;
  52 def : Processor<"604", G3Itineraries, []>;
  53 def : Processor<"604e", G3Itineraries, []>;
  54 def : Processor<"620", G3Itineraries, []>;
  55 def : Processor<"7400", G4Itineraries, [FeatureAltivec]>;
  56 def : Processor<"7450", G4PlusItineraries, [FeatureAltivec]>;
  57 def : Processor<"750", G3Itineraries, []>;
  58 def : Processor<"970", G5Itineraries,
  59                   [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
  60                    Feature64Bit /*, Feature64BitRegs*/]>;
  61 def : Processor<"g4", G4Itineraries, [FeatureAltivec]>;
  62 def : Processor<"g4+", G4PlusItineraries, [FeatureAltivec]>;
  63 def : Processor<"g5", G5Itineraries,
  64                   [FeatureAltivec, FeatureGPUL, FeatureFSqrt,
  65                    Feature64Bit /*, Feature64BitRegs*/]>;
  66 def : Processor<"generic", G3Itineraries, []>;
  67
  68
  69 def PPC : Target {
  70   // Pointers on PPC are 32-bits in size.
  71   let PointerType = i32;
  72
  73   // According to the Mach-O Runtime ABI, these regs are nonvolatile across
  74   // calls
  75   let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
  76     R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
  77     F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
  78     F30, F31, CR2, CR3, CR4, LR];
  79
  80   // Pull in Instruction Info:
  81   let InstructionSet = PowerPCInstrInfo;
  82 }